diff options
4 files changed, 156 insertions, 59 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C index 40912011..54aa9ec2 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_scominit.C @@ -95,37 +95,66 @@ p9_hcd_cache_scominit( } } - for (auto l_iter = l_ex_targets.begin(); l_iter != l_ex_targets.end(); l_iter++) - { - fapi2::Target<fapi2::TARGET_TYPE_EX> l_ex = *l_iter; - auto l_core_targets = l_ex.getChildren<fapi2::TARGET_TYPE_CORE>(); - - FAPI_ASSERT((l_core_targets.size() != 0), - fapi2::PMPROC_CACHESCOMINIT_NOGOODCOREINEX().set_QCSR(l_qcsr), - "NO Good Children Cores under this So-Called Good EX!"); - - auto l_core = l_core_targets.begin(); - fapi2::Target<fapi2::TARGET_TYPE_CORE> l_ec = *l_core; - fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = - l_ec.getParent<fapi2::TARGET_TYPE_PERV>(); - - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, - l_attr_chip_unit_pos)); - l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_CORE_POS_OFFSET; - l_exid = (l_attr_chip_unit_pos >> 1); + // EX0 or only one configured EX target given: l_exloop = 0; + // possible EX1 when two EX targets are given: l_exloop = 1; + // (If you had to ask why not put l_exloop = 0 in the for loop syntax, + // well, the syntax "auto" doesnt allows it.) + l_exloop = 0; - if (!(l_exlist & (0x8000 >> l_exid))) + for (auto l_iter = l_ex_targets.begin(); l_iter != l_ex_targets.end(); l_iter++, l_exloop++) + { + // Hostboot mode(not force_all_cores) is the default IPL mode + // That is, one mater core is bought up through istep4 by SBE + // and then being powered off along with its cache in istep15 + // via stop11 function provided by SGPE. + // + // 1)The defined target pattern being processed by stop11 is + // Core[X] + // L2 of the EX where Core[X] is on + // L3 of EX0 if configured, L3 of EX1 if configured + // Quad where Core[X] is on + // (by defination, the EX with core has to be configured) + // + // Therefore, hostboot through istep4 has to bring up the + // same elements above that will be shutdown by istep15. + // + // 2)In another word, the targets for istep4 needs to be + // Core[X] + // Both EXs if both configured + // Require following special handling in istep4: + // a) skip the L2 that Core[X] isnt on, but + // b) bring up L3 that Core[X] isnt on(or both L3) + // If only one EX is configured, then it has to be the EX + // that Core[X] is on, bring up both L2+L3 on that EX + // Quad where Core[X] is on + // + // 3)Master core is defined to be chip's 1st configured core + // Now select_ex in istep3 will provide such targets above + // a) Master core is in the first EX of a quad, + // AND second EX is also configured. + // Set master core in CCSR, set both EXes in QCSR + // (This is the case requires istep4 special handling) + // b) Master core is in the first EX of a quad, + // AND second EX is deconfigured + // Set master core in CCSR, set master EX in QCSR + // c) Master core is in the second EX, by defination, + // the first EX must have been deconfigured + // Set master core in CCSR, set master EX in QCSR + // Note: There wont be any problems on targets or require + // special handling in procedure for case b) and c) above + // + // Now we only skip L2 if we are in HB mode(not force_all_cores) + // AND we are give second configured EX to process(l_exloop==1) + if (l_attr_sys_force_all_cores || (!l_exloop)) { - continue; - } + FAPI_EXEC_HWP(l_rc, p9_l2_scom, *l_iter, l_sys); - FAPI_EXEC_HWP(l_rc, p9_l2_scom, *l_iter, l_sys); - - if (l_rc) - { - FAPI_ERR("Error from p9_l2_scom (p9.l2.scom.initfile)"); - fapi2::current_err = l_rc; - goto fapi_try_exit; + if (l_rc) + { + FAPI_ERR("Error from p9_l2_scom (p9.l2.scom.initfile)"); + fapi2::current_err = l_rc; + goto fapi_try_exit; + } } FAPI_EXEC_HWP(l_rc, p9_l3_scom, *l_iter, l_sys); @@ -148,29 +177,51 @@ p9_hcd_cache_scominit( if (l_attr_sys_force_all_cores) { - FAPI_DBG("Setup L3-LCO on TARGET_ID[%d] via EX_L3_MODE_REG1[0,2-5,6-21]", l_exid); - FAPI_TRY(getScom(*l_iter, EX_L3_MODE_REG1, l_data64)); - l_data64.insertFromRight<2, 4>(l_exid).insertFromRight<6, 16>(l_exlist); + fapi2::Target<fapi2::TARGET_TYPE_EX> l_ex = *l_iter; + auto l_core_targets = l_ex.getChildren<fapi2::TARGET_TYPE_CORE>(); - if (l_excount > 1) - { - l_data64.setBit<0>(); - } + FAPI_ASSERT((l_core_targets.size() != 0), + fapi2::PMPROC_CACHESCOMINIT_NOGOODCOREINEX().set_QCSR(l_qcsr), + "NO Good Children Cores under this So-Called Good EX!"); - FAPI_TRY(putScom(*l_iter, EX_L3_MODE_REG1, l_data64)); + auto l_core = l_core_targets.begin(); + fapi2::Target<fapi2::TARGET_TYPE_CORE> l_ec = *l_core; + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = + l_ec.getParent<fapi2::TARGET_TYPE_PERV>(); - FAPI_TRY(getScom(*l_iter, EX_L3_MODE_REG0, l_data64)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, + l_attr_chip_unit_pos)); + l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_CORE_POS_OFFSET; + l_exid = (l_attr_chip_unit_pos >> 1); - if (l_excount == 2) - { - FAPI_DBG("Assert L3_DYN_LCO_BLK_DIS_CFG on TARGET_ID[%d] via EX_L3_MODE_REG0[9]", l_exid); - FAPI_TRY(putScom(*l_iter, EX_L3_MODE_REG0, DATA_SET(9))); - } - else - { - FAPI_DBG("Drop L3_DYN_LCO_BLK_DIS_CFG on TARGET_ID[%d] via EX_L3_MODE_REG0[9]", l_exid); - FAPI_TRY(putScom(*l_iter, EX_L3_MODE_REG0, DATA_UNSET(9))); - } + } + else + { + l_exid = l_exloop; + } + + FAPI_DBG("Setup L3-LCO on TARGET_ID[%d] via EX_L3_MODE_REG1[0,2-5,6-21]", l_exid); + FAPI_TRY(getScom(*l_iter, EX_L3_MODE_REG1, l_data64)); + l_data64.insertFromRight<2, 4>(l_exid).insertFromRight<6, 16>(l_exlist); + + if (l_excount > 1) + { + l_data64.setBit<0>(); + } + + FAPI_TRY(putScom(*l_iter, EX_L3_MODE_REG1, l_data64)); + + FAPI_TRY(getScom(*l_iter, EX_L3_MODE_REG0, l_data64)); + + if (l_excount == 2) + { + FAPI_DBG("Assert L3_DYN_LCO_BLK_DIS_CFG on TARGET_ID[%d] via EX_L3_MODE_REG0[9]", l_exid); + FAPI_TRY(putScom(*l_iter, EX_L3_MODE_REG0, DATA_SET(9))); + } + else + { + FAPI_DBG("Drop L3_DYN_LCO_BLK_DIS_CFG on TARGET_ID[%d] via EX_L3_MODE_REG0[9]", l_exid); + FAPI_TRY(putScom(*l_iter, EX_L3_MODE_REG0, DATA_UNSET(9))); } } diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C index c5b07b37..414b4922 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C @@ -99,6 +99,7 @@ p9_hcd_cache_startclocks( uint8_t l_attr_chip_id = 0; uint8_t l_attr_chip_unit_pos = 0; uint8_t l_attr_system_ipl_phase; + uint8_t l_attr_sys_force_all_cores; uint8_t l_attr_dd1_skip_flushmode_inhibit_drop; fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_chip = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); @@ -108,6 +109,8 @@ p9_hcd_cache_startclocks( FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_IPL_PHASE, l_sys, l_attr_system_ipl_phase)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, l_sys, + l_attr_sys_force_all_cores)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW388878, l_chip, l_attr_dd1_skip_flushmode_inhibit_drop)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, l_chip, @@ -163,10 +166,22 @@ p9_hcd_cache_startclocks( if (l_qcsr & BIT64((l_attr_chip_unit_pos << 1) + 1)) { - l_qssr |= (BIT64((l_attr_chip_unit_pos << 1) + 1) | - BIT64(l_attr_chip_unit_pos + 14)); - l_region_clock |= p9hcd::CLK_REGION_EX1_L2_L3_REFR; - l_l2sync_clock |= BIT64(37); + // Now we only skip L2 if we are in HB mode(not force_all_cores) + // AND we are give second configured EX to process + // (l_l2sync_clock is already initialized by EX0) + // Note: more details see comments in p9_hcd_cache_scominit.C + if (!l_attr_sys_force_all_cores && l_l2sync_clock) + { + l_region_clock |= p9hcd::CLK_REGION_EX1_L3_REFR; + } + else + { + l_qssr |= (BIT64((l_attr_chip_unit_pos << 1) + 1) | + BIT64(l_attr_chip_unit_pos + 14)); + l_region_clock |= p9hcd::CLK_REGION_EX1_L2_L3_REFR; + l_l2sync_clock |= BIT64(37); + } + FAPI_DBG("Sequence EX1 EDRAM enables via QPPM_QCCR[4-7]"); FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WOR, MASK_SET(4))); FAPI_TRY(fapi2::delay(12000, 200)); diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H index 19e087f1..76d41a3d 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -182,6 +182,8 @@ enum P9_HCD_CLK_CTRL_CONSTANTS CLK_REGION_EX1_L2 = BIT64(9), CLK_REGION_EX0_REFR = BIT64(12), CLK_REGION_EX1_REFR = BIT64(13), + CLK_REGION_EX0_L3_REFR = BIT64(6) | BIT64(12), + CLK_REGION_EX1_L3_REFR = BIT64(7) | BIT64(13), CLK_REGION_EX0_L2_L3_REFR = BIT64(6) | BIT64(8) | BIT64(12), CLK_REGION_EX1_L2_L3_REFR = BIT64(7) | BIT64(9) | BIT64(13), CLK_REGION_ALL_BUT_L3_REFR = BITS64(4, 2) | BITS64(8, 4) | BIT64(14), diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C index 04cd0822..c2cd7f68 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C @@ -223,6 +223,39 @@ fapi2::ReturnCode p9_sbe_select_ex( uint32_t l_ex_num = l_core_num / 2; uint32_t l_eq_num = l_core_num / 4; + // if b_host_core_found (only set in single mode), break out of core loop + if (b_host_core_found) + { + // since the very first functional core in chip will be named master core + // and if the master core is in second ex of a quad, then the first ex + // must be partial bad as there is no functional core found before master core; + + // therefore, only need to check the second ex to be partial good if master core + // is in the first ex. if so, add second ex to QCSR so that istep4 can process + // hostboot core bring up as a stop11 pattern of l2/l3 in both EXes + + // after found master core but next core still remain in the same ex, + // continue to the next core in the loop + if (l_ex_num == l_master_ex_num) + { + continue; + } + // moved to next ex now, but could be already into next quad + // either next ex is in the same quad or next quad, break the loop + else + { + // if still in the same eq, then this is the sibling ex, note it down + if (l_eq_num == l_master_eq_num) + { + l_quad_config.setBit(l_ex_num); + FAPI_DBG("Sibling EX found, l_ex_num = 0x%02X, QCSR 0x%016llX", + l_ex_num, l_quad_config); + } + + break; + } + } + if (b_single) { if (!b_host_core_found) @@ -281,12 +314,6 @@ fapi2::ReturnCode p9_sbe_select_ex( l_data64), "Error: Core PFET Delay register"); - // if b_host_core_found (only set in single mode), break out of core loop - if (b_host_core_found) - { - break; - } - } // Core loop // Process the good EQs @@ -317,7 +344,9 @@ fapi2::ReturnCode p9_sbe_select_ex( i, l_master_ex_num, i, l_quad_config.getBit(i)); // Add to MC group - if ((i == l_master_ex_num) && l_quad_config.getBit(i)) + // under single mode, + // l_quad_config should only have master ex and possible sibling ex + if (l_quad_config.getBit(i)) { FAPI_TRY(select_ex_add_ex_to_mc_groups(eq, i)); } |