diff options
| -rw-r--r-- | import/chips/p9/common/include/p9_misc_scom_addresses.H | 3222 | ||||
| -rw-r--r-- | import/chips/p9/common/include/p9_misc_scom_addresses_fld.H | 45367 | ||||
| -rw-r--r-- | import/chips/p9/common/include/p9_perv_scom_addresses.H | 2200 | ||||
| -rw-r--r-- | import/chips/p9/common/include/p9_perv_scom_addresses_fld.H | 3397 | ||||
| -rw-r--r-- | import/chips/p9/common/include/p9_scom_template_consts.H | 33028 |
5 files changed, 55297 insertions, 31917 deletions
diff --git a/import/chips/p9/common/include/p9_misc_scom_addresses.H b/import/chips/p9/common/include/p9_misc_scom_addresses.H index 335db2c4..ed5882f4 100644 --- a/import/chips/p9/common/include/p9_misc_scom_addresses.H +++ b/import/chips/p9/common/include/p9_misc_scom_addresses.H @@ -254,6 +254,72 @@ REG64( PU_ADDR_8_HASH_FUNCTION_REG , RULL(0x02011149 REG64( PU_ADDR_9_HASH_FUNCTION_REG , RULL(0x0201114A), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PEC_ADDR_TRAP_REG , RULL(0x0D010003), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_ADDR_TRAP_REG , RULL(0x02010003), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_ADDR_TRAP_REG , RULL(0x03010003), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_ADDR_TRAP_REG , RULL(0x04010003), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_ADDR_TRAP_REG , RULL(0x05010003), SH_UNT_PU_N3 , SH_ACS_SCOM ); + +REG64( CAPP_APCFG , RULL(0x02010819), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_APCFG , RULL(0x02010819), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_APCFG , RULL(0x04010819), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_APCLCO , RULL(0x02010821), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_APCLCO , RULL(0x02010821), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_APCLCO , RULL(0x04010821), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_APCRDFSMMASK , RULL(0x02010823), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_APCRDFSMMASK , RULL(0x02010823), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_APCRDFSMMASK , RULL(0x04010823), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_APCTL , RULL(0x02010818), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_APCTL , RULL(0x02010818), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_APCTL , RULL(0x04010818), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_APC_ARRY_ADDR , RULL(0x0201082A), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_APC_ARRY_ADDR , RULL(0x0201082A), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_APC_ARRY_ADDR , RULL(0x0401082A), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_APC_ARRY_RDDATA , RULL(0x0201082B), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_APC_ARRY_RDDATA , RULL(0x0201082B), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_APC_ARRY_RDDATA , RULL(0x0401082B), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_APC_ARRY_WRDATA , RULL(0x02010842), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_APC_ARRY_WRDATA , RULL(0x02010842), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_APC_ARRY_WRDATA , RULL(0x04010842), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_APC_PMUSEL , RULL(0x02010816), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_APC_PMUSEL , RULL(0x02010816), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_APC_PMUSEL , RULL(0x04010816), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_ASE_TUPLE0 , RULL(0x02010846), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_ASE_TUPLE0 , RULL(0x02010846), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_ASE_TUPLE0 , RULL(0x04010846), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_ASE_TUPLE1 , RULL(0x02010847), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_ASE_TUPLE1 , RULL(0x02010847), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_ASE_TUPLE1 , RULL(0x04010847), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_ASE_TUPLE2 , RULL(0x02010848), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_ASE_TUPLE2 , RULL(0x02010848), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_ASE_TUPLE2 , RULL(0x04010848), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_ASE_TUPLE3 , RULL(0x02010849), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_ASE_TUPLE3 , RULL(0x02010849), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_ASE_TUPLE3 , RULL(0x04010849), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( PEC_ASSIST_INTERRUPT_REG , RULL(0x0D0F0011), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_ATOMIC_LOCK_MASK_LATCH_REG , RULL(0x0D010007), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_ATOMIC_LOCK_MASK_LATCH_REG , RULL(0x02010007), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_ATOMIC_LOCK_MASK_LATCH_REG , RULL(0x03010007), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_ATOMIC_LOCK_MASK_LATCH_REG , RULL(0x04010007), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_ATOMIC_LOCK_MASK_LATCH_REG , RULL(0x05010007), SH_UNT_PU_N3 , SH_ACS_SCOM ); + +REG64( PEC_ATOMIC_LOCK_REG , RULL(0x0D0F03FF), SH_UNT_PEC , SH_ACS_SCOM ); + REG64( PU_NPU_SM0_ATS_CKSW , RULL(0x05011304), SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW ); @@ -266,6 +332,8 @@ REG64( PU_NPU_SM0_ATS_HOLD , RULL(0x05011305 REG64( PU_NPU_SM1_ATS_TCR , RULL(0x05011326), SH_UNT_PU_NPU_SM1, SH_ACS_SCOM ); +REG64( PEC_ATTN_INTERRUPT_REG , RULL(0x0D0F001A), SH_UNT_PEC , SH_ACS_SCOM ); + REG64( PU_BANK0_MCD_BOT , RULL(0x0301140C), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_MCD1_BANK0_MCD_BOT , RULL(0x0301100C), SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW ); @@ -290,37 +358,13 @@ REG64( PU_MCD1_BANK0_MCD_TOP , RULL(0x0301100A REG64( PU_BANK0_MCD_VGC , RULL(0x03011411), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_MCD1_BANK0_MCD_VGC , RULL(0x03011011), SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK0_BARE_REG , RULL(0x04010C55), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK1_BARE_REG , RULL(0x04010C95), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK2_BARE_REG , RULL(0x04010CD5), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK0_BARE_REG , RULL(0x04011055), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK1_BARE_REG , RULL(0x04011095), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK2_BARE_REG , RULL(0x040110D5), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK0_BARE_REG , RULL(0x04011455), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK1_BARE_REG , RULL(0x04011495), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK2_BARE_REG , RULL(0x040114D5), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK0_BARE_REG , RULL(0x04010C55), SH_UNT_PEC_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK1_BARE_REG , RULL(0x04010C95), SH_UNT_PEC_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK2_BARE_REG , RULL(0x04010CD5), SH_UNT_PEC_STACK2, - SH_ACS_SCOM_RW ); -REG64( PHB_BARE_REG , RULL(0x04010C55), SH_UNT_PHB , SH_ACS_SCOM_RW ); -REG64( PHB_0_BARE_REG , RULL(0x04010C55), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); -REG64( PHB_1_BARE_REG , RULL(0x04011055), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); -REG64( PHB_2_BARE_REG , RULL(0x04011095), SH_UNT_PHB_2 , SH_ACS_SCOM_RW ); -REG64( PHB_3_BARE_REG , RULL(0x04011455), SH_UNT_PHB_3 , SH_ACS_SCOM_RW ); -REG64( PHB_4_BARE_REG , RULL(0x04011495), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); -REG64( PHB_5_BARE_REG , RULL(0x040114D5), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); +REG64( PHB_BARE_REG , RULL(0x04010C54), SH_UNT_PHB , SH_ACS_SCOM_RW ); +REG64( PHB_0_BARE_REG , RULL(0x04010C54), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); +REG64( PHB_1_BARE_REG , RULL(0x04011054), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); +REG64( PHB_2_BARE_REG , RULL(0x04011094), SH_UNT_PHB_2 , SH_ACS_SCOM_RW ); +REG64( PHB_3_BARE_REG , RULL(0x04011454), SH_UNT_PHB_3 , SH_ACS_SCOM_RW ); +REG64( PHB_4_BARE_REG , RULL(0x04011494), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); +REG64( PHB_5_BARE_REG , RULL(0x040114D4), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); REG64( PU_BCDE_CTL_OCI , RULL(0xC0040080), SH_UNT , SH_ACS_OCI ); REG64( PU_BCDE_CTL_SCOM , RULL(0x05016850), SH_UNT , SH_ACS_SCOM ); @@ -426,21 +470,19 @@ REG64( PU_NPU_DAT_BDF2PE_51_CONFIG , RULL(0x050113B0 REG64( PU_NPU_DAT_BDF2PE_52_CONFIG , RULL(0x050113B1), SH_UNT_PU_NPU_DAT, SH_ACS_SCOM ); -REG64( PU_CC_ATOMIC_LOCK_REG_B , RULL(0x000A03FF), SH_UNT , SH_ACS_SCOM ); - -REG64( PU_CC_ATOMIC_LOCK_REG_C , RULL(0x000A13FF), SH_UNT , SH_ACS_SCOM ); - -REG64( PU_CC_ATOMIC_LOCK_REG_D , RULL(0x000A23FF), SH_UNT , SH_ACS_SCOM ); +REG64( PEC_BIST , RULL(0x0D03000B), SH_UNT_PEC , SH_ACS_SCOM ); -REG64( PU_CC_ATOMIC_LOCK_REG_E , RULL(0x000A33FF), SH_UNT , SH_ACS_SCOM ); +REG64( CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL , RULL(0x0201082C), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL , RULL(0x0201082C), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL , RULL(0x0401082C), SH_UNT_CAPP_1 , SH_ACS_SCOM ); -REG64( PU_CC_PROTECT_MODE_REG_B , RULL(0x000A03FE), SH_UNT , SH_ACS_SCOM ); +REG64( CAPP_CAPP_ERR_STATUS_CONTROL , RULL(0x0201080E), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CAPP_ERR_STATUS_CONTROL , RULL(0x0201080E), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CAPP_ERR_STATUS_CONTROL , RULL(0x0401080E), SH_UNT_CAPP_1 , SH_ACS_SCOM ); -REG64( PU_CC_PROTECT_MODE_REG_C , RULL(0x000A13FE), SH_UNT , SH_ACS_SCOM ); +REG64( PEC_CC_ATOMIC_LOCK_REG , RULL(0x0D0303FF), SH_UNT_PEC , SH_ACS_SCOM ); -REG64( PU_CC_PROTECT_MODE_REG_D , RULL(0x000A23FE), SH_UNT , SH_ACS_SCOM ); - -REG64( PU_CC_PROTECT_MODE_REG_E , RULL(0x000A33FE), SH_UNT , SH_ACS_SCOM ); +REG64( PEC_CC_PROTECT_MODE_REG , RULL(0x0D0303FE), SH_UNT_PEC , SH_ACS_SCOM ); REG64( PU_NPU0_CERR_ECC_FIRST , RULL(0x050110A6), SH_UNT_PU_NPU0 , SH_ACS_SCOM ); REG64( PU_NPU1_CERR_ECC_FIRST , RULL(0x050111A6), SH_UNT_PU_NPU1 , SH_ACS_SCOM ); @@ -460,29 +502,29 @@ REG64( PU_NPU1_CTL_CERR_FIRST0 , RULL(0x0501119A SH_ACS_SCOM ); REG64( PU_NPU2_CTL_CERR_FIRST0 , RULL(0x0501129A), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_CERR_FIRST0 , RULL(0x0501101A), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM0_CERR_FIRST0 , RULL(0x05011017), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_CERR_FIRST0 , RULL(0x0501103A), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_CERR_FIRST0 , RULL(0x05011037), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_CERR_FIRST0 , RULL(0x0501105A), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_CERR_FIRST0 , RULL(0x05011057), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_CERR_FIRST0 , RULL(0x0501107A), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_CERR_FIRST0 , RULL(0x05011077), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_CERR_FIRST0 , RULL(0x0501111A), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_CERR_FIRST0 , RULL(0x05011117), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_CERR_FIRST0 , RULL(0x0501113A), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_CERR_FIRST0 , RULL(0x05011137), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_CERR_FIRST0 , RULL(0x0501115A), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_CERR_FIRST0 , RULL(0x05011157), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_CERR_FIRST0 , RULL(0x0501117A), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_CERR_FIRST0 , RULL(0x05011177), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_CERR_FIRST0 , RULL(0x0501121A), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_CERR_FIRST0 , RULL(0x05011217), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_CERR_FIRST0 , RULL(0x0501123A), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_CERR_FIRST0 , RULL(0x05011237), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_CERR_FIRST0 , RULL(0x0501125A), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_CERR_FIRST0 , RULL(0x05011257), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_CERR_FIRST0 , RULL(0x0501127A), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_CERR_FIRST0 , RULL(0x05011277), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); REG64( NV_CERR_FIRST1 , RULL(0x050110C6), SH_UNT_NV , SH_ACS_SCOM ); @@ -496,33 +538,33 @@ REG64( PU_NPU1_CTL_CERR_FIRST1 , RULL(0x0501119B SH_ACS_SCOM ); REG64( PU_NPU2_CTL_CERR_FIRST1 , RULL(0x0501129B), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_CERR_FIRST1 , RULL(0x0501101B), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM0_CERR_FIRST1 , RULL(0x05011018), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_CERR_FIRST1 , RULL(0x0501103B), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_CERR_FIRST1 , RULL(0x05011038), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_CERR_FIRST1 , RULL(0x0501105B), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_CERR_FIRST1 , RULL(0x05011058), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_CERR_FIRST1 , RULL(0x0501107B), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_CERR_FIRST1 , RULL(0x05011078), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_CERR_FIRST1 , RULL(0x0501111B), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_CERR_FIRST1 , RULL(0x05011118), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_CERR_FIRST1 , RULL(0x0501113B), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_CERR_FIRST1 , RULL(0x05011138), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_CERR_FIRST1 , RULL(0x0501115B), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_CERR_FIRST1 , RULL(0x05011158), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_CERR_FIRST1 , RULL(0x0501117B), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_CERR_FIRST1 , RULL(0x05011178), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); REG64( PU_NPU2_NTL0_CERR_FIRST1 , RULL(0x050112C6), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM ); REG64( PU_NPU2_NTL1_CERR_FIRST1 , RULL(0x050112E6), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_CERR_FIRST1 , RULL(0x0501121B), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_CERR_FIRST1 , RULL(0x05011218), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_CERR_FIRST1 , RULL(0x0501123B), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_CERR_FIRST1 , RULL(0x05011238), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_CERR_FIRST1 , RULL(0x0501125B), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_CERR_FIRST1 , RULL(0x05011258), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_CERR_FIRST1 , RULL(0x0501127B), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_CERR_FIRST1 , RULL(0x05011278), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); REG64( NV_CERR_FIRST2 , RULL(0x050110C9), SH_UNT_NV , SH_ACS_SCOM ); @@ -530,10 +572,34 @@ REG64( NV_0_CERR_FIRST2 , RULL(0x050110C9 REG64( NV_1_CERR_FIRST2 , RULL(0x050110E9), SH_UNT_NV_1 , SH_ACS_SCOM ); REG64( NV_2_CERR_FIRST2 , RULL(0x050111C9), SH_UNT_NV_2 , SH_ACS_SCOM ); REG64( NV_3_CERR_FIRST2 , RULL(0x050111E9), SH_UNT_NV_3 , SH_ACS_SCOM ); +REG64( PU_NPU0_SM0_CERR_FIRST2 , RULL(0x05011019), SH_UNT_PU_NPU0_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM1_CERR_FIRST2 , RULL(0x05011039), SH_UNT_PU_NPU0_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM2_CERR_FIRST2 , RULL(0x05011059), SH_UNT_PU_NPU0_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM3_CERR_FIRST2 , RULL(0x05011079), SH_UNT_PU_NPU0_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM0_CERR_FIRST2 , RULL(0x05011119), SH_UNT_PU_NPU1_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM1_CERR_FIRST2 , RULL(0x05011139), SH_UNT_PU_NPU1_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM2_CERR_FIRST2 , RULL(0x05011159), SH_UNT_PU_NPU1_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM3_CERR_FIRST2 , RULL(0x05011179), SH_UNT_PU_NPU1_SM3, + SH_ACS_SCOM ); REG64( PU_NPU2_NTL0_CERR_FIRST2 , RULL(0x050112C9), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM ); REG64( PU_NPU2_NTL1_CERR_FIRST2 , RULL(0x050112E9), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM ); +REG64( PU_NPU2_SM0_CERR_FIRST2 , RULL(0x05011219), SH_UNT_PU_NPU2_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM1_CERR_FIRST2 , RULL(0x05011239), SH_UNT_PU_NPU2_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM2_CERR_FIRST2 , RULL(0x05011259), SH_UNT_PU_NPU2_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM3_CERR_FIRST2 , RULL(0x05011279), SH_UNT_PU_NPU2_SM3, + SH_ACS_SCOM ); REG64( PU_NPU0_CTL_CERR_HOLD0 , RULL(0x0501109E), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM ); @@ -541,29 +607,29 @@ REG64( PU_NPU1_CTL_CERR_HOLD0 , RULL(0x0501119E SH_ACS_SCOM ); REG64( PU_NPU2_CTL_CERR_HOLD0 , RULL(0x0501129E), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_CERR_HOLD0 , RULL(0x0501101E), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM0_CERR_HOLD0 , RULL(0x0501101D), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_CERR_HOLD0 , RULL(0x0501103E), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_CERR_HOLD0 , RULL(0x0501103D), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_CERR_HOLD0 , RULL(0x0501105E), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_CERR_HOLD0 , RULL(0x0501105D), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_CERR_HOLD0 , RULL(0x0501107E), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_CERR_HOLD0 , RULL(0x0501107D), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_CERR_HOLD0 , RULL(0x0501111E), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_CERR_HOLD0 , RULL(0x0501111D), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_CERR_HOLD0 , RULL(0x0501113E), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_CERR_HOLD0 , RULL(0x0501113D), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_CERR_HOLD0 , RULL(0x0501115E), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_CERR_HOLD0 , RULL(0x0501115D), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_CERR_HOLD0 , RULL(0x0501117E), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_CERR_HOLD0 , RULL(0x0501117D), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_CERR_HOLD0 , RULL(0x0501121E), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_CERR_HOLD0 , RULL(0x0501121D), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_CERR_HOLD0 , RULL(0x0501123E), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_CERR_HOLD0 , RULL(0x0501123D), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_CERR_HOLD0 , RULL(0x0501125E), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_CERR_HOLD0 , RULL(0x0501125D), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_CERR_HOLD0 , RULL(0x0501127E), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_CERR_HOLD0 , RULL(0x0501127D), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); REG64( NV_CERR_HOLD1 , RULL(0x050110C4), SH_UNT_NV , SH_ACS_SCOM ); @@ -577,33 +643,33 @@ REG64( PU_NPU1_CTL_CERR_HOLD1 , RULL(0x0501119F SH_ACS_SCOM ); REG64( PU_NPU2_CTL_CERR_HOLD1 , RULL(0x0501129F), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_CERR_HOLD1 , RULL(0x0501101F), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM0_CERR_HOLD1 , RULL(0x0501101E), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_CERR_HOLD1 , RULL(0x0501103F), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_CERR_HOLD1 , RULL(0x0501103E), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_CERR_HOLD1 , RULL(0x0501105F), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_CERR_HOLD1 , RULL(0x0501105E), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_CERR_HOLD1 , RULL(0x0501107F), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_CERR_HOLD1 , RULL(0x0501107E), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_CERR_HOLD1 , RULL(0x0501111F), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_CERR_HOLD1 , RULL(0x0501111E), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_CERR_HOLD1 , RULL(0x0501113F), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_CERR_HOLD1 , RULL(0x0501113E), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_CERR_HOLD1 , RULL(0x0501115F), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_CERR_HOLD1 , RULL(0x0501115E), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_CERR_HOLD1 , RULL(0x0501117F), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_CERR_HOLD1 , RULL(0x0501117E), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); REG64( PU_NPU2_NTL0_CERR_HOLD1 , RULL(0x050112C4), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM ); REG64( PU_NPU2_NTL1_CERR_HOLD1 , RULL(0x050112E4), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_CERR_HOLD1 , RULL(0x0501121F), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_CERR_HOLD1 , RULL(0x0501121E), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_CERR_HOLD1 , RULL(0x0501123F), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_CERR_HOLD1 , RULL(0x0501123E), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_CERR_HOLD1 , RULL(0x0501125F), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_CERR_HOLD1 , RULL(0x0501125E), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_CERR_HOLD1 , RULL(0x0501127F), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_CERR_HOLD1 , RULL(0x0501127E), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); REG64( NV_CERR_HOLD2 , RULL(0x050110C7), SH_UNT_NV , SH_ACS_SCOM ); @@ -611,10 +677,34 @@ REG64( NV_0_CERR_HOLD2 , RULL(0x050110C7 REG64( NV_1_CERR_HOLD2 , RULL(0x050110E7), SH_UNT_NV_1 , SH_ACS_SCOM ); REG64( NV_2_CERR_HOLD2 , RULL(0x050111C7), SH_UNT_NV_2 , SH_ACS_SCOM ); REG64( NV_3_CERR_HOLD2 , RULL(0x050111E7), SH_UNT_NV_3 , SH_ACS_SCOM ); +REG64( PU_NPU0_SM0_CERR_HOLD2 , RULL(0x0501101F), SH_UNT_PU_NPU0_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM1_CERR_HOLD2 , RULL(0x0501103F), SH_UNT_PU_NPU0_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM2_CERR_HOLD2 , RULL(0x0501105F), SH_UNT_PU_NPU0_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM3_CERR_HOLD2 , RULL(0x0501107F), SH_UNT_PU_NPU0_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM0_CERR_HOLD2 , RULL(0x0501111F), SH_UNT_PU_NPU1_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM1_CERR_HOLD2 , RULL(0x0501113F), SH_UNT_PU_NPU1_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM2_CERR_HOLD2 , RULL(0x0501115F), SH_UNT_PU_NPU1_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM3_CERR_HOLD2 , RULL(0x0501117F), SH_UNT_PU_NPU1_SM3, + SH_ACS_SCOM ); REG64( PU_NPU2_NTL0_CERR_HOLD2 , RULL(0x050112C7), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM ); REG64( PU_NPU2_NTL1_CERR_HOLD2 , RULL(0x050112E7), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM ); +REG64( PU_NPU2_SM0_CERR_HOLD2 , RULL(0x0501121F), SH_UNT_PU_NPU2_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM1_CERR_HOLD2 , RULL(0x0501123F), SH_UNT_PU_NPU2_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM2_CERR_HOLD2 , RULL(0x0501125F), SH_UNT_PU_NPU2_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM3_CERR_HOLD2 , RULL(0x0501127F), SH_UNT_PU_NPU2_SM3, + SH_ACS_SCOM ); REG64( PU_NPU0_CERR_LOG_FIRST , RULL(0x050110AC), SH_UNT_PU_NPU0 , SH_ACS_SCOM ); REG64( PU_NPU1_CERR_LOG_FIRST , RULL(0x050111AC), SH_UNT_PU_NPU1 , SH_ACS_SCOM ); @@ -634,29 +724,29 @@ REG64( PU_NPU1_CTL_CERR_MASK0 , RULL(0x0501119C SH_ACS_SCOM ); REG64( PU_NPU2_CTL_CERR_MASK0 , RULL(0x0501129C), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_CERR_MASK0 , RULL(0x0501101C), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM0_CERR_MASK0 , RULL(0x0501101A), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_CERR_MASK0 , RULL(0x0501103C), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_CERR_MASK0 , RULL(0x0501103A), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_CERR_MASK0 , RULL(0x0501105C), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_CERR_MASK0 , RULL(0x0501105A), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_CERR_MASK0 , RULL(0x0501107C), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_CERR_MASK0 , RULL(0x0501107A), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_CERR_MASK0 , RULL(0x0501111C), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_CERR_MASK0 , RULL(0x0501111A), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_CERR_MASK0 , RULL(0x0501113C), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_CERR_MASK0 , RULL(0x0501113A), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_CERR_MASK0 , RULL(0x0501115C), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_CERR_MASK0 , RULL(0x0501115A), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_CERR_MASK0 , RULL(0x0501117C), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_CERR_MASK0 , RULL(0x0501117A), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_CERR_MASK0 , RULL(0x0501121C), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_CERR_MASK0 , RULL(0x0501121A), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_CERR_MASK0 , RULL(0x0501123C), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_CERR_MASK0 , RULL(0x0501123A), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_CERR_MASK0 , RULL(0x0501125C), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_CERR_MASK0 , RULL(0x0501125A), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_CERR_MASK0 , RULL(0x0501127C), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_CERR_MASK0 , RULL(0x0501127A), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); REG64( NV_CERR_MASK1 , RULL(0x050110C5), SH_UNT_NV , SH_ACS_SCOM ); @@ -670,33 +760,33 @@ REG64( PU_NPU1_CTL_CERR_MASK1 , RULL(0x0501119D SH_ACS_SCOM ); REG64( PU_NPU2_CTL_CERR_MASK1 , RULL(0x0501129D), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_CERR_MASK1 , RULL(0x0501101D), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM0_CERR_MASK1 , RULL(0x0501101B), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_CERR_MASK1 , RULL(0x0501103D), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_CERR_MASK1 , RULL(0x0501103B), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_CERR_MASK1 , RULL(0x0501105D), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_CERR_MASK1 , RULL(0x0501105B), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_CERR_MASK1 , RULL(0x0501107D), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_CERR_MASK1 , RULL(0x0501107B), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_CERR_MASK1 , RULL(0x0501111D), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_CERR_MASK1 , RULL(0x0501111B), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_CERR_MASK1 , RULL(0x0501113D), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_CERR_MASK1 , RULL(0x0501113B), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_CERR_MASK1 , RULL(0x0501115D), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_CERR_MASK1 , RULL(0x0501115B), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_CERR_MASK1 , RULL(0x0501117D), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_CERR_MASK1 , RULL(0x0501117B), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); REG64( PU_NPU2_NTL0_CERR_MASK1 , RULL(0x050112C5), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM ); REG64( PU_NPU2_NTL1_CERR_MASK1 , RULL(0x050112E5), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_CERR_MASK1 , RULL(0x0501121D), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_CERR_MASK1 , RULL(0x0501121B), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_CERR_MASK1 , RULL(0x0501123D), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_CERR_MASK1 , RULL(0x0501123B), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_CERR_MASK1 , RULL(0x0501125D), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_CERR_MASK1 , RULL(0x0501125B), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_CERR_MASK1 , RULL(0x0501127D), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_CERR_MASK1 , RULL(0x0501127B), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); REG64( NV_CERR_MASK2 , RULL(0x050110C8), SH_UNT_NV , SH_ACS_SCOM ); @@ -704,10 +794,171 @@ REG64( NV_0_CERR_MASK2 , RULL(0x050110C8 REG64( NV_1_CERR_MASK2 , RULL(0x050110E8), SH_UNT_NV_1 , SH_ACS_SCOM ); REG64( NV_2_CERR_MASK2 , RULL(0x050111C8), SH_UNT_NV_2 , SH_ACS_SCOM ); REG64( NV_3_CERR_MASK2 , RULL(0x050111E8), SH_UNT_NV_3 , SH_ACS_SCOM ); +REG64( PU_NPU0_SM0_CERR_MASK2 , RULL(0x0501101C), SH_UNT_PU_NPU0_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM1_CERR_MASK2 , RULL(0x0501103C), SH_UNT_PU_NPU0_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM2_CERR_MASK2 , RULL(0x0501105C), SH_UNT_PU_NPU0_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM3_CERR_MASK2 , RULL(0x0501107C), SH_UNT_PU_NPU0_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM0_CERR_MASK2 , RULL(0x0501111C), SH_UNT_PU_NPU1_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM1_CERR_MASK2 , RULL(0x0501113C), SH_UNT_PU_NPU1_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM2_CERR_MASK2 , RULL(0x0501115C), SH_UNT_PU_NPU1_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM3_CERR_MASK2 , RULL(0x0501117C), SH_UNT_PU_NPU1_SM3, + SH_ACS_SCOM ); REG64( PU_NPU2_NTL0_CERR_MASK2 , RULL(0x050112C8), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM ); REG64( PU_NPU2_NTL1_CERR_MASK2 , RULL(0x050112E8), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM ); +REG64( PU_NPU2_SM0_CERR_MASK2 , RULL(0x0501121C), SH_UNT_PU_NPU2_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM1_CERR_MASK2 , RULL(0x0501123C), SH_UNT_PU_NPU2_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM2_CERR_MASK2 , RULL(0x0501125C), SH_UNT_PU_NPU2_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM3_CERR_MASK2 , RULL(0x0501127C), SH_UNT_PU_NPU2_SM3, + SH_ACS_SCOM ); + +REG64( PU_NPU0_CTL_CERR_MESSAGE0 , RULL(0x05011098), SH_UNT_PU_NPU0_CTL, + SH_ACS_SCOM ); +REG64( PU_NPU1_CTL_CERR_MESSAGE0 , RULL(0x05011198), SH_UNT_PU_NPU1_CTL, + SH_ACS_SCOM ); +REG64( PU_NPU2_CTL_CERR_MESSAGE0 , RULL(0x05011298), SH_UNT_PU_NPU2_CTL, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM0_CERR_MESSAGE0 , RULL(0x05011011), SH_UNT_PU_NPU0_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM1_CERR_MESSAGE0 , RULL(0x05011031), SH_UNT_PU_NPU0_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM2_CERR_MESSAGE0 , RULL(0x05011051), SH_UNT_PU_NPU0_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM3_CERR_MESSAGE0 , RULL(0x05011071), SH_UNT_PU_NPU0_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM0_CERR_MESSAGE0 , RULL(0x05011111), SH_UNT_PU_NPU1_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM1_CERR_MESSAGE0 , RULL(0x05011131), SH_UNT_PU_NPU1_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM2_CERR_MESSAGE0 , RULL(0x05011151), SH_UNT_PU_NPU1_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM3_CERR_MESSAGE0 , RULL(0x05011171), SH_UNT_PU_NPU1_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM0_CERR_MESSAGE0 , RULL(0x05011211), SH_UNT_PU_NPU2_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM1_CERR_MESSAGE0 , RULL(0x05011231), SH_UNT_PU_NPU2_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM2_CERR_MESSAGE0 , RULL(0x05011251), SH_UNT_PU_NPU2_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM3_CERR_MESSAGE0 , RULL(0x05011271), SH_UNT_PU_NPU2_SM3, + SH_ACS_SCOM ); + +REG64( PU_NPU0_CTL_CERR_MESSAGE1 , RULL(0x05011099), SH_UNT_PU_NPU0_CTL, + SH_ACS_SCOM ); +REG64( PU_NPU1_CTL_CERR_MESSAGE1 , RULL(0x05011199), SH_UNT_PU_NPU1_CTL, + SH_ACS_SCOM ); +REG64( PU_NPU2_CTL_CERR_MESSAGE1 , RULL(0x05011299), SH_UNT_PU_NPU2_CTL, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM0_CERR_MESSAGE1 , RULL(0x05011012), SH_UNT_PU_NPU0_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM1_CERR_MESSAGE1 , RULL(0x05011032), SH_UNT_PU_NPU0_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM2_CERR_MESSAGE1 , RULL(0x05011052), SH_UNT_PU_NPU0_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM3_CERR_MESSAGE1 , RULL(0x05011072), SH_UNT_PU_NPU0_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM0_CERR_MESSAGE1 , RULL(0x05011112), SH_UNT_PU_NPU1_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM1_CERR_MESSAGE1 , RULL(0x05011132), SH_UNT_PU_NPU1_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM2_CERR_MESSAGE1 , RULL(0x05011152), SH_UNT_PU_NPU1_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM3_CERR_MESSAGE1 , RULL(0x05011172), SH_UNT_PU_NPU1_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM0_CERR_MESSAGE1 , RULL(0x05011212), SH_UNT_PU_NPU2_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM1_CERR_MESSAGE1 , RULL(0x05011232), SH_UNT_PU_NPU2_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM2_CERR_MESSAGE1 , RULL(0x05011252), SH_UNT_PU_NPU2_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM3_CERR_MESSAGE1 , RULL(0x05011272), SH_UNT_PU_NPU2_SM3, + SH_ACS_SCOM ); + +REG64( PU_NPU0_SM0_CERR_MESSAGE2 , RULL(0x05011013), SH_UNT_PU_NPU0_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM1_CERR_MESSAGE2 , RULL(0x05011033), SH_UNT_PU_NPU0_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM2_CERR_MESSAGE2 , RULL(0x05011053), SH_UNT_PU_NPU0_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM3_CERR_MESSAGE2 , RULL(0x05011073), SH_UNT_PU_NPU0_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM0_CERR_MESSAGE2 , RULL(0x05011113), SH_UNT_PU_NPU1_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM1_CERR_MESSAGE2 , RULL(0x05011133), SH_UNT_PU_NPU1_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM2_CERR_MESSAGE2 , RULL(0x05011153), SH_UNT_PU_NPU1_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM3_CERR_MESSAGE2 , RULL(0x05011173), SH_UNT_PU_NPU1_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM0_CERR_MESSAGE2 , RULL(0x05011213), SH_UNT_PU_NPU2_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM1_CERR_MESSAGE2 , RULL(0x05011233), SH_UNT_PU_NPU2_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM2_CERR_MESSAGE2 , RULL(0x05011253), SH_UNT_PU_NPU2_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM3_CERR_MESSAGE2 , RULL(0x05011273), SH_UNT_PU_NPU2_SM3, + SH_ACS_SCOM ); + +REG64( PU_NPU0_SM0_CERR_MESSAGE3 , RULL(0x05011014), SH_UNT_PU_NPU0_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM1_CERR_MESSAGE3 , RULL(0x05011034), SH_UNT_PU_NPU0_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM2_CERR_MESSAGE3 , RULL(0x05011054), SH_UNT_PU_NPU0_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM3_CERR_MESSAGE3 , RULL(0x05011074), SH_UNT_PU_NPU0_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM0_CERR_MESSAGE3 , RULL(0x05011114), SH_UNT_PU_NPU1_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM1_CERR_MESSAGE3 , RULL(0x05011134), SH_UNT_PU_NPU1_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM2_CERR_MESSAGE3 , RULL(0x05011154), SH_UNT_PU_NPU1_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM3_CERR_MESSAGE3 , RULL(0x05011174), SH_UNT_PU_NPU1_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM0_CERR_MESSAGE3 , RULL(0x05011214), SH_UNT_PU_NPU2_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM1_CERR_MESSAGE3 , RULL(0x05011234), SH_UNT_PU_NPU2_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM2_CERR_MESSAGE3 , RULL(0x05011254), SH_UNT_PU_NPU2_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM3_CERR_MESSAGE3 , RULL(0x05011274), SH_UNT_PU_NPU2_SM3, + SH_ACS_SCOM ); + +REG64( PU_NPU0_SM0_CERR_MESSAGE4 , RULL(0x05011015), SH_UNT_PU_NPU0_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM1_CERR_MESSAGE4 , RULL(0x05011035), SH_UNT_PU_NPU0_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM2_CERR_MESSAGE4 , RULL(0x05011055), SH_UNT_PU_NPU0_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM3_CERR_MESSAGE4 , RULL(0x05011075), SH_UNT_PU_NPU0_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM0_CERR_MESSAGE4 , RULL(0x05011115), SH_UNT_PU_NPU1_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM1_CERR_MESSAGE4 , RULL(0x05011135), SH_UNT_PU_NPU1_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM2_CERR_MESSAGE4 , RULL(0x05011155), SH_UNT_PU_NPU1_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM3_CERR_MESSAGE4 , RULL(0x05011175), SH_UNT_PU_NPU1_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM0_CERR_MESSAGE4 , RULL(0x05011215), SH_UNT_PU_NPU2_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM1_CERR_MESSAGE4 , RULL(0x05011235), SH_UNT_PU_NPU2_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM2_CERR_MESSAGE4 , RULL(0x05011255), SH_UNT_PU_NPU2_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM3_CERR_MESSAGE4 , RULL(0x05011275), SH_UNT_PU_NPU2_SM3, + SH_ACS_SCOM ); REG64( PU_NPU0_CERR_PTY_FIRST , RULL(0x050110A9), SH_UNT_PU_NPU0 , SH_ACS_SCOM ); REG64( PU_NPU1_CERR_PTY_FIRST , RULL(0x050111A9), SH_UNT_PU_NPU1 , SH_ACS_SCOM ); @@ -721,30 +972,6 @@ REG64( PU_NPU0_CERR_PTY_MASK , RULL(0x050110A8 REG64( PU_NPU1_CERR_PTY_MASK , RULL(0x050111A8), SH_UNT_PU_NPU1 , SH_ACS_SCOM ); REG64( PU_NPU2_CERR_PTY_MASK , RULL(0x050112A8), SH_UNT_PU_NPU2 , SH_ACS_SCOM ); -REG64( PEC_0_STACK0_CERR_RPT0_REG , RULL(0x04010C4A), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM_RO ); -REG64( PEC_0_STACK1_CERR_RPT0_REG , RULL(0x04010C8A), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM_RO ); -REG64( PEC_0_STACK2_CERR_RPT0_REG , RULL(0x04010CCA), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM_RO ); -REG64( PEC_1_STACK0_CERR_RPT0_REG , RULL(0x0401104A), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM_RO ); -REG64( PEC_1_STACK1_CERR_RPT0_REG , RULL(0x0401108A), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM_RO ); -REG64( PEC_1_STACK2_CERR_RPT0_REG , RULL(0x040110CA), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM_RO ); -REG64( PEC_2_STACK0_CERR_RPT0_REG , RULL(0x0401144A), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM_RO ); -REG64( PEC_2_STACK1_CERR_RPT0_REG , RULL(0x0401148A), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM_RO ); -REG64( PEC_2_STACK2_CERR_RPT0_REG , RULL(0x040114CA), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM_RO ); -REG64( PEC_STACK0_CERR_RPT0_REG , RULL(0x04010C4A), SH_UNT_PEC_STACK0, - SH_ACS_SCOM_RO ); -REG64( PEC_STACK1_CERR_RPT0_REG , RULL(0x04010C8A), SH_UNT_PEC_STACK1, - SH_ACS_SCOM_RO ); -REG64( PEC_STACK2_CERR_RPT0_REG , RULL(0x04010CCA), SH_UNT_PEC_STACK2, - SH_ACS_SCOM_RO ); REG64( PHB_CERR_RPT0_REG , RULL(0x04010C4A), SH_UNT_PHB , SH_ACS_SCOM_RO ); REG64( PHB_0_CERR_RPT0_REG , RULL(0x04010C4A), SH_UNT_PHB_0 , SH_ACS_SCOM_RO ); REG64( PHB_1_CERR_RPT0_REG , RULL(0x0401104A), SH_UNT_PHB_1 , SH_ACS_SCOM_RO ); @@ -753,30 +980,6 @@ REG64( PHB_3_CERR_RPT0_REG , RULL(0x0401144A REG64( PHB_4_CERR_RPT0_REG , RULL(0x0401148A), SH_UNT_PHB_4 , SH_ACS_SCOM_RO ); REG64( PHB_5_CERR_RPT0_REG , RULL(0x040114CA), SH_UNT_PHB_5 , SH_ACS_SCOM_RO ); -REG64( PEC_0_STACK0_CERR_RPT1_REG , RULL(0x04010C4B), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM_RO ); -REG64( PEC_0_STACK1_CERR_RPT1_REG , RULL(0x04010C8B), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM_RO ); -REG64( PEC_0_STACK2_CERR_RPT1_REG , RULL(0x04010CCB), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM_RO ); -REG64( PEC_1_STACK0_CERR_RPT1_REG , RULL(0x0401104B), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM_RO ); -REG64( PEC_1_STACK1_CERR_RPT1_REG , RULL(0x0401108B), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM_RO ); -REG64( PEC_1_STACK2_CERR_RPT1_REG , RULL(0x040110CB), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM_RO ); -REG64( PEC_2_STACK0_CERR_RPT1_REG , RULL(0x0401144B), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM_RO ); -REG64( PEC_2_STACK1_CERR_RPT1_REG , RULL(0x0401148B), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM_RO ); -REG64( PEC_2_STACK2_CERR_RPT1_REG , RULL(0x040114CB), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM_RO ); -REG64( PEC_STACK0_CERR_RPT1_REG , RULL(0x04010C4B), SH_UNT_PEC_STACK0, - SH_ACS_SCOM_RO ); -REG64( PEC_STACK1_CERR_RPT1_REG , RULL(0x04010C8B), SH_UNT_PEC_STACK1, - SH_ACS_SCOM_RO ); -REG64( PEC_STACK2_CERR_RPT1_REG , RULL(0x04010CCB), SH_UNT_PEC_STACK2, - SH_ACS_SCOM_RO ); REG64( PHB_CERR_RPT1_REG , RULL(0x04010C4B), SH_UNT_PHB , SH_ACS_SCOM_RO ); REG64( PHB_0_CERR_RPT1_REG , RULL(0x04010C4B), SH_UNT_PHB_0 , SH_ACS_SCOM_RO ); REG64( PHB_1_CERR_RPT1_REG , RULL(0x0401104B), SH_UNT_PHB_1 , SH_ACS_SCOM_RO ); @@ -785,6 +988,14 @@ REG64( PHB_3_CERR_RPT1_REG , RULL(0x0401144B REG64( PHB_4_CERR_RPT1_REG , RULL(0x0401148B), SH_UNT_PHB_4 , SH_ACS_SCOM_RO ); REG64( PHB_5_CERR_RPT1_REG , RULL(0x040114CB), SH_UNT_PHB_5 , SH_ACS_SCOM_RO ); +REG64( PEC_CLK_REGION , RULL(0x0D030006), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_CLOCK_STAT_ARY , RULL(0x0D03000A), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_CLOCK_STAT_NSL , RULL(0x0D030009), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_CLOCK_STAT_SL , RULL(0x0D030008), SH_UNT_PEC , SH_ACS_SCOM ); + REG64( PU_CME0_CME_LCL_DBG_PPE , RULL(0x109010120), SH_UNT_PU_CME0 , SH_ACS_PPE ); REG64( PU_CME0_CME_LCL_DBG_PPE1 , RULL(0x109010138), SH_UNT_PU_CME0 , @@ -2267,16 +2478,13 @@ REG64( NV_2_CONFIG1 , RULL(0x050111D0 REG64( NV_3_CONFIG1 , RULL(0x050111F0), SH_UNT_NV_3 , SH_ACS_SCOM ); REG64( PU_NPU0_CTL_CONFIG1 , RULL(0x05011081), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_DAT_CONFIG1 , RULL(0x050110B0), SH_UNT_PU_NPU0_DAT, - SH_ACS_SCOM ); +REG64( PU_NPU0_CONFIG1 , RULL(0x050110A1), SH_UNT_PU_NPU0 , SH_ACS_SCOM ); +REG64( PU_NPU1_CONFIG1 , RULL(0x050111A1), SH_UNT_PU_NPU1 , SH_ACS_SCOM ); REG64( PU_NPU1_CTL_CONFIG1 , RULL(0x05011181), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM ); -REG64( PU_NPU1_DAT_CONFIG1 , RULL(0x050111B0), SH_UNT_PU_NPU1_DAT, - SH_ACS_SCOM ); -REG64( PU_NPU2_DAT_CONFIG1 , RULL(0x050112B0), SH_UNT_PU_NPU2_DAT, - SH_ACS_SCOM ); REG64( PU_NPU2_CTL_CONFIG1 , RULL(0x05011281), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); +REG64( PU_NPU2_CONFIG1 , RULL(0x050112A1), SH_UNT_PU_NPU2 , SH_ACS_SCOM ); REG64( PU_NPU0_SM0_CONFIG1 , RULL(0x05011001), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); REG64( PU_NPU0_SM1_CONFIG1 , RULL(0x05011021), SH_UNT_PU_NPU0_SM1, @@ -2317,75 +2525,104 @@ REG64( PU_NPU1_CTL_CONFIG2 , RULL(0x05011182 SH_ACS_SCOM ); REG64( PU_NPU2_CTL_CONFIG2 , RULL(0x05011282), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_CONFIG2 , RULL(0x05011002), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU2_NTL0_CONFIG2 , RULL(0x050112C0), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_CONFIG2 , RULL(0x05011022), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU2_NTL1_CONFIG2 , RULL(0x050112E0), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_CONFIG2 , RULL(0x05011042), SH_UNT_PU_NPU0_SM2, + +REG64( NV_CONFIG3 , RULL(0x050110C1), SH_UNT_NV , SH_ACS_SCOM ); +REG64( NV_0_CONFIG3 , RULL(0x050110C1), SH_UNT_NV_0 , SH_ACS_SCOM ); +REG64( NV_1_CONFIG3 , RULL(0x050110E1), SH_UNT_NV_1 , SH_ACS_SCOM ); +REG64( NV_2_CONFIG3 , RULL(0x050111C1), SH_UNT_NV_2 , SH_ACS_SCOM ); +REG64( NV_3_CONFIG3 , RULL(0x050111E1), SH_UNT_NV_3 , SH_ACS_SCOM ); +REG64( PU_NPU0_CTL_CONFIG3 , RULL(0x05011083), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_CONFIG2 , RULL(0x05011062), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU1_CTL_CONFIG3 , RULL(0x05011183), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_CONFIG2 , RULL(0x05011102), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU2_CTL_CONFIG3 , RULL(0x05011283), SH_UNT_PU_NPU2_CTL, + SH_ACS_SCOM ); +REG64( PU_NPU2_NTL0_CONFIG3 , RULL(0x050112C1), SH_UNT_PU_NPU2_NTL0, + SH_ACS_SCOM ); +REG64( PU_NPU2_NTL1_CONFIG3 , RULL(0x050112E1), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_CONFIG2 , RULL(0x05011122), SH_UNT_PU_NPU1_SM1, + +REG64( PU_NPU0_SM0_CONFIG_RELAXED0 , RULL(0x0501100A), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_CONFIG2 , RULL(0x05011142), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU0_SM1_CONFIG_RELAXED0 , RULL(0x0501102A), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_CONFIG2 , RULL(0x05011162), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU0_SM2_CONFIG_RELAXED0 , RULL(0x0501104A), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_NTL0_CONFIG2 , RULL(0x050112C0), SH_UNT_PU_NPU2_NTL0, +REG64( PU_NPU0_SM3_CONFIG_RELAXED0 , RULL(0x0501106A), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_NTL1_CONFIG2 , RULL(0x050112E0), SH_UNT_PU_NPU2_NTL1, +REG64( PU_NPU1_SM0_CONFIG_RELAXED0 , RULL(0x0501110A), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_CONFIG2 , RULL(0x05011202), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU1_SM1_CONFIG_RELAXED0 , RULL(0x0501112A), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_CONFIG2 , RULL(0x05011222), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU1_SM2_CONFIG_RELAXED0 , RULL(0x0501114A), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_CONFIG2 , RULL(0x05011242), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU1_SM3_CONFIG_RELAXED0 , RULL(0x0501116A), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_CONFIG2 , RULL(0x05011262), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM0_CONFIG_RELAXED0 , RULL(0x0501120A), SH_UNT_PU_NPU2_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM1_CONFIG_RELAXED0 , RULL(0x0501122A), SH_UNT_PU_NPU2_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM2_CONFIG_RELAXED0 , RULL(0x0501124A), SH_UNT_PU_NPU2_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM3_CONFIG_RELAXED0 , RULL(0x0501126A), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); -REG64( NV_CONFIG3 , RULL(0x050110C1), SH_UNT_NV , SH_ACS_SCOM ); -REG64( NV_0_CONFIG3 , RULL(0x050110C1), SH_UNT_NV_0 , SH_ACS_SCOM ); -REG64( NV_1_CONFIG3 , RULL(0x050110E1), SH_UNT_NV_1 , SH_ACS_SCOM ); -REG64( NV_2_CONFIG3 , RULL(0x050111C1), SH_UNT_NV_2 , SH_ACS_SCOM ); -REG64( NV_3_CONFIG3 , RULL(0x050111E1), SH_UNT_NV_3 , SH_ACS_SCOM ); -REG64( PU_NPU0_CTL_CONFIG3 , RULL(0x05011083), SH_UNT_PU_NPU0_CTL, +REG64( PU_NPU0_SM0_CONFIG_RELAXED1 , RULL(0x0501100B), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_CTL_CONFIG3 , RULL(0x05011183), SH_UNT_PU_NPU1_CTL, +REG64( PU_NPU0_SM1_CONFIG_RELAXED1 , RULL(0x0501102B), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_CTL_CONFIG3 , RULL(0x05011283), SH_UNT_PU_NPU2_CTL, +REG64( PU_NPU0_SM2_CONFIG_RELAXED1 , RULL(0x0501104B), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_CONFIG3 , RULL(0x05011003), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM3_CONFIG_RELAXED1 , RULL(0x0501106B), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_CONFIG3 , RULL(0x05011023), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU1_SM0_CONFIG_RELAXED1 , RULL(0x0501110B), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_CONFIG3 , RULL(0x05011043), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU1_SM1_CONFIG_RELAXED1 , RULL(0x0501112B), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_CONFIG3 , RULL(0x05011063), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU1_SM2_CONFIG_RELAXED1 , RULL(0x0501114B), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_CONFIG3 , RULL(0x05011103), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM3_CONFIG_RELAXED1 , RULL(0x0501116B), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_CONFIG3 , RULL(0x05011123), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU2_SM0_CONFIG_RELAXED1 , RULL(0x0501120B), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_CONFIG3 , RULL(0x05011143), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU2_SM1_CONFIG_RELAXED1 , RULL(0x0501122B), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_CONFIG3 , RULL(0x05011163), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU2_SM2_CONFIG_RELAXED1 , RULL(0x0501124B), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_NTL0_CONFIG3 , RULL(0x050112C1), SH_UNT_PU_NPU2_NTL0, +REG64( PU_NPU2_SM3_CONFIG_RELAXED1 , RULL(0x0501126B), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_NTL1_CONFIG3 , RULL(0x050112E1), SH_UNT_PU_NPU2_NTL1, + +REG64( PU_NPU0_SM0_CONFIG_RELAXED2 , RULL(0x0501100C), SH_UNT_PU_NPU0_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM1_CONFIG_RELAXED2 , RULL(0x0501102C), SH_UNT_PU_NPU0_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM2_CONFIG_RELAXED2 , RULL(0x0501104C), SH_UNT_PU_NPU0_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM3_CONFIG_RELAXED2 , RULL(0x0501106C), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_CONFIG3 , RULL(0x05011203), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU1_SM0_CONFIG_RELAXED2 , RULL(0x0501110C), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_CONFIG3 , RULL(0x05011223), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU1_SM1_CONFIG_RELAXED2 , RULL(0x0501112C), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_CONFIG3 , RULL(0x05011243), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU1_SM2_CONFIG_RELAXED2 , RULL(0x0501114C), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_CONFIG3 , RULL(0x05011263), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU1_SM3_CONFIG_RELAXED2 , RULL(0x0501116C), SH_UNT_PU_NPU1_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM0_CONFIG_RELAXED2 , RULL(0x0501120C), SH_UNT_PU_NPU2_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM1_CONFIG_RELAXED2 , RULL(0x0501122C), SH_UNT_PU_NPU2_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM2_CONFIG_RELAXED2 , RULL(0x0501124C), SH_UNT_PU_NPU2_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM3_CONFIG_RELAXED2 , RULL(0x0501126C), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); +REG64( PEC_CONTROL_REG , RULL(0x0D050012), SH_UNT_PEC , SH_ACS_SCOM ); + REG64( PU_CONTROL_REGISTER_B , RULL(0x000A0000), SH_UNT , SH_ACS_SCOM ); REG64( PU_CONTROL_REGISTER_C , RULL(0x000A1000), SH_UNT , SH_ACS_SCOM ); @@ -2394,30 +2631,30 @@ REG64( PU_CONTROL_REGISTER_D , RULL(0x000A2000 REG64( PU_CONTROL_REGISTER_E , RULL(0x000A3000), SH_UNT , SH_ACS_SCOM ); -REG64( PEC_0_STACK0_CQSTAT_REG , RULL(0x04010C4C), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM_RO ); -REG64( PEC_0_STACK1_CQSTAT_REG , RULL(0x04010C8C), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM_RO ); -REG64( PEC_0_STACK2_CQSTAT_REG , RULL(0x04010CCC), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM_RO ); -REG64( PEC_1_STACK0_CQSTAT_REG , RULL(0x0401104C), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM_RO ); -REG64( PEC_1_STACK1_CQSTAT_REG , RULL(0x0401108C), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM_RO ); -REG64( PEC_1_STACK2_CQSTAT_REG , RULL(0x040110CC), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM_RO ); -REG64( PEC_2_STACK0_CQSTAT_REG , RULL(0x0401144C), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM_RO ); -REG64( PEC_2_STACK1_CQSTAT_REG , RULL(0x0401148C), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM_RO ); -REG64( PEC_2_STACK2_CQSTAT_REG , RULL(0x040114CC), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM_RO ); -REG64( PEC_STACK0_CQSTAT_REG , RULL(0x04010C4C), SH_UNT_PEC_STACK0, - SH_ACS_SCOM_RO ); -REG64( PEC_STACK1_CQSTAT_REG , RULL(0x04010C8C), SH_UNT_PEC_STACK1, - SH_ACS_SCOM_RO ); -REG64( PEC_STACK2_CQSTAT_REG , RULL(0x04010CCC), SH_UNT_PEC_STACK2, - SH_ACS_SCOM_RO ); +REG64( PEC_CPLT_CONF0 , RULL(0x0D000008), SH_UNT_PEC , SH_ACS_SCOM_RW ); +REG64( PEC_CPLT_CONF0_OR , RULL(0x0D000018), SH_UNT_PEC , SH_ACS_SCOM1_OR ); +REG64( PEC_CPLT_CONF0_CLEAR , RULL(0x0D000028), SH_UNT_PEC , + SH_ACS_SCOM2_CLEAR ); + +REG64( PEC_CPLT_CONF1 , RULL(0x0D000009), SH_UNT_PEC , SH_ACS_SCOM_RW ); +REG64( PEC_CPLT_CONF1_OR , RULL(0x0D000019), SH_UNT_PEC , SH_ACS_SCOM1_OR ); +REG64( PEC_CPLT_CONF1_CLEAR , RULL(0x0D000029), SH_UNT_PEC , + SH_ACS_SCOM2_CLEAR ); + +REG64( PEC_CPLT_CTRL0 , RULL(0x0D000000), SH_UNT_PEC , SH_ACS_SCOM_RW ); +REG64( PEC_CPLT_CTRL0_OR , RULL(0x0D000010), SH_UNT_PEC , SH_ACS_SCOM1_OR ); +REG64( PEC_CPLT_CTRL0_CLEAR , RULL(0x0D000020), SH_UNT_PEC , + SH_ACS_SCOM2_CLEAR ); + +REG64( PEC_CPLT_CTRL1 , RULL(0x0D000001), SH_UNT_PEC , SH_ACS_SCOM_RW ); +REG64( PEC_CPLT_CTRL1_OR , RULL(0x0D000011), SH_UNT_PEC , SH_ACS_SCOM1_OR ); +REG64( PEC_CPLT_CTRL1_CLEAR , RULL(0x0D000021), SH_UNT_PEC , + SH_ACS_SCOM2_CLEAR ); + +REG64( PEC_CPLT_MASK0 , RULL(0x0D000101), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_CPLT_STAT0 , RULL(0x0D000100), SH_UNT_PEC , SH_ACS_SCOM ); + REG64( PHB_CQSTAT_REG , RULL(0x04010C4C), SH_UNT_PHB , SH_ACS_SCOM_RO ); REG64( PHB_0_CQSTAT_REG , RULL(0x04010C4C), SH_UNT_PHB_0 , SH_ACS_SCOM_RO ); REG64( PHB_1_CQSTAT_REG , RULL(0x0401104C), SH_UNT_PHB_1 , SH_ACS_SCOM_RO ); @@ -2426,14 +2663,86 @@ REG64( PHB_3_CQSTAT_REG , RULL(0x0401144C REG64( PHB_4_CQSTAT_REG , RULL(0x0401148C), SH_UNT_PHB_4 , SH_ACS_SCOM_RO ); REG64( PHB_5_CQSTAT_REG , RULL(0x040114CC), SH_UNT_PHB_5 , SH_ACS_SCOM_RO ); -REG64( PU_IOPPE_CSAR , RULL(0x06010803), SH_UNT_PU_IOPPE , SH_ACS_SCOM_RW ); +REG64( PU_CSAR , RULL(0x06010858), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_CSCR , RULL(0x06010855), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_IOPPE_CSCR , RULL(0x06010800), SH_UNT_PU_IOPPE , SH_ACS_SCOM_RW ); REG64( PU_IOPPE_CSCR_CLEAR , RULL(0x06010801), SH_UNT_PU_IOPPE , SH_ACS_SCOM1_CLEAR ); REG64( PU_IOPPE_CSCR_OR , RULL(0x06010802), SH_UNT_PU_IOPPE , SH_ACS_SCOM2_OR ); -REG64( PU_IOPPE_CSDR , RULL(0x06010804), SH_UNT_PU_IOPPE , SH_ACS_SCOM_RW ); +REG64( PU_CSDR , RULL(0x06010859), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_NPU0_CTL_CTL_STATUS , RULL(0x05011092), SH_UNT_PU_NPU0_CTL, + SH_ACS_SCOM ); +REG64( PU_NPU1_CTL_CTL_STATUS , RULL(0x05011192), SH_UNT_PU_NPU1_CTL, + SH_ACS_SCOM ); +REG64( PU_NPU2_CTL_CTL_STATUS , RULL(0x05011292), SH_UNT_PU_NPU2_CTL, + SH_ACS_SCOM ); + +REG64( PEC_CTRL_ATOMIC_LOCK_REG , RULL(0x0D0003FF), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_CTRL_PROTECT_MODE_REG , RULL(0x0D0003FE), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_ARRAY_ADDR_REG , RULL(0x02010828), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_ARRAY_ADDR_REG , RULL(0x02010828), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_ARRAY_ADDR_REG , RULL(0x04010828), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_ARRAY_READ_REG , RULL(0x02010829), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_ARRAY_READ_REG , RULL(0x02010829), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_ARRAY_READ_REG , RULL(0x04010829), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_ARRAY_WRITE_REG , RULL(0x02010841), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_ARRAY_WRITE_REG , RULL(0x02010841), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_ARRAY_WRITE_REG , RULL(0x04010841), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_CAN_PRESP_REG0 , RULL(0x0201081D), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_CAN_PRESP_REG0 , RULL(0x0201081D), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_CAN_PRESP_REG0 , RULL(0x0401081D), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_CAN_PRESP_REG1 , RULL(0x0201081E), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_CAN_PRESP_REG1 , RULL(0x0201081E), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_CAN_PRESP_REG1 , RULL(0x0401081E), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_CAN_PRESP_REG2 , RULL(0x0201081F), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_CAN_PRESP_REG2 , RULL(0x0201081F), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_CAN_PRESP_REG2 , RULL(0x0401081F), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_CAPI_CFG_REG , RULL(0x0201081A), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_CAPI_CFG_REG , RULL(0x0201081A), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_CAPI_CFG_REG , RULL(0x0401081A), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_CNTL_REG , RULL(0x0201081B), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_CNTL_REG , RULL(0x0201081B), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_CNTL_REG , RULL(0x0401081B), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_ERROR_REPORT_REG , RULL(0x0201080A), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_ERROR_REPORT_REG , RULL(0x0201080A), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_ERROR_REPORT_REG , RULL(0x0401080A), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_PHB_TTAG_FILTER_REG , RULL(0x02010831), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_PHB_TTAG_FILTER_REG , RULL(0x02010831), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_PHB_TTAG_FILTER_REG , RULL(0x04010831), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG , RULL(0x02010817), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_PMU_EVENTS_SELECT_REG , RULL(0x02010817), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_PMU_EVENTS_SELECT_REG , RULL(0x04010817), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG , RULL(0x02010840), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG , RULL(0x02010840), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG , RULL(0x04010840), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1 , RULL(0x02010844), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1 , RULL(0x02010844), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1 , RULL(0x04010844), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG , RULL(0x0201084A), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG , RULL(0x0201084A), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG , RULL(0x0401084A), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1 , RULL(0x0201084B), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1 , RULL(0x0201084B), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1 , RULL(0x0401084B), SH_UNT_CAPP_1 , SH_ACS_SCOM ); REG64( PU_DATA0TO7_REGISTER_B , RULL(0x000A0003), SH_UNT , SH_ACS_SCOM ); @@ -2471,80 +2780,126 @@ REG64( PU_NPU_CTL_DA_ADDR , RULL(0x0501138E REG64( PU_NPU_CTL_DA_DATA , RULL(0x0501138F), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM_RW ); +REG64( PEC_DBG_CBS_CC , RULL(0x0D030013), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_DBG_INST1_COND_REG_1 , RULL(0x0D0107C1), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_DBG_INST1_COND_REG_1 , RULL(0x020107E1), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_DBG_INST1_COND_REG_1 , RULL(0x030107E1), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_DBG_INST1_COND_REG_1 , RULL(0x040107E1), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_DBG_INST1_COND_REG_1 , RULL(0x050107E1), SH_UNT_PU_N3 , SH_ACS_SCOM ); + +REG64( PEC_DBG_INST1_COND_REG_2 , RULL(0x0D0107C2), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_DBG_INST1_COND_REG_2 , RULL(0x020107E2), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_DBG_INST1_COND_REG_2 , RULL(0x030107E2), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_DBG_INST1_COND_REG_2 , RULL(0x040107E2), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_DBG_INST1_COND_REG_2 , RULL(0x050107E2), SH_UNT_PU_N3 , SH_ACS_SCOM ); + +REG64( PEC_DBG_INST2_COND_REG_1 , RULL(0x0D0107C3), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_DBG_INST2_COND_REG_1 , RULL(0x020107E3), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_DBG_INST2_COND_REG_1 , RULL(0x030107E3), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_DBG_INST2_COND_REG_1 , RULL(0x040107E3), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_DBG_INST2_COND_REG_1 , RULL(0x050107E3), SH_UNT_PU_N3 , SH_ACS_SCOM ); + +REG64( PEC_DBG_INST2_COND_REG_2 , RULL(0x0D0107C4), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_DBG_INST2_COND_REG_2 , RULL(0x020107E4), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_DBG_INST2_COND_REG_2 , RULL(0x030107E4), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_DBG_INST2_COND_REG_2 , RULL(0x040107E4), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_DBG_INST2_COND_REG_2 , RULL(0x050107E4), SH_UNT_PU_N3 , SH_ACS_SCOM ); + +REG64( PEC_DBG_MODE_REG , RULL(0x0D0107C0), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_DBG_MODE_REG , RULL(0x020107E0), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_DBG_MODE_REG , RULL(0x030107E0), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_DBG_MODE_REG , RULL(0x040107E0), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_DBG_MODE_REG , RULL(0x050107E0), SH_UNT_PU_N3 , SH_ACS_SCOM ); + +REG64( PEC_DBG_TRACE_MODE_REG_2 , RULL(0x0D0107CB), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_DBG_TRACE_MODE_REG_2 , RULL(0x020107EB), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_DBG_TRACE_MODE_REG_2 , RULL(0x030107EB), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_DBG_TRACE_MODE_REG_2 , RULL(0x040107EB), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_DBG_TRACE_MODE_REG_2 , RULL(0x050107EB), SH_UNT_PU_N3 , SH_ACS_SCOM ); + +REG64( PEC_DBG_TRACE_REG_0 , RULL(0x0D0107C9), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_DBG_TRACE_REG_0 , RULL(0x020107E9), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_DBG_TRACE_REG_0 , RULL(0x030107E9), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_DBG_TRACE_REG_0 , RULL(0x040107E9), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_DBG_TRACE_REG_0 , RULL(0x050107E9), SH_UNT_PU_N3 , SH_ACS_SCOM ); + +REG64( PEC_DBG_TRACE_REG_1 , RULL(0x0D0107CA), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_DBG_TRACE_REG_1 , RULL(0x020107EA), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_DBG_TRACE_REG_1 , RULL(0x030107EA), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_DBG_TRACE_REG_1 , RULL(0x040107EA), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_DBG_TRACE_REG_1 , RULL(0x050107EA), SH_UNT_PU_N3 , SH_ACS_SCOM ); + REG64( PU_NPU0_CTL_DEBUG0_CONFIG , RULL(0x05011088), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_DAT_DEBUG0_CONFIG , RULL(0x050110B4), SH_UNT_PU_NPU0_DAT, - SH_ACS_SCOM ); REG64( PU_NPU1_CTL_DEBUG0_CONFIG , RULL(0x05011188), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM ); -REG64( PU_NPU1_DAT_DEBUG0_CONFIG , RULL(0x050111B4), SH_UNT_PU_NPU1_DAT, - SH_ACS_SCOM ); -REG64( PU_NPU2_DAT_DEBUG0_CONFIG , RULL(0x050112B4), SH_UNT_PU_NPU2_DAT, - SH_ACS_SCOM ); REG64( PU_NPU2_CTL_DEBUG0_CONFIG , RULL(0x05011288), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_DEBUG0_CONFIG , RULL(0x05011008), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM0_DEBUG0_CONFIG , RULL(0x0501100D), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_DEBUG0_CONFIG , RULL(0x05011028), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_DEBUG0_CONFIG , RULL(0x0501102D), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_DEBUG0_CONFIG , RULL(0x05011048), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_DEBUG0_CONFIG , RULL(0x0501104D), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_DEBUG0_CONFIG , RULL(0x05011068), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_DEBUG0_CONFIG , RULL(0x0501106D), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_DEBUG0_CONFIG , RULL(0x05011108), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_DEBUG0_CONFIG , RULL(0x0501110D), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_DEBUG0_CONFIG , RULL(0x05011128), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_DEBUG0_CONFIG , RULL(0x0501112D), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_DEBUG0_CONFIG , RULL(0x05011148), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_DEBUG0_CONFIG , RULL(0x0501114D), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_DEBUG0_CONFIG , RULL(0x05011168), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_DEBUG0_CONFIG , RULL(0x0501116D), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_DEBUG0_CONFIG , RULL(0x05011208), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_DEBUG0_CONFIG , RULL(0x0501120D), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_DEBUG0_CONFIG , RULL(0x05011228), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_DEBUG0_CONFIG , RULL(0x0501122D), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_DEBUG0_CONFIG , RULL(0x05011248), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_DEBUG0_CONFIG , RULL(0x0501124D), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_DEBUG0_CONFIG , RULL(0x05011268), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_DEBUG0_CONFIG , RULL(0x0501126D), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); REG64( PU_NPU_SM2_DEBUG0_CONFIG , RULL(0x05011346), SH_UNT_PU_NPU_SM2, SH_ACS_SCOM ); REG64( PU_NPU0_CTL_DEBUG1_CONFIG , RULL(0x05011089), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_DAT_DEBUG1_CONFIG , RULL(0x050110B5), SH_UNT_PU_NPU0_DAT, - SH_ACS_SCOM ); REG64( PU_NPU1_CTL_DEBUG1_CONFIG , RULL(0x05011189), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM ); -REG64( PU_NPU1_DAT_DEBUG1_CONFIG , RULL(0x050111B5), SH_UNT_PU_NPU1_DAT, - SH_ACS_SCOM ); -REG64( PU_NPU2_DAT_DEBUG1_CONFIG , RULL(0x050112B5), SH_UNT_PU_NPU2_DAT, - SH_ACS_SCOM ); REG64( PU_NPU2_CTL_DEBUG1_CONFIG , RULL(0x05011289), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_DEBUG1_CONFIG , RULL(0x05011009), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM0_DEBUG1_CONFIG , RULL(0x0501100E), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_DEBUG1_CONFIG , RULL(0x05011029), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_DEBUG1_CONFIG , RULL(0x0501102E), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_DEBUG1_CONFIG , RULL(0x05011049), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_DEBUG1_CONFIG , RULL(0x0501104E), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_DEBUG1_CONFIG , RULL(0x05011069), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_DEBUG1_CONFIG , RULL(0x0501106E), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_DEBUG1_CONFIG , RULL(0x05011109), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_DEBUG1_CONFIG , RULL(0x0501110E), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_DEBUG1_CONFIG , RULL(0x05011129), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_DEBUG1_CONFIG , RULL(0x0501112E), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_DEBUG1_CONFIG , RULL(0x05011149), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_DEBUG1_CONFIG , RULL(0x0501114E), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_DEBUG1_CONFIG , RULL(0x05011169), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_DEBUG1_CONFIG , RULL(0x0501116E), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_DEBUG1_CONFIG , RULL(0x05011209), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_DEBUG1_CONFIG , RULL(0x0501120E), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_DEBUG1_CONFIG , RULL(0x05011229), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_DEBUG1_CONFIG , RULL(0x0501122E), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_DEBUG1_CONFIG , RULL(0x05011249), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_DEBUG1_CONFIG , RULL(0x0501124E), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_DEBUG1_CONFIG , RULL(0x05011269), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_DEBUG1_CONFIG , RULL(0x0501126E), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); REG64( PU_NPU_SM2_DEBUG1_CONFIG , RULL(0x05011347), SH_UNT_PU_NPU_SM2, SH_ACS_SCOM ); @@ -2552,6 +2907,21 @@ REG64( PU_NPU_SM2_DEBUG1_CONFIG , RULL(0x05011347 REG64( PU_NPU_CTL_DEBUG_CONFIG , RULL(0x05011380), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM ); +REG64( CAPP_DEBUG_CONTROL , RULL(0x02010811), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_DEBUG_CONTROL , RULL(0x02010811), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_DEBUG_CONTROL , RULL(0x04010811), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( PEC_DEBUG_STATUS_REG , RULL(0x0D010004), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_DEBUG_STATUS_REG , RULL(0x02010004), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_DEBUG_STATUS_REG , RULL(0x03010004), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_DEBUG_STATUS_REG , RULL(0x04010004), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_DEBUG_STATUS_REG , RULL(0x05010004), SH_UNT_PU_N3 , SH_ACS_SCOM ); + +REG64( CAPP_DFSUOP1 , RULL(0x02010843), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_DFSUOP1 , RULL(0x02010843), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_DFSUOP1 , RULL(0x04010843), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + REG64( PU_DISABLE_FORCE_PFET_OFF , RULL(0x0001000D), SH_UNT , SH_ACS_SCOM ); REG64( PU_NPU_SM1_DMA_SYNC , RULL(0x05011323), SH_UNT_PU_NPU_SM1, @@ -2562,18 +2932,15 @@ REG64( PU_DMA_UP_ADDR , RULL(0x05012914 REG64( PU_DMA_VAS_MMIO_BAR , RULL(0x0201105E), SH_UNT , SH_ACS_SCOM_RW ); REG64( PEC_DRPPRICTL_REG , RULL(0x04010C01), SH_UNT_PEC , SH_ACS_SCOM_RW ); -REG64( PEC_0_DRPPRICTL_REG , RULL(0x04010C01), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); -REG64( PEC_1_DRPPRICTL_REG , RULL(0x04011001), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); -REG64( PEC_2_DRPPRICTL_REG , RULL(0x04011401), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); + +REG64( PEC_DTS_RESULT0 , RULL(0x0D050000), SH_UNT_PEC , SH_ACS_SCOM_RO ); + +REG64( PEC_DTS_TRC_RESULT , RULL(0x0D050003), SH_UNT_PEC , SH_ACS_SCOM_RO ); REG64( PU_NPU0_ECC_CONFIG , RULL(0x050110A2), SH_UNT_PU_NPU0 , SH_ACS_SCOM ); REG64( PU_NPU1_ECC_CONFIG , RULL(0x050111A2), SH_UNT_PU_NPU1 , SH_ACS_SCOM ); REG64( PU_NPU2_ECC_CONFIG , RULL(0x050112A2), SH_UNT_PU_NPU2 , SH_ACS_SCOM ); -REG64( PU_NPU0_ECC_ERRINJ , RULL(0x050110A1), SH_UNT_PU_NPU0 , SH_ACS_SCOM ); -REG64( PU_NPU1_ECC_ERRINJ , RULL(0x050111A1), SH_UNT_PU_NPU1 , SH_ACS_SCOM ); -REG64( PU_NPU2_ECC_ERRINJ , RULL(0x050112A1), SH_UNT_PU_NPU2 , SH_ACS_SCOM ); - REG64( PU_OTPROM0_ECID_PART0_REGISTER , RULL(0x00018000), SH_UNT_PU_OTPROM0, SH_ACS_SCOM ); REG64( PU_OTPROM1_ECID_PART0_REGISTER , RULL(0x00018040), SH_UNT_PU_OTPROM1, @@ -2922,29 +3289,29 @@ REG64( PU_EHHCA_FIR_REG , RULL(0x05012980 REG64( PU_EHHCA_FIR_REG_AND , RULL(0x05012981), SH_UNT , SH_ACS_SCOM1_AND ); REG64( PU_EHHCA_FIR_REG_OR , RULL(0x05012982), SH_UNT , SH_ACS_SCOM2_OR ); -REG64( PU_NPU0_SM0_EPSILON_CONFIG , RULL(0x05011004), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM0_EPSILON_CONFIG , RULL(0x05011002), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_EPSILON_CONFIG , RULL(0x05011024), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_EPSILON_CONFIG , RULL(0x05011022), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_EPSILON_CONFIG , RULL(0x05011044), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_EPSILON_CONFIG , RULL(0x05011042), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_EPSILON_CONFIG , RULL(0x05011064), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_EPSILON_CONFIG , RULL(0x05011062), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_EPSILON_CONFIG , RULL(0x05011104), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_EPSILON_CONFIG , RULL(0x05011102), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_EPSILON_CONFIG , RULL(0x05011124), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_EPSILON_CONFIG , RULL(0x05011122), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_EPSILON_CONFIG , RULL(0x05011144), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_EPSILON_CONFIG , RULL(0x05011142), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_EPSILON_CONFIG , RULL(0x05011164), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_EPSILON_CONFIG , RULL(0x05011162), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_EPSILON_CONFIG , RULL(0x05011204), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_EPSILON_CONFIG , RULL(0x05011202), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_EPSILON_CONFIG , RULL(0x05011224), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_EPSILON_CONFIG , RULL(0x05011222), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_EPSILON_CONFIG , RULL(0x05011244), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_EPSILON_CONFIG , RULL(0x05011242), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_EPSILON_CONFIG , RULL(0x05011264), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_EPSILON_CONFIG , RULL(0x05011262), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); REG64( PU_ERAT_STATUS_CONTROL , RULL(0x020110D6), SH_UNT , SH_ACS_SCOM ); @@ -2952,15 +3319,31 @@ REG64( PU_ERAT_STATUS_CONTROL , RULL(0x020110D6 REG64( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG , RULL(0x05011394), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM ); +REG64( PEC_ERROR_REG , RULL(0x0D0F001F), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_ERROR_STATUS , RULL(0x0D03000F), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( CAPP_ERRRPT , RULL(0x0201080B), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_ERRRPT , RULL(0x0201080B), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_ERRRPT , RULL(0x0401080B), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + REG64( PU_NPU_SM2_ERR_FIRST , RULL(0x05011343), SH_UNT_PU_NPU_SM2, SH_ACS_SCOM ); REG64( PU_NPU_SM2_ERR_HOLD , RULL(0x05011340), SH_UNT_PU_NPU_SM2, SH_ACS_SCOM ); +REG64( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR , RULL(0x05011392), SH_UNT_PU_NPU_CTL, + SH_ACS_SCOM ); + REG64( PU_NPU_SM2_ERR_MASK , RULL(0x05011342), SH_UNT_PU_NPU_SM2, SH_ACS_SCOM ); +REG64( PU_NPU_CTL_ERR_SCOPE_CTL_CONFIG , RULL(0x05011391), SH_UNT_PU_NPU_CTL, + SH_ACS_SCOM ); + +REG64( PEC_ERR_STATUS_REG , RULL(0x0D050013), SH_UNT_PEC , SH_ACS_SCOM_RO ); + REG64( PU_ESB_CI_BASE , RULL(0x05012916), SH_UNT , SH_ACS_SCOM ); REG64( PU_ESB_NOTIFY , RULL(0x05012917), SH_UNT , SH_ACS_SCOM ); @@ -2984,6 +3367,28 @@ REG64( PU_NPU_CTL_FENCE_1_CONFIG , RULL(0x0501138B REG64( PU_NPU_CTL_FENCE_STATE , RULL(0x05011396), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM ); +REG64( PU_FI2C_CFG_PPE , RULL(0xC0000800), SH_UNT , SH_ACS_PPE ); +REG64( PU_FI2C_CFG_PPE1 , RULL(0xC0000810), SH_UNT , SH_ACS_PPE1 ); +REG64( PU_FI2C_CFG_PPE2 , RULL(0xC0000818), SH_UNT , SH_ACS_PPE2 ); + +REG64( PU_FI2C_SCFG0_PPE , RULL(0xC0000860), SH_UNT , SH_ACS_PPE ); +REG64( PU_FI2C_SCFG0_PPE1 , RULL(0xC0000870), SH_UNT , SH_ACS_PPE1 ); +REG64( PU_FI2C_SCFG0_PPE2 , RULL(0xC0000878), SH_UNT , SH_ACS_PPE2 ); + +REG64( PU_FI2C_SCFG1_PPE , RULL(0xC0000880), SH_UNT , SH_ACS_PPE ); +REG64( PU_FI2C_SCFG1_PPE1 , RULL(0xC0000890), SH_UNT , SH_ACS_PPE1 ); +REG64( PU_FI2C_SCFG1_PPE2 , RULL(0xC0000898), SH_UNT , SH_ACS_PPE2 ); + +REG64( PU_FI2C_SCFG2_PPE , RULL(0xC00008A0), SH_UNT , SH_ACS_PPE ); +REG64( PU_FI2C_SCFG2_PPE1 , RULL(0xC00008B0), SH_UNT , SH_ACS_PPE1 ); +REG64( PU_FI2C_SCFG2_PPE2 , RULL(0xC00008B8), SH_UNT , SH_ACS_PPE2 ); + +REG64( PU_FI2C_SCFG3_PPE , RULL(0xC00008C0), SH_UNT , SH_ACS_PPE ); +REG64( PU_FI2C_SCFG3_PPE1 , RULL(0xC00008D0), SH_UNT , SH_ACS_PPE1 ); +REG64( PU_FI2C_SCFG3_PPE2 , RULL(0xC00008D8), SH_UNT , SH_ACS_PPE2 ); + +REG64( PU_FI2C_STAT_PPE , RULL(0xC0000820), SH_UNT , SH_ACS_PPE ); + REG64( PU_FIFO1_REGISTER_READ_B , RULL(0x000A0004), SH_UNT , SH_ACS_SCOM ); REG64( PU_FIFO1_REGISTER_READ_C , RULL(0x000A1004), SH_UNT , SH_ACS_SCOM ); @@ -3001,43 +3406,45 @@ REG64( PU_FIFO4_REGISTER_READ_D , RULL(0x000A2012 REG64( PU_FIFO4_REGISTER_READ_E , RULL(0x000A3012), SH_UNT , SH_ACS_SCOM ); REG64( PU_FIR_ACTION0_REG , RULL(0x04011806), SH_UNT , SH_ACS_SCOM_RW ); +REG64( CAPP_FIR_ACTION0_REG , RULL(0x02010806), SH_UNT_CAPP , SH_ACS_SCOM_RO ); +REG64( CAPP_0_FIR_ACTION0_REG , RULL(0x02010806), SH_UNT_CAPP_0 , SH_ACS_SCOM_RO ); +REG64( CAPP_1_FIR_ACTION0_REG , RULL(0x04010806), SH_UNT_CAPP_1 , SH_ACS_SCOM_RO ); REG64( PEC_FIR_ACTION0_REG , RULL(0x0D010C06), SH_UNT_PEC , SH_ACS_SCOM_RO ); -REG64( PEC_0_FIR_ACTION0_REG , RULL(0x0D010C06), SH_UNT_PEC_0 , SH_ACS_SCOM_RO ); -REG64( PEC_1_FIR_ACTION0_REG , RULL(0x0E010C06), SH_UNT_PEC_1 , SH_ACS_SCOM_RO ); -REG64( PEC_2_FIR_ACTION0_REG , RULL(0x0F010C06), SH_UNT_PEC_2 , SH_ACS_SCOM_RO ); REG64( _SM0_FIR_ACTION0_REG_0 , RULL(0x05011406), SH_UNT__SM0 , SH_ACS_SCOM_RW ); REG64( _SM2_FIR_ACTION0_REG_1 , RULL(0x05011446), SH_UNT__SM2 , SH_ACS_SCOM_RW ); REG64( PU_FIR_ACTION1_REG , RULL(0x04011807), SH_UNT , SH_ACS_SCOM_RW ); +REG64( CAPP_FIR_ACTION1_REG , RULL(0x02010807), SH_UNT_CAPP , SH_ACS_SCOM_RO ); +REG64( CAPP_0_FIR_ACTION1_REG , RULL(0x02010807), SH_UNT_CAPP_0 , SH_ACS_SCOM_RO ); +REG64( CAPP_1_FIR_ACTION1_REG , RULL(0x04010807), SH_UNT_CAPP_1 , SH_ACS_SCOM_RO ); REG64( PEC_FIR_ACTION1_REG , RULL(0x0D010C07), SH_UNT_PEC , SH_ACS_SCOM_RO ); -REG64( PEC_0_FIR_ACTION1_REG , RULL(0x0D010C07), SH_UNT_PEC_0 , SH_ACS_SCOM_RO ); -REG64( PEC_1_FIR_ACTION1_REG , RULL(0x0E010C07), SH_UNT_PEC_1 , SH_ACS_SCOM_RO ); -REG64( PEC_2_FIR_ACTION1_REG , RULL(0x0F010C07), SH_UNT_PEC_2 , SH_ACS_SCOM_RO ); REG64( _SM0_FIR_ACTION1_REG_0 , RULL(0x05011407), SH_UNT__SM0 , SH_ACS_SCOM_RW ); REG64( _SM2_FIR_ACTION1_REG_1 , RULL(0x05011447), SH_UNT__SM2 , SH_ACS_SCOM_RW ); +REG64( PEC_FIR_MASK , RULL(0x0D040002), SH_UNT_PEC , SH_ACS_SCOM ); + REG64( PU_FIR_MASK_REG , RULL(0x04011803), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_FIR_MASK_REG_AND , RULL(0x04011804), SH_UNT , SH_ACS_SCOM1_AND ); REG64( PU_FIR_MASK_REG_OR , RULL(0x04011805), SH_UNT , SH_ACS_SCOM2_OR ); +REG64( CAPP_FIR_MASK_REG , RULL(0x02010803), SH_UNT_CAPP , SH_ACS_SCOM_RW ); +REG64( CAPP_FIR_MASK_REG_AND , RULL(0x02010804), SH_UNT_CAPP , SH_ACS_SCOM1_AND ); +REG64( CAPP_FIR_MASK_REG_OR , RULL(0x02010805), SH_UNT_CAPP , SH_ACS_SCOM2_OR ); +REG64( CAPP_0_FIR_MASK_REG , RULL(0x02010803), SH_UNT_CAPP_0 , SH_ACS_SCOM_RW ); +REG64( CAPP_0_FIR_MASK_REG_AND , RULL(0x02010804), SH_UNT_CAPP_0 , SH_ACS_SCOM1_AND ); +REG64( CAPP_0_FIR_MASK_REG_OR , RULL(0x02010805), SH_UNT_CAPP_0 , SH_ACS_SCOM2_OR ); +REG64( CAPP_1_FIR_MASK_REG , RULL(0x04010803), SH_UNT_CAPP_1 , SH_ACS_SCOM_RW ); +REG64( CAPP_1_FIR_MASK_REG_AND , RULL(0x04010804), SH_UNT_CAPP_1 , SH_ACS_SCOM1_AND ); +REG64( CAPP_1_FIR_MASK_REG_OR , RULL(0x04010805), SH_UNT_CAPP_1 , SH_ACS_SCOM2_OR ); REG64( PEC_FIR_MASK_REG , RULL(0x0D010C03), SH_UNT_PEC , SH_ACS_SCOM_RW ); REG64( PEC_FIR_MASK_REG_AND , RULL(0x0D010C04), SH_UNT_PEC , SH_ACS_SCOM1_AND ); REG64( PEC_FIR_MASK_REG_OR , RULL(0x0D010C05), SH_UNT_PEC , SH_ACS_SCOM2_OR ); -REG64( PEC_0_FIR_MASK_REG , RULL(0x0D010C03), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); -REG64( PEC_0_FIR_MASK_REG_AND , RULL(0x0D010C04), SH_UNT_PEC_0 , SH_ACS_SCOM1_AND ); -REG64( PEC_0_FIR_MASK_REG_OR , RULL(0x0D010C05), SH_UNT_PEC_0 , SH_ACS_SCOM2_OR ); -REG64( PEC_1_FIR_MASK_REG , RULL(0x0E010C03), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); -REG64( PEC_1_FIR_MASK_REG_AND , RULL(0x0E010C04), SH_UNT_PEC_1 , SH_ACS_SCOM1_AND ); -REG64( PEC_1_FIR_MASK_REG_OR , RULL(0x0E010C05), SH_UNT_PEC_1 , SH_ACS_SCOM2_OR ); -REG64( PEC_2_FIR_MASK_REG , RULL(0x0F010C03), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); -REG64( PEC_2_FIR_MASK_REG_AND , RULL(0x0F010C04), SH_UNT_PEC_2 , SH_ACS_SCOM1_AND ); -REG64( PEC_2_FIR_MASK_REG_OR , RULL(0x0F010C05), SH_UNT_PEC_2 , SH_ACS_SCOM2_OR ); REG64( PU_FIR_MASK_REGISTER , RULL(0x00088008), SH_UNT , SH_ACS_SCOM ); @@ -3052,6 +3459,15 @@ REG64( _SM2_FIR_MASK_REG_1_OR , RULL(0x05011445 REG64( PU_FIR_REG , RULL(0x04011800), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_FIR_REG_AND , RULL(0x04011801), SH_UNT , SH_ACS_SCOM1_AND ); REG64( PU_FIR_REG_OR , RULL(0x04011802), SH_UNT , SH_ACS_SCOM2_OR ); +REG64( CAPP_FIR_REG , RULL(0x02010800), SH_UNT_CAPP , SH_ACS_SCOM_RW ); +REG64( CAPP_FIR_REG_AND , RULL(0x02010801), SH_UNT_CAPP , SH_ACS_SCOM1_AND ); +REG64( CAPP_FIR_REG_OR , RULL(0x02010802), SH_UNT_CAPP , SH_ACS_SCOM2_OR ); +REG64( CAPP_0_FIR_REG , RULL(0x02010800), SH_UNT_CAPP_0 , SH_ACS_SCOM_RW ); +REG64( CAPP_0_FIR_REG_AND , RULL(0x02010801), SH_UNT_CAPP_0 , SH_ACS_SCOM1_AND ); +REG64( CAPP_0_FIR_REG_OR , RULL(0x02010802), SH_UNT_CAPP_0 , SH_ACS_SCOM2_OR ); +REG64( CAPP_1_FIR_REG , RULL(0x04010800), SH_UNT_CAPP_1 , SH_ACS_SCOM_RW ); +REG64( CAPP_1_FIR_REG_AND , RULL(0x04010801), SH_UNT_CAPP_1 , SH_ACS_SCOM1_AND ); +REG64( CAPP_1_FIR_REG_OR , RULL(0x04010802), SH_UNT_CAPP_1 , SH_ACS_SCOM2_OR ); REG64( _SM0_FIR_REG_0 , RULL(0x05011400), SH_UNT__SM0 , SH_ACS_SCOM_RW ); REG64( _SM0_FIR_REG_0_AND , RULL(0x05011401), SH_UNT__SM0 , SH_ACS_SCOM1_AND ); @@ -3064,26 +3480,11 @@ REG64( _SM2_FIR_REG_1_OR , RULL(0x05011442 REG64( PEC_FIR_STATUS_REG , RULL(0x0D010C00), SH_UNT_PEC , SH_ACS_SCOM_RW ); REG64( PEC_FIR_STATUS_REG_AND , RULL(0x0D010C01), SH_UNT_PEC , SH_ACS_SCOM1_AND ); REG64( PEC_FIR_STATUS_REG_OR , RULL(0x0D010C02), SH_UNT_PEC , SH_ACS_SCOM2_OR ); -REG64( PEC_0_FIR_STATUS_REG , RULL(0x0D010C00), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); -REG64( PEC_0_FIR_STATUS_REG_AND , RULL(0x0D010C01), SH_UNT_PEC_0 , SH_ACS_SCOM1_AND ); -REG64( PEC_0_FIR_STATUS_REG_OR , RULL(0x0D010C02), SH_UNT_PEC_0 , SH_ACS_SCOM2_OR ); -REG64( PEC_1_FIR_STATUS_REG , RULL(0x0E010C00), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); -REG64( PEC_1_FIR_STATUS_REG_AND , RULL(0x0E010C01), SH_UNT_PEC_1 , SH_ACS_SCOM1_AND ); -REG64( PEC_1_FIR_STATUS_REG_OR , RULL(0x0E010C02), SH_UNT_PEC_1 , SH_ACS_SCOM2_OR ); -REG64( PEC_2_FIR_STATUS_REG , RULL(0x0F010C00), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); -REG64( PEC_2_FIR_STATUS_REG_AND , RULL(0x0F010C01), SH_UNT_PEC_2 , SH_ACS_SCOM1_AND ); -REG64( PEC_2_FIR_STATUS_REG_OR , RULL(0x0F010C02), SH_UNT_PEC_2 , SH_ACS_SCOM2_OR ); REG64( PU_FIR_WOF_REG , RULL(0x04011808), SH_UNT , SH_ACS_SCOM_WCLRREG ); REG64( PEC_FIR_WOF_REG , RULL(0x0D010C08), SH_UNT_PEC , SH_ACS_SCOM_WCLRREG ); -REG64( PEC_0_FIR_WOF_REG , RULL(0x0D010C08), SH_UNT_PEC_0 , - SH_ACS_SCOM_WCLRREG ); -REG64( PEC_1_FIR_WOF_REG , RULL(0x0E010C08), SH_UNT_PEC_1 , - SH_ACS_SCOM_WCLRREG ); -REG64( PEC_2_FIR_WOF_REG , RULL(0x0F010C08), SH_UNT_PEC_2 , - SH_ACS_SCOM_WCLRREG ); REG64( _SM0_FIR_WOF_REG_0 , RULL(0x05011408), SH_UNT__SM0 , SH_ACS_SCOM_WCLRREG ); @@ -3091,6 +3492,14 @@ REG64( _SM0_FIR_WOF_REG_0 , RULL(0x05011408 REG64( _SM2_FIR_WOF_REG_1 , RULL(0x05011448), SH_UNT__SM2 , SH_ACS_SCOM_WCLRREG ); +REG64( CAPP_FLUSHCPIG , RULL(0x02010820), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_FLUSHCPIG , RULL(0x02010820), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_FLUSHCPIG , RULL(0x04010820), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_FLUSHSHUE , RULL(0x0201080F), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_FLUSHSHUE , RULL(0x0201080F), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_FLUSHSHUE , RULL(0x0401080F), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + REG64( PU_NPU_CTL_FREEZE_0_CONFIG , RULL(0x05011388), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM ); @@ -3116,29 +3525,29 @@ REG64( PU_FSB_UPFIFO_RESET , RULL(0x000B0004 REG64( PU_FSB_UPFIFO_STATUS , RULL(0x000B0001), SH_UNT , SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_GENID_BAR , RULL(0x05011011), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM0_GENID_BAR , RULL(0x05011007), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_GENID_BAR , RULL(0x05011031), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_GENID_BAR , RULL(0x05011027), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_GENID_BAR , RULL(0x05011051), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_GENID_BAR , RULL(0x05011047), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_GENID_BAR , RULL(0x05011071), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_GENID_BAR , RULL(0x05011067), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_GENID_BAR , RULL(0x05011111), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_GENID_BAR , RULL(0x05011107), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_GENID_BAR , RULL(0x05011131), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_GENID_BAR , RULL(0x05011127), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_GENID_BAR , RULL(0x05011151), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_GENID_BAR , RULL(0x05011147), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_GENID_BAR , RULL(0x05011171), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_GENID_BAR , RULL(0x05011167), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_GENID_BAR , RULL(0x05011211), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_GENID_BAR , RULL(0x05011207), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_GENID_BAR , RULL(0x05011231), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_GENID_BAR , RULL(0x05011227), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_GENID_BAR , RULL(0x05011251), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_GENID_BAR , RULL(0x05011247), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_GENID_BAR , RULL(0x05011271), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_GENID_BAR , RULL(0x05011267), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); REG64( PU_GPE0_GPEDBG_OCI , RULL(0xC0000010), SH_UNT , SH_ACS_OCI ); @@ -3183,8 +3592,6 @@ REG64( PU_GPE0_MIB_XIMEM , RULL(0x00060017 REG64( PU_GPE0_MIB_XISGB , RULL(0x00060018), SH_UNT , SH_ACS_SCOM_RO ); -REG64( PU_GPE0_MIB_XISIB , RULL(0x00060016), SH_UNT , SH_ACS_SCOM_RO ); - REG64( PU_GPE0_PPE_XIDBGPRO , RULL(0x00060015), SH_UNT , SH_ACS_SCOM ); REG64( PU_GPE0_PPE_XIRAMDBG , RULL(0x00060013), SH_UNT , SH_ACS_SCOM ); @@ -3239,8 +3646,6 @@ REG64( PU_GPE1_MIB_XIMEM , RULL(0x00062017 REG64( PU_GPE1_MIB_XISGB , RULL(0x00062018), SH_UNT , SH_ACS_SCOM_RO ); -REG64( PU_GPE1_MIB_XISIB , RULL(0x00062016), SH_UNT , SH_ACS_SCOM_RO ); - REG64( PU_GPE1_PPE_XIDBGPRO , RULL(0x00062015), SH_UNT , SH_ACS_SCOM ); REG64( PU_GPE1_PPE_XIRAMDBG , RULL(0x00062013), SH_UNT , SH_ACS_SCOM ); @@ -3295,8 +3700,6 @@ REG64( PU_GPE2_MIB_XIMEM , RULL(0x00064017 REG64( PU_GPE2_MIB_XISGB , RULL(0x00064018), SH_UNT , SH_ACS_SCOM_RO ); -REG64( PU_GPE2_MIB_XISIB , RULL(0x00064016), SH_UNT , SH_ACS_SCOM_RO ); - REG64( PU_GPE2_PPE_XIDBGPRO , RULL(0x00064015), SH_UNT , SH_ACS_SCOM ); REG64( PU_GPE2_PPE_XIRAMDBG , RULL(0x00064013), SH_UNT , SH_ACS_SCOM ); @@ -3351,8 +3754,6 @@ REG64( PU_GPE3_MIB_XIMEM , RULL(0x00066017 REG64( PU_GPE3_MIB_XISGB , RULL(0x00066018), SH_UNT , SH_ACS_SCOM_RO ); -REG64( PU_GPE3_MIB_XISIB , RULL(0x00066016), SH_UNT , SH_ACS_SCOM_RO ); - REG64( PU_GPE3_PPE_XIDBGPRO , RULL(0x00066015), SH_UNT , SH_ACS_SCOM ); REG64( PU_GPE3_PPE_XIRAMDBG , RULL(0x00066013), SH_UNT , SH_ACS_SCOM ); @@ -3365,55 +3766,38 @@ REG64( PU_GPE3_PPE_XIRAMRA , RULL(0x00066011 REG64( PU_GPE3_PPE_XIXCR , RULL(0x00066010), SH_UNT , SH_ACS_SCOM_WO ); -REG64( PU_NPU0_SM0_GPU0_BAR , RULL(0x0501100B), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM0_GPU_BAR , RULL(0x05011004), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_GPU0_BAR , RULL(0x0501102B), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_GPU_BAR , RULL(0x05011024), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_GPU0_BAR , RULL(0x0501104B), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_GPU_BAR , RULL(0x05011044), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_GPU0_BAR , RULL(0x0501106B), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_GPU_BAR , RULL(0x05011064), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_GPU0_BAR , RULL(0x0501110B), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_GPU_BAR , RULL(0x05011104), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_GPU0_BAR , RULL(0x0501112B), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_GPU_BAR , RULL(0x05011124), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_GPU0_BAR , RULL(0x0501114B), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_GPU_BAR , RULL(0x05011144), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_GPU0_BAR , RULL(0x0501116B), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_GPU_BAR , RULL(0x05011164), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_GPU0_BAR , RULL(0x0501120B), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_GPU_BAR , RULL(0x05011204), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_GPU0_BAR , RULL(0x0501122B), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_GPU_BAR , RULL(0x05011224), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_GPU0_BAR , RULL(0x0501124B), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_GPU_BAR , RULL(0x05011244), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_GPU0_BAR , RULL(0x0501126B), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_GPU_BAR , RULL(0x05011264), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_GPU1_BAR , RULL(0x0501100C), SH_UNT_PU_NPU0_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_GPU1_BAR , RULL(0x0501102C), SH_UNT_PU_NPU0_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_GPU1_BAR , RULL(0x0501104C), SH_UNT_PU_NPU0_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_GPU1_BAR , RULL(0x0501106C), SH_UNT_PU_NPU0_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_GPU1_BAR , RULL(0x0501110C), SH_UNT_PU_NPU1_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_GPU1_BAR , RULL(0x0501112C), SH_UNT_PU_NPU1_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_GPU1_BAR , RULL(0x0501114C), SH_UNT_PU_NPU1_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_GPU1_BAR , RULL(0x0501116C), SH_UNT_PU_NPU1_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_GPU1_BAR , RULL(0x0501120C), SH_UNT_PU_NPU2_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_GPU1_BAR , RULL(0x0501122C), SH_UNT_PU_NPU2_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_GPU1_BAR , RULL(0x0501124C), SH_UNT_PU_NPU2_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_GPU1_BAR , RULL(0x0501126C), SH_UNT_PU_NPU2_SM3, - SH_ACS_SCOM ); +REG64( PEC_GXSTOP0_MASK_REG , RULL(0x0D040014), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_GXSTOP1_MASK_REG , RULL(0x0D040015), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_GXSTOP2_MASK_REG , RULL(0x0D040016), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_GXSTOP_TRIG_REG , RULL(0x0D040013), SH_UNT_PEC , SH_ACS_SCOM ); REG64( PU_GZIP_CONTROL_REG , RULL(0x02011140), SH_UNT , SH_ACS_SCOM ); @@ -3433,6 +3817,20 @@ REG64( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL , RULL(0x020110CE REG64( PU_GZIP_MAX_BYTE_CNT , RULL(0x0201105B), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PEC_HANG_PULSE_0_REG , RULL(0x0D0F0020), SH_UNT_PEC , SH_ACS_SCOM_RW ); + +REG64( PEC_HANG_PULSE_1_REG , RULL(0x0D0F0021), SH_UNT_PEC , SH_ACS_SCOM_RW ); + +REG64( PEC_HANG_PULSE_2_REG , RULL(0x0D0F0022), SH_UNT_PEC , SH_ACS_SCOM_RW ); + +REG64( PEC_HANG_PULSE_3_REG , RULL(0x0D0F0023), SH_UNT_PEC , SH_ACS_SCOM_RW ); + +REG64( PEC_HANG_PULSE_4_REG , RULL(0x0D0F0024), SH_UNT_PEC , SH_ACS_SCOM_RW ); + +REG64( PEC_HANG_PULSE_5_REG , RULL(0x0D0F0025), SH_UNT_PEC , SH_ACS_SCOM_RW ); + +REG64( PEC_HANG_PULSE_6_REG , RULL(0x0D0F0026), SH_UNT_PEC , SH_ACS_SCOM_RW ); + REG64( PU_HCA_BAR , RULL(0x0501298A), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_HCA_COUNT_BAR , RULL(0x0501298B), SH_UNT , SH_ACS_SCOM_RW ); @@ -3449,31 +3847,37 @@ REG64( PU_HCA_REF_BAR , RULL(0x0501298E REG64( PU_HCA_RESET , RULL(0x05012992), SH_UNT , SH_ACS_SCOM_W ); -REG64( PU_NPU0_SM0_HIGH_WATER , RULL(0x05011015), SH_UNT_PU_NPU0_SM0, +REG64( PEC_HEARTBEAT_REG , RULL(0x0D0F0018), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_NPU0_SM0_HIGH_WATER , RULL(0x05011009), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_HIGH_WATER , RULL(0x05011035), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_HIGH_WATER , RULL(0x05011029), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_HIGH_WATER , RULL(0x05011055), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_HIGH_WATER , RULL(0x05011049), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_HIGH_WATER , RULL(0x05011075), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_HIGH_WATER , RULL(0x05011069), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_HIGH_WATER , RULL(0x05011115), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_HIGH_WATER , RULL(0x05011109), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_HIGH_WATER , RULL(0x05011135), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_HIGH_WATER , RULL(0x05011129), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_HIGH_WATER , RULL(0x05011155), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_HIGH_WATER , RULL(0x05011149), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_HIGH_WATER , RULL(0x05011175), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_HIGH_WATER , RULL(0x05011169), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_HIGH_WATER , RULL(0x05011215), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_HIGH_WATER , RULL(0x05011209), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_HIGH_WATER , RULL(0x05011235), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_HIGH_WATER , RULL(0x05011229), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_HIGH_WATER , RULL(0x05011255), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_HIGH_WATER , RULL(0x05011249), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_HIGH_WATER , RULL(0x05011275), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_HIGH_WATER , RULL(0x05011269), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); +REG64( PEC_HOSTATTN , RULL(0x0D040009), SH_UNT_PEC , SH_ACS_SCOM_RO ); + +REG64( PEC_HOSTATTN_MASK , RULL(0x0D040020), SH_UNT_PEC , SH_ACS_SCOM ); + REG64( PU_HTM0_HTM_CFG , RULL(0x05012888), SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW ); REG64( PU_HTM1_HTM_CFG , RULL(0x050128C8), SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW ); @@ -3570,33 +3974,43 @@ REG64( PU_NPU1_CTL_INHIBIT_CONFIG , RULL(0x05011191 SH_ACS_SCOM ); REG64( PU_NPU2_CTL_INHIBIT_CONFIG , RULL(0x05011291), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_INHIBIT_CONFIG , RULL(0x05011018), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM0_INHIBIT_CONFIG , RULL(0x05011010), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_INHIBIT_CONFIG , RULL(0x05011038), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_INHIBIT_CONFIG , RULL(0x05011030), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_INHIBIT_CONFIG , RULL(0x05011058), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_INHIBIT_CONFIG , RULL(0x05011050), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_INHIBIT_CONFIG , RULL(0x05011078), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_INHIBIT_CONFIG , RULL(0x05011070), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_INHIBIT_CONFIG , RULL(0x05011118), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_INHIBIT_CONFIG , RULL(0x05011110), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_INHIBIT_CONFIG , RULL(0x05011138), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_INHIBIT_CONFIG , RULL(0x05011130), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_INHIBIT_CONFIG , RULL(0x05011158), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_INHIBIT_CONFIG , RULL(0x05011150), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_INHIBIT_CONFIG , RULL(0x05011178), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_INHIBIT_CONFIG , RULL(0x05011170), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_INHIBIT_CONFIG , RULL(0x05011218), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_INHIBIT_CONFIG , RULL(0x05011210), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_INHIBIT_CONFIG , RULL(0x05011238), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_INHIBIT_CONFIG , RULL(0x05011230), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_INHIBIT_CONFIG , RULL(0x05011258), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_INHIBIT_CONFIG , RULL(0x05011250), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_INHIBIT_CONFIG , RULL(0x05011278), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_INHIBIT_CONFIG , RULL(0x05011270), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); REG64( PU_NPU_CTL_INHIBIT_CONFIG , RULL(0x05011387), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM ); +REG64( PEC_INJECT_REG , RULL(0x0D050011), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PHB_INTBAR_REG , RULL(0x04010C53), SH_UNT_PHB , SH_ACS_SCOM ); +REG64( PHB_0_INTBAR_REG , RULL(0x04010C53), SH_UNT_PHB_0 , SH_ACS_SCOM ); +REG64( PHB_1_INTBAR_REG , RULL(0x04011053), SH_UNT_PHB_1 , SH_ACS_SCOM ); +REG64( PHB_2_INTBAR_REG , RULL(0x04011093), SH_UNT_PHB_2 , SH_ACS_SCOM ); +REG64( PHB_3_INTBAR_REG , RULL(0x04011453), SH_UNT_PHB_3 , SH_ACS_SCOM ); +REG64( PHB_4_INTBAR_REG , RULL(0x04011493), SH_UNT_PHB_4 , SH_ACS_SCOM ); +REG64( PHB_5_INTBAR_REG , RULL(0x040114D3), SH_UNT_PHB_5 , SH_ACS_SCOM ); + REG64( PU_INTERRUPTS_B , RULL(0x000A000A), SH_UNT , SH_ACS_SCOM ); REG64( PU_INTERRUPTS_C , RULL(0x000A100A), SH_UNT , SH_ACS_SCOM ); @@ -3646,6 +4060,10 @@ REG64( PU_NPU_CTL_INT_1_CONFIG , RULL(0x0501138D REG64( PU_NPU_CTL_INT_BAR , RULL(0x05011393), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM ); +REG64( PU_INT_CQ_ACTION0 , RULL(0x05013036), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_CQ_ACTION1 , RULL(0x05013037), SH_UNT , SH_ACS_SCOM_RW ); + REG64( PU_INT_CQ_AIB_CTL , RULL(0x05013022), SH_UNT , SH_ACS_SCOM ); REG64( PU_INT_CQ_CFG_LDQ , RULL(0x05013026), SH_UNT , SH_ACS_SCOM_RW ); @@ -3672,6 +4090,10 @@ REG64( PU_INT_CQ_ERR_INFO3 , RULL(0x0501303D REG64( PU_INT_CQ_ERR_RPT_HOLD , RULL(0x05013039), SH_UNT , SH_ACS_SCOM_RO ); +REG64( PU_INT_CQ_FIR , RULL(0x05013030), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_CQ_FIRMASK , RULL(0x05013033), SH_UNT , SH_ACS_SCOM_RW ); + REG64( PU_INT_CQ_IC_BAR , RULL(0x05013010), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_INT_CQ_MSGSND , RULL(0x0501300B), SH_UNT , SH_ACS_SCOM_RW ); @@ -3764,63 +4186,138 @@ REG64( PU_NPU_NTL1_INT_LOG_PE8 , RULL(0x050113E8 REG64( PU_NPU_NTL1_INT_LOG_PE9 , RULL(0x050113E9), SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM ); -REG64( PU_INT_PC_AIB_MAX_CMD_CRD_REG , RULL(0x05013129), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_AIB_RX_CRD_CMD , RULL(0x05013129), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_AIB_RX_CRD_DAT , RULL(0x0501312A), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_AIB_RX_CRD_INIT , RULL(0x05013128), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_AIB_MAX_DAT_CRD_REG , RULL(0x0501312A), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_AIB_TX_CRD , RULL(0x0501312C), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_CRD_INIT_TIMER , RULL(0x05013128), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_AIB_TX_ORDER , RULL(0x0501312E), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_GEN_CFG , RULL(0x0501312B), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_AIB_TX_PRIO , RULL(0x0501312D), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_INDIR0_REG , RULL(0x05013103), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_AT_KILL , RULL(0x05013116), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_INDIR1_REG , RULL(0x05013104), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_AT_KILL_MASK , RULL(0x05013117), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_INDIR2_REG , RULL(0x05013105), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_EQD_BLOCK_MODE , RULL(0x05013114), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_INDIR3_REG , RULL(0x05013106), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_GLOBAL_CFG , RULL(0x05013110), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_MMIO_ARB_CFG , RULL(0x05013125), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_IVE_BLOCK_MODE , RULL(0x05013113), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_PCMD_ARB_CFG , RULL(0x05013120), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_MMIO_ARB , RULL(0x0501311A), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_REGS_ERR_CFG_REG0 , RULL(0x05013130), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_PCMD_ARB , RULL(0x05013118), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_REGS_ERR_CFG_REG1 , RULL(0x05013131), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_REGS_ERR_CFG_REG0 , RULL(0x05013140), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_REGS_FATAL_ERR , RULL(0x05013133), SH_UNT , +REG64( PU_INT_PC_REGS_ERR_CFG_REG1 , RULL(0x05013141), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_REGS_FATAL_ERR , RULL(0x05013144), SH_UNT , SH_ACS_SCOM_CLRPART ); -REG64( PU_INT_PC_REGS_INFO_ERR , RULL(0x05013134), SH_UNT , +REG64( PU_INT_PC_REGS_INFO_ERR , RULL(0x05013146), SH_UNT , SH_ACS_SCOM_CLRPART ); -REG64( PU_INT_PC_REGS_RECOV_ERR , RULL(0x05013135), SH_UNT , +REG64( PU_INT_PC_REGS_RECOV_ERR , RULL(0x05013145), SH_UNT , SH_ACS_SCOM_CLRPART ); -REG64( PU_INT_PC_REGS_WOF_ERR , RULL(0x05013132), SH_UNT , +REG64( PU_INT_PC_REGS_WOF_ERR , RULL(0x05013142), SH_UNT , SH_ACS_SCOM_CLRPART ); -REG64( PU_INT_PC_REGS_WOF_ERR_DETAIL , RULL(0x05013136), SH_UNT , SH_ACS_SCOM_RO ); +REG64( PU_INT_PC_REGS_WOF_ERR_DETAIL , RULL(0x05013143), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_INT_PC_VPC_ADDITIONAL_PERF_1 , RULL(0x05013174), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_INT_PC_VPC_ADDITIONAL_PERF_2 , RULL(0x05013175), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_INT_PC_VPC_CACHE_EN , RULL(0x05013161), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA0 , RULL(0x05013168), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA2 , RULL(0x0501316A), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA3 , RULL(0x0501316B), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA4 , RULL(0x0501316C), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA6 , RULL(0x0501316E), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_CACHE_WATCH_DATA7 , RULL(0x0501316F), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_CACHE_WATCH_SPEC , RULL(0x05013167), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_INT_PC_VPC_CONFIG , RULL(0x05013164), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_DEBUG , RULL(0x05013170), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_ERR_CFG0 , RULL(0x05013178), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_ERR_CFG1 , RULL(0x05013179), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_ERR_CFG_REG , RULL(0x05013148), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_FATAL_ERR , RULL(0x0501314C), SH_UNT , + SH_ACS_SCOM_CLRPART ); //DUPS: 0501317C, + +REG64( PU_INT_PC_VPC_INFO_ERR , RULL(0x0501314E), SH_UNT , + SH_ACS_SCOM_CLRPART ); //DUPS: 0501317E, + +REG64( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD , RULL(0x05013160), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_PERF_EVENT_SEL_1 , RULL(0x05013171), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_PERF_EVENT_SEL_2 , RULL(0x05013172), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_PERF_EVENT_SEL_3 , RULL(0x05013173), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VPC_RECOV_ERR , RULL(0x0501314D), SH_UNT , + SH_ACS_SCOM_CLRPART ); //DUPS: 0501317D, + +REG64( PU_INT_PC_VPC_SCRUB_MASK , RULL(0x05013163), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_TCTXT_CFG_REG , RULL(0x05013100), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_VPC_SCRUB_TRIG , RULL(0x05013162), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_THRD_EN_REG0 , RULL(0x05013101), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_VPC_WOF_ERR , RULL(0x0501314A), SH_UNT , + SH_ACS_SCOM_CLRPART ); //DUPS: 0501317A, -REG64( PU_INT_PC_THRD_EN_REG1 , RULL(0x05013102), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_VPC_WOF_ERR_DETAIL , RULL(0x0501314B), SH_UNT , + SH_ACS_SCOM_RO ); //DUPS: 0501317B, -REG64( PU_INT_PC_VRQ_ARB_CFG , RULL(0x05013123), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_VPD_BLOCK_MODE , RULL(0x05013115), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_VRQ_CRD_CFG , RULL(0x05013124), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_VRQ_CFG , RULL(0x0501311C), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_VRQ_PEND_CFG , RULL(0x05013122), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_VRQ_PEND_ARB , RULL(0x0501311D), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_VRQ_QUE_CFG , RULL(0x05013121), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_VRQ_VPC_ARB , RULL(0x0501311F), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_INT_PC_VSD_TABLE_ADDR , RULL(0x0501312C), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_INT_PC_VRQ_VPC_CRD , RULL(0x0501311E), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_PC_VSD_TABLE_ADDR , RULL(0x05013111), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_NPU_CTL_INT_REQ , RULL(0x05011397), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM ); +REG64( PU_INT_TCTXT_CFG , RULL(0x05013100), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_TCTXT_EN0 , RULL(0x05013108), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_TCTXT_EN1 , RULL(0x0501310C), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_TCTXT_INDIR0 , RULL(0x05013104), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_TCTXT_INDIR1 , RULL(0x05013105), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_TCTXT_INDIR2 , RULL(0x05013106), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_TCTXT_INDIR3 , RULL(0x05013107), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_INT_TCTXT_TRACK , RULL(0x05013101), SH_UNT , SH_ACS_SCOM_RW ); + REG64( PU_INT_VC_AIB_TIMEOUT , RULL(0x0501322B), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_INT_VC_AIB_TX_CMD_PRIORITY , RULL(0x0501323D), SH_UNT , SH_ACS_SCOM_RW ); @@ -4034,6 +4531,90 @@ REG64( PU_JTG_PIB_OJTDO , RULL(0x0006D00D REG64( PU_NPU_CTL_LCO_CONFIG , RULL(0x05011382), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM ); +REG64( CAPP_LINK_DELAY_RESP_DATA0 , RULL(0x02010850), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA0 , RULL(0x02010850), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA0 , RULL(0x04010850), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA1 , RULL(0x02010851), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA1 , RULL(0x02010851), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA1 , RULL(0x04010851), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA10 , RULL(0x0201085A), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA10 , RULL(0x0201085A), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA10 , RULL(0x0401085A), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA11 , RULL(0x0201085B), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA11 , RULL(0x0201085B), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA11 , RULL(0x0401085B), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA12 , RULL(0x0201085C), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA12 , RULL(0x0201085C), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA12 , RULL(0x0401085C), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA13 , RULL(0x0201085D), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA13 , RULL(0x0201085D), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA13 , RULL(0x0401085D), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA14 , RULL(0x0201085E), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA14 , RULL(0x0201085E), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA14 , RULL(0x0401085E), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA15 , RULL(0x0201085F), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA15 , RULL(0x0201085F), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA15 , RULL(0x0401085F), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA2 , RULL(0x02010852), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA2 , RULL(0x02010852), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA2 , RULL(0x04010852), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA3 , RULL(0x02010853), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA3 , RULL(0x02010853), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA3 , RULL(0x04010853), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA4 , RULL(0x02010854), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA4 , RULL(0x02010854), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA4 , RULL(0x04010854), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA5 , RULL(0x02010855), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA5 , RULL(0x02010855), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA5 , RULL(0x04010855), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA6 , RULL(0x02010856), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA6 , RULL(0x02010856), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA6 , RULL(0x04010856), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA7 , RULL(0x02010857), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA7 , RULL(0x02010857), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA7 , RULL(0x04010857), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA8 , RULL(0x02010858), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA8 , RULL(0x02010858), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA8 , RULL(0x04010858), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_RESP_DATA9 , RULL(0x02010859), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_RESP_DATA9 , RULL(0x02010859), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_RESP_DATA9 , RULL(0x04010859), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_LINK_DELAY_TIMER , RULL(0x02010845), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_LINK_DELAY_TIMER , RULL(0x02010845), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_LINK_DELAY_TIMER , RULL(0x04010845), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( PEC_LOCAL_FIR , RULL(0x0D04000A), SH_UNT_PEC , SH_ACS_SCOM_RW ); +REG64( PEC_LOCAL_FIR_AND , RULL(0x0D04000B), SH_UNT_PEC , SH_ACS_SCOM1_AND ); +REG64( PEC_LOCAL_FIR_OR , RULL(0x0D04000C), SH_UNT_PEC , SH_ACS_SCOM2_OR ); + +REG64( PEC_LOCAL_FIR_ACTION0 , RULL(0x0D040010), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_LOCAL_FIR_ACTION1 , RULL(0x0D040011), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_LOCAL_FIR_MASK , RULL(0x0D04000D), SH_UNT_PEC , SH_ACS_SCOM_RW ); +REG64( PEC_LOCAL_FIR_MASK_AND , RULL(0x0D04000E), SH_UNT_PEC , SH_ACS_SCOM1_AND ); +REG64( PEC_LOCAL_FIR_MASK_OR , RULL(0x0D04000F), SH_UNT_PEC , SH_ACS_SCOM2_OR ); + +REG64( PEC_LOCAL_XSTOP_ERR , RULL(0x0D040018), SH_UNT_PEC , SH_ACS_SCOM_RO ); + +REG64( PEC_LOCAL_XSTOP_MASK , RULL(0x0D040019), SH_UNT_PEC , SH_ACS_SCOM ); + REG64( NV_LOW_PWR , RULL(0x050110D8), SH_UNT_NV , SH_ACS_SCOM ); REG64( NV_0_LOW_PWR , RULL(0x050110D8), SH_UNT_NV_0 , SH_ACS_SCOM ); REG64( NV_1_LOW_PWR , RULL(0x050110F8), SH_UNT_NV_1 , SH_ACS_SCOM ); @@ -4044,29 +4625,29 @@ REG64( PU_NPU2_NTL0_LOW_PWR , RULL(0x050112D8 REG64( PU_NPU2_NTL1_LOW_PWR , RULL(0x050112F8), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_LOW_WATER , RULL(0x05011014), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM0_LOW_WATER , RULL(0x05011008), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_LOW_WATER , RULL(0x05011034), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_LOW_WATER , RULL(0x05011028), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_LOW_WATER , RULL(0x05011054), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_LOW_WATER , RULL(0x05011048), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_LOW_WATER , RULL(0x05011074), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_LOW_WATER , RULL(0x05011068), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_LOW_WATER , RULL(0x05011114), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_LOW_WATER , RULL(0x05011108), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_LOW_WATER , RULL(0x05011134), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_LOW_WATER , RULL(0x05011128), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_LOW_WATER , RULL(0x05011154), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_LOW_WATER , RULL(0x05011148), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_LOW_WATER , RULL(0x05011174), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_LOW_WATER , RULL(0x05011168), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_LOW_WATER , RULL(0x05011214), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_LOW_WATER , RULL(0x05011208), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_LOW_WATER , RULL(0x05011234), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_LOW_WATER , RULL(0x05011228), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_LOW_WATER , RULL(0x05011254), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_LOW_WATER , RULL(0x05011248), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_LOW_WATER , RULL(0x05011274), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_LOW_WATER , RULL(0x05011268), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); REG64( PU_NPU0_CTL_LPCTH_CONFIG , RULL(0x05011090), SH_UNT_PU_NPU0_CTL, @@ -4076,62 +4657,37 @@ REG64( PU_NPU1_CTL_LPCTH_CONFIG , RULL(0x05011190 REG64( PU_NPU2_CTL_LPCTH_CONFIG , RULL(0x05011290), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); -REG64( PEC_0_STACK0_LSIBAR_REG , RULL(0x04010C54), SH_UNT_PEC_0_STACK0, +REG64( PU_NPU0_SM0_MAX_PHY_BAR , RULL(0x05011006), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PEC_0_STACK1_LSIBAR_REG , RULL(0x04010C94), SH_UNT_PEC_0_STACK1, +REG64( PU_NPU0_SM1_MAX_PHY_BAR , RULL(0x05011026), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PEC_0_STACK2_LSIBAR_REG , RULL(0x04010CD4), SH_UNT_PEC_0_STACK2, +REG64( PU_NPU0_SM2_MAX_PHY_BAR , RULL(0x05011046), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PEC_1_STACK0_LSIBAR_REG , RULL(0x04011054), SH_UNT_PEC_1_STACK0, +REG64( PU_NPU0_SM3_MAX_PHY_BAR , RULL(0x05011066), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PEC_1_STACK1_LSIBAR_REG , RULL(0x04011094), SH_UNT_PEC_1_STACK1, +REG64( PU_NPU1_SM0_MAX_PHY_BAR , RULL(0x05011106), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PEC_1_STACK2_LSIBAR_REG , RULL(0x040110D4), SH_UNT_PEC_1_STACK2, +REG64( PU_NPU1_SM1_MAX_PHY_BAR , RULL(0x05011126), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PEC_2_STACK0_LSIBAR_REG , RULL(0x04011454), SH_UNT_PEC_2_STACK0, +REG64( PU_NPU1_SM2_MAX_PHY_BAR , RULL(0x05011146), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PEC_2_STACK1_LSIBAR_REG , RULL(0x04011494), SH_UNT_PEC_2_STACK1, +REG64( PU_NPU1_SM3_MAX_PHY_BAR , RULL(0x05011166), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PEC_2_STACK2_LSIBAR_REG , RULL(0x040114D4), SH_UNT_PEC_2_STACK2, +REG64( PU_NPU2_SM0_MAX_PHY_BAR , RULL(0x05011206), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PEC_STACK0_LSIBAR_REG , RULL(0x04010C54), SH_UNT_PEC_STACK0, +REG64( PU_NPU2_SM1_MAX_PHY_BAR , RULL(0x05011226), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PEC_STACK1_LSIBAR_REG , RULL(0x04010C94), SH_UNT_PEC_STACK1, +REG64( PU_NPU2_SM2_MAX_PHY_BAR , RULL(0x05011246), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PEC_STACK2_LSIBAR_REG , RULL(0x04010CD4), SH_UNT_PEC_STACK2, +REG64( PU_NPU2_SM3_MAX_PHY_BAR , RULL(0x05011266), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); -REG64( PHB_LSIBAR_REG , RULL(0x04010C54), SH_UNT_PHB , SH_ACS_SCOM ); -REG64( PHB_0_LSIBAR_REG , RULL(0x04010C54), SH_UNT_PHB_0 , SH_ACS_SCOM ); -REG64( PHB_1_LSIBAR_REG , RULL(0x04011054), SH_UNT_PHB_1 , SH_ACS_SCOM ); -REG64( PHB_2_LSIBAR_REG , RULL(0x04011094), SH_UNT_PHB_2 , SH_ACS_SCOM ); -REG64( PHB_3_LSIBAR_REG , RULL(0x04011454), SH_UNT_PHB_3 , SH_ACS_SCOM ); -REG64( PHB_4_LSIBAR_REG , RULL(0x04011494), SH_UNT_PHB_4 , SH_ACS_SCOM ); -REG64( PHB_5_LSIBAR_REG , RULL(0x040114D4), SH_UNT_PHB_5 , SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_MAX_BAR , RULL(0x0501100F), SH_UNT_PU_NPU0_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_MAX_BAR , RULL(0x0501102F), SH_UNT_PU_NPU0_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_MAX_BAR , RULL(0x0501104F), SH_UNT_PU_NPU0_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_MAX_BAR , RULL(0x0501106F), SH_UNT_PU_NPU0_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_MAX_BAR , RULL(0x0501110F), SH_UNT_PU_NPU1_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_MAX_BAR , RULL(0x0501112F), SH_UNT_PU_NPU1_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_MAX_BAR , RULL(0x0501114F), SH_UNT_PU_NPU1_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_MAX_BAR , RULL(0x0501116F), SH_UNT_PU_NPU1_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_MAX_BAR , RULL(0x0501120F), SH_UNT_PU_NPU2_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_MAX_BAR , RULL(0x0501122F), SH_UNT_PU_NPU2_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_MAX_BAR , RULL(0x0501124F), SH_UNT_PU_NPU2_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_MAX_BAR , RULL(0x0501126F), SH_UNT_PU_NPU2_SM3, - SH_ACS_SCOM ); +REG64( PU_MCC_FIR_REG , RULL(0x03011400), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_MCC_FIR_REG_AND , RULL(0x03011401), SH_UNT , SH_ACS_SCOM1_AND ); +REG64( PU_MCC_FIR_REG_OR , RULL(0x03011402), SH_UNT , SH_ACS_SCOM2_OR ); +REG64( PU_MCD1_MCC_FIR_REG , RULL(0x03011000), SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW ); +REG64( PU_MCD1_MCC_FIR_REG_AND , RULL(0x03011001), SH_UNT_PU_MCD1 , SH_ACS_SCOM1_AND ); +REG64( PU_MCD1_MCC_FIR_REG_OR , RULL(0x03011002), SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR ); REG64( PU_MCD_DBG , RULL(0x03011413), SH_UNT , SH_ACS_SCOM ); REG64( PU_MCD1_MCD_DBG , RULL(0x03011013), SH_UNT_PU_MCD1 , SH_ACS_SCOM ); @@ -4139,21 +4695,27 @@ REG64( PU_MCD1_MCD_DBG , RULL(0x03011013 REG64( PU_MCD_ECAP , RULL(0x03011412), SH_UNT , SH_ACS_SCOM ); REG64( PU_MCD1_MCD_ECAP , RULL(0x03011012), SH_UNT_PU_MCD1 , SH_ACS_SCOM ); -REG64( PU_MIB_XIICAC , RULL(0x000E0009), SH_UNT , SH_ACS_SCOM_RO ); - -REG64( PU_IOPPE_MIB_XIICAC , RULL(0x06010809), SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO ); - -REG64( PU_MIB_XIMEM , RULL(0x000E0007), SH_UNT , SH_ACS_SCOM_RO ); +REG64( PU_MCD_FIR_ACTION0_REG , RULL(0x03011406), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_MCD1_MCD_FIR_ACTION0_REG , RULL(0x03011006), SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW ); -REG64( PU_IOPPE_MIB_XIMEM , RULL(0x06010807), SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO ); +REG64( PU_MCD_FIR_ACTION1_REG , RULL(0x03011407), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_MCD1_MCD_FIR_ACTION1_REG , RULL(0x03011007), SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW ); -REG64( PU_MIB_XISGB , RULL(0x000E0008), SH_UNT , SH_ACS_SCOM_RO ); +REG64( PU_MCD_FIR_MASK_REG , RULL(0x03011403), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_MCD_FIR_MASK_REG_AND , RULL(0x03011404), SH_UNT , SH_ACS_SCOM1_AND ); +REG64( PU_MCD_FIR_MASK_REG_OR , RULL(0x03011405), SH_UNT , SH_ACS_SCOM2_OR ); +REG64( PU_MCD1_MCD_FIR_MASK_REG , RULL(0x03011003), SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW ); +REG64( PU_MCD1_MCD_FIR_MASK_REG_AND , RULL(0x03011004), SH_UNT_PU_MCD1 , SH_ACS_SCOM1_AND ); +REG64( PU_MCD1_MCD_FIR_MASK_REG_OR , RULL(0x03011005), SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR ); -REG64( PU_IOPPE_MIB_XISGB , RULL(0x06010808), SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO ); +REG64( PU_MIB_XIICAC , RULL(0x000E0009), SH_UNT , + SH_ACS_SCOM_RO ); //DUPS: 06010853, -REG64( PU_MIB_XISIB , RULL(0x000E0006), SH_UNT , SH_ACS_SCOM_RO ); +REG64( PU_MIB_XIMEM , RULL(0x000E0007), SH_UNT , + SH_ACS_SCOM_RO ); //DUPS: 06010851, -REG64( PU_IOPPE_MIB_XISIB , RULL(0x06010806), SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO ); +REG64( PU_MIB_XISGB , RULL(0x000E0008), SH_UNT , + SH_ACS_SCOM_RO ); //DUPS: 06010852, REG64( PU_NPU_CTL_MISC_CONFIG , RULL(0x05011386), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM ); @@ -4164,30 +4726,8 @@ REG64( PU_NPU_CTL_MISC_HOLD , RULL(0x05011384 REG64( PU_NPU_CTL_MISC_MASK , RULL(0x05011385), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM ); -REG64( PEC_0_STACK0_MMIOBAR0_MASK_REG , RULL(0x04010C4F), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM ); -REG64( PEC_0_STACK1_MMIOBAR0_MASK_REG , RULL(0x04010C8F), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM ); -REG64( PEC_0_STACK2_MMIOBAR0_MASK_REG , RULL(0x04010CCF), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM ); -REG64( PEC_1_STACK0_MMIOBAR0_MASK_REG , RULL(0x0401104F), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM ); -REG64( PEC_1_STACK1_MMIOBAR0_MASK_REG , RULL(0x0401108F), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM ); -REG64( PEC_1_STACK2_MMIOBAR0_MASK_REG , RULL(0x040110CF), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM ); -REG64( PEC_2_STACK0_MMIOBAR0_MASK_REG , RULL(0x0401144F), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM ); -REG64( PEC_2_STACK1_MMIOBAR0_MASK_REG , RULL(0x0401148F), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM ); -REG64( PEC_2_STACK2_MMIOBAR0_MASK_REG , RULL(0x040114CF), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM ); -REG64( PEC_STACK0_MMIOBAR0_MASK_REG , RULL(0x04010C4F), SH_UNT_PEC_STACK0, - SH_ACS_SCOM ); -REG64( PEC_STACK1_MMIOBAR0_MASK_REG , RULL(0x04010C8F), SH_UNT_PEC_STACK1, - SH_ACS_SCOM ); -REG64( PEC_STACK2_MMIOBAR0_MASK_REG , RULL(0x04010CCF), SH_UNT_PEC_STACK2, - SH_ACS_SCOM ); +REG64( PU_NMMU_MMCQ_PB_MODE_REG , RULL(0x05012C15), SH_UNT_PU_NMMU , SH_ACS_SCOM ); + REG64( PHB_MMIOBAR0_MASK_REG , RULL(0x04010C4F), SH_UNT_PHB , SH_ACS_SCOM ); REG64( PHB_0_MMIOBAR0_MASK_REG , RULL(0x04010C4F), SH_UNT_PHB_0 , SH_ACS_SCOM ); REG64( PHB_1_MMIOBAR0_MASK_REG , RULL(0x0401104F), SH_UNT_PHB_1 , SH_ACS_SCOM ); @@ -4196,30 +4736,6 @@ REG64( PHB_3_MMIOBAR0_MASK_REG , RULL(0x0401144F REG64( PHB_4_MMIOBAR0_MASK_REG , RULL(0x0401148F), SH_UNT_PHB_4 , SH_ACS_SCOM ); REG64( PHB_5_MMIOBAR0_MASK_REG , RULL(0x040114CF), SH_UNT_PHB_5 , SH_ACS_SCOM ); -REG64( PEC_0_STACK0_MMIOBAR0_REG , RULL(0x04010C4E), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM ); -REG64( PEC_0_STACK1_MMIOBAR0_REG , RULL(0x04010C8E), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM ); -REG64( PEC_0_STACK2_MMIOBAR0_REG , RULL(0x04010CCE), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM ); -REG64( PEC_1_STACK0_MMIOBAR0_REG , RULL(0x0401104E), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM ); -REG64( PEC_1_STACK1_MMIOBAR0_REG , RULL(0x0401108E), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM ); -REG64( PEC_1_STACK2_MMIOBAR0_REG , RULL(0x040110CE), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM ); -REG64( PEC_2_STACK0_MMIOBAR0_REG , RULL(0x0401144E), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM ); -REG64( PEC_2_STACK1_MMIOBAR0_REG , RULL(0x0401148E), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM ); -REG64( PEC_2_STACK2_MMIOBAR0_REG , RULL(0x040114CE), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM ); -REG64( PEC_STACK0_MMIOBAR0_REG , RULL(0x04010C4E), SH_UNT_PEC_STACK0, - SH_ACS_SCOM ); -REG64( PEC_STACK1_MMIOBAR0_REG , RULL(0x04010C8E), SH_UNT_PEC_STACK1, - SH_ACS_SCOM ); -REG64( PEC_STACK2_MMIOBAR0_REG , RULL(0x04010CCE), SH_UNT_PEC_STACK2, - SH_ACS_SCOM ); REG64( PHB_MMIOBAR0_REG , RULL(0x04010C4E), SH_UNT_PHB , SH_ACS_SCOM ); REG64( PHB_0_MMIOBAR0_REG , RULL(0x04010C4E), SH_UNT_PHB_0 , SH_ACS_SCOM ); REG64( PHB_1_MMIOBAR0_REG , RULL(0x0401104E), SH_UNT_PHB_1 , SH_ACS_SCOM ); @@ -4228,30 +4744,6 @@ REG64( PHB_3_MMIOBAR0_REG , RULL(0x0401144E REG64( PHB_4_MMIOBAR0_REG , RULL(0x0401148E), SH_UNT_PHB_4 , SH_ACS_SCOM ); REG64( PHB_5_MMIOBAR0_REG , RULL(0x040114CE), SH_UNT_PHB_5 , SH_ACS_SCOM ); -REG64( PEC_0_STACK0_MMIOBAR1_MASK_REG , RULL(0x04010C51), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM ); -REG64( PEC_0_STACK1_MMIOBAR1_MASK_REG , RULL(0x04010C91), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM ); -REG64( PEC_0_STACK2_MMIOBAR1_MASK_REG , RULL(0x04010CD1), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM ); -REG64( PEC_1_STACK0_MMIOBAR1_MASK_REG , RULL(0x04011051), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM ); -REG64( PEC_1_STACK1_MMIOBAR1_MASK_REG , RULL(0x04011091), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM ); -REG64( PEC_1_STACK2_MMIOBAR1_MASK_REG , RULL(0x040110D1), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM ); -REG64( PEC_2_STACK0_MMIOBAR1_MASK_REG , RULL(0x04011451), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM ); -REG64( PEC_2_STACK1_MMIOBAR1_MASK_REG , RULL(0x04011491), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM ); -REG64( PEC_2_STACK2_MMIOBAR1_MASK_REG , RULL(0x040114D1), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM ); -REG64( PEC_STACK0_MMIOBAR1_MASK_REG , RULL(0x04010C51), SH_UNT_PEC_STACK0, - SH_ACS_SCOM ); -REG64( PEC_STACK1_MMIOBAR1_MASK_REG , RULL(0x04010C91), SH_UNT_PEC_STACK1, - SH_ACS_SCOM ); -REG64( PEC_STACK2_MMIOBAR1_MASK_REG , RULL(0x04010CD1), SH_UNT_PEC_STACK2, - SH_ACS_SCOM ); REG64( PHB_MMIOBAR1_MASK_REG , RULL(0x04010C51), SH_UNT_PHB , SH_ACS_SCOM ); REG64( PHB_0_MMIOBAR1_MASK_REG , RULL(0x04010C51), SH_UNT_PHB_0 , SH_ACS_SCOM ); REG64( PHB_1_MMIOBAR1_MASK_REG , RULL(0x04011051), SH_UNT_PHB_1 , SH_ACS_SCOM ); @@ -4260,30 +4752,6 @@ REG64( PHB_3_MMIOBAR1_MASK_REG , RULL(0x04011451 REG64( PHB_4_MMIOBAR1_MASK_REG , RULL(0x04011491), SH_UNT_PHB_4 , SH_ACS_SCOM ); REG64( PHB_5_MMIOBAR1_MASK_REG , RULL(0x040114D1), SH_UNT_PHB_5 , SH_ACS_SCOM ); -REG64( PEC_0_STACK0_MMIOBAR1_REG , RULL(0x04010C50), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM ); -REG64( PEC_0_STACK1_MMIOBAR1_REG , RULL(0x04010C90), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM ); -REG64( PEC_0_STACK2_MMIOBAR1_REG , RULL(0x04010CD0), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM ); -REG64( PEC_1_STACK0_MMIOBAR1_REG , RULL(0x04011050), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM ); -REG64( PEC_1_STACK1_MMIOBAR1_REG , RULL(0x04011090), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM ); -REG64( PEC_1_STACK2_MMIOBAR1_REG , RULL(0x040110D0), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM ); -REG64( PEC_2_STACK0_MMIOBAR1_REG , RULL(0x04011450), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM ); -REG64( PEC_2_STACK1_MMIOBAR1_REG , RULL(0x04011490), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM ); -REG64( PEC_2_STACK2_MMIOBAR1_REG , RULL(0x040114D0), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM ); -REG64( PEC_STACK0_MMIOBAR1_REG , RULL(0x04010C50), SH_UNT_PEC_STACK0, - SH_ACS_SCOM ); -REG64( PEC_STACK1_MMIOBAR1_REG , RULL(0x04010C90), SH_UNT_PEC_STACK1, - SH_ACS_SCOM ); -REG64( PEC_STACK2_MMIOBAR1_REG , RULL(0x04010CD0), SH_UNT_PEC_STACK2, - SH_ACS_SCOM ); REG64( PHB_MMIOBAR1_REG , RULL(0x04010C50), SH_UNT_PHB , SH_ACS_SCOM ); REG64( PHB_0_MMIOBAR1_REG , RULL(0x04010C50), SH_UNT_PHB_0 , SH_ACS_SCOM ); REG64( PHB_1_MMIOBAR1_REG , RULL(0x04011050), SH_UNT_PHB_1 , SH_ACS_SCOM ); @@ -4292,27 +4760,29 @@ REG64( PHB_3_MMIOBAR1_REG , RULL(0x04011450 REG64( PHB_4_MMIOBAR1_REG , RULL(0x04011490), SH_UNT_PHB_4 , SH_ACS_SCOM ); REG64( PHB_5_MMIOBAR1_REG , RULL(0x040114D0), SH_UNT_PHB_5 , SH_ACS_SCOM ); -REG64( PU_NMMU_MM_CFG_NMMU_CTL_MISC , RULL(0x05012C49), SH_UNT_PU_NMMU , SH_ACS_SCOM ); +REG64( PU_NMMU_MM_CFG_NMMU_CTL_MISC , RULL(0x05012C53), SH_UNT_PU_NMMU , SH_ACS_SCOM ); -REG64( PU_NMMU_MM_CFG_NMMU_CTL_SLB , RULL(0x05012C4A), SH_UNT_PU_NMMU , SH_ACS_SCOM ); +REG64( PU_NMMU_MM_CFG_NMMU_CTL_SLB , RULL(0x05012C54), SH_UNT_PU_NMMU , SH_ACS_SCOM ); -REG64( PU_NMMU_MM_CFG_NMMU_CTL_SM , RULL(0x05012C48), SH_UNT_PU_NMMU , SH_ACS_SCOM ); +REG64( PU_NMMU_MM_CFG_NMMU_CTL_SM , RULL(0x05012C52), SH_UNT_PU_NMMU , SH_ACS_SCOM ); -REG64( PU_NMMU_MM_CFG_NMMU_CTL_TLB , RULL(0x05012C4B), SH_UNT_PU_NMMU , SH_ACS_SCOM ); +REG64( PU_NMMU_MM_CFG_NMMU_CTL_TLB , RULL(0x05012C55), SH_UNT_PU_NMMU , SH_ACS_SCOM ); -REG64( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0 , RULL(0x05012C40), SH_UNT_PU_NMMU , SH_ACS_SCOM ); +REG64( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0 , RULL(0x05012C4A), SH_UNT_PU_NMMU , SH_ACS_SCOM ); -REG64( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG1 , RULL(0x05012C41), SH_UNT_PU_NMMU , SH_ACS_SCOM ); +REG64( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG1 , RULL(0x05012C4B), SH_UNT_PU_NMMU , SH_ACS_SCOM ); -REG64( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG2 , RULL(0x05012C42), SH_UNT_PU_NMMU , SH_ACS_SCOM ); +REG64( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG2 , RULL(0x05012C4C), SH_UNT_PU_NMMU , SH_ACS_SCOM ); -REG64( PU_NMMU_MM_NMMU_DBG_MODE , RULL(0x05012C4F), SH_UNT_PU_NMMU , SH_ACS_SCOM ); +REG64( PU_NMMU_MM_EPSILON_COUNTER_VALUE , RULL(0x05012C1D), SH_UNT_PU_NMMU , SH_ACS_SCOM ); -REG64( PU_NMMU_MM_NMMU_ERR_INJ , RULL(0x05012C4E), SH_UNT_PU_NMMU , SH_ACS_SCOM ); +REG64( PU_NMMU_MM_NMMU_DBG_MODE , RULL(0x05012C59), SH_UNT_PU_NMMU , SH_ACS_SCOM ); -REG64( PU_NMMU_MM_NMMU_ERR_LOG , RULL(0x05012C4D), SH_UNT_PU_NMMU , SH_ACS_SCOM ); +REG64( PU_NMMU_MM_NMMU_ERR_INJ , RULL(0x05012C58), SH_UNT_PU_NMMU , SH_ACS_SCOM ); -REG64( PU_NMMU_MM_NMMU_FIR , RULL(0x05012C4C), SH_UNT_PU_NMMU , SH_ACS_SCOM ); +REG64( PU_NMMU_MM_NMMU_ERR_LOG , RULL(0x05012C57), SH_UNT_PU_NMMU , SH_ACS_SCOM ); + +REG64( PEC_MODE_REG , RULL(0x0D040008), SH_UNT_PEC , SH_ACS_SCOM ); REG64( PU_MODE_REGISTER , RULL(0x00010008), SH_UNT , SH_ACS_SCOM ); @@ -4324,117 +4794,41 @@ REG64( PU_MODE_REGISTER_D , RULL(0x000A2006 REG64( PU_MODE_REGISTER_E , RULL(0x000A3006), SH_UNT , SH_ACS_SCOM ); -REG64( PEC_0_STACK0_MSIBAR_REG , RULL(0x04010C53), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM ); -REG64( PEC_0_STACK1_MSIBAR_REG , RULL(0x04010C93), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM ); -REG64( PEC_0_STACK2_MSIBAR_REG , RULL(0x04010CD3), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM ); -REG64( PEC_1_STACK0_MSIBAR_REG , RULL(0x04011053), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM ); -REG64( PEC_1_STACK1_MSIBAR_REG , RULL(0x04011093), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM ); -REG64( PEC_1_STACK2_MSIBAR_REG , RULL(0x040110D3), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM ); -REG64( PEC_2_STACK0_MSIBAR_REG , RULL(0x04011453), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM ); -REG64( PEC_2_STACK1_MSIBAR_REG , RULL(0x04011493), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM ); -REG64( PEC_2_STACK2_MSIBAR_REG , RULL(0x040114D3), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM ); -REG64( PEC_STACK0_MSIBAR_REG , RULL(0x04010C53), SH_UNT_PEC_STACK0, - SH_ACS_SCOM ); -REG64( PEC_STACK1_MSIBAR_REG , RULL(0x04010C93), SH_UNT_PEC_STACK1, - SH_ACS_SCOM ); -REG64( PEC_STACK2_MSIBAR_REG , RULL(0x04010CD3), SH_UNT_PEC_STACK2, - SH_ACS_SCOM ); -REG64( PHB_MSIBAR_REG , RULL(0x04010C53), SH_UNT_PHB , SH_ACS_SCOM ); -REG64( PHB_0_MSIBAR_REG , RULL(0x04010C53), SH_UNT_PHB_0 , SH_ACS_SCOM ); -REG64( PHB_1_MSIBAR_REG , RULL(0x04011053), SH_UNT_PHB_1 , SH_ACS_SCOM ); -REG64( PHB_2_MSIBAR_REG , RULL(0x04011093), SH_UNT_PHB_2 , SH_ACS_SCOM ); -REG64( PHB_3_MSIBAR_REG , RULL(0x04011453), SH_UNT_PHB_3 , SH_ACS_SCOM ); -REG64( PHB_4_MSIBAR_REG , RULL(0x04011493), SH_UNT_PHB_4 , SH_ACS_SCOM ); -REG64( PHB_5_MSIBAR_REG , RULL(0x040114D3), SH_UNT_PHB_5 , SH_ACS_SCOM ); +REG64( PEC_MULTICAST_GROUP_1 , RULL(0x0D0F0001), SH_UNT_PEC , SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_NDT0_BAR , RULL(0x0501100D), SH_UNT_PU_NPU0_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_NDT0_BAR , RULL(0x0501102D), SH_UNT_PU_NPU0_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_NDT0_BAR , RULL(0x0501104D), SH_UNT_PU_NPU0_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_NDT0_BAR , RULL(0x0501106D), SH_UNT_PU_NPU0_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_NDT0_BAR , RULL(0x0501110D), SH_UNT_PU_NPU1_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_NDT0_BAR , RULL(0x0501112D), SH_UNT_PU_NPU1_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_NDT0_BAR , RULL(0x0501114D), SH_UNT_PU_NPU1_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_NDT0_BAR , RULL(0x0501116D), SH_UNT_PU_NPU1_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_NDT0_BAR , RULL(0x0501120D), SH_UNT_PU_NPU2_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_NDT0_BAR , RULL(0x0501122D), SH_UNT_PU_NPU2_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_NDT0_BAR , RULL(0x0501124D), SH_UNT_PU_NPU2_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_NDT0_BAR , RULL(0x0501126D), SH_UNT_PU_NPU2_SM3, - SH_ACS_SCOM ); +REG64( PEC_MULTICAST_GROUP_2 , RULL(0x0D0F0002), SH_UNT_PEC , SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_NDT1_BAR , RULL(0x0501100E), SH_UNT_PU_NPU0_SM0, +REG64( PEC_MULTICAST_GROUP_3 , RULL(0x0D0F0003), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_MULTICAST_GROUP_4 , RULL(0x0D0F0004), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_NPU0_SM0_NDT_BAR , RULL(0x05011005), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_NDT1_BAR , RULL(0x0501102E), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_NDT_BAR , RULL(0x05011025), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_NDT1_BAR , RULL(0x0501104E), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_NDT_BAR , RULL(0x05011045), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_NDT1_BAR , RULL(0x0501106E), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_NDT_BAR , RULL(0x05011065), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_NDT1_BAR , RULL(0x0501110E), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_NDT_BAR , RULL(0x05011105), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_NDT1_BAR , RULL(0x0501112E), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_NDT_BAR , RULL(0x05011125), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_NDT1_BAR , RULL(0x0501114E), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_NDT_BAR , RULL(0x05011145), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_NDT1_BAR , RULL(0x0501116E), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_NDT_BAR , RULL(0x05011165), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_NDT1_BAR , RULL(0x0501120E), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_NDT_BAR , RULL(0x05011205), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_NDT1_BAR , RULL(0x0501122E), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_NDT_BAR , RULL(0x05011225), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_NDT1_BAR , RULL(0x0501124E), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_NDT_BAR , RULL(0x05011245), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_NDT1_BAR , RULL(0x0501126E), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_NDT_BAR , RULL(0x05011265), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); REG64( PEC_NESTTRC_REG , RULL(0x04010C03), SH_UNT_PEC , SH_ACS_SCOM_RW ); -REG64( PEC_0_NESTTRC_REG , RULL(0x04010C03), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); -REG64( PEC_1_NESTTRC_REG , RULL(0x04011003), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); -REG64( PEC_2_NESTTRC_REG , RULL(0x04011403), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK0_NFIRACTION0_REG , RULL(0x04010C46), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK1_NFIRACTION0_REG , RULL(0x04010C86), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK2_NFIRACTION0_REG , RULL(0x04010CC6), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK0_NFIRACTION0_REG , RULL(0x04011046), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK1_NFIRACTION0_REG , RULL(0x04011086), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK2_NFIRACTION0_REG , RULL(0x040110C6), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK0_NFIRACTION0_REG , RULL(0x04011446), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK1_NFIRACTION0_REG , RULL(0x04011486), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK2_NFIRACTION0_REG , RULL(0x040114C6), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK0_NFIRACTION0_REG , RULL(0x04010C46), SH_UNT_PEC_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK1_NFIRACTION0_REG , RULL(0x04010C86), SH_UNT_PEC_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK2_NFIRACTION0_REG , RULL(0x04010CC6), SH_UNT_PEC_STACK2, - SH_ACS_SCOM_RW ); REG64( PHB_NFIRACTION0_REG , RULL(0x04010C46), SH_UNT_PHB , SH_ACS_SCOM_RW ); REG64( PHB_0_NFIRACTION0_REG , RULL(0x04010C46), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); REG64( PHB_1_NFIRACTION0_REG , RULL(0x04011046), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); @@ -4443,30 +4837,6 @@ REG64( PHB_3_NFIRACTION0_REG , RULL(0x04011446 REG64( PHB_4_NFIRACTION0_REG , RULL(0x04011486), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); REG64( PHB_5_NFIRACTION0_REG , RULL(0x040114C6), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK0_NFIRACTION1_REG , RULL(0x04010C47), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK1_NFIRACTION1_REG , RULL(0x04010C87), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK2_NFIRACTION1_REG , RULL(0x04010CC7), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK0_NFIRACTION1_REG , RULL(0x04011047), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK1_NFIRACTION1_REG , RULL(0x04011087), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK2_NFIRACTION1_REG , RULL(0x040110C7), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK0_NFIRACTION1_REG , RULL(0x04011447), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK1_NFIRACTION1_REG , RULL(0x04011487), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK2_NFIRACTION1_REG , RULL(0x040114C7), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK0_NFIRACTION1_REG , RULL(0x04010C47), SH_UNT_PEC_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK1_NFIRACTION1_REG , RULL(0x04010C87), SH_UNT_PEC_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK2_NFIRACTION1_REG , RULL(0x04010CC7), SH_UNT_PEC_STACK2, - SH_ACS_SCOM_RW ); REG64( PHB_NFIRACTION1_REG , RULL(0x04010C47), SH_UNT_PHB , SH_ACS_SCOM_RW ); REG64( PHB_0_NFIRACTION1_REG , RULL(0x04010C47), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); REG64( PHB_1_NFIRACTION1_REG , RULL(0x04011047), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); @@ -4475,78 +4845,6 @@ REG64( PHB_3_NFIRACTION1_REG , RULL(0x04011447 REG64( PHB_4_NFIRACTION1_REG , RULL(0x04011487), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); REG64( PHB_5_NFIRACTION1_REG , RULL(0x040114C7), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK0_NFIRMASK_REG , RULL(0x04010C43), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK0_NFIRMASK_REG_AND , RULL(0x04010C44), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM1_AND ); -REG64( PEC_0_STACK0_NFIRMASK_REG_OR , RULL(0x04010C45), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM2_OR ); -REG64( PEC_0_STACK1_NFIRMASK_REG , RULL(0x04010C83), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK1_NFIRMASK_REG_AND , RULL(0x04010C84), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM1_AND ); -REG64( PEC_0_STACK1_NFIRMASK_REG_OR , RULL(0x04010C85), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM2_OR ); -REG64( PEC_0_STACK2_NFIRMASK_REG , RULL(0x04010CC3), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK2_NFIRMASK_REG_AND , RULL(0x04010CC4), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM1_AND ); -REG64( PEC_0_STACK2_NFIRMASK_REG_OR , RULL(0x04010CC5), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM2_OR ); -REG64( PEC_1_STACK0_NFIRMASK_REG , RULL(0x04011043), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK0_NFIRMASK_REG_AND , RULL(0x04011044), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM1_AND ); -REG64( PEC_1_STACK0_NFIRMASK_REG_OR , RULL(0x04011045), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM2_OR ); -REG64( PEC_1_STACK1_NFIRMASK_REG , RULL(0x04011083), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK1_NFIRMASK_REG_AND , RULL(0x04011084), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM1_AND ); -REG64( PEC_1_STACK1_NFIRMASK_REG_OR , RULL(0x04011085), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM2_OR ); -REG64( PEC_1_STACK2_NFIRMASK_REG , RULL(0x040110C3), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK2_NFIRMASK_REG_AND , RULL(0x040110C4), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM1_AND ); -REG64( PEC_1_STACK2_NFIRMASK_REG_OR , RULL(0x040110C5), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM2_OR ); -REG64( PEC_2_STACK0_NFIRMASK_REG , RULL(0x04011443), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK0_NFIRMASK_REG_AND , RULL(0x04011444), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM1_AND ); -REG64( PEC_2_STACK0_NFIRMASK_REG_OR , RULL(0x04011445), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM2_OR ); -REG64( PEC_2_STACK1_NFIRMASK_REG , RULL(0x04011483), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK1_NFIRMASK_REG_AND , RULL(0x04011484), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM1_AND ); -REG64( PEC_2_STACK1_NFIRMASK_REG_OR , RULL(0x04011485), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM2_OR ); -REG64( PEC_2_STACK2_NFIRMASK_REG , RULL(0x040114C3), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK2_NFIRMASK_REG_AND , RULL(0x040114C4), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM1_AND ); -REG64( PEC_2_STACK2_NFIRMASK_REG_OR , RULL(0x040114C5), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM2_OR ); -REG64( PEC_STACK0_NFIRMASK_REG , RULL(0x04010C43), SH_UNT_PEC_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK0_NFIRMASK_REG_AND , RULL(0x04010C44), SH_UNT_PEC_STACK0, - SH_ACS_SCOM1_AND ); -REG64( PEC_STACK0_NFIRMASK_REG_OR , RULL(0x04010C45), SH_UNT_PEC_STACK0, - SH_ACS_SCOM2_OR ); -REG64( PEC_STACK1_NFIRMASK_REG , RULL(0x04010C83), SH_UNT_PEC_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK1_NFIRMASK_REG_AND , RULL(0x04010C84), SH_UNT_PEC_STACK1, - SH_ACS_SCOM1_AND ); -REG64( PEC_STACK1_NFIRMASK_REG_OR , RULL(0x04010C85), SH_UNT_PEC_STACK1, - SH_ACS_SCOM2_OR ); -REG64( PEC_STACK2_NFIRMASK_REG , RULL(0x04010CC3), SH_UNT_PEC_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK2_NFIRMASK_REG_AND , RULL(0x04010CC4), SH_UNT_PEC_STACK2, - SH_ACS_SCOM1_AND ); -REG64( PEC_STACK2_NFIRMASK_REG_OR , RULL(0x04010CC5), SH_UNT_PEC_STACK2, - SH_ACS_SCOM2_OR ); REG64( PHB_NFIRMASK_REG , RULL(0x04010C43), SH_UNT_PHB , SH_ACS_SCOM_RW ); REG64( PHB_NFIRMASK_REG_AND , RULL(0x04010C44), SH_UNT_PHB , SH_ACS_SCOM1_AND ); REG64( PHB_NFIRMASK_REG_OR , RULL(0x04010C45), SH_UNT_PHB , SH_ACS_SCOM2_OR ); @@ -4569,30 +4867,6 @@ REG64( PHB_5_NFIRMASK_REG , RULL(0x040114C3 REG64( PHB_5_NFIRMASK_REG_AND , RULL(0x040114C4), SH_UNT_PHB_5 , SH_ACS_SCOM1_AND ); REG64( PHB_5_NFIRMASK_REG_OR , RULL(0x040114C5), SH_UNT_PHB_5 , SH_ACS_SCOM2_OR ); -REG64( PEC_0_STACK0_NFIRWOF_REG , RULL(0x04010C48), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM_WCLRREG ); -REG64( PEC_0_STACK1_NFIRWOF_REG , RULL(0x04010C88), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM_WCLRREG ); -REG64( PEC_0_STACK2_NFIRWOF_REG , RULL(0x04010CC8), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM_WCLRREG ); -REG64( PEC_1_STACK0_NFIRWOF_REG , RULL(0x04011048), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM_WCLRREG ); -REG64( PEC_1_STACK1_NFIRWOF_REG , RULL(0x04011088), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM_WCLRREG ); -REG64( PEC_1_STACK2_NFIRWOF_REG , RULL(0x040110C8), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM_WCLRREG ); -REG64( PEC_2_STACK0_NFIRWOF_REG , RULL(0x04011448), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM_WCLRREG ); -REG64( PEC_2_STACK1_NFIRWOF_REG , RULL(0x04011488), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM_WCLRREG ); -REG64( PEC_2_STACK2_NFIRWOF_REG , RULL(0x040114C8), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM_WCLRREG ); -REG64( PEC_STACK0_NFIRWOF_REG , RULL(0x04010C48), SH_UNT_PEC_STACK0, - SH_ACS_SCOM_WCLRREG ); -REG64( PEC_STACK1_NFIRWOF_REG , RULL(0x04010C88), SH_UNT_PEC_STACK1, - SH_ACS_SCOM_WCLRREG ); -REG64( PEC_STACK2_NFIRWOF_REG , RULL(0x04010CC8), SH_UNT_PEC_STACK2, - SH_ACS_SCOM_WCLRREG ); REG64( PHB_NFIRWOF_REG , RULL(0x04010C48), SH_UNT_PHB , SH_ACS_SCOM_WCLRREG ); REG64( PHB_0_NFIRWOF_REG , RULL(0x04010C48), SH_UNT_PHB_0 , @@ -4608,78 +4882,6 @@ REG64( PHB_4_NFIRWOF_REG , RULL(0x04011488 REG64( PHB_5_NFIRWOF_REG , RULL(0x040114C8), SH_UNT_PHB_5 , SH_ACS_SCOM_WCLRREG ); -REG64( PEC_0_STACK0_NFIR_REG , RULL(0x04010C40), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK0_NFIR_REG_AND , RULL(0x04010C41), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM1_AND ); -REG64( PEC_0_STACK0_NFIR_REG_OR , RULL(0x04010C42), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM2_OR ); -REG64( PEC_0_STACK1_NFIR_REG , RULL(0x04010C80), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK1_NFIR_REG_AND , RULL(0x04010C81), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM1_AND ); -REG64( PEC_0_STACK1_NFIR_REG_OR , RULL(0x04010C82), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM2_OR ); -REG64( PEC_0_STACK2_NFIR_REG , RULL(0x04010CC0), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK2_NFIR_REG_AND , RULL(0x04010CC1), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM1_AND ); -REG64( PEC_0_STACK2_NFIR_REG_OR , RULL(0x04010CC2), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM2_OR ); -REG64( PEC_1_STACK0_NFIR_REG , RULL(0x04011040), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK0_NFIR_REG_AND , RULL(0x04011041), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM1_AND ); -REG64( PEC_1_STACK0_NFIR_REG_OR , RULL(0x04011042), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM2_OR ); -REG64( PEC_1_STACK1_NFIR_REG , RULL(0x04011080), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK1_NFIR_REG_AND , RULL(0x04011081), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM1_AND ); -REG64( PEC_1_STACK1_NFIR_REG_OR , RULL(0x04011082), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM2_OR ); -REG64( PEC_1_STACK2_NFIR_REG , RULL(0x040110C0), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK2_NFIR_REG_AND , RULL(0x040110C1), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM1_AND ); -REG64( PEC_1_STACK2_NFIR_REG_OR , RULL(0x040110C2), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM2_OR ); -REG64( PEC_2_STACK0_NFIR_REG , RULL(0x04011440), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK0_NFIR_REG_AND , RULL(0x04011441), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM1_AND ); -REG64( PEC_2_STACK0_NFIR_REG_OR , RULL(0x04011442), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM2_OR ); -REG64( PEC_2_STACK1_NFIR_REG , RULL(0x04011480), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK1_NFIR_REG_AND , RULL(0x04011481), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM1_AND ); -REG64( PEC_2_STACK1_NFIR_REG_OR , RULL(0x04011482), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM2_OR ); -REG64( PEC_2_STACK2_NFIR_REG , RULL(0x040114C0), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK2_NFIR_REG_AND , RULL(0x040114C1), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM1_AND ); -REG64( PEC_2_STACK2_NFIR_REG_OR , RULL(0x040114C2), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM2_OR ); -REG64( PEC_STACK0_NFIR_REG , RULL(0x04010C40), SH_UNT_PEC_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK0_NFIR_REG_AND , RULL(0x04010C41), SH_UNT_PEC_STACK0, - SH_ACS_SCOM1_AND ); -REG64( PEC_STACK0_NFIR_REG_OR , RULL(0x04010C42), SH_UNT_PEC_STACK0, - SH_ACS_SCOM2_OR ); -REG64( PEC_STACK1_NFIR_REG , RULL(0x04010C80), SH_UNT_PEC_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK1_NFIR_REG_AND , RULL(0x04010C81), SH_UNT_PEC_STACK1, - SH_ACS_SCOM1_AND ); -REG64( PEC_STACK1_NFIR_REG_OR , RULL(0x04010C82), SH_UNT_PEC_STACK1, - SH_ACS_SCOM2_OR ); -REG64( PEC_STACK2_NFIR_REG , RULL(0x04010CC0), SH_UNT_PEC_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK2_NFIR_REG_AND , RULL(0x04010CC1), SH_UNT_PEC_STACK2, - SH_ACS_SCOM1_AND ); -REG64( PEC_STACK2_NFIR_REG_OR , RULL(0x04010CC2), SH_UNT_PEC_STACK2, - SH_ACS_SCOM2_OR ); REG64( PHB_NFIR_REG , RULL(0x04010C40), SH_UNT_PHB , SH_ACS_SCOM_RW ); REG64( PHB_NFIR_REG_AND , RULL(0x04010C41), SH_UNT_PHB , SH_ACS_SCOM1_AND ); REG64( PHB_NFIR_REG_OR , RULL(0x04010C42), SH_UNT_PHB , SH_ACS_SCOM2_OR ); @@ -4702,13 +4904,13 @@ REG64( PHB_5_NFIR_REG , RULL(0x040114C0 REG64( PHB_5_NFIR_REG_AND , RULL(0x040114C1), SH_UNT_PHB_5 , SH_ACS_SCOM1_AND ); REG64( PHB_5_NFIR_REG_OR , RULL(0x040114C2), SH_UNT_PHB_5 , SH_ACS_SCOM2_OR ); -REG64( PU_NOTRUST_BAR0 , RULL(0x05015F40), SH_UNT , SH_ACS_SCOM ); +REG64( PU_NOTRUST_BAR0 , RULL(0x05012B40), SH_UNT , SH_ACS_SCOM ); -REG64( PU_NOTRUST_BAR0MASK , RULL(0x05015F42), SH_UNT , SH_ACS_SCOM ); +REG64( PU_NOTRUST_BAR0MASK , RULL(0x05012B42), SH_UNT , SH_ACS_SCOM ); -REG64( PU_NOTRUST_BAR1 , RULL(0x05015F41), SH_UNT , SH_ACS_SCOM ); +REG64( PU_NOTRUST_BAR1 , RULL(0x05012B41), SH_UNT , SH_ACS_SCOM ); -REG64( PU_NOTRUST_BAR1MASK , RULL(0x05015F43), SH_UNT , SH_ACS_SCOM ); +REG64( PU_NOTRUST_BAR1MASK , RULL(0x05012B43), SH_UNT , SH_ACS_SCOM ); REG64( PU_NPU_SM0_NPU_ATS_DEBUG , RULL(0x05011303), SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW ); @@ -4737,6 +4939,9 @@ REG64( PU_NPU_SM0_NPU_AT_PMU_CTRL , RULL(0x05011300 REG64( PU_NPU_SM1_NPU_Q_DMA_R , RULL(0x05011325), SH_UNT_PU_NPU_SM1, SH_ACS_SCOM ); +REG64( PU_NPU_CTL_NPU_VERSION , RULL(0x05011390), SH_UNT_PU_NPU_CTL, + SH_ACS_SCOM ); + REG64( PU_NXCQ_PB_MODE_REG , RULL(0x02011095), SH_UNT , SH_ACS_SCOM ); REG64( PU_NX_CQ_FIR_ACTION0_REG , RULL(0x02011086), SH_UNT , SH_ACS_SCOM_RW ); @@ -4787,8 +4992,6 @@ REG64( PU_NX_DMA_ENG_FIR_MASK_OR , RULL(0x02011105 REG64( PU_NX_DMA_ENG_FIR_WOF , RULL(0x02011108), SH_UNT , SH_ACS_SCOM_WCLRREG ); -REG64( PU_NMMU_NX_EPSILON_COUNTER_VALUE , RULL(0x05012C1D), SH_UNT_PU_NMMU , SH_ACS_SCOM ); - REG64( PU_NX_ERRORINJ_CTRL , RULL(0x0201110C), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_NX_MISC_CONTROL_REG , RULL(0x020110A8), SH_UNT , SH_ACS_SCOM ); @@ -6138,13 +6341,13 @@ REG64( PU_OCB_PIB_OCBCSR3_CLEAR , RULL(0x0006D072 SH_ACS_SCOM1_CLEAR ); REG64( PU_OCB_PIB_OCBCSR3_OR , RULL(0x0006D073), SH_UNT , SH_ACS_SCOM2_OR ); -REG64( PU_OCB_PIB_OCBDR0 , RULL(0x0006D015), SH_UNT , SH_ACS_SCOM_WO ); +REG64( PU_OCB_PIB_OCBDR0 , RULL(0x0006D015), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_OCB_PIB_OCBDR1 , RULL(0x0006D035), SH_UNT , SH_ACS_SCOM_WO ); +REG64( PU_OCB_PIB_OCBDR1 , RULL(0x0006D035), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_OCB_PIB_OCBDR2 , RULL(0x0006D055), SH_UNT , SH_ACS_SCOM_WO ); +REG64( PU_OCB_PIB_OCBDR2 , RULL(0x0006D055), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_OCB_PIB_OCBDR3 , RULL(0x0006D075), SH_UNT , SH_ACS_SCOM_WO ); +REG64( PU_OCB_PIB_OCBDR3 , RULL(0x0006D075), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_OCB_PIB_OCBEAR , RULL(0x0006D210), SH_UNT , SH_ACS_SCOM_WCLRPART ); @@ -6184,6 +6387,20 @@ REG64( PU_OCB_PIB_OSTOESR , RULL(0x0006D201 REG64( PU_OCB_PIB_OTDCR , RULL(0x0006D110), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PEC_OPCG_ALIGN , RULL(0x0D030001), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_OPCG_CAPT1 , RULL(0x0D030010), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_OPCG_CAPT2 , RULL(0x0D030011), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_OPCG_CAPT3 , RULL(0x0D030012), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_OPCG_REG0 , RULL(0x0D030002), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_OPCG_REG1 , RULL(0x0D030003), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_OPCG_REG2 , RULL(0x0D030004), SH_UNT_PEC , SH_ACS_SCOM ); + REG64( PU_NPU_CTL_OPTICAL_IO_CONFIG , RULL(0x05011383), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM ); @@ -6224,10 +6441,7 @@ REG64( PU_PBAFIRMASK , RULL(0x05012843 REG64( PU_PBAFIRMASK_AND , RULL(0x05012844), SH_UNT , SH_ACS_SCOM1_AND ); REG64( PU_PBAFIRMASK_OR , RULL(0x05012845), SH_UNT , SH_ACS_SCOM2_OR ); -REG64( PEC_PBAIBHWCFG_REG , RULL(0x0D010802), SH_UNT_PEC , SH_ACS_SCOM_RW ); -REG64( PEC_0_PBAIBHWCFG_REG , RULL(0x0D010802), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); -REG64( PEC_1_PBAIBHWCFG_REG , RULL(0x0E010802), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); -REG64( PEC_2_PBAIBHWCFG_REG , RULL(0x0F010802), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); +REG64( PEC_PBAIBHWCFG_REG , RULL(0x0D010800), SH_UNT_PEC , SH_ACS_SCOM_RW ); REG64( PHB_PBAIB_CERR_RPT_REG , RULL(0x0D010841), SH_UNT_PHB , SH_ACS_SCOM_RO ); REG64( PHB_0_PBAIB_CERR_RPT_REG , RULL(0x0D010841), SH_UNT_PHB_0 , SH_ACS_SCOM_RO ); @@ -6322,39 +6536,9 @@ REG64( PU_PBAXSNDTX_OCI , RULL(0xC0040100 REG64( PU_PBAXSNDTX_SCOM , RULL(0x05016860), SH_UNT , SH_ACS_SCOM_RW ); REG64( PEC_PBCQEINJ_REG , RULL(0x04010C02), SH_UNT_PEC , SH_ACS_SCOM_RW ); -REG64( PEC_0_PBCQEINJ_REG , RULL(0x04010C02), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); -REG64( PEC_1_PBCQEINJ_REG , RULL(0x04011002), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); -REG64( PEC_2_PBCQEINJ_REG , RULL(0x04011402), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); REG64( PEC_PBCQHWCFG_REG , RULL(0x04010C00), SH_UNT_PEC , SH_ACS_SCOM_RW ); -REG64( PEC_0_PBCQHWCFG_REG , RULL(0x04010C00), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); -REG64( PEC_1_PBCQHWCFG_REG , RULL(0x04011000), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); -REG64( PEC_2_PBCQHWCFG_REG , RULL(0x04011400), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK0_PBCQMODE_REG , RULL(0x04010C4D), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK1_PBCQMODE_REG , RULL(0x04010C8D), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_0_STACK2_PBCQMODE_REG , RULL(0x04010CCD), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK0_PBCQMODE_REG , RULL(0x0401104D), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK1_PBCQMODE_REG , RULL(0x0401108D), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_1_STACK2_PBCQMODE_REG , RULL(0x040110CD), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK0_PBCQMODE_REG , RULL(0x0401144D), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK1_PBCQMODE_REG , RULL(0x0401148D), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_2_STACK2_PBCQMODE_REG , RULL(0x040114CD), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK0_PBCQMODE_REG , RULL(0x04010C4D), SH_UNT_PEC_STACK0, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK1_PBCQMODE_REG , RULL(0x04010C8D), SH_UNT_PEC_STACK1, - SH_ACS_SCOM_RW ); -REG64( PEC_STACK2_PBCQMODE_REG , RULL(0x04010CCD), SH_UNT_PEC_STACK2, - SH_ACS_SCOM_RW ); REG64( PHB_PBCQMODE_REG , RULL(0x04010C4D), SH_UNT_PHB , SH_ACS_SCOM_RW ); REG64( PHB_0_PBCQMODE_REG , RULL(0x04010C4D), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); REG64( PHB_1_PBCQMODE_REG , RULL(0x0401104D), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); @@ -6427,6 +6611,30 @@ REG64( PU_IOE_PBO_MAILBOX_CTL_REG , RULL(0x0501382E REG64( PU_IOE_PBO_MAILBOX_DATA_REG , RULL(0x0501382F), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); +REG64( _SM0_PB_CENT_FIR_ACTION0_REG , RULL(0x05011C06), SH_UNT__SM0 , SH_ACS_SCOM_RW ); + +REG64( _SM0_PB_CENT_FIR_ACTION1_REG , RULL(0x05011C07), SH_UNT__SM0 , SH_ACS_SCOM_RW ); + +REG64( _SM0_PB_CENT_FIR_MASK_REG , RULL(0x05011C03), SH_UNT__SM0 , SH_ACS_SCOM_RW ); +REG64( _SM0_PB_CENT_FIR_MASK_REG_AND , RULL(0x05011C04), SH_UNT__SM0 , SH_ACS_SCOM1_AND ); +REG64( _SM0_PB_CENT_FIR_MASK_REG_OR , RULL(0x05011C05), SH_UNT__SM0 , SH_ACS_SCOM2_OR ); + +REG64( _SM0_PB_CENT_FIR_REG , RULL(0x05011C00), SH_UNT__SM0 , SH_ACS_SCOM_RW ); +REG64( _SM0_PB_CENT_FIR_REG_AND , RULL(0x05011C01), SH_UNT__SM0 , SH_ACS_SCOM1_AND ); +REG64( _SM0_PB_CENT_FIR_REG_OR , RULL(0x05011C02), SH_UNT__SM0 , SH_ACS_SCOM2_OR ); + +REG64( PU_PB_EAST_FIR_ACTION0_REG , RULL(0x05012006), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_PB_EAST_FIR_ACTION1_REG , RULL(0x05012007), SH_UNT , SH_ACS_SCOM_RW ); + +REG64( PU_PB_EAST_FIR_MASK_REG , RULL(0x05012003), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_PB_EAST_FIR_MASK_REG_AND , RULL(0x05012004), SH_UNT , SH_ACS_SCOM1_AND ); +REG64( PU_PB_EAST_FIR_MASK_REG_OR , RULL(0x05012005), SH_UNT , SH_ACS_SCOM2_OR ); + +REG64( PU_PB_EAST_FIR_REG , RULL(0x05012000), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_PB_EAST_FIR_REG_AND , RULL(0x05012001), SH_UNT , SH_ACS_SCOM1_AND ); +REG64( PU_PB_EAST_FIR_REG_OR , RULL(0x05012002), SH_UNT , SH_ACS_SCOM2_OR ); + REG64( PU_PB_ELINK_DATA_01_CFG_REG , RULL(0x05013410), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_PB_ELINK_DATA_23_CFG_REG , RULL(0x05013411), SH_UNT , SH_ACS_SCOM_RW ); @@ -6437,34 +6645,39 @@ REG64( PU_PB_ELINK_DLY_0123_REG , RULL(0x0501340E REG64( PU_PB_ELINK_DLY_45_REG , RULL(0x0501340F), SH_UNT , SH_ACS_SCOM_RO ); -REG64( PU_PB_ELINK_PMU0 , RULL(0x0501341B), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_PB_ELINK_PMU0 , RULL(0x0501341B), SH_UNT , + SH_ACS_SCOM_WCLRREG ); -REG64( PU_PB_ELINK_PMU1 , RULL(0x0501341C), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_PB_ELINK_PMU1 , RULL(0x0501341C), SH_UNT , + SH_ACS_SCOM_WCLRREG ); -REG64( PU_PB_ELINK_PMU2 , RULL(0x0501341D), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_PB_ELINK_PMU2 , RULL(0x0501341D), SH_UNT , + SH_ACS_SCOM_WCLRREG ); -REG64( PU_PB_ELINK_PMU3 , RULL(0x0501341E), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_PB_ELINK_PMU3 , RULL(0x0501341E), SH_UNT , + SH_ACS_SCOM_WCLRREG ); -REG64( PU_PB_ELINK_PMU4 , RULL(0x0501341F), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_PB_ELINK_PMU4 , RULL(0x0501341F), SH_UNT , + SH_ACS_SCOM_WCLRREG ); -REG64( PU_PB_ELINK_PMU5 , RULL(0x05013420), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_PB_ELINK_PMU5 , RULL(0x05013420), SH_UNT , + SH_ACS_SCOM_WCLRREG ); -REG64( PU_PB_ELINK_PMU6 , RULL(0x05013421), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_PB_ELINK_PMU6 , RULL(0x05013421), SH_UNT , + SH_ACS_SCOM_WCLRREG ); -REG64( PU_PB_ELINK_PMU7 , RULL(0x05013422), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_PB_ELINK_PMU7 , RULL(0x05013422), SH_UNT , + SH_ACS_SCOM_WCLRREG ); REG64( PU_PB_ELINK_PMU_CTL_REG , RULL(0x0501341A), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_PB_ELINK_RT_DELAY_CTL_REG , RULL(0x05013419), SH_UNT , SH_ACS_SCOM ); -REG64( PU_PB_ELINK_SYN_01_REG , RULL(0x05013414), SH_UNT , - SH_ACS_SCOM_WCLEAR ); +REG64( PU_PB_ELINK_SYN_01_REG , RULL(0x05013414), SH_UNT , SH_ACS_SCOM_RO ); -REG64( PU_PB_ELINK_SYN_23_REG , RULL(0x05013415), SH_UNT , - SH_ACS_SCOM_WCLEAR ); +REG64( PU_PB_ELINK_SYN_23_REG , RULL(0x05013415), SH_UNT , SH_ACS_SCOM_RO ); -REG64( PU_PB_ELINK_SYN_45_REG , RULL(0x05013416), SH_UNT , - SH_ACS_SCOM_WCLEAR ); +REG64( PU_PB_ELINK_SYN_45_REG , RULL(0x05013416), SH_UNT , SH_ACS_SCOM_RO ); REG64( PU_PB_EN_DOB_ECC_ERR_REG , RULL(0x05013418), SH_UNT , SH_ACS_SCOM_RO ); REG64( PU_IOE_PB_EN_DOB_ECC_ERR_REG , RULL(0x05013818), SH_UNT_PU_IOE , SH_ACS_SCOM_RO ); @@ -6526,37 +6739,44 @@ REG64( PU_IOE_PB_OLINK_DLY_0123_REG , RULL(0x0501380E REG64( PU_IOE_PB_OLINK_DLY_4567_REG , RULL(0x0501380F), SH_UNT_PU_IOE , SH_ACS_SCOM_RO ); -REG64( PU_IOE_PB_OLINK_PMU0 , RULL(0x0501381B), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); +REG64( PU_IOE_PB_OLINK_PMU0 , RULL(0x0501381B), SH_UNT_PU_IOE , + SH_ACS_SCOM_WCLRREG ); -REG64( PU_IOE_PB_OLINK_PMU1 , RULL(0x0501381C), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); +REG64( PU_IOE_PB_OLINK_PMU1 , RULL(0x0501381C), SH_UNT_PU_IOE , + SH_ACS_SCOM_WCLRREG ); -REG64( PU_IOE_PB_OLINK_PMU2 , RULL(0x0501381D), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); +REG64( PU_IOE_PB_OLINK_PMU2 , RULL(0x0501381D), SH_UNT_PU_IOE , + SH_ACS_SCOM_WCLRREG ); -REG64( PU_IOE_PB_OLINK_PMU3 , RULL(0x0501381E), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); +REG64( PU_IOE_PB_OLINK_PMU3 , RULL(0x0501381E), SH_UNT_PU_IOE , + SH_ACS_SCOM_WCLRREG ); -REG64( PU_IOE_PB_OLINK_PMU4 , RULL(0x0501381F), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); +REG64( PU_IOE_PB_OLINK_PMU4 , RULL(0x0501381F), SH_UNT_PU_IOE , + SH_ACS_SCOM_WCLRREG ); -REG64( PU_IOE_PB_OLINK_PMU5 , RULL(0x05013820), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); +REG64( PU_IOE_PB_OLINK_PMU5 , RULL(0x05013820), SH_UNT_PU_IOE , + SH_ACS_SCOM_WCLRREG ); -REG64( PU_IOE_PB_OLINK_PMU6 , RULL(0x05013821), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); +REG64( PU_IOE_PB_OLINK_PMU6 , RULL(0x05013821), SH_UNT_PU_IOE , + SH_ACS_SCOM_WCLRREG ); -REG64( PU_IOE_PB_OLINK_PMU7 , RULL(0x05013822), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); +REG64( PU_IOE_PB_OLINK_PMU7 , RULL(0x05013822), SH_UNT_PU_IOE , + SH_ACS_SCOM_WCLRREG ); REG64( PU_IOE_PB_OLINK_PMU_CTL_REG , RULL(0x0501381A), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); REG64( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG , RULL(0x05013819), SH_UNT_PU_IOE , SH_ACS_SCOM ); -REG64( PU_IOE_PB_OLINK_SYN_01_REG , RULL(0x05013814), SH_UNT_PU_IOE , - SH_ACS_SCOM_WCLEAR ); +REG64( PU_IOE_PB_OLINK_SYN_01_REG , RULL(0x05013814), SH_UNT_PU_IOE , SH_ACS_SCOM_RO ); -REG64( PU_IOE_PB_OLINK_SYN_23_REG , RULL(0x05013815), SH_UNT_PU_IOE , - SH_ACS_SCOM_WCLEAR ); +REG64( PU_IOE_PB_OLINK_SYN_23_REG , RULL(0x05013815), SH_UNT_PU_IOE , SH_ACS_SCOM_RO ); -REG64( PU_IOE_PB_OLINK_SYN_45_REG , RULL(0x05013816), SH_UNT_PU_IOE , - SH_ACS_SCOM_WCLEAR ); +REG64( PU_IOE_PB_OLINK_SYN_45_REG , RULL(0x05013816), SH_UNT_PU_IOE , SH_ACS_SCOM_RO ); -REG64( PU_IOE_PB_OLINK_SYN_67_REG , RULL(0x05013817), SH_UNT_PU_IOE , - SH_ACS_SCOM_WCLEAR ); +REG64( PU_IOE_PB_OLINK_SYN_67_REG , RULL(0x05013817), SH_UNT_PU_IOE , SH_ACS_SCOM_RO ); + +REG64( PU_PB_PERFTRACE_CFG_REG , RULL(0x05013429), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_IOE_PB_PERFTRACE_CFG_REG , RULL(0x05013829), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); REG64( PU_PB_PR0123_ERR , RULL(0x05013427), SH_UNT , SH_ACS_SCOM_RO ); REG64( PU_IOE_PB_PR0123_ERR , RULL(0x05013827), SH_UNT_PU_IOE , SH_ACS_SCOM_RO ); @@ -6568,147 +6788,87 @@ REG64( PU_PB_PR45_ERR , RULL(0x05013428 REG64( PU_PB_TRACE_CFG , RULL(0x05013424), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_IOE_PB_TRACE_CFG , RULL(0x05013824), SH_UNT_PU_IOE , SH_ACS_SCOM_RW ); +REG64( _SM0_PB_WEST_FIR_ACTION0_REG , RULL(0x05011806), SH_UNT__SM0 , SH_ACS_SCOM_RW ); + +REG64( _SM0_PB_WEST_FIR_ACTION1_REG , RULL(0x05011807), SH_UNT__SM0 , SH_ACS_SCOM_RW ); + +REG64( _SM0_PB_WEST_FIR_MASK_REG , RULL(0x05011803), SH_UNT__SM0 , SH_ACS_SCOM_RW ); +REG64( _SM0_PB_WEST_FIR_MASK_REG_AND , RULL(0x05011804), SH_UNT__SM0 , SH_ACS_SCOM1_AND ); +REG64( _SM0_PB_WEST_FIR_MASK_REG_OR , RULL(0x05011805), SH_UNT__SM0 , SH_ACS_SCOM2_OR ); + +REG64( _SM0_PB_WEST_FIR_REG , RULL(0x05011800), SH_UNT__SM0 , SH_ACS_SCOM_RW ); +REG64( _SM0_PB_WEST_FIR_REG_AND , RULL(0x05011801), SH_UNT__SM0 , SH_ACS_SCOM1_AND ); +REG64( _SM0_PB_WEST_FIR_REG_OR , RULL(0x05011802), SH_UNT__SM0 , SH_ACS_SCOM2_OR ); + REG64( PEC_PCS_M1_CONTROL_REG , RULL(0x80000C010D010C3F), SH_UNT_PEC , SH_ACS_SCOM ); -REG64( PEC_0_PCS_M1_CONTROL_REG , RULL(0x80000C010D010C3F), SH_UNT_PEC_0 , - SH_ACS_SCOM ); -REG64( PEC_1_PCS_M1_CONTROL_REG , RULL(0x80000C010E010C3F), SH_UNT_PEC_1 , - SH_ACS_SCOM ); -REG64( PEC_2_PCS_M1_CONTROL_REG , RULL(0x80000C010F010C3F), SH_UNT_PEC_2 , - SH_ACS_SCOM ); REG64( PEC_PCS_M2_CONTROL_REG , RULL(0x80000C020D010C3F), SH_UNT_PEC , SH_ACS_SCOM ); -REG64( PEC_0_PCS_M2_CONTROL_REG , RULL(0x80000C020D010C3F), SH_UNT_PEC_0 , - SH_ACS_SCOM ); -REG64( PEC_1_PCS_M2_CONTROL_REG , RULL(0x80000C020E010C3F), SH_UNT_PEC_1 , - SH_ACS_SCOM ); -REG64( PEC_2_PCS_M2_CONTROL_REG , RULL(0x80000C020F010C3F), SH_UNT_PEC_2 , - SH_ACS_SCOM ); REG64( PEC_PCS_M3_CONTROL_REG , RULL(0x80000C030D010C3F), SH_UNT_PEC , SH_ACS_SCOM ); -REG64( PEC_0_PCS_M3_CONTROL_REG , RULL(0x80000C030D010C3F), SH_UNT_PEC_0 , - SH_ACS_SCOM ); -REG64( PEC_1_PCS_M3_CONTROL_REG , RULL(0x80000C030E010C3F), SH_UNT_PEC_1 , - SH_ACS_SCOM ); -REG64( PEC_2_PCS_M3_CONTROL_REG , RULL(0x80000C030F010C3F), SH_UNT_PEC_2 , - SH_ACS_SCOM ); REG64( PEC_PCS_M4_CONTROL_REG , RULL(0x80000C040D010C3F), SH_UNT_PEC , SH_ACS_SCOM ); -REG64( PEC_0_PCS_M4_CONTROL_REG , RULL(0x80000C040D010C3F), SH_UNT_PEC_0 , - SH_ACS_SCOM ); -REG64( PEC_1_PCS_M4_CONTROL_REG , RULL(0x80000C040E010C3F), SH_UNT_PEC_1 , - SH_ACS_SCOM ); -REG64( PEC_2_PCS_M4_CONTROL_REG , RULL(0x80000C040F010C3F), SH_UNT_PEC_2 , - SH_ACS_SCOM ); REG64( PEC_PCS_SYS_CONTROL_REG , RULL(0x80000C000D010C3F), SH_UNT_PEC , SH_ACS_SCOM ); -REG64( PEC_0_PCS_SYS_CONTROL_REG , RULL(0x80000C000D010C3F), SH_UNT_PEC_0 , - SH_ACS_SCOM ); -REG64( PEC_1_PCS_SYS_CONTROL_REG , RULL(0x80000C000E010C3F), SH_UNT_PEC_1 , - SH_ACS_SCOM ); -REG64( PEC_2_PCS_SYS_CONTROL_REG , RULL(0x80000C000F010C3F), SH_UNT_PEC_2 , - SH_ACS_SCOM ); -REG64( PEC_PECAPP_CNTL_REG , RULL(0x0D010800), SH_UNT_PEC , SH_ACS_SCOM_RW ); -REG64( PEC_0_PECAPP_CNTL_REG , RULL(0x0D010800), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); -REG64( PEC_1_PECAPP_CNTL_REG , RULL(0x0E010800), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); -REG64( PEC_2_PECAPP_CNTL_REG , RULL(0x0F010800), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); +REG64( PEC_PECAPP_CNTL_REG , RULL(0x04010C07), SH_UNT_PEC , SH_ACS_SCOM_RW ); REG64( PEC_PECAPP_SEC_BAR , RULL(0x0D010801), SH_UNT_PEC , SH_ACS_SCOM ); -REG64( PEC_0_PECAPP_SEC_BAR , RULL(0x0D010801), SH_UNT_PEC_0 , SH_ACS_SCOM ); -REG64( PEC_1_PECAPP_SEC_BAR , RULL(0x0E010801), SH_UNT_PEC_1 , SH_ACS_SCOM ); -REG64( PEC_2_PECAPP_SEC_BAR , RULL(0x0F010801), SH_UNT_PEC_2 , SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_PERF2_CONFIG , RULL(0x05011016), SH_UNT_PU_NPU0_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_PERF2_CONFIG , RULL(0x05011036), SH_UNT_PU_NPU0_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_PERF2_CONFIG , RULL(0x05011056), SH_UNT_PU_NPU0_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_PERF2_CONFIG , RULL(0x05011076), SH_UNT_PU_NPU0_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_PERF2_CONFIG , RULL(0x05011116), SH_UNT_PU_NPU1_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_PERF2_CONFIG , RULL(0x05011136), SH_UNT_PU_NPU1_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_PERF2_CONFIG , RULL(0x05011156), SH_UNT_PU_NPU1_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_PERF2_CONFIG , RULL(0x05011176), SH_UNT_PU_NPU1_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_PERF2_CONFIG , RULL(0x05011216), SH_UNT_PU_NPU2_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_PERF2_CONFIG , RULL(0x05011236), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU0_CTL_PERF_CONFIG , RULL(0x05011087), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_PERF2_CONFIG , RULL(0x05011256), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU1_CTL_PERF_CONFIG , RULL(0x05011187), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_PERF2_CONFIG , RULL(0x05011276), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_CTL_PERF_CONFIG , RULL(0x05011287), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); - -REG64( PU_NPU0_SM0_PERF3_CONFIG , RULL(0x05011017), SH_UNT_PU_NPU0_SM0, +REG64( PU_NPU0_SM0_PERF_CONFIG , RULL(0x0501100F), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_PERF3_CONFIG , RULL(0x05011037), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_PERF_CONFIG , RULL(0x0501102F), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_PERF3_CONFIG , RULL(0x05011057), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_PERF_CONFIG , RULL(0x0501104F), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_PERF3_CONFIG , RULL(0x05011077), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_PERF_CONFIG , RULL(0x0501106F), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_PERF3_CONFIG , RULL(0x05011117), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_PERF_CONFIG , RULL(0x0501110F), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_PERF3_CONFIG , RULL(0x05011137), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_PERF_CONFIG , RULL(0x0501112F), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_PERF3_CONFIG , RULL(0x05011157), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_PERF_CONFIG , RULL(0x0501114F), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_PERF3_CONFIG , RULL(0x05011177), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_PERF_CONFIG , RULL(0x0501116F), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_PERF3_CONFIG , RULL(0x05011217), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_PERF_CONFIG , RULL(0x0501120F), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_PERF3_CONFIG , RULL(0x05011237), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_PERF_CONFIG , RULL(0x0501122F), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_PERF3_CONFIG , RULL(0x05011257), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_PERF_CONFIG , RULL(0x0501124F), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_PERF3_CONFIG , RULL(0x05011277), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_PERF_CONFIG , RULL(0x0501126F), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); -REG64( PU_NPU0_CTL_PERF_CONFIG , RULL(0x05011087), SH_UNT_PU_NPU0_CTL, - SH_ACS_SCOM ); -REG64( PU_NPU1_CTL_PERF_CONFIG , RULL(0x05011187), SH_UNT_PU_NPU1_CTL, - SH_ACS_SCOM ); -REG64( PU_NPU2_CTL_PERF_CONFIG , RULL(0x05011287), SH_UNT_PU_NPU2_CTL, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_PERF_CONFIG , RULL(0x05011007), SH_UNT_PU_NPU0_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_PERF_CONFIG , RULL(0x05011027), SH_UNT_PU_NPU0_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_PERF_CONFIG , RULL(0x05011047), SH_UNT_PU_NPU0_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_PERF_CONFIG , RULL(0x05011067), SH_UNT_PU_NPU0_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_PERF_CONFIG , RULL(0x05011107), SH_UNT_PU_NPU1_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_PERF_CONFIG , RULL(0x05011127), SH_UNT_PU_NPU1_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_PERF_CONFIG , RULL(0x05011147), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU0_CTL_PERF_COUNT , RULL(0x05011086), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_PERF_CONFIG , RULL(0x05011167), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_CTL_PERF_COUNT , RULL(0x05011186), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_PERF_CONFIG , RULL(0x05011207), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_CTL_PERF_COUNT , RULL(0x05011286), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_PERF_CONFIG , RULL(0x05011227), SH_UNT_PU_NPU2_SM1, + +REG64( PU_NPU0_CTL_PERF_MASK_CONFIG , RULL(0x05011085), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_PERF_CONFIG , RULL(0x05011247), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU1_CTL_PERF_MASK_CONFIG , RULL(0x05011185), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_PERF_CONFIG , RULL(0x05011267), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_CTL_PERF_MASK_CONFIG , RULL(0x05011285), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); -REG64( PU_NPU0_CTL_PERF_COUNT , RULL(0x05011086), SH_UNT_PU_NPU0_CTL, +REG64( PU_NPU0_CTL_PERF_MATCH_CONFIG , RULL(0x05011084), SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM ); -REG64( PU_NPU1_CTL_PERF_COUNT , RULL(0x05011186), SH_UNT_PU_NPU1_CTL, +REG64( PU_NPU1_CTL_PERF_MATCH_CONFIG , RULL(0x05011184), SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM ); -REG64( PU_NPU2_CTL_PERF_COUNT , RULL(0x05011286), SH_UNT_PU_NPU2_CTL, +REG64( PU_NPU2_CTL_PERF_MATCH_CONFIG , RULL(0x05011284), SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM ); REG64( PU_NPU_NTL0_PESTB_ADDR_PE0 , RULL(0x050113D0), SH_UNT_PU_NPU_NTL0, @@ -6807,30 +6967,14 @@ REG64( PU_NPU_NTL0_PESTB_DATA_PE8 , RULL(0x050113C8 REG64( PU_NPU_NTL0_PESTB_DATA_PE9 , RULL(0x050113C9), SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM ); -REG64( PEC_0_STACK0_PHBBAR_REG , RULL(0x04010C52), SH_UNT_PEC_0_STACK0, - SH_ACS_SCOM ); -REG64( PEC_0_STACK1_PHBBAR_REG , RULL(0x04010C92), SH_UNT_PEC_0_STACK1, - SH_ACS_SCOM ); -REG64( PEC_0_STACK2_PHBBAR_REG , RULL(0x04010CD2), SH_UNT_PEC_0_STACK2, - SH_ACS_SCOM ); -REG64( PEC_1_STACK0_PHBBAR_REG , RULL(0x04011052), SH_UNT_PEC_1_STACK0, - SH_ACS_SCOM ); -REG64( PEC_1_STACK1_PHBBAR_REG , RULL(0x04011092), SH_UNT_PEC_1_STACK1, - SH_ACS_SCOM ); -REG64( PEC_1_STACK2_PHBBAR_REG , RULL(0x040110D2), SH_UNT_PEC_1_STACK2, - SH_ACS_SCOM ); -REG64( PEC_2_STACK0_PHBBAR_REG , RULL(0x04011452), SH_UNT_PEC_2_STACK0, - SH_ACS_SCOM ); -REG64( PEC_2_STACK1_PHBBAR_REG , RULL(0x04011492), SH_UNT_PEC_2_STACK1, - SH_ACS_SCOM ); -REG64( PEC_2_STACK2_PHBBAR_REG , RULL(0x040114D2), SH_UNT_PEC_2_STACK2, - SH_ACS_SCOM ); -REG64( PEC_STACK0_PHBBAR_REG , RULL(0x04010C52), SH_UNT_PEC_STACK0, - SH_ACS_SCOM ); -REG64( PEC_STACK1_PHBBAR_REG , RULL(0x04010C92), SH_UNT_PEC_STACK1, - SH_ACS_SCOM ); -REG64( PEC_STACK2_PHBBAR_REG , RULL(0x04010CD2), SH_UNT_PEC_STACK2, - SH_ACS_SCOM ); +REG64( PHB_PE_DFREEZE_REG , RULL(0x04010C55), SH_UNT_PHB , SH_ACS_SCOM_RW ); +REG64( PHB_0_PE_DFREEZE_REG , RULL(0x04010C55), SH_UNT_PHB_0 , SH_ACS_SCOM_RW ); +REG64( PHB_1_PE_DFREEZE_REG , RULL(0x04011055), SH_UNT_PHB_1 , SH_ACS_SCOM_RW ); +REG64( PHB_2_PE_DFREEZE_REG , RULL(0x04011095), SH_UNT_PHB_2 , SH_ACS_SCOM_RW ); +REG64( PHB_3_PE_DFREEZE_REG , RULL(0x04011455), SH_UNT_PHB_3 , SH_ACS_SCOM_RW ); +REG64( PHB_4_PE_DFREEZE_REG , RULL(0x04011495), SH_UNT_PHB_4 , SH_ACS_SCOM_RW ); +REG64( PHB_5_PE_DFREEZE_REG , RULL(0x040114D5), SH_UNT_PHB_5 , SH_ACS_SCOM_RW ); + REG64( PHB_PHBBAR_REG , RULL(0x04010C52), SH_UNT_PHB , SH_ACS_SCOM ); REG64( PHB_0_PHBBAR_REG , RULL(0x04010C52), SH_UNT_PHB_0 , SH_ACS_SCOM ); REG64( PHB_1_PHBBAR_REG , RULL(0x04011052), SH_UNT_PHB_1 , SH_ACS_SCOM ); @@ -6853,30 +6997,21 @@ REG64( PU_PBAIB_STACK2_PHBRESET_REG , RULL(0x0D0108C0 REG64( PU_PBAIB_STACK5_PHBRESET_REG , RULL(0x0E0108C0), SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW ); -REG64( PU_NPU0_SM0_PHY_BAR , RULL(0x05011010), SH_UNT_PU_NPU0_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_PHY_BAR , RULL(0x05011030), SH_UNT_PU_NPU0_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_PHY_BAR , RULL(0x05011050), SH_UNT_PU_NPU0_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_PHY_BAR , RULL(0x05011070), SH_UNT_PU_NPU0_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_PHY_BAR , RULL(0x05011110), SH_UNT_PU_NPU1_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_PHY_BAR , RULL(0x05011130), SH_UNT_PU_NPU1_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_PHY_BAR , RULL(0x05011150), SH_UNT_PU_NPU1_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_PHY_BAR , RULL(0x05011170), SH_UNT_PU_NPU1_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_PHY_BAR , RULL(0x05011210), SH_UNT_PU_NPU2_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_PHY_BAR , RULL(0x05011230), SH_UNT_PU_NPU2_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_PHY_BAR , RULL(0x05011250), SH_UNT_PU_NPU2_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_PHY_BAR , RULL(0x05011270), SH_UNT_PU_NPU2_SM3, - SH_ACS_SCOM ); +REG64( PU_PIBI2CM_ATOMIC_LOCK_REG_B , RULL(0x000A03FF), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_PIBI2CM_ATOMIC_LOCK_REG_C , RULL(0x000A13FF), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_PIBI2CM_ATOMIC_LOCK_REG_D , RULL(0x000A23FF), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_PIBI2CM_ATOMIC_LOCK_REG_E , RULL(0x000A33FF), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_PIBI2CM_PROTECT_MODE_REG_B , RULL(0x000A03FE), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_PIBI2CM_PROTECT_MODE_REG_C , RULL(0x000A13FE), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_PIBI2CM_PROTECT_MODE_REG_D , RULL(0x000A23FE), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_PIBI2CM_PROTECT_MODE_REG_E , RULL(0x000A33FE), SH_UNT , SH_ACS_SCOM ); REG64( PU_PIBMEM_ADDRESS_REGISTER , RULL(0x00088001), SH_UNT , SH_ACS_SCOM ); @@ -6890,48 +7025,87 @@ REG64( PU_PIBMEM_REPAIR_REGISTER_1 , RULL(0x0008800C REG64( PU_PIBMEM_REPAIR_REGISTER_2 , RULL(0x0008800D), SH_UNT , SH_ACS_SCOM ); +REG64( PU_PIBMEM_REPAIR_REGISTER_3 , RULL(0x0008800E), SH_UNT , SH_ACS_SCOM ); + REG64( PU_PIBMEM_RESET_REGISTER , RULL(0x00088006), SH_UNT , SH_ACS_SCOM ); REG64( PU_PIBMEM_STATUS_REG , RULL(0x00088005), SH_UNT , SH_ACS_SCOM ); -REG64( PEC_PMONCTL_REG , RULL(0x04010C04), SH_UNT_PEC , SH_ACS_SCOM_RW ); -REG64( PEC_0_PMONCTL_REG , RULL(0x04010C04), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); -REG64( PEC_1_PMONCTL_REG , RULL(0x04011004), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); -REG64( PEC_2_PMONCTL_REG , RULL(0x04011404), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); - -REG64( PU_PPE_XIDBGPRO , RULL(0x000E0005), SH_UNT , SH_ACS_SCOM ); +REG64( PEC_PLL_LOCK_REG , RULL(0x0D0F0019), SH_UNT_PEC , SH_ACS_SCOM ); -REG64( PU_IOPPE_PPE_XIDBGPRO , RULL(0x06010805), SH_UNT_PU_IOPPE , SH_ACS_SCOM ); +REG64( PEC_PMONCTL_REG , RULL(0x04010C04), SH_UNT_PEC , SH_ACS_SCOM_RW ); -REG64( PU_PPE_XIRAMDBG , RULL(0x000E0003), SH_UNT , SH_ACS_SCOM ); +REG64( CAPP_PMU_CNTRA_CFG , RULL(0x02010814), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_PMU_CNTRA_CFG , RULL(0x02010814), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_PMU_CNTRA_CFG , RULL(0x04010814), SH_UNT_CAPP_1 , SH_ACS_SCOM ); -REG64( PU_IOPPE_PPE_XIRAMDBG , RULL(0x06010803), SH_UNT_PU_IOPPE , SH_ACS_SCOM ); +REG64( CAPP_PMU_CNTRA_REG , RULL(0x02010815), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_PMU_CNTRA_REG , RULL(0x02010815), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_PMU_CNTRA_REG , RULL(0x04010815), SH_UNT_CAPP_1 , SH_ACS_SCOM ); -REG64( PU_PPE_XIRAMEDR , RULL(0x000E0004), SH_UNT , SH_ACS_SCOM ); +REG64( CAPP_PMU_CNTRB_CFG , RULL(0x02010824), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_PMU_CNTRB_CFG , RULL(0x02010824), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_PMU_CNTRB_CFG , RULL(0x04010824), SH_UNT_CAPP_1 , SH_ACS_SCOM ); -REG64( PU_IOPPE_PPE_XIRAMEDR , RULL(0x06010804), SH_UNT_PU_IOPPE , SH_ACS_SCOM ); +REG64( CAPP_PMU_CNTRB_REG , RULL(0x02010825), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_PMU_CNTRB_REG , RULL(0x02010825), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_PMU_CNTRB_REG , RULL(0x04010825), SH_UNT_CAPP_1 , SH_ACS_SCOM ); -REG64( PU_PPE_XIRAMGA , RULL(0x000E0002), SH_UNT , SH_ACS_SCOM_WO ); +REG64( PU_PPE_XIDBGPRO , RULL(0x000E0005), SH_UNT , + SH_ACS_SCOM ); //DUPS: 0601084F, -REG64( PU_IOPPE_PPE_XIRAMGA , RULL(0x06010802), SH_UNT_PU_IOPPE , SH_ACS_SCOM_WO ); +REG64( PU_PPE_XIRAMDBG , RULL(0x000E0003), SH_UNT , + SH_ACS_SCOM ); //DUPS: 0601084D, -REG64( PU_PPE_XIRAMRA , RULL(0x000E0001), SH_UNT , SH_ACS_SCOM_WO ); +REG64( PU_PPE_XIRAMEDR , RULL(0x000E0004), SH_UNT , + SH_ACS_SCOM ); //DUPS: 0601084E, -REG64( PU_IOPPE_PPE_XIRAMRA , RULL(0x06010801), SH_UNT_PU_IOPPE , SH_ACS_SCOM_WO ); +REG64( PU_PPE_XIRAMGA , RULL(0x000E0002), SH_UNT , + SH_ACS_SCOM_WO ); //DUPS: 0601084C, -REG64( PU_PPE_XIXCR , RULL(0x000E0000), SH_UNT , SH_ACS_SCOM_WO ); +REG64( PU_PPE_XIRAMRA , RULL(0x000E0001), SH_UNT , + SH_ACS_SCOM_WO ); //DUPS: 0601084B, -REG64( PU_IOPPE_PPE_XIXCR , RULL(0x06010800), SH_UNT_PU_IOPPE , SH_ACS_SCOM_WO ); +REG64( PU_PPE_XIXCR , RULL(0x000E0000), SH_UNT , + SH_ACS_SCOM_WO ); //DUPS: 0601084A, REG64( PEC_PREDV_REG , RULL(0x04010C06), SH_UNT_PEC , SH_ACS_SCOM_RW ); -REG64( PEC_0_PREDV_REG , RULL(0x04010C06), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); -REG64( PEC_1_PREDV_REG , RULL(0x04011006), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); -REG64( PEC_2_PREDV_REG , RULL(0x04011406), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); + +REG64( PEC_PRE_COUNTER_REG , RULL(0x0D0F0028), SH_UNT_PEC , SH_ACS_SCOM ); REG64( PU_PRGM_REGISTER , RULL(0x00010009), SH_UNT , SH_ACS_SCOM ); +REG64( PEC_PRIMARY_ADDRESS_REG , RULL(0x0D0F0000), SH_UNT_PEC , SH_ACS_SCOM ); + REG64( PU_PROBE_PROTECT_STATUS , RULL(0x0001000A), SH_UNT , SH_ACS_SCOM ); +REG64( PEC_PROTECT_MODE_REG , RULL(0x0D0F03FE), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_PRV_MISC_PPE , RULL(0xC0002000), SH_UNT , SH_ACS_PPE ); +REG64( PU_PRV_MISC_PPE1 , RULL(0xC0002010), SH_UNT , SH_ACS_PPE1 ); +REG64( PU_PRV_MISC_PPE2 , RULL(0xC0002018), SH_UNT , SH_ACS_PPE2 ); + +REG64( PEC_PSCOM_ERROR_MASK , RULL(0x0D010002), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_PSCOM_ERROR_MASK , RULL(0x02010002), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_PSCOM_ERROR_MASK , RULL(0x03010002), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_PSCOM_ERROR_MASK , RULL(0x04010002), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_PSCOM_ERROR_MASK , RULL(0x05010002), SH_UNT_PU_N3 , SH_ACS_SCOM ); + +REG64( PEC_PSCOM_MODE_REG , RULL(0x0D010000), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_PSCOM_MODE_REG , RULL(0x02010000), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_PSCOM_MODE_REG , RULL(0x03010000), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_PSCOM_MODE_REG , RULL(0x04010000), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_PSCOM_MODE_REG , RULL(0x05010000), SH_UNT_PU_N3 , SH_ACS_SCOM ); + +REG64( PEC_PSCOM_STATUS_ERROR_REG , RULL(0x0D010001), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_PSCOM_STATUS_ERROR_REG , RULL(0x02010001), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_PSCOM_STATUS_ERROR_REG , RULL(0x03010001), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_PSCOM_STATUS_ERROR_REG , RULL(0x04010001), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_PSCOM_STATUS_ERROR_REG , RULL(0x05010001), SH_UNT_PU_N3 , SH_ACS_SCOM ); + REG64( PU_PSIHB_DEBUG_REG , RULL(0x05012911), SH_UNT , SH_ACS_SCOM ); REG64( PU_PSIHB_ERROR_MASK_REG , RULL(0x0501290F), SH_UNT , SH_ACS_SCOM ); @@ -6952,7 +7126,7 @@ REG64( PU_PSIHB_INTERRUPT_CONTROL , RULL(0x05012915 REG64( PU_PSIHB_INTERRUPT_LEVEL , RULL(0x05012919), SH_UNT , SH_ACS_SCOM ); -REG64( PU_PSIHB_INTERRUPT_STATUS , RULL(0x05012920), SH_UNT , SH_ACS_SCOM ); +REG64( PU_PSIHB_INTERRUPT_STATUS , RULL(0x0501291A), SH_UNT , SH_ACS_SCOM ); REG64( PU_PSIHB_STATUS_CTL_REG_SCOM , RULL(0x0501290E), SH_UNT , SH_ACS_SCOM ); REG64( PU_PSIHB_STATUS_CTL_REG_SCOM1 , RULL(0x05012912), SH_UNT , SH_ACS_SCOM1 ); @@ -6964,7 +7138,23 @@ REG64( PU_PSI_BRIDGE_FSP_BAR_REG , RULL(0x0501290B REG64( PU_PSI_FSP_MMR_REG , RULL(0x0501290C), SH_UNT , SH_ACS_SCOM ); -REG64( PU_PSI_TCE_ADDR_REG , RULL(0x05015F44), SH_UNT , SH_ACS_SCOM ); +REG64( PU_PSI_TCE_ADDR_REG , RULL(0x05012B44), SH_UNT , SH_ACS_SCOM ); + +REG64( CAPP_PSLTTMAP0 , RULL(0x0201082D), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_PSLTTMAP0 , RULL(0x0201082D), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_PSLTTMAP0 , RULL(0x0401082D), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_PSLTTMAP1 , RULL(0x0201082E), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_PSLTTMAP1 , RULL(0x0201082E), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_PSLTTMAP1 , RULL(0x0401082E), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_PSLTTMAP2 , RULL(0x0201082F), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_PSLTTMAP2 , RULL(0x0201082F), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_PSLTTMAP2 , RULL(0x0401082F), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_PSLTTMAP3 , RULL(0x02010830), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_PSLTTMAP3 , RULL(0x02010830), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_PSLTTMAP3 , RULL(0x04010830), SH_UNT_CAPP_1 , SH_ACS_SCOM ); REG64( PU_PSU_HOST_DOORBELL_REG , RULL(0x000D0063), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_PSU_HOST_DOORBELL_REG_AND , RULL(0x000D0064), SH_UNT , SH_ACS_SCOM1_AND ); @@ -7050,55 +7240,15 @@ REG64( PU_PSU_SBE_DOORBELL_REG , RULL(0x000D0060 REG64( PU_PSU_SBE_DOORBELL_REG_AND , RULL(0x000D0061), SH_UNT , SH_ACS_SCOM1_AND ); REG64( PU_PSU_SBE_DOORBELL_REG_OR , RULL(0x000D0062), SH_UNT , SH_ACS_SCOM2_OR ); -REG64( PU_NPU0_SM0_RELAXED_CMD , RULL(0x05011006), SH_UNT_PU_NPU0_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_RELAXED_CMD , RULL(0x05011026), SH_UNT_PU_NPU0_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_RELAXED_CMD , RULL(0x05011046), SH_UNT_PU_NPU0_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_RELAXED_CMD , RULL(0x05011066), SH_UNT_PU_NPU0_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_RELAXED_CMD , RULL(0x05011106), SH_UNT_PU_NPU1_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_RELAXED_CMD , RULL(0x05011126), SH_UNT_PU_NPU1_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_RELAXED_CMD , RULL(0x05011146), SH_UNT_PU_NPU1_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_RELAXED_CMD , RULL(0x05011166), SH_UNT_PU_NPU1_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_RELAXED_CMD , RULL(0x05011206), SH_UNT_PU_NPU2_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_RELAXED_CMD , RULL(0x05011226), SH_UNT_PU_NPU2_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_RELAXED_CMD , RULL(0x05011246), SH_UNT_PU_NPU2_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_RELAXED_CMD , RULL(0x05011266), SH_UNT_PU_NPU2_SM3, - SH_ACS_SCOM ); +REG64( PEC_RECOV_INTERRUPT_REG , RULL(0x0D0F001B), SH_UNT_PEC , SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_RELAXED_SOURCE , RULL(0x05011005), SH_UNT_PU_NPU0_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_RELAXED_SOURCE , RULL(0x05011025), SH_UNT_PU_NPU0_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_RELAXED_SOURCE , RULL(0x05011045), SH_UNT_PU_NPU0_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_RELAXED_SOURCE , RULL(0x05011065), SH_UNT_PU_NPU0_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_RELAXED_SOURCE , RULL(0x05011105), SH_UNT_PU_NPU1_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_RELAXED_SOURCE , RULL(0x05011125), SH_UNT_PU_NPU1_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_RELAXED_SOURCE , RULL(0x05011145), SH_UNT_PU_NPU1_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_RELAXED_SOURCE , RULL(0x05011165), SH_UNT_PU_NPU1_SM3, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_RELAXED_SOURCE , RULL(0x05011205), SH_UNT_PU_NPU2_SM0, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_RELAXED_SOURCE , RULL(0x05011225), SH_UNT_PU_NPU2_SM1, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_RELAXED_SOURCE , RULL(0x05011245), SH_UNT_PU_NPU2_SM2, - SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_RELAXED_SOURCE , RULL(0x05011265), SH_UNT_PU_NPU2_SM3, - SH_ACS_SCOM ); +REG64( PU_NPU0_REM0 , RULL(0x050110AD), SH_UNT_PU_NPU0 , SH_ACS_SCOM ); +REG64( PU_NPU1_REM0 , RULL(0x050111AD), SH_UNT_PU_NPU1 , SH_ACS_SCOM ); +REG64( PU_NPU2_REM0 , RULL(0x050112AD), SH_UNT_PU_NPU2 , SH_ACS_SCOM ); + +REG64( PU_NPU0_REM1 , RULL(0x050110AE), SH_UNT_PU_NPU0 , SH_ACS_SCOM ); +REG64( PU_NPU1_REM1 , RULL(0x050111AE), SH_UNT_PU_NPU1 , SH_ACS_SCOM ); +REG64( PU_NPU2_REM1 , RULL(0x050112AE), SH_UNT_PU_NPU2 , SH_ACS_SCOM ); REG64( PU_RESET_REGISTER_B , RULL(0x000A0001), SH_UNT , SH_ACS_SCOM ); //WARNING - VALUE SET SAME AS ANOTHER REG @@ -7124,6 +7274,15 @@ REG64( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D , RULL(0x000A200D REG64( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E , RULL(0x000A300D), SH_UNT , SH_ACS_SCOM ); //WARNING - VALUE SET SAME AS ANOTHER REG +REG64( PEC_RFIR , RULL(0x0D040001), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_RING_FENCE_MASK_LATCH_REG , RULL(0x0D010008), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_RING_FENCE_MASK_LATCH_REG , RULL(0x02010008), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_RING_FENCE_MASK_LATCH_REG , RULL(0x03010008), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_RING_FENCE_MASK_LATCH_REG , RULL(0x04010008), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_RING_FENCE_MASK_LATCH_REG , RULL(0x05010008), SH_UNT_PU_N3 , SH_ACS_SCOM ); + REG64( PU_NPU_CTL_RLX_CONFIG , RULL(0x05011381), SH_UNT_PU_NPU_CTL, SH_ACS_SCOM ); @@ -7157,16 +7316,34 @@ REG64( PU_RX_PSI_MODE , RULL(0x04011821 REG64( PU_RX_PSI_STATUS , RULL(0x04011822), SH_UNT , SH_ACS_SCOM ); -REG64( PU_NPU0_SCRATCH0 , RULL(0x050110AE), SH_UNT_PU_NPU0 , SH_ACS_SCOM ); -REG64( PU_NPU1_SCRATCH0 , RULL(0x050111AE), SH_UNT_PU_NPU1 , SH_ACS_SCOM ); -REG64( PU_NPU2_SCRATCH0 , RULL(0x050112AE), SH_UNT_PU_NPU2 , SH_ACS_SCOM ); +REG64( PEC_SCAN_REGION_TYPE , RULL(0x0D030005), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_SCOM_PPE_CNTL , RULL(0x06010860), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_SCOM_PPE_FLAGS , RULL(0x06010863), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PU_SCOM_PPE_FLAGS_OR , RULL(0x06010864), SH_UNT , SH_ACS_SCOM1_OR ); +REG64( PU_SCOM_PPE_FLAGS_CLEAR , RULL(0x06010865), SH_UNT , + SH_ACS_SCOM2_CLEAR ); + +REG64( PU_SCOM_PPE_WORK_REG1 , RULL(0x06010861), SH_UNT , SH_ACS_SCOM ); +REG64( PU_SCOM_PPE_WORK_REG2 , RULL(0x06010862), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_SCRATCH0_PPE , RULL(0xC0001000), SH_UNT , SH_ACS_PPE ); +REG64( PU_SCRATCH0_PPE1 , RULL(0xC0001010), SH_UNT , SH_ACS_PPE1 ); +REG64( PU_SCRATCH0_PPE2 , RULL(0xC0001018), SH_UNT , SH_ACS_PPE2 ); +REG64( PU_NPU0_SCRATCH0 , RULL(0x050110A3), SH_UNT_PU_NPU0 , SH_ACS_SCOM ); +REG64( PU_NPU1_SCRATCH0 , RULL(0x050111A3), SH_UNT_PU_NPU1 , SH_ACS_SCOM ); +REG64( PU_NPU2_SCRATCH0 , RULL(0x050112A3), SH_UNT_PU_NPU2 , SH_ACS_SCOM ); + +REG64( PU_SCRATCH1_PPE , RULL(0xC0001020), SH_UNT , SH_ACS_PPE ); +REG64( PU_SCRATCH1_PPE1 , RULL(0xC0001030), SH_UNT , SH_ACS_PPE1 ); +REG64( PU_SCRATCH1_PPE2 , RULL(0xC0001038), SH_UNT , SH_ACS_PPE2 ); REG64( NV_SCRATCH1 , RULL(0x050110D4), SH_UNT_NV , SH_ACS_SCOM ); REG64( NV_0_SCRATCH1 , RULL(0x050110D4), SH_UNT_NV_0 , SH_ACS_SCOM ); REG64( NV_1_SCRATCH1 , RULL(0x050110F4), SH_UNT_NV_1 , SH_ACS_SCOM ); REG64( NV_2_SCRATCH1 , RULL(0x050111D4), SH_UNT_NV_2 , SH_ACS_SCOM ); REG64( NV_3_SCRATCH1 , RULL(0x050111F4), SH_UNT_NV_3 , SH_ACS_SCOM ); - REG64( PU_NPU0_DAT_SCRATCH1 , RULL(0x050110BC), SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM ); REG64( PU_NPU1_DAT_SCRATCH1 , RULL(0x050111BC), SH_UNT_PU_NPU1_DAT, @@ -7178,34 +7355,90 @@ REG64( PU_NPU2_NTL0_SCRATCH1 , RULL(0x050112D4 REG64( PU_NPU2_NTL1_SCRATCH1 , RULL(0x050112F4), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM ); +REG64( PU_SCRATCH2_PPE , RULL(0xC0001040), SH_UNT , SH_ACS_PPE ); +REG64( PU_SCRATCH2_PPE1 , RULL(0xC0001050), SH_UNT , SH_ACS_PPE1 ); +REG64( PU_SCRATCH2_PPE2 , RULL(0xC0001058), SH_UNT , SH_ACS_PPE2 ); REG64( NV_SCRATCH2 , RULL(0x050110CC), SH_UNT_NV , SH_ACS_SCOM ); REG64( NV_0_SCRATCH2 , RULL(0x050110CC), SH_UNT_NV_0 , SH_ACS_SCOM ); REG64( NV_1_SCRATCH2 , RULL(0x050110EC), SH_UNT_NV_1 , SH_ACS_SCOM ); REG64( NV_2_SCRATCH2 , RULL(0x050111CC), SH_UNT_NV_2 , SH_ACS_SCOM ); REG64( NV_3_SCRATCH2 , RULL(0x050111EC), SH_UNT_NV_3 , SH_ACS_SCOM ); - REG64( PU_NPU2_NTL0_SCRATCH2 , RULL(0x050112CC), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM ); REG64( PU_NPU2_NTL1_SCRATCH2 , RULL(0x050112EC), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM ); +REG64( PU_SCRATCH3_PPE , RULL(0xC0001060), SH_UNT , SH_ACS_PPE ); +REG64( PU_SCRATCH3_PPE1 , RULL(0xC0001070), SH_UNT , SH_ACS_PPE1 ); +REG64( PU_SCRATCH3_PPE2 , RULL(0xC0001078), SH_UNT , SH_ACS_PPE2 ); REG64( NV_SCRATCH3 , RULL(0x050110CD), SH_UNT_NV , SH_ACS_SCOM ); REG64( NV_0_SCRATCH3 , RULL(0x050110CD), SH_UNT_NV_0 , SH_ACS_SCOM ); REG64( NV_1_SCRATCH3 , RULL(0x050110ED), SH_UNT_NV_1 , SH_ACS_SCOM ); REG64( NV_2_SCRATCH3 , RULL(0x050111CD), SH_UNT_NV_2 , SH_ACS_SCOM ); REG64( NV_3_SCRATCH3 , RULL(0x050111ED), SH_UNT_NV_3 , SH_ACS_SCOM ); - REG64( PU_NPU2_NTL0_SCRATCH3 , RULL(0x050112CD), SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM ); REG64( PU_NPU2_NTL1_SCRATCH3 , RULL(0x050112ED), SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM ); +REG64( PEC_SECURE_PIB_MASTER_ID_REG , RULL(0x0D010009), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_SECURE_PIB_MASTER_ID_REG , RULL(0x02010009), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_SECURE_PIB_MASTER_ID_REG , RULL(0x03010009), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_SECURE_PIB_MASTER_ID_REG , RULL(0x04010009), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_SECURE_PIB_MASTER_ID_REG , RULL(0x05010009), SH_UNT_PU_N3 , SH_ACS_SCOM ); + REG64( PU_SECURITY_SWITCH_REGISTER_WOR , RULL(0x00010005), SH_UNT , SH_ACS_SCOM_WOR ); REG64( PU_SECURITY_SWITCH_REGISTER_CLEAR , RULL(0x00010006), SH_UNT , SH_ACS_SCOM1_CLEAR ); REG64( PU_SEND_WC_BASE_ADDR , RULL(0x020110D2), SH_UNT , SH_ACS_SCOM ); +REG64( PEC_SKITTER_CLKSRC_REG , RULL(0x0D050016), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_SKITTER_DATA0 , RULL(0x0D050019), SH_UNT_PEC , SH_ACS_SCOM_RO ); + +REG64( PEC_SKITTER_DATA1 , RULL(0x0D05001A), SH_UNT_PEC , SH_ACS_SCOM_RO ); + +REG64( PEC_SKITTER_DATA2 , RULL(0x0D05001B), SH_UNT_PEC , SH_ACS_SCOM_RO ); + +REG64( PEC_SKITTER_FORCE_REG , RULL(0x0D050014), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_SKITTER_MODE_REG , RULL(0x0D050010), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_SLAVE_CONFIG_REG , RULL(0x0D0F001E), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_NPU0_SM0_SM_STATUS , RULL(0x05011016), SH_UNT_PU_NPU0_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM1_SM_STATUS , RULL(0x05011036), SH_UNT_PU_NPU0_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM2_SM_STATUS , RULL(0x05011056), SH_UNT_PU_NPU0_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU0_SM3_SM_STATUS , RULL(0x05011076), SH_UNT_PU_NPU0_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM0_SM_STATUS , RULL(0x05011116), SH_UNT_PU_NPU1_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM1_SM_STATUS , RULL(0x05011136), SH_UNT_PU_NPU1_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM2_SM_STATUS , RULL(0x05011156), SH_UNT_PU_NPU1_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU1_SM3_SM_STATUS , RULL(0x05011176), SH_UNT_PU_NPU1_SM3, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM0_SM_STATUS , RULL(0x05011216), SH_UNT_PU_NPU2_SM0, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM1_SM_STATUS , RULL(0x05011236), SH_UNT_PU_NPU2_SM1, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM2_SM_STATUS , RULL(0x05011256), SH_UNT_PU_NPU2_SM2, + SH_ACS_SCOM ); +REG64( PU_NPU2_SM3_SM_STATUS , RULL(0x05011276), SH_UNT_PU_NPU2_SM3, + SH_ACS_SCOM ); + +REG64( PEC_SPATTN_SCOM , RULL(0x0D040004), SH_UNT_PEC , SH_ACS_SCOM_RO ); +REG64( PEC_SPATTN_SCOM1 , RULL(0x0D040005), SH_UNT_PEC , SH_ACS_SCOM1_NC ); +REG64( PEC_SPATTN_SCOM2 , RULL(0x0D040006), SH_UNT_PEC , SH_ACS_SCOM2_NC ); + +REG64( PEC_SPA_MASK , RULL(0x0D040007), SH_UNT_PEC , SH_ACS_SCOM ); + REG64( PU_SPIMPSS_ADC_CTRL_REG0 , RULL(0x00070000), SH_UNT , SH_ACS_SCOM ); REG64( PU_SPIPSS_100NS_REG , RULL(0x00070028), SH_UNT , SH_ACS_SCOM ); @@ -7292,6 +7525,8 @@ REG64( PU_STATUS_REGISTER_ENGINE_D , RULL(0x000A200B REG64( PU_STATUS_REGISTER_ENGINE_E , RULL(0x000A300B), SH_UNT , SH_ACS_SCOM ); //WARNING - VALUE SET SAME AS ANOTHER REG +REG64( PEC_SUM_MASK_REG , RULL(0x0D040017), SH_UNT_PEC , SH_ACS_SCOM ); + REG64( PU_SU_CH0_ABORT_CSB , RULL(0x02011043), SH_UNT , SH_ACS_SCOM_RO ); REG64( PU_SU_CH1_ABORT_CSB , RULL(0x02011045), SH_UNT , SH_ACS_SCOM_RO ); @@ -7338,6 +7573,8 @@ REG64( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL , RULL(0x020110CD REG64( PU_SYM_MAX_BYTE_CNT , RULL(0x0201105A), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PEC_SYNC_CONFIG , RULL(0x0D030000), SH_UNT_PEC , SH_ACS_SCOM ); + REG64( PU_SYNC_FIR_ACTION0_REG , RULL(0x050129C6), SH_UNT , SH_ACS_SCOM_RO ); REG64( PU_SYNC_FIR_ACTION1_REG , RULL(0x050129C7), SH_UNT , SH_ACS_SCOM_RO ); @@ -7353,18 +7590,570 @@ REG64( PU_SYNC_FIR_REG_OR , RULL(0x050129C2 REG64( PU_NPU_SM1_TCE_KILL , RULL(0x05011324), SH_UNT_PU_NPU_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_TEST_CERR , RULL(0x050110AD), SH_UNT_PU_NPU0 , SH_ACS_SCOM ); -REG64( PU_NPU1_TEST_CERR , RULL(0x050111AD), SH_UNT_PU_NPU1 , SH_ACS_SCOM ); -REG64( PU_NPU2_TEST_CERR , RULL(0x050112AD), SH_UNT_PU_NPU2 , SH_ACS_SCOM ); +REG64( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG , RULL(0x02010400), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG , RULL(0x02010401), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG , RULL(0x02010402), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x02010403), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x02010404), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x02010405), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x02010406), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x02010407), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x02010408), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x02010409), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG , RULL(0x02010440), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG , RULL(0x02010441), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG , RULL(0x02010442), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x02010443), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x02010444), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x02010445), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x02010446), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x02010447), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x02010448), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x02010449), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA1_TR0_TRACE_HI_DATA_REG , RULL(0x02010480), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG , RULL(0x02010481), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG , RULL(0x02010482), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x02010483), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x02010484), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x02010485), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x02010486), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x02010487), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x02010488), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x02010489), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG , RULL(0x03010400), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG , RULL(0x03010401), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG , RULL(0x03010402), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x03010403), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x03010404), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x03010405), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x03010406), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x03010407), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x03010408), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x03010409), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG , RULL(0x03010440), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG , RULL(0x03010441), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG , RULL(0x03010442), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x03010443), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x03010444), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x03010445), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x03010446), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x03010447), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x03010448), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x03010449), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG , RULL(0x03010480), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG , RULL(0x03010481), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG , RULL(0x03010482), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x03010483), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x03010484), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x03010485), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x03010486), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x03010487), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x03010488), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x03010489), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG , RULL(0x030104C0), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG , RULL(0x030104C1), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG , RULL(0x030104C2), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x030104C3), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x030104C4), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x030104C5), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x030104C6), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x030104C7), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x030104C8), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x030104C9), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG , RULL(0x03010500), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG , RULL(0x03010501), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG , RULL(0x03010502), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x03010503), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x03010504), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x03010505), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x03010506), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x03010507), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x03010508), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x03010509), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG , RULL(0x03010540), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG , RULL(0x03010541), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG , RULL(0x03010542), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x03010543), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x03010544), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x03010545), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x03010546), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x03010547), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x03010548), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x03010549), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG , RULL(0x03010580), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG , RULL(0x03010581), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG , RULL(0x03010582), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x03010583), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x03010584), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x03010585), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x03010586), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x03010587), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x03010588), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x03010589), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG , RULL(0x030105C0), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG , RULL(0x030105C1), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG , RULL(0x030105C2), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x030105C3), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x030105C4), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x030105C5), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x030105C6), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x030105C7), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x030105C8), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x030105C9), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG , RULL(0x03010600), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG , RULL(0x03010601), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG , RULL(0x03010602), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x03010603), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x03010604), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x03010605), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x03010606), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x03010607), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x03010608), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x03010609), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG , RULL(0x03010640), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG , RULL(0x03010641), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG , RULL(0x03010642), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x03010643), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x03010644), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x03010645), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x03010646), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x03010647), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x03010648), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x03010649), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG , RULL(0x04010400), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG , RULL(0x04010401), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG , RULL(0x04010402), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x04010403), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x04010404), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x04010405), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x04010406), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x04010407), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x04010408), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x04010409), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG , RULL(0x04010440), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG , RULL(0x04010441), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG , RULL(0x04010442), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x04010443), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x04010444), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x04010445), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x04010446), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x04010447), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x04010448), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x04010449), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG , RULL(0x05010400), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG , RULL(0x05010401), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG , RULL(0x05010402), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x05010403), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x05010404), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x05010405), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x05010406), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x05010407), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x05010408), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x05010409), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG , RULL(0x05010440), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG , RULL(0x05010441), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG , RULL(0x05010442), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x05010443), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x05010444), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x05010445), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x05010446), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x05010447), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x05010448), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x05010449), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG , RULL(0x05010480), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG , RULL(0x05010481), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG , RULL(0x05010482), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x05010483), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x05010484), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x05010485), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x05010486), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x05010487), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x05010488), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x05010489), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG , RULL(0x050104C0), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG , RULL(0x050104C1), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG , RULL(0x050104C2), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x050104C3), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x050104C4), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x050104C5), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x050104C6), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x050104C7), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x050104C8), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x050104C9), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG , RULL(0x05010500), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG , RULL(0x05010501), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG , RULL(0x05010502), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x05010503), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x05010504), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x05010505), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x05010506), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x05010507), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x05010508), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x05010509), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG , RULL(0x05010540), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG , RULL(0x05010541), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG , RULL(0x05010542), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x05010543), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x05010544), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x05010545), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x05010546), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x05010547), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x05010548), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x05010549), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG , RULL(0x05010580), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG , RULL(0x05010581), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG , RULL(0x05010582), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x05010583), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x05010584), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x05010585), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x05010586), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x05010587), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x05010588), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x05010589), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG , RULL(0x050105C0), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG , RULL(0x050105C1), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG , RULL(0x050105C2), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x050105C3), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x050105C4), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x050105C5), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x050105C6), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x050105C7), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x050105C8), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x050105C9), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA4_TR0_TRACE_HI_DATA_REG , RULL(0x05010600), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG , RULL(0x05010601), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG , RULL(0x05010602), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x05010603), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x05010604), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x05010605), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x05010606), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x05010607), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x05010608), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x05010609), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG , RULL(0x05010680), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG , RULL(0x05010681), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG , RULL(0x05010682), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x05010683), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x05010684), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x05010685), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x05010686), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x05010687), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x05010688), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x05010689), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG , RULL(0x050106C0), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG , RULL(0x050106C1), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG , RULL(0x050106C2), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x050106C3), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x050106C4), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x050106C5), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x050106C6), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x050106C7), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x050106C8), SH_UNT , SH_ACS_SCOM ); + +REG64( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x050106C9), SH_UNT , SH_ACS_SCOM ); + +REG64( PEC_TCPCI0_TRA0_TR0_TRACE_HI_DATA_REG , RULL(0x0D010400), SH_UNT_PEC , SH_ACS_SCOM_RO ); + +REG64( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG , RULL(0x0D010401), SH_UNT_PEC , SH_ACS_SCOM_RO ); + +REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG , RULL(0x0D010402), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x0D010403), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x0D010404), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x0D010405), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x0D010406), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x0D010407), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x0D010408), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x0D010409), SH_UNT_PEC , SH_ACS_SCOM ); + REG64( PU_NPU_SM2_TEST_CERR , RULL(0x05011341), SH_UNT_PU_NPU_SM2, SH_ACS_SCOM ); -REG64( PU_TRUST_CONTROL , RULL(0x05015F45), SH_UNT , SH_ACS_SCOM ); +REG64( CAPP_TFMR , RULL(0x02010827), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TFMR , RULL(0x02010827), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TFMR , RULL(0x04010827), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( PEC_THERM_MODE_REG , RULL(0x0D05000F), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_TIMEOUT_REG , RULL(0x0D0F0010), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_TIMESTAMP_COUNTER_READ , RULL(0x0D05001C), SH_UNT_PEC , SH_ACS_SCOM_RO ); + +REG64( CAPP_TLBI_ERROR_REPORT , RULL(0x0201080D), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TLBI_ERROR_REPORT , RULL(0x0201080D), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TLBI_ERROR_REPORT , RULL(0x0401080D), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_TOD_SYNC000 , RULL(0x02010826), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_TOD_SYNC000 , RULL(0x02010826), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_TOD_SYNC000 , RULL(0x04010826), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( PU_TRUST_CONTROL , RULL(0x05012B45), SH_UNT , SH_ACS_SCOM ); REG64( PEC_TUNNEL_BAR_REG , RULL(0x04010C05), SH_UNT_PEC , SH_ACS_SCOM_RW ); -REG64( PEC_0_TUNNEL_BAR_REG , RULL(0x04010C05), SH_UNT_PEC_0 , SH_ACS_SCOM_RW ); -REG64( PEC_1_TUNNEL_BAR_REG , RULL(0x04011005), SH_UNT_PEC_1 , SH_ACS_SCOM_RW ); -REG64( PEC_2_TUNNEL_BAR_REG , RULL(0x04011405), SH_UNT_PEC_2 , SH_ACS_SCOM_RW ); REG64( PU_TX_CH_FSM_REG , RULL(0x05012805), SH_UNT , SH_ACS_SCOM ); @@ -7400,6 +8189,12 @@ REG64( PU_UMAC_STATUS_CONTROL , RULL(0x020110D5 REG64( PU_VAS_BUFCTL , RULL(0x0301180C), SH_UNT , SH_ACS_SCOM ); +REG64( PU_VAS_CAMDATA0 , RULL(0x03011834), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_VAS_CAMDATA1 , RULL(0x03011835), SH_UNT , SH_ACS_SCOM_RO ); + +REG64( PU_VAS_CAMDISPCNTL , RULL(0x03011833), SH_UNT , SH_ACS_SCOM_WO ); + REG64( PU_VAS_CQERRRPT , RULL(0x03011848), SH_UNT , SH_ACS_SCOM ); REG64( PU_VAS_DBGCONT , RULL(0x0301182E), SH_UNT , SH_ACS_SCOM_RO ); @@ -7479,8 +8274,6 @@ REG64( PU_VAS_WCERRRPT , RULL(0x03011849 REG64( PU_VAS_WCMBAR , RULL(0x0301180A), SH_UNT , SH_ACS_SCOM_RW ); -REG64( PU_VAS_WCPOIS , RULL(0x03011828), SH_UNT , SH_ACS_SCOM_RW ); - REG64( PU_VAS_WRMON0BAR , RULL(0x03011810), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_VAS_WRMON0CMP , RULL(0x03011820), SH_UNT , SH_ACS_SCOM_RW ); @@ -7529,6 +8322,8 @@ REG64( PU_VAS_WRMON7CMP , RULL(0x03011827 REG64( PU_VAS_WRMON7WID , RULL(0x0301181F), SH_UNT , SH_ACS_SCOM_RW ); +REG64( PEC_VITAL_SCAN_OUT , RULL(0x0D0F0017), SH_UNT_PEC , SH_ACS_SCOM_RO ); + REG64( PU_WATCHDOG_HANG_TIMERS_CNTL , RULL(0x0201105C), SH_UNT , SH_ACS_SCOM_RW ); REG64( PU_WATER_MARK_REGISTER_B , RULL(0x000A0007), SH_UNT , SH_ACS_SCOM ); @@ -7539,32 +8334,67 @@ REG64( PU_WATER_MARK_REGISTER_D , RULL(0x000A2007 REG64( PU_WATER_MARK_REGISTER_E , RULL(0x000A3007), SH_UNT , SH_ACS_SCOM ); -REG64( PU_NPU0_SM0_XTIMER_CONFIG , RULL(0x0501100A), SH_UNT_PU_NPU0_SM0, +REG64( PEC_WRITE_PROTECT_ENABLE_REG , RULL(0x0D010005), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_WRITE_PROTECT_ENABLE_REG , RULL(0x02010005), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_WRITE_PROTECT_ENABLE_REG , RULL(0x03010005), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_WRITE_PROTECT_ENABLE_REG , RULL(0x04010005), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_WRITE_PROTECT_ENABLE_REG , RULL(0x05010005), SH_UNT_PU_N3 , SH_ACS_SCOM ); + +REG64( PEC_WRITE_PROTECT_RINGS_REG , RULL(0x0D010006), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_N0_WRITE_PROTECT_RINGS_REG , RULL(0x02010006), SH_UNT_PU_N0 , SH_ACS_SCOM ); +REG64( PU_N1_WRITE_PROTECT_RINGS_REG , RULL(0x03010006), SH_UNT_PU_N1 , SH_ACS_SCOM ); +REG64( PU_N2_WRITE_PROTECT_RINGS_REG , RULL(0x04010006), SH_UNT_PU_N2 , SH_ACS_SCOM ); +REG64( PU_N3_WRITE_PROTECT_RINGS_REG , RULL(0x05010006), SH_UNT_PU_N3 , SH_ACS_SCOM ); + +REG64( PEC_XFIR , RULL(0x0D040000), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( CAPP_XPT_CONTROL , RULL(0x0201081C), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_XPT_CONTROL , RULL(0x0201081C), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_XPT_CONTROL , RULL(0x0401081C), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( CAPP_XPT_PMU_EVENTS_SEL , RULL(0x02010822), SH_UNT_CAPP , SH_ACS_SCOM ); +REG64( CAPP_0_XPT_PMU_EVENTS_SEL , RULL(0x02010822), SH_UNT_CAPP_0 , SH_ACS_SCOM ); +REG64( CAPP_1_XPT_PMU_EVENTS_SEL , RULL(0x04010822), SH_UNT_CAPP_1 , SH_ACS_SCOM ); + +REG64( PEC_XSTOP1 , RULL(0x0D03000C), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_XSTOP2 , RULL(0x0D03000D), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_XSTOP3 , RULL(0x0D03000E), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PEC_XSTOP_INTERRUPT_REG , RULL(0x0D0F001C), SH_UNT_PEC , SH_ACS_SCOM ); + +REG64( PU_NPU0_SM0_XTIMER_CONFIG , RULL(0x05011003), SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM ); -REG64( PU_NPU0_SM1_XTIMER_CONFIG , RULL(0x0501102A), SH_UNT_PU_NPU0_SM1, +REG64( PU_NPU0_SM1_XTIMER_CONFIG , RULL(0x05011023), SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM ); -REG64( PU_NPU0_SM2_XTIMER_CONFIG , RULL(0x0501104A), SH_UNT_PU_NPU0_SM2, +REG64( PU_NPU0_SM2_XTIMER_CONFIG , RULL(0x05011043), SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM ); -REG64( PU_NPU0_SM3_XTIMER_CONFIG , RULL(0x0501106A), SH_UNT_PU_NPU0_SM3, +REG64( PU_NPU0_SM3_XTIMER_CONFIG , RULL(0x05011063), SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM ); -REG64( PU_NPU1_SM0_XTIMER_CONFIG , RULL(0x0501110A), SH_UNT_PU_NPU1_SM0, +REG64( PU_NPU1_SM0_XTIMER_CONFIG , RULL(0x05011103), SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM ); -REG64( PU_NPU1_SM1_XTIMER_CONFIG , RULL(0x0501112A), SH_UNT_PU_NPU1_SM1, +REG64( PU_NPU1_SM1_XTIMER_CONFIG , RULL(0x05011123), SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM ); -REG64( PU_NPU1_SM2_XTIMER_CONFIG , RULL(0x0501114A), SH_UNT_PU_NPU1_SM2, +REG64( PU_NPU1_SM2_XTIMER_CONFIG , RULL(0x05011143), SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM ); -REG64( PU_NPU1_SM3_XTIMER_CONFIG , RULL(0x0501116A), SH_UNT_PU_NPU1_SM3, +REG64( PU_NPU1_SM3_XTIMER_CONFIG , RULL(0x05011163), SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM ); -REG64( PU_NPU2_SM0_XTIMER_CONFIG , RULL(0x0501120A), SH_UNT_PU_NPU2_SM0, +REG64( PU_NPU2_SM0_XTIMER_CONFIG , RULL(0x05011203), SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM ); -REG64( PU_NPU2_SM1_XTIMER_CONFIG , RULL(0x0501122A), SH_UNT_PU_NPU2_SM1, +REG64( PU_NPU2_SM1_XTIMER_CONFIG , RULL(0x05011223), SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM ); -REG64( PU_NPU2_SM2_XTIMER_CONFIG , RULL(0x0501124A), SH_UNT_PU_NPU2_SM2, +REG64( PU_NPU2_SM2_XTIMER_CONFIG , RULL(0x05011243), SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM ); -REG64( PU_NPU2_SM3_XTIMER_CONFIG , RULL(0x0501126A), SH_UNT_PU_NPU2_SM3, +REG64( PU_NPU2_SM3_XTIMER_CONFIG , RULL(0x05011263), SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM ); REG64( PU_NPU_SM2_XTS_CONFIG , RULL(0x05011344), SH_UNT_PU_NPU_SM2, SH_ACS_SCOM ); + +REG64( PU_NPU_SM2_XTS_CONFIG2 , RULL(0x05011345), SH_UNT_PU_NPU_SM2, + SH_ACS_SCOM ); #endif diff --git a/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H b/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H index 98e84dd6..579074ff 100644 --- a/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H +++ b/import/chips/p9/common/include/p9_misc_scom_addresses_fld.H @@ -87,6 +87,313 @@ REG64_FLD( PU_ADDR_9_HASH_FUNCTION_REG_ADDRESS , 0 , SH_UN REG64_FLD( PU_ADDR_9_HASH_FUNCTION_REG_ADDRESS_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_N3_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( PU_N3_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); +REG64_FLD( PU_N3_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( PU_N3_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RESERVED_LAST_LT ); +REG64_FLD( PU_N3_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); +REG64_FLD( PU_N3_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); +REG64_FLD( PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); +REG64_FLD( PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); +REG64_FLD( PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); +REG64_FLD( PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); + +REG64_FLD( PU_N1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( PU_N1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); +REG64_FLD( PU_N1_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( PU_N1_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RESERVED_LAST_LT ); +REG64_FLD( PU_N1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); +REG64_FLD( PU_N1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); +REG64_FLD( PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); +REG64_FLD( PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); +REG64_FLD( PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); +REG64_FLD( PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); + +REG64_FLD( PU_N2_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( PU_N2_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); +REG64_FLD( PU_N2_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( PU_N2_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RESERVED_LAST_LT ); +REG64_FLD( PU_N2_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); +REG64_FLD( PU_N2_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); +REG64_FLD( PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); +REG64_FLD( PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); +REG64_FLD( PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); +REG64_FLD( PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); + +REG64_FLD( PEC_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( PEC_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); +REG64_FLD( PEC_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( PEC_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESERVED_LAST_LT ); +REG64_FLD( PEC_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); +REG64_FLD( PEC_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); +REG64_FLD( PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); +REG64_FLD( PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); +REG64_FLD( PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); +REG64_FLD( PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); + +REG64_FLD( PU_N0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( PU_N0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); +REG64_FLD( PU_N0_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( PU_N0_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RESERVED_LAST_LT ); +REG64_FLD( PU_N0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); +REG64_FLD( PU_N0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); +REG64_FLD( PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); +REG64_FLD( PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); +REG64_FLD( PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); +REG64_FLD( PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); + +REG64_FLD( CAPP_APCFG_APCCTL_PHB_SEL , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_PHB_SEL ); +REG64_FLD( CAPP_APCFG_APCCTL_PHB_SEL_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_PHB_SEL_LEN ); +REG64_FLD( CAPP_APCFG_HANG_POLL_SCALE , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_HANG_POLL_SCALE ); +REG64_FLD( CAPP_APCFG_HANG_POLL_SCALE_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_HANG_POLL_SCALE_LEN ); +REG64_FLD( CAPP_APCFG_SPEC_HPC_DIR_STATE , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SPEC_HPC_DIR_STATE ); +REG64_FLD( CAPP_APCFG_SPEC_HPC_DIR_STATE_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SPEC_HPC_DIR_STATE_LEN ); +REG64_FLD( CAPP_APCFG_APCCTL_P9_MODE , 14 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_P9_MODE ); +REG64_FLD( CAPP_APCFG_APCCTL_SYSADDR , 15 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_SYSADDR ); +REG64_FLD( CAPP_APCFG_APCCTL_SYSADDR_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_SYSADDR_LEN ); +REG64_FLD( CAPP_APCFG_APCCTL_MEM_SEL_MODE , 21 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_MEM_SEL_MODE ); +REG64_FLD( CAPP_APCFG_APCCTL_ENB_FRC_ADDR13 , 22 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_ENB_FRC_ADDR13 ); + +REG64_FLD( CAPP_APCLCO_TARGET_VALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TARGET_VALID ); +REG64_FLD( CAPP_APCLCO_TARGET_VALID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TARGET_VALID_LEN ); +REG64_FLD( CAPP_APCLCO_TARGET_ID0 , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TARGET_ID0 ); +REG64_FLD( CAPP_APCLCO_TARGET_MIN , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TARGET_MIN ); +REG64_FLD( CAPP_APCLCO_TARGET_MIN_LEN , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TARGET_MIN_LEN ); + +REG64_FLD( CAPP_APCRDFSMMASK_APC_RDFSM_MASK , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APC_RDFSM_MASK ); +REG64_FLD( CAPP_APCRDFSMMASK_APC_RDFSM_MASK_LEN , 48 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APC_RDFSM_MASK_LEN ); + +REG64_FLD( CAPP_APCTL_APCCTL_ENB_CRESP_EXAM , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_ENB_CRESP_EXAM ); +REG64_FLD( CAPP_APCTL_APCCTL_ADR_BAR_MODE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_ADR_BAR_MODE ); +REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_NN_RN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_DISABLE_NN_RN ); +REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_VG_NOT_SYS , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_DISABLE_VG_NOT_SYS ); +REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_G , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_DISABLE_G ); +REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_LN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_DISABLE_LN ); +REG64_FLD( CAPP_APCTL_APCCTL_SKIP_G , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_SKIP_G ); +REG64_FLD( CAPP_APCTL_APCCTL_HANG_ARE , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_HANG_ARE ); +REG64_FLD( CAPP_APCTL_APCCTL_HANG_DEAD , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_HANG_DEAD ); +REG64_FLD( CAPP_APCTL_APCCTL_CFG_BKILL_INC , 9 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_CFG_BKILL_INC ); +REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_PSL_CMDQUEUE , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_DISABLE_PSL_CMDQUEUE ); +REG64_FLD( CAPP_APCTL_APCCTL_ENABLE_MASTER_RETRY_BACKOFF , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_ENABLE_MASTER_RETRY_BACKOFF ); +REG64_FLD( CAPP_APCTL_SCPTGT_LFSR_MODE , 14 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SCPTGT_LFSR_MODE ); +REG64_FLD( CAPP_APCTL_SCPTGT_LFSR_MODE_LEN , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SCPTGT_LFSR_MODE_LEN ); +REG64_FLD( CAPP_APCTL_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT , 17 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT ); +REG64_FLD( CAPP_APCTL_WR_EPSILON_VALUE , 39 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_WR_EPSILON_VALUE ); +REG64_FLD( CAPP_APCTL_WR_EPSILON_VALUE_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_WR_EPSILON_VALUE_LEN ); +REG64_FLD( CAPP_APCTL_APCCTL_MAX_RETRY , 56 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_MAX_RETRY ); +REG64_FLD( CAPP_APCTL_APCCTL_MAX_RETRY_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCCTL_MAX_RETRY_LEN ); + +REG64_FLD( CAPP_APC_ARRY_ADDR_APCARY_ADDRESS , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCARY_ADDRESS ); +REG64_FLD( CAPP_APC_ARRY_ADDR_APCARY_ADDRESS_LEN , 9 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCARY_ADDRESS_LEN ); + +REG64_FLD( CAPP_APC_ARRY_RDDATA_APCARY , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCARY ); +REG64_FLD( CAPP_APC_ARRY_RDDATA_APCARY_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCARY_LEN ); + +REG64_FLD( CAPP_APC_ARRY_WRDATA_APCARY , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCARY ); +REG64_FLD( CAPP_APC_ARRY_WRDATA_APCARY_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_APCARY_LEN ); + +REG64_FLD( CAPP_APC_PMUSEL_GRPSEL , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_GRPSEL ); +REG64_FLD( CAPP_APC_PMUSEL_GRPSEL_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_GRPSEL_LEN ); +REG64_FLD( CAPP_APC_PMUSEL_FSMJ_EVENT_SEL , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FSMJ_EVENT_SEL ); +REG64_FLD( CAPP_APC_PMUSEL_FSMJ_EVENT_SEL_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FSMJ_EVENT_SEL_LEN ); +REG64_FLD( CAPP_APC_PMUSEL_FSMJ_FSM_SEL , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FSMJ_FSM_SEL ); +REG64_FLD( CAPP_APC_PMUSEL_FSMJ_FSM_SEL_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FSMJ_FSM_SEL_LEN ); + +REG64_FLD( CAPP_ASE_TUPLE0_LPID , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_ASE_TUPLE0_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); +REG64_FLD( CAPP_ASE_TUPLE0_PID , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_ASE_TUPLE0_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_ASE_TUPLE0_TID , 44 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TID ); +REG64_FLD( CAPP_ASE_TUPLE0_TID_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TID_LEN ); +REG64_FLD( CAPP_ASE_TUPLE0_VALID , 63 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_VALID ); + +REG64_FLD( CAPP_ASE_TUPLE1_LPID , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_ASE_TUPLE1_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); +REG64_FLD( CAPP_ASE_TUPLE1_PID , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_ASE_TUPLE1_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_ASE_TUPLE1_TID , 44 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TID ); +REG64_FLD( CAPP_ASE_TUPLE1_TID_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TID_LEN ); +REG64_FLD( CAPP_ASE_TUPLE1_VALID , 63 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_VALID ); + +REG64_FLD( CAPP_ASE_TUPLE2_LPID , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_ASE_TUPLE2_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); +REG64_FLD( CAPP_ASE_TUPLE2_PID , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_ASE_TUPLE2_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_ASE_TUPLE2_TID , 44 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TID ); +REG64_FLD( CAPP_ASE_TUPLE2_TID_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TID_LEN ); +REG64_FLD( CAPP_ASE_TUPLE2_VALID , 63 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_VALID ); + +REG64_FLD( CAPP_ASE_TUPLE3_LPID , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID ); +REG64_FLD( CAPP_ASE_TUPLE3_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPID_LEN ); +REG64_FLD( CAPP_ASE_TUPLE3_PID , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID ); +REG64_FLD( CAPP_ASE_TUPLE3_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PID_LEN ); +REG64_FLD( CAPP_ASE_TUPLE3_TID , 44 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TID ); +REG64_FLD( CAPP_ASE_TUPLE3_TID_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TID_LEN ); +REG64_FLD( CAPP_ASE_TUPLE3_VALID , 63 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_VALID ); + +REG64_FLD( PU_N3_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_MASK ); +REG64_FLD( PU_N3_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_MASK_LEN ); + +REG64_FLD( PU_N1_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_MASK ); +REG64_FLD( PU_N1_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_MASK_LEN ); + +REG64_FLD( PU_N2_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_MASK ); +REG64_FLD( PU_N2_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_MASK_LEN ); + +REG64_FLD( PEC_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASK ); +REG64_FLD( PEC_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASK_LEN ); + +REG64_FLD( PU_N0_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_MASK ); +REG64_FLD( PU_N0_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_MASK_LEN ); + +REG64_FLD( PEC_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( PEC_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ID ); +REG64_FLD( PEC_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ID_LEN ); +REG64_FLD( PEC_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACTIVITY ); +REG64_FLD( PEC_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACTIVITY_LEN ); + REG64_FLD( PU_NPU_SM0_ATS_CKSW_SPARE , 0 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_SPARE ); REG64_FLD( PU_NPU_SM0_ATS_CKSW_SPARE_LEN , 64 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , @@ -149,8 +456,8 @@ REG64_FLD( PU_NPU_SM0_ATS_HOLD_TOR_PERR_ESR , 17 , SH_UN SH_FLD_TOR_PERR_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_INVAL_IODA_TBL_SEL_ESR , 18 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_INVAL_IODA_TBL_SEL_ESR ); -REG64_FLD( PU_NPU_SM0_ATS_HOLD_CTL_ADDR_ERR_ESR , 19 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, - SH_FLD_CTL_ADDR_ERR_ESR ); +REG64_FLD( PU_NPU_SM0_ATS_HOLD_ESR_RSVD_19 , 19 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, + SH_FLD_ESR_RSVD_19 ); REG64_FLD( PU_NPU_SM1_ATS_TCR_TCE_TIMEOUT , 10 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_TCE_TIMEOUT ); @@ -449,49 +756,14 @@ REG64_FLD( PU_MCD1_BANK0_MCD_VGC_MASK_AGV_DISABLE_MODE , 36 , SH_UN REG64_FLD( PU_MCD1_BANK0_MCD_VGC_XLATE_TO_ADDR_ID_ENABLE , 37 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_XLATE_TO_ADDR_ID_ENABLE ); -REG64_FLD( PEC_STACK2_BARE_REG_PE_MMIO_BAR0_EN , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , - SH_FLD_PE_MMIO_BAR0_EN ); -REG64_FLD( PEC_STACK2_BARE_REG_PE_MMIO_BAR1_EN , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , - SH_FLD_PE_MMIO_BAR1_EN ); -REG64_FLD( PEC_STACK2_BARE_REG_PE_PHB_BAR_EN , 2 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , - SH_FLD_PE_PHB_BAR_EN ); -REG64_FLD( PEC_STACK2_BARE_REG_PE_MSI_BAR_EN , 3 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , - SH_FLD_PE_MSI_BAR_EN ); -REG64_FLD( PEC_STACK2_BARE_REG_PE_LSI_BAR_EN , 4 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , - SH_FLD_PE_LSI_BAR_EN ); - -REG64_FLD( PEC_STACK1_BARE_REG_PE_MMIO_BAR0_EN , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , - SH_FLD_PE_MMIO_BAR0_EN ); -REG64_FLD( PEC_STACK1_BARE_REG_PE_MMIO_BAR1_EN , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , - SH_FLD_PE_MMIO_BAR1_EN ); -REG64_FLD( PEC_STACK1_BARE_REG_PE_PHB_BAR_EN , 2 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , - SH_FLD_PE_PHB_BAR_EN ); -REG64_FLD( PEC_STACK1_BARE_REG_PE_MSI_BAR_EN , 3 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , - SH_FLD_PE_MSI_BAR_EN ); -REG64_FLD( PEC_STACK1_BARE_REG_PE_LSI_BAR_EN , 4 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , - SH_FLD_PE_LSI_BAR_EN ); - REG64_FLD( PHB_BARE_REG_PE_MMIO_BAR0_EN , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_MMIO_BAR0_EN ); REG64_FLD( PHB_BARE_REG_PE_MMIO_BAR1_EN , 1 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_MMIO_BAR1_EN ); REG64_FLD( PHB_BARE_REG_PE_PHB_BAR_EN , 2 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_PHB_BAR_EN ); -REG64_FLD( PHB_BARE_REG_PE_MSI_BAR_EN , 3 , SH_UNT_PHB , SH_ACS_SCOM_RW , - SH_FLD_PE_MSI_BAR_EN ); -REG64_FLD( PHB_BARE_REG_PE_LSI_BAR_EN , 4 , SH_UNT_PHB , SH_ACS_SCOM_RW , - SH_FLD_PE_LSI_BAR_EN ); - -REG64_FLD( PEC_STACK0_BARE_REG_PE_MMIO_BAR0_EN , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , - SH_FLD_PE_MMIO_BAR0_EN ); -REG64_FLD( PEC_STACK0_BARE_REG_PE_MMIO_BAR1_EN , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , - SH_FLD_PE_MMIO_BAR1_EN ); -REG64_FLD( PEC_STACK0_BARE_REG_PE_PHB_BAR_EN , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , - SH_FLD_PE_PHB_BAR_EN ); -REG64_FLD( PEC_STACK0_BARE_REG_PE_MSI_BAR_EN , 3 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , - SH_FLD_PE_MSI_BAR_EN ); -REG64_FLD( PEC_STACK0_BARE_REG_PE_LSI_BAR_EN , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , - SH_FLD_PE_LSI_BAR_EN ); +REG64_FLD( PHB_BARE_REG_PE_INT_BAR_EN , 3 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_PE_INT_BAR_EN ); REG64_FLD( PU_BCDE_CTL_STOP , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STOP ); @@ -621,9 +893,11 @@ REG64_FLD( PU_BCUE_STAT_DONE , 31 , SH_UN REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); -REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_WILDCARD , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_WILDCARD ); +REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_RESERVED , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_RESERVED_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_PE , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE ); @@ -651,9 +925,11 @@ REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_BDF_LEN , 16 , SH_UN REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); -REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_WILDCARD , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_WILDCARD ); +REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_RESERVED , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_RESERVED_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_PE , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE ); @@ -666,9 +942,11 @@ REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_BDF_LEN , 16 , SH_UN REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); -REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_WILDCARD , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_WILDCARD ); +REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_RESERVED , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_RESERVED_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_PE , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE ); @@ -801,9 +1079,11 @@ REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_BDF_LEN , 16 , SH_UN REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); -REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_WILDCARD , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_WILDCARD ); +REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_RESERVED , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_RESERVED_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_PE , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE ); @@ -831,9 +1111,11 @@ REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_BDF_LEN , 16 , SH_UN REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); -REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_WILDCARD , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_WILDCARD ); +REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_RESERVED , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_RESERVED_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_PE , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE ); @@ -846,9 +1128,11 @@ REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_BDF_LEN , 16 , SH_UN REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); -REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_WILDCARD , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_WILDCARD ); +REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_RESERVED , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_RESERVED_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_PE , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE ); @@ -1159,69 +1443,86 @@ REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_BDF , 8 , SH_UN REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_BDF_LEN ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_B_ENABLE_0 , 0 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ENABLE_0 ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_B_ID_0 , 1 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ID_0 ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_B_ID_0_LEN , 4 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ID_0_LEN ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_B_ACTIVITY_0 , 8 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ACTIVITY_0 ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_B_ACTIVITY_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ACTIVITY_0_LEN ); - -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_C_ENABLE_1 , 0 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ENABLE_1 ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_C_ID_1 , 1 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ID_1 ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_C_ID_1_LEN , 4 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ID_1_LEN ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_C_ACTIVITY_1 , 8 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ACTIVITY_1 ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_C_ACTIVITY_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ACTIVITY_1_LEN ); - -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_D_ENABLE_2 , 0 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ENABLE_2 ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_D_ID_2 , 1 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ID_2 ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_D_ID_2_LEN , 4 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ID_2_LEN ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_D_ACTIVITY_2 , 8 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ACTIVITY_2 ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_D_ACTIVITY_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ACTIVITY_2_LEN ); - -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_E_ENABLE_3 , 0 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ENABLE_3 ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_E_ID_3 , 1 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ID_3 ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_E_ID_3_LEN , 4 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ID_3_LEN ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_E_ACTIVITY_3 , 8 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ACTIVITY_3 ); -REG64_FLD( PU_CC_ATOMIC_LOCK_REG_E_ACTIVITY_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , - SH_FLD_ACTIVITY_3_LEN ); - -REG64_FLD( PU_CC_PROTECT_MODE_REG_B_READ_ENABLE_0 , 0 , SH_UNT , SH_ACS_SCOM , - SH_FLD_READ_ENABLE_0 ); -REG64_FLD( PU_CC_PROTECT_MODE_REG_B_WRITE_ENABLE_0 , 1 , SH_UNT , SH_ACS_SCOM , - SH_FLD_WRITE_ENABLE_0 ); - -REG64_FLD( PU_CC_PROTECT_MODE_REG_C_READ_ENABLE_1 , 0 , SH_UNT , SH_ACS_SCOM , - SH_FLD_READ_ENABLE_1 ); -REG64_FLD( PU_CC_PROTECT_MODE_REG_C_WRITE_ENABLE_1 , 1 , SH_UNT , SH_ACS_SCOM , - SH_FLD_WRITE_ENABLE_1 ); - -REG64_FLD( PU_CC_PROTECT_MODE_REG_D_READ_ENABLE_2 , 0 , SH_UNT , SH_ACS_SCOM , - SH_FLD_READ_ENABLE_2 ); -REG64_FLD( PU_CC_PROTECT_MODE_REG_D_WRITE_ENABLE_2 , 1 , SH_UNT , SH_ACS_SCOM , - SH_FLD_WRITE_ENABLE_2 ); - -REG64_FLD( PU_CC_PROTECT_MODE_REG_E_READ_ENABLE_3 , 0 , SH_UNT , SH_ACS_SCOM , - SH_FLD_READ_ENABLE_3 ); -REG64_FLD( PU_CC_PROTECT_MODE_REG_E_WRITE_ENABLE_3 , 1 , SH_UNT , SH_ACS_SCOM , - SH_FLD_WRITE_ENABLE_3 ); +REG64_FLD( PEC_BIST_TC_START_TEST_DC , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TC_START_TEST_DC ); +REG64_FLD( PEC_BIST_TC_SRAM_ABIST_MODE_DC , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TC_SRAM_ABIST_MODE_DC ); +REG64_FLD( PEC_BIST_TC_EDRAM_ABIST_MODE_DC , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TC_EDRAM_ABIST_MODE_DC ); +REG64_FLD( PEC_BIST_TC_IOBIST_MODE_DC , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TC_IOBIST_MODE_DC ); +REG64_FLD( PEC_BIST_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PERV ); +REG64_FLD( PEC_BIST_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT1 ); +REG64_FLD( PEC_BIST_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT2 ); +REG64_FLD( PEC_BIST_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT3 ); +REG64_FLD( PEC_BIST_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT4 ); +REG64_FLD( PEC_BIST_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT5 ); +REG64_FLD( PEC_BIST_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT6 ); +REG64_FLD( PEC_BIST_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT7 ); +REG64_FLD( PEC_BIST_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT8 ); +REG64_FLD( PEC_BIST_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT9 ); +REG64_FLD( PEC_BIST_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT10 ); + +REG64_FLD( CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_ENABLE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TIMER_ENABLE ); +REG64_FLD( CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_PERIOD_MASK , 48 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TIMER_PERIOD_MASK ); +REG64_FLD( CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_PERIOD_MASK_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TIMER_PERIOD_MASK_LEN ); + +REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_ERROR_RECOVERY_INITIATED , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ERROR_RECOVERY_INITIATED ); +REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_ERROR_RECOVERY_COMPLETE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ERROR_RECOVERY_COMPLETE ); +REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_TLBI_PSL_DEAD , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBI_PSL_DEAD ); +REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_TLBI_FENCE , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBI_FENCE ); +REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_RECOVERY_FAILED , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RECOVERY_FAILED ); +REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_RTAGFLUSH_FAILED , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RTAGFLUSH_FAILED ); +REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_PRECISE_DIR_FLUSH_FAILED , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PRECISE_DIR_FLUSH_FAILED ); +REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_COURSE_DIR_FLUSH_FAILED , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COURSE_DIR_FLUSH_FAILED ); +REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_RECOVERY_HANG_DETECTED , 9 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RECOVERY_HANG_DETECTED ); +REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_EPOCH_VALUE , 10 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_EPOCH_VALUE ); +REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_EPOCH_VALUE_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_EPOCH_VALUE_LEN ); +REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_FORCE_QUIESCE , 14 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FORCE_QUIESCE ); +REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_QUIESCE_DONE , 15 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_QUIESCE_DONE ); + +REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ID ); +REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ID_LEN ); +REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACTIVITY ); +REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACTIVITY_LEN ); + +REG64_FLD( PEC_CC_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_READ_ENABLE ); +REG64_FLD( PEC_CC_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WRITE_ENABLE ); REG64_FLD( PU_NPU0_CERR_ECC_FIRST_BITS , 10 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS ); @@ -1436,908 +1737,740 @@ REG64_FLD( PU_NPU2_CERR_ECC_MASK_BITS , 10 , SH_UN REG64_FLD( PU_NPU2_CERR_ECC_MASK_BITS_LEN , 54 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_0 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_1 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_2 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_3 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_4 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_5 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_6 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_7 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_8 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_8 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_9 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_9 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_10 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_10 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_11 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_11 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_0 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_1 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_2 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_3 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_4 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_5 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_6 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_7 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_24 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_25 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_26 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_27 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_28 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_29 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_30 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_31 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 57 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 58 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 59 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 60 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 61 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 62 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); - -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_0 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_1 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_2 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_3 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_4 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_5 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_6 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_7 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_8 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_8 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_9 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_9 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_10 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_10 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_11 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_11 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_0 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_1 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_2 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_3 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_4 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_5 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_6 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_7 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_7 ); + +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_24 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_25 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_26 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_27 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_28 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_29 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_30 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_31 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 57 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 58 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 59 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 60 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 61 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 62 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); - -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_0 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_1 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_2 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_3 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_4 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_5 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_6 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_7 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_8 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_8 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_9 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_9 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_10 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_10 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_11 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_11 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_0 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_1 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_2 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_3 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_4 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_5 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_6 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_7 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_7 ); + +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_24 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_25 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_26 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_27 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_28 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_29 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_30 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_31 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 57 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 58 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 59 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 60 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 61 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 62 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); - -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_0 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_1 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_2 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_3 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_4 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_5 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_6 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_7 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_8 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_8 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_9 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_9 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_10 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_10 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_11 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_11 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_0 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_1 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_2 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_3 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_4 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_5 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_6 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_7 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_7 ); + +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_24 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_25 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_26 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_27 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_28 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_29 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_30 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_31 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 57 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 58 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 59 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 60 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 61 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 62 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); - -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBP_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_0 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_1 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_2 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_3 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_4 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_5 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_6 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_7 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_8 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_8 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_9 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_9 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_10 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_10 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBF_11 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_11 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_0 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_1 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_2 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_3 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_4 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_5 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_6 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBC_7 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_7 ); + +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_24 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_25 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_26 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_27 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_28 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_29 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_30 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_31 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 57 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 58 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 59 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 60 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 61 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 62 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); - -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_0 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_1 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_2 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_3 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_4 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_5 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_6 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_7 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_8 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_8 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_9 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_9 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_10 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_10 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_11 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_11 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_0 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_1 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_2 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_3 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_4 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_5 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_6 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_7 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_7 ); + +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_24 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_25 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_26 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_27 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_28 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_29 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_30 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_31 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 57 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 58 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 59 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 60 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 61 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 62 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); - -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_0 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_1 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_2 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_3 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_4 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_5 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_6 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_7 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_8 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_8 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_9 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_9 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_10 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_10 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_11 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_11 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_0 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_1 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_2 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_3 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_4 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_5 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_6 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_7 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_7 ); + +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_24 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_25 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_26 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_27 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_28 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_29 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_30 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_31 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 57 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 58 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 59 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 60 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 61 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 62 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_7 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_0 ); @@ -2459,401 +2592,329 @@ REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_2 , 58 , SH_UN SH_FLD_IDIAL_CTL_FIRST_DUE_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_3 , 59 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_3 ); -REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV4_0 , 60 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_FIRST_RSV4_0 ); -REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV4_1 , 61 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_FIRST_RSV4_1 ); -REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV4_2 , 62 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_FIRST_RSV4_2 ); -REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV4_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_FIRST_RSV4_3 ); - -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_0 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_1 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_2 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_3 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_4 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_5 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_6 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_7 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_8 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_8 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_9 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_9 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_10 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_10 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_11 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_11 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_0 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_1 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_2 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_3 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_4 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_5 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_6 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_7 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_0 , 60 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_FIRST_PEF_0 ); +REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_1 , 61 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_FIRST_PEF_1 ); +REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_2 , 62 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_FIRST_PEF_2 ); +REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_FIRST_PEF_3 ); + +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_24 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_25 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_26 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_27 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_28 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_29 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_30 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_31 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 57 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 58 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 59 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 60 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 61 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 62 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); - -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBP_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_0 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_1 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_2 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_3 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_4 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_5 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_6 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_7 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_8 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_8 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_9 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_9 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_10 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_10 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBF_11 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_11 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_0 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_1 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_2 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_3 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_4 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_5 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_6 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBC_7 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_7 ); + +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_24 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_25 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_26 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_27 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_28 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_29 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_30 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_31 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 57 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 58 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 59 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 60 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 61 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 62 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); - -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_0 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_1 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_2 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_3 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_4 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_5 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_6 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_7 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_8 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_8 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_9 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_9 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_10 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_10 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_11 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_11 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_0 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_1 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_2 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_3 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_4 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_5 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_6 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_7 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_7 ); + +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_24 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_25 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_26 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_27 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_28 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_29 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_30 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_31 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 57 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 58 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 59 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 60 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 61 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 62 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_7 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_0 ); @@ -2975,14 +3036,14 @@ REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_2 , 58 , SH_UN SH_FLD_IDIAL_CTL_FIRST_DUE_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_3 , 59 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_3 ); -REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV4_0 , 60 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_FIRST_RSV4_0 ); -REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV4_1 , 61 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_FIRST_RSV4_1 ); -REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV4_2 , 62 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_FIRST_RSV4_2 ); -REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV4_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_FIRST_RSV4_3 ); +REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_0 , 60 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_FIRST_PEF_0 ); +REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_1 , 61 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_FIRST_PEF_1 ); +REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_2 , 62 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_FIRST_PEF_2 ); +REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_FIRST_PEF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_0 ); @@ -3104,530 +3165,450 @@ REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_2 , 58 , SH_UN SH_FLD_IDIAL_CTL_FIRST_DUE_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_3 , 59 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_3 ); -REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV4_0 , 60 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_FIRST_RSV4_0 ); -REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV4_1 , 61 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_FIRST_RSV4_1 ); -REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV4_2 , 62 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_FIRST_RSV4_2 ); -REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV4_3 , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_FIRST_RSV4_3 ); - -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBP_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_0 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_1 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_2 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_3 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_4 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_5 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_6 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_7 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_8 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_8 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_9 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_9 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_10 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_10 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBF_11 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_11 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_0 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_1 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_2 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_3 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_4 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_5 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_6 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBC_7 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_0 , 60 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_FIRST_PEF_0 ); +REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_1 , 61 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_FIRST_PEF_1 ); +REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_2 , 62 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_FIRST_PEF_2 ); +REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_3 , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_FIRST_PEF_3 ); + +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_24 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_25 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_26 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_27 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_28 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_29 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_30 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_31 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 57 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 58 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 59 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 60 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 61 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 62 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); - -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBP_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBP_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_0 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_1 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_2 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_3 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_4 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_5 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_6 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_7 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_8 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_8 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_9 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_9 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_10 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_10 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBF_11 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBF_11 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_0 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_1 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_2 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_3 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_4 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_5 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_6 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBC_7 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_PBC_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NCF_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_7 ); + +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_24 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_25 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_26 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_27 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_28 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_29 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_30 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NVF_31 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NCF_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 57 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 58 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 59 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 60 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 61 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 62 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); - -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_8 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_9 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_10 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_11 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_12 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_13 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_14 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_15 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_16 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_17 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_18 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_19 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_20 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_21 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_22 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_23 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_24 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_25 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_26 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_27 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_28 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_29 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_30 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_31 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_32 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_33 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_34 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_35 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_36 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_37 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_38 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_39 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_40 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_41 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_42 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_43 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_44 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_45 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_46 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_47 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_48 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_49 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_50 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_51 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_52 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_53 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_54 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_55 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBR_7 ); + +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 57 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 58 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 59 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 60 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 61 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 62 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); - -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_8 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_9 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_10 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_11 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_12 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_13 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_14 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_15 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_16 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_17 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_18 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_19 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_20 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_21 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_22 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_23 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_24 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_25 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_26 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_27 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_28 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_29 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_30 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_31 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_32 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_33 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_34 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_35 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_36 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_37 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_38 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_39 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_40 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_41 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_42 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_43 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_44 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_45 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_46 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_47 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_48 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_49 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_50 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_51 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_52 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_53 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_54 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_55 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_8 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_9 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_10 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_11 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_8 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_9 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_10 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_11 ); + +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 57 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 58 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 59 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 60 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 61 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 62 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_8 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_9 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_10 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_11 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_8 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_9 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_10 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_0 ); @@ -3758,263 +3739,231 @@ REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_62 , 62 , SH_UN REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_8 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_9 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_10 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_11 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_12 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_13 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_14 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_15 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_16 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_17 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_18 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_19 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_20 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_21 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_22 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_23 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_24 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_25 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_26 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_27 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_28 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_29 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_30 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_31 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_32 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_33 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_34 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_35 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_36 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_37 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_38 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_39 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_40 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_41 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_42 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_43 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_44 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_45 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_46 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_47 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_48 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_49 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_50 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_51 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_52 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_53 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_54 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_55 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 57 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 58 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 59 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 60 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 61 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 62 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); - -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_8 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_9 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_10 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_11 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_12 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_13 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_14 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_15 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_16 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_17 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_18 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_19 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_20 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_21 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_22 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_23 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_24 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_25 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_26 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_27 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_28 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_29 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_30 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_31 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_32 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_33 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_34 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_35 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_36 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_37 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_38 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_39 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_40 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_41 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_42 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_43 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_44 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_45 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_46 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_47 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_48 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_49 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_50 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_51 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_52 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_53 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_54 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_55 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_8 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_9 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_10 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_11 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_8 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_9 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_10 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_11 ); + +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 57 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 58 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 59 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 60 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 61 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 62 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_8 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_9 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_10 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_11 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_8 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_9 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_10 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_0 ); @@ -4145,263 +4094,231 @@ REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_2 , 62 , SH_UN REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV3_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_8 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_9 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_10 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_11 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_12 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_13 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_14 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_15 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_16 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_17 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_18 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_19 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_20 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_21 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_22 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_23 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_24 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_25 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_26 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_27 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_28 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_29 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_30 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_31 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_32 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_33 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_34 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_35 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_36 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_37 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_38 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_39 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_40 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_41 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_42 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_43 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_44 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_45 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_46 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_47 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_48 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_49 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_50 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_51 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_52 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_53 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_54 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_55 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 57 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 58 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 59 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 60 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 61 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 62 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); - -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_8 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_9 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_10 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_11 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_12 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_13 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_14 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_15 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_16 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_17 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_18 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_19 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_20 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_21 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_22 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_23 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_24 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_25 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_26 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_27 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_28 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_29 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_30 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_31 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_32 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_33 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_34 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_35 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_36 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_37 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_38 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_39 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_40 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_41 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_42 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_43 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_44 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_45 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_46 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_47 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_48 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_49 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_50 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_51 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_52 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_53 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_54 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_55 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_8 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_9 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_10 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_11 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_8 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_9 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_10 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_11 ); + +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 57 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 58 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 59 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 60 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 61 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 62 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_8 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_9 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_10 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_11 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_8 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_9 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_10 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_0 ); @@ -4532,392 +4449,344 @@ REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_62 , 62 , SH_UN REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_8 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_9 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_10 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_11 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_12 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_13 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_14 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_15 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_16 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_17 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_18 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_19 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_20 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_21 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_22 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_23 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_24 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_25 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_26 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_27 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_28 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_29 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_30 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_31 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_32 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_33 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_34 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_35 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_36 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_37 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_38 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_39 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_40 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_41 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_42 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_43 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_44 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_45 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_46 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_47 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_48 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_49 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_50 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_51 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_52 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_53 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_54 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_55 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 57 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 58 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 59 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 60 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 61 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 62 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); - -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_8 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_9 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_10 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_11 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_12 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_13 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_14 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_15 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_16 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_17 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_18 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_19 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_20 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_21 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_22 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_23 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_24 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_25 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_26 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_27 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_28 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_29 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_30 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_31 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_32 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_33 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_34 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_35 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_36 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_37 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_38 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_39 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_40 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_41 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_42 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_43 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_44 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_45 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_46 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_47 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_48 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_49 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_50 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_51 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_52 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_53 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_54 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_55 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_8 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_9 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_10 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_11 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_8 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_9 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_10 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_11 ); + +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 57 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 58 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 59 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 60 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 61 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 62 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); - -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_8 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_9 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_10 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_11 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_12 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_13 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_14 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_15 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_16 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_17 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_18 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_19 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_20 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_21 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_22 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_23 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_24 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_25 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_26 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_27 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_28 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_29 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_30 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_31 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_32 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_33 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_34 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_35 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_36 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_37 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_38 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_39 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_40 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_41 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_42 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_43 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_44 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_45 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_46 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_47 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_48 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_49 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_50 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_51 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_52 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_53 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_54 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_55 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_8 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_9 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_10 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_11 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_8 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_9 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_10 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_11 ); + +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 57 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 58 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 59 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 60 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 61 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 62 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_8 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_9 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_10 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_11 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_8 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_9 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_10 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_0 ); @@ -5048,263 +4917,231 @@ REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_2 , 62 , SH_UN REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV3_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_8 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_9 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_10 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_11 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_12 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_13 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_14 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_15 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_16 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_17 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_18 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_19 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_20 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_21 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_22 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_23 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_24 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_25 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_26 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_27 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_28 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_29 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_30 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_31 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_32 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_33 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_34 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_35 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_36 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_37 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_38 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_39 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_40 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_41 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_42 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_43 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_44 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_45 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_46 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_47 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_48 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_49 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_50 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_51 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_52 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_53 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_54 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_55 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 57 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 58 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 59 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 60 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 61 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 62 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); - -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_8 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_9 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_10 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_11 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_12 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_13 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_14 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_15 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_16 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_17 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_18 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_19 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_20 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_21 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_22 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_23 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_24 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_25 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_26 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_27 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_28 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_29 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_30 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_31 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_32 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_33 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_34 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_35 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_36 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_37 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_38 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_39 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_40 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_41 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_42 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_43 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_44 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_45 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_46 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_47 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_48 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_49 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_50 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_51 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_52 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_53 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_54 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_NLG_55 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_8 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_9 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_10 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_11 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_8 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_9 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_10 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_11 ); + +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 57 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 58 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 59 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 60 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 61 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 62 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_8 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_9 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_10 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_11 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_8 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_9 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_10 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_0 ); @@ -5564,134 +5401,247 @@ REG64_FLD( NV_CERR_FIRST1_NTL_62 , 62 , SH_UN REG64_FLD( NV_CERR_FIRST1_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_FWD_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_FWD_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_FWD_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_FWD_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_AUE_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_AUE_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_AUE_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_AUE_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBP_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_8 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_9 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_10 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBF_11 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_8 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_9 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_10 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_PBC_11 ); + +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_8 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_9 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_10 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_11 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_12 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_13 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_14 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_15 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_16 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_17 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_18 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_19 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_20 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_21 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_22 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_23 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_24 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_25 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_26 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_27 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_28 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_29 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_30 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_31 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_32 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_33 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_34 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_35 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_36 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_37 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_38 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_39 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_40 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_41 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_42 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_43 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_44 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_45 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_46 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_47 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_48 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_49 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_50 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_51 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_52 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_53 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_54 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_55 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_FWD_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 57 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_FWD_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 58 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_FWD_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 59 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_FWD_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 60 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_AUE_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 61 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_AUE_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 62 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_AUE_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_FIRST_AUE_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_56 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_57 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_58 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_59 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_60 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_61 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_62 ); +REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_63 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_0 ); @@ -5822,134 +5772,521 @@ REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_62 , 62 , SH_UN REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( NV_CERR_FIRST2_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_0 ); -REG64_FLD( NV_CERR_FIRST2_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_1 ); -REG64_FLD( NV_CERR_FIRST2_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_2 ); -REG64_FLD( NV_CERR_FIRST2_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_3 ); -REG64_FLD( NV_CERR_FIRST2_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_4 ); -REG64_FLD( NV_CERR_FIRST2_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_5 ); -REG64_FLD( NV_CERR_FIRST2_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_6 ); -REG64_FLD( NV_CERR_FIRST2_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_7 ); -REG64_FLD( NV_CERR_FIRST2_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_8 ); -REG64_FLD( NV_CERR_FIRST2_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_9 ); -REG64_FLD( NV_CERR_FIRST2_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_10 ); -REG64_FLD( NV_CERR_FIRST2_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_11 ); -REG64_FLD( NV_CERR_FIRST2_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_12 ); -REG64_FLD( NV_CERR_FIRST2_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_13 ); -REG64_FLD( NV_CERR_FIRST2_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_14 ); -REG64_FLD( NV_CERR_FIRST2_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_15 ); -REG64_FLD( NV_CERR_FIRST2_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_16 ); -REG64_FLD( NV_CERR_FIRST2_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_17 ); -REG64_FLD( NV_CERR_FIRST2_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_18 ); -REG64_FLD( NV_CERR_FIRST2_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_19 ); -REG64_FLD( NV_CERR_FIRST2_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_20 ); -REG64_FLD( NV_CERR_FIRST2_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_21 ); -REG64_FLD( NV_CERR_FIRST2_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_22 ); -REG64_FLD( NV_CERR_FIRST2_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_23 ); -REG64_FLD( NV_CERR_FIRST2_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_24 ); -REG64_FLD( NV_CERR_FIRST2_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_25 ); -REG64_FLD( NV_CERR_FIRST2_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_26 ); -REG64_FLD( NV_CERR_FIRST2_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_27 ); -REG64_FLD( NV_CERR_FIRST2_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_28 ); -REG64_FLD( NV_CERR_FIRST2_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_29 ); -REG64_FLD( NV_CERR_FIRST2_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_30 ); -REG64_FLD( NV_CERR_FIRST2_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_31 ); -REG64_FLD( NV_CERR_FIRST2_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_32 ); -REG64_FLD( NV_CERR_FIRST2_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_33 ); -REG64_FLD( NV_CERR_FIRST2_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_34 ); -REG64_FLD( NV_CERR_FIRST2_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_35 ); -REG64_FLD( NV_CERR_FIRST2_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_36 ); -REG64_FLD( NV_CERR_FIRST2_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_37 ); -REG64_FLD( NV_CERR_FIRST2_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_38 ); -REG64_FLD( NV_CERR_FIRST2_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_39 ); -REG64_FLD( NV_CERR_FIRST2_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_40 ); -REG64_FLD( NV_CERR_FIRST2_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_41 ); -REG64_FLD( NV_CERR_FIRST2_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_42 ); -REG64_FLD( NV_CERR_FIRST2_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_43 ); -REG64_FLD( NV_CERR_FIRST2_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_44 ); -REG64_FLD( NV_CERR_FIRST2_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_45 ); -REG64_FLD( NV_CERR_FIRST2_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_46 ); -REG64_FLD( NV_CERR_FIRST2_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_47 ); -REG64_FLD( NV_CERR_FIRST2_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_48 ); -REG64_FLD( NV_CERR_FIRST2_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_49 ); -REG64_FLD( NV_CERR_FIRST2_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_50 ); -REG64_FLD( NV_CERR_FIRST2_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_51 ); -REG64_FLD( NV_CERR_FIRST2_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_52 ); -REG64_FLD( NV_CERR_FIRST2_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_53 ); -REG64_FLD( NV_CERR_FIRST2_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_54 ); -REG64_FLD( NV_CERR_FIRST2_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_55 ); -REG64_FLD( NV_CERR_FIRST2_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_56 ); -REG64_FLD( NV_CERR_FIRST2_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_57 ); -REG64_FLD( NV_CERR_FIRST2_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_58 ); -REG64_FLD( NV_CERR_FIRST2_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_59 ); -REG64_FLD( NV_CERR_FIRST2_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_60 ); -REG64_FLD( NV_CERR_FIRST2_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_61 ); -REG64_FLD( NV_CERR_FIRST2_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_62 ); -REG64_FLD( NV_CERR_FIRST2_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_63 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_8 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_9 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_10 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_11 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_12 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_13 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_14 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_15 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_16 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_17 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_18 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_19 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_20 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_21 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_22 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_23 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_24 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_25 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_26 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_27 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_28 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_29 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_30 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_31 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_32 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_33 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_34 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_35 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_36 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_37 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_38 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_39 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_40 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_41 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_42 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_43 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_44 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_45 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_46 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_47 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_48 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_49 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_50 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_51 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_52 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_53 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_54 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_55 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_56 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_57 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_58 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_59 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_60 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_61 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_62 ); +REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_63 ); + +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_8 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_9 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_10 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_11 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_12 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_13 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_14 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_15 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_16 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_17 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_18 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_19 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_20 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_21 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_22 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_23 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_24 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_25 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_26 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_27 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_28 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_29 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_30 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_31 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_32 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_33 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_34 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_35 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_36 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_37 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_38 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_39 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_40 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_41 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_42 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_43 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_44 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_45 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_46 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_47 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_48 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_49 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_50 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_51 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_52 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_53 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_54 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_55 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_56 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_57 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_58 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_59 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_60 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_61 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_62 ); +REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_63 ); + +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_8 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_9 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_10 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_11 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_12 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_13 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_14 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_15 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_16 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_17 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_18 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_19 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_20 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_21 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_22 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_23 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_24 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_25 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_26 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_27 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_28 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_29 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_30 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_31 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_32 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_33 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_34 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_35 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_36 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_37 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_38 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_39 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_40 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_41 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_42 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_43 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_44 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_45 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_46 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_47 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_48 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_49 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_50 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_51 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_52 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_53 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_54 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_55 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_56 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_57 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_58 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_59 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_60 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_61 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_62 ); +REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_63 ); + +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_8 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_9 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_10 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_11 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_12 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_13 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_14 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_15 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_16 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_17 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_18 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_19 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_20 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_21 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_22 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_23 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_24 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_25 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_26 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_27 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_28 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_29 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_30 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_31 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_32 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_33 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_34 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_35 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_36 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_37 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_38 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_39 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_40 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_41 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_42 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_43 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_44 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_45 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_46 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_47 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_48 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_49 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_50 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_51 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_52 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_53 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_54 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_55 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_56 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_57 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_58 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_59 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_60 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_61 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_62 ); +REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_63 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_0 ); @@ -6080,908 +6417,1772 @@ REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_62 , 62 , SH_UN REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_0 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_1 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_2 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_3 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_4 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_5 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_6 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_7 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_8 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_8 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_9 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_9 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_10 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_10 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_11 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_11 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_0 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_1 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_2 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_3 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_4 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_5 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_6 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_7 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_8 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_9 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_10 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_11 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_12 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_13 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_14 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_15 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_16 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_17 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_18 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_19 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_20 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_21 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_22 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_23 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_24 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_25 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_26 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_27 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_28 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_29 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_30 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_31 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_32 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_33 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_34 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_35 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_36 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_37 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_38 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_39 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_40 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_41 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_42 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_43 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_44 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_45 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_46 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_47 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_48 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_49 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_50 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_51 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_52 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_53 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_54 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_55 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_56 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_57 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_58 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_59 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_60 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_61 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_62 ); +REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_63 ); + +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_8 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_9 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_10 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_11 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_12 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_13 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_14 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_15 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_16 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_17 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_18 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_19 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_20 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_21 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_22 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_23 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_24 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_25 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_26 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_27 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_28 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_29 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_30 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_31 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_32 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_33 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_34 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_35 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_36 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_37 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_38 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_39 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_40 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_41 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_42 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_43 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_44 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_45 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_46 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_47 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_48 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_49 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_50 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_51 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_52 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_53 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_54 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_55 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_56 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_57 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_58 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_59 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_60 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_61 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_62 ); +REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_63 ); + +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_8 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_9 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_10 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_11 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_12 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_13 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_14 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_15 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_16 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_17 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_18 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_19 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_20 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_21 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_22 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_23 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_24 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_25 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_26 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_27 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_28 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_29 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_30 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_31 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_32 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_33 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_34 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_35 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_36 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_37 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_38 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_39 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_40 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_41 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_42 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_43 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_44 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_45 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_46 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_47 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_48 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_49 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_50 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_51 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_52 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_53 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_54 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_55 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_56 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_57 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_58 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_59 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_60 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_61 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_62 ); +REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_63 ); + +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_8 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_9 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_10 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_11 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_12 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_13 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_14 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_15 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_16 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_17 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_18 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_19 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_20 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_21 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_22 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_23 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_24 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_25 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_26 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_27 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_28 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_29 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_30 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_31 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_32 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_33 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_34 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_35 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_36 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_37 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_38 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_39 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_40 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_41 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_42 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_43 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_44 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_45 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_46 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_47 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_48 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_49 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_50 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_51 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_52 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_53 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_54 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_55 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_56 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_57 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_58 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_59 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_60 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_61 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_62 ); +REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_63 ); + +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_8 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_9 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_10 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_11 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_12 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_13 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_14 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_15 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_16 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_17 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_18 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_19 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_20 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_21 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_22 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_23 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_24 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_25 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_26 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_27 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_28 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_29 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_30 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_31 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_32 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_33 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_34 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_35 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_36 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_37 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_38 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_39 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_40 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_41 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_42 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_43 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_44 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_45 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_46 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_47 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_48 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_49 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_50 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_51 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_52 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_53 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_54 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_55 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_56 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_57 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_58 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_59 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_60 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_61 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_62 ); +REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_63 ); + +REG64_FLD( NV_CERR_FIRST2_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_0 ); +REG64_FLD( NV_CERR_FIRST2_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_1 ); +REG64_FLD( NV_CERR_FIRST2_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_2 ); +REG64_FLD( NV_CERR_FIRST2_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_3 ); +REG64_FLD( NV_CERR_FIRST2_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_4 ); +REG64_FLD( NV_CERR_FIRST2_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_5 ); +REG64_FLD( NV_CERR_FIRST2_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_6 ); +REG64_FLD( NV_CERR_FIRST2_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_7 ); +REG64_FLD( NV_CERR_FIRST2_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_8 ); +REG64_FLD( NV_CERR_FIRST2_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_9 ); +REG64_FLD( NV_CERR_FIRST2_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_10 ); +REG64_FLD( NV_CERR_FIRST2_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_11 ); +REG64_FLD( NV_CERR_FIRST2_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_12 ); +REG64_FLD( NV_CERR_FIRST2_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_13 ); +REG64_FLD( NV_CERR_FIRST2_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_14 ); +REG64_FLD( NV_CERR_FIRST2_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_15 ); +REG64_FLD( NV_CERR_FIRST2_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_16 ); +REG64_FLD( NV_CERR_FIRST2_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_17 ); +REG64_FLD( NV_CERR_FIRST2_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_18 ); +REG64_FLD( NV_CERR_FIRST2_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_19 ); +REG64_FLD( NV_CERR_FIRST2_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_20 ); +REG64_FLD( NV_CERR_FIRST2_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_21 ); +REG64_FLD( NV_CERR_FIRST2_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_22 ); +REG64_FLD( NV_CERR_FIRST2_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_23 ); +REG64_FLD( NV_CERR_FIRST2_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_24 ); +REG64_FLD( NV_CERR_FIRST2_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_25 ); +REG64_FLD( NV_CERR_FIRST2_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_26 ); +REG64_FLD( NV_CERR_FIRST2_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_27 ); +REG64_FLD( NV_CERR_FIRST2_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_28 ); +REG64_FLD( NV_CERR_FIRST2_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_29 ); +REG64_FLD( NV_CERR_FIRST2_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_30 ); +REG64_FLD( NV_CERR_FIRST2_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_31 ); +REG64_FLD( NV_CERR_FIRST2_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_32 ); +REG64_FLD( NV_CERR_FIRST2_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_33 ); +REG64_FLD( NV_CERR_FIRST2_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_34 ); +REG64_FLD( NV_CERR_FIRST2_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_35 ); +REG64_FLD( NV_CERR_FIRST2_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_36 ); +REG64_FLD( NV_CERR_FIRST2_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_37 ); +REG64_FLD( NV_CERR_FIRST2_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_38 ); +REG64_FLD( NV_CERR_FIRST2_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_39 ); +REG64_FLD( NV_CERR_FIRST2_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_40 ); +REG64_FLD( NV_CERR_FIRST2_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_41 ); +REG64_FLD( NV_CERR_FIRST2_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_42 ); +REG64_FLD( NV_CERR_FIRST2_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_43 ); +REG64_FLD( NV_CERR_FIRST2_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_44 ); +REG64_FLD( NV_CERR_FIRST2_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_45 ); +REG64_FLD( NV_CERR_FIRST2_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_46 ); +REG64_FLD( NV_CERR_FIRST2_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_47 ); +REG64_FLD( NV_CERR_FIRST2_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_48 ); +REG64_FLD( NV_CERR_FIRST2_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_49 ); +REG64_FLD( NV_CERR_FIRST2_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_50 ); +REG64_FLD( NV_CERR_FIRST2_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_51 ); +REG64_FLD( NV_CERR_FIRST2_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_52 ); +REG64_FLD( NV_CERR_FIRST2_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_53 ); +REG64_FLD( NV_CERR_FIRST2_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_54 ); +REG64_FLD( NV_CERR_FIRST2_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_55 ); +REG64_FLD( NV_CERR_FIRST2_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_56 ); +REG64_FLD( NV_CERR_FIRST2_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_57 ); +REG64_FLD( NV_CERR_FIRST2_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_58 ); +REG64_FLD( NV_CERR_FIRST2_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_59 ); +REG64_FLD( NV_CERR_FIRST2_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_60 ); +REG64_FLD( NV_CERR_FIRST2_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_61 ); +REG64_FLD( NV_CERR_FIRST2_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_62 ); +REG64_FLD( NV_CERR_FIRST2_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_63 ); + +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_8 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_9 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_10 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_11 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_12 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_13 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_14 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_15 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_16 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_17 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_18 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_19 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_20 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_21 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_22 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_23 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_24 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_25 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_26 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_27 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_28 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_29 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_30 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_31 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_32 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_33 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_34 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_35 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_36 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_37 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_38 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_39 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_40 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_41 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_42 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_43 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_44 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_45 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_46 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_47 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_48 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_49 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_50 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_51 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_52 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_53 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_54 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_55 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_56 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_57 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_58 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_59 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_60 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_61 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_62 ); +REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_63 ); + +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_8 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_9 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_10 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_11 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_12 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_13 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_14 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_15 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_16 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_17 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_18 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_19 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_20 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_21 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_22 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_23 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_24 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_25 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_26 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_27 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_28 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_29 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_30 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_31 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_32 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_33 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_34 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_35 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_36 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_37 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_38 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_39 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_40 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_41 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_42 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_43 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_44 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_45 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_46 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_47 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_48 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_49 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_50 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_51 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_52 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_53 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_54 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_55 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_56 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_57 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_58 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_59 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_60 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_61 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_62 ); +REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_FIRST_NLG_63 ); + +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_24 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_25 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_26 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_27 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_28 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_29 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_30 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_31 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 57 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 58 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 59 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 60 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 61 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 62 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); - -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_0 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_1 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_2 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_3 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_4 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_5 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_6 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_7 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_8 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_8 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_9 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_9 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_10 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_10 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_11 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_11 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_0 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_1 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_2 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_3 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_4 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_5 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_6 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_7 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_7 ); + +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_24 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_25 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_26 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_27 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_28 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_29 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_30 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_31 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 57 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 58 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 59 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 60 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 61 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 62 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); - -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_0 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_1 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_2 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_3 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_4 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_5 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_6 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_7 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_8 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_8 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_9 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_9 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_10 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_10 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_11 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_11 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_0 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_1 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_2 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_3 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_4 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_5 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_6 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_7 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_7 ); + +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_24 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_25 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_26 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_27 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_28 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_29 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_30 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_31 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 57 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 58 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 59 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 60 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 61 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 62 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); - -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_0 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_1 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_2 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_3 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_4 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_5 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_6 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_7 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_8 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_8 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_9 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_9 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_10 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_10 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_11 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_11 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_0 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_1 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_2 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_3 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_4 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_5 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_6 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_7 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_7 ); + +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_24 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_25 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_26 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_27 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_28 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_29 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_30 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_31 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 57 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 58 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 59 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 60 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 61 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 62 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); - -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBP_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_0 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_1 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_2 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_3 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_4 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_5 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_6 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_7 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_8 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_8 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_9 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_9 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_10 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_10 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBF_11 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_11 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_0 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_1 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_2 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_3 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_4 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_5 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_6 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBC_7 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_7 ); + +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_24 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_25 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_26 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_27 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_28 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_29 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_30 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_31 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 57 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 58 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 59 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 60 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 61 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 62 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); - -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_0 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_1 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_2 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_3 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_4 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_5 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_6 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_7 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_8 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_8 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_9 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_9 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_10 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_10 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_11 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_11 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_0 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_1 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_2 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_3 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_4 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_5 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_6 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_7 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_7 ); + +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_24 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_25 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_26 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_27 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_28 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_29 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_30 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_31 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 57 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 58 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 59 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 60 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 61 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 62 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); - -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_0 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_1 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_2 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_3 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_4 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_5 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_6 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_7 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_8 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_8 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_9 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_9 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_10 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_10 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_11 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_11 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_0 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_1 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_2 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_3 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_4 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_5 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_6 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_7 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_7 ); + +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_24 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_25 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_26 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_27 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_28 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_29 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_30 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_31 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 57 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 58 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 59 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 60 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 61 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 62 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_7 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_0 ); @@ -7103,401 +8304,329 @@ REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_2 , 58 , SH_UN SH_FLD_IDIAL_CTL_HOLD_DUE_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_3 , 59 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_3 ); -REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV4_0 , 60 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_HOLD_RSV4_0 ); -REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV4_1 , 61 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_HOLD_RSV4_1 ); -REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV4_2 , 62 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_HOLD_RSV4_2 ); -REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV4_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_HOLD_RSV4_3 ); - -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_0 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_1 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_2 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_3 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_4 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_5 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_6 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_7 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_8 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_8 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_9 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_9 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_10 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_10 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_11 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_11 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_0 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_1 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_2 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_3 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_4 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_5 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_6 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_7 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_0 , 60 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_HOLD_PEF_0 ); +REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_1 , 61 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_HOLD_PEF_1 ); +REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_2 , 62 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_HOLD_PEF_2 ); +REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_HOLD_PEF_3 ); + +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_24 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_25 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_26 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_27 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_28 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_29 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_30 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_31 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 57 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 58 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 59 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 60 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 61 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 62 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); - -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBP_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_0 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_1 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_2 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_3 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_4 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_5 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_6 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_7 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_8 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_8 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_9 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_9 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_10 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_10 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBF_11 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_11 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_0 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_1 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_2 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_3 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_4 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_5 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_6 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBC_7 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_7 ); + +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_24 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_25 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_26 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_27 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_28 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_29 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_30 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_31 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 57 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 58 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 59 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 60 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 61 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 62 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); - -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_0 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_1 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_2 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_3 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_4 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_5 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_6 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_7 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_8 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_8 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_9 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_9 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_10 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_10 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_11 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_11 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_0 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_1 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_2 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_3 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_4 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_5 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_6 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_7 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_7 ); + +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_24 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_25 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_26 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_27 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_28 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_29 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_30 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_31 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 57 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 58 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 59 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 60 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 61 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 62 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_7 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_0 ); @@ -7619,14 +8748,14 @@ REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_2 , 58 , SH_UN SH_FLD_IDIAL_CTL_HOLD_DUE_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_3 , 59 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_3 ); -REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV4_0 , 60 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_HOLD_RSV4_0 ); -REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV4_1 , 61 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_HOLD_RSV4_1 ); -REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV4_2 , 62 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_HOLD_RSV4_2 ); -REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV4_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_HOLD_RSV4_3 ); +REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_0 , 60 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_HOLD_PEF_0 ); +REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_1 , 61 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_HOLD_PEF_1 ); +REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_2 , 62 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_HOLD_PEF_2 ); +REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_HOLD_PEF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_0 ); @@ -7748,530 +8877,450 @@ REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_2 , 58 , SH_UN SH_FLD_IDIAL_CTL_HOLD_DUE_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_3 , 59 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_3 ); -REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV4_0 , 60 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_HOLD_RSV4_0 ); -REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV4_1 , 61 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_HOLD_RSV4_1 ); -REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV4_2 , 62 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_HOLD_RSV4_2 ); -REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV4_3 , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_HOLD_RSV4_3 ); - -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBP_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_0 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_1 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_2 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_3 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_4 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_5 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_6 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_7 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_8 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_8 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_9 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_9 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_10 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_10 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBF_11 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_11 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_0 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_1 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_2 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_3 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_4 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_5 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_6 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBC_7 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_0 , 60 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_HOLD_PEF_0 ); +REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_1 , 61 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_HOLD_PEF_1 ); +REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_2 , 62 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_HOLD_PEF_2 ); +REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_3 , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_HOLD_PEF_3 ); + +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_24 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_25 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_26 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_27 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_28 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_29 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_30 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_31 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 57 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 58 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 59 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 60 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 61 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 62 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); - -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBP_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBP_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_0 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_1 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_2 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_3 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_4 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_5 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_6 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_7 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_8 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_8 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_9 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_9 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_10 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_10 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBF_11 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBF_11 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_0 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_1 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_2 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_3 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_4 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_5 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_6 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBC_7 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_PBC_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NCF_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_7 ); + +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_24 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_25 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_26 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_27 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_28 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_29 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_30 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NVF_31 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NCF_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 57 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 58 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 59 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 60 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 61 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 62 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); - -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_8 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_9 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_10 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_11 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_12 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_13 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_14 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_15 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_16 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_17 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_18 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_19 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_20 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_21 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_22 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_23 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_24 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_25 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_26 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_27 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_28 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_29 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_30 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_31 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_32 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_33 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_34 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_35 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_36 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_37 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_38 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_39 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_40 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_41 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_42 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_43 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_44 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_45 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_46 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_47 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_48 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_49 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_50 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_51 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_52 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_53 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_54 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_55 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBR_7 ); + +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 57 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 58 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 59 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 60 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 61 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 62 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); - -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_8 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_9 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_10 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_11 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_12 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_13 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_14 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_15 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_16 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_17 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_18 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_19 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_20 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_21 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_22 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_23 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_24 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_25 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_26 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_27 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_28 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_29 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_30 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_31 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_32 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_33 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_34 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_35 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_36 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_37 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_38 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_39 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_40 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_41 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_42 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_43 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_44 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_45 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_46 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_47 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_48 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_49 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_50 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_51 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_52 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_53 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_54 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_55 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_8 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_9 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_10 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_11 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_8 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_9 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_10 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_11 ); + +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 57 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 58 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 59 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 60 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 61 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 62 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_8 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_9 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_10 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_11 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_8 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_9 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_10 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_0 ); @@ -8402,263 +9451,231 @@ REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_62 , 62 , SH_UN REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_8 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_9 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_10 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_11 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_12 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_13 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_14 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_15 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_16 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_17 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_18 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_19 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_20 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_21 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_22 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_23 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_24 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_25 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_26 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_27 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_28 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_29 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_30 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_31 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_32 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_33 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_34 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_35 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_36 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_37 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_38 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_39 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_40 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_41 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_42 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_43 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_44 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_45 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_46 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_47 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_48 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_49 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_50 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_51 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_52 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_53 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_54 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_55 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 57 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 58 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 59 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 60 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 61 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 62 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); - -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_8 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_9 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_10 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_11 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_12 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_13 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_14 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_15 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_16 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_17 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_18 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_19 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_20 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_21 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_22 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_23 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_24 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_25 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_26 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_27 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_28 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_29 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_30 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_31 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_32 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_33 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_34 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_35 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_36 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_37 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_38 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_39 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_40 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_41 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_42 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_43 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_44 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_45 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_46 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_47 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_48 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_49 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_50 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_51 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_52 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_53 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_54 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_55 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_8 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_9 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_10 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_11 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_8 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_9 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_10 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_11 ); + +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 57 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 58 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 59 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 60 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 61 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 62 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_8 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_9 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_10 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_11 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_8 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_9 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_10 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_0 ); @@ -8789,263 +9806,231 @@ REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_2 , 62 , SH_UN REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV3_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_8 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_9 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_10 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_11 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_12 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_13 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_14 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_15 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_16 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_17 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_18 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_19 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_20 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_21 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_22 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_23 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_24 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_25 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_26 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_27 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_28 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_29 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_30 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_31 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_32 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_33 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_34 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_35 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_36 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_37 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_38 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_39 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_40 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_41 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_42 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_43 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_44 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_45 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_46 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_47 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_48 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_49 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_50 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_51 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_52 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_53 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_54 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_55 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 57 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 58 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 59 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 60 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 61 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 62 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); - -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_8 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_9 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_10 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_11 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_12 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_13 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_14 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_15 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_16 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_17 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_18 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_19 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_20 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_21 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_22 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_23 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_24 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_25 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_26 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_27 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_28 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_29 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_30 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_31 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_32 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_33 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_34 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_35 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_36 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_37 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_38 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_39 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_40 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_41 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_42 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_43 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_44 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_45 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_46 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_47 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_48 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_49 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_50 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_51 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_52 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_53 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_54 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_55 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_8 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_9 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_10 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_11 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_8 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_9 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_10 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_11 ); + +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 57 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 58 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 59 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 60 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 61 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 62 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_8 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_9 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_10 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_11 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_8 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_9 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_10 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_0 ); @@ -9176,392 +10161,344 @@ REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_62 , 62 , SH_UN REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_8 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_9 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_10 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_11 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_12 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_13 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_14 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_15 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_16 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_17 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_18 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_19 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_20 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_21 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_22 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_23 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_24 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_25 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_26 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_27 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_28 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_29 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_30 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_31 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_32 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_33 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_34 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_35 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_36 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_37 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_38 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_39 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_40 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_41 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_42 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_43 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_44 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_45 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_46 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_47 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_48 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_49 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_50 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_51 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_52 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_53 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_54 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_55 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 57 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 58 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 59 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 60 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 61 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 62 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); - -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_8 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_9 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_10 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_11 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_12 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_13 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_14 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_15 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_16 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_17 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_18 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_19 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_20 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_21 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_22 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_23 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_24 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_25 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_26 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_27 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_28 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_29 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_30 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_31 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_32 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_33 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_34 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_35 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_36 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_37 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_38 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_39 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_40 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_41 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_42 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_43 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_44 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_45 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_46 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_47 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_48 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_49 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_50 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_51 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_52 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_53 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_54 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_55 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_8 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_9 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_10 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_11 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_8 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_9 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_10 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_11 ); + +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 57 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 58 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 59 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 60 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 61 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 62 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); - -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_8 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_9 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_10 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_11 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_12 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_13 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_14 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_15 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_16 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_17 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_18 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_19 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_20 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_21 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_22 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_23 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_24 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_25 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_26 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_27 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_28 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_29 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_30 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_31 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_32 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_33 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_34 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_35 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_36 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_37 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_38 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_39 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_40 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_41 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_42 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_43 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_44 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_45 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_46 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_47 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_48 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_49 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_50 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_51 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_52 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_53 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_54 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_55 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_8 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_9 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_10 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_11 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_8 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_9 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_10 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_11 ); + +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 57 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 58 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 59 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 60 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 61 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 62 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_8 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_9 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_10 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_11 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_8 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_9 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_10 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_0 ); @@ -9692,263 +10629,231 @@ REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_2 , 62 , SH_UN REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV3_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_8 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_9 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_10 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_11 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_12 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_13 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_14 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_15 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_16 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_17 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_18 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_19 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_20 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_21 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_22 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_23 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_24 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_25 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_26 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_27 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_28 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_29 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_30 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_31 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_32 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_33 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_34 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_35 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_36 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_37 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_38 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_39 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_40 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_41 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_42 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_43 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_44 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_45 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_46 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_47 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_48 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_49 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_50 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_51 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_52 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_53 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_54 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_55 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 57 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 58 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 59 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 60 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 61 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 62 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); - -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_8 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_9 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_10 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_11 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_12 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_13 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_14 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_15 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_16 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_17 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_18 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_19 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_20 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_21 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_22 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_23 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_24 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_25 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_26 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_27 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_28 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_29 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_30 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_31 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_32 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_33 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_34 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_35 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_36 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_37 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_38 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_39 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_40 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_41 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_42 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_43 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_44 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_45 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_46 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_47 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_48 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_49 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_50 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_51 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_52 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_53 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_54 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_NLG_55 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_8 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_9 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_10 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_11 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_8 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_9 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_10 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_11 ); + +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 57 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 58 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 59 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 60 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 61 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 62 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_8 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_9 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_10 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_11 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_8 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_9 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_10 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_0 ); @@ -10208,134 +11113,247 @@ REG64_FLD( NV_CERR_HOLD1_NTL_62 , 62 , SH_UN REG64_FLD( NV_CERR_HOLD1_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_FWD_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_FWD_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_FWD_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_FWD_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_AUE_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_AUE_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_AUE_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_AUE_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBP_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_8 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_9 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_10 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBF_11 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_8 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_9 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_10 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_PBC_11 ); + +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_8 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_9 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_10 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_11 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_12 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_13 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_14 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_15 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_16 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_17 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_18 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_19 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_20 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_21 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_22 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_23 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_24 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_25 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_26 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_27 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_28 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_29 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_30 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_31 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_32 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_33 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_34 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_35 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_36 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_37 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_38 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_39 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_40 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_41 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_42 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_43 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_44 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_45 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_46 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_47 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_48 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_49 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_50 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_51 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_52 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_53 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_54 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_55 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_FWD_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 57 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_FWD_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 58 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_FWD_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 59 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_FWD_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 60 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_AUE_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 61 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_AUE_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 62 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_AUE_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_HOLD_AUE_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_56 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_57 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_58 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_59 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_60 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_61 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_62 ); +REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_63 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_0 ); @@ -10466,134 +11484,521 @@ REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_62 , 62 , SH_UN REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( NV_CERR_HOLD2_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_0 ); -REG64_FLD( NV_CERR_HOLD2_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_1 ); -REG64_FLD( NV_CERR_HOLD2_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_2 ); -REG64_FLD( NV_CERR_HOLD2_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_3 ); -REG64_FLD( NV_CERR_HOLD2_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_4 ); -REG64_FLD( NV_CERR_HOLD2_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_5 ); -REG64_FLD( NV_CERR_HOLD2_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_6 ); -REG64_FLD( NV_CERR_HOLD2_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_7 ); -REG64_FLD( NV_CERR_HOLD2_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_8 ); -REG64_FLD( NV_CERR_HOLD2_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_9 ); -REG64_FLD( NV_CERR_HOLD2_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_10 ); -REG64_FLD( NV_CERR_HOLD2_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_11 ); -REG64_FLD( NV_CERR_HOLD2_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_12 ); -REG64_FLD( NV_CERR_HOLD2_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_13 ); -REG64_FLD( NV_CERR_HOLD2_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_14 ); -REG64_FLD( NV_CERR_HOLD2_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_15 ); -REG64_FLD( NV_CERR_HOLD2_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_16 ); -REG64_FLD( NV_CERR_HOLD2_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_17 ); -REG64_FLD( NV_CERR_HOLD2_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_18 ); -REG64_FLD( NV_CERR_HOLD2_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_19 ); -REG64_FLD( NV_CERR_HOLD2_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_20 ); -REG64_FLD( NV_CERR_HOLD2_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_21 ); -REG64_FLD( NV_CERR_HOLD2_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_22 ); -REG64_FLD( NV_CERR_HOLD2_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_23 ); -REG64_FLD( NV_CERR_HOLD2_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_24 ); -REG64_FLD( NV_CERR_HOLD2_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_25 ); -REG64_FLD( NV_CERR_HOLD2_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_26 ); -REG64_FLD( NV_CERR_HOLD2_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_27 ); -REG64_FLD( NV_CERR_HOLD2_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_28 ); -REG64_FLD( NV_CERR_HOLD2_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_29 ); -REG64_FLD( NV_CERR_HOLD2_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_30 ); -REG64_FLD( NV_CERR_HOLD2_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_31 ); -REG64_FLD( NV_CERR_HOLD2_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_32 ); -REG64_FLD( NV_CERR_HOLD2_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_33 ); -REG64_FLD( NV_CERR_HOLD2_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_34 ); -REG64_FLD( NV_CERR_HOLD2_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_35 ); -REG64_FLD( NV_CERR_HOLD2_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_36 ); -REG64_FLD( NV_CERR_HOLD2_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_37 ); -REG64_FLD( NV_CERR_HOLD2_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_38 ); -REG64_FLD( NV_CERR_HOLD2_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_39 ); -REG64_FLD( NV_CERR_HOLD2_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_40 ); -REG64_FLD( NV_CERR_HOLD2_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_41 ); -REG64_FLD( NV_CERR_HOLD2_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_42 ); -REG64_FLD( NV_CERR_HOLD2_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_43 ); -REG64_FLD( NV_CERR_HOLD2_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_44 ); -REG64_FLD( NV_CERR_HOLD2_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_45 ); -REG64_FLD( NV_CERR_HOLD2_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_46 ); -REG64_FLD( NV_CERR_HOLD2_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_47 ); -REG64_FLD( NV_CERR_HOLD2_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_48 ); -REG64_FLD( NV_CERR_HOLD2_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_49 ); -REG64_FLD( NV_CERR_HOLD2_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_50 ); -REG64_FLD( NV_CERR_HOLD2_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_51 ); -REG64_FLD( NV_CERR_HOLD2_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_52 ); -REG64_FLD( NV_CERR_HOLD2_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_53 ); -REG64_FLD( NV_CERR_HOLD2_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_54 ); -REG64_FLD( NV_CERR_HOLD2_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_55 ); -REG64_FLD( NV_CERR_HOLD2_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_56 ); -REG64_FLD( NV_CERR_HOLD2_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_57 ); -REG64_FLD( NV_CERR_HOLD2_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_58 ); -REG64_FLD( NV_CERR_HOLD2_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_59 ); -REG64_FLD( NV_CERR_HOLD2_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_60 ); -REG64_FLD( NV_CERR_HOLD2_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_61 ); -REG64_FLD( NV_CERR_HOLD2_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_62 ); -REG64_FLD( NV_CERR_HOLD2_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_63 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_8 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_9 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_10 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_11 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_12 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_13 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_14 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_15 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_16 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_17 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_18 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_19 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_20 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_21 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_22 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_23 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_24 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_25 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_26 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_27 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_28 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_29 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_30 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_31 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_32 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_33 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_34 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_35 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_36 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_37 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_38 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_39 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_40 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_41 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_42 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_43 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_44 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_45 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_46 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_47 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_48 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_49 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_50 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_51 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_52 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_53 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_54 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_55 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_56 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_57 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_58 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_59 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_60 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_61 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_62 ); +REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_63 ); + +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_8 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_9 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_10 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_11 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_12 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_13 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_14 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_15 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_16 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_17 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_18 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_19 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_20 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_21 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_22 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_23 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_24 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_25 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_26 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_27 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_28 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_29 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_30 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_31 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_32 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_33 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_34 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_35 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_36 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_37 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_38 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_39 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_40 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_41 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_42 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_43 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_44 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_45 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_46 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_47 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_48 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_49 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_50 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_51 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_52 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_53 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_54 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_55 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_56 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_57 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_58 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_59 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_60 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_61 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_62 ); +REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_63 ); + +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_8 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_9 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_10 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_11 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_12 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_13 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_14 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_15 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_16 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_17 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_18 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_19 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_20 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_21 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_22 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_23 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_24 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_25 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_26 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_27 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_28 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_29 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_30 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_31 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_32 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_33 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_34 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_35 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_36 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_37 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_38 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_39 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_40 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_41 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_42 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_43 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_44 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_45 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_46 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_47 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_48 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_49 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_50 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_51 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_52 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_53 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_54 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_55 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_56 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_57 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_58 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_59 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_60 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_61 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_62 ); +REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_63 ); + +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_8 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_9 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_10 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_11 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_12 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_13 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_14 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_15 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_16 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_17 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_18 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_19 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_20 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_21 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_22 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_23 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_24 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_25 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_26 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_27 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_28 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_29 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_30 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_31 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_32 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_33 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_34 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_35 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_36 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_37 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_38 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_39 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_40 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_41 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_42 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_43 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_44 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_45 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_46 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_47 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_48 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_49 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_50 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_51 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_52 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_53 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_54 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_55 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_56 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_57 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_58 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_59 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_60 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_61 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_62 ); +REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_63 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_0 ); @@ -10724,965 +12129,1883 @@ REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_62 , 62 , SH_UN REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( PU_NPU0_CERR_LOG_FIRST_BITS , 60 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_8 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_9 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_10 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_11 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_12 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_13 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_14 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_15 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_16 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_17 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_18 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_19 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_20 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_21 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_22 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_23 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_24 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_25 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_26 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_27 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_28 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_29 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_30 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_31 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_32 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_33 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_34 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_35 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_36 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_37 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_38 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_39 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_40 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_41 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_42 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_43 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_44 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_45 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_46 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_47 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_48 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_49 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_50 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_51 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_52 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_53 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_54 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_55 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_56 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_57 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_58 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_59 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_60 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_61 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_62 ); +REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_63 ); + +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_8 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_9 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_10 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_11 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_12 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_13 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_14 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_15 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_16 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_17 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_18 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_19 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_20 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_21 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_22 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_23 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_24 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_25 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_26 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_27 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_28 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_29 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_30 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_31 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_32 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_33 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_34 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_35 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_36 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_37 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_38 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_39 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_40 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_41 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_42 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_43 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_44 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_45 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_46 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_47 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_48 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_49 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_50 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_51 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_52 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_53 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_54 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_55 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_56 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_57 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_58 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_59 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_60 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_61 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_62 ); +REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_63 ); + +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_8 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_9 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_10 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_11 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_12 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_13 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_14 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_15 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_16 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_17 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_18 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_19 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_20 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_21 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_22 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_23 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_24 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_25 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_26 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_27 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_28 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_29 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_30 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_31 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_32 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_33 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_34 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_35 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_36 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_37 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_38 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_39 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_40 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_41 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_42 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_43 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_44 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_45 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_46 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_47 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_48 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_49 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_50 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_51 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_52 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_53 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_54 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_55 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_56 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_57 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_58 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_59 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_60 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_61 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_62 ); +REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_63 ); + +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_8 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_9 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_10 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_11 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_12 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_13 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_14 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_15 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_16 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_17 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_18 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_19 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_20 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_21 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_22 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_23 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_24 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_25 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_26 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_27 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_28 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_29 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_30 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_31 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_32 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_33 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_34 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_35 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_36 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_37 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_38 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_39 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_40 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_41 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_42 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_43 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_44 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_45 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_46 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_47 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_48 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_49 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_50 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_51 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_52 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_53 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_54 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_55 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_56 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_57 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_58 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_59 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_60 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_61 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_62 ); +REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_63 ); + +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_8 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_9 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_10 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_11 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_12 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_13 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_14 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_15 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_16 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_17 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_18 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_19 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_20 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_21 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_22 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_23 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_24 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_25 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_26 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_27 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_28 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_29 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_30 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_31 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_32 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_33 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_34 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_35 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_36 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_37 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_38 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_39 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_40 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_41 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_42 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_43 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_44 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_45 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_46 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_47 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_48 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_49 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_50 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_51 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_52 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_53 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_54 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_55 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_56 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_57 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_58 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_59 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_60 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_61 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_62 ); +REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_63 ); + +REG64_FLD( NV_CERR_HOLD2_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_0 ); +REG64_FLD( NV_CERR_HOLD2_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_1 ); +REG64_FLD( NV_CERR_HOLD2_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_2 ); +REG64_FLD( NV_CERR_HOLD2_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_3 ); +REG64_FLD( NV_CERR_HOLD2_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_4 ); +REG64_FLD( NV_CERR_HOLD2_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_5 ); +REG64_FLD( NV_CERR_HOLD2_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_6 ); +REG64_FLD( NV_CERR_HOLD2_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_7 ); +REG64_FLD( NV_CERR_HOLD2_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_8 ); +REG64_FLD( NV_CERR_HOLD2_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_9 ); +REG64_FLD( NV_CERR_HOLD2_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_10 ); +REG64_FLD( NV_CERR_HOLD2_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_11 ); +REG64_FLD( NV_CERR_HOLD2_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_12 ); +REG64_FLD( NV_CERR_HOLD2_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_13 ); +REG64_FLD( NV_CERR_HOLD2_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_14 ); +REG64_FLD( NV_CERR_HOLD2_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_15 ); +REG64_FLD( NV_CERR_HOLD2_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_16 ); +REG64_FLD( NV_CERR_HOLD2_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_17 ); +REG64_FLD( NV_CERR_HOLD2_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_18 ); +REG64_FLD( NV_CERR_HOLD2_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_19 ); +REG64_FLD( NV_CERR_HOLD2_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_20 ); +REG64_FLD( NV_CERR_HOLD2_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_21 ); +REG64_FLD( NV_CERR_HOLD2_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_22 ); +REG64_FLD( NV_CERR_HOLD2_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_23 ); +REG64_FLD( NV_CERR_HOLD2_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_24 ); +REG64_FLD( NV_CERR_HOLD2_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_25 ); +REG64_FLD( NV_CERR_HOLD2_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_26 ); +REG64_FLD( NV_CERR_HOLD2_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_27 ); +REG64_FLD( NV_CERR_HOLD2_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_28 ); +REG64_FLD( NV_CERR_HOLD2_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_29 ); +REG64_FLD( NV_CERR_HOLD2_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_30 ); +REG64_FLD( NV_CERR_HOLD2_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_31 ); +REG64_FLD( NV_CERR_HOLD2_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_32 ); +REG64_FLD( NV_CERR_HOLD2_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_33 ); +REG64_FLD( NV_CERR_HOLD2_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_34 ); +REG64_FLD( NV_CERR_HOLD2_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_35 ); +REG64_FLD( NV_CERR_HOLD2_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_36 ); +REG64_FLD( NV_CERR_HOLD2_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_37 ); +REG64_FLD( NV_CERR_HOLD2_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_38 ); +REG64_FLD( NV_CERR_HOLD2_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_39 ); +REG64_FLD( NV_CERR_HOLD2_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_40 ); +REG64_FLD( NV_CERR_HOLD2_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_41 ); +REG64_FLD( NV_CERR_HOLD2_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_42 ); +REG64_FLD( NV_CERR_HOLD2_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_43 ); +REG64_FLD( NV_CERR_HOLD2_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_44 ); +REG64_FLD( NV_CERR_HOLD2_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_45 ); +REG64_FLD( NV_CERR_HOLD2_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_46 ); +REG64_FLD( NV_CERR_HOLD2_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_47 ); +REG64_FLD( NV_CERR_HOLD2_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_48 ); +REG64_FLD( NV_CERR_HOLD2_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_49 ); +REG64_FLD( NV_CERR_HOLD2_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_50 ); +REG64_FLD( NV_CERR_HOLD2_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_51 ); +REG64_FLD( NV_CERR_HOLD2_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_52 ); +REG64_FLD( NV_CERR_HOLD2_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_53 ); +REG64_FLD( NV_CERR_HOLD2_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_54 ); +REG64_FLD( NV_CERR_HOLD2_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_55 ); +REG64_FLD( NV_CERR_HOLD2_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_56 ); +REG64_FLD( NV_CERR_HOLD2_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_57 ); +REG64_FLD( NV_CERR_HOLD2_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_58 ); +REG64_FLD( NV_CERR_HOLD2_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_59 ); +REG64_FLD( NV_CERR_HOLD2_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_60 ); +REG64_FLD( NV_CERR_HOLD2_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_61 ); +REG64_FLD( NV_CERR_HOLD2_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_62 ); +REG64_FLD( NV_CERR_HOLD2_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_63 ); + +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_8 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_9 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_10 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_11 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_12 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_13 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_14 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_15 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_16 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_17 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_18 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_19 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_20 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_21 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_22 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_23 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_24 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_25 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_26 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_27 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_28 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_29 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_30 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_31 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_32 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_33 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_34 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_35 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_36 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_37 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_38 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_39 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_40 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_41 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_42 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_43 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_44 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_45 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_46 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_47 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_48 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_49 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_50 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_51 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_52 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_53 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_54 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_55 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_56 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_57 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_58 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_59 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_60 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_61 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_62 ); +REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_63 ); + +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_8 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_9 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_10 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_11 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_12 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_13 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_14 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_15 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_16 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_17 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_18 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_19 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_20 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_21 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_22 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_23 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_24 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_25 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_26 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_27 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_28 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_29 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_30 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_31 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_32 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_33 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_34 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_35 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_36 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_37 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_38 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_39 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_40 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_41 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_42 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_43 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_44 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_45 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_46 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_47 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_48 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_49 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_50 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_51 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_52 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_53 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_54 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_55 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_56 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_57 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_58 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_59 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_60 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_61 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_62 ); +REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_HOLD_NLG_63 ); + +REG64_FLD( PU_NPU0_CERR_LOG_FIRST_BITS , 47 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS ); -REG64_FLD( PU_NPU0_CERR_LOG_FIRST_BITS_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CERR_LOG_FIRST_BITS_LEN , 17 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); -REG64_FLD( PU_NPU1_CERR_LOG_FIRST_BITS , 60 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CERR_LOG_FIRST_BITS , 47 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS ); -REG64_FLD( PU_NPU1_CERR_LOG_FIRST_BITS_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CERR_LOG_FIRST_BITS_LEN , 17 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); -REG64_FLD( PU_NPU2_CERR_LOG_FIRST_BITS , 60 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CERR_LOG_FIRST_BITS , 47 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS ); -REG64_FLD( PU_NPU2_CERR_LOG_FIRST_BITS_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CERR_LOG_FIRST_BITS_LEN , 17 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); +REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_BBUF_RDWR , 47 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IDIAL_BBUF_RDWR ); +REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_IBUF_RDWR , 48 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IDIAL_IBUF_RDWR ); +REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_OBUF_RDWR , 49 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IDIAL_OBUF_RDWR ); +REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_RQIN_OVF , 50 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IDIAL_RQIN_OVF ); +REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_RQIN_OVF_LEN , 6 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IDIAL_RQIN_OVF_LEN ); +REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_IBUF_CTL_PIPE , 56 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IDIAL_IBUF_CTL_PIPE ); +REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_PBTX_PIPE , 57 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IDIAL_PBTX_PIPE ); +REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_MRG_IR_PIPE , 58 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IDIAL_MRG_IR_PIPE ); +REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_MRG_OR_PIPE , 59 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IDIAL_MRG_OR_PIPE ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_AMO_ADDR , 60 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_AMO_ADDR ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_PBRX_RTAG , 61 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PBRX_RTAG ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_IBUF_WRITE , 62 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_WRITE ); -REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_RESERVED , 63 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_IDIAL_RESERVED ); - +REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_IBUF_WARB , 63 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IDIAL_IBUF_WARB ); + +REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_BBUF_RDWR , 47 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IDIAL_BBUF_RDWR ); +REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_IBUF_RDWR , 48 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IDIAL_IBUF_RDWR ); +REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_OBUF_RDWR , 49 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IDIAL_OBUF_RDWR ); +REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_RQIN_OVF , 50 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IDIAL_RQIN_OVF ); +REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_RQIN_OVF_LEN , 6 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IDIAL_RQIN_OVF_LEN ); +REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_IBUF_CTL_PIPE , 56 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IDIAL_IBUF_CTL_PIPE ); +REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_PBTX_PIPE , 57 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IDIAL_PBTX_PIPE ); +REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_MRG_IR_PIPE , 58 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IDIAL_MRG_IR_PIPE ); +REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_MRG_OR_PIPE , 59 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IDIAL_MRG_OR_PIPE ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_AMO_ADDR , 60 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_AMO_ADDR ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_PBRX_RTAG , 61 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PBRX_RTAG ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_IBUF_WRITE , 62 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_WRITE ); -REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_RESERVED , 63 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_IDIAL_RESERVED ); - +REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_IBUF_WARB , 63 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IDIAL_IBUF_WARB ); + +REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_BBUF_RDWR , 47 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IDIAL_BBUF_RDWR ); +REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_IBUF_RDWR , 48 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IDIAL_IBUF_RDWR ); +REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_OBUF_RDWR , 49 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IDIAL_OBUF_RDWR ); +REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_RQIN_OVF , 50 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IDIAL_RQIN_OVF ); +REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_RQIN_OVF_LEN , 6 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IDIAL_RQIN_OVF_LEN ); +REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_IBUF_CTL_PIPE , 56 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IDIAL_IBUF_CTL_PIPE ); +REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_PBTX_PIPE , 57 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IDIAL_PBTX_PIPE ); +REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_MRG_IR_PIPE , 58 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IDIAL_MRG_IR_PIPE ); +REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_MRG_OR_PIPE , 59 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IDIAL_MRG_OR_PIPE ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_AMO_ADDR , 60 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_AMO_ADDR ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_PBRX_RTAG , 61 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PBRX_RTAG ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_IBUF_WRITE , 62 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_WRITE ); -REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_RESERVED , 63 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_IDIAL_RESERVED ); +REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_IBUF_WARB , 63 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IDIAL_IBUF_WARB ); -REG64_FLD( PU_NPU0_CERR_LOG_MASK_BITS , 60 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CERR_LOG_MASK_BITS , 47 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS ); -REG64_FLD( PU_NPU0_CERR_LOG_MASK_BITS_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CERR_LOG_MASK_BITS_LEN , 17 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); -REG64_FLD( PU_NPU1_CERR_LOG_MASK_BITS , 60 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CERR_LOG_MASK_BITS , 47 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS ); -REG64_FLD( PU_NPU1_CERR_LOG_MASK_BITS_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CERR_LOG_MASK_BITS_LEN , 17 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); -REG64_FLD( PU_NPU2_CERR_LOG_MASK_BITS , 60 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CERR_LOG_MASK_BITS , 47 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS ); -REG64_FLD( PU_NPU2_CERR_LOG_MASK_BITS_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CERR_LOG_MASK_BITS_LEN , 17 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_0 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_1 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_2 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_3 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_4 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_5 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_6 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_7 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_8 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_8 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_9 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_9 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_10 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_10 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_11 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_11 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_0 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_1 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_2 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_3 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_4 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_5 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_6 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_7 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_24 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_25 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_26 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_27 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_28 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_29 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_30 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_31 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 57 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 58 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 59 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 60 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 61 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 62 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); - -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_0 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_1 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_2 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_3 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_4 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_5 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_6 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_7 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_8 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_8 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_9 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_9 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_10 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_10 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_11 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_11 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_0 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_1 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_2 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_3 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_4 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_5 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_6 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_7 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_7 ); + +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_24 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_25 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_26 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_27 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_28 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_29 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_30 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_31 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 57 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 58 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 59 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 60 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 61 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 62 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); - -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_0 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_1 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_2 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_3 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_4 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_5 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_6 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_7 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_8 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_8 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_9 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_9 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_10 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_10 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_11 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_11 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_0 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_1 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_2 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_3 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_4 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_5 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_6 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_7 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_7 ); + +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_24 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_25 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_26 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_27 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_28 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_29 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_30 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_31 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 57 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 58 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 59 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 60 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 61 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 62 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); - -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_0 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_1 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_2 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_3 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_4 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_5 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_6 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_7 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_8 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_8 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_9 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_9 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_10 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_10 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_11 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_11 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_0 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_1 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_2 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_3 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_4 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_5 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_6 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_7 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_7 ); + +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_24 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_25 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_26 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_27 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_28 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_29 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_30 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_31 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 57 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 58 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 59 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 60 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 61 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 62 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); - -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBP_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_0 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_1 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_2 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_3 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_4 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_5 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_6 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_7 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_8 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_8 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_9 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_9 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_10 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_10 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBF_11 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_11 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_0 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_1 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_2 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_3 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_4 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_5 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_6 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBC_7 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_7 ); + +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_24 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_25 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_26 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_27 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_28 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_29 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_30 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_31 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 57 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 58 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 59 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 60 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 61 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 62 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); - -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_0 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_1 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_2 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_3 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_4 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_5 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_6 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_7 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_8 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_8 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_9 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_9 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_10 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_10 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_11 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_11 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_0 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_1 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_2 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_3 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_4 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_5 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_6 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_7 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_7 ); + +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_24 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_25 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_26 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_27 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_28 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_29 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_30 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_31 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 57 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 58 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 59 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 60 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 61 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 62 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); - -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_0 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_1 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_2 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_3 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_4 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_5 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_6 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_7 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_8 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_8 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_9 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_9 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_10 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_10 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_11 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_11 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_0 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_1 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_2 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_3 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_4 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_5 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_6 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_7 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_7 ); + +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_24 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_25 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_26 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_27 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_28 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_29 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_30 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_31 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 57 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 58 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 59 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 60 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 61 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 62 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_7 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_0 ); @@ -11804,401 +14127,329 @@ REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_2 , 58 , SH_UN SH_FLD_IDIAL_CTL_MASK_DUE_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_3 , 59 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_3 ); -REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV4_0 , 60 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_MASK_RSV4_0 ); -REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV4_1 , 61 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_MASK_RSV4_1 ); -REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV4_2 , 62 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_MASK_RSV4_2 ); -REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV4_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_MASK_RSV4_3 ); - -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_0 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_1 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_2 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_3 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_4 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_5 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_6 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_7 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_8 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_8 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_9 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_9 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_10 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_10 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_11 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_11 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_0 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_1 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_2 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_3 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_4 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_5 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_6 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_7 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_0 , 60 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_MASK_PEF_0 ); +REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_1 , 61 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_MASK_PEF_1 ); +REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_2 , 62 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_MASK_PEF_2 ); +REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_MASK_PEF_3 ); + +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_24 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_25 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_26 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_27 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_28 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_29 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_30 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_31 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 57 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 58 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 59 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 60 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 61 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 62 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); - -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBP_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_0 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_1 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_2 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_3 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_4 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_5 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_6 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_7 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_8 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_8 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_9 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_9 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_10 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_10 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBF_11 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_11 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_0 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_1 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_2 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_3 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_4 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_5 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_6 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBC_7 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_7 ); + +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_24 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_25 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_26 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_27 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_28 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_29 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_30 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_31 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 57 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 58 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 59 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 60 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 61 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 62 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); - -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_0 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_1 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_2 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_3 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_4 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_5 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_6 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_7 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_8 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_8 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_9 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_9 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_10 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_10 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_11 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_11 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_0 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_1 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_2 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_3 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_4 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_5 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_6 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_7 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_7 ); + +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_24 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_25 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_26 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_27 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_28 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_29 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_30 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_31 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 57 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 58 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 59 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 60 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 61 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 62 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_7 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_0 ); @@ -12320,14 +14571,14 @@ REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_2 , 58 , SH_UN SH_FLD_IDIAL_CTL_MASK_DUE_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_3 , 59 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_3 ); -REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV4_0 , 60 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_MASK_RSV4_0 ); -REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV4_1 , 61 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_MASK_RSV4_1 ); -REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV4_2 , 62 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_MASK_RSV4_2 ); -REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV4_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_MASK_RSV4_3 ); +REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_0 , 60 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_MASK_PEF_0 ); +REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_1 , 61 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_MASK_PEF_1 ); +REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_2 , 62 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_MASK_PEF_2 ); +REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_MASK_PEF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_0 ); @@ -12449,530 +14700,450 @@ REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_2 , 58 , SH_UN SH_FLD_IDIAL_CTL_MASK_DUE_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_3 , 59 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_3 ); -REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV4_0 , 60 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_MASK_RSV4_0 ); -REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV4_1 , 61 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_MASK_RSV4_1 ); -REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV4_2 , 62 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_MASK_RSV4_2 ); -REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV4_3 , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_CTL_MASK_RSV4_3 ); - -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBP_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_0 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_1 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_2 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_3 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_4 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_5 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_6 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_7 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_8 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_8 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_9 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_9 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_10 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_10 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBF_11 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_11 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_0 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_1 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_2 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_3 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_4 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_5 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_6 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBC_7 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_0 , 60 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_MASK_PEF_0 ); +REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_1 , 61 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_MASK_PEF_1 ); +REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_2 , 62 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_MASK_PEF_2 ); +REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_3 , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CTL_MASK_PEF_3 ); + +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_24 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_25 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_26 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_27 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_28 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_29 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_30 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_31 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 57 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 58 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 59 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 60 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 61 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 62 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); - -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBP_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBP_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_0 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_1 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_2 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_3 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_4 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_5 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_6 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_7 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_8 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_8 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_9 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_9 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_10 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_10 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBF_11 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBF_11 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_0 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_1 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_2 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_3 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_4 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_5 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_6 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBC_7 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_PBC_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NCF_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_7 ); + +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_24 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_25 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_26 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_27 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_28 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_29 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_30 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NVF_31 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NCF_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 57 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 58 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 59 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 60 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 61 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 62 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); - -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_4 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_5 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_6 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_7 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_8 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_9 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_10 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_11 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_12 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_13 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_14 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_15 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_16 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_17 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_18 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_19 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_20 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_21 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_22 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_23 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_24 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_25 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_26 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_27 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_28 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_29 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_30 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_31 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_32 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_33 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_34 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_35 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_36 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_37 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_38 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_39 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_40 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_41 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_42 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_43 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_44 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_45 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_46 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_47 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_48 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_49 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_50 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_51 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_52 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_53 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_54 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_55 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBR_7 ); + +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_8 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_9 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_10 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_11 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_12 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_13 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_14 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_15 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 57 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 58 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 59 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 60 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 61 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 62 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); -REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); - -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_4 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_5 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_6 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_7 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_8 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_9 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_10 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_11 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_12 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_13 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_14 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_15 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_16 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_17 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_18 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_19 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_20 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_21 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_22 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_23 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_24 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_25 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_26 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_27 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_28 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_29 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_30 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_31 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_32 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_33 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_34 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_35 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_36 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_37 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_38 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_39 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_40 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_41 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_42 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_43 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_44 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_45 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_46 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_47 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_48 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_49 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_50 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_51 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_52 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_53 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_54 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_55 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_8 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_9 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_10 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_11 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_8 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_9 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_10 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_11 ); + +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_8 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_9 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_10 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_11 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_12 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_13 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_14 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_15 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 57 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 58 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 59 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 60 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 61 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 62 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); -REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_8 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_9 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_10 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_11 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_8 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_9 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_10 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_0 ); @@ -13103,263 +15274,231 @@ REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_62 , 62 , SH_UN REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_4 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_5 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_6 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_7 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_8 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_9 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_10 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_11 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_12 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_13 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_14 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_15 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_16 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_17 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_18 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_19 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_20 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_21 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_22 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_23 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_24 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_25 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_26 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_27 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_28 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_29 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_30 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_31 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_32 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_33 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_34 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_35 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_36 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_37 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_38 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_39 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_40 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_41 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_42 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_43 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_44 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_45 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_46 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_47 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_48 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_49 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_50 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_51 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_52 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_53 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_54 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_55 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_8 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_9 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_10 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_11 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_12 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_13 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_14 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_15 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 57 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 58 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 59 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 60 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 61 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 62 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); -REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); - -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_4 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_5 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_6 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_7 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_8 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_9 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_10 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_11 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_12 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_13 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_14 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_15 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_16 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_17 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_18 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_19 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_20 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_21 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_22 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_23 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_24 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_25 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_26 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_27 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_28 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_29 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_30 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_31 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_32 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_33 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_34 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_35 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_36 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_37 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_38 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_39 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_40 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_41 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_42 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_43 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_44 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_45 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_46 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_47 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_48 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_49 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_50 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_51 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_52 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_53 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_54 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_55 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_8 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_9 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_10 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_11 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_8 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_9 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_10 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_11 ); + +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_8 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_9 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_10 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_11 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_12 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_13 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_14 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_15 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 57 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 58 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 59 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 60 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 61 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 62 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); -REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_8 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_9 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_10 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_11 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_8 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_9 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_10 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_0 ); @@ -13490,263 +15629,231 @@ REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_2 , 62 , SH_UN REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV3_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_4 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_5 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_6 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_7 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_8 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_9 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_10 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_11 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_12 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_13 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_14 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_15 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_16 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_17 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_18 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_19 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_20 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_21 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_22 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_23 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_24 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_25 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_26 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_27 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_28 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_29 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_30 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_31 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_32 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_33 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_34 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_35 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_36 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_37 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_38 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_39 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_40 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_41 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_42 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_43 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_44 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_45 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_46 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_47 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_48 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_49 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_50 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_51 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_52 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_53 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_54 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_55 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_8 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_9 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_10 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_11 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_12 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_13 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_14 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_15 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 57 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 58 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 59 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 60 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 61 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 62 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); -REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); - -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_4 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_5 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_6 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_7 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_8 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_9 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_10 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_11 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_12 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_13 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_14 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_15 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_16 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_17 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_18 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_19 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_20 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_21 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_22 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_23 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_24 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_25 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_26 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_27 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_28 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_29 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_30 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_31 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_32 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_33 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_34 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_35 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_36 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_37 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_38 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_39 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_40 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_41 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_42 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_43 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_44 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_45 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_46 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_47 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_48 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_49 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_50 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_51 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_52 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_53 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_54 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_55 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_8 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_9 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_10 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_11 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_8 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_9 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_10 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_11 ); + +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_8 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_9 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_10 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_11 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_12 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_13 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_14 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_15 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 57 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 58 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 59 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 60 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 61 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 62 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); -REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_8 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_9 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_10 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_11 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_0 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_1 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_2 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_4 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_5 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_6 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_7 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_8 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_9 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_10 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_0 ); @@ -13877,392 +15984,344 @@ REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_62 , 62 , SH_UN REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_4 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_5 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_6 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_7 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_8 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_9 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_10 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_11 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_12 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_13 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_14 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_15 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_16 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_17 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_18 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_19 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_20 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_21 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_22 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_23 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_24 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_25 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_26 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_27 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_28 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_29 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_30 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_31 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_32 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_33 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_34 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_35 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_36 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_37 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_38 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_39 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_40 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_41 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_42 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_43 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_44 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_45 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_46 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_47 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_48 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_49 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_50 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_51 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_52 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_53 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_54 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_55 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_8 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_9 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_10 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_11 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_12 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_13 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_14 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_15 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 57 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 58 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 59 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 60 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 61 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 62 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); -REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); - -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_4 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_5 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_6 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_7 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_8 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_9 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_10 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_11 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_12 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_13 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_14 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_15 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_16 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_17 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_18 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_19 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_20 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_21 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_22 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_23 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_24 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_25 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_26 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_27 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_28 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_29 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_30 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_31 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_32 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_33 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_34 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_35 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_36 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_37 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_38 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_39 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_40 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_41 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_42 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_43 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_44 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_45 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_46 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_47 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_48 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_49 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_50 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_51 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_52 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_53 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_54 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_55 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_8 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_9 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_10 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_11 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_8 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_9 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_10 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_11 ); + +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_8 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_9 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_10 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_11 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_12 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_13 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_14 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_15 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 57 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 58 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 59 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 60 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 61 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 62 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); -REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); - -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_4 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_5 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_6 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_7 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_8 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_9 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_10 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_11 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_12 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_13 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_14 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_15 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_16 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_17 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_18 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_19 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_20 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_21 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_22 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_23 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_24 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_25 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_26 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_27 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_28 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_29 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_30 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_31 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_32 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_33 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_34 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_35 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_36 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_37 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_38 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_39 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_40 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_41 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_42 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_43 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_44 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_45 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_46 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_47 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_48 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_49 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_50 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_51 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_52 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_53 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_54 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_55 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_8 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_9 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_10 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_11 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_8 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_9 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_10 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_11 ); + +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_8 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_9 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_10 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_11 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_12 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_13 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_14 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_15 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 57 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 58 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 59 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 60 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 61 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 62 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); -REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_8 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_9 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_10 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_11 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_8 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_9 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_10 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_0 ); @@ -14393,263 +16452,231 @@ REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_2 , 62 , SH_UN REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV3_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_4 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_5 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_6 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_7 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_8 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_9 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_10 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_11 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_12 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_13 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_14 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_15 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_16 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_17 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_18 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_19 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_20 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_21 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_22 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_23 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_24 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_25 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_26 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_27 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_28 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_29 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_30 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_31 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_32 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_33 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_34 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_35 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_36 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_37 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_38 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_39 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_40 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_41 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_42 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_43 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_44 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_45 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_46 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_47 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_48 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_49 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_50 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_51 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_52 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_53 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_54 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_55 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_8 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_9 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_10 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_11 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_12 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_13 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_14 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_15 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 57 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 58 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 59 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 60 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 61 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 62 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); -REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); - -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_4 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_5 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_6 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_7 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_8 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_9 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_10 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_11 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_12 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_13 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_14 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_15 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_16 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_17 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_18 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_19 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_20 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_21 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_22 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_23 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_24 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_25 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_26 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_27 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_28 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_29 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_30 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_31 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_32 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_33 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_34 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_35 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_36 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_37 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_38 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_39 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_40 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_41 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_42 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_43 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_44 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_45 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_46 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_47 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_48 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_49 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_50 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_51 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_52 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_53 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_54 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_NLG_55 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_8 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_9 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_10 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_11 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_8 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_9 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_10 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_11 ); + +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_8 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_9 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_10 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_11 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_12 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_13 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_14 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_15 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 57 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 58 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 59 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 60 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 61 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 62 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); -REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_8 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_9 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_10 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_11 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_8 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_9 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_10 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_0 ); @@ -14909,134 +16936,247 @@ REG64_FLD( NV_CERR_MASK1_NTL_62 , 62 , SH_UN REG64_FLD( NV_CERR_MASK1_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_8 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_9 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_10 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_11 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_12 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_13 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_14 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLGX_15 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_FWD_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_FWD_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_FWD_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_FWD_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_AUE_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_AUE_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_AUE_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_AUE_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBP_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_8 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_9 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_10 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBF_11 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_8 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_9 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_10 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_PBC_11 ); + +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_4 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_5 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_6 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_7 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_8 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_9 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_10 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_11 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_12 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_13 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_14 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_15 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_16 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_17 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_18 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_19 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_20 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_21 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_22 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_23 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_24 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_25 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_26 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_27 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_28 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_29 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_30 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_31 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_32 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_33 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_34 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_35 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_36 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_37 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_38 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_39 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_40 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_41 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_42 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_43 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_44 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_45 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_46 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_47 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_48 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_49 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_50 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_51 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_52 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_53 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_54 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_55 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_FWD_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 57 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_FWD_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 58 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_FWD_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 59 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_FWD_3 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 60 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_AUE_0 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 61 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_AUE_1 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 62 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_AUE_2 ); -REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_SM_MASK_AUE_3 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_56 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_57 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_58 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_59 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_60 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_61 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_62 ); +REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_63 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_0 ); @@ -15167,134 +17307,521 @@ REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_62 , 62 , SH_UN REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( NV_CERR_MASK2_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_0 ); -REG64_FLD( NV_CERR_MASK2_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_1 ); -REG64_FLD( NV_CERR_MASK2_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_2 ); -REG64_FLD( NV_CERR_MASK2_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_3 ); -REG64_FLD( NV_CERR_MASK2_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_4 ); -REG64_FLD( NV_CERR_MASK2_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_5 ); -REG64_FLD( NV_CERR_MASK2_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_6 ); -REG64_FLD( NV_CERR_MASK2_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_7 ); -REG64_FLD( NV_CERR_MASK2_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_8 ); -REG64_FLD( NV_CERR_MASK2_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_9 ); -REG64_FLD( NV_CERR_MASK2_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_10 ); -REG64_FLD( NV_CERR_MASK2_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_11 ); -REG64_FLD( NV_CERR_MASK2_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_12 ); -REG64_FLD( NV_CERR_MASK2_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_13 ); -REG64_FLD( NV_CERR_MASK2_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_14 ); -REG64_FLD( NV_CERR_MASK2_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_15 ); -REG64_FLD( NV_CERR_MASK2_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_16 ); -REG64_FLD( NV_CERR_MASK2_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_17 ); -REG64_FLD( NV_CERR_MASK2_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_18 ); -REG64_FLD( NV_CERR_MASK2_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_19 ); -REG64_FLD( NV_CERR_MASK2_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_20 ); -REG64_FLD( NV_CERR_MASK2_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_21 ); -REG64_FLD( NV_CERR_MASK2_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_22 ); -REG64_FLD( NV_CERR_MASK2_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_23 ); -REG64_FLD( NV_CERR_MASK2_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_24 ); -REG64_FLD( NV_CERR_MASK2_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_25 ); -REG64_FLD( NV_CERR_MASK2_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_26 ); -REG64_FLD( NV_CERR_MASK2_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_27 ); -REG64_FLD( NV_CERR_MASK2_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_28 ); -REG64_FLD( NV_CERR_MASK2_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_29 ); -REG64_FLD( NV_CERR_MASK2_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_30 ); -REG64_FLD( NV_CERR_MASK2_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_31 ); -REG64_FLD( NV_CERR_MASK2_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_32 ); -REG64_FLD( NV_CERR_MASK2_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_33 ); -REG64_FLD( NV_CERR_MASK2_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_34 ); -REG64_FLD( NV_CERR_MASK2_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_35 ); -REG64_FLD( NV_CERR_MASK2_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_36 ); -REG64_FLD( NV_CERR_MASK2_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_37 ); -REG64_FLD( NV_CERR_MASK2_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_38 ); -REG64_FLD( NV_CERR_MASK2_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_39 ); -REG64_FLD( NV_CERR_MASK2_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_40 ); -REG64_FLD( NV_CERR_MASK2_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_41 ); -REG64_FLD( NV_CERR_MASK2_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_42 ); -REG64_FLD( NV_CERR_MASK2_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_43 ); -REG64_FLD( NV_CERR_MASK2_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_44 ); -REG64_FLD( NV_CERR_MASK2_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_45 ); -REG64_FLD( NV_CERR_MASK2_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_46 ); -REG64_FLD( NV_CERR_MASK2_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_47 ); -REG64_FLD( NV_CERR_MASK2_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_48 ); -REG64_FLD( NV_CERR_MASK2_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_49 ); -REG64_FLD( NV_CERR_MASK2_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_50 ); -REG64_FLD( NV_CERR_MASK2_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_51 ); -REG64_FLD( NV_CERR_MASK2_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_52 ); -REG64_FLD( NV_CERR_MASK2_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_53 ); -REG64_FLD( NV_CERR_MASK2_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_54 ); -REG64_FLD( NV_CERR_MASK2_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_55 ); -REG64_FLD( NV_CERR_MASK2_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_56 ); -REG64_FLD( NV_CERR_MASK2_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_57 ); -REG64_FLD( NV_CERR_MASK2_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_58 ); -REG64_FLD( NV_CERR_MASK2_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_59 ); -REG64_FLD( NV_CERR_MASK2_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_60 ); -REG64_FLD( NV_CERR_MASK2_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_61 ); -REG64_FLD( NV_CERR_MASK2_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_62 ); -REG64_FLD( NV_CERR_MASK2_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_NTL_63 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_0 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_1 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_2 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_3 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_4 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_5 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_6 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_7 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_8 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_9 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_10 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_11 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_12 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_13 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_14 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_15 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_16 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_17 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_18 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_19 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_20 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_21 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_22 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_23 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_24 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_25 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_26 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_27 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_28 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_29 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_30 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_31 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_32 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_33 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_34 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_35 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_36 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_37 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_38 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_39 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_40 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_41 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_42 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_43 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_44 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_45 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_46 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_47 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_48 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_49 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_50 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_51 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_52 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_53 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_54 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_55 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_56 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_57 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_58 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_59 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_60 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_61 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_62 ); +REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_63 ); + +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_0 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_1 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_2 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_3 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_4 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_5 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_6 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_7 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_8 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_9 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_10 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_11 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_12 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_13 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_14 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_15 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_16 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_17 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_18 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_19 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_20 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_21 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_22 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_23 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_24 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_25 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_26 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_27 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_28 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_29 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_30 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_31 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_32 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_33 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_34 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_35 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_36 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_37 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_38 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_39 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_40 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_41 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_42 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_43 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_44 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_45 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_46 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_47 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_48 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_49 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_50 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_51 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_52 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_53 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_54 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_55 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_56 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_57 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_58 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_59 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_60 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_61 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_62 ); +REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_63 ); + +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_0 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_1 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_2 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_3 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_4 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_5 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_6 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_7 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_8 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_9 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_10 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_11 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_12 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_13 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_14 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_15 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_16 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_17 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_18 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_19 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_20 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_21 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_22 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_23 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_24 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_25 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_26 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_27 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_28 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_29 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_30 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_31 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_32 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_33 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_34 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_35 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_36 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_37 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_38 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_39 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_40 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_41 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_42 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_43 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_44 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_45 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_46 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_47 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_48 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_49 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_50 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_51 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_52 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_53 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_54 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_55 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_56 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_57 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_58 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_59 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_60 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_61 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_62 ); +REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_63 ); + +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_0 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_1 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_2 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_3 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_4 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_5 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_6 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_7 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_8 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_9 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_10 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_11 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_12 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_13 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_14 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_15 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_16 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_17 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_18 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_19 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_20 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_21 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_22 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_23 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_24 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_25 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_26 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_27 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_28 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_29 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_30 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_31 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_32 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_33 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_34 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_35 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_36 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_37 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_38 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_39 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_40 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_41 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_42 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_43 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_44 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_45 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_46 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_47 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_48 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_49 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_50 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_51 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_52 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_53 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_54 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_55 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_56 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_57 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_58 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_59 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_60 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_61 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_62 ); +REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_63 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_0 ); @@ -15425,21 +17952,1385 @@ REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_62 , 62 , SH_UN REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_63 ); -REG64_FLD( PU_NPU0_CERR_PTY_FIRST_BITS , 38 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_0 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_1 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_2 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_3 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_4 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_5 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_6 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_7 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_8 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_9 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_10 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_11 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_12 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_13 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_14 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_15 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_16 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_17 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_18 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_19 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_20 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_21 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_22 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_23 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_24 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_25 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_26 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_27 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_28 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_29 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_30 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_31 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_32 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_33 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_34 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_35 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_36 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_37 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_38 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_39 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_40 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_41 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_42 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_43 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_44 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_45 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_46 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_47 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_48 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_49 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_50 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_51 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_52 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_53 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_54 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_55 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_56 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_57 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_58 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_59 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_60 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_61 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_62 ); +REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_63 ); + +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_0 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_1 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_2 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_3 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_4 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_5 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_6 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_7 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_8 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_9 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_10 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_11 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_12 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_13 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_14 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_15 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_16 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_17 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_18 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_19 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_20 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_21 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_22 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_23 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_24 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_25 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_26 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_27 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_28 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_29 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_30 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_31 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_32 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_33 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_34 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_35 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_36 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_37 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_38 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_39 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_40 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_41 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_42 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_43 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_44 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_45 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_46 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_47 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_48 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_49 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_50 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_51 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_52 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_53 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_54 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_55 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_56 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_57 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_58 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_59 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_60 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_61 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_62 ); +REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_63 ); + +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_0 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_1 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_2 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_3 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_4 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_5 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_6 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_7 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_8 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_9 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_10 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_11 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_12 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_13 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_14 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_15 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_16 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_17 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_18 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_19 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_20 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_21 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_22 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_23 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_24 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_25 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_26 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_27 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_28 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_29 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_30 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_31 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_32 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_33 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_34 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_35 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_36 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_37 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_38 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_39 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_40 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_41 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_42 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_43 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_44 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_45 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_46 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_47 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_48 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_49 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_50 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_51 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_52 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_53 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_54 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_55 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_56 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_57 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_58 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_59 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_60 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_61 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_62 ); +REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_63 ); + +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_0 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_1 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_2 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_3 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_4 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_5 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_6 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_7 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_8 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_9 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_10 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_11 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_12 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_13 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_14 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_15 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_16 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_17 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_18 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_19 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_20 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_21 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_22 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_23 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_24 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_25 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_26 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_27 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_28 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_29 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_30 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_31 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_32 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_33 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_34 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_35 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_36 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_37 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_38 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_39 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_40 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_41 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_42 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_43 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_44 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_45 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_46 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_47 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_48 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_49 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_50 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_51 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_52 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_53 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_54 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_55 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_56 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_57 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_58 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_59 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_60 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_61 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_62 ); +REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_63 ); + +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_0 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_1 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_2 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_3 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_4 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_5 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_6 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_7 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_8 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_9 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_10 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_11 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_12 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_13 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_14 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_15 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_16 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_17 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_18 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_19 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_20 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_21 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_22 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_23 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_24 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_25 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_26 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_27 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_28 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_29 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_30 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_31 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_32 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_33 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_34 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_35 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_36 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_37 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_38 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_39 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_40 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_41 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_42 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_43 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_44 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_45 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_46 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_47 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_48 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_49 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_50 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_51 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_52 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_53 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_54 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_55 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_56 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_57 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_58 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_59 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_60 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_61 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_62 ); +REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_63 ); + +REG64_FLD( NV_CERR_MASK2_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_0 ); +REG64_FLD( NV_CERR_MASK2_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_1 ); +REG64_FLD( NV_CERR_MASK2_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_2 ); +REG64_FLD( NV_CERR_MASK2_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_3 ); +REG64_FLD( NV_CERR_MASK2_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_4 ); +REG64_FLD( NV_CERR_MASK2_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_5 ); +REG64_FLD( NV_CERR_MASK2_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_6 ); +REG64_FLD( NV_CERR_MASK2_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_7 ); +REG64_FLD( NV_CERR_MASK2_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_8 ); +REG64_FLD( NV_CERR_MASK2_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_9 ); +REG64_FLD( NV_CERR_MASK2_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_10 ); +REG64_FLD( NV_CERR_MASK2_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_11 ); +REG64_FLD( NV_CERR_MASK2_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_12 ); +REG64_FLD( NV_CERR_MASK2_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_13 ); +REG64_FLD( NV_CERR_MASK2_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_14 ); +REG64_FLD( NV_CERR_MASK2_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_15 ); +REG64_FLD( NV_CERR_MASK2_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_16 ); +REG64_FLD( NV_CERR_MASK2_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_17 ); +REG64_FLD( NV_CERR_MASK2_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_18 ); +REG64_FLD( NV_CERR_MASK2_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_19 ); +REG64_FLD( NV_CERR_MASK2_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_20 ); +REG64_FLD( NV_CERR_MASK2_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_21 ); +REG64_FLD( NV_CERR_MASK2_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_22 ); +REG64_FLD( NV_CERR_MASK2_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_23 ); +REG64_FLD( NV_CERR_MASK2_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_24 ); +REG64_FLD( NV_CERR_MASK2_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_25 ); +REG64_FLD( NV_CERR_MASK2_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_26 ); +REG64_FLD( NV_CERR_MASK2_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_27 ); +REG64_FLD( NV_CERR_MASK2_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_28 ); +REG64_FLD( NV_CERR_MASK2_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_29 ); +REG64_FLD( NV_CERR_MASK2_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_30 ); +REG64_FLD( NV_CERR_MASK2_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_31 ); +REG64_FLD( NV_CERR_MASK2_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_32 ); +REG64_FLD( NV_CERR_MASK2_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_33 ); +REG64_FLD( NV_CERR_MASK2_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_34 ); +REG64_FLD( NV_CERR_MASK2_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_35 ); +REG64_FLD( NV_CERR_MASK2_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_36 ); +REG64_FLD( NV_CERR_MASK2_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_37 ); +REG64_FLD( NV_CERR_MASK2_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_38 ); +REG64_FLD( NV_CERR_MASK2_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_39 ); +REG64_FLD( NV_CERR_MASK2_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_40 ); +REG64_FLD( NV_CERR_MASK2_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_41 ); +REG64_FLD( NV_CERR_MASK2_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_42 ); +REG64_FLD( NV_CERR_MASK2_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_43 ); +REG64_FLD( NV_CERR_MASK2_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_44 ); +REG64_FLD( NV_CERR_MASK2_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_45 ); +REG64_FLD( NV_CERR_MASK2_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_46 ); +REG64_FLD( NV_CERR_MASK2_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_47 ); +REG64_FLD( NV_CERR_MASK2_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_48 ); +REG64_FLD( NV_CERR_MASK2_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_49 ); +REG64_FLD( NV_CERR_MASK2_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_50 ); +REG64_FLD( NV_CERR_MASK2_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_51 ); +REG64_FLD( NV_CERR_MASK2_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_52 ); +REG64_FLD( NV_CERR_MASK2_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_53 ); +REG64_FLD( NV_CERR_MASK2_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_54 ); +REG64_FLD( NV_CERR_MASK2_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_55 ); +REG64_FLD( NV_CERR_MASK2_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_56 ); +REG64_FLD( NV_CERR_MASK2_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_57 ); +REG64_FLD( NV_CERR_MASK2_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_58 ); +REG64_FLD( NV_CERR_MASK2_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_59 ); +REG64_FLD( NV_CERR_MASK2_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_60 ); +REG64_FLD( NV_CERR_MASK2_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_61 ); +REG64_FLD( NV_CERR_MASK2_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_62 ); +REG64_FLD( NV_CERR_MASK2_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_63 ); + +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_0 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_1 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_2 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_3 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_4 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_5 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_6 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_7 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_8 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_9 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_10 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_11 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_12 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_13 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_14 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_15 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_16 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_17 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_18 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_19 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_20 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_21 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_22 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_23 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_24 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_25 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_26 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_27 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_28 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_29 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_30 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_31 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_32 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_33 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_34 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_35 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_36 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_37 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_38 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_39 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_40 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_41 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_42 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_43 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_44 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_45 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_46 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_47 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_48 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_49 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_50 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_51 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_52 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_53 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_54 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_55 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_56 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_57 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_58 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_59 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_60 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_61 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_62 ); +REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_63 ); + +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_0 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_1 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_2 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_3 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_4 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_5 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_6 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_7 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_8 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_9 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_10 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_11 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_12 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_13 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_14 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_15 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_16 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_17 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_18 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_19 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_20 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_21 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_22 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_23 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_24 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_25 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_26 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_27 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_28 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_29 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_30 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_31 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_32 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_33 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_34 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_35 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_36 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_37 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_38 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_39 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_40 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_41 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_42 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_43 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_44 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_45 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_46 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_47 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_48 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_49 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_50 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_51 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_52 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_53 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_54 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_55 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_56 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_57 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_58 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_59 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_60 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_61 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_62 ); +REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_IDIAL_SM_MASK_NLG_63 ); + +REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU1_CTL_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU1_CTL_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU0_CTL_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU0_CTL_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU2_CTL_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU2_CTL_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0 ); +REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS0_LEN ); + +REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU1_CTL_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU1_CTL_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU0_CTL_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU0_CTL_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU2_CTL_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU2_CTL_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1 ); +REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS1_LEN ); + +REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2 ); +REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2_LEN ); + +REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2 ); +REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2_LEN ); + +REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2 ); +REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2_LEN ); + +REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2 ); +REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2_LEN ); + +REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2 ); +REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2_LEN ); + +REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2 ); +REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2_LEN ); + +REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2 ); +REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2_LEN ); + +REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2 ); +REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2_LEN ); + +REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2 ); +REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2_LEN ); + +REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2 ); +REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2_LEN ); + +REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2 ); +REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2_LEN ); + +REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2 ); +REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS2_LEN ); + +REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3 ); +REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3_LEN ); + +REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3 ); +REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3_LEN ); + +REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3 ); +REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3_LEN ); + +REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3 ); +REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3_LEN ); + +REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3 ); +REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3_LEN ); + +REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3 ); +REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3_LEN ); + +REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3 ); +REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3_LEN ); + +REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3 ); +REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3_LEN ); + +REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3 ); +REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3_LEN ); + +REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3 ); +REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3_LEN ); + +REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3 ); +REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3_LEN ); + +REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3 ); +REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS3_LEN ); + +REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4 ); +REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4_LEN ); + +REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4 ); +REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4_LEN ); + +REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4 ); +REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4_LEN ); + +REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4 ); +REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4_LEN ); + +REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4 ); +REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4_LEN ); + +REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4 ); +REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4_LEN ); + +REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4 ); +REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4_LEN ); + +REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4 ); +REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4_LEN ); + +REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4 ); +REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4_LEN ); + +REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4 ); +REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4_LEN ); + +REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4 ); +REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4_LEN ); + +REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4 ); +REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MESSAGE_BITS4_LEN ); + +REG64_FLD( PU_NPU0_CERR_PTY_FIRST_BITS , 37 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS ); -REG64_FLD( PU_NPU0_CERR_PTY_FIRST_BITS_LEN , 26 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CERR_PTY_FIRST_BITS_LEN , 27 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); -REG64_FLD( PU_NPU1_CERR_PTY_FIRST_BITS , 38 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CERR_PTY_FIRST_BITS , 37 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS ); -REG64_FLD( PU_NPU1_CERR_PTY_FIRST_BITS_LEN , 26 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CERR_PTY_FIRST_BITS_LEN , 27 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); -REG64_FLD( PU_NPU2_CERR_PTY_FIRST_BITS , 38 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CERR_PTY_FIRST_BITS , 37 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS ); -REG64_FLD( PU_NPU2_CERR_PTY_FIRST_BITS_LEN , 26 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CERR_PTY_FIRST_BITS_LEN , 27 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); +REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_INHIBIT_CONFIG , 37 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IDIAL_INHIBIT_CONFIG ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_MISC_STATE , 38 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_MISC_STATE ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_MRG_STATE , 39 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , @@ -15481,6 +19372,8 @@ REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_DEBUG0_CONFIG , 62 , SH_UN REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_DEBUG1_CONFIG , 63 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_DEBUG1_CONFIG ); +REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_INHIBIT_CONFIG , 37 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IDIAL_INHIBIT_CONFIG ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_MISC_STATE , 38 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_MISC_STATE ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_MRG_STATE , 39 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , @@ -15522,6 +19415,8 @@ REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_DEBUG0_CONFIG , 62 , SH_UN REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_DEBUG1_CONFIG , 63 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_DEBUG1_CONFIG ); +REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_INHIBIT_CONFIG , 37 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IDIAL_INHIBIT_CONFIG ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_MISC_STATE , 38 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_MISC_STATE ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_MRG_STATE , 39 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , @@ -15563,21 +19458,129 @@ REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_DEBUG0_CONFIG , 62 , SH_UN REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_DEBUG1_CONFIG , 63 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_DEBUG1_CONFIG ); -REG64_FLD( PU_NPU0_CERR_PTY_MASK_BITS , 38 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CERR_PTY_MASK_BITS , 37 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS ); -REG64_FLD( PU_NPU0_CERR_PTY_MASK_BITS_LEN , 26 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CERR_PTY_MASK_BITS_LEN , 27 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); -REG64_FLD( PU_NPU1_CERR_PTY_MASK_BITS , 38 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CERR_PTY_MASK_BITS , 37 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS ); -REG64_FLD( PU_NPU1_CERR_PTY_MASK_BITS_LEN , 26 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CERR_PTY_MASK_BITS_LEN , 27 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); -REG64_FLD( PU_NPU2_CERR_PTY_MASK_BITS , 38 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CERR_PTY_MASK_BITS , 37 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS ); -REG64_FLD( PU_NPU2_CERR_PTY_MASK_BITS_LEN , 26 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CERR_PTY_MASK_BITS_LEN , 27 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); +REG64_FLD( PEC_CLK_REGION_CLOCK_CMD , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_CMD ); +REG64_FLD( PEC_CLK_REGION_CLOCK_CMD_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_CMD_LEN ); +REG64_FLD( PEC_CLK_REGION_SLAVE_MODE , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SLAVE_MODE ); +REG64_FLD( PEC_CLK_REGION_MASTER_MODE , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASTER_MODE ); +REG64_FLD( PEC_CLK_REGION_CLOCK_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_PERV ); +REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_UNIT1 ); +REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_UNIT2 ); +REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_UNIT3 ); +REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_UNIT4 ); +REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_UNIT5 ); +REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_UNIT6 ); +REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_UNIT7 ); +REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_UNIT8 ); +REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_UNIT9 ); +REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_UNIT10 ); +REG64_FLD( PEC_CLK_REGION_SEL_THOLD_SL , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEL_THOLD_SL ); +REG64_FLD( PEC_CLK_REGION_SEL_THOLD_NSL , 49 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEL_THOLD_NSL ); +REG64_FLD( PEC_CLK_REGION_SEL_THOLD_ARY , 50 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEL_THOLD_ARY ); +REG64_FLD( PEC_CLK_REGION_CLOCK_PULSE_USE_EVEN , 52 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLOCK_PULSE_USE_EVEN ); + +REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_PERV ); +REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT1 ); +REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT2 ); +REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT3 ); +REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT4 ); +REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT5 ); +REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT6 ); +REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT7 ); +REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT8 ); +REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT9 ); +REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT10 ); + +REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_PERV ); +REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT1 ); +REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT2 ); +REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT3 ); +REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT4 ); +REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT5 ); +REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT6 ); +REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT7 ); +REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT8 ); +REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT9 ); +REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT10 ); + +REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_PERV ); +REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT1 ); +REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT2 ); +REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT3 ); +REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT4 ); +REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT5 ); +REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT6 ); +REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT7 ); +REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT8 ); +REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT9 ); +REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATUS_UNIT10 ); + REG64_FLD( PU_CME4_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_EN ); REG64_FLD( PU_CME4_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , @@ -16118,10 +20121,10 @@ REG64_FLD( PU_CME4_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UN SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME4_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); -REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_6_7 , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7 ); -REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_6_7_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7_LEN ); +REG64_FLD( PU_CME4_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_DROPOUT_DETECT ); +REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SPARE_7 ); REG64_FLD( PU_CME4_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME4_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , @@ -16160,10 +20163,10 @@ REG64_FLD( PU_CME4_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UN SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME4_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); -REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_27_28 , 27 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28 ); -REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_27_28_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28_LEN ); +REG64_FLD( PU_CME4_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01 ); +REG64_FLD( PU_CME4_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME4_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME4_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , @@ -16207,10 +20210,10 @@ REG64_FLD( PU_CME3_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UN SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME3_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); -REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_6_7 , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7 ); -REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_6_7_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7_LEN ); +REG64_FLD( PU_CME3_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_DROPOUT_DETECT ); +REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SPARE_7 ); REG64_FLD( PU_CME3_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME3_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , @@ -16249,10 +20252,10 @@ REG64_FLD( PU_CME3_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UN SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME3_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); -REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_27_28 , 27 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28 ); -REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_27_28_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28_LEN ); +REG64_FLD( PU_CME3_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01 ); +REG64_FLD( PU_CME3_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME3_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME3_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , @@ -16296,10 +20299,10 @@ REG64_FLD( PU_CME11_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UN SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME11_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); -REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_6_7 , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7 ); -REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_6_7_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7_LEN ); +REG64_FLD( PU_CME11_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_DROPOUT_DETECT ); +REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SPARE_7 ); REG64_FLD( PU_CME11_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME11_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , @@ -16338,10 +20341,10 @@ REG64_FLD( PU_CME11_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UN SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME11_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); -REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_27_28 , 27 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28 ); -REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_27_28_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28_LEN ); +REG64_FLD( PU_CME11_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01 ); +REG64_FLD( PU_CME11_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME11_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME11_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , @@ -16385,10 +20388,10 @@ REG64_FLD( PU_CME2_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UN SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME2_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); -REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_6_7 , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7 ); -REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_6_7_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7_LEN ); +REG64_FLD( PU_CME2_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_DROPOUT_DETECT ); +REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SPARE_7 ); REG64_FLD( PU_CME2_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME2_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , @@ -16427,10 +20430,10 @@ REG64_FLD( PU_CME2_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UN SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME2_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); -REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_27_28 , 27 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28 ); -REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_27_28_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28_LEN ); +REG64_FLD( PU_CME2_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01 ); +REG64_FLD( PU_CME2_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME2_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME2_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , @@ -16474,10 +20477,10 @@ REG64_FLD( PU_CME5_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UN SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME5_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); -REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_6_7 , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7 ); -REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_6_7_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7_LEN ); +REG64_FLD( PU_CME5_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_DROPOUT_DETECT ); +REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SPARE_7 ); REG64_FLD( PU_CME5_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME5_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , @@ -16516,10 +20519,10 @@ REG64_FLD( PU_CME5_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UN SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME5_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); -REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_27_28 , 27 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28 ); -REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_27_28_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28_LEN ); +REG64_FLD( PU_CME5_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01 ); +REG64_FLD( PU_CME5_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME5_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME5_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , @@ -16563,10 +20566,10 @@ REG64_FLD( PU_CME9_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UN SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME9_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); -REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_6_7 , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7 ); -REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_6_7_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7_LEN ); +REG64_FLD( PU_CME9_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_DROPOUT_DETECT ); +REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SPARE_7 ); REG64_FLD( PU_CME9_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME9_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , @@ -16605,10 +20608,10 @@ REG64_FLD( PU_CME9_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UN SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME9_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); -REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_27_28 , 27 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28 ); -REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_27_28_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28_LEN ); +REG64_FLD( PU_CME9_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01 ); +REG64_FLD( PU_CME9_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME9_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME9_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , @@ -16652,10 +20655,10 @@ REG64_FLD( PU_CME6_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UN SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME6_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); -REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_6_7 , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7 ); -REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_6_7_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7_LEN ); +REG64_FLD( PU_CME6_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_DROPOUT_DETECT ); +REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SPARE_7 ); REG64_FLD( PU_CME6_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME6_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , @@ -16694,10 +20697,10 @@ REG64_FLD( PU_CME6_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UN SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME6_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); -REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_27_28 , 27 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28 ); -REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_27_28_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28_LEN ); +REG64_FLD( PU_CME6_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01 ); +REG64_FLD( PU_CME6_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME6_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME6_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , @@ -16741,10 +20744,10 @@ REG64_FLD( PU_CME10_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UN SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME10_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); -REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_6_7 , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7 ); -REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_6_7_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7_LEN ); +REG64_FLD( PU_CME10_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_DROPOUT_DETECT ); +REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SPARE_7 ); REG64_FLD( PU_CME10_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME10_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , @@ -16783,10 +20786,10 @@ REG64_FLD( PU_CME10_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UN SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME10_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); -REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_27_28 , 27 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28 ); -REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_27_28_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28_LEN ); +REG64_FLD( PU_CME10_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01 ); +REG64_FLD( PU_CME10_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME10_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME10_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , @@ -16830,10 +20833,10 @@ REG64_FLD( PU_CME8_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UN SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME8_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); -REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_6_7 , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7 ); -REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_6_7_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7_LEN ); +REG64_FLD( PU_CME8_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_DROPOUT_DETECT ); +REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SPARE_7 ); REG64_FLD( PU_CME8_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME8_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , @@ -16872,10 +20875,10 @@ REG64_FLD( PU_CME8_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UN SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME8_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); -REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_27_28 , 27 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28 ); -REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_27_28_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28_LEN ); +REG64_FLD( PU_CME8_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01 ); +REG64_FLD( PU_CME8_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME8_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME8_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , @@ -16919,10 +20922,10 @@ REG64_FLD( PU_CME1_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UN SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME1_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); -REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_6_7 , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7 ); -REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_6_7_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7_LEN ); +REG64_FLD( PU_CME1_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_DROPOUT_DETECT ); +REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SPARE_7 ); REG64_FLD( PU_CME1_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME1_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , @@ -16961,10 +20964,10 @@ REG64_FLD( PU_CME1_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UN SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME1_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); -REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_27_28 , 27 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28 ); -REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_27_28_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28_LEN ); +REG64_FLD( PU_CME1_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01 ); +REG64_FLD( PU_CME1_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME1_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME1_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , @@ -17008,10 +21011,10 @@ REG64_FLD( PU_CME0_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UN SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME0_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); -REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_6_7 , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7 ); -REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_6_7_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7_LEN ); +REG64_FLD( PU_CME0_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_DROPOUT_DETECT ); +REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SPARE_7 ); REG64_FLD( PU_CME0_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME0_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , @@ -17050,10 +21053,10 @@ REG64_FLD( PU_CME0_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UN SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME0_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); -REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_27_28 , 27 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28 ); -REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_27_28_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28_LEN ); +REG64_FLD( PU_CME0_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01 ); +REG64_FLD( PU_CME0_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME0_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME0_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , @@ -17097,10 +21100,10 @@ REG64_FLD( PU_CME7_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UN SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME7_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); -REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_6_7 , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7 ); -REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_6_7_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_SPARE_6_7_LEN ); +REG64_FLD( PU_CME7_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_DROPOUT_DETECT ); +REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_7 , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SPARE_7 ); REG64_FLD( PU_CME7_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME7_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , @@ -17139,10 +21142,10 @@ REG64_FLD( PU_CME7_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UN SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME7_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); -REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_27_28 , 27 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28 ); -REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_27_28_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_SPARE_27_28_LEN ); +REG64_FLD( PU_CME7_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01 ); +REG64_FLD( PU_CME7_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME7_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME7_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , @@ -17424,6 +21427,10 @@ REG64_FLD( PU_CME4_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UN SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME4_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME4_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); +REG64_FLD( PU_CME4_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME3_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); @@ -17435,6 +21442,10 @@ REG64_FLD( PU_CME3_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UN SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME3_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME3_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); +REG64_FLD( PU_CME3_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME11_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); @@ -17446,6 +21457,10 @@ REG64_FLD( PU_CME11_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UN SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME11_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME11_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); +REG64_FLD( PU_CME11_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME2_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); @@ -17457,6 +21472,10 @@ REG64_FLD( PU_CME2_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UN SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME2_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME2_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); +REG64_FLD( PU_CME2_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME5_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); @@ -17468,6 +21487,10 @@ REG64_FLD( PU_CME5_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UN SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME5_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME5_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); +REG64_FLD( PU_CME5_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME9_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); @@ -17479,6 +21502,10 @@ REG64_FLD( PU_CME9_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UN SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME9_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME9_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); +REG64_FLD( PU_CME9_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME6_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); @@ -17490,6 +21517,10 @@ REG64_FLD( PU_CME6_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UN SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME6_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME6_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); +REG64_FLD( PU_CME6_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME10_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); @@ -17501,6 +21532,10 @@ REG64_FLD( PU_CME10_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UN SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME10_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME10_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); +REG64_FLD( PU_CME10_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME8_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); @@ -17512,6 +21547,10 @@ REG64_FLD( PU_CME8_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UN SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME8_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME8_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); +REG64_FLD( PU_CME8_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME1_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); @@ -17523,6 +21562,10 @@ REG64_FLD( PU_CME1_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UN SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME1_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME1_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); +REG64_FLD( PU_CME1_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME0_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); @@ -17534,6 +21577,10 @@ REG64_FLD( PU_CME0_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UN SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME0_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME0_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); +REG64_FLD( PU_CME0_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME7_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); @@ -17545,6 +21592,10 @@ REG64_FLD( PU_CME7_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UN SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME7_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); +REG64_FLD( PU_CME7_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); +REG64_FLD( PU_CME7_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); @@ -18098,569 +22149,833 @@ REG64_FLD( PU_CME7_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UN REG64_FLD( PU_CME7_CME_LCL_PECESR1_PC_FUSED_CORE_MODE , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_FUSED_CORE_MODE ); -REG64_FLD( PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_PC_UNMASKED_ATTN_C0 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C0 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C0 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_PM_STATE_ACTIVE_C0 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C0 , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0_LEN ); -REG64_FLD( PU_CME4_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_ALLOW_REG_WAKEUP_C0 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_SPARE_9 , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_SPARE_9 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C0_ACTUAL ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C1_ACTUAL ); +REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9_LEN ); REG64_FLD( PU_CME4_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); -REG64_FLD( PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , +REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME4_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); +REG64_FLD( PU_CME4_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); +REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PC_UNMASKED_ATTN_C0 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 17 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C1 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 18 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C1 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 19 , SH_UNT_PU_CME4 , SH_ACS_PPE , +REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PM_STATE_ACTIVE_C0 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C1 , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE , +REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0_LEN ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); -REG64_FLD( PU_CME4_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_ALLOW_REG_WAKEUP_C1 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_SPARE_25_27 , 25 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_SPARE_25_27 ); -REG64_FLD( PU_CME4_CME_LCL_SISR_SPARE_25_27_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , - SH_FLD_SPARE_25_27_LEN ); -REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 28 , SH_UNT_PU_CME4 , SH_ACS_PPE , +REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C0 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C1 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C0 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C1 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); +REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); - -REG64_FLD( PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_PC_UNMASKED_ATTN_C0 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C0 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C0 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_PM_STATE_ACTIVE_C0 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C0 , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0_LEN ); -REG64_FLD( PU_CME3_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , +REG64_FLD( PU_CME4_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_SPARE_9 , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_SPARE_9 ); +REG64_FLD( PU_CME4_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME4 , SH_ACS_PPE , + SH_FLD_ALLOW_REG_WAKEUP_C1 ); + +REG64_FLD( PU_CME3_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C0_ACTUAL ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C1_ACTUAL ); +REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9_LEN ); REG64_FLD( PU_CME3_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); -REG64_FLD( PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , +REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME3_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); +REG64_FLD( PU_CME3_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); +REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PC_UNMASKED_ATTN_C0 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 17 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C1 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 18 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C1 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 19 , SH_UNT_PU_CME3 , SH_ACS_PPE , +REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PM_STATE_ACTIVE_C0 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C1 , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE , +REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0_LEN ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); -REG64_FLD( PU_CME3_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_ALLOW_REG_WAKEUP_C1 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_SPARE_25_27 , 25 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_SPARE_25_27 ); -REG64_FLD( PU_CME3_CME_LCL_SISR_SPARE_25_27_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , - SH_FLD_SPARE_25_27_LEN ); -REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 28 , SH_UNT_PU_CME3 , SH_ACS_PPE , +REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C0 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C1 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C0 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C1 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); +REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); - -REG64_FLD( PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_PC_UNMASKED_ATTN_C0 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C0 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C0 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_PM_STATE_ACTIVE_C0 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C0 , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0_LEN ); -REG64_FLD( PU_CME11_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , +REG64_FLD( PU_CME3_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_SPARE_9 , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_SPARE_9 ); +REG64_FLD( PU_CME3_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME3 , SH_ACS_PPE , + SH_FLD_ALLOW_REG_WAKEUP_C1 ); + +REG64_FLD( PU_CME11_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C0_ACTUAL ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C1_ACTUAL ); +REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9_LEN ); REG64_FLD( PU_CME11_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); -REG64_FLD( PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , +REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME11_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); +REG64_FLD( PU_CME11_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); +REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PC_UNMASKED_ATTN_C0 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 17 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C1 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 18 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C1 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 19 , SH_UNT_PU_CME11 , SH_ACS_PPE , +REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PM_STATE_ACTIVE_C0 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C1 , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE , +REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0_LEN ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); -REG64_FLD( PU_CME11_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_ALLOW_REG_WAKEUP_C1 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_SPARE_25_27 , 25 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_SPARE_25_27 ); -REG64_FLD( PU_CME11_CME_LCL_SISR_SPARE_25_27_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , - SH_FLD_SPARE_25_27_LEN ); -REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 28 , SH_UNT_PU_CME11 , SH_ACS_PPE , +REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C0 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C1 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C0 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C1 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); +REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); - -REG64_FLD( PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_PC_UNMASKED_ATTN_C0 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C0 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C0 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_PM_STATE_ACTIVE_C0 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C0 , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0_LEN ); -REG64_FLD( PU_CME2_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , +REG64_FLD( PU_CME11_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_SPARE_9 , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_SPARE_9 ); +REG64_FLD( PU_CME11_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME11 , SH_ACS_PPE , + SH_FLD_ALLOW_REG_WAKEUP_C1 ); + +REG64_FLD( PU_CME2_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C0_ACTUAL ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C1_ACTUAL ); +REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9_LEN ); REG64_FLD( PU_CME2_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); -REG64_FLD( PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , +REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME2_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); +REG64_FLD( PU_CME2_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); +REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PC_UNMASKED_ATTN_C0 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 17 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C1 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 18 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C1 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 19 , SH_UNT_PU_CME2 , SH_ACS_PPE , +REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PM_STATE_ACTIVE_C0 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C1 , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE , +REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0_LEN ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); -REG64_FLD( PU_CME2_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_ALLOW_REG_WAKEUP_C1 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_SPARE_25_27 , 25 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_SPARE_25_27 ); -REG64_FLD( PU_CME2_CME_LCL_SISR_SPARE_25_27_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , - SH_FLD_SPARE_25_27_LEN ); -REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 28 , SH_UNT_PU_CME2 , SH_ACS_PPE , +REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C0 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C1 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C0 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C1 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); +REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); - -REG64_FLD( PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_PC_UNMASKED_ATTN_C0 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C0 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C0 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_PM_STATE_ACTIVE_C0 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C0 , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0_LEN ); -REG64_FLD( PU_CME5_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , +REG64_FLD( PU_CME2_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_SPARE_9 , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_SPARE_9 ); +REG64_FLD( PU_CME2_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME2 , SH_ACS_PPE , + SH_FLD_ALLOW_REG_WAKEUP_C1 ); + +REG64_FLD( PU_CME5_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C0_ACTUAL ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C1_ACTUAL ); +REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9_LEN ); REG64_FLD( PU_CME5_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); -REG64_FLD( PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , +REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME5_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); +REG64_FLD( PU_CME5_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); +REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PC_UNMASKED_ATTN_C0 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 17 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C1 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 18 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C1 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 19 , SH_UNT_PU_CME5 , SH_ACS_PPE , +REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PM_STATE_ACTIVE_C0 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C1 , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE , +REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0_LEN ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); -REG64_FLD( PU_CME5_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_ALLOW_REG_WAKEUP_C1 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_SPARE_25_27 , 25 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_SPARE_25_27 ); -REG64_FLD( PU_CME5_CME_LCL_SISR_SPARE_25_27_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , - SH_FLD_SPARE_25_27_LEN ); -REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 28 , SH_UNT_PU_CME5 , SH_ACS_PPE , +REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C0 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C1 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C0 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C1 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); +REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); - -REG64_FLD( PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_PC_UNMASKED_ATTN_C0 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C0 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C0 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_PM_STATE_ACTIVE_C0 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C0 , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0_LEN ); -REG64_FLD( PU_CME9_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , +REG64_FLD( PU_CME5_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_SPARE_9 , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_SPARE_9 ); +REG64_FLD( PU_CME5_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME5 , SH_ACS_PPE , + SH_FLD_ALLOW_REG_WAKEUP_C1 ); + +REG64_FLD( PU_CME9_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C0_ACTUAL ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C1_ACTUAL ); +REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9_LEN ); REG64_FLD( PU_CME9_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); -REG64_FLD( PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , +REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME9_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); +REG64_FLD( PU_CME9_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); +REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PC_UNMASKED_ATTN_C0 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 17 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C1 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 18 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C1 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 19 , SH_UNT_PU_CME9 , SH_ACS_PPE , +REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PM_STATE_ACTIVE_C0 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C1 , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE , +REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0_LEN ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); -REG64_FLD( PU_CME9_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_ALLOW_REG_WAKEUP_C1 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_SPARE_25_27 , 25 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_SPARE_25_27 ); -REG64_FLD( PU_CME9_CME_LCL_SISR_SPARE_25_27_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , - SH_FLD_SPARE_25_27_LEN ); -REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 28 , SH_UNT_PU_CME9 , SH_ACS_PPE , +REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C0 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C1 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C0 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C1 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); +REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); - -REG64_FLD( PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_PC_UNMASKED_ATTN_C0 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C0 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C0 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_PM_STATE_ACTIVE_C0 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C0 , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0_LEN ); -REG64_FLD( PU_CME6_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , +REG64_FLD( PU_CME9_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_SPARE_9 , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_SPARE_9 ); +REG64_FLD( PU_CME9_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME9 , SH_ACS_PPE , + SH_FLD_ALLOW_REG_WAKEUP_C1 ); + +REG64_FLD( PU_CME6_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C0_ACTUAL ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C1_ACTUAL ); +REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9_LEN ); REG64_FLD( PU_CME6_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); -REG64_FLD( PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , +REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME6_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); +REG64_FLD( PU_CME6_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); +REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PC_UNMASKED_ATTN_C0 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 17 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C1 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 18 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C1 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 19 , SH_UNT_PU_CME6 , SH_ACS_PPE , +REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PM_STATE_ACTIVE_C0 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C1 , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE , +REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0_LEN ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); -REG64_FLD( PU_CME6_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_ALLOW_REG_WAKEUP_C1 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_SPARE_25_27 , 25 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_SPARE_25_27 ); -REG64_FLD( PU_CME6_CME_LCL_SISR_SPARE_25_27_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , - SH_FLD_SPARE_25_27_LEN ); -REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 28 , SH_UNT_PU_CME6 , SH_ACS_PPE , +REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C0 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C1 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C0 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C1 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); +REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); - -REG64_FLD( PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_PC_UNMASKED_ATTN_C0 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C0 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C0 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_PM_STATE_ACTIVE_C0 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C0 , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0_LEN ); -REG64_FLD( PU_CME10_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , +REG64_FLD( PU_CME6_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_SPARE_9 , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_SPARE_9 ); +REG64_FLD( PU_CME6_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME6 , SH_ACS_PPE , + SH_FLD_ALLOW_REG_WAKEUP_C1 ); + +REG64_FLD( PU_CME10_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C0_ACTUAL ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C1_ACTUAL ); +REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9_LEN ); REG64_FLD( PU_CME10_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); -REG64_FLD( PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , +REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME10_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); +REG64_FLD( PU_CME10_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); +REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PC_UNMASKED_ATTN_C0 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 17 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C1 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 18 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C1 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 19 , SH_UNT_PU_CME10 , SH_ACS_PPE , +REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PM_STATE_ACTIVE_C0 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C1 , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE , +REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0_LEN ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); -REG64_FLD( PU_CME10_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_ALLOW_REG_WAKEUP_C1 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_SPARE_25_27 , 25 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_SPARE_25_27 ); -REG64_FLD( PU_CME10_CME_LCL_SISR_SPARE_25_27_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , - SH_FLD_SPARE_25_27_LEN ); -REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 28 , SH_UNT_PU_CME10 , SH_ACS_PPE , +REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C0 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C1 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C0 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C1 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); +REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); - -REG64_FLD( PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_PC_UNMASKED_ATTN_C0 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C0 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C0 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_PM_STATE_ACTIVE_C0 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C0 , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0_LEN ); -REG64_FLD( PU_CME8_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , +REG64_FLD( PU_CME10_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_SPARE_9 , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_SPARE_9 ); +REG64_FLD( PU_CME10_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME10 , SH_ACS_PPE , + SH_FLD_ALLOW_REG_WAKEUP_C1 ); + +REG64_FLD( PU_CME8_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C0_ACTUAL ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C1_ACTUAL ); +REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9_LEN ); REG64_FLD( PU_CME8_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); -REG64_FLD( PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , +REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME8_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); +REG64_FLD( PU_CME8_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); +REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PC_UNMASKED_ATTN_C0 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 17 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C1 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 18 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C1 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 19 , SH_UNT_PU_CME8 , SH_ACS_PPE , +REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PM_STATE_ACTIVE_C0 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C1 , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE , +REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0_LEN ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); -REG64_FLD( PU_CME8_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_ALLOW_REG_WAKEUP_C1 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_SPARE_25_27 , 25 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_SPARE_25_27 ); -REG64_FLD( PU_CME8_CME_LCL_SISR_SPARE_25_27_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , - SH_FLD_SPARE_25_27_LEN ); -REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 28 , SH_UNT_PU_CME8 , SH_ACS_PPE , +REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C0 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C1 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C0 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C1 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); +REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); - -REG64_FLD( PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_PC_UNMASKED_ATTN_C0 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C0 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C0 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_PM_STATE_ACTIVE_C0 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C0 , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0_LEN ); -REG64_FLD( PU_CME1_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , +REG64_FLD( PU_CME8_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_SPARE_9 , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_SPARE_9 ); +REG64_FLD( PU_CME8_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME8 , SH_ACS_PPE , + SH_FLD_ALLOW_REG_WAKEUP_C1 ); + +REG64_FLD( PU_CME1_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C0_ACTUAL ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C1_ACTUAL ); +REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9_LEN ); REG64_FLD( PU_CME1_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); -REG64_FLD( PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , +REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME1_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); +REG64_FLD( PU_CME1_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); +REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PC_UNMASKED_ATTN_C0 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 17 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C1 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 18 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C1 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 19 , SH_UNT_PU_CME1 , SH_ACS_PPE , +REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PM_STATE_ACTIVE_C0 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C1 , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE , +REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0_LEN ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); -REG64_FLD( PU_CME1_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_ALLOW_REG_WAKEUP_C1 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_SPARE_25_27 , 25 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_SPARE_25_27 ); -REG64_FLD( PU_CME1_CME_LCL_SISR_SPARE_25_27_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , - SH_FLD_SPARE_25_27_LEN ); -REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 28 , SH_UNT_PU_CME1 , SH_ACS_PPE , +REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C0 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C1 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C0 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C1 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); +REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); - -REG64_FLD( PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_PC_UNMASKED_ATTN_C0 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C0 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C0 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_PM_STATE_ACTIVE_C0 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C0 , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0_LEN ); -REG64_FLD( PU_CME0_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , +REG64_FLD( PU_CME1_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_SPARE_9 , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_SPARE_9 ); +REG64_FLD( PU_CME1_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME1 , SH_ACS_PPE , + SH_FLD_ALLOW_REG_WAKEUP_C1 ); + +REG64_FLD( PU_CME0_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C0_ACTUAL ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C1_ACTUAL ); +REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9_LEN ); REG64_FLD( PU_CME0_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); -REG64_FLD( PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , +REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME0_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); +REG64_FLD( PU_CME0_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); +REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PC_UNMASKED_ATTN_C0 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 17 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C1 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 18 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C1 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 19 , SH_UNT_PU_CME0 , SH_ACS_PPE , +REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PM_STATE_ACTIVE_C0 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C1 , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE , +REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0_LEN ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); -REG64_FLD( PU_CME0_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_ALLOW_REG_WAKEUP_C1 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_SPARE_25_27 , 25 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_SPARE_25_27 ); -REG64_FLD( PU_CME0_CME_LCL_SISR_SPARE_25_27_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , - SH_FLD_SPARE_25_27_LEN ); -REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 28 , SH_UNT_PU_CME0 , SH_ACS_PPE , +REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C0 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C1 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C0 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C1 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); +REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); - -REG64_FLD( PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_PC_UNMASKED_ATTN_C0 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C0 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C0 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_PM_STATE_ACTIVE_C0 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C0 , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_PM_STATE_C0_LEN ); -REG64_FLD( PU_CME7_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , +REG64_FLD( PU_CME0_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_SPARE_9 , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_SPARE_9 ); +REG64_FLD( PU_CME0_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME0 , SH_ACS_PPE , + SH_FLD_ALLOW_REG_WAKEUP_C1 ); + +REG64_FLD( PU_CME7_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C0_ACTUAL ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PM_EXIT_C1_ACTUAL ); +REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_6_9 , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_6_9_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_RESERVED_6_9_LEN ); REG64_FLD( PU_CME7_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); -REG64_FLD( PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , +REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME7_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); +REG64_FLD( PU_CME7_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); +REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_18_31 , 18 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_18_31_LEN , 14 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PC_UNMASKED_ATTN_C0 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 17 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_PC_INSTR_RUNNING_C1 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 18 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_PM_STATE_ALL_HV_C1 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 19 , SH_UNT_PU_CME7 , SH_ACS_PPE , +REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PM_STATE_ACTIVE_C0 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C1 , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE , +REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PM_STATE_C0_LEN ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); -REG64_FLD( PU_CME7_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_ALLOW_REG_WAKEUP_C1 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_SPARE_25_27 , 25 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_SPARE_25_27 ); -REG64_FLD( PU_CME7_CME_LCL_SISR_SPARE_25_27_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , - SH_FLD_SPARE_25_27_LEN ); -REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 28 , SH_UNT_PU_CME7 , SH_ACS_PPE , +REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C0 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PM_STATE_ALL_HV_C1 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C0 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PC_INSTR_RUNNING_C1 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); +REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); +REG64_FLD( PU_CME7_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_ALLOW_REG_WAKEUP_C0 ); +REG64_FLD( PU_CME7_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME7 , SH_ACS_PPE , + SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( PU_CME4_CME_LCL_TSEL_FIT_SEL , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_FIT_SEL ); @@ -23318,833 +27633,737 @@ REG64_FLD( PU_CME7_CME_SCOM_QFMR_CYCLES , 32 , SH_UN REG64_FLD( PU_CME7_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_CYCLES_LEN ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_PC_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C0 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0 , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C0 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_PC_WAKEUP_C0 , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C0 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_PCBMUX_REQ_C0 , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C0 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_4_5 , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_4_5_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C0 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C1 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C0 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_8_11 , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_8_11_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11_LEN ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_PC_ENTRY_ACK_C1 , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C1 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1 , 13 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C1 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_PC_WAKEUP_C1 , 14 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C1 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_PCBMUX_REQ_C1 , 15 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C1 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_16_17 , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_16_17_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17_LEN ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 18 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 19 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_20_23 , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_20_23_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23_LEN ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_PURGE , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C0 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C1 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C0 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C1 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_PURGE_ABORT , 25 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED26 , 26 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_RESERVED26 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 27 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_PURGE , 28 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_PURGE_ABORT , 29 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_CHTM_PURGE_C0 , 30 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_CHTM_PURGE_C1 , 31 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_HMI_REQUEST_C0 , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_HMI_REQUEST_C1 , 33 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 34 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 35 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , +REG64_FLD( PU_CME4_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_36_39 , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39 ); -REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_36_39_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39_LEN ); - -REG64_FLD( PU_CME3_CME_SCOM_SICR_PC_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C0 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0 , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C0 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_PC_WAKEUP_C0 , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C0 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_PCBMUX_REQ_C0 , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C0 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_4_5 , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_4_5_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5_LEN ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31 ); +REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31_LEN ); + +REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C0 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C1 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C0 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_8_11 , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_8_11_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11_LEN ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_PC_ENTRY_ACK_C1 , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C1 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1 , 13 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C1 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_PC_WAKEUP_C1 , 14 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C1 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_PCBMUX_REQ_C1 , 15 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C1 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_16_17 , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_16_17_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17_LEN ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 18 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 19 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_20_23 , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_20_23_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23_LEN ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_PURGE , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C0 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C1 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C0 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C1 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_PURGE_ABORT , 25 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED26 , 26 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_RESERVED26 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 27 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_PURGE , 28 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_PURGE_ABORT , 29 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_CHTM_PURGE_C0 , 30 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_CHTM_PURGE_C1 , 31 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_HMI_REQUEST_C0 , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_HMI_REQUEST_C1 , 33 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 34 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 35 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , +REG64_FLD( PU_CME3_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_36_39 , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39 ); -REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_36_39_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39_LEN ); - -REG64_FLD( PU_CME11_CME_SCOM_SICR_PC_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C0 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0 , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C0 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_PC_WAKEUP_C0 , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C0 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_PCBMUX_REQ_C0 , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C0 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_4_5 , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_4_5_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5_LEN ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31 ); +REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31_LEN ); + +REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C0 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C1 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C0 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_8_11 , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_8_11_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11_LEN ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_PC_ENTRY_ACK_C1 , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C1 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1 , 13 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C1 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_PC_WAKEUP_C1 , 14 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C1 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_PCBMUX_REQ_C1 , 15 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C1 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_16_17 , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_16_17_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17_LEN ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 18 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 19 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_20_23 , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_20_23_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23_LEN ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_PURGE , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C0 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C1 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C0 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C1 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_PURGE_ABORT , 25 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED26 , 26 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_RESERVED26 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 27 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_PURGE , 28 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_PURGE_ABORT , 29 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_CHTM_PURGE_C0 , 30 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_CHTM_PURGE_C1 , 31 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_HMI_REQUEST_C0 , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_HMI_REQUEST_C1 , 33 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 34 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 35 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , +REG64_FLD( PU_CME11_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_36_39 , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39 ); -REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_36_39_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39_LEN ); - -REG64_FLD( PU_CME2_CME_SCOM_SICR_PC_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C0 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0 , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C0 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_PC_WAKEUP_C0 , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C0 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_PCBMUX_REQ_C0 , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C0 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_4_5 , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_4_5_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5_LEN ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31 ); +REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31_LEN ); + +REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C0 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C1 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C0 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_8_11 , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_8_11_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11_LEN ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_PC_ENTRY_ACK_C1 , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C1 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1 , 13 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C1 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_PC_WAKEUP_C1 , 14 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C1 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_PCBMUX_REQ_C1 , 15 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C1 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_16_17 , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_16_17_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17_LEN ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 18 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 19 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_20_23 , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_20_23_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23_LEN ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_PURGE , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C0 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C1 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C0 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C1 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_PURGE_ABORT , 25 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED26 , 26 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_RESERVED26 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 27 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_PURGE , 28 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_PURGE_ABORT , 29 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_CHTM_PURGE_C0 , 30 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_CHTM_PURGE_C1 , 31 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_HMI_REQUEST_C0 , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_HMI_REQUEST_C1 , 33 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 34 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 35 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , +REG64_FLD( PU_CME2_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_36_39 , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39 ); -REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_36_39_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39_LEN ); - -REG64_FLD( PU_CME5_CME_SCOM_SICR_PC_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C0 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0 , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C0 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_PC_WAKEUP_C0 , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C0 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_PCBMUX_REQ_C0 , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C0 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_4_5 , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_4_5_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5_LEN ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31 ); +REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31_LEN ); + +REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C0 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C1 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C0 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_8_11 , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_8_11_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11_LEN ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_PC_ENTRY_ACK_C1 , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C1 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1 , 13 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C1 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_PC_WAKEUP_C1 , 14 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C1 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_PCBMUX_REQ_C1 , 15 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C1 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_16_17 , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_16_17_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17_LEN ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 18 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 19 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_20_23 , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_20_23_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23_LEN ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_PURGE , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C0 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C1 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C0 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C1 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_PURGE_ABORT , 25 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED26 , 26 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_RESERVED26 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 27 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_PURGE , 28 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_PURGE_ABORT , 29 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_CHTM_PURGE_C0 , 30 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_CHTM_PURGE_C1 , 31 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_HMI_REQUEST_C0 , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_HMI_REQUEST_C1 , 33 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 34 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 35 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , +REG64_FLD( PU_CME5_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_36_39 , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39 ); -REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_36_39_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39_LEN ); - -REG64_FLD( PU_CME9_CME_SCOM_SICR_PC_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C0 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0 , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C0 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_PC_WAKEUP_C0 , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C0 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_PCBMUX_REQ_C0 , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C0 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_4_5 , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_4_5_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5_LEN ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31 ); +REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31_LEN ); + +REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C0 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C1 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C0 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_8_11 , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_8_11_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11_LEN ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_PC_ENTRY_ACK_C1 , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C1 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1 , 13 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C1 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_PC_WAKEUP_C1 , 14 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C1 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_PCBMUX_REQ_C1 , 15 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C1 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_16_17 , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_16_17_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17_LEN ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 18 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 19 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_20_23 , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_20_23_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23_LEN ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_PURGE , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C0 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C1 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C0 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C1 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_PURGE_ABORT , 25 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED26 , 26 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_RESERVED26 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 27 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_PURGE , 28 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_PURGE_ABORT , 29 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_CHTM_PURGE_C0 , 30 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_CHTM_PURGE_C1 , 31 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_HMI_REQUEST_C0 , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_HMI_REQUEST_C1 , 33 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 34 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 35 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , +REG64_FLD( PU_CME9_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_36_39 , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39 ); -REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_36_39_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39_LEN ); - -REG64_FLD( PU_CME6_CME_SCOM_SICR_PC_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C0 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0 , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C0 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_PC_WAKEUP_C0 , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C0 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_PCBMUX_REQ_C0 , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C0 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_4_5 , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_4_5_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5_LEN ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31 ); +REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31_LEN ); + +REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C0 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C1 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C0 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_8_11 , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_8_11_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11_LEN ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_PC_ENTRY_ACK_C1 , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C1 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1 , 13 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C1 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_PC_WAKEUP_C1 , 14 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C1 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_PCBMUX_REQ_C1 , 15 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C1 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_16_17 , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_16_17_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17_LEN ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 18 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 19 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_20_23 , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_20_23_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23_LEN ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_PURGE , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C0 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C1 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C0 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C1 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_PURGE_ABORT , 25 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED26 , 26 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_RESERVED26 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 27 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_PURGE , 28 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_PURGE_ABORT , 29 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_CHTM_PURGE_C0 , 30 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_CHTM_PURGE_C1 , 31 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_HMI_REQUEST_C0 , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_HMI_REQUEST_C1 , 33 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 34 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 35 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , +REG64_FLD( PU_CME6_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_36_39 , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39 ); -REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_36_39_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39_LEN ); - -REG64_FLD( PU_CME10_CME_SCOM_SICR_PC_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C0 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0 , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C0 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_PC_WAKEUP_C0 , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C0 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_PCBMUX_REQ_C0 , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C0 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_4_5 , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_4_5_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5_LEN ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31 ); +REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31_LEN ); + +REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C0 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C1 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C0 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_8_11 , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_8_11_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11_LEN ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_PC_ENTRY_ACK_C1 , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C1 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1 , 13 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C1 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_PC_WAKEUP_C1 , 14 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C1 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_PCBMUX_REQ_C1 , 15 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C1 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_16_17 , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_16_17_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17_LEN ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 18 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 19 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_20_23 , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_20_23_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23_LEN ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_PURGE , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C0 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C1 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C0 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C1 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_PURGE_ABORT , 25 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED26 , 26 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_RESERVED26 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 27 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_PURGE , 28 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_PURGE_ABORT , 29 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_CHTM_PURGE_C0 , 30 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_CHTM_PURGE_C1 , 31 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_HMI_REQUEST_C0 , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_HMI_REQUEST_C1 , 33 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 34 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 35 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , +REG64_FLD( PU_CME10_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_36_39 , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39 ); -REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_36_39_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39_LEN ); - -REG64_FLD( PU_CME8_CME_SCOM_SICR_PC_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C0 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0 , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C0 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_PC_WAKEUP_C0 , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C0 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_PCBMUX_REQ_C0 , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C0 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_4_5 , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_4_5_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5_LEN ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31 ); +REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31_LEN ); + +REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C0 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C1 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C0 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_8_11 , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_8_11_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11_LEN ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_PC_ENTRY_ACK_C1 , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C1 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1 , 13 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C1 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_PC_WAKEUP_C1 , 14 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C1 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_PCBMUX_REQ_C1 , 15 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C1 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_16_17 , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_16_17_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17_LEN ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 18 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 19 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_20_23 , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_20_23_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23_LEN ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_PURGE , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C0 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C1 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C0 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C1 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_PURGE_ABORT , 25 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED26 , 26 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_RESERVED26 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 27 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_PURGE , 28 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_PURGE_ABORT , 29 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_CHTM_PURGE_C0 , 30 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_CHTM_PURGE_C1 , 31 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_HMI_REQUEST_C0 , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_HMI_REQUEST_C1 , 33 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 34 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 35 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , +REG64_FLD( PU_CME8_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_36_39 , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39 ); -REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_36_39_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39_LEN ); - -REG64_FLD( PU_CME1_CME_SCOM_SICR_PC_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C0 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0 , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C0 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_PC_WAKEUP_C0 , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C0 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_PCBMUX_REQ_C0 , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C0 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_4_5 , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_4_5_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5_LEN ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31 ); +REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31_LEN ); + +REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C0 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C1 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C0 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_8_11 , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_8_11_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11_LEN ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_PC_ENTRY_ACK_C1 , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C1 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1 , 13 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C1 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_PC_WAKEUP_C1 , 14 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C1 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_PCBMUX_REQ_C1 , 15 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C1 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_16_17 , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_16_17_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17_LEN ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 18 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 19 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_20_23 , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_20_23_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23_LEN ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_PURGE , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C0 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C1 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C0 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C1 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_PURGE_ABORT , 25 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED26 , 26 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_RESERVED26 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 27 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_PURGE , 28 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_PURGE_ABORT , 29 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_CHTM_PURGE_C0 , 30 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_CHTM_PURGE_C1 , 31 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_HMI_REQUEST_C0 , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_HMI_REQUEST_C1 , 33 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 34 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 35 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , +REG64_FLD( PU_CME1_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_36_39 , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39 ); -REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_36_39_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39_LEN ); - -REG64_FLD( PU_CME0_CME_SCOM_SICR_PC_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C0 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0 , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C0 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_PC_WAKEUP_C0 , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C0 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_PCBMUX_REQ_C0 , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C0 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_4_5 , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_4_5_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5_LEN ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31 ); +REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31_LEN ); + +REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C0 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C1 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C0 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_8_11 , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_8_11_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11_LEN ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_PC_ENTRY_ACK_C1 , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C1 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1 , 13 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C1 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_PC_WAKEUP_C1 , 14 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C1 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_PCBMUX_REQ_C1 , 15 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C1 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_16_17 , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_16_17_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17_LEN ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 18 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 19 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_20_23 , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_20_23_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23_LEN ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_PURGE , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C0 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C1 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C0 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C1 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_PURGE_ABORT , 25 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED26 , 26 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_RESERVED26 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 27 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_PURGE , 28 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_PURGE_ABORT , 29 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_CHTM_PURGE_C0 , 30 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_CHTM_PURGE_C1 , 31 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_HMI_REQUEST_C0 , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_HMI_REQUEST_C1 , 33 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 34 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 35 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , +REG64_FLD( PU_CME0_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_36_39 , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39 ); -REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_36_39_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39_LEN ); - -REG64_FLD( PU_CME7_CME_SCOM_SICR_PC_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C0 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C0 , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C0 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_PC_WAKEUP_C0 , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C0 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_PCBMUX_REQ_C0 , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C0 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_4_5 , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_4_5_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_5_LEN ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31 ); +REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31_LEN ); + +REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C0 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PM_ENTRY_ACK_C1 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C0 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_8_11 , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_8_11_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_11_LEN ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_PC_ENTRY_ACK_C1 , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_PC_ENTRY_ACK_C1 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_PC_BLOCK_INTERRUPTS_C1 , 13 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_PC_BLOCK_INTERRUPTS_C1 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_PC_WAKEUP_C1 , 14 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_PC_WAKEUP_C1 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_PCBMUX_REQ_C1 , 15 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_PCBMUX_REQ_C1 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_16_17 , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_16_17_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_17_LEN ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 18 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 19 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_20_23 , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_20_23_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_RESERVED_20_23_LEN ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_PURGE , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C0 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_PCBMUX_REQ_C1 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_RESERVED_12_15_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C0 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_SPECIAL_WKUP_DONE_C1 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_PURGE_ABORT , 25 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED26 , 26 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_RESERVED26 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 27 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_RESERVED20 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_PURGE , 28 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_PURGE_ABORT , 29 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_CHTM_PURGE_C0 , 30 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_CHTM_PURGE_C1 , 31 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_HMI_REQUEST_C0 , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_HMI_REQUEST_C1 , 33 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 34 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 35 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , +REG64_FLD( PU_CME7_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_36_39 , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39 ); -REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_36_39_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , - SH_FLD_RESERVED_36_39_LEN ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31 ); +REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , + SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_CME4_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA ); @@ -25140,10 +29359,10 @@ REG32_FLD( PU_COMMAND_REGISTER_UNUSED_16_22 , 16 , SH_UN SH_FLD_UNUSED_16_22 ); REG32_FLD( PU_COMMAND_REGISTER_UNUSED_16_22_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_16_22_LEN ); -REG32_FLD( PU_COMMAND_REGISTER_REG_ADDR_LEN , 23 , SH_UNT , SH_ACS_SCOM , - SH_FLD_REG_ADDR_LEN ); -REG32_FLD( PU_COMMAND_REGISTER_REG_ADDR_LEN_LEN , 3 , SH_UNT , SH_ACS_SCOM , - SH_FLD_REG_ADDR_LEN_LEN ); +REG32_FLD( PU_COMMAND_REGISTER_REG_ADDR_LENGTH , 23 , SH_UNT , SH_ACS_SCOM , + SH_FLD_REG_ADDR_LENGTH ); +REG32_FLD( PU_COMMAND_REGISTER_REG_ADDR_LENGTH_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_REG_ADDR_LENGTH_LEN ); REG32_FLD( PU_COMMAND_REGISTER_UNUSED_26_31 , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_26_31 ); REG32_FLD( PU_COMMAND_REGISTER_UNUSED_26_31_LEN , 6 , SH_UNT , SH_ACS_SCOM , @@ -25377,9 +29596,15 @@ REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UN SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); -REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); +REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_PCKT_BLK_PRB ); +REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_P9P9_MODE ); +REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3_LEN , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , @@ -25478,9 +29703,15 @@ REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UN SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); -REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); +REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_PCKT_BLK_PRB ); +REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_P9P9_MODE ); +REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3_LEN , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , @@ -25579,9 +29810,15 @@ REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UN SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); -REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); +REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_PCKT_BLK_PRB ); +REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_P9P9_MODE ); +REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3_LEN , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , @@ -25680,9 +29917,15 @@ REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UN SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); -REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); +REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_PCKT_BLK_PRB ); +REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_P9P9_MODE ); +REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3_LEN , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , @@ -25781,9 +30024,15 @@ REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UN SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); -REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); +REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_PCKT_BLK_PRB ); +REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_P9P9_MODE ); +REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3_LEN , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , @@ -25882,9 +30131,15 @@ REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UN SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); -REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); +REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_PCKT_BLK_PRB ); +REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_P9P9_MODE ); +REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3_LEN , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , @@ -25983,9 +30238,15 @@ REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UN SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); -REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); +REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_PCKT_BLK_PRB ); +REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_P9P9_MODE ); +REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3_LEN , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , @@ -26038,9 +30299,11 @@ REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN , 4 , SH_UN SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_BRAZOS_MODE , 48 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); -REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED2 , 49 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR , 49 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_CONFIG_DISABLE_PBM_ECC_COR ); +REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED2 , 50 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); -REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 15 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 14 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , @@ -26139,9 +30402,15 @@ REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UN SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); -REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); +REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_PCKT_BLK_PRB ); +REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_P9P9_MODE ); +REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3_LEN , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , @@ -26240,9 +30509,15 @@ REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UN SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); -REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); +REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_PCKT_BLK_PRB ); +REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_P9P9_MODE ); +REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3_LEN , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , @@ -26341,9 +30616,15 @@ REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UN SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); -REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); +REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_PCKT_BLK_PRB ); +REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_P9P9_MODE ); +REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3_LEN , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , @@ -26396,9 +30677,11 @@ REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN , 4 , SH_UN SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_BRAZOS_MODE , 48 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); -REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED2 , 49 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR , 49 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_CONFIG_DISABLE_PBM_ECC_COR ); +REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED2 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); -REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 15 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 14 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , @@ -26451,9 +30734,11 @@ REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN , 4 , SH_UN SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_BRAZOS_MODE , 48 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); -REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED2 , 49 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR , 49 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_CONFIG_DISABLE_PBM_ECC_COR ); +REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED2 , 50 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); -REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 15 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 14 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , @@ -26552,9 +30837,15 @@ REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UN SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); -REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); +REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_PCKT_BLK_PRB ); +REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_P9P9_MODE ); +REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3_LEN , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , @@ -26653,35 +30944,65 @@ REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UN SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); -REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); +REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_PCKT_BLK_PRB ); +REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_P9P9_MODE ); +REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3_LEN , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); -REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN ); -REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN ); -REG64_FLD( PU_NPU1_SM2_CONFIG1_RESERVED , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); +REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); +REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); +REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT ); +REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU1_SM2_CONFIG1_RESERVED_LEN , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); -REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN ); -REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN ); -REG64_FLD( PU_NPU1_SM3_CONFIG1_RESERVED , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); +REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); +REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); +REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT ); +REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU1_SM3_CONFIG1_RESERVED_LEN , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_NTL1_CONFIG1_COMPRESSED_RSP_ENA , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , @@ -26698,33 +31019,63 @@ REG64_FLD( PU_NPU2_NTL1_CONFIG1_RSP_AE_ALWAYS , 6 , SH_UN SH_FLD_RSP_AE_ALWAYS ); REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED2 , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED2_LEN , 57 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_NTL1_CONFIG1_NTL_RESET , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_RESET ); +REG64_FLD( PU_NPU2_NTL1_CONFIG1_NTL_RESET_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NTL_RESET_LEN ); +REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED3 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED3_LEN , 54 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); -REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN ); -REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN ); -REG64_FLD( PU_NPU1_SM1_CONFIG1_RESERVED , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); +REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); +REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); +REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT ); +REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU1_SM1_CONFIG1_RESERVED_LEN , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); -REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN ); -REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN ); -REG64_FLD( PU_NPU0_SM2_CONFIG1_RESERVED , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); +REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); +REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); +REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT ); +REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU0_SM2_CONFIG1_RESERVED_LEN , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG1_IDIAL , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , @@ -26732,164 +31083,123 @@ REG64_FLD( PU_NPU0_CTL_CONFIG1_IDIAL , 0 , SH_UN REG64_FLD( PU_NPU0_CTL_CONFIG1_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); -REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); -REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); -REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN ); -REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN ); -REG64_FLD( PU_NPU0_SM1_CONFIG1_RESERVED , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED ); -REG64_FLD( PU_NPU0_SM1_CONFIG1_RESERVED_LEN , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED_LEN ); - -REG64_FLD( PU_NPU2_DAT_CONFIG1_MGR_CREDIT , 0 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MGR_CREDIT , 0 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MGR_CREDIT ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MGR_CREDIT_LEN , 2 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MGR_CREDIT_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MGR_CREDIT_LEN ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_PBTX_NBUF , 2 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MRG_PBTX_NBUF , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_PBTX_NBUF ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_PBTX_NBUF_LEN , 3 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MRG_PBTX_NBUF_LEN , 3 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_PBTX_NBUF_LEN ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_RDBF_NBUF , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MRG_RDBF_NBUF , 5 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_RDBF_NBUF ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_RDBF_NBUF_LEN , 4 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MRG_RDBF_NBUF_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_RDBF_NBUF_LEN ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_IBWR_NBUF , 9 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MRG_IBWR_NBUF , 9 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_IBWR_NBUF ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_IBWR_NBUF_LEN , 4 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MRG_IBWR_NBUF_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_IBWR_NBUF_LEN ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_IBRD_NBUF , 13 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MRG_IBRD_NBUF , 13 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_IBRD_NBUF ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_IBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MRG_IBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_IBRD_NBUF_LEN ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_BBRD_NBUF , 16 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MRG_BBRD_NBUF , 16 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_BBRD_NBUF ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_BBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MRG_BBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_BBRD_NBUF_LEN ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_OBRD_NBUF , 19 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MRG_OBRD_NBUF , 19 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_OBRD_NBUF ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_OBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MRG_OBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_OBRD_NBUF_LEN ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_CR_DIS , 22 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MRG_CR_DIS , 22 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_CR_DIS ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_MRG_CTLW_CR_DIS , 23 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_MRG_CTLW_CR_DIS , 23 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_CTLW_CR_DIS ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_NTLR_PAUSE_THRESH , 24 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_NTLR_PAUSE_THRESH , 24 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_NTLR_PAUSE_THRESH ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_NTLR_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_NTLR_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_NTLR_PAUSE_THRESH_LEN ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_CTLR_HP_THRESH , 26 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_CTLR_HP_THRESH , 26 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CTLR_HP_THRESH ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_CTLR_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_CTLR_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CTLR_HP_THRESH_LEN ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_NTLW_PAUSE_THRESH , 28 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_NTLW_PAUSE_THRESH , 28 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_NTLW_PAUSE_THRESH ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_NTLW_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_NTLW_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_NTLW_PAUSE_THRESH_LEN ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_CTLW_HP_THRESH , 30 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_CTLW_HP_THRESH , 30 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CTLW_HP_THRESH ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_CTLW_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_CTLW_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CTLW_HP_THRESH_LEN ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_PBTX_REDUCE_RTAG , 32 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_PBTX_REDUCE_RTAG , 32 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_PBTX_REDUCE_RTAG ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_PBTX_DELAY_BDONE , 33 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_PBTX_DELAY_BDONE , 33 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_PBTX_DELAY_BDONE ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_PBTX_FLIP_IMIN_BIG , 34 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_PBTX_FLIP_IMIN_BIG , 34 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_PBTX_FLIP_IMIN_BIG ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_PBTX_FLIP_IMIN_LITTLE , 35 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_PBTX_FLIP_IMIN_LITTLE , 35 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_PBTX_FLIP_IMIN_LITTLE ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_ALU_SAFE_LATENCY , 36 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_ALU_SAFE_LATENCY , 36 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_ALU_SAFE_LATENCY ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_ALU_FLIP_ENDIAN_BIG , 37 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_ALU_FLIP_ENDIAN_BIG , 37 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_ALU_FLIP_ENDIAN_BIG ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_ALU_FLIP_ENDIAN_LITTLE , 38 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_ALU_FLIP_ENDIAN_LITTLE , 38 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_ALU_FLIP_ENDIAN_LITTLE ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_RESERVED1 , 39 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_PBTX_EARLY_AFTAG , 39 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_PBTX_EARLY_AFTAG ); +REG64_FLD( PU_NPU1_CONFIG1_RESERVED1 , 40 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_DAT_CONFIG1_RESERVED1_LEN , 25 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_CONFIG1_RESERVED1_LEN , 24 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MGR_CREDIT , 0 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MGR_CREDIT ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MGR_CREDIT_LEN , 2 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MGR_CREDIT_LEN ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_PBTX_NBUF , 2 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MRG_PBTX_NBUF ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_PBTX_NBUF_LEN , 3 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MRG_PBTX_NBUF_LEN ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_RDBF_NBUF , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MRG_RDBF_NBUF ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_RDBF_NBUF_LEN , 4 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MRG_RDBF_NBUF_LEN ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_IBWR_NBUF , 9 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MRG_IBWR_NBUF ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_IBWR_NBUF_LEN , 4 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MRG_IBWR_NBUF_LEN ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_IBRD_NBUF , 13 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MRG_IBRD_NBUF ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_IBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MRG_IBRD_NBUF_LEN ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_BBRD_NBUF , 16 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MRG_BBRD_NBUF ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_BBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MRG_BBRD_NBUF_LEN ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_OBRD_NBUF , 19 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MRG_OBRD_NBUF ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_OBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MRG_OBRD_NBUF_LEN ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_CR_DIS , 22 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MRG_CR_DIS ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_MRG_CTLW_CR_DIS , 23 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_MRG_CTLW_CR_DIS ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_NTLR_PAUSE_THRESH , 24 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_NTLR_PAUSE_THRESH ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_NTLR_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_NTLR_PAUSE_THRESH_LEN ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_CTLR_HP_THRESH , 26 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_CTLR_HP_THRESH ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_CTLR_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_CTLR_HP_THRESH_LEN ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_NTLW_PAUSE_THRESH , 28 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_NTLW_PAUSE_THRESH ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_NTLW_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_NTLW_PAUSE_THRESH_LEN ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_CTLW_HP_THRESH , 30 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_CTLW_HP_THRESH ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_CTLW_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_CTLW_HP_THRESH_LEN ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_PBTX_REDUCE_RTAG , 32 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_PBTX_REDUCE_RTAG ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_PBTX_DELAY_BDONE , 33 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_PBTX_DELAY_BDONE ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_PBTX_FLIP_IMIN_BIG , 34 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_PBTX_FLIP_IMIN_BIG ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_PBTX_FLIP_IMIN_LITTLE , 35 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_PBTX_FLIP_IMIN_LITTLE ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_ALU_SAFE_LATENCY , 36 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_ALU_SAFE_LATENCY ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_ALU_FLIP_ENDIAN_BIG , 37 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_ALU_FLIP_ENDIAN_BIG ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_ALU_FLIP_ENDIAN_LITTLE , 38 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_ALU_FLIP_ENDIAN_LITTLE ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_RESERVED1 , 39 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_DAT_CONFIG1_RESERVED1_LEN , 25 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED ); +REG64_FLD( PU_NPU0_SM1_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); -REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN ); -REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN ); -REG64_FLD( PU_NPU0_SM0_CONFIG1_RESERVED , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); +REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); +REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); +REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT ); +REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU0_SM0_CONFIG1_RESERVED_LEN , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_NTL0_CONFIG1_COMPRESSED_RSP_ENA , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , @@ -26906,48 +31216,159 @@ REG64_FLD( PU_NPU2_NTL0_CONFIG1_RSP_AE_ALWAYS , 6 , SH_UN SH_FLD_RSP_AE_ALWAYS ); REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED2 , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED2_LEN , 57 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_NTL0_CONFIG1_NTL_RESET , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_RESET ); +REG64_FLD( PU_NPU2_NTL0_CONFIG1_NTL_RESET_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_NTL_RESET_LEN ); +REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED3 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED3_LEN , 54 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); -REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN ); -REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN ); -REG64_FLD( PU_NPU2_SM3_CONFIG1_RESERVED , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); +REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); +REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); +REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT ); +REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU2_SM3_CONFIG1_RESERVED_LEN , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); -REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN ); -REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN ); -REG64_FLD( PU_NPU0_SM3_CONFIG1_RESERVED , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); +REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); +REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); +REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT ); +REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU0_SM3_CONFIG1_RESERVED_LEN , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); -REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN ); -REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN ); -REG64_FLD( PU_NPU2_SM2_CONFIG1_RESERVED , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); +REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); +REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); +REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT ); +REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU2_SM2_CONFIG1_RESERVED_LEN , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); +REG64_FLD( PU_NPU0_CONFIG1_MGR_CREDIT , 0 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MGR_CREDIT ); +REG64_FLD( PU_NPU0_CONFIG1_MGR_CREDIT_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MGR_CREDIT_LEN ); +REG64_FLD( PU_NPU0_CONFIG1_MRG_PBTX_NBUF , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MRG_PBTX_NBUF ); +REG64_FLD( PU_NPU0_CONFIG1_MRG_PBTX_NBUF_LEN , 3 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MRG_PBTX_NBUF_LEN ); +REG64_FLD( PU_NPU0_CONFIG1_MRG_RDBF_NBUF , 5 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MRG_RDBF_NBUF ); +REG64_FLD( PU_NPU0_CONFIG1_MRG_RDBF_NBUF_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MRG_RDBF_NBUF_LEN ); +REG64_FLD( PU_NPU0_CONFIG1_MRG_IBWR_NBUF , 9 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MRG_IBWR_NBUF ); +REG64_FLD( PU_NPU0_CONFIG1_MRG_IBWR_NBUF_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MRG_IBWR_NBUF_LEN ); +REG64_FLD( PU_NPU0_CONFIG1_MRG_IBRD_NBUF , 13 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MRG_IBRD_NBUF ); +REG64_FLD( PU_NPU0_CONFIG1_MRG_IBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MRG_IBRD_NBUF_LEN ); +REG64_FLD( PU_NPU0_CONFIG1_MRG_BBRD_NBUF , 16 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MRG_BBRD_NBUF ); +REG64_FLD( PU_NPU0_CONFIG1_MRG_BBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MRG_BBRD_NBUF_LEN ); +REG64_FLD( PU_NPU0_CONFIG1_MRG_OBRD_NBUF , 19 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MRG_OBRD_NBUF ); +REG64_FLD( PU_NPU0_CONFIG1_MRG_OBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MRG_OBRD_NBUF_LEN ); +REG64_FLD( PU_NPU0_CONFIG1_MRG_CR_DIS , 22 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MRG_CR_DIS ); +REG64_FLD( PU_NPU0_CONFIG1_MRG_CTLW_CR_DIS , 23 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_MRG_CTLW_CR_DIS ); +REG64_FLD( PU_NPU0_CONFIG1_NTLR_PAUSE_THRESH , 24 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_NTLR_PAUSE_THRESH ); +REG64_FLD( PU_NPU0_CONFIG1_NTLR_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_NTLR_PAUSE_THRESH_LEN ); +REG64_FLD( PU_NPU0_CONFIG1_CTLR_HP_THRESH , 26 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_CTLR_HP_THRESH ); +REG64_FLD( PU_NPU0_CONFIG1_CTLR_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_CTLR_HP_THRESH_LEN ); +REG64_FLD( PU_NPU0_CONFIG1_NTLW_PAUSE_THRESH , 28 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_NTLW_PAUSE_THRESH ); +REG64_FLD( PU_NPU0_CONFIG1_NTLW_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_NTLW_PAUSE_THRESH_LEN ); +REG64_FLD( PU_NPU0_CONFIG1_CTLW_HP_THRESH , 30 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_CTLW_HP_THRESH ); +REG64_FLD( PU_NPU0_CONFIG1_CTLW_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_CTLW_HP_THRESH_LEN ); +REG64_FLD( PU_NPU0_CONFIG1_PBTX_REDUCE_RTAG , 32 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_PBTX_REDUCE_RTAG ); +REG64_FLD( PU_NPU0_CONFIG1_PBTX_DELAY_BDONE , 33 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_PBTX_DELAY_BDONE ); +REG64_FLD( PU_NPU0_CONFIG1_PBTX_FLIP_IMIN_BIG , 34 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_PBTX_FLIP_IMIN_BIG ); +REG64_FLD( PU_NPU0_CONFIG1_PBTX_FLIP_IMIN_LITTLE , 35 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_PBTX_FLIP_IMIN_LITTLE ); +REG64_FLD( PU_NPU0_CONFIG1_ALU_SAFE_LATENCY , 36 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_ALU_SAFE_LATENCY ); +REG64_FLD( PU_NPU0_CONFIG1_ALU_FLIP_ENDIAN_BIG , 37 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_ALU_FLIP_ENDIAN_BIG ); +REG64_FLD( PU_NPU0_CONFIG1_ALU_FLIP_ENDIAN_LITTLE , 38 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_ALU_FLIP_ENDIAN_LITTLE ); +REG64_FLD( PU_NPU0_CONFIG1_PBTX_EARLY_AFTAG , 39 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_PBTX_EARLY_AFTAG ); +REG64_FLD( PU_NPU0_CONFIG1_RESERVED1 , 40 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_CONFIG1_RESERVED1_LEN , 24 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + REG64_FLD( PU_NPU1_CTL_CONFIG1_IDIAL , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU1_CTL_CONFIG1_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , @@ -26957,26 +31378,50 @@ REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UN SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); -REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN ); -REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN ); -REG64_FLD( PU_NPU2_SM1_CONFIG1_RESERVED , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); +REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); +REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); +REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT ); +REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU2_SM1_CONFIG1_RESERVED_LEN , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); -REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN ); -REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN ); -REG64_FLD( PU_NPU2_SM0_CONFIG1_RESERVED , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); +REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); +REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); +REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT ); +REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU2_SM0_CONFIG1_RESERVED_LEN , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG1_IDIAL , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , @@ -26998,176 +31443,108 @@ REG64_FLD( NV_CONFIG1_RSP_AE_ALWAYS , 6 , SH_UN SH_FLD_RSP_AE_ALWAYS ); REG64_FLD( NV_CONFIG1_RESERVED2 , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2 ); -REG64_FLD( NV_CONFIG1_RESERVED2_LEN , 57 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); - -REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); -REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); -REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN ); -REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN ); -REG64_FLD( PU_NPU1_SM0_CONFIG1_RESERVED , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED ); -REG64_FLD( PU_NPU1_SM0_CONFIG1_RESERVED_LEN , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED_LEN ); +REG64_FLD( NV_CONFIG1_NTL_RESET , 8 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_RESET ); +REG64_FLD( NV_CONFIG1_NTL_RESET_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_NTL_RESET_LEN ); +REG64_FLD( NV_CONFIG1_RESERVED3 , 10 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED3 ); +REG64_FLD( NV_CONFIG1_RESERVED3_LEN , 54 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED3_LEN ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MGR_CREDIT , 0 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MGR_CREDIT , 0 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MGR_CREDIT ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MGR_CREDIT_LEN , 2 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MGR_CREDIT_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MGR_CREDIT_LEN ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_PBTX_NBUF , 2 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MRG_PBTX_NBUF , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_PBTX_NBUF ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_PBTX_NBUF_LEN , 3 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MRG_PBTX_NBUF_LEN , 3 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_PBTX_NBUF_LEN ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_RDBF_NBUF , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MRG_RDBF_NBUF , 5 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_RDBF_NBUF ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_RDBF_NBUF_LEN , 4 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MRG_RDBF_NBUF_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_RDBF_NBUF_LEN ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_IBWR_NBUF , 9 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MRG_IBWR_NBUF , 9 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_IBWR_NBUF ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_IBWR_NBUF_LEN , 4 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MRG_IBWR_NBUF_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_IBWR_NBUF_LEN ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_IBRD_NBUF , 13 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MRG_IBRD_NBUF , 13 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_IBRD_NBUF ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_IBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MRG_IBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_IBRD_NBUF_LEN ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_BBRD_NBUF , 16 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MRG_BBRD_NBUF , 16 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_BBRD_NBUF ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_BBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MRG_BBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_BBRD_NBUF_LEN ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_OBRD_NBUF , 19 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MRG_OBRD_NBUF , 19 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_OBRD_NBUF ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_OBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MRG_OBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_OBRD_NBUF_LEN ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_CR_DIS , 22 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MRG_CR_DIS , 22 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_CR_DIS ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_MRG_CTLW_CR_DIS , 23 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_MRG_CTLW_CR_DIS , 23 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_CTLW_CR_DIS ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_NTLR_PAUSE_THRESH , 24 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_NTLR_PAUSE_THRESH , 24 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_NTLR_PAUSE_THRESH ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_NTLR_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_NTLR_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_NTLR_PAUSE_THRESH_LEN ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_CTLR_HP_THRESH , 26 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_CTLR_HP_THRESH , 26 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CTLR_HP_THRESH ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_CTLR_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_CTLR_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CTLR_HP_THRESH_LEN ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_NTLW_PAUSE_THRESH , 28 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_NTLW_PAUSE_THRESH , 28 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_NTLW_PAUSE_THRESH ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_NTLW_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_NTLW_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_NTLW_PAUSE_THRESH_LEN ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_CTLW_HP_THRESH , 30 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_CTLW_HP_THRESH , 30 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CTLW_HP_THRESH ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_CTLW_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_CTLW_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CTLW_HP_THRESH_LEN ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_PBTX_REDUCE_RTAG , 32 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_PBTX_REDUCE_RTAG , 32 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_PBTX_REDUCE_RTAG ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_PBTX_DELAY_BDONE , 33 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_PBTX_DELAY_BDONE , 33 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_PBTX_DELAY_BDONE ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_PBTX_FLIP_IMIN_BIG , 34 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_PBTX_FLIP_IMIN_BIG , 34 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_PBTX_FLIP_IMIN_BIG ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_PBTX_FLIP_IMIN_LITTLE , 35 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_PBTX_FLIP_IMIN_LITTLE , 35 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_PBTX_FLIP_IMIN_LITTLE ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_ALU_SAFE_LATENCY , 36 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_ALU_SAFE_LATENCY , 36 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_ALU_SAFE_LATENCY ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_ALU_FLIP_ENDIAN_BIG , 37 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_ALU_FLIP_ENDIAN_BIG , 37 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_ALU_FLIP_ENDIAN_BIG ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_ALU_FLIP_ENDIAN_LITTLE , 38 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_ALU_FLIP_ENDIAN_LITTLE , 38 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_ALU_FLIP_ENDIAN_LITTLE ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_RESERVED1 , 39 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_PBTX_EARLY_AFTAG , 39 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_PBTX_EARLY_AFTAG ); +REG64_FLD( PU_NPU2_CONFIG1_RESERVED1 , 40 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_DAT_CONFIG1_RESERVED1_LEN , 25 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_CONFIG1_RESERVED1_LEN , 24 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU1_SM2_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU1_SM2_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU1_SM3_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU1_SM3_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU2_NTL1_CONFIG2_BRICK_ENABLE , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_BRICK_ENABLE ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_RSP_CTL_CRED_SINGLE_ENA , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_RSP_CTL_CRED_SINGLE_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_CREQ_BE_128 , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_CREQ_BE_128 ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_DGD_BE_128 , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_DGD_BE_128 ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_WR_SPLIT_UT0_ENA , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_WR_SPLIT_UT0_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_WR_SPLIT_UT1_ENA , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_WR_SPLIT_UT1_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_BRICK_DEBUG_MODE , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_BRICK_DEBUG_MODE ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED1 , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_CAM256_MAX_CNT , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_CAM256_MAX_CNT ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_CAM256_MAX_CNT_LEN , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_CAM256_MAX_CNT_LEN ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_RX_PARITY_ENA , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_NDL_RX_PARITY_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_TX_PARITY_ENA , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_NDL_TX_PARITY_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_PRI_PARITY_ENA , 18 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_NDL_PRI_PARITY_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_RCV_CREDIT_OVERFLOW_ENA , 19 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_RCV_CREDIT_OVERFLOW_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_HDR_ARR_ECC_CORR_ENA , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_HDR_ARR_ECC_CORR_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_DAT_ARR_ECC_CORR_ENA , 21 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_DAT_ARR_ECC_CORR_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_TX_DATA_ECC_CORR_ENA , 22 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_TX_DATA_ECC_CORR_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED3 , 23 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_PARITY_ERROR_SUE_ENA , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_PARITY_ERROR_SUE_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_DATA_POISON_SUE_ENA , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_DATA_POISON_SUE_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_HDR_ARR_ECC_SUE_ENA , 26 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_HDR_ARR_ECC_SUE_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_DAT_ARR_ECC_SUE_ENA , 27 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_DAT_ARR_ECC_SUE_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_TX_ECC_DATA_POISON_ENA , 28 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_TX_ECC_DATA_POISON_ENA ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED4 , 29 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_RESERVED4 ); -REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED4_LEN , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , - SH_FLD_RESERVED4_LEN ); - -REG64_FLD( PU_NPU1_SM1_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU1_SM1_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU0_SM2_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU0_SM2_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU0_CTL_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU0_CTL_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU0_SM1_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU0_SM1_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU0_SM0_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU0_SM0_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_RESERVED , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED ); +REG64_FLD( PU_NPU1_SM0_CONFIG1_RESERVED_LEN , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_BRICK_ENABLE , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_BRICK_ENABLE ); @@ -27183,9 +31560,11 @@ REG64_FLD( PU_NPU2_NTL0_CONFIG2_WR_SPLIT_UT1_ENA , 5 , SH_UN SH_FLD_WR_SPLIT_UT1_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_BRICK_DEBUG_MODE , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_BRICK_DEBUG_MODE ); -REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED1 , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_CONFIG2_P9_TO_P9_MODE , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_P9_TO_P9_MODE ); +REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED1 , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_CAM256_MAX_CNT , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_CAM256_MAX_CNT ); @@ -27205,8 +31584,8 @@ REG64_FLD( PU_NPU2_NTL0_CONFIG2_DAT_ARR_ECC_CORR_ENA , 21 , SH_UN SH_FLD_DAT_ARR_ECC_CORR_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_TX_DATA_ECC_CORR_ENA , 22 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_TX_DATA_ECC_CORR_ENA ); -REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED3 , 23 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , - SH_FLD_RESERVED3 ); +REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED2 , 23 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_PARITY_ERROR_SUE_ENA , 24 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_PARITY_ERROR_SUE_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_DATA_POISON_SUE_ENA , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , @@ -27217,39 +31596,25 @@ REG64_FLD( PU_NPU2_NTL0_CONFIG2_DAT_ARR_ECC_SUE_ENA , 27 , SH_UN SH_FLD_DAT_ARR_ECC_SUE_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_TX_ECC_DATA_POISON_ENA , 28 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_TX_ECC_DATA_POISON_ENA ); -REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED4 , 29 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED3 , 29 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED3_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_RESERVED3_LEN ); +REG64_FLD( PU_NPU2_NTL0_CONFIG2_PRI_STATE_MACHINE_RESET , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , + SH_FLD_PRI_STATE_MACHINE_RESET ); +REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED4 , 33 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED4 ); -REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED4_LEN , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED4_LEN , 31 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED4_LEN ); -REG64_FLD( PU_NPU2_SM3_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU2_SM3_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU0_SM3_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU0_SM3_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU2_SM2_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU2_SM2_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - REG64_FLD( PU_NPU1_CTL_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU1_CTL_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); -REG64_FLD( PU_NPU2_SM1_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU2_SM1_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU2_SM0_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); -REG64_FLD( PU_NPU2_SM0_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , @@ -27271,9 +31636,11 @@ REG64_FLD( NV_CONFIG2_WR_SPLIT_UT1_ENA , 5 , SH_UN SH_FLD_WR_SPLIT_UT1_ENA ); REG64_FLD( NV_CONFIG2_BRICK_DEBUG_MODE , 6 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_BRICK_DEBUG_MODE ); -REG64_FLD( NV_CONFIG2_RESERVED1 , 7 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( NV_CONFIG2_P9_TO_P9_MODE , 7 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_P9_TO_P9_MODE ); +REG64_FLD( NV_CONFIG2_RESERVED1 , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( NV_CONFIG2_RESERVED1_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( NV_CONFIG2_RESERVED1_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( NV_CONFIG2_CAM256_MAX_CNT , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_CAM256_MAX_CNT ); @@ -27293,8 +31660,8 @@ REG64_FLD( NV_CONFIG2_DAT_ARR_ECC_CORR_ENA , 21 , SH_UN SH_FLD_DAT_ARR_ECC_CORR_ENA ); REG64_FLD( NV_CONFIG2_TX_DATA_ECC_CORR_ENA , 22 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_TX_DATA_ECC_CORR_ENA ); -REG64_FLD( NV_CONFIG2_RESERVED3 , 23 , SH_UNT_NV , SH_ACS_SCOM , - SH_FLD_RESERVED3 ); +REG64_FLD( NV_CONFIG2_RESERVED2 , 23 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED2 ); REG64_FLD( NV_CONFIG2_PARITY_ERROR_SUE_ENA , 24 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_PARITY_ERROR_SUE_ENA ); REG64_FLD( NV_CONFIG2_DATA_POISON_SUE_ENA , 25 , SH_UNT_NV , SH_ACS_SCOM , @@ -27305,89 +31672,91 @@ REG64_FLD( NV_CONFIG2_DAT_ARR_ECC_SUE_ENA , 27 , SH_UN SH_FLD_DAT_ARR_ECC_SUE_ENA ); REG64_FLD( NV_CONFIG2_TX_ECC_DATA_POISON_ENA , 28 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_TX_ECC_DATA_POISON_ENA ); -REG64_FLD( NV_CONFIG2_RESERVED4 , 29 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( NV_CONFIG2_RESERVED3 , 29 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED3 ); +REG64_FLD( NV_CONFIG2_RESERVED3_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_RESERVED3_LEN ); +REG64_FLD( NV_CONFIG2_PRI_STATE_MACHINE_RESET , 32 , SH_UNT_NV , SH_ACS_SCOM , + SH_FLD_PRI_STATE_MACHINE_RESET ); +REG64_FLD( NV_CONFIG2_RESERVED4 , 33 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED4 ); -REG64_FLD( NV_CONFIG2_RESERVED4_LEN , 35 , SH_UNT_NV , SH_ACS_SCOM , +REG64_FLD( NV_CONFIG2_RESERVED4_LEN , 31 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED4_LEN ); -REG64_FLD( PU_NPU1_SM0_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU1_SM0_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU1_SM2_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU1_SM2_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU1_SM3_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU1_SM3_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU2_NTL1_CONFIG3_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_CONFIG2_BRICK_ENABLE , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_BRICK_ENABLE ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_RSP_CTL_CRED_SINGLE_ENA , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RSP_CTL_CRED_SINGLE_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_CREQ_BE_128 , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_CREQ_BE_128 ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_DGD_BE_128 , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_DGD_BE_128 ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_WR_SPLIT_UT0_ENA , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_WR_SPLIT_UT0_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_WR_SPLIT_UT1_ENA , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_WR_SPLIT_UT1_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_BRICK_DEBUG_MODE , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_BRICK_DEBUG_MODE ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_P9_TO_P9_MODE , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_P9_TO_P9_MODE ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED1 , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_NTL1_CONFIG3_RESERVED1_LEN , 64 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU1_SM1_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU1_SM1_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU0_SM2_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU0_SM2_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU0_CTL_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU0_CTL_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU0_SM1_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU0_SM1_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU0_SM0_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU0_SM0_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_CAM256_MAX_CNT , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_CAM256_MAX_CNT ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_CAM256_MAX_CNT_LEN , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_CAM256_MAX_CNT_LEN ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_RX_PARITY_ENA , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NDL_RX_PARITY_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_TX_PARITY_ENA , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NDL_TX_PARITY_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_PRI_PARITY_ENA , 18 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_NDL_PRI_PARITY_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_RCV_CREDIT_OVERFLOW_ENA , 19 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RCV_CREDIT_OVERFLOW_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_HDR_ARR_ECC_CORR_ENA , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_HDR_ARR_ECC_CORR_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_DAT_ARR_ECC_CORR_ENA , 21 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_DAT_ARR_ECC_CORR_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_TX_DATA_ECC_CORR_ENA , 22 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_TX_DATA_ECC_CORR_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED2 , 23 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_PARITY_ERROR_SUE_ENA , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_PARITY_ERROR_SUE_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_DATA_POISON_SUE_ENA , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_DATA_POISON_SUE_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_HDR_ARR_ECC_SUE_ENA , 26 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_HDR_ARR_ECC_SUE_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_DAT_ARR_ECC_SUE_ENA , 27 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_DAT_ARR_ECC_SUE_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_TX_ECC_DATA_POISON_ENA , 28 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_TX_ECC_DATA_POISON_ENA ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED3 , 29 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED3 ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED3_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED3_LEN ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_PRI_STATE_MACHINE_RESET , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_PRI_STATE_MACHINE_RESET ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED4 , 33 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED4 ); +REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED4_LEN , 31 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED4_LEN ); REG64_FLD( PU_NPU2_NTL0_CONFIG3_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL0_CONFIG3_RESERVED1_LEN , 64 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_SM3_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU2_SM3_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU0_SM3_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU0_SM3_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU2_SM2_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU2_SM2_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - REG64_FLD( PU_NPU1_CTL_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU1_CTL_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); -REG64_FLD( PU_NPU2_SM1_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU2_SM1_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); - -REG64_FLD( PU_NPU2_SM0_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); -REG64_FLD( PU_NPU2_SM0_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_CTL_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , @@ -27400,10 +31769,1390 @@ REG64_FLD( NV_CONFIG3_RESERVED1 , 0 , SH_UN REG64_FLD( NV_CONFIG3_RESERVED1_LEN , 64 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU1_SM0_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL ); -REG64_FLD( PU_NPU1_SM0_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_IDIAL_LEN ); +REG64_FLD( PU_NPU2_NTL1_CONFIG3_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_NTL1_CONFIG3_RESERVED1_LEN , 64 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_WRENA ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_RDENA ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0 ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_WRENA ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_RDENA ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); + +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_WRENA ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_RDENA ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0 ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_WRENA ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_RDENA ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); + +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_WRENA ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_RDENA ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0 ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_WRENA ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_RDENA ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); + +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_WRENA ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_RDENA ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0 ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_WRENA ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_RDENA ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); + +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_WRENA ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_RDENA ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0 ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_WRENA ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_RDENA ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); + +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_WRENA ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_RDENA ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0 ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_WRENA ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_RDENA ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); + +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_WRENA ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_RDENA ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0 ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_WRENA ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_RDENA ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); + +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_WRENA ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_RDENA ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0 ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_WRENA ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_RDENA ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); + +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_WRENA ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_RDENA ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0 ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_WRENA ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_RDENA ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); + +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_WRENA ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_RDENA ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0 ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_WRENA ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_RDENA ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); + +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_WRENA ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_RDENA ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0 ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_WRENA ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_RDENA ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); + +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_WRENA ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_RDENA ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE0_MASK_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0 ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED0_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_WRENA ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_RDENA ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); + +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1 ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_WRENA ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_RDENA ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2 ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2_LEN ); + +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1 ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_WRENA ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_RDENA ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2 ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2_LEN ); + +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1 ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_WRENA ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_RDENA ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2 ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2_LEN ); + +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1 ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_WRENA ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_RDENA ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2 ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2_LEN ); + +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1 ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_WRENA ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_RDENA ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2 ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2_LEN ); + +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1 ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_WRENA ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_RDENA ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2 ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2_LEN ); + +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1 ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_WRENA ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_RDENA ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2 ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2_LEN ); + +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1 ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_WRENA ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_RDENA ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2 ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2_LEN ); + +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1 ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_WRENA ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_RDENA ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2 ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2_LEN ); + +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1 ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_WRENA ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_RDENA ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2 ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2_LEN ); + +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1 ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_WRENA ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_RDENA ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2 ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2_LEN ); + +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE1_MASK_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1 ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_WRENA ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_RDENA ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE2_MASK_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2 ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED2_LEN ); + +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_INJ ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_PR_DMA_INJ ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_DMA_PR_W ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_ADD ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_AND ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_OR ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_XOR ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_ADD ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_AND ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_OR ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_XOR ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_WRENA ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_RDENA ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK_LEN ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3 ); +REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3_LEN ); + +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_INJ ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_PR_DMA_INJ ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_DMA_PR_W ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_ADD ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_AND ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_OR ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_XOR ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_ADD ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_AND ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_OR ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_XOR ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_WRENA ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_RDENA ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK_LEN ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3 ); +REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3_LEN ); + +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_INJ ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_PR_DMA_INJ ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_DMA_PR_W ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_ADD ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_AND ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_OR ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_XOR ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_ADD ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_AND ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_OR ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_XOR ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_WRENA ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_RDENA ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK_LEN ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3 ); +REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3_LEN ); + +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_INJ ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_PR_DMA_INJ ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_DMA_PR_W ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_ADD ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_AND ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_OR ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_XOR ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_ADD ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_AND ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_OR ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_XOR ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_WRENA ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_RDENA ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK_LEN ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3 ); +REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3_LEN ); + +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_INJ ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_PR_DMA_INJ ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_DMA_PR_W ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_ADD ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_AND ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_OR ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_XOR ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_ADD ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_AND ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_OR ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_XOR ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_WRENA ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_RDENA ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK_LEN ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3 ); +REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3_LEN ); + +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_INJ ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_PR_DMA_INJ ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_DMA_PR_W ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_ADD ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_AND ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_OR ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_XOR ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_ADD ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_AND ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_OR ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_XOR ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_WRENA ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_RDENA ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK_LEN ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3 ); +REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3_LEN ); + +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_INJ ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_PR_DMA_INJ ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_DMA_PR_W ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_ADD ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_AND ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_OR ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_XOR ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_ADD ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_AND ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_OR ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_XOR ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_WRENA ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_RDENA ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK_LEN ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3 ); +REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3_LEN ); + +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_INJ ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_PR_DMA_INJ ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_DMA_PR_W ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_ADD ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_AND ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_OR ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_XOR ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_ADD ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_AND ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_OR ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_XOR ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_WRENA ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_RDENA ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK_LEN ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3 ); +REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3_LEN ); + +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_INJ ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_PR_DMA_INJ ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_DMA_PR_W ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_ADD ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_AND ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_OR ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_XOR ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_ADD ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_AND ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_OR ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_XOR ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_WRENA ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_RDENA ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK_LEN ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3 ); +REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3_LEN ); + +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_INJ ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_PR_DMA_INJ ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_DMA_PR_W ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_ADD ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_AND ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_OR ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_XOR ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_ADD ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_AND ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_OR ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_XOR ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_WRENA ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_RDENA ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK_LEN ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3 ); +REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3_LEN ); + +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_INJ ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_PR_DMA_INJ ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_DMA_PR_W ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_ADD ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_AND ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_OR ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_XOR ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_ADD ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_AND ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_OR ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_XOR ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_WRENA ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_RDENA ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK_LEN ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3 ); +REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3_LEN ); + +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_DMA_INJ ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_PR_DMA_INJ ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_DMA_PR_W ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_ADD ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_AND ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_OR ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMW_XOR ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_ADD ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_AND ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_OR ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_XOR ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_WRENA ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_RDENA ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_SOURCE3_MASK_LEN ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3 ); +REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RELAXED_RESERVED3_LEN ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHSTART_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_0 ); @@ -27443,8 +33192,10 @@ REG64_FLD( PU_CONTROL_REGISTER_B_ECCCHK_DISABLE_0 , 28 , SH_UN SH_FLD_ECCCHK_DISABLE_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_UNUSED_0 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_0 ); -REG64_FLD( PU_CONTROL_REGISTER_B_UNUSED_0_LEN , 3 , SH_UNT , SH_ACS_SCOM , - SH_FLD_UNUSED_0_LEN ); +REG64_FLD( PU_CONTROL_REGISTER_B_FAST_MODE_INTERRUPT_STERRING_BITS_0 , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_0 ); +REG64_FLD( PU_CONTROL_REGISTER_B_FAST_MODE_INTERRUPT_STERRING_BITS_0_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_0_LEN ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_1_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -27500,8 +33251,10 @@ REG64_FLD( PU_CONTROL_REGISTER_C_ECCCHK_DISABLE_1 , 28 , SH_UN SH_FLD_ECCCHK_DISABLE_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_UNUSED_1 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_1 ); -REG64_FLD( PU_CONTROL_REGISTER_C_UNUSED_1_LEN , 3 , SH_UNT , SH_ACS_SCOM , - SH_FLD_UNUSED_1_LEN ); +REG64_FLD( PU_CONTROL_REGISTER_C_FAST_MODE_INTERRUPT_STERRING_BITS_1 , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_1 ); +REG64_FLD( PU_CONTROL_REGISTER_C_FAST_MODE_INTERRUPT_STERRING_BITS_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_1_LEN ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_1_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -27557,8 +33310,10 @@ REG64_FLD( PU_CONTROL_REGISTER_D_ECCCHK_DISABLE_2 , 28 , SH_UN SH_FLD_ECCCHK_DISABLE_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_UNUSED_2 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); -REG64_FLD( PU_CONTROL_REGISTER_D_UNUSED_2_LEN , 3 , SH_UNT , SH_ACS_SCOM , - SH_FLD_UNUSED_2_LEN ); +REG64_FLD( PU_CONTROL_REGISTER_D_FAST_MODE_INTERRUPT_STERRING_BITS_2 , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_2 ); +REG64_FLD( PU_CONTROL_REGISTER_D_FAST_MODE_INTERRUPT_STERRING_BITS_2_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_2_LEN ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_1_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -27614,8 +33369,10 @@ REG64_FLD( PU_CONTROL_REGISTER_E_ECCCHK_DISABLE_3 , 28 , SH_UN SH_FLD_ECCCHK_DISABLE_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_UNUSED_3 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_3 ); -REG64_FLD( PU_CONTROL_REGISTER_E_UNUSED_3_LEN , 3 , SH_UNT , SH_ACS_SCOM , - SH_FLD_UNUSED_3_LEN ); +REG64_FLD( PU_CONTROL_REGISTER_E_FAST_MODE_INTERRUPT_STERRING_BITS_3 , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_3 ); +REG64_FLD( PU_CONTROL_REGISTER_E_FAST_MODE_INTERRUPT_STERRING_BITS_3_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_3_LEN ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_1_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -27633,29 +33390,398 @@ REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_4_3 , 56 , SH_UN REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_4_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_4_3_LEN ); -REG64_FLD( PEC_STACK2_CQSTAT_REG_PE_INBOUND_ACTIVE , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RO , - SH_FLD_PE_INBOUND_ACTIVE ); -REG64_FLD( PEC_STACK2_CQSTAT_REG_PE_OUTBOUND_ACTIVE , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RO , - SH_FLD_PE_OUTBOUND_ACTIVE ); - -REG64_FLD( PEC_STACK1_CQSTAT_REG_PE_INBOUND_ACTIVE , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RO , - SH_FLD_PE_INBOUND_ACTIVE ); -REG64_FLD( PEC_STACK1_CQSTAT_REG_PE_OUTBOUND_ACTIVE , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RO , - SH_FLD_PE_OUTBOUND_ACTIVE ); +REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_MISC_PROBE0_SEL_DC ); +REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_6C , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_6C ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_7C , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_7C ); +REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_MISC_PROBE1_SEL_DC ); +REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_14C , 14 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_14C ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_15C , 15 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_15C ); +REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC , 16 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_MISC_PROBE2_SEL_DC ); +REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_22C , 22 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_22C ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_23C , 23 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_23C ); +REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC , 24 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_MISC_PROBE3_SEL_DC ); +REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_30C , 30 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_30C ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_31C , 31 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_31C ); +REG64_FLD( PEC_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC , 32 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC ); +REG64_FLD( PEC_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC , 33 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_CC_SCAN_PROTECT_DC ); +REG64_FLD( PEC_CPLT_CONF0_CTRL_CC_SDIS_DC_N , 34 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_CC_SDIS_DC_N ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_35C , 35 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_TEST_CONTROL_35C ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_36C , 36 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_TEST_CONTROL_36C ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_37C , 37 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_TEST_CONTROL_37C ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_38C , 38 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_TEST_CONTROL_38C ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_39C , 39 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_TEST_CONTROL_39C ); +REG64_FLD( PEC_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC , 40 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC ); +REG64_FLD( PEC_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC , 41 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC ); +REG64_FLD( PEC_CPLT_CONF0_ERR501 , 42 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_ERR501 ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_43C , 43 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_43C ); +REG64_FLD( PEC_CPLT_CONF0_FREE_USAGE_44C , 44 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_44C ); +REG64_FLD( PEC_CPLT_CONF0_FREE_USAGE_45C , 45 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_45C ); +REG64_FLD( PEC_CPLT_CONF0_FREE_USAGE_46C , 46 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_46C ); +REG64_FLD( PEC_CPLT_CONF0_FREE_USAGE_47C , 47 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_47C ); +REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_GROUP_ID_DC , 48 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_UNIT_GROUP_ID_DC ); +REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_UNIT_GROUP_ID_DC_LEN ); +REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_CHIP_ID_DC , 52 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_UNIT_CHIP_ID_DC ); +REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_UNIT_CHIP_ID_DC_LEN ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_55C , 55 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_ID_55C ); +REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_SYS_ID_DC , 56 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_UNIT_SYS_ID_DC ); +REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_UNIT_SYS_ID_DC_LEN ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_61C , 61 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_ID_61C ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_62C , 62 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_ID_62C ); +REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_63C , 63 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_ID_63C ); + +REG64_FLD( PEC_CPLT_CONF1_UNUSED_0D , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_0D ); +REG64_FLD( PEC_CPLT_CONF1_UNUSED_1D , 1 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_1D ); +REG64_FLD( PEC_CPLT_CONF1_UNUSED_2D , 2 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_2D ); +REG64_FLD( PEC_CPLT_CONF1_UNUSED_3D , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_3D ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_IOVALID , 4 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_IOVALID ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_5D , 5 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_5D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_6D , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_6D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_7D , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_7D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_8D , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_8D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_9D , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_9D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_10D , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_10D ); +REG64_FLD( PEC_CPLT_CONF1_IOVALID_11D , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_IOVALID_11D ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_SWAP_DC , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_SWAP_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_LANE_CFG_DC , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_LANE_CFG_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_LANE_CFG_DC_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_LANE_CFG_DC_LEN ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_RATIO_OVERRIDE , 15 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_RATIO_OVERRIDE ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_RATIO_DC , 16 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_RATIO_DC ); +REG64_FLD( PEC_CPLT_CONF1_TC_PCI0_RATIO_DC_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PCI0_RATIO_DC_LEN ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_19D , 19 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_19D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_20D , 20 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_20D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_21D , 21 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_21D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_22D , 22 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_22D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_23D , 23 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_23D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_24D , 24 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_24D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_25D , 25 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_25D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_26D , 26 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_26D ); +REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_27D , 27 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_27D ); +REG64_FLD( PEC_CPLT_CONF1_TC_IOP_SYS_RESET_PCS , 28 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_IOP_SYS_RESET_PCS ); +REG64_FLD( PEC_CPLT_CONF1_TC_IOP_SYS_RESET_PMA , 29 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_IOP_SYS_RESET_PMA ); +REG64_FLD( PEC_CPLT_CONF1_TC_IOP_HSSPORWREN , 30 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_IOP_HSSPORWREN ); +REG64_FLD( PEC_CPLT_CONF1_TC_IOP_HSSPCLKOUTEN , 31 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_IOP_HSSPCLKOUTEN ); + +REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC ); +REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC , 1 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC ); +REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC , 2 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_CC_FLUSHMODE_INH_DC ); +REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_CC_FORCE_ALIGN_DC ); +REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC , 4 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_UNIT_ARY_WRT_THRU_DC ); +REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_AVP_MODE , 5 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_UNIT_AVP_MODE ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_6A , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_6A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_7A , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_7A ); +REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_9A , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_9A ); +REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC ); +REG64_FLD( PEC_CPLT_CTRL0_RESERVED_11A , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_11A ); +REG64_FLD( PEC_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_SKIT_MODE_BIST_DC ); +REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC ); +REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC , 14 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC ); +REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC , 15 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC ); +REG64_FLD( PEC_CPLT_CTRL0_TC_NBTI_HDR_ENABLE_OVR_DC , 16 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC ); +REG64_FLD( PEC_CPLT_CTRL0_TC_NBTI_PROBE_GATE_DC , 17 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_NBTI_PROBE_GATE_DC ); +REG64_FLD( PEC_CPLT_CTRL0_RESERVED_18A , 18 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_18A ); +REG64_FLD( PEC_CPLT_CTRL0_RESERVED_19A , 19 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_19A ); +REG64_FLD( PEC_CPLT_CTRL0_TC_PSRO_SEL_DC , 20 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PSRO_SEL_DC ); +REG64_FLD( PEC_CPLT_CTRL0_TC_PSRO_SEL_DC_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PSRO_SEL_DC_LEN ); +REG64_FLD( PEC_CPLT_CTRL0_TC_BSC_WRAPSEL_DC , 28 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_BSC_WRAPSEL_DC ); +REG64_FLD( PEC_CPLT_CTRL0_TC_BSC_INTMODE_DC , 29 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_BSC_INTMODE_DC ); +REG64_FLD( PEC_CPLT_CTRL0_TC_BSC_INV_DC , 30 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_BSC_INV_DC ); +REG64_FLD( PEC_CPLT_CTRL0_TC_BSC_EXTMODE_DC , 31 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_BSC_EXTMODE_DC ); +REG64_FLD( PEC_CPLT_CTRL0_TC_REFCLK_DRVR_EN_DC , 32 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REFCLK_DRVR_EN_DC ); +REG64_FLD( PEC_CPLT_CTRL0_RESERVED_33A , 33 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_33A ); +REG64_FLD( PEC_CPLT_CTRL0_RESERVED_34A , 34 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_34A ); +REG64_FLD( PEC_CPLT_CTRL0_RESERVED_35A , 35 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_35A ); +REG64_FLD( PEC_CPLT_CTRL0_TC_OELCC_EDGE_DELAYED_DC , 36 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_OELCC_EDGE_DELAYED_DC ); +REG64_FLD( PEC_CPLT_CTRL0_TC_OELCC_ALIGN_FLUSH_DC , 37 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_OELCC_ALIGN_FLUSH_DC ); +REG64_FLD( PEC_CPLT_CTRL0_RESERVED_38A , 38 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_38A ); +REG64_FLD( PEC_CPLT_CTRL0_RESERVED_39A , 39 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_39A ); +REG64_FLD( PEC_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC , 40 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_MISC_CLKDIV_SEL_DC ); +REG64_FLD( PEC_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN ); +REG64_FLD( PEC_CPLT_CTRL0_RESERVED_42A , 42 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_42A ); +REG64_FLD( PEC_CPLT_CTRL0_RESERVED_43A , 43 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED_43A ); +REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_DCTEST_DC , 44 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_CC_DCTEST_DC ); +REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_OTP_PRGMODE_DC , 45 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_CC_OTP_PRGMODE_DC ); +REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC , 46 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_CC_SSS_CALIBRATE_DC ); +REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC , 47 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_CTRL_CC_PIN_LBIST_DC ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_48A , 48 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_48A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_49A , 49 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_49A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_50A , 50 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_50A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_51A , 51 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_51A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_52A , 52 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_52A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_53A , 53 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_53A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_54A , 54 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_54A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_55A , 55 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_55A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_56A , 56 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_56A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_57A , 57 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_57A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_58A , 58 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_58A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_59A , 59 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_59A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_60A , 60 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_60A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_61A , 61 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_61A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_62A , 62 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_62A ); +REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_63A , 63 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_FREE_USAGE_63A ); + +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_0B , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_0B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_1B , 1 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_1B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_2B , 2 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_2B ); +REG64_FLD( PEC_CPLT_CTRL1_TC_VITL_REGION_FENCE , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_VITL_REGION_FENCE ); +REG64_FLD( PEC_CPLT_CTRL1_TC_PERV_REGION_FENCE , 4 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_PERV_REGION_FENCE ); +REG64_FLD( PEC_CPLT_CTRL1_TC_REGION1_FENCE , 5 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION1_FENCE ); +REG64_FLD( PEC_CPLT_CTRL1_TC_REGION2_FENCE , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_REGION2_FENCE ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_7B , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_7B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_8B , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_8B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_9B , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_9B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_10B , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_10B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_11B , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_11B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_12B , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_12B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_13B , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_13B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_14B , 14 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_14B ); +REG64_FLD( PEC_CPLT_CTRL1_RESERVED , 15 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_RESERVED ); +REG64_FLD( PEC_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE , 16 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_17B , 17 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_17B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_18B , 18 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_18B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_19B , 19 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_19B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_20B , 20 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_20B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_21B , 21 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_21B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_22B , 22 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_22B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_23B , 23 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_23B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_24B , 24 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_24B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_25B , 25 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_25B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_26B , 26 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_26B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_27B , 27 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_27B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_28B , 28 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_28B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_29B , 29 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_29B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_30B , 30 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_30B ); +REG64_FLD( PEC_CPLT_CTRL1_UNUSED_31B , 31 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, + SH_FLD_UNUSED_31B ); + +REG64_FLD( PEC_CPLT_MASK0_CPLTMASK0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CPLTMASK0 ); +REG64_FLD( PEC_CPLT_MASK0_CPLTMASK0_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CPLTMASK0_LEN ); + +REG64_FLD( PEC_CPLT_STAT0_SRAM_ABIST_DONE_DC , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SRAM_ABIST_DONE_DC ); +REG64_FLD( PEC_CPLT_STAT0_DRAM_ABIST_DONE_DC , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DRAM_ABIST_DONE_DC ); +REG64_FLD( PEC_CPLT_STAT0_RESERVED_2E , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESERVED_2E ); +REG64_FLD( PEC_CPLT_STAT0_RESERVED_3E , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESERVED_3E ); +REG64_FLD( PEC_CPLT_STAT0_TC_DIAG_PORT0_OUT , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TC_DIAG_PORT0_OUT ); +REG64_FLD( PEC_CPLT_STAT0_TC_DIAG_PORT1_OUT , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TC_DIAG_PORT1_OUT ); +REG64_FLD( PEC_CPLT_STAT0_RESERVED_6E , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESERVED_6E ); +REG64_FLD( PEC_CPLT_STAT0_PLL_DESTOUT , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PLL_DESTOUT ); +REG64_FLD( PEC_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CC_CTRL_OPCG_DONE_DC ); +REG64_FLD( PEC_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC ); +REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_10E , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREE_USAGE_10E ); +REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_11E , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREE_USAGE_11E ); +REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_12E , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREE_USAGE_12E ); +REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_13E , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREE_USAGE_13E ); +REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_14E , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREE_USAGE_14E ); +REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_15E , 15 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREE_USAGE_15E ); +REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_16E , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREE_USAGE_16E ); +REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_17E , 17 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREE_USAGE_17E ); +REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_18E , 18 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREE_USAGE_18E ); +REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_19E , 19 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREE_USAGE_19E ); +REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_20E , 20 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREE_USAGE_20E ); +REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_21E , 21 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREE_USAGE_21E ); +REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_22E , 22 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREE_USAGE_22E ); +REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_23E , 23 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREE_USAGE_23E ); REG64_FLD( PHB_CQSTAT_REG_PE_INBOUND_ACTIVE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RO , SH_FLD_PE_INBOUND_ACTIVE ); REG64_FLD( PHB_CQSTAT_REG_PE_OUTBOUND_ACTIVE , 1 , SH_UNT_PHB , SH_ACS_SCOM_RO , SH_FLD_PE_OUTBOUND_ACTIVE ); -REG64_FLD( PEC_STACK0_CQSTAT_REG_PE_INBOUND_ACTIVE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RO , - SH_FLD_PE_INBOUND_ACTIVE ); -REG64_FLD( PEC_STACK0_CQSTAT_REG_PE_OUTBOUND_ACTIVE , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RO , - SH_FLD_PE_OUTBOUND_ACTIVE ); - -REG64_FLD( PU_IOPPE_CSAR_SRAM_ADDRESS , 16 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RW , +REG64_FLD( PU_CSAR_SRAM_ADDRESS , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_ADDRESS ); -REG64_FLD( PU_IOPPE_CSAR_SRAM_ADDRESS_LEN , 13 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RW , +REG64_FLD( PU_CSAR_SRAM_ADDRESS_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_ADDRESS_LEN ); REG64_FLD( PU_IOPPE_CSCR_SRAM_ACCESS_MODE , 0 , SH_UNT_PU_IOPPE , SH_ACS_SCOM2_OR , @@ -27679,11 +33805,446 @@ REG64_FLD( PU_IOPPE_CSCR_SRAM_SCRUB_INDEX , 47 , SH_UN REG64_FLD( PU_IOPPE_CSCR_SRAM_SCRUB_INDEX_LEN , 13 , SH_UNT_PU_IOPPE , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_INDEX_LEN ); -REG64_FLD( PU_IOPPE_CSDR_SRAM_DATA , 0 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RW , +REG64_FLD( PU_CSCR_SRAM_ACCESS_MODE , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_SRAM_ACCESS_MODE ); +REG64_FLD( PU_CSCR_SRAM_SCRUB_ENABLE , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_SRAM_SCRUB_ENABLE ); +REG64_FLD( PU_CSCR_ECC_CORRECT_DIS , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ECC_CORRECT_DIS ); +REG64_FLD( PU_CSCR_ECC_DETECT_DIS , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ECC_DETECT_DIS ); +REG64_FLD( PU_CSCR_ECC_INJECT_TYPE , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ECC_INJECT_TYPE ); +REG64_FLD( PU_CSCR_ECC_INJECT_ERR , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ECC_INJECT_ERR ); +REG64_FLD( PU_CSCR_SPARE_6_7 , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_SPARE_6_7 ); +REG64_FLD( PU_CSCR_SPARE_6_7_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_SPARE_6_7_LEN ); +REG64_FLD( PU_CSCR_SRAM_SCRUB_INDEX , 47 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_SRAM_SCRUB_INDEX ); +REG64_FLD( PU_CSCR_SRAM_SCRUB_INDEX_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_SRAM_SCRUB_INDEX_LEN ); + +REG64_FLD( PU_CSDR_SRAM_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_DATA ); -REG64_FLD( PU_IOPPE_CSDR_SRAM_DATA_LEN , 64 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RW , +REG64_FLD( PU_CSDR_SRAM_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_DATA_LEN ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_SM_MMIO0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_SM_MMIO0 ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_SM_MMIO1 , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_SM_MMIO1 ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_SM_MMIO2 , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_SM_MMIO2 ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_SM_MMIO3 , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_SM_MMIO3 ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MRBGP , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MRBSP , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_FENCE0 , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_FENCE1 , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_LPCTH , 20 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_LPCTH ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_LPCTH_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_LPCTH_LEN ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBM_STATE , 22 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_PBM_STATE ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBM_STATE_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_PBM_STATE_LEN ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_BRK0_RLX , 27 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_BRK0_RLX ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_BRK1_RLX , 28 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_BRK1_RLX ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_BRK0_NVL , 29 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_BRK0_NVL ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_BRK1_NVL , 30 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_BRK1_NVL ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_ATS_SYNC , 31 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_ATS_SYNC ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NMMU , 32 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NMMU ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBLN , 33 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBNNG , 34 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBRNVG , 35 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVREQ0 , 36 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NVREQ0 ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVDGD0 , 37 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NVDGD0 ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVREQ1 , 38 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NVREQ1 ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVDGD1 , 39 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NVDGD1 ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_ATSREQ , 40 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_ATSREQ ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MMIO , 41 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBRS , 42 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_PBRS ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVRS0 , 43 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NVRS0 ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVRS1 , 44 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NVRS1 ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_XARS , 45 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_XARS ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_ATRR , 46 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_ATRR ); +REG64_FLD( PU_NPU1_CTL_CTL_STATUS_RESERVED1 , 47 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); + +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_SM_MMIO0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_SM_MMIO0 ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_SM_MMIO1 , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_SM_MMIO1 ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_SM_MMIO2 , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_SM_MMIO2 ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_SM_MMIO3 , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_SM_MMIO3 ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MRBGP , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MRBSP , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_FENCE0 , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_FENCE1 , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_LPCTH , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_LPCTH ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_LPCTH_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_LPCTH_LEN ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBM_STATE , 22 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PBM_STATE ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBM_STATE_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PBM_STATE_LEN ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_BRK0_RLX , 27 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_BRK0_RLX ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_BRK1_RLX , 28 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_BRK1_RLX ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_BRK0_NVL , 29 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_BRK0_NVL ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_BRK1_NVL , 30 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_BRK1_NVL ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_ATS_SYNC , 31 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_ATS_SYNC ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NMMU , 32 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NMMU ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBLN , 33 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBNNG , 34 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBRNVG , 35 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVREQ0 , 36 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NVREQ0 ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVDGD0 , 37 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NVDGD0 ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVREQ1 , 38 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NVREQ1 ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVDGD1 , 39 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NVDGD1 ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_ATSREQ , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_ATSREQ ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MMIO , 41 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBRS , 42 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PBRS ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVRS0 , 43 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NVRS0 ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVRS1 , 44 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NVRS1 ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_XARS , 45 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_XARS ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_ATRR , 46 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_ATRR ); +REG64_FLD( PU_NPU0_CTL_CTL_STATUS_RESERVED1 , 47 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); + +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_SM_MMIO0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_SM_MMIO0 ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_SM_MMIO1 , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_SM_MMIO1 ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_SM_MMIO2 , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_SM_MMIO2 ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_SM_MMIO3 , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_SM_MMIO3 ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MRBGP , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MRBSP , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_FENCE0 , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_FENCE1 , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_LPCTH , 20 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_LPCTH ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_LPCTH_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_LPCTH_LEN ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBM_STATE , 22 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_PBM_STATE ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBM_STATE_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_PBM_STATE_LEN ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_BRK0_RLX , 27 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_BRK0_RLX ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_BRK1_RLX , 28 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_BRK1_RLX ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_BRK0_NVL , 29 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_BRK0_NVL ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_BRK1_NVL , 30 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_BRK1_NVL ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_ATS_SYNC , 31 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_ATS_SYNC ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NMMU , 32 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NMMU ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBLN , 33 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBNNG , 34 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBRNVG , 35 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVREQ0 , 36 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NVREQ0 ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVDGD0 , 37 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NVDGD0 ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVREQ1 , 38 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NVREQ1 ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVDGD1 , 39 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NVDGD1 ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_ATSREQ , 40 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_ATSREQ ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MMIO , 41 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBRS , 42 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_PBRS ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVRS0 , 43 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NVRS0 ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVRS1 , 44 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NVRS1 ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_XARS , 45 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_XARS ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_ATRR , 46 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_ATRR ); +REG64_FLD( PU_NPU2_CTL_CTL_STATUS_RESERVED1 , 47 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); + +REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ID ); +REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ID_LEN ); +REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACTIVITY ); +REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACTIVITY_LEN ); + +REG64_FLD( PEC_CTRL_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_READ_ENABLE ); +REG64_FLD( PEC_CTRL_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WRITE_ENABLE ); + +REG64_FLD( CAPP_CXA_SNP_ARRAY_ADDR_REG_ADDRESS , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ADDRESS ); +REG64_FLD( CAPP_CXA_SNP_ARRAY_ADDR_REG_ADDRESS_LEN , 15 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ADDRESS_LEN ); + +REG64_FLD( CAPP_CXA_SNP_ARRAY_READ_REG_DATA , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA ); +REG64_FLD( CAPP_CXA_SNP_ARRAY_READ_REG_DATA_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_LEN ); + +REG64_FLD( CAPP_CXA_SNP_ARRAY_WRITE_REG_DATA , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA ); +REG64_FLD( CAPP_CXA_SNP_ARRAY_WRITE_REG_DATA_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_LEN ); + +REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG0_0_CANNED_0 , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_0_CANNED_0 ); +REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG0_0_CANNED_0_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_0_CANNED_0_LEN ); +REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG0_0_CANNED_1 , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_0_CANNED_1 ); +REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG0_0_CANNED_1_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_0_CANNED_1_LEN ); + +REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG1_1_CANNED_0 , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_1_CANNED_0 ); +REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG1_1_CANNED_0_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_1_CANNED_0_LEN ); +REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG1_1_CANNED_1 , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_1_CANNED_1 ); +REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG1_1_CANNED_1_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_1_CANNED_1_LEN ); + +REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG2_2_CANNED_0 , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_2_CANNED_0 ); +REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG2_2_CANNED_0_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_2_CANNED_0_LEN ); +REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG2_2_CANNED_1 , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_2_CANNED_1 ); +REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG2_2_CANNED_1_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_2_CANNED_1_LEN ); + +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_ENABLE_TTYPE_DECODE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ENABLE_TTYPE_DECODE ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_PRECISE_DIR_SIZE , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PRECISE_DIR_SIZE ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_PRECISE_DIR_SIZE_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PRECISE_DIR_SIZE_LEN ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_COARSE_DIR_ENABLE , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COARSE_DIR_ENABLE ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_COARSE_DIR_SECTORS , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COARSE_DIR_SECTORS ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_MCD_CHICKEN_SWITCH , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_MCD_CHICKEN_SWITCH ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_BHR_DIR_STATE , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BHR_DIR_STATE ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_BHR_DIR_STATE_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BHR_DIR_STATE_LEN ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_LPC_MODE , 12 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPC_MODE ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_LPC_MODE_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LPC_MODE_LEN ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_CT_COMPARE_VECTOR , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CT_COMPARE_VECTOR ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_CT_COMPARE_VECTOR_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CT_COMPARE_VECTOR_LEN ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_PHB_FILTER_CNTL , 38 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PHB_FILTER_CNTL ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_PHB_FILTER_CNTL_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PHB_FILTER_CNTL_LEN ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_EPOCH_TEST_VECTOR , 40 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_EPOCH_TEST_VECTOR ); +REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_EPOCH_TEST_VECTOR_LEN , 24 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_EPOCH_TEST_VECTOR_LEN ); + +REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_MODE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_READ_EPSILON_MODE ); +REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER0 , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_READ_EPSILON_TIER0 ); +REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER0_LEN , 9 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_READ_EPSILON_TIER0_LEN ); +REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER1 , 15 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_READ_EPSILON_TIER1 ); +REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER1_LEN , 9 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_READ_EPSILON_TIER1_LEN ); +REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER2 , 25 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_READ_EPSILON_TIER2 ); +REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER2_LEN , 11 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_READ_EPSILON_TIER2_LEN ); +REG64_FLD( CAPP_CXA_SNP_CNTL_REG_ADDRESS_PIPELINE_MASTERWAIT_COUNT , 45 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT ); +REG64_FLD( CAPP_CXA_SNP_CNTL_REG_ADDRESS_PIPELINE_MASTERWAIT_COUNT_LEN , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT_LEN ); +REG64_FLD( CAPP_CXA_SNP_CNTL_REG_DATA_HANG_POLL_SCALE , 48 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_HANG_POLL_SCALE ); +REG64_FLD( CAPP_CXA_SNP_CNTL_REG_DATA_HANG_POLL_SCALE_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_DATA_HANG_POLL_SCALE_LEN ); + +REG64_FLD( CAPP_CXA_SNP_ERROR_REPORT_REG_C_ERR_RPT_HOLD_DATA , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_C_ERR_RPT_HOLD_DATA ); +REG64_FLD( CAPP_CXA_SNP_ERROR_REPORT_REG_C_ERR_RPT_HOLD_DATA_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_C_ERR_RPT_HOLD_DATA_LEN ); + +REG64_FLD( CAPP_CXA_SNP_PHB_TTAG_FILTER_REG_FILTER , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FILTER ); +REG64_FLD( CAPP_CXA_SNP_PHB_TTAG_FILTER_REG_FILTER_LEN , 48 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FILTER_LEN ); + +REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_GROUP , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_GROUP ); +REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_GROUP_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_GROUP_LEN ); +REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_EVENT , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FSMJ_EVENT ); +REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_EVENT_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FSMJ_EVENT_LEN ); +REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_FSM , 14 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FSMJ_FSM ); +REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_FSM_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FSMJ_FSM_LEN ); + +REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_EN , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_EN ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_SIZE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SIZE ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_SIZE_LEN , 18 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SIZE_LEN ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_STARTING_ADDRESS , 19 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_STARTING_ADDRESS ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_STARTING_ADDRESS_LEN , 27 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_STARTING_ADDRESS_LEN ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_SYSTEM , 50 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SYSTEM ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_SYSTEM_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SYSTEM_LEN ); + +REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_EN , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BAR1_EN ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_SIZE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BAR1_SIZE ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_SIZE_LEN , 18 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BAR1_SIZE_LEN ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_STARTING_ADDRESS , 19 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BAR1_STARTING_ADDRESS ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_STARTING_ADDRESS_LEN , 27 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BAR1_STARTING_ADDRESS_LEN ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_SYSTEM , 50 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BAR1_SYSTEM ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_SYSTEM_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BAR1_SYSTEM_LEN ); + +REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_EN , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_EN ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_MS_GROUP_CHIP , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_MS_GROUP_CHIP ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_MS_GROUP_CHIP_LEN , 9 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_MS_GROUP_CHIP_LEN ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_STARTING_ADDRESS , 22 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_STARTING_ADDRESS ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_STARTING_ADDRESS_LEN , 31 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_STARTING_ADDRESS_LEN ); + +REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_EN , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BAR1_EN ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_MS_GROUP_CHIP , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BAR1_MS_GROUP_CHIP ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_MS_GROUP_CHIP_LEN , 9 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BAR1_MS_GROUP_CHIP_LEN ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_STARTING_ADDRESS , 22 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BAR1_STARTING_ADDRESS ); +REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_STARTING_ADDRESS_LEN , 31 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BAR1_STARTING_ADDRESS_LEN ); + REG64_FLD( PU_DATA0TO7_REGISTER_B_PIB_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_0 ); REG64_FLD( PU_DATA0TO7_REGISTER_B_PIB_0_LEN , 64 , SH_UNT , SH_ACS_SCOM , @@ -27761,8 +34322,1825 @@ REG64_FLD( PU_DATA_REGISTER_OTP_LEN , 64 , SH_UN REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC ); -REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_LEN , 64 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_LEN , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_LEN ); +REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_LENGTH , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_LENGTH ); +REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_LENGTH_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_LENGTH_LEN ); +REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_RSVD , 26 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_RSVD ); +REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_RSVD_LEN , 38 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_RSVD_LEN ); + +REG64_FLD( PEC_DBG_CBS_CC_RESET_EP , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_EP ); +REG64_FLD( PEC_DBG_CBS_CC_OPCG_IP , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_OPCG_IP ); +REG64_FLD( PEC_DBG_CBS_CC_VITL_CLKOFF , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_VITL_CLKOFF ); +REG64_FLD( PEC_DBG_CBS_CC_TEST_ENABLE , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TEST_ENABLE ); +REG64_FLD( PEC_DBG_CBS_CC_REQ , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_REQ ); +REG64_FLD( PEC_DBG_CBS_CC_CMD , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CMD ); +REG64_FLD( PEC_DBG_CBS_CC_CMD_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CMD_LEN ); +REG64_FLD( PEC_DBG_CBS_CC_STATE , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATE ); +REG64_FLD( PEC_DBG_CBS_CC_STATE_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STATE_LEN ); +REG64_FLD( PEC_DBG_CBS_CC_SECURITY_DEBUG_MODE , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SECURITY_DEBUG_MODE ); +REG64_FLD( PEC_DBG_CBS_CC_PROTOCOL_ERROR , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PROTOCOL_ERROR ); +REG64_FLD( PEC_DBG_CBS_CC_PCB_IDLE , 15 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_IDLE ); +REG64_FLD( PEC_DBG_CBS_CC_CURRENT_OPCG_MODE , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CURRENT_OPCG_MODE ); +REG64_FLD( PEC_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CURRENT_OPCG_MODE_LEN ); +REG64_FLD( PEC_DBG_CBS_CC_LAST_OPCG_MODE , 20 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LAST_OPCG_MODE ); +REG64_FLD( PEC_DBG_CBS_CC_LAST_OPCG_MODE_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LAST_OPCG_MODE_LEN ); +REG64_FLD( PEC_DBG_CBS_CC_PCB_ERROR , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_ERROR ); +REG64_FLD( PEC_DBG_CBS_CC_PARITY_ERROR , 25 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ERROR ); +REG64_FLD( PEC_DBG_CBS_CC_ERROR , 26 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ERROR ); +REG64_FLD( PEC_DBG_CBS_CC_CHIPLET_IS_ALIGNED , 27 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CHIPLET_IS_ALIGNED ); +REG64_FLD( PEC_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET , 28 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_REQUEST_SINCE_RESET ); +REG64_FLD( PEC_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE , 29 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARANOIA_TEST_ENABLE_CHANGE ); +REG64_FLD( PEC_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE , 30 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE ); +REG64_FLD( PEC_DBG_CBS_CC_TP_TPFSI_ACK , 31 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TP_TPFSI_ACK ); + +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_C1_INAROW_MODE ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE1 ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE1 ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE1 ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1 ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_C2_INAROW_MODE ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE2 ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE2 ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE2 ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2 ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND3_ENABLE_RESET ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_EXACT_TO_MODE ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RESET_C2TIMER_ON_C1 ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RESET_C3_ON_C0 ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SLOW_TO_MODE ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_EXACT_RESET_C3_ON_TO ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); + +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_C1_INAROW_MODE ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE1 ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE1 ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE1 ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1 ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_C2_INAROW_MODE ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE2 ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE2 ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE2 ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2 ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND3_ENABLE_RESET ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_EXACT_TO_MODE ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RESET_C2TIMER_ON_C1 ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RESET_C3_ON_C0 ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SLOW_TO_MODE ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_EXACT_RESET_C3_ON_TO ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); + +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_C1_INAROW_MODE ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE1 ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE1 ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE1 ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1 ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_C2_INAROW_MODE ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE2 ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE2 ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE2 ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2 ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND3_ENABLE_RESET ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_EXACT_TO_MODE ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RESET_C2TIMER_ON_C1 ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RESET_C3_ON_C0 ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SLOW_TO_MODE ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_EXACT_RESET_C3_ON_TO ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); + +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_C1_INAROW_MODE ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE1 ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE1 ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE1 ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1 ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_C2_INAROW_MODE ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE2 ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE2 ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE2 ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2 ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND3_ENABLE_RESET ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EXACT_TO_MODE ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_C2TIMER_ON_C1 ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_C3_ON_C0 ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SLOW_TO_MODE ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EXACT_RESET_C3_ON_TO ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PEC_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); + +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_C1_INAROW_MODE ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE1 ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE1 ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE1 ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1 ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_C2_INAROW_MODE ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE2 ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE2 ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE2 ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2 ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND3_ENABLE_RESET ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_EXACT_TO_MODE ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RESET_C2TIMER_ON_C1 ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RESET_C3_ON_C0 ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SLOW_TO_MODE ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_EXACT_RESET_C3_ON_TO ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); + +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE_LEN ); +REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST_MODE ); + +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE_LEN ); +REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST_MODE ); + +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE_LEN ); +REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST_MODE ); + +REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B ); +REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B ); +REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PEC_DBG_INST1_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE ); +REG64_FLD( PEC_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE_LEN ); +REG64_FLD( PEC_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_TEST_MODE ); + +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE_LEN ); +REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST_MODE ); + +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_C1_INAROW_MODE ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE1 ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE1 ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE1 ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1 ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_C2_INAROW_MODE ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE2 ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE2 ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE2 ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2 ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND3_ENABLE_RESET ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_EXACT_TO_MODE ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RESET_C2TIMER_ON_C1 ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RESET_C3_ON_C0 ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SLOW_TO_MODE ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_EXACT_RESET_C3_ON_TO ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); + +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_C1_INAROW_MODE ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE1 ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE1 ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE1 ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1 ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_C2_INAROW_MODE ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE2 ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE2 ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE2 ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2 ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND3_ENABLE_RESET ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_EXACT_TO_MODE ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RESET_C2TIMER_ON_C1 ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RESET_C3_ON_C0 ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SLOW_TO_MODE ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_EXACT_RESET_C3_ON_TO ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); + +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_C1_INAROW_MODE ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE1 ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE1 ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE1 ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1 ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_C2_INAROW_MODE ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE2 ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE2 ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE2 ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2 ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND3_ENABLE_RESET ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_EXACT_TO_MODE ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RESET_C2TIMER_ON_C1 ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RESET_C3_ON_C0 ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SLOW_TO_MODE ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_EXACT_RESET_C3_ON_TO ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); + +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_C1_INAROW_MODE ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE1 ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE1 ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE1 ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1 ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_C2_INAROW_MODE ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE2 ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE2 ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE2 ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2 ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND3_ENABLE_RESET ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EXACT_TO_MODE ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_C2TIMER_ON_C1 ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_C3_ON_C0 ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SLOW_TO_MODE ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EXACT_RESET_C3_ON_TO ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PEC_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); + +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_C1_INAROW_MODE ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE1 ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE1 ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE1 ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1 ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_C2_INAROW_MODE ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE2 ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE2 ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE2 ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2 ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND3_ENABLE_RESET ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_EXACT_TO_MODE ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RESET_C2TIMER_ON_C1 ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RESET_C3_ON_C0 ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SLOW_TO_MODE ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_EXACT_RESET_C3_ON_TO ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); + +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE_LEN ); +REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST_MODE ); + +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE_LEN ); +REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST_MODE ); + +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE_LEN ); +REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST_MODE ); + +REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B ); +REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B ); +REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PEC_DBG_INST2_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE ); +REG64_FLD( PEC_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE_LEN ); +REG64_FLD( PEC_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_TEST_MODE ); + +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE_LEN ); +REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST_MODE ); + +REG64_FLD( PU_N3_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_GLB_BRCST ); +REG64_FLD( PU_N3_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_GLB_BRCST_LEN ); +REG64_FLD( PU_N3_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL ); +REG64_FLD( PU_N3_DBG_MODE_REG_TRACE_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PU_N3_DBG_MODE_REG_TRIG_SEL , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL ); +REG64_FLD( PU_N3_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); +REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_STOP_ON_XSTOP_SELECTION ); +REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); +REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 9 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_STOP_ON_SPATTN_SELECTION ); +REG64_FLD( PU_N3_DBG_MODE_REG_FREEZE_SEL , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_FREEZE_SEL ); + +REG64_FLD( PU_N1_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_GLB_BRCST ); +REG64_FLD( PU_N1_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_GLB_BRCST_LEN ); +REG64_FLD( PU_N1_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL ); +REG64_FLD( PU_N1_DBG_MODE_REG_TRACE_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PU_N1_DBG_MODE_REG_TRIG_SEL , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL ); +REG64_FLD( PU_N1_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); +REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_STOP_ON_XSTOP_SELECTION ); +REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); +REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 9 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_STOP_ON_SPATTN_SELECTION ); +REG64_FLD( PU_N1_DBG_MODE_REG_FREEZE_SEL , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_FREEZE_SEL ); + +REG64_FLD( PU_N2_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_GLB_BRCST ); +REG64_FLD( PU_N2_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_GLB_BRCST_LEN ); +REG64_FLD( PU_N2_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL ); +REG64_FLD( PU_N2_DBG_MODE_REG_TRACE_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PU_N2_DBG_MODE_REG_TRIG_SEL , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL ); +REG64_FLD( PU_N2_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); +REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_STOP_ON_XSTOP_SELECTION ); +REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); +REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 9 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_STOP_ON_SPATTN_SELECTION ); +REG64_FLD( PU_N2_DBG_MODE_REG_FREEZE_SEL , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_FREEZE_SEL ); + +REG64_FLD( PEC_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GLB_BRCST ); +REG64_FLD( PEC_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GLB_BRCST_LEN ); +REG64_FLD( PEC_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRACE_SEL ); +REG64_FLD( PEC_DBG_MODE_REG_TRACE_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PEC_DBG_MODE_REG_TRIG_SEL , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG_SEL ); +REG64_FLD( PEC_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); +REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STOP_ON_XSTOP_SELECTION ); +REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); +REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STOP_ON_SPATTN_SELECTION ); +REG64_FLD( PEC_DBG_MODE_REG_FREEZE_SEL , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FREEZE_SEL ); + +REG64_FLD( PU_N0_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_GLB_BRCST ); +REG64_FLD( PU_N0_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_GLB_BRCST_LEN ); +REG64_FLD( PU_N0_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL ); +REG64_FLD( PU_N0_DBG_MODE_REG_TRACE_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PU_N0_DBG_MODE_REG_TRIG_SEL , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL ); +REG64_FLD( PU_N0_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); +REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_STOP_ON_XSTOP_SELECTION ); +REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); +REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 9 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_STOP_ON_SPATTN_SELECTION ); +REG64_FLD( PU_N0_DBG_MODE_REG_FREEZE_SEL , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_FREEZE_SEL ); + +REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RUNN_COUNT_COMPARE_VALUE ); +REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_IMM_FREEZE , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_IMM_FREEZE ); +REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_STOP_ON_ERR , 17 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_STOP_ON_ERR ); +REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH , 18 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_BANK_ON_RUNN_MATCH ); +REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_FORCE_TEST , 19 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST ); +REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_ACCUM_HIST , 20 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ACCUM_HIST ); +REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ , 21 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_FRZ_COUNT_ON_FRZ ); + +REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RUNN_COUNT_COMPARE_VALUE ); +REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_IMM_FREEZE , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_IMM_FREEZE ); +REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_STOP_ON_ERR , 17 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_STOP_ON_ERR ); +REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH , 18 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_BANK_ON_RUNN_MATCH ); +REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_FORCE_TEST , 19 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST ); +REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_ACCUM_HIST , 20 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ACCUM_HIST ); +REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ , 21 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_FRZ_COUNT_ON_FRZ ); + +REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RUNN_COUNT_COMPARE_VALUE ); +REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_IMM_FREEZE , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_IMM_FREEZE ); +REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_STOP_ON_ERR , 17 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_STOP_ON_ERR ); +REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH , 18 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_BANK_ON_RUNN_MATCH ); +REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_FORCE_TEST , 19 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST ); +REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_ACCUM_HIST , 20 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ACCUM_HIST ); +REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ , 21 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_FRZ_COUNT_ON_FRZ ); + +REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RUNN_COUNT_COMPARE_VALUE ); +REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN ); +REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_IMM_FREEZE , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IMM_FREEZE ); +REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_STOP_ON_ERR , 17 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STOP_ON_ERR ); +REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH , 18 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_BANK_ON_RUNN_MATCH ); +REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_FORCE_TEST , 19 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_TEST ); +REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_ACCUM_HIST , 20 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACCUM_HIST ); +REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ , 21 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FRZ_COUNT_ON_FRZ ); + +REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RUNN_COUNT_COMPARE_VALUE ); +REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_IMM_FREEZE , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_IMM_FREEZE ); +REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_STOP_ON_ERR , 17 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_STOP_ON_ERR ); +REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH , 18 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_BANK_ON_RUNN_MATCH ); +REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_FORCE_TEST , 19 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST ); +REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_ACCUM_HIST , 20 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ACCUM_HIST ); +REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ , 21 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_FRZ_COUNT_ON_FRZ ); + +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_COND3_ENABLE , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_COND3_ENABLE ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_COND3_ENABLE , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_COND3_ENABLE ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST3_COND3_ENABLE , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST3_COND3_ENABLE ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST4_COND3_ENABLE , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST4_COND3_ENABLE ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_SLOW_LFSR_MODE ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_SLOW_LFSR_MODE ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE , 6 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST3_SLOW_LFSR_MODE ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST4_SLOW_LFSR_MODE ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_TRIG_SEL ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_TRIG_SEL ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL , 12 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL , 14 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_TRIG_SEL ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_TRIG_SEL ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL , 18 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP , 32 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_EXT_TRIG_ON_STOP ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE , 33 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_EXT_TRIG_ON_FREEZE ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL , 34 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CORE_RAS0_TRIG_SEL ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CORE_RAS0_TRIG_SEL_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CORE_RAS1_TRIG_SEL ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_CORE_RAS1_TRIG_SEL_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_PC_TP_TRIG_SEL , 44 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_PC_TP_TRIG_SEL ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_PC_TP_TRIG_SEL_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_ARM_SEL , 46 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ARM_SEL ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_ARM_SEL_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ARM_SEL_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL , 50 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRIG0_LEVEL_SEL ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRIG0_LEVEL_SEL_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL , 54 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRIG1_LEVEL_SEL ); +REG64_FLD( PU_N3_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRIG1_LEVEL_SEL_LEN ); + +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_COND3_ENABLE , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_COND3_ENABLE ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_COND3_ENABLE , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_COND3_ENABLE ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST3_COND3_ENABLE , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST3_COND3_ENABLE ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST4_COND3_ENABLE , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST4_COND3_ENABLE ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_SLOW_LFSR_MODE ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_SLOW_LFSR_MODE ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE , 6 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST3_SLOW_LFSR_MODE ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST4_SLOW_LFSR_MODE ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_TRIG_SEL ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_TRIG_SEL ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL , 12 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL , 14 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_TRIG_SEL ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_TRIG_SEL ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL , 18 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP , 32 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_EXT_TRIG_ON_STOP ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE , 33 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_EXT_TRIG_ON_FREEZE ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL , 34 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CORE_RAS0_TRIG_SEL ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CORE_RAS0_TRIG_SEL_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CORE_RAS1_TRIG_SEL ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_CORE_RAS1_TRIG_SEL_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL , 44 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_PC_TP_TRIG_SEL ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_PC_TP_TRIG_SEL_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_ARM_SEL , 46 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ARM_SEL ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_ARM_SEL_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ARM_SEL_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL , 50 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRIG0_LEVEL_SEL ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRIG0_LEVEL_SEL_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL , 54 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRIG1_LEVEL_SEL ); +REG64_FLD( PU_N1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRIG1_LEVEL_SEL_LEN ); + +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_COND3_ENABLE , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_COND3_ENABLE ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_COND3_ENABLE , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_COND3_ENABLE ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST3_COND3_ENABLE , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST3_COND3_ENABLE ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST4_COND3_ENABLE , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST4_COND3_ENABLE ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_SLOW_LFSR_MODE ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_SLOW_LFSR_MODE ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE , 6 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST3_SLOW_LFSR_MODE ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST4_SLOW_LFSR_MODE ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_TRIG_SEL ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_TRIG_SEL ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL , 12 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL , 14 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_TRIG_SEL ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_TRIG_SEL ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL , 18 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP , 32 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_EXT_TRIG_ON_STOP ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE , 33 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_EXT_TRIG_ON_FREEZE ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL , 34 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CORE_RAS0_TRIG_SEL ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CORE_RAS0_TRIG_SEL_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CORE_RAS1_TRIG_SEL ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_CORE_RAS1_TRIG_SEL_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_PC_TP_TRIG_SEL , 44 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_PC_TP_TRIG_SEL ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_PC_TP_TRIG_SEL_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_ARM_SEL , 46 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ARM_SEL ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_ARM_SEL_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ARM_SEL_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL , 50 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRIG0_LEVEL_SEL ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRIG0_LEVEL_SEL_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL , 54 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRIG1_LEVEL_SEL ); +REG64_FLD( PU_N2_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRIG1_LEVEL_SEL_LEN ); + +REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_COND3_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_COND3_ENABLE ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_COND3_ENABLE , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_COND3_ENABLE ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST3_COND3_ENABLE , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST3_COND3_ENABLE ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST4_COND3_ENABLE , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST4_COND3_ENABLE ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_SLOW_LFSR_MODE ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_SLOW_LFSR_MODE ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST3_SLOW_LFSR_MODE ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST4_SLOW_LFSR_MODE ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_TRIG_SEL ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_TRIG_SEL ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_TRIG_SEL ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_TRIG_SEL ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL , 18 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL ); +REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP , 32 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EXT_TRIG_ON_STOP ); +REG64_FLD( PEC_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE , 33 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_EXT_TRIG_ON_FREEZE ); +REG64_FLD( PEC_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL , 34 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CORE_RAS0_TRIG_SEL ); +REG64_FLD( PEC_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CORE_RAS0_TRIG_SEL_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL , 39 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CORE_RAS1_TRIG_SEL ); +REG64_FLD( PEC_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CORE_RAS1_TRIG_SEL_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_0_PC_TP_TRIG_SEL , 44 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PC_TP_TRIG_SEL ); +REG64_FLD( PEC_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PC_TP_TRIG_SEL_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_0_ARM_SEL , 46 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ARM_SEL ); +REG64_FLD( PEC_DBG_TRACE_REG_0_ARM_SEL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ARM_SEL_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL , 50 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG0_LEVEL_SEL ); +REG64_FLD( PEC_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG0_LEVEL_SEL_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL , 54 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG1_LEVEL_SEL ); +REG64_FLD( PEC_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG1_LEVEL_SEL_LEN ); + +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_COND3_ENABLE , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_COND3_ENABLE ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_COND3_ENABLE , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_COND3_ENABLE ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST3_COND3_ENABLE , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST3_COND3_ENABLE ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST4_COND3_ENABLE , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST4_COND3_ENABLE ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_SLOW_LFSR_MODE ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_SLOW_LFSR_MODE ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE , 6 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST3_SLOW_LFSR_MODE ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST4_SLOW_LFSR_MODE ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_TRIG_SEL ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_TRIG_SEL ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL , 12 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL , 14 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_TRIG_SEL ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_TRIG_SEL ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL , 18 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP , 32 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_EXT_TRIG_ON_STOP ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE , 33 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_EXT_TRIG_ON_FREEZE ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL , 34 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CORE_RAS0_TRIG_SEL ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CORE_RAS0_TRIG_SEL_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CORE_RAS1_TRIG_SEL ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_CORE_RAS1_TRIG_SEL_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL , 44 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_PC_TP_TRIG_SEL ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_PC_TP_TRIG_SEL_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_ARM_SEL , 46 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ARM_SEL ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_ARM_SEL_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ARM_SEL_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL , 50 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRIG0_LEVEL_SEL ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRIG0_LEVEL_SEL_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL , 54 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRIG1_LEVEL_SEL ); +REG64_FLD( PU_N0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRIG1_LEVEL_SEL_LEN ); + +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_DO ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_DO_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_DO ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_DO_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_DO ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO , 6 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_DO ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_DO_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_DO ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_DO_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_DO ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_WAITN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_WAITN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_WAITN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_WAITN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_BANK ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_BANK ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_BANK ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_BANK ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT , 48 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_LT ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT , 52 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_LT ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN ); +REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); + +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_DO ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_DO_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_DO ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_DO_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_DO ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO , 6 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_DO ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_DO_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_DO ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_DO_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_DO ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_WAITN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_WAITN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_WAITN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_WAITN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_BANK ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_BANK ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_BANK ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_BANK ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT , 48 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_LT ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT , 52 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_LT ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN ); +REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); + +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_DO ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_DO_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_DO ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_DO_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_DO ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO , 6 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_DO ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_DO_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_DO ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_DO_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_DO ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_WAITN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_WAITN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_WAITN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_WAITN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_BANK ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_BANK ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_BANK ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_BANK ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT , 48 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_LT ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT , 52 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_LT ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN ); +REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); + +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_DO ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_DO_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_DO ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_DO_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_DO ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_DO ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_DO_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_DO ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_DO_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_DO ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_WAITN ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_WAITN ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_WAITN ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_WAITN ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_BANK ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_BANK ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_BANK ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_BANK ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_LT ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT , 52 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_LT ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN ); +REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); + +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_DO ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_DO_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_DO ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_DO_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_DO ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO , 6 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_DO ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_DO_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_DO ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_DO_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_DO ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_WAITN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_WAITN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_WAITN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_WAITN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_BANK ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_BANK ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_BANK ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_BANK ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT , 48 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_LT ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT , 52 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_LT ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN ); +REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( PU_NPU1_SM2_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_POD0 ); @@ -28070,157 +36448,106 @@ REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU0_SM1_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , @@ -28274,55 +36601,55 @@ REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU2_SM3_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , @@ -28376,57 +36703,6 @@ REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_ACT ); - REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , @@ -28682,57 +36958,6 @@ REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU1_SM0_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_ACT ); - REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_SM2_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , @@ -29039,157 +37264,106 @@ REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU0_SM1_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , - SH_FLD_ACT ); - -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM0_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , @@ -29243,55 +37417,55 @@ REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU2_SM3_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD0 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD1 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD2 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD3 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD4 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD5 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD6 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD7 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD8 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD9 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD10 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_SM3_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , @@ -29345,57 +37519,6 @@ REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_SM2_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_ACT ); - REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , @@ -29651,61 +37774,279 @@ REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UN REG64_FLD( PU_NPU1_SM0_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD0 ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD0_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD1 ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD1_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD2 ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD2_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD3 ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD3_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD4 ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD4_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD5 ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD5_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD6 ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD6_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD7 ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD7_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD8 ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD8_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD9 ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD9_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD10 ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_POD10_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE0 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE0 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE0_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE0_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE1 , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE1 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE1_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE1_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE2 , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE2 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE2_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE2_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE3 , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE3 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE3_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE3_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE4 , 8 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE4 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE4_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE4_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE5 , 10 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE5 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE5_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE5_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE6 , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE6 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE6_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE6_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE7 , 14 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE7 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE7_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE7_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE8 , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE8 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE8_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE8_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE9 , 18 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE9 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE9_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE9_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE10 , 20 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE10 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE10_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS0BYTE10_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE0 , 22 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE0 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE0_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE0_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE1 , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE1 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE1_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE1_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE2 , 26 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE2 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE2_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE2_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE3 , 28 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE3 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE3_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE3_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE4 , 30 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE4 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE4_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE4_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE5 , 32 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE5 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE5_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE5_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE6 , 34 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE6 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE6_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE6_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE7 , 36 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE7 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE7_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE7_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE8 , 38 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE8 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE8_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE8_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE9 , 40 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE9 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE9_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE9_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE10 , 42 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE10 ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE10_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_BUS1BYTE10_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_RESERVED , 44 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_RESERVED_LEN , 19 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED_LEN ); +REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_ACT , 63 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , - SH_FLD_MISC ); -REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_LEN , 64 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , - SH_FLD_MISC_LEN ); +REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_MUX_PORT_SEL , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BLOCK_MUX_PORT_SEL ); +REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_MUX_PORT_SEL_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BLOCK_MUX_PORT_SEL_LEN ); +REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_SEL , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BLOCK_SEL ); +REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_SEL_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BLOCK_SEL_LEN ); + +REG64_FLD( PU_N3_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_LOCAL_TRACE_RUN_IN ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_TRACE_STATE_LAT , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRACE_STATE_LAT ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRACE_STATE_LAT_LEN ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_TRACE_FREEZE , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRACE_FREEZE ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_COND3_STATE_LT , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND3_STATE_LT ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_COND3_STATE_LT_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND3_STATE_LT_LEN ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_COND5_STATE_LT , 6 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND5_STATE_LT ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_COND5_STATE_LT_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_COND5_STATE_LT_LEN ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_HISTORY_CONDITION0_LT ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT , 9 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_HISTORY_CONDITION1_LT ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND2_3_EVENT ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT , 11 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND2_TIMEOUT ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT , 12 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND4_5_EVENT ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT , 13 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND4_TIMEOUT ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_RESERVED_TCDBG_LT , 14 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RESERVED_TCDBG_LT ); +REG64_FLD( PU_N3_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RESERVED_TCDBG_LT_LEN ); + +REG64_FLD( PU_N1_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_LOCAL_TRACE_RUN_IN ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_TRACE_STATE_LAT , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRACE_STATE_LAT ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRACE_STATE_LAT_LEN ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_TRACE_FREEZE , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRACE_FREEZE ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_COND3_STATE_LT , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND3_STATE_LT ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_COND3_STATE_LT_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND3_STATE_LT_LEN ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_COND5_STATE_LT , 6 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND5_STATE_LT ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_COND5_STATE_LT_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_COND5_STATE_LT_LEN ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_HISTORY_CONDITION0_LT ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT , 9 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_HISTORY_CONDITION1_LT ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND2_3_EVENT ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT , 11 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND2_TIMEOUT ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT , 12 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND4_5_EVENT ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT , 13 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND4_TIMEOUT ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_RESERVED_TCDBG_LT , 14 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RESERVED_TCDBG_LT ); +REG64_FLD( PU_N1_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RESERVED_TCDBG_LT_LEN ); + +REG64_FLD( PU_N2_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_LOCAL_TRACE_RUN_IN ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_TRACE_STATE_LAT , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRACE_STATE_LAT ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRACE_STATE_LAT_LEN ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_TRACE_FREEZE , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRACE_FREEZE ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_COND3_STATE_LT , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND3_STATE_LT ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_COND3_STATE_LT_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND3_STATE_LT_LEN ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_COND5_STATE_LT , 6 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND5_STATE_LT ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_COND5_STATE_LT_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_COND5_STATE_LT_LEN ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_HISTORY_CONDITION0_LT ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT , 9 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_HISTORY_CONDITION1_LT ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND2_3_EVENT ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT , 11 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND2_TIMEOUT ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT , 12 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND4_5_EVENT ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT , 13 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND4_TIMEOUT ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_RESERVED_TCDBG_LT , 14 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RESERVED_TCDBG_LT ); +REG64_FLD( PU_N2_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RESERVED_TCDBG_LT_LEN ); + +REG64_FLD( PEC_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LOCAL_TRACE_RUN_IN ); +REG64_FLD( PEC_DEBUG_STATUS_REG_TRACE_STATE_LAT , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRACE_STATE_LAT ); +REG64_FLD( PEC_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRACE_STATE_LAT_LEN ); +REG64_FLD( PEC_DEBUG_STATUS_REG_TRACE_FREEZE , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRACE_FREEZE ); +REG64_FLD( PEC_DEBUG_STATUS_REG_COND3_STATE_LT , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND3_STATE_LT ); +REG64_FLD( PEC_DEBUG_STATUS_REG_COND3_STATE_LT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND3_STATE_LT_LEN ); +REG64_FLD( PEC_DEBUG_STATUS_REG_COND5_STATE_LT , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND5_STATE_LT ); +REG64_FLD( PEC_DEBUG_STATUS_REG_COND5_STATE_LT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COND5_STATE_LT_LEN ); +REG64_FLD( PEC_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_HISTORY_CONDITION0_LT ); +REG64_FLD( PEC_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_HISTORY_CONDITION1_LT ); +REG64_FLD( PEC_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_HISTORY_COND2_3_EVENT ); +REG64_FLD( PEC_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_HISTORY_COND2_TIMEOUT ); +REG64_FLD( PEC_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_HISTORY_COND4_5_EVENT ); +REG64_FLD( PEC_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_HISTORY_COND4_TIMEOUT ); +REG64_FLD( PEC_DEBUG_STATUS_REG_RESERVED_TCDBG_LT , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESERVED_TCDBG_LT ); +REG64_FLD( PEC_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESERVED_TCDBG_LT_LEN ); + +REG64_FLD( PU_N0_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_LOCAL_TRACE_RUN_IN ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_TRACE_STATE_LAT , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRACE_STATE_LAT ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRACE_STATE_LAT_LEN ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_TRACE_FREEZE , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRACE_FREEZE ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_COND3_STATE_LT , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND3_STATE_LT ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_COND3_STATE_LT_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND3_STATE_LT_LEN ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_COND5_STATE_LT , 6 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND5_STATE_LT ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_COND5_STATE_LT_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_COND5_STATE_LT_LEN ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_HISTORY_CONDITION0_LT ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT , 9 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_HISTORY_CONDITION1_LT ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND2_3_EVENT ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT , 11 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND2_TIMEOUT ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT , 12 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND4_5_EVENT ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT , 13 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND4_TIMEOUT ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_RESERVED_TCDBG_LT , 14 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RESERVED_TCDBG_LT ); +REG64_FLD( PU_N0_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RESERVED_TCDBG_LT_LEN ); + +REG64_FLD( CAPP_DFSUOP1_WORD , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_WORD ); +REG64_FLD( CAPP_DFSUOP1_WORD_LEN , 56 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_WORD_LEN ); REG64_FLD( PU_DISABLE_FORCE_PFET_OFF_REG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_REG ); @@ -29760,196 +38101,123 @@ REG64_FLD( PEC_DRPPRICTL_REG_PE_RTYDROPDIVIDER , 23 , SH_UN REG64_FLD( PEC_DRPPRICTL_REG_PE_RTYDROPDIVIDER_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_RTYDROPDIVIDER_LEN ); -REG64_FLD( PU_NPU0_ECC_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_ECC_CONFIG_RESERVED1_LEN , 29 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU0_ECC_CONFIG_PBTX_AMO_IGNORE_XUE , 29 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PEC_DTS_RESULT0_0_RESULT , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_0_RESULT ); +REG64_FLD( PEC_DTS_RESULT0_0_RESULT_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_0_RESULT_LEN ); +REG64_FLD( PEC_DTS_RESULT0_1_RESULT , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_1_RESULT ); +REG64_FLD( PEC_DTS_RESULT0_1_RESULT_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_1_RESULT_LEN ); + +REG64_FLD( PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_TIMESTAMP_COUNTER_VALUE ); +REG64_FLD( PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN , 44 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN ); +REG64_FLD( PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR , 44 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR ); +REG64_FLD( PEC_DTS_TRC_RESULT_1 , 48 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_1 ); +REG64_FLD( PEC_DTS_TRC_RESULT_1_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_1_LEN ); + +REG64_FLD( PU_NPU0_ECC_CONFIG_PBTX_AMO_IGNORE_XUE , 0 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_PBTX_AMO_IGNORE_XUE ); -REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_BR_PERR , 30 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_BR_PERR , 1 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_BR_PERR ); -REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_IR_PERR , 31 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_IR_PERR , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_IR_PERR ); -REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_OR_PERR , 32 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_OR_PERR , 3 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_OR_PERR ); -REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_PT , 33 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_PT , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_CORR_DIS_PT ); -REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_PR , 34 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_PR , 5 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_CORR_DIS_PR ); -REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_BR , 35 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_BR , 6 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_CORR_DIS_BR ); -REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_IR , 36 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_IR , 7 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_CORR_DIS_IR ); -REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_OR , 37 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_OR , 8 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_CORR_DIS_OR ); -REG64_FLD( PU_NPU0_ECC_CONFIG_RESERVED3 , 38 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU0_ECC_CONFIG_RESERVED3_LEN , 5 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_RESERVED3_LEN ); -REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_PT , 43 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_PT , 9 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_PT ); -REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_PR , 44 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_PR , 10 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_PR ); -REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_BR , 45 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_BR , 11 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_BR ); -REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_IR , 46 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_IR , 12 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_IR ); -REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_OR , 47 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , +REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_OR , 13 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_OR ); -REG64_FLD( PU_NPU0_ECC_CONFIG_RESERVED2 , 48 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU0_ECC_CONFIG_RESERVED2_LEN , 16 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU0_ECC_CONFIG_RESERVED , 14 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_RESERVED ); +REG64_FLD( PU_NPU0_ECC_CONFIG_RESERVED_LEN , 18 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_RESERVED_LEN ); -REG64_FLD( PU_NPU1_ECC_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_ECC_CONFIG_RESERVED1_LEN , 29 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU1_ECC_CONFIG_PBTX_AMO_IGNORE_XUE , 29 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_ECC_CONFIG_PBTX_AMO_IGNORE_XUE , 0 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_PBTX_AMO_IGNORE_XUE ); -REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_BR_PERR , 30 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_BR_PERR , 1 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_BR_PERR ); -REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_IR_PERR , 31 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_IR_PERR , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_IR_PERR ); -REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_OR_PERR , 32 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_OR_PERR , 3 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_OR_PERR ); -REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_PT , 33 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_PT , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CORR_DIS_PT ); -REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_PR , 34 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_PR , 5 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CORR_DIS_PR ); -REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_BR , 35 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_BR , 6 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CORR_DIS_BR ); -REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_IR , 36 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_IR , 7 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CORR_DIS_IR ); -REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_OR , 37 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_OR , 8 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CORR_DIS_OR ); -REG64_FLD( PU_NPU1_ECC_CONFIG_RESERVED3 , 38 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU1_ECC_CONFIG_RESERVED3_LEN , 5 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_RESERVED3_LEN ); -REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_PT , 43 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_PT , 9 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_PT ); -REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_PR , 44 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_PR , 10 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_PR ); -REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_BR , 45 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_BR , 11 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_BR ); -REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_IR , 46 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_IR , 12 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_IR ); -REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_OR , 47 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , +REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_OR , 13 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_OR ); -REG64_FLD( PU_NPU1_ECC_CONFIG_RESERVED2 , 48 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU1_ECC_CONFIG_RESERVED2_LEN , 16 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); +REG64_FLD( PU_NPU1_ECC_CONFIG_RESERVED , 14 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_RESERVED ); +REG64_FLD( PU_NPU1_ECC_CONFIG_RESERVED_LEN , 18 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_RESERVED_LEN ); -REG64_FLD( PU_NPU2_ECC_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_ECC_CONFIG_RESERVED1_LEN , 29 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); -REG64_FLD( PU_NPU2_ECC_CONFIG_PBTX_AMO_IGNORE_XUE , 29 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_PBTX_AMO_IGNORE_XUE , 0 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_PBTX_AMO_IGNORE_XUE ); -REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_BR_PERR , 30 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_BR_PERR , 1 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_BR_PERR ); -REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_IR_PERR , 31 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_IR_PERR , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_IR_PERR ); -REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_OR_PERR , 32 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_OR_PERR , 3 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_OR_PERR ); -REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_PT , 33 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_PT , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CORR_DIS_PT ); -REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_PR , 34 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_PR , 5 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CORR_DIS_PR ); -REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_BR , 35 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_BR , 6 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CORR_DIS_BR ); -REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_IR , 36 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_IR , 7 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CORR_DIS_IR ); -REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_OR , 37 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_OR , 8 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CORR_DIS_OR ); -REG64_FLD( PU_NPU2_ECC_CONFIG_RESERVED3 , 38 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_RESERVED3 ); -REG64_FLD( PU_NPU2_ECC_CONFIG_RESERVED3_LEN , 5 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_RESERVED3_LEN ); -REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_PT , 43 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_PT , 9 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_PT ); -REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_PR , 44 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_PR , 10 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_PR ); -REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_BR , 45 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_BR , 11 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_BR ); -REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_IR , 46 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_IR , 12 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_IR ); -REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_OR , 47 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_OR , 13 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_OR ); -REG64_FLD( PU_NPU2_ECC_CONFIG_RESERVED2 , 48 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_RESERVED2 ); -REG64_FLD( PU_NPU2_ECC_CONFIG_RESERVED2_LEN , 16 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_RESERVED2_LEN ); - -REG64_FLD( PU_NPU0_ECC_ERRINJ_ENABLE , 0 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_ENABLE ); -REG64_FLD( PU_NPU0_ECC_ERRINJ_PBRX_MASK , 1 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_PBRX_MASK ); -REG64_FLD( PU_NPU0_ECC_ERRINJ_PBRX_MASK_LEN , 8 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_PBRX_MASK_LEN ); -REG64_FLD( PU_NPU0_ECC_ERRINJ_BBWR_MASK , 9 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_BBWR_MASK ); -REG64_FLD( PU_NPU0_ECC_ERRINJ_BBWR_MASK_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_BBWR_MASK_LEN ); -REG64_FLD( PU_NPU0_ECC_ERRINJ_IBWR_MASK , 13 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_IBWR_MASK ); -REG64_FLD( PU_NPU0_ECC_ERRINJ_IBWR_MASK_LEN , 16 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_IBWR_MASK_LEN ); -REG64_FLD( PU_NPU0_ECC_ERRINJ_OBWR_MASK , 29 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_OBWR_MASK ); -REG64_FLD( PU_NPU0_ECC_ERRINJ_OBWR_MASK_LEN , 16 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_OBWR_MASK_LEN ); -REG64_FLD( PU_NPU0_ECC_ERRINJ_RESERVED , 45 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_RESERVED ); -REG64_FLD( PU_NPU0_ECC_ERRINJ_RESERVED_LEN , 3 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_RESERVED_LEN ); - -REG64_FLD( PU_NPU1_ECC_ERRINJ_ENABLE , 0 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_ENABLE ); -REG64_FLD( PU_NPU1_ECC_ERRINJ_PBRX_MASK , 1 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_PBRX_MASK ); -REG64_FLD( PU_NPU1_ECC_ERRINJ_PBRX_MASK_LEN , 8 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_PBRX_MASK_LEN ); -REG64_FLD( PU_NPU1_ECC_ERRINJ_BBWR_MASK , 9 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_BBWR_MASK ); -REG64_FLD( PU_NPU1_ECC_ERRINJ_BBWR_MASK_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_BBWR_MASK_LEN ); -REG64_FLD( PU_NPU1_ECC_ERRINJ_IBWR_MASK , 13 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_IBWR_MASK ); -REG64_FLD( PU_NPU1_ECC_ERRINJ_IBWR_MASK_LEN , 16 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_IBWR_MASK_LEN ); -REG64_FLD( PU_NPU1_ECC_ERRINJ_OBWR_MASK , 29 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_OBWR_MASK ); -REG64_FLD( PU_NPU1_ECC_ERRINJ_OBWR_MASK_LEN , 16 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_OBWR_MASK_LEN ); -REG64_FLD( PU_NPU1_ECC_ERRINJ_RESERVED , 45 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_RESERVED ); -REG64_FLD( PU_NPU1_ECC_ERRINJ_RESERVED_LEN , 3 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_RESERVED_LEN ); - -REG64_FLD( PU_NPU2_ECC_ERRINJ_ENABLE , 0 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_ENABLE ); -REG64_FLD( PU_NPU2_ECC_ERRINJ_PBRX_MASK , 1 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_PBRX_MASK ); -REG64_FLD( PU_NPU2_ECC_ERRINJ_PBRX_MASK_LEN , 8 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_PBRX_MASK_LEN ); -REG64_FLD( PU_NPU2_ECC_ERRINJ_BBWR_MASK , 9 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_BBWR_MASK ); -REG64_FLD( PU_NPU2_ECC_ERRINJ_BBWR_MASK_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_BBWR_MASK_LEN ); -REG64_FLD( PU_NPU2_ECC_ERRINJ_IBWR_MASK , 13 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_IBWR_MASK ); -REG64_FLD( PU_NPU2_ECC_ERRINJ_IBWR_MASK_LEN , 16 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_IBWR_MASK_LEN ); -REG64_FLD( PU_NPU2_ECC_ERRINJ_OBWR_MASK , 29 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_OBWR_MASK ); -REG64_FLD( PU_NPU2_ECC_ERRINJ_OBWR_MASK_LEN , 16 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_OBWR_MASK_LEN ); -REG64_FLD( PU_NPU2_ECC_ERRINJ_RESERVED , 45 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_RESERVED , 14 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_RESERVED ); -REG64_FLD( PU_NPU2_ECC_ERRINJ_RESERVED_LEN , 3 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , +REG64_FLD( PU_NPU2_ECC_CONFIG_RESERVED_LEN , 18 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART0_REGISTER_PART_0 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , @@ -31275,6 +39543,12 @@ REG64_FLD( PU_ERAT_STATUS_CONTROL_VALID_ENTRY , 2 , SH_UN SH_FLD_VALID_ENTRY ); REG64_FLD( PU_ERAT_STATUS_CONTROL_DISABLE_HIT_UNDER_BARRIER , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_HIT_UNDER_BARRIER ); +REG64_FLD( PU_ERAT_STATUS_CONTROL_DISABLE_PROMOTE , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_PROMOTE ); +REG64_FLD( PU_ERAT_STATUS_CONTROL_DISABLE_CHECKIN_HANG_TIMER , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_CHECKIN_HANG_TIMER ); +REG64_FLD( PU_ERAT_STATUS_CONTROL_DISABLE_CHECKOUT_HANG_TIMER , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_CHECKOUT_HANG_TIMER ); REG64_FLD( PU_ERAT_STATUS_CONTROL_SPECULATIVE_CHECKIN_COUNT , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPECULATIVE_CHECKIN_COUNT ); REG64_FLD( PU_ERAT_STATUS_CONTROL_SPECULATIVE_CHECKIN_COUNT_LEN , 3 , SH_UNT , SH_ACS_SCOM , @@ -31305,6 +39579,64 @@ REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK5 , 30 , SH_UN REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK5_LEN , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ERR_BRK5_LEN ); +REG64_FLD( PEC_ERROR_REG_CE , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CE ); +REG64_FLD( PEC_ERROR_REG_CHIPLET_ERRORS , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CHIPLET_ERRORS ); +REG64_FLD( PEC_ERROR_REG_CHIPLET_ERRORS_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CHIPLET_ERRORS_LEN ); +REG64_FLD( PEC_ERROR_REG_PARITY , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY ); +REG64_FLD( PEC_ERROR_REG_DATA_BUFFER , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DATA_BUFFER ); +REG64_FLD( PEC_ERROR_REG_ADDR_BUFFER , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ADDR_BUFFER ); +REG64_FLD( PEC_ERROR_REG_PCB_FSM , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_FSM ); +REG64_FLD( PEC_ERROR_REG_CL_FSM , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CL_FSM ); +REG64_FLD( PEC_ERROR_REG_INT_RX_FSM , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INT_RX_FSM ); +REG64_FLD( PEC_ERROR_REG_INT_TX_FSM , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INT_TX_FSM ); +REG64_FLD( PEC_ERROR_REG_INT_TYPE , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INT_TYPE ); +REG64_FLD( PEC_ERROR_REG_CL_DATA , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CL_DATA ); +REG64_FLD( PEC_ERROR_REG_INFO , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INFO ); +REG64_FLD( PEC_ERROR_REG_UNUSED_0 , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_0 ); +REG64_FLD( PEC_ERROR_REG_CHIPLET_ATOMIC_LOCK , 15 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CHIPLET_ATOMIC_LOCK ); +REG64_FLD( PEC_ERROR_REG_PCB_INTERFACE , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_INTERFACE ); +REG64_FLD( PEC_ERROR_REG_CHIPLET_OFFLINE , 17 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CHIPLET_OFFLINE ); +REG64_FLD( PEC_ERROR_REG_CHIPLET_GRID_SKITTER , 18 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CHIPLET_GRID_SKITTER ); +REG64_FLD( PEC_ERROR_REG_CTRL_PARITY , 19 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CTRL_PARITY ); +REG64_FLD( PEC_ERROR_REG_ADDRESS_PARITY , 20 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ADDRESS_PARITY ); +REG64_FLD( PEC_ERROR_REG_TIMEOUT_PARITY , 21 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TIMEOUT_PARITY ); +REG64_FLD( PEC_ERROR_REG_CONFIG_PARITY , 22 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CONFIG_PARITY ); +REG64_FLD( PEC_ERROR_REG_UNUSED_1 , 23 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_1 ); +REG64_FLD( PEC_ERROR_REG_DIV_PARITY , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DIV_PARITY ); +REG64_FLD( PEC_ERROR_REG_PLL_UNLOCK , 25 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PLL_UNLOCK ); +REG64_FLD( PEC_ERROR_REG_PLL_UNLOCK_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PLL_UNLOCK_LEN ); + +REG64_FLD( PEC_ERROR_STATUS_ERRORS , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ERRORS ); +REG64_FLD( PEC_ERROR_STATUS_ERRORS_LEN , 32 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ERRORS_LEN ); + REG64_FLD( PU_NPU_SM2_ERR_FIRST_BITS , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU_SM2_ERR_FIRST_BITS_LEN , 64 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , @@ -31334,9 +39666,27 @@ REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR5 , 13 , SH_UN SH_FLD_SNP_REG_ERR5 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR6 , 14 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_SNP_REG_ERR6 ); -REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED2 , 15 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATR_SM_STATE , 15 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATR_SM_STATE ); +REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATSD_SM_STATE , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATSD_SM_STATE ); +REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATR_TIMEOUT , 17 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATR_TIMEOUT ); +REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATSD_TIMEOUT , 18 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATSD_TIMEOUT ); +REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATSD_BAD_TAG , 19 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATSD_BAD_TAG ); +REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_ERR2 , 20 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_MAP_REG_ERR2 ); +REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_ERR3 , 21 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_MAP_REG_ERR3 ); +REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_ERR4 , 22 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_MAP_REG_ERR4 ); +REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATR_ARBSTATE , 23 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATR_ARBSTATE ); +REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED2 , 24 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED2 ); -REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED2_LEN , 17 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED2_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED2_LEN ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_CERR0 , 32 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_IFC_REG_CERR0 ); @@ -31379,11 +39729,60 @@ REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED4 , 59 , SH_UN REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED4_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED4_LEN ); +REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC ); +REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_LEN , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_LEN ); +REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_LENR , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_LENR ); +REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_LENR_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_LENR_LEN ); +REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_RNW , 26 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_RNW ); +REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_DA_OP , 27 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MISC_DA_OP ); + REG64_FLD( PU_NPU_SM2_ERR_MASK_BITS , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU_SM2_ERR_MASK_BITS_LEN , 64 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BITS_LEN ); +REG64_FLD( PU_NPU_CTL_ERR_SCOPE_CTL_CONFIG_CTL , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_CTL ); +REG64_FLD( PU_NPU_CTL_ERR_SCOPE_CTL_CONFIG_CTL_LEN , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_CTL_LEN ); + +REG64_FLD( PEC_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK , 17 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_THERM_MODEREG_PARITY_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK , 18 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_MODEREG_PARITY_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK , 19 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SKITTER_FORCEREG_PARITY_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK , 20 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SCAN_INIT_VERSION_PARITY_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK , 21 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_VOLT_MODEREG_PARITY_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_COUNT_STATE_MASK , 23 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_COUNT_STATE_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_RUN_STATE_MASK , 24 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_RUN_STATE_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_THRES_STATE_MASK , 25 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_THRES_STATE_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_OVERFLOW_MASK , 26 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_OVERFLOW_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_SHIFTER_PARITY_MASK , 27 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SHIFTER_PARITY_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_SHIFTER_VALID_MASK , 28 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_SHIFTER_VALID_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_TIMEOUT_MASK , 29 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_TIMEOUT_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_F_SKITTER_READ_MASK , 30 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_F_SKITTER_READ_MASK ); +REG64_FLD( PEC_ERR_STATUS_REG_PCB_MASK , 31 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_PCB_MASK ); + REG64_FLD( PU_ESB_CI_BASE_BASE , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BASE ); REG64_FLD( PU_ESB_CI_BASE_BASE_LEN , 40 , SH_UNT , SH_ACS_SCOM , @@ -31482,6 +39881,210 @@ REG64_FLD( PU_NPU_CTL_FENCE_STATE_BRK4 , 4 , SH_UN REG64_FLD( PU_NPU_CTL_FENCE_STATE_BRK5 , 5 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK5 ); +REG64_FLD( PU_FI2C_CFG_PIBI2CM_PIB_SLAVE_ID , 0 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_PIBI2CM_PIB_SLAVE_ID ); +REG64_FLD( PU_FI2C_CFG_PIBI2CM_PIB_SLAVE_ID_LEN , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_PIBI2CM_PIB_SLAVE_ID_LEN ); +REG64_FLD( PU_FI2C_CFG_ECC_ENABLE , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_ECC_ENABLE ); +REG64_FLD( PU_FI2C_CFG_DISABLE_ECC_CHK , 17 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_DISABLE_ECC_CHK ); +REG64_FLD( PU_FI2C_CFG_I2C_SPEED_MUX , 18 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_I2C_SPEED_MUX ); +REG64_FLD( PU_FI2C_CFG_I2C_SPEED_MUX_LEN , 2 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_I2C_SPEED_MUX_LEN ); +REG64_FLD( PU_FI2C_CFG_BIT_RATE_DIVISOR_VALUE , 20 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_BIT_RATE_DIVISOR_VALUE ); +REG64_FLD( PU_FI2C_CFG_BIT_RATE_DIVISOR_VALUE_LEN , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_BIT_RATE_DIVISOR_VALUE_LEN ); +REG64_FLD( PU_FI2C_CFG_I2C_BUS_HELD_MODE_ENABLE , 36 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_I2C_BUS_HELD_MODE_ENABLE ); +REG64_FLD( PU_FI2C_CFG_PIPELINE_ENABLE , 37 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_PIPELINE_ENABLE ); +REG64_FLD( PU_FI2C_CFG_BACKUP_SEEPROM_SELECT , 38 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_BACKUP_SEEPROM_SELECT ); +REG64_FLD( PU_FI2C_CFG_FORCE_RESET , 39 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_FORCE_RESET ); +REG64_FLD( PU_FI2C_CFG_RESET_PIB , 40 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESET_PIB ); +REG64_FLD( PU_FI2C_CFG_DISABLE_TIMEOUT , 41 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_DISABLE_TIMEOUT ); +REG64_FLD( PU_FI2C_CFG_RESERVED_FOR_CONFIGS , 42 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_FOR_CONFIGS ); +REG64_FLD( PU_FI2C_CFG_RESERVED_FOR_CONFIGS_LEN , 18 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_FOR_CONFIGS_LEN ); + +REG64_FLD( PU_FI2C_SCFG0_REGISTER_VALID , 0 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_REGISTER_VALID ); +REG64_FLD( PU_FI2C_SCFG0_RESERVED_3 , 1 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_3 ); +REG64_FLD( PU_FI2C_SCFG0_RESERVED_4 , 2 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_4 ); +REG64_FLD( PU_FI2C_SCFG0_RESERVED_4_LEN , 2 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_4_LEN ); +REG64_FLD( PU_FI2C_SCFG0_RESERVED_5 , 4 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_5 ); +REG64_FLD( PU_FI2C_SCFG0_RESERVED_5_LEN , 4 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_5_LEN ); +REG64_FLD( PU_FI2C_SCFG0_DEVICE_ID , 8 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_DEVICE_ID ); +REG64_FLD( PU_FI2C_SCFG0_DEVICE_ID_LEN , 7 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_DEVICE_ID_LEN ); +REG64_FLD( PU_FI2C_SCFG0_ECC_ENABLE , 15 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_ECC_ENABLE ); +REG64_FLD( PU_FI2C_SCFG0_MEMORY_SIZE_IN_PPE_ADDR_MAP , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP ); +REG64_FLD( PU_FI2C_SCFG0_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN ); +REG64_FLD( PU_FI2C_SCFG0_START_SEEPROM_ADDRESS , 32 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_SEEPROM_ADDRESS ); +REG64_FLD( PU_FI2C_SCFG0_START_SEEPROM_ADDRESS_LEN , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_SEEPROM_ADDRESS_LEN ); +REG64_FLD( PU_FI2C_SCFG0_START_PPE_ADDR , 48 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_PPE_ADDR ); +REG64_FLD( PU_FI2C_SCFG0_START_PPE_ADDR_LEN , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_PPE_ADDR_LEN ); + +REG64_FLD( PU_FI2C_SCFG1_REGISTER_VALID , 0 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_REGISTER_VALID ); +REG64_FLD( PU_FI2C_SCFG1_RESERVED_6 , 1 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_6 ); +REG64_FLD( PU_FI2C_SCFG1_RESERVED_7 , 2 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_7 ); +REG64_FLD( PU_FI2C_SCFG1_RESERVED_7_LEN , 2 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_7_LEN ); +REG64_FLD( PU_FI2C_SCFG1_RESERVED_8 , 4 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_8 ); +REG64_FLD( PU_FI2C_SCFG1_RESERVED_8_LEN , 4 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_8_LEN ); +REG64_FLD( PU_FI2C_SCFG1_DEVICE_ID , 8 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_DEVICE_ID ); +REG64_FLD( PU_FI2C_SCFG1_DEVICE_ID_LEN , 7 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_DEVICE_ID_LEN ); +REG64_FLD( PU_FI2C_SCFG1_ECC_ENABLE , 15 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_ECC_ENABLE ); +REG64_FLD( PU_FI2C_SCFG1_MEMORY_SIZE_IN_PPE_ADDR_MAP , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP ); +REG64_FLD( PU_FI2C_SCFG1_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN ); +REG64_FLD( PU_FI2C_SCFG1_START_SEEPROM_ADDRESS , 32 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_SEEPROM_ADDRESS ); +REG64_FLD( PU_FI2C_SCFG1_START_SEEPROM_ADDRESS_LEN , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_SEEPROM_ADDRESS_LEN ); +REG64_FLD( PU_FI2C_SCFG1_START_PPE_ADDR , 48 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_PPE_ADDR ); +REG64_FLD( PU_FI2C_SCFG1_START_PPE_ADDR_LEN , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_PPE_ADDR_LEN ); + +REG64_FLD( PU_FI2C_SCFG2_REGISTER_VALID , 0 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_REGISTER_VALID ); +REG64_FLD( PU_FI2C_SCFG2_RESERVED_9 , 1 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_9 ); +REG64_FLD( PU_FI2C_SCFG2_RESERVED_10 , 2 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_10 ); +REG64_FLD( PU_FI2C_SCFG2_RESERVED_10_LEN , 2 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_10_LEN ); +REG64_FLD( PU_FI2C_SCFG2_RESERVED_11 , 4 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_11 ); +REG64_FLD( PU_FI2C_SCFG2_RESERVED_11_LEN , 4 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_11_LEN ); +REG64_FLD( PU_FI2C_SCFG2_DEVICE_ID , 8 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_DEVICE_ID ); +REG64_FLD( PU_FI2C_SCFG2_DEVICE_ID_LEN , 7 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_DEVICE_ID_LEN ); +REG64_FLD( PU_FI2C_SCFG2_ECC_ENABLE , 15 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_ECC_ENABLE ); +REG64_FLD( PU_FI2C_SCFG2_MEMORY_SIZE_IN_PPE_ADDR_MAP , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP ); +REG64_FLD( PU_FI2C_SCFG2_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN ); +REG64_FLD( PU_FI2C_SCFG2_START_SEEPROM_ADDRESS , 32 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_SEEPROM_ADDRESS ); +REG64_FLD( PU_FI2C_SCFG2_START_SEEPROM_ADDRESS_LEN , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_SEEPROM_ADDRESS_LEN ); +REG64_FLD( PU_FI2C_SCFG2_START_PPE_ADDR , 48 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_PPE_ADDR ); +REG64_FLD( PU_FI2C_SCFG2_START_PPE_ADDR_LEN , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_PPE_ADDR_LEN ); + +REG64_FLD( PU_FI2C_SCFG3_REGISTER_VALID , 0 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_REGISTER_VALID ); +REG64_FLD( PU_FI2C_SCFG3_RESERVED_12 , 1 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_12 ); +REG64_FLD( PU_FI2C_SCFG3_RESERVED_13 , 2 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_13 ); +REG64_FLD( PU_FI2C_SCFG3_RESERVED_13_LEN , 2 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_13_LEN ); +REG64_FLD( PU_FI2C_SCFG3_RESERVED_14 , 4 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_14 ); +REG64_FLD( PU_FI2C_SCFG3_RESERVED_14_LEN , 4 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_14_LEN ); +REG64_FLD( PU_FI2C_SCFG3_DEVICE_ID , 8 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_DEVICE_ID ); +REG64_FLD( PU_FI2C_SCFG3_DEVICE_ID_LEN , 7 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_DEVICE_ID_LEN ); +REG64_FLD( PU_FI2C_SCFG3_ECC_ENABLE , 15 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_ECC_ENABLE ); +REG64_FLD( PU_FI2C_SCFG3_MEMORY_SIZE_IN_PPE_ADDR_MAP , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP ); +REG64_FLD( PU_FI2C_SCFG3_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN ); +REG64_FLD( PU_FI2C_SCFG3_START_SEEPROM_ADDRESS , 32 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_SEEPROM_ADDRESS ); +REG64_FLD( PU_FI2C_SCFG3_START_SEEPROM_ADDRESS_LEN , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_SEEPROM_ADDRESS_LEN ); +REG64_FLD( PU_FI2C_SCFG3_START_PPE_ADDR , 48 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_PPE_ADDR ); +REG64_FLD( PU_FI2C_SCFG3_START_PPE_ADDR_LEN , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_START_PPE_ADDR_LEN ); + +REG64_FLD( PU_FI2C_STAT_PIB_RESPONSE_INFO , 0 , SH_UNT , SH_ACS_PPE , + SH_FLD_PIB_RESPONSE_INFO ); +REG64_FLD( PU_FI2C_STAT_PIB_RESPONSE_INFO_LEN , 3 , SH_UNT , SH_ACS_PPE , + SH_FLD_PIB_RESPONSE_INFO_LEN ); +REG64_FLD( PU_FI2C_STAT_I2CM_PIB_ERRORS , 3 , SH_UNT , SH_ACS_PPE , + SH_FLD_I2CM_PIB_ERRORS ); +REG64_FLD( PU_FI2C_STAT_I2CM_PIB_ERRORS_LEN , 6 , SH_UNT , SH_ACS_PPE , + SH_FLD_I2CM_PIB_ERRORS_LEN ); +REG64_FLD( PU_FI2C_STAT_I2CM_ECC_ERRORS , 9 , SH_UNT , SH_ACS_PPE , + SH_FLD_I2CM_ECC_ERRORS ); +REG64_FLD( PU_FI2C_STAT_I2CM_ECC_ERRORS_LEN , 3 , SH_UNT , SH_ACS_PPE , + SH_FLD_I2CM_ECC_ERRORS_LEN ); +REG64_FLD( PU_FI2C_STAT_I2CM_I2C_ERRORS , 12 , SH_UNT , SH_ACS_PPE , + SH_FLD_I2CM_I2C_ERRORS ); +REG64_FLD( PU_FI2C_STAT_I2CM_I2C_ERRORS_LEN , 7 , SH_UNT , SH_ACS_PPE , + SH_FLD_I2CM_I2C_ERRORS_LEN ); +REG64_FLD( PU_FI2C_STAT_ERR_ADDR_BEYOND_RANGE , 19 , SH_UNT , SH_ACS_PPE , + SH_FLD_ERR_ADDR_BEYOND_RANGE ); +REG64_FLD( PU_FI2C_STAT_ERR_ADDR_OVERLAP , 20 , SH_UNT , SH_ACS_PPE , + SH_FLD_ERR_ADDR_OVERLAP ); +REG64_FLD( PU_FI2C_STAT_PIB_ABORT , 21 , SH_UNT , SH_ACS_PPE , + SH_FLD_PIB_ABORT ); +REG64_FLD( PU_FI2C_STAT_TIMEOUT_ON_I2C_STATUS_RD , 22 , SH_UNT , SH_ACS_PPE , + SH_FLD_TIMEOUT_ON_I2C_STATUS_RD ); +REG64_FLD( PU_FI2C_STAT_RESERVED_FOR_ERRS , 23 , SH_UNT , SH_ACS_PPE , + SH_FLD_RESERVED_FOR_ERRS ); +REG64_FLD( PU_FI2C_STAT_RESERVED_FOR_ERRS_LEN , 9 , SH_UNT , SH_ACS_PPE , + SH_FLD_RESERVED_FOR_ERRS_LEN ); +REG64_FLD( PU_FI2C_STAT_LOCKED_PIBM_ADDR , 32 , SH_UNT , SH_ACS_PPE , + SH_FLD_LOCKED_PIBM_ADDR ); +REG64_FLD( PU_FI2C_STAT_LOCKED_PIBM_ADDR_LEN , 8 , SH_UNT , SH_ACS_PPE , + SH_FLD_LOCKED_PIBM_ADDR_LEN ); +REG64_FLD( PU_FI2C_STAT_LOCKED_FSM_RESET_ONGOING , 40 , SH_UNT , SH_ACS_PPE , + SH_FLD_LOCKED_FSM_RESET_ONGOING ); +REG64_FLD( PU_FI2C_STAT_RESERVED_FOR_ADDRESS , 41 , SH_UNT , SH_ACS_PPE , + SH_FLD_RESERVED_FOR_ADDRESS ); +REG64_FLD( PU_FI2C_STAT_RESERVED_FOR_ADDRESS_LEN , 2 , SH_UNT , SH_ACS_PPE , + SH_FLD_RESERVED_FOR_ADDRESS_LEN ); +REG64_FLD( PU_FI2C_STAT_LOCKED_FSM_STATE , 43 , SH_UNT , SH_ACS_PPE , + SH_FLD_LOCKED_FSM_STATE ); +REG64_FLD( PU_FI2C_STAT_LOCKED_FSM_STATE_LEN , 5 , SH_UNT , SH_ACS_PPE , + SH_FLD_LOCKED_FSM_STATE_LEN ); +REG64_FLD( PU_FI2C_STAT_LOCKED_SEEPROM_ADDRESS , 48 , SH_UNT , SH_ACS_PPE , + SH_FLD_LOCKED_SEEPROM_ADDRESS ); +REG64_FLD( PU_FI2C_STAT_LOCKED_SEEPROM_ADDRESS_LEN , 16 , SH_UNT , SH_ACS_PPE , + SH_FLD_LOCKED_SEEPROM_ADDRESS_LEN ); + REG64_FLD( PU_FIFO1_REGISTER_READ_B_FIFO_BITS_READ0_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_0 ); REG64_FLD( PU_FIFO1_REGISTER_READ_B_FIFO_BITS_READ0_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -31570,6 +40173,11 @@ REG64_FLD( PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3_LEN , 8 , SH_UN REG64_FLD( PU_FIFO4_REGISTER_READ_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); +REG64_FLD( CAPP_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_CAPP , SH_ACS_SCOM_RO , + SH_FLD_ACTION0 ); +REG64_FLD( CAPP_FIR_ACTION0_REG_ACTION0_LEN , 52 , SH_UNT_CAPP , SH_ACS_SCOM_RO , + SH_FLD_ACTION0_LEN ); + REG64_FLD( PEC_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_ACTION0 ); REG64_FLD( PEC_FIR_ACTION0_REG_ACTION0_LEN , 37 , SH_UNT_PEC , SH_ACS_SCOM_RO , @@ -31590,6 +40198,11 @@ REG64_FLD( _SM2_FIR_ACTION0_REG_1_1 , 0 , SH_UN REG64_FLD( _SM2_FIR_ACTION0_REG_1_1_LEN , 64 , SH_UNT__SM2 , SH_ACS_SCOM_RW , SH_FLD_1_LEN ); +REG64_FLD( CAPP_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_CAPP , SH_ACS_SCOM_RO , + SH_FLD_ACTION1 ); +REG64_FLD( CAPP_FIR_ACTION1_REG_ACTION1_LEN , 52 , SH_UNT_CAPP , SH_ACS_SCOM_RO , + SH_FLD_ACTION1_LEN ); + REG64_FLD( PEC_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_ACTION1 ); REG64_FLD( PEC_FIR_ACTION1_REG_ACTION1_LEN , 37 , SH_UNT_PEC , SH_ACS_SCOM_RO , @@ -31610,6 +40223,130 @@ REG64_FLD( _SM2_FIR_ACTION1_REG_1_1 , 0 , SH_UN REG64_FLD( _SM2_FIR_ACTION1_REG_1_1_LEN , 64 , SH_UNT__SM2 , SH_ACS_SCOM_RW , SH_FLD_1_LEN ); +REG64_FLD( PEC_FIR_MASK_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN0 ); +REG64_FLD( PEC_FIR_MASK_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN1 ); +REG64_FLD( PEC_FIR_MASK_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN2 ); +REG64_FLD( PEC_FIR_MASK_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN3 ); +REG64_FLD( PEC_FIR_MASK_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN4 ); +REG64_FLD( PEC_FIR_MASK_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN5 ); +REG64_FLD( PEC_FIR_MASK_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN6 ); +REG64_FLD( PEC_FIR_MASK_IN6_LEN , 20 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN6_LEN ); +REG64_FLD( PEC_FIR_MASK_IN26 , 26 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN26 ); + +REG64_FLD( CAPP_FIR_MASK_REG_BAR_PE , 0 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_BAR_PE ); +REG64_FLD( CAPP_FIR_MASK_REG_REGISTER_PE , 1 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_REGISTER_PE ); +REG64_FLD( CAPP_FIR_MASK_REG_MASTER_ARRAY_CE , 2 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_MASTER_ARRAY_CE ); +REG64_FLD( CAPP_FIR_MASK_REG_MASTER_ARRAY_UE , 3 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_MASTER_ARRAY_UE ); +REG64_FLD( CAPP_FIR_MASK_REG_TIMER_EXPIRED_RECOV_ERROR , 4 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TIMER_EXPIRED_RECOV_ERROR ); +REG64_FLD( CAPP_FIR_MASK_REG_TIMER_EXPIRED_XSTOP_ERROR , 5 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TIMER_EXPIRED_XSTOP_ERROR ); +REG64_FLD( CAPP_FIR_MASK_REG_PSL_CMD_UE , 6 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_PSL_CMD_UE ); +REG64_FLD( CAPP_FIR_MASK_REG_PSL_CMD_SUE , 7 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_PSL_CMD_SUE ); +REG64_FLD( CAPP_FIR_MASK_REG_SNOOP_ARRAY_CE , 8 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SNOOP_ARRAY_CE ); +REG64_FLD( CAPP_FIR_MASK_REG_SNOOP_ARRAY_UE , 9 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SNOOP_ARRAY_UE ); +REG64_FLD( CAPP_FIR_MASK_REG_RECOVERY_FAILED , 10 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_RECOVERY_FAILED ); +REG64_FLD( CAPP_FIR_MASK_REG_ILLEGAL_LPC_BAR_ACCESS , 11 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_ILLEGAL_LPC_BAR_ACCESS ); +REG64_FLD( CAPP_FIR_MASK_REG_XPT_RECOVERABLE_ERROR , 12 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_XPT_RECOVERABLE_ERROR ); +REG64_FLD( CAPP_FIR_MASK_REG_MASTER_RECOVERABLE_ERROR , 13 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_MASTER_RECOVERABLE_ERROR ); +REG64_FLD( CAPP_FIR_MASK_REG_SNOOPER_RECOVERABLE_ERROR , 14 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SNOOPER_RECOVERABLE_ERROR ); +REG64_FLD( CAPP_FIR_MASK_REG_SECURE_SCOM_ERROR , 15 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SECURE_SCOM_ERROR ); +REG64_FLD( CAPP_FIR_MASK_REG_MASTER_SYS_XSTOP_ERROR , 16 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_MASTER_SYS_XSTOP_ERROR ); +REG64_FLD( CAPP_FIR_MASK_REG_SNOOPER_SYS_XSTOP_ERROR , 17 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SNOOPER_SYS_XSTOP_ERROR ); +REG64_FLD( CAPP_FIR_MASK_REG_XPT_SYS_XSTOP_ERROR , 18 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_XPT_SYS_XSTOP_ERROR ); +REG64_FLD( CAPP_FIR_MASK_REG_MUOP_ERROR_1 , 19 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_MUOP_ERROR_1 ); +REG64_FLD( CAPP_FIR_MASK_REG_MUOP_ERROR_2 , 20 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_MUOP_ERROR_2 ); +REG64_FLD( CAPP_FIR_MASK_REG_MUOP_ERROR_3 , 21 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_MUOP_ERROR_3 ); +REG64_FLD( CAPP_FIR_MASK_REG_SUOP_ERROR_1 , 22 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SUOP_ERROR_1 ); +REG64_FLD( CAPP_FIR_MASK_REG_SUOP_ERROR_2 , 23 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SUOP_ERROR_2 ); +REG64_FLD( CAPP_FIR_MASK_REG_SUOP_ERROR_3 , 24 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SUOP_ERROR_3 ); +REG64_FLD( CAPP_FIR_MASK_REG_POWERBUS_MISC_ERROR , 25 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_POWERBUS_MISC_ERROR ); +REG64_FLD( CAPP_FIR_MASK_REG_POWERBUS_INTERFACE_PE , 26 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_POWERBUS_INTERFACE_PE ); +REG64_FLD( CAPP_FIR_MASK_REG_POWERBUS_DATA_HANG_ERROR , 27 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_POWERBUS_DATA_HANG_ERROR ); +REG64_FLD( CAPP_FIR_MASK_REG_POWERBUS_HANG_ERROR , 28 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_POWERBUS_HANG_ERROR ); +REG64_FLD( CAPP_FIR_MASK_REG_LD_CLASS_CMD_ADDR_ERR , 29 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_LD_CLASS_CMD_ADDR_ERR ); +REG64_FLD( CAPP_FIR_MASK_REG_ST_CLASS_CMD_ADDR_ERR , 30 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_ST_CLASS_CMD_ADDR_ERR ); +REG64_FLD( CAPP_FIR_MASK_REG_PHB_LINK_DOWN , 31 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_PHB_LINK_DOWN ); +REG64_FLD( CAPP_FIR_MASK_REG_LD_CLASS_CMD_FOREIGN_LINK_FAIL , 32 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_LD_CLASS_CMD_FOREIGN_LINK_FAIL ); +REG64_FLD( CAPP_FIR_MASK_REG_FOREIGN_LINK_HANG_ERROR , 33 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_FOREIGN_LINK_HANG_ERROR ); +REG64_FLD( CAPP_FIR_MASK_REG_XPT_POWERBUS_CE , 34 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_XPT_POWERBUS_CE ); +REG64_FLD( CAPP_FIR_MASK_REG_XPT_POWERBUS_UE , 35 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_XPT_POWERBUS_UE ); +REG64_FLD( CAPP_FIR_MASK_REG_XPT_POWERBUS_SUE , 36 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_XPT_POWERBUS_SUE ); +REG64_FLD( CAPP_FIR_MASK_REG_TLBI_TIMEOUT , 37 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TLBI_TIMEOUT ); +REG64_FLD( CAPP_FIR_MASK_REG_TLBI_SEQ_ERR , 38 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TLBI_SEQ_ERR ); +REG64_FLD( CAPP_FIR_MASK_REG_TLBI_BAD_OP_ERR , 39 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TLBI_BAD_OP_ERR ); +REG64_FLD( CAPP_FIR_MASK_REG_TLBI_SEQ_NUM_PARITY_ERR , 40 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TLBI_SEQ_NUM_PARITY_ERR ); +REG64_FLD( CAPP_FIR_MASK_REG_ST_CLASS_CMD_FOREIGN_LINK_FAIL , 41 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_ST_CLASS_CMD_FOREIGN_LINK_FAIL ); +REG64_FLD( CAPP_FIR_MASK_REG_TIME_BASE_ERR , 42 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TIME_BASE_ERR ); +REG64_FLD( CAPP_FIR_MASK_REG_TRANSPORT_INFORMATIONAL_ERR , 43 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TRANSPORT_INFORMATIONAL_ERR ); +REG64_FLD( CAPP_FIR_MASK_REG_APC_ARRAY_CMD_CE_ERPT , 44 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_APC_ARRAY_CMD_CE_ERPT ); +REG64_FLD( CAPP_FIR_MASK_REG_APC_ARRAY_CMD_UE_ERPT , 45 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_APC_ARRAY_CMD_UE_ERPT ); +REG64_FLD( CAPP_FIR_MASK_REG_PSL_CREDIT_TIMEOUT_ERR , 46 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_PSL_CREDIT_TIMEOUT_ERR ); +REG64_FLD( CAPP_FIR_MASK_REG_SPARE_2 , 47 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_2 ); +REG64_FLD( CAPP_FIR_MASK_REG_SPARE_3 , 48 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_3 ); +REG64_FLD( CAPP_FIR_MASK_REG_HYPERVISOR , 49 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_HYPERVISOR ); +REG64_FLD( CAPP_FIR_MASK_REG_SCOM_ERR2 , 50 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR2 ); +REG64_FLD( CAPP_FIR_MASK_REG_SCOM_ERR , 51 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR ); + REG64_FLD( PEC_FIR_MASK_REG_HSSCALERR , 0 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_HSSCALERR ); REG64_FLD( PEC_FIR_MASK_REG_HSSPLLAERR , 1 , SH_UNT_PEC , SH_ACS_SCOM2_OR , @@ -31727,6 +40464,111 @@ REG64_FLD( _SM2_FIR_MASK_REG_1_1 , 0 , SH_UN REG64_FLD( _SM2_FIR_MASK_REG_1_1_LEN , 64 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_1_LEN ); +REG64_FLD( CAPP_FIR_REG_BAR_PE , 0 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_BAR_PE ); +REG64_FLD( CAPP_FIR_REG_REGISTER_PE , 1 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_REGISTER_PE ); +REG64_FLD( CAPP_FIR_REG_MASTER_ARRAY_CE , 2 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_MASTER_ARRAY_CE ); +REG64_FLD( CAPP_FIR_REG_MASTER_ARRAY_UE , 3 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_MASTER_ARRAY_UE ); +REG64_FLD( CAPP_FIR_REG_TIMER_EXPIRED_RECOV_ERROR , 4 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TIMER_EXPIRED_RECOV_ERROR ); +REG64_FLD( CAPP_FIR_REG_TIMER_EXPIRED_XSTOP_ERROR , 5 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TIMER_EXPIRED_XSTOP_ERROR ); +REG64_FLD( CAPP_FIR_REG_PSL_CMD_UE , 6 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_PSL_CMD_UE ); +REG64_FLD( CAPP_FIR_REG_PSL_CMD_SUE , 7 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_PSL_CMD_SUE ); +REG64_FLD( CAPP_FIR_REG_SNOOP_ARRAY_CE , 8 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SNOOP_ARRAY_CE ); +REG64_FLD( CAPP_FIR_REG_SNOOP_ARRAY_UE , 9 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SNOOP_ARRAY_UE ); +REG64_FLD( CAPP_FIR_REG_RECOVERY_FAILED , 10 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_RECOVERY_FAILED ); +REG64_FLD( CAPP_FIR_REG_ILLEGAL_LPC_BAR_ACCESS , 11 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_ILLEGAL_LPC_BAR_ACCESS ); +REG64_FLD( CAPP_FIR_REG_XPT_RECOVERABLE_ERROR , 12 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_XPT_RECOVERABLE_ERROR ); +REG64_FLD( CAPP_FIR_REG_MASTER_RECOVERABLE_ERROR , 13 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_MASTER_RECOVERABLE_ERROR ); +REG64_FLD( CAPP_FIR_REG_SNOOPER_RECOVERABLE_ERROR , 14 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SNOOPER_RECOVERABLE_ERROR ); +REG64_FLD( CAPP_FIR_REG_SECURE_SCOM_ERROR , 15 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SECURE_SCOM_ERROR ); +REG64_FLD( CAPP_FIR_REG_MASTER_SYS_XSTOP_ERROR , 16 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_MASTER_SYS_XSTOP_ERROR ); +REG64_FLD( CAPP_FIR_REG_SNOOPER_SYS_XSTOP_ERROR , 17 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SNOOPER_SYS_XSTOP_ERROR ); +REG64_FLD( CAPP_FIR_REG_XPT_SYS_XSTOP_ERROR , 18 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_XPT_SYS_XSTOP_ERROR ); +REG64_FLD( CAPP_FIR_REG_MUOP_ERROR_1 , 19 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_MUOP_ERROR_1 ); +REG64_FLD( CAPP_FIR_REG_MUOP_ERROR_2 , 20 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_MUOP_ERROR_2 ); +REG64_FLD( CAPP_FIR_REG_MUOP_ERROR_3 , 21 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_MUOP_ERROR_3 ); +REG64_FLD( CAPP_FIR_REG_SUOP_ERROR_1 , 22 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SUOP_ERROR_1 ); +REG64_FLD( CAPP_FIR_REG_SUOP_ERROR_2 , 23 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SUOP_ERROR_2 ); +REG64_FLD( CAPP_FIR_REG_SUOP_ERROR_3 , 24 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SUOP_ERROR_3 ); +REG64_FLD( CAPP_FIR_REG_POWERBUS_MISC_ERROR , 25 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_POWERBUS_MISC_ERROR ); +REG64_FLD( CAPP_FIR_REG_POWERBUS_INTERFACE_PE , 26 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_POWERBUS_INTERFACE_PE ); +REG64_FLD( CAPP_FIR_REG_POWERBUS_DATA_HANG_ERROR , 27 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_POWERBUS_DATA_HANG_ERROR ); +REG64_FLD( CAPP_FIR_REG_POWERBUS_HANG_ERROR , 28 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_POWERBUS_HANG_ERROR ); +REG64_FLD( CAPP_FIR_REG_LD_CLASS_CMD_ADDR_ERR , 29 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_LD_CLASS_CMD_ADDR_ERR ); +REG64_FLD( CAPP_FIR_REG_ST_CLASS_CMD_ADDR_ERR , 30 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_ST_CLASS_CMD_ADDR_ERR ); +REG64_FLD( CAPP_FIR_REG_PHB_LINK_DOWN , 31 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_PHB_LINK_DOWN ); +REG64_FLD( CAPP_FIR_REG_LD_CLASS_CMD_FOREIGN_LINK_FAIL , 32 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_LD_CLASS_CMD_FOREIGN_LINK_FAIL ); +REG64_FLD( CAPP_FIR_REG_FOREIGN_LINK_HANG_ERROR , 33 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_FOREIGN_LINK_HANG_ERROR ); +REG64_FLD( CAPP_FIR_REG_XPT_POWERBUS_CE , 34 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_XPT_POWERBUS_CE ); +REG64_FLD( CAPP_FIR_REG_XPT_POWERBUS_UE , 35 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_XPT_POWERBUS_UE ); +REG64_FLD( CAPP_FIR_REG_XPT_POWERBUS_SUE , 36 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_XPT_POWERBUS_SUE ); +REG64_FLD( CAPP_FIR_REG_TLBI_TIMEOUT , 37 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TLBI_TIMEOUT ); +REG64_FLD( CAPP_FIR_REG_TLBI_SEQ_ERR , 38 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TLBI_SEQ_ERR ); +REG64_FLD( CAPP_FIR_REG_TLBI_BAD_OP_ERR , 39 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TLBI_BAD_OP_ERR ); +REG64_FLD( CAPP_FIR_REG_TLBI_SEQ_NUM_PARITY_ERR , 40 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TLBI_SEQ_NUM_PARITY_ERR ); +REG64_FLD( CAPP_FIR_REG_ST_CLASS_CMD_FOREIGN_LINK_FAIL , 41 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_ST_CLASS_CMD_FOREIGN_LINK_FAIL ); +REG64_FLD( CAPP_FIR_REG_TIME_BASE_ERR , 42 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TIME_BASE_ERR ); +REG64_FLD( CAPP_FIR_REG_TRANSPORT_INFORMATIONAL_ERR , 43 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_TRANSPORT_INFORMATIONAL_ERR ); +REG64_FLD( CAPP_FIR_REG_APC_ARRAY_CMD_CE_ERPT , 44 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_APC_ARRAY_CMD_CE_ERPT ); +REG64_FLD( CAPP_FIR_REG_APC_ARRAY_CMD_UE_ERPT , 45 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_APC_ARRAY_CMD_UE_ERPT ); +REG64_FLD( CAPP_FIR_REG_PSL_CREDIT_TIMEOUT_ERR , 46 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_PSL_CREDIT_TIMEOUT_ERR ); +REG64_FLD( CAPP_FIR_REG_SPARE_2 , 47 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_2 ); +REG64_FLD( CAPP_FIR_REG_HYPERVISOR , 48 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_HYPERVISOR ); +REG64_FLD( CAPP_FIR_REG_SPARE_3 , 49 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_3 ); +REG64_FLD( CAPP_FIR_REG_SCOM_ERR2 , 50 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR2 ); +REG64_FLD( CAPP_FIR_REG_SCOM_ERR , 51 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR ); + REG64_FLD( PU_FIR_REG_PSI_RESERVED0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED0 ); REG64_FLD( PU_FIR_REG_PSI_RESERVED1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , @@ -31764,82 +40606,108 @@ REG64_FLD( _SM0_FIR_REG_0_NTL_PRI_ERR , 9 , SH_UN SH_FLD_NTL_PRI_ERR ); REG64_FLD( _SM0_FIR_REG_0_NTL_LOGIC_ERR , 10 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_NTL_LOGIC_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_ARRAY_CE , 11 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_NTL_LMD_POISON , 11 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_NTL_LMD_POISON ); +REG64_FLD( _SM0_FIR_REG_0_NTL_ARRAY_DATA_SUE , 12 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_NTL_ARRAY_DATA_SUE ); +REG64_FLD( _SM0_FIR_REG_0_CTL_ARRAY_CE , 13 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_CTL_ARRAY_CE ); -REG64_FLD( _SM0_FIR_REG_0_CTL_PBUS_RECOV_ERR , 12 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_CTL_PBUS_RECOV_ERR , 14 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_CTL_PBUS_RECOV_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_RING_ERR , 13 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_CTL_RING_ERR , 15 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_CTL_RING_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_MMIO_ST_DATA_UE , 14 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_CTL_MMIO_ST_DATA_UE , 16 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_CTL_MMIO_ST_DATA_UE ); -REG64_FLD( _SM0_FIR_REG_0_RESERVED_4 , 15 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_RESERVED_4 ); -REG64_FLD( _SM0_FIR_REG_0_CTL_NVL_CFG_ERR , 16 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_CTL_PEF , 17 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_CTL_PEF ); +REG64_FLD( _SM0_FIR_REG_0_CTL_NVL_CFG_ERR , 18 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_CTL_NVL_CFG_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_NVL_FATAL_ERR , 17 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_CTL_NVL_FATAL_ERR , 19 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_CTL_NVL_FATAL_ERR ); -REG64_FLD( _SM0_FIR_REG_0_RESERVED_1 , 18 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_RESERVED_1 , 20 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_1 ); -REG64_FLD( _SM0_FIR_REG_0_CTL_ARRAY_UE , 19 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_CTL_ARRAY_UE , 21 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_CTL_ARRAY_UE ); -REG64_FLD( _SM0_FIR_REG_0_CTL_PBUS_PERR , 20 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_CTL_PBUS_PERR , 22 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_CTL_PBUS_PERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_PBUS_FATAL_ERR , 21 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_CTL_PBUS_FATAL_ERR , 23 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_CTL_PBUS_FATAL_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_PBUS_CONFIG_ERR , 22 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_CTL_PBUS_CONFIG_ERR , 24 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_CTL_PBUS_CONFIG_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_FWD_PROGRESS_ERR , 23 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_CTL_FWD_PROGRESS_ERR , 25 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_CTL_FWD_PROGRESS_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_LOGIC_ERR , 24 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_CTL_LOGIC_ERR , 26 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_CTL_LOGIC_ERR ); -REG64_FLD( _SM0_FIR_REG_0_CTL_PEST_DIS , 25 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_CTL_PEST_DIS , 27 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_CTL_PEST_DIS ); -REG64_FLD( _SM0_FIR_REG_0_DAT_DATA_BE_UE , 26 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_CTL_RSVD_15 , 28 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_CTL_RSVD_15 ); +REG64_FLD( _SM0_FIR_REG_0_DAT_DATA_BE_UE , 29 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_DAT_DATA_BE_UE ); -REG64_FLD( _SM0_FIR_REG_0_DAT_DATA_BE_CE , 27 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_DAT_DATA_BE_CE , 30 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_DAT_DATA_BE_CE ); -REG64_FLD( _SM0_FIR_REG_0_DAT_DATA_BE_PERR , 28 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_DAT_DATA_BE_PERR , 31 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_DAT_DATA_BE_PERR ); -REG64_FLD( _SM0_FIR_REG_0_DAT_CREG_PERR , 29 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_DAT_CREG_PERR , 32 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_DAT_CREG_PERR ); -REG64_FLD( _SM0_FIR_REG_0_DAT_RTAG_PERR , 30 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_DAT_RTAG_PERR , 33 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_DAT_RTAG_PERR ); -REG64_FLD( _SM0_FIR_REG_0_DAT_STATE_PERR , 31 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_DAT_STATE_PERR , 34 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_DAT_STATE_PERR ); -REG64_FLD( _SM0_FIR_REG_0_DAT_LOGIC_ERR , 32 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_DAT_LOGIC_ERR , 35 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_DAT_LOGIC_ERR ); -REG64_FLD( _SM0_FIR_REG_0_DAT_DATA_BE_CE_OVERTHRESH , 33 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_DAT_DATA_BE_CE_OVERTHRESH ); -REG64_FLD( _SM0_FIR_REG_0_XTS_INT , 34 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_DAT_DATA_BE_SUE , 36 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_DAT_DATA_BE_SUE ); +REG64_FLD( _SM0_FIR_REG_0_DAT_PBRX_SUE , 37 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_DAT_PBRX_SUE ); +REG64_FLD( _SM0_FIR_REG_0_DAT_RSVD_9 , 38 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_DAT_RSVD_9 ); +REG64_FLD( _SM0_FIR_REG_0_DAT_RSVD_10 , 39 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_DAT_RSVD_10 ); +REG64_FLD( _SM0_FIR_REG_0_XTS_INT , 40 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_XTS_INT ); -REG64_FLD( _SM0_FIR_REG_0_XTS_SRAM_CE , 35 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_XTS_SRAM_CE , 41 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_XTS_SRAM_CE ); -REG64_FLD( _SM0_FIR_REG_0_XTS_SRAM_UE , 36 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_XTS_SRAM_UE , 42 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_XTS_SRAM_UE ); -REG64_FLD( _SM0_FIR_REG_0_XTS_PROTOCOL_CE , 37 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_XTS_PROTOCOL_CE , 43 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_XTS_PROTOCOL_CE ); -REG64_FLD( _SM0_FIR_REG_0_XTS_PROTOCOL_UE , 38 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_XTS_PROTOCOL_UE , 44 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_XTS_PROTOCOL_UE ); -REG64_FLD( _SM0_FIR_REG_0_XTS_PBUS_PROTOCOL , 39 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM0_FIR_REG_0_XTS_PBUS_PROTOCOL , 45 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_XTS_PBUS_PROTOCOL ); -REG64_FLD( _SM0_FIR_REG_0_MISC_RING_ERR , 40 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_MISC_RING_ERR ); -REG64_FLD( _SM0_FIR_REG_0_MISC_INT_RA_PERR , 41 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_MISC_INT_RA_PERR ); -REG64_FLD( _SM0_FIR_REG_0_MISC_DA_ADDR_PERR , 42 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_MISC_DA_ADDR_PERR ); -REG64_FLD( _SM0_FIR_REG_0_MISC_CTRL_PERR , 43 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_MISC_CTRL_PERR ); -REG64_FLD( _SM0_FIR_REG_0_MISC_NMMU_ERR , 44 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_MISC_NMMU_ERR ); -REG64_FLD( _SM0_FIR_REG_0_MISC_SCOMSAT00_ERR , 45 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_MISC_SCOMSAT00_ERR ); -REG64_FLD( _SM0_FIR_REG_0_MISC_SCOMSAT01_ERR , 46 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_MISC_SCOMSAT01_ERR ); -REG64_FLD( _SM0_FIR_REG_0_IDIAL_REG0_RSVD0 , 47 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_IDIAL_REG0_RSVD0 ); -REG64_FLD( _SM0_FIR_REG_0_IDIAL_REG0_RSVD0_LEN , 15 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , - SH_FLD_IDIAL_REG0_RSVD0_LEN ); +REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_6 , 46 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_XTS_RSVD_6 ); +REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_7 , 47 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_XTS_RSVD_7 ); +REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_8 , 48 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_XTS_RSVD_8 ); +REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_9 , 49 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_XTS_RSVD_9 ); +REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_10 , 50 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_XTS_RSVD_10 ); +REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_11 , 51 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_XTS_RSVD_11 ); +REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_12 , 52 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_XTS_RSVD_12 ); +REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_13 , 53 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_XTS_RSVD_13 ); +REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_14 , 54 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_XTS_RSVD_14 ); +REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_15 , 55 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_XTS_RSVD_15 ); +REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_16 , 56 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_XTS_RSVD_16 ); +REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_17 , 57 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_XTS_RSVD_17 ); +REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_18 , 58 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_XTS_RSVD_18 ); +REG64_FLD( _SM0_FIR_REG_0_XTS_RSVD_19 , 59 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_XTS_RSVD_19 ); +REG64_FLD( _SM0_FIR_REG_0_SCOMSAT00_ERR , 60 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SCOMSAT00_ERR ); +REG64_FLD( _SM0_FIR_REG_0_SCOMSAT01_ERR , 61 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SCOMSAT01_ERR ); REG64_FLD( _SM0_FIR_REG_0_PARITY_ERR2 , 62 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR2 ); REG64_FLD( _SM0_FIR_REG_0_PARITY_ERR , 63 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , @@ -31869,50 +40737,106 @@ REG64_FLD( _SM2_FIR_REG_1_NDL_BRK5_STALL , 10 , SH_UN SH_FLD_NDL_BRK5_STALL ); REG64_FLD( _SM2_FIR_REG_1_NDL_BRK5_NOSTALL , 11 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK5_NOSTALL ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TVT_ENTRY_INVALID , 12 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_MISC_RING_ERR , 12 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_MISC_RING_ERR ); +REG64_FLD( _SM2_FIR_REG_1_MISC_INT_RA_PERR , 13 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_MISC_INT_RA_PERR ); +REG64_FLD( _SM2_FIR_REG_1_MISC_DA_ADDR_PERR , 14 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_MISC_DA_ADDR_PERR ); +REG64_FLD( _SM2_FIR_REG_1_MISC_CTRL_PERR , 15 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_MISC_CTRL_PERR ); +REG64_FLD( _SM2_FIR_REG_1_MISC_NMMU_ERR , 16 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_MISC_NMMU_ERR ); +REG64_FLD( _SM2_FIR_REG_1_ATS_TVT_ENTRY_INVALID , 17 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_TVT_ENTRY_INVALID ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TVT_ADDR_RANGE_ERR , 13 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_TVT_ADDR_RANGE_ERR , 18 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_TVT_ADDR_RANGE_ERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TCE_PAGE_ACCESS_CA_ERR , 14 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_TCE_PAGE_ACCESS_CA_ERR , 19 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_TCE_PAGE_ACCESS_CA_ERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TCE_CACHE_MULT_HIT_ERR , 15 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_TCE_CACHE_MULT_HIT_ERR , 20 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_TCE_CACHE_MULT_HIT_ERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TCE_PAGE_ACCESS_TW_ERR , 16 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_TCE_PAGE_ACCESS_TW_ERR , 21 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_TCE_PAGE_ACCESS_TW_ERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TCE_REQ_TO_ERR , 17 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_TCE_REQ_TO_ERR , 22 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_TCE_REQ_TO_ERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TCD_PERR , 18 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_TCD_PERR , 23 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_TCD_PERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TDR_PERR , 19 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_TDR_PERR , 24 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_TDR_PERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_AT_EA_UE , 20 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_AT_EA_UE , 25 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_EA_UE ); -REG64_FLD( _SM2_FIR_REG_1_ATS_AT_EA_CE , 21 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_AT_EA_CE , 26 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_EA_CE ); -REG64_FLD( _SM2_FIR_REG_1_ATS_AT_TDRMEM_UE , 22 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_AT_TDRMEM_UE , 27 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_TDRMEM_UE ); -REG64_FLD( _SM2_FIR_REG_1_ATS_AT_TDRMEM_CE , 23 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_AT_TDRMEM_CE , 28 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_TDRMEM_CE ); -REG64_FLD( _SM2_FIR_REG_1_ATS_AT_RSPOUT_UE , 24 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_AT_RSPOUT_UE , 29 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_RSPOUT_UE ); -REG64_FLD( _SM2_FIR_REG_1_ATS_AT_RSPOUT_CE , 25 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_AT_RSPOUT_CE , 30 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_RSPOUT_CE ); -REG64_FLD( _SM2_FIR_REG_1_ATS_TVT_PERR , 26 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_TVT_PERR , 31 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_TVT_PERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_IODA_ADDR_PERR , 27 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_IODA_ADDR_PERR , 32 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_IODA_ADDR_PERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_NPU_CTRL_PERR , 28 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_NPU_CTRL_PERR , 33 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_NPU_CTRL_PERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_NPU_TOR_PERR , 29 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_NPU_TOR_PERR , 34 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_NPU_TOR_PERR ); -REG64_FLD( _SM2_FIR_REG_1_ATS_INVAL_IODA_TBL_SEL , 30 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , +REG64_FLD( _SM2_FIR_REG_1_ATS_INVAL_IODA_TBL_SEL , 35 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_ATS_INVAL_IODA_TBL_SEL ); -REG64_FLD( _SM2_FIR_REG_1_ATS_RSPOUT_ADDR_ERR , 31 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , - SH_FLD_ATS_RSPOUT_ADDR_ERR ); -REG64_FLD( _SM2_FIR_REG_1_IDIAL_REG1_RSVD0 , 32 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , - SH_FLD_IDIAL_REG1_RSVD0 ); -REG64_FLD( _SM2_FIR_REG_1_IDIAL_REG1_RSVD0_LEN , 30 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , - SH_FLD_IDIAL_REG1_RSVD0_LEN ); +REG64_FLD( _SM2_FIR_REG_1_ATS_RSVD_19 , 36 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_ATS_RSVD_19 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_37 , 37 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_37 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_38 , 38 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_38 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_39 , 39 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_39 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_40 , 40 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_40 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_41 , 41 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_41 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_42 , 42 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_42 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_43 , 43 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_43 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_44 , 44 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_44 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_45 , 45 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_45 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_46 , 46 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_46 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_47 , 47 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_47 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_48 , 48 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_48 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_49 , 49 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_49 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_50 , 50 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_50 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_51 , 51 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_51 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_52 , 52 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_52 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_53 , 53 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_53 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_54 , 54 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_54 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_55 , 55 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_55 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_56 , 56 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_56 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_57 , 57 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_57 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_58 , 58 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_58 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_59 , 59 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_59 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_60 , 60 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_60 ); +REG64_FLD( _SM2_FIR_REG_1_FIR1_RSVD_61 , 61 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , + SH_FLD_FIR1_RSVD_61 ); REG64_FLD( _SM2_FIR_REG_1_PARITY_ERR2 , 62 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR2 ); REG64_FLD( _SM2_FIR_REG_1_PARITY_ERR , 63 , SH_UNT__SM2 , SH_ACS_SCOM2_OR , @@ -32008,6 +40932,16 @@ REG64_FLD( _SM2_FIR_WOF_REG_1_1 , 0 , SH_UN REG64_FLD( _SM2_FIR_WOF_REG_1_1_LEN , 64 , SH_UNT__SM2 , SH_ACS_SCOM_WCLRREG, SH_FLD_1_LEN ); +REG64_FLD( CAPP_FLUSHCPIG_FLUSH_CP_IG_STATE_MAP , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FLUSH_CP_IG_STATE_MAP ); +REG64_FLD( CAPP_FLUSHCPIG_FLUSH_CP_IG_STATE_MAP_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FLUSH_CP_IG_STATE_MAP_LEN ); + +REG64_FLD( CAPP_FLUSHSHUE_FLUSH_SUE_STATE_MAP , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FLUSH_SUE_STATE_MAP ); +REG64_FLD( CAPP_FLUSHSHUE_FLUSH_SUE_STATE_MAP_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_FLUSH_SUE_STATE_MAP_LEN ); + REG64_FLD( PU_NPU_CTL_FREEZE_0_CONFIG_0 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( PU_NPU_CTL_FREEZE_0_CONFIG_0_LEN , 64 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , @@ -32350,8 +41284,6 @@ REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); -REG64_FLD( PU_GPE0_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_XISIB_PIB_IFETCH_PENDING ); REG64_FLD( PU_GPE0_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , @@ -32397,25 +41329,6 @@ REG64_FLD( PU_GPE0_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PU_GPE0_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); -REG64_FLD( PU_GPE0_MIB_XISIB_PIB_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_ADDR ); -REG64_FLD( PU_GPE0_MIB_XISIB_PIB_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_ADDR_LEN ); -REG64_FLD( PU_GPE0_MIB_XISIB_PIB_R_NW , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_R_NW ); -REG64_FLD( PU_GPE0_MIB_XISIB_PIB_BUSY , 33 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_BUSY ); -REG64_FLD( PU_GPE0_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_IMPRECISE_ERROR_PENDING ); -REG64_FLD( PU_GPE0_MIB_XISIB_PIB_RSP_INFO , 49 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_RSP_INFO ); -REG64_FLD( PU_GPE0_MIB_XISIB_PIB_RSP_INFO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_RSP_INFO_LEN ); -REG64_FLD( PU_GPE0_MIB_XISIB_PIB_IFETCH_PENDING , 62 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_IFETCH_PENDING ); -REG64_FLD( PU_GPE0_MIB_XISIB_PIB_DATAOP_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_DATAOP_PENDING ); - REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , @@ -32587,8 +41500,6 @@ REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); -REG64_FLD( PU_GPE1_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_XISIB_PIB_IFETCH_PENDING ); REG64_FLD( PU_GPE1_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , @@ -32634,25 +41545,6 @@ REG64_FLD( PU_GPE1_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PU_GPE1_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); -REG64_FLD( PU_GPE1_MIB_XISIB_PIB_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_ADDR ); -REG64_FLD( PU_GPE1_MIB_XISIB_PIB_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_ADDR_LEN ); -REG64_FLD( PU_GPE1_MIB_XISIB_PIB_R_NW , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_R_NW ); -REG64_FLD( PU_GPE1_MIB_XISIB_PIB_BUSY , 33 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_BUSY ); -REG64_FLD( PU_GPE1_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_IMPRECISE_ERROR_PENDING ); -REG64_FLD( PU_GPE1_MIB_XISIB_PIB_RSP_INFO , 49 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_RSP_INFO ); -REG64_FLD( PU_GPE1_MIB_XISIB_PIB_RSP_INFO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_RSP_INFO_LEN ); -REG64_FLD( PU_GPE1_MIB_XISIB_PIB_IFETCH_PENDING , 62 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_IFETCH_PENDING ); -REG64_FLD( PU_GPE1_MIB_XISIB_PIB_DATAOP_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_DATAOP_PENDING ); - REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , @@ -32824,8 +41716,6 @@ REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); -REG64_FLD( PU_GPE2_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_XISIB_PIB_IFETCH_PENDING ); REG64_FLD( PU_GPE2_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , @@ -32871,25 +41761,6 @@ REG64_FLD( PU_GPE2_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PU_GPE2_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); -REG64_FLD( PU_GPE2_MIB_XISIB_PIB_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_ADDR ); -REG64_FLD( PU_GPE2_MIB_XISIB_PIB_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_ADDR_LEN ); -REG64_FLD( PU_GPE2_MIB_XISIB_PIB_R_NW , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_R_NW ); -REG64_FLD( PU_GPE2_MIB_XISIB_PIB_BUSY , 33 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_BUSY ); -REG64_FLD( PU_GPE2_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_IMPRECISE_ERROR_PENDING ); -REG64_FLD( PU_GPE2_MIB_XISIB_PIB_RSP_INFO , 49 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_RSP_INFO ); -REG64_FLD( PU_GPE2_MIB_XISIB_PIB_RSP_INFO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_RSP_INFO_LEN ); -REG64_FLD( PU_GPE2_MIB_XISIB_PIB_IFETCH_PENDING , 62 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_IFETCH_PENDING ); -REG64_FLD( PU_GPE2_MIB_XISIB_PIB_DATAOP_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_DATAOP_PENDING ); - REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , @@ -33061,8 +41932,6 @@ REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); -REG64_FLD( PU_GPE3_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_XISIB_PIB_IFETCH_PENDING ); REG64_FLD( PU_GPE3_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , @@ -33108,25 +41977,6 @@ REG64_FLD( PU_GPE3_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PU_GPE3_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); -REG64_FLD( PU_GPE3_MIB_XISIB_PIB_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_ADDR ); -REG64_FLD( PU_GPE3_MIB_XISIB_PIB_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_ADDR_LEN ); -REG64_FLD( PU_GPE3_MIB_XISIB_PIB_R_NW , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_R_NW ); -REG64_FLD( PU_GPE3_MIB_XISIB_PIB_BUSY , 33 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_BUSY ); -REG64_FLD( PU_GPE3_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_IMPRECISE_ERROR_PENDING ); -REG64_FLD( PU_GPE3_MIB_XISIB_PIB_RSP_INFO , 49 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_RSP_INFO ); -REG64_FLD( PU_GPE3_MIB_XISIB_PIB_RSP_INFO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_RSP_INFO_LEN ); -REG64_FLD( PU_GPE3_MIB_XISIB_PIB_IFETCH_PENDING , 62 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_IFETCH_PENDING ); -REG64_FLD( PU_GPE3_MIB_XISIB_PIB_DATAOP_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_DATAOP_PENDING ); - REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , @@ -33181,509 +42031,693 @@ REG64_FLD( PU_GPE3_PPE_XIXCR_XCR , 1 , SH_UN REG64_FLD( PU_GPE3_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU0_SM0_GPU0_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU1_SM2_GPU0_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU2_SM3_GPU0_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU1_SM3_GPU0_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU0_SM3_GPU0_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU1_SM1_GPU0_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU2_SM2_GPU0_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU2_SM1_GPU0_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU0_SM2_GPU0_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU2_SM0_GPU0_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU0_SM1_GPU0_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU1_SM0_GPU0_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU0_SM0_GPU1_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU1_SM2_GPU1_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU2_SM3_GPU1_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU1_SM3_GPU1_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU0_SM3_GPU1_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU1_SM1_GPU1_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU2_SM2_GPU1_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU2_SM1_GPU1_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU0_SM2_GPU1_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU2_SM0_GPU1_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU0_SM1_GPU1_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); - -REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_GRANULE , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_GRANULE ); -REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE ); -REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MEMTYPE_LEN ); -REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_ADDR , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_SIZE , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE ); -REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_SIZE_LEN ); -REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_MODE , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE ); -REG64_FLD( PU_NPU1_SM0_GPU1_BAR_CONFIG_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_MODE_LEN ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ENABLE ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE_LEN ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE_LEN ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED_LEN ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ENABLE ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE_LEN ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE_LEN ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED_LEN ); + +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ENABLE ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE_LEN ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE_LEN ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED_LEN ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ENABLE ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE_LEN ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE_LEN ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED_LEN ); + +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ENABLE ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE_LEN ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE_LEN ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED_LEN ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ENABLE ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE_LEN ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE_LEN ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED_LEN ); + +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ENABLE ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE_LEN ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE_LEN ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED_LEN ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ENABLE ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE_LEN ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE_LEN ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED_LEN ); + +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ENABLE ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE_LEN ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE_LEN ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED_LEN ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ENABLE ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE_LEN ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE_LEN ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED_LEN ); + +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ENABLE ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE_LEN ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE_LEN ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED_LEN ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ENABLE ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE_LEN ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE_LEN ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED_LEN ); + +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ENABLE ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE_LEN ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE_LEN ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED_LEN ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ENABLE ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE_LEN ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE_LEN ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED_LEN ); + +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ENABLE ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE_LEN ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE_LEN ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED_LEN ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ENABLE ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE_LEN ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE_LEN ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED_LEN ); + +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ENABLE ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE_LEN ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE_LEN ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED_LEN ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ENABLE ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE_LEN ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE_LEN ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED_LEN ); + +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ENABLE ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE_LEN ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE_LEN ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED_LEN ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ENABLE ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE_LEN ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE_LEN ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED_LEN ); + +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ENABLE ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE_LEN ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE_LEN ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED_LEN ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ENABLE ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE_LEN ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE_LEN ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED_LEN ); + +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ENABLE ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_GRANULE , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_GRANULE ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_ADDR , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_SIZE , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_SIZE_LEN ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MODE , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_MODE_LEN ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_RESERVED , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU0_RESERVED_LEN ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ENABLE ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_GRANULE , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_GRANULE ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_ADDR , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_SIZE , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_SIZE_LEN ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MODE , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_MODE_LEN ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_RESERVED , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED ); +REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_RESERVED_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_GPU1_RESERVED_LEN ); + +REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN0 ); +REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN1 ); +REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN2 ); +REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN3 ); +REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN4 ); +REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN5 ); +REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN6 ); +REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN7 ); +REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN8 ); +REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN9 ); +REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN10 ); +REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN11 ); + +REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN0 ); +REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN1 ); +REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN2 ); +REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN3 ); +REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN4 ); +REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN5 ); +REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN6 ); +REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN7 ); +REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN8 ); +REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN9 ); +REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN10 ); +REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN11 ); + +REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN0 ); +REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN1 ); +REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN2 ); +REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN3 ); +REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN4 ); +REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN5 ); +REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN6 ); +REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN7 ); +REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN8 ); +REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN9 ); +REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN10 ); +REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN11 ); + +REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP_IN0 ); +REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP_IN1 ); +REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP_IN2 ); +REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP_IN3 ); +REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP_IN4 ); +REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP_IN5 ); +REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP_IN6 ); +REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP_IN7 ); +REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP_IN8 ); +REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP_IN9 ); +REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP_IN10 ); +REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GXSTP_IN11 ); REG64_FLD( PU_GZIP_CONTROL_REG_DISABLE_NEAR_HISTORY , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_NEAR_HISTORY ); @@ -33792,6 +42826,55 @@ REG64_FLD( PU_GZIP_MAX_BYTE_CNT_TARGET_DDE , 19 , SH_UN REG64_FLD( PU_GZIP_MAX_BYTE_CNT_TARGET_DDE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TARGET_DDE_LEN ); +REG64_FLD( PEC_HANG_PULSE_0_REG_0 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_0 ); +REG64_FLD( PEC_HANG_PULSE_0_REG_0_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_0_LEN ); +REG64_FLD( PEC_HANG_PULSE_0_REG_SUPPRESS , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_SUPPRESS ); + +REG64_FLD( PEC_HANG_PULSE_1_REG_1 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_1 ); +REG64_FLD( PEC_HANG_PULSE_1_REG_1_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_1_LEN ); +REG64_FLD( PEC_HANG_PULSE_1_REG_SUPPRESS , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_SUPPRESS ); + +REG64_FLD( PEC_HANG_PULSE_2_REG_2 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_2 ); +REG64_FLD( PEC_HANG_PULSE_2_REG_2_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_2_LEN ); +REG64_FLD( PEC_HANG_PULSE_2_REG_SUPPRESS , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_SUPPRESS ); + +REG64_FLD( PEC_HANG_PULSE_3_REG_3 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_3 ); +REG64_FLD( PEC_HANG_PULSE_3_REG_3_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_3_LEN ); +REG64_FLD( PEC_HANG_PULSE_3_REG_SUPPRESS , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_SUPPRESS ); + +REG64_FLD( PEC_HANG_PULSE_4_REG_4 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_4 ); +REG64_FLD( PEC_HANG_PULSE_4_REG_4_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_4_LEN ); +REG64_FLD( PEC_HANG_PULSE_4_REG_SUPPRESS , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_SUPPRESS ); + +REG64_FLD( PEC_HANG_PULSE_5_REG_5 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_5 ); +REG64_FLD( PEC_HANG_PULSE_5_REG_5_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_5_LEN ); +REG64_FLD( PEC_HANG_PULSE_5_REG_SUPPRESS , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_SUPPRESS ); + +REG64_FLD( PEC_HANG_PULSE_6_REG_6 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_6 ); +REG64_FLD( PEC_HANG_PULSE_6_REG_6_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_6_LEN ); +REG64_FLD( PEC_HANG_PULSE_6_REG_SUPPRESS , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_SUPPRESS ); + REG64_FLD( PU_HCA_BAR_ADDR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR ); REG64_FLD( PU_HCA_BAR_ADDR_LEN , 24 , SH_UNT , SH_ACS_SCOM_RW , @@ -33857,6 +42940,9 @@ REG64_FLD( PU_HCA_REF_BAR_ADDR_LEN , 25 , SH_UN REG64_FLD( PU_HCA_REF_BAR_VALID , 63 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); +REG64_FLD( PEC_HEARTBEAT_REG_DEAD , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DEAD ); + REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -34253,6 +43339,58 @@ REG64_FLD( PU_NPU1_SM0_HIGH_WATER_RESERVED1 , 42 , SH_UN REG64_FLD( PU_NPU1_SM0_HIGH_WATER_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); +REG64_FLD( PEC_HOSTATTN_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN0 ); +REG64_FLD( PEC_HOSTATTN_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN1 ); +REG64_FLD( PEC_HOSTATTN_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN2 ); +REG64_FLD( PEC_HOSTATTN_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN3 ); +REG64_FLD( PEC_HOSTATTN_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN4 ); +REG64_FLD( PEC_HOSTATTN_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN5 ); +REG64_FLD( PEC_HOSTATTN_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN6 ); +REG64_FLD( PEC_HOSTATTN_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN7 ); +REG64_FLD( PEC_HOSTATTN_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN8 ); +REG64_FLD( PEC_HOSTATTN_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN9 ); +REG64_FLD( PEC_HOSTATTN_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN10 ); +REG64_FLD( PEC_HOSTATTN_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN11 ); +REG64_FLD( PEC_HOSTATTN_IN12 , 12 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN12 ); +REG64_FLD( PEC_HOSTATTN_IN13 , 13 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN13 ); +REG64_FLD( PEC_HOSTATTN_IN14 , 14 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN14 ); +REG64_FLD( PEC_HOSTATTN_IN15 , 15 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN15 ); +REG64_FLD( PEC_HOSTATTN_IN16 , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN16 ); +REG64_FLD( PEC_HOSTATTN_IN17 , 17 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN17 ); +REG64_FLD( PEC_HOSTATTN_IN18 , 18 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN18 ); +REG64_FLD( PEC_HOSTATTN_IN19 , 19 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN19 ); +REG64_FLD( PEC_HOSTATTN_IN20 , 20 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN20 ); +REG64_FLD( PEC_HOSTATTN_IN21 , 21 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN21 ); +REG64_FLD( PEC_HOSTATTN_IN22 , 22 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN22 ); + +REG64_FLD( PEC_HOSTATTN_MASK_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN ); +REG64_FLD( PEC_HOSTATTN_MASK_IN_LEN , 22 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN_LEN ); + REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO , 0 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_OPER_HANG_DIV_RATIO ); REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO_LEN , 5 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , @@ -35275,6 +44413,20 @@ REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_DEST1 , 24 , SH_UN REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); +REG64_FLD( PEC_INJECT_REG_THERM_TRIP , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_THERM_TRIP ); +REG64_FLD( PEC_INJECT_REG_THERM_TRIP_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_THERM_TRIP_LEN ); +REG64_FLD( PEC_INJECT_REG_THERM_MODE , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_THERM_MODE ); +REG64_FLD( PEC_INJECT_REG_THERM_MODE_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_THERM_MODE_LEN ); + +REG64_FLD( PHB_INTBAR_REG_PE_INT_BAR , 0 , SH_UNT_PHB , SH_ACS_SCOM , + SH_FLD_PE_INT_BAR ); +REG64_FLD( PHB_INTBAR_REG_PE_INT_BAR_LEN , 28 , SH_UNT_PHB , SH_ACS_SCOM , + SH_FLD_PE_INT_BAR_LEN ); + REG64_FLD( PU_INTERRUPTS_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_INTERRUPTS_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , @@ -35474,6 +44626,16 @@ REG64_FLD( PU_NPU_CTL_INT_BAR_CONFIG , 0 , SH_UN REG64_FLD( PU_NPU_CTL_INT_BAR_CONFIG_LEN , 39 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_LEN ); +REG64_FLD( PU_INT_CQ_ACTION0_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION0 ); +REG64_FLD( PU_INT_CQ_ACTION0_ACTION0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION0_LEN ); + +REG64_FLD( PU_INT_CQ_ACTION1_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION1 ); +REG64_FLD( PU_INT_CQ_ACTION1_ACTION1_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION1_LEN ); + REG64_FLD( PU_INT_CQ_AIB_CTL_DIS_ECCCHK_IN , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIS_ECCCHK_IN ); REG64_FLD( PU_INT_CQ_AIB_CTL_EXTRA_CMD_SPACING_0_2 , 1 , SH_UNT , SH_ACS_SCOM , @@ -35496,10 +44658,12 @@ REG64_FLD( PU_INT_CQ_AIB_CTL_PRIORITY_LIMIT_0_3 , 16 , SH_UN SH_FLD_PRIORITY_LIMIT_0_3 ); REG64_FLD( PU_INT_CQ_AIB_CTL_PRIORITY_LIMIT_0_3_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LIMIT_0_3_LEN ); -REG64_FLD( PU_INT_CQ_AIB_CTL_RESERVED_20_31 , 20 , SH_UNT , SH_ACS_SCOM , - SH_FLD_RESERVED_20_31 ); -REG64_FLD( PU_INT_CQ_AIB_CTL_RESERVED_20_31_LEN , 12 , SH_UNT , SH_ACS_SCOM , - SH_FLD_RESERVED_20_31_LEN ); +REG64_FLD( PU_INT_CQ_AIB_CTL_BLOCK_CMD_OVERLAP , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BLOCK_CMD_OVERLAP ); +REG64_FLD( PU_INT_CQ_AIB_CTL_RESERVED_21_31 , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_21_31 ); +REG64_FLD( PU_INT_CQ_AIB_CTL_RESERVED_21_31_LEN , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_21_31_LEN ); REG64_FLD( PU_INT_CQ_AIB_CTL_CH0_CMD_CREDITS_0_5 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH0_CMD_CREDITS_0_5 ); REG64_FLD( PU_INT_CQ_AIB_CTL_CH0_CMD_CREDITS_0_5_LEN , 6 , SH_UNT , SH_ACS_SCOM , @@ -35661,30 +44825,30 @@ REG64_FLD( PU_INT_CQ_CFG_STQ2_RESERVED_20_31 , 20 , SH_UN REG64_FLD( PU_INT_CQ_CFG_STQ2_RESERVED_20_31_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_20_31_LEN ); -REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE0 , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_PMON_MUX_BYTE0 ); -REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE0_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_PMON_MUX_BYTE0_LEN ); -REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE1 , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_PMON_MUX_BYTE1 ); -REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE1_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_PMON_MUX_BYTE1_LEN ); -REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE2 , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_PMON_MUX_BYTE2 ); -REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_PMON_MUX_BYTE2_LEN ); -REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE3 , 9 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_PMON_MUX_BYTE3 ); -REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE3_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_PMON_MUX_BYTE3_LEN ); +REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE0_0_2 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PMON_MUX_BYTE0_0_2 ); +REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE0_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PMON_MUX_BYTE0_0_2_LEN ); +REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE1_0_2 , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PMON_MUX_BYTE1_0_2 ); +REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE1_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PMON_MUX_BYTE1_0_2_LEN ); +REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE2_0_2 , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PMON_MUX_BYTE2_0_2 ); +REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE2_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PMON_MUX_BYTE2_0_2_LEN ); +REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE3_0_2 , 9 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PMON_MUX_BYTE3_0_2 ); +REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE3_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PMON_MUX_BYTE3_0_2_LEN ); REG64_FLD( PU_INT_CQ_CNPM_SEL_RESERVED_12_23 , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_12_23 ); REG64_FLD( PU_INT_CQ_CNPM_SEL_RESERVED_12_23_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_12_23_LEN ); -REG64_FLD( PU_INT_CQ_CNPM_SEL_EBUS_ENABLE , 24 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_EBUS_ENABLE ); -REG64_FLD( PU_INT_CQ_CNPM_SEL_EBUS_ENABLE_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_EBUS_ENABLE_LEN ); +REG64_FLD( PU_INT_CQ_CNPM_SEL_EBUS_ENABLE_0_15 , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EBUS_ENABLE_0_15 ); +REG64_FLD( PU_INT_CQ_CNPM_SEL_EBUS_ENABLE_0_15_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EBUS_ENABLE_0_15_LEN ); REG64_FLD( PU_INT_CQ_ERR_INFO0_INFO_CAPTURED , 0 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INFO_CAPTURED ); @@ -35767,8 +44931,8 @@ REG64_FLD( PU_INT_CQ_ERR_INFO2_SYN_LO_0_7_LEN , 8 , SH_UN REG64_FLD( PU_INT_CQ_ERR_INFO3_INFO_CAPTURED , 0 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INFO_CAPTURED ); -REG64_FLD( PU_INT_CQ_ERR_INFO3_STQ_INVALID_ST , 1 , SH_UNT , SH_ACS_SCOM_WCLRPART, - SH_FLD_STQ_INVALID_ST ); +REG64_FLD( PU_INT_CQ_ERR_INFO3_STQ_FSM_PERR , 1 , SH_UNT , SH_ACS_SCOM_WCLRPART, + SH_FLD_STQ_FSM_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO3_LDQ_FSM_PERR , 2 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_LDQ_FSM_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO3_WRQ_FSM_PERR , 3 , SH_UNT , SH_ACS_SCOM_WCLRPART, @@ -35784,31 +44948,163 @@ REG64_FLD( PU_INT_CQ_ERR_INFO3_RDQ_OVERFLOW , 7 , SH_UN REG64_FLD( PU_INT_CQ_ERR_INFO3_INTQ_OVERFLOW , 8 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INTQ_OVERFLOW ); -REG64_FLD( PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_51 , 0 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_HOLD_0_51 ); -REG64_FLD( PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_51_LEN , 52 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_HOLD_0_51_LEN ); - +REG64_FLD( PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_48 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_0_48 ); +REG64_FLD( PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_48_LEN , 49 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_0_48_LEN ); + +REG64_FLD( PU_INT_CQ_FIR_PI_ECC_CE , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PI_ECC_CE ); +REG64_FLD( PU_INT_CQ_FIR_PI_ECC_UE , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PI_ECC_UE ); +REG64_FLD( PU_INT_CQ_FIR_PI_ECC_SUE , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PI_ECC_SUE ); +REG64_FLD( PU_INT_CQ_FIR_ST_ECC_CE , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ST_ECC_CE ); +REG64_FLD( PU_INT_CQ_FIR_ST_ECC_UE , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ST_ECC_UE ); +REG64_FLD( PU_INT_CQ_FIR_LD_ECC_CE , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_LD_ECC_CE ); +REG64_FLD( PU_INT_CQ_FIR_LD_ECC_UE , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_LD_ECC_UE ); +REG64_FLD( PU_INT_CQ_FIR_CL_ECC_CE , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CL_ECC_CE ); +REG64_FLD( PU_INT_CQ_FIR_CL_ECC_UE , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CL_ECC_UE ); +REG64_FLD( PU_INT_CQ_FIR_WR_ECC_CE , 9 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WR_ECC_CE ); +REG64_FLD( PU_INT_CQ_FIR_WR_ECC_UE , 10 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WR_ECC_UE ); +REG64_FLD( PU_INT_CQ_FIR_RD_ECC_CE , 11 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RD_ECC_CE ); +REG64_FLD( PU_INT_CQ_FIR_RD_ECC_UE , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RD_ECC_UE ); +REG64_FLD( PU_INT_CQ_FIR_AI_ECC_CE , 13 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_AI_ECC_CE ); +REG64_FLD( PU_INT_CQ_FIR_AI_ECC_UE , 14 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_AI_ECC_UE ); +REG64_FLD( PU_INT_CQ_FIR_AIB_IN_CMD_CTL_PERR , 15 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_AIB_IN_CMD_CTL_PERR ); +REG64_FLD( PU_INT_CQ_FIR_AIB_IN_CMD_PERR , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_AIB_IN_CMD_PERR ); +REG64_FLD( PU_INT_CQ_FIR_AIB_IN_DAT_CTL_PERR , 17 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_AIB_IN_DAT_CTL_PERR ); +REG64_FLD( PU_INT_CQ_FIR_PB_PARITY_ERROR , 18 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PB_PARITY_ERROR ); +REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR1 , 19 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PB_RCMDX_CI_ERR1 ); +REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR2 , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PB_RCMDX_CI_ERR2 ); +REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR3 , 21 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PB_RCMDX_CI_ERR3 ); +REG64_FLD( PU_INT_CQ_FIR_RCVD_POISONED_CIST_DATA , 22 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RCVD_POISONED_CIST_DATA ); +REG64_FLD( PU_INT_CQ_FIR_MRT_ERR_NOT_VALID , 23 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MRT_ERR_NOT_VALID ); +REG64_FLD( PU_INT_CQ_FIR_MRT_ERR_PSIZE , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MRT_ERR_PSIZE ); +REG64_FLD( PU_INT_CQ_FIR_SCOM_S_ERR , 25 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_SCOM_S_ERR ); +REG64_FLD( PU_INT_CQ_FIR_TCTXT_PRESP_ERROR , 26 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_TCTXT_PRESP_ERROR ); +REG64_FLD( PU_INT_CQ_FIR_WRQ_OP_HANG , 27 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WRQ_OP_HANG ); +REG64_FLD( PU_INT_CQ_FIR_RDQ_OP_HANG , 28 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RDQ_OP_HANG ); +REG64_FLD( PU_INT_CQ_FIR_INTQ_OP_HANG , 29 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INTQ_OP_HANG ); +REG64_FLD( PU_INT_CQ_FIR_RDQ_DATA_HANG , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RDQ_DATA_HANG ); +REG64_FLD( PU_INT_CQ_FIR_STQ_DATA_HANG , 31 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_STQ_DATA_HANG ); +REG64_FLD( PU_INT_CQ_FIR_LDQ_DATA_HANG , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_LDQ_DATA_HANG ); +REG64_FLD( PU_INT_CQ_FIR_WRQ_BAD_CRESP , 33 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WRQ_BAD_CRESP ); +REG64_FLD( PU_INT_CQ_FIR_RDQ_BAD_CRESP , 34 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RDQ_BAD_CRESP ); +REG64_FLD( PU_INT_CQ_FIR_INTQ_BAD_CRESP , 35 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INTQ_BAD_CRESP ); +REG64_FLD( PU_INT_CQ_FIR_BAD_128K_VP_OP , 36 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BAD_128K_VP_OP ); +REG64_FLD( PU_INT_CQ_FIR_RDQ_ABORT_OP , 37 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RDQ_ABORT_OP ); +REG64_FLD( PU_INT_CQ_FIR_PC_CRD_PERR , 38 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PC_CRD_PERR ); +REG64_FLD( PU_INT_CQ_FIR_PC_CRD_AVAIL_PERR , 39 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PC_CRD_AVAIL_PERR ); +REG64_FLD( PU_INT_CQ_FIR_VC_CRD_PERR , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VC_CRD_PERR ); +REG64_FLD( PU_INT_CQ_FIR_VC_CRD_AVAIL_PERR , 41 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VC_CRD_AVAIL_PERR ); +REG64_FLD( PU_INT_CQ_FIR_CMD_QX_SEVERE_ERR , 42 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CMD_QX_SEVERE_ERR ); +REG64_FLD( PU_INT_CQ_FIR_RDQ_ABORT_TRM , 43 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RDQ_ABORT_TRM ); +REG64_FLD( PU_INT_CQ_FIR_UNSOLICITED_CRESP , 44 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_UNSOLICITED_CRESP ); +REG64_FLD( PU_INT_CQ_FIR_UNSOLICITED_PBDATA , 45 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_UNSOLICITED_PBDATA ); +REG64_FLD( PU_INT_CQ_FIR_FIR_PARITY_ERR , 46 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_FIR_PARITY_ERR ); +REG64_FLD( PU_INT_CQ_FIR_RESERVED_47 , 47 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_47 ); +REG64_FLD( PU_INT_CQ_FIR_RESERVED_48 , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_48 ); +REG64_FLD( PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2 , 49 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PC_FATAL_ERROR_0_2 ); +REG64_FLD( PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PC_FATAL_ERROR_0_2_LEN ); +REG64_FLD( PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2 , 52 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PC_RECOV_ERROR_0_2 ); +REG64_FLD( PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PC_RECOV_ERROR_0_2_LEN ); +REG64_FLD( PU_INT_CQ_FIR_PC_INFO_ERROR_0_2 , 55 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PC_INFO_ERROR_0_2 ); +REG64_FLD( PU_INT_CQ_FIR_PC_INFO_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PC_INFO_ERROR_0_2_LEN ); +REG64_FLD( PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1 , 58 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VC_FATAL_ERROR_0_1 ); +REG64_FLD( PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VC_FATAL_ERROR_0_1_LEN ); +REG64_FLD( PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1 , 60 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VC_RECOV_ERROR_0_1 ); +REG64_FLD( PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VC_RECOV_ERROR_0_1_LEN ); +REG64_FLD( PU_INT_CQ_FIR_VC_INFO_ERROR_0_1 , 62 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VC_INFO_ERROR_0_1 ); +REG64_FLD( PU_INT_CQ_FIR_VC_INFO_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VC_INFO_ERROR_0_1_LEN ); + +REG64_FLD( PU_INT_CQ_FIRMASK_FIR_MASK , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_FIR_MASK ); +REG64_FLD( PU_INT_CQ_FIRMASK_FIR_MASK_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_FIR_MASK_LEN ); + +REG64_FLD( PU_INT_CQ_IC_BAR_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VALID ); +REG64_FLD( PU_INT_CQ_IC_BAR_PAGE_SIZE_64K , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PAGE_SIZE_64K ); REG64_FLD( PU_INT_CQ_IC_BAR_ADDR_8_48 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_48 ); REG64_FLD( PU_INT_CQ_IC_BAR_ADDR_8_48_LEN , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_48_LEN ); -REG64_FLD( PU_INT_CQ_MSGSND_CORES_ENABLED , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CORES_ENABLED ); -REG64_FLD( PU_INT_CQ_MSGSND_CORES_ENABLED_LEN , 24 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CORES_ENABLED_LEN ); +REG64_FLD( PU_INT_CQ_MSGSND_CORES_ENABLED_0_23 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CORES_ENABLED_0_23 ); +REG64_FLD( PU_INT_CQ_MSGSND_CORES_ENABLED_0_23_LEN , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CORES_ENABLED_0_23_LEN ); REG64_FLD( PU_INT_CQ_PBI_CTL_DIS_ECCCHK , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIS_ECCCHK ); REG64_FLD( PU_INT_CQ_PBI_CTL_DIS_ECCCHK_STO , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIS_ECCCHK_STO ); -REG64_FLD( PU_INT_CQ_PBI_CTL_EN_SPEC_CILD , 2 , SH_UNT , SH_ACS_SCOM , - SH_FLD_EN_SPEC_CILD ); -REG64_FLD( PU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_IC , 3 , SH_UNT , SH_ACS_SCOM , - SH_FLD_PAGE_SIZE_64K_IC ); -REG64_FLD( PU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_TM , 4 , SH_UNT , SH_ACS_SCOM , - SH_FLD_PAGE_SIZE_64K_TM ); +REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_2 , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_2 ); +REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_3 , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_3 ); +REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_4 , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_4 ); REG64_FLD( PU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_PC , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PAGE_SIZE_64K_PC ); REG64_FLD( PU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_VC , 6 , SH_UNT , SH_ACS_SCOM , @@ -35835,10 +45131,18 @@ REG64_FLD( PU_INT_CQ_PBI_CTL_FORCE_ECC_SEL , 16 , SH_UN SH_FLD_FORCE_ECC_SEL ); REG64_FLD( PU_INT_CQ_PBI_CTL_SPEC_CILD_G , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPEC_CILD_G ); -REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_18_31 , 18 , SH_UNT , SH_ACS_SCOM , - SH_FLD_RESERVED_18_31 ); -REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_18_31_LEN , 14 , SH_UNT , SH_ACS_SCOM , - SH_FLD_RESERVED_18_31_LEN ); +REG64_FLD( PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_IVE , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_SPEC_CILD_IVE ); +REG64_FLD( PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_EQD , 19 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_SPEC_CILD_EQD ); +REG64_FLD( PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_VPC_HW , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_SPEC_CILD_VPC_HW ); +REG64_FLD( PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_VPC_SW , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EN_SPEC_CILD_VPC_SW ); +REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_22_31 , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_22_31 ); +REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_22_31_LEN , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_22_31_LEN ); REG64_FLD( PU_INT_CQ_PBO_CTL_DIS_ECCCHK_LDO , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIS_ECCCHK_LDO ); @@ -35892,29 +45196,35 @@ REG64_FLD( PU_INT_CQ_PBO_CTL_HANG_ON_ACK_DEAD , 28 , SH_UN SH_FLD_HANG_ON_ACK_DEAD ); REG64_FLD( PU_INT_CQ_PBO_CTL_POLL_BCST_RTY_MON , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_POLL_BCST_RTY_MON ); -REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_GRP_POLL_BCST_0_4 , 30 , SH_UNT , SH_ACS_SCOM , - SH_FLD_MAX_GRP_POLL_BCST_0_4 ); -REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_GRP_POLL_BCST_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM , - SH_FLD_MAX_GRP_POLL_BCST_0_4_LEN ); -REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_ALL_POLL_BCST_0_4 , 35 , SH_UNT , SH_ACS_SCOM , - SH_FLD_MAX_ALL_POLL_BCST_0_4 ); -REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_ALL_POLL_BCST_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM , - SH_FLD_MAX_ALL_POLL_BCST_0_4_LEN ); -REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_NN_RN , 40 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_1_0_4 , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MAX_POLL_BCAST_1_0_4 ); +REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_1_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MAX_POLL_BCAST_1_0_4_LEN ); +REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_2_0_4 , 35 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MAX_POLL_BCAST_2_0_4 ); +REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_2_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MAX_POLL_BCAST_2_0_4_LEN ); +REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_3_0_4 , 40 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MAX_POLL_BCAST_3_0_4 ); +REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_3_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MAX_POLL_BCAST_3_0_4_LEN ); +REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_NN_RN , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_NN_RN ); -REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_VG_NOT_SYS , 41 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_VG_NOT_SYS , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_VG_NOT_SYS ); -REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_G , 42 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_G , 47 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_G ); -REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_LN , 43 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_LN , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_LN ); -REG64_FLD( PU_INT_CQ_PBO_CTL_SKIP_G , 44 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_INT_CQ_PBO_CTL_SKIP_G , 49 , SH_UNT , SH_ACS_SCOM , SH_FLD_SKIP_G ); -REG64_FLD( PU_INT_CQ_PBO_CTL_RESERVED_45_63 , 45 , SH_UNT , SH_ACS_SCOM , - SH_FLD_RESERVED_45_63 ); -REG64_FLD( PU_INT_CQ_PBO_CTL_RESERVED_45_63_LEN , 19 , SH_UNT , SH_ACS_SCOM , - SH_FLD_RESERVED_45_63_LEN ); +REG64_FLD( PU_INT_CQ_PBO_CTL_RESERVED_50_63 , 50 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_50_63 ); +REG64_FLD( PU_INT_CQ_PBO_CTL_RESERVED_50_63_LEN , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_50_63_LEN ); +REG64_FLD( PU_INT_CQ_PC_BAR_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VALID ); REG64_FLD( PU_INT_CQ_PC_BAR_ADDR_8_38 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_38 ); REG64_FLD( PU_INT_CQ_PC_BAR_ADDR_8_38_LEN , 31 , SH_UNT , SH_ACS_SCOM_RW , @@ -35990,10 +45300,12 @@ REG64_FLD( PU_INT_CQ_RST_CTL_MASTER_IDLE , 2 , SH_UN SH_FLD_MASTER_IDLE ); REG64_FLD( PU_INT_CQ_RST_CTL_SLAVE_IDLE , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SLAVE_IDLE ); -REG64_FLD( PU_INT_CQ_RST_CTL_RESERVED_4_7 , 4 , SH_UNT , SH_ACS_SCOM , - SH_FLD_RESERVED_4_7 ); -REG64_FLD( PU_INT_CQ_RST_CTL_RESERVED_4_7_LEN , 4 , SH_UNT , SH_ACS_SCOM , - SH_FLD_RESERVED_4_7_LEN ); +REG64_FLD( PU_INT_CQ_RST_CTL_PB_BAR_RESET , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PB_BAR_RESET ); +REG64_FLD( PU_INT_CQ_RST_CTL_RESERVED_5_7 , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_5_7 ); +REG64_FLD( PU_INT_CQ_RST_CTL_RESERVED_5_7_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_5_7_LEN ); REG64_FLD( PU_INT_CQ_SWI_RSP_HIST_DONE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HIST_DONE ); @@ -36001,10 +45313,10 @@ REG64_FLD( PU_INT_CQ_SWI_RSP_POLL_DONE , 1 , SH_UN SH_FLD_POLL_DONE ); REG64_FLD( PU_INT_CQ_SWI_RSP_BCAST_DONE , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BCAST_DONE ); -REG64_FLD( PU_INT_CQ_SWI_RSP_ASSN_DONE , 3 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_ASSN_DONE ); -REG64_FLD( PU_INT_CQ_SWI_RSP_BLKU_DONE , 4 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_BLKU_DONE ); +REG64_FLD( PU_INT_CQ_SWI_RSP_ASSIGN_DONE , 3 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ASSIGN_DONE ); +REG64_FLD( PU_INT_CQ_SWI_RSP_BLK_UPDT_DONE , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_BLK_UPDT_DONE ); REG64_FLD( PU_INT_CQ_SWI_RSP_Z , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_Z ); REG64_FLD( PU_INT_CQ_SWI_RSP_O , 6 , SH_UNT , SH_ACS_SCOM_RO , @@ -36015,8 +45327,8 @@ REG64_FLD( PU_INT_CQ_SWI_RSP_CRESP_0_4 , 8 , SH_UN SH_FLD_CRESP_0_4 ); REG64_FLD( PU_INT_CQ_SWI_RSP_CRESP_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CRESP_0_4_LEN ); -REG64_FLD( PU_INT_CQ_SWI_RSP_RSVD0 , 13 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_RSVD0 ); +REG64_FLD( PU_INT_CQ_SWI_RSP_RESERVED_13 , 13 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_13 ); REG64_FLD( PU_INT_CQ_SWI_RSP_COLLISON , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COLLISON ); REG64_FLD( PU_INT_CQ_SWI_RSP_PRECLUDE , 15 , SH_UNT , SH_ACS_SCOM_RO , @@ -36037,16 +45349,26 @@ REG64_FLD( PU_INT_CQ_TAR_ENTRY_SEL_0_5 , 26 , SH_UN REG64_FLD( PU_INT_CQ_TAR_ENTRY_SEL_0_5_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENTRY_SEL_0_5_LEN ); +REG64_FLD( PU_INT_CQ_TM1_BAR_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VALID ); +REG64_FLD( PU_INT_CQ_TM1_BAR_PAGE_SIZE_64K , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PAGE_SIZE_64K ); REG64_FLD( PU_INT_CQ_TM1_BAR_ADDR_8_49 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_49 ); REG64_FLD( PU_INT_CQ_TM1_BAR_ADDR_8_49_LEN , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_49_LEN ); +REG64_FLD( PU_INT_CQ_TM2_BAR_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VALID ); +REG64_FLD( PU_INT_CQ_TM2_BAR_PAGE_SIZE_64K , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PAGE_SIZE_64K ); REG64_FLD( PU_INT_CQ_TM2_BAR_ADDR_8_49 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_49 ); REG64_FLD( PU_INT_CQ_TM2_BAR_ADDR_8_49_LEN , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_49_LEN ); +REG64_FLD( PU_INT_CQ_VC_BAR_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VALID ); REG64_FLD( PU_INT_CQ_VC_BAR_ADDR_8_37 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_37 ); REG64_FLD( PU_INT_CQ_VC_BAR_ADDR_8_37_LEN , 30 , SH_UNT , SH_ACS_SCOM_RW , @@ -36057,224 +45379,651 @@ REG64_FLD( PU_INT_CQ_VC_BARM_ADDR_21_37 , 21 , SH_UN REG64_FLD( PU_INT_CQ_VC_BARM_ADDR_21_37_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_21_37_LEN ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR0 , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0 ); -REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR0_LEN , 64 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , - SH_FLD_ERR0_LEN ); - -REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH0 , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH0 ); -REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH0_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH0_LEN ); -REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH1 , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH1 ); -REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH1_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH1_LEN ); -REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH2 , 12 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH2 ); -REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH2_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH2_LEN ); -REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH3 , 18 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH3 ); -REG64_FLD( PU_INT_PC_AIB_MAX_CMD_CRD_REG_CH3_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH3_LEN ); - -REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH0 , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH0 ); -REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH0_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH0_LEN ); -REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH1 , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH1 ); -REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH1_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH1_LEN ); -REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH2 , 12 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH2 ); -REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH2_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH2_LEN ); -REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH3 , 18 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH3 ); -REG64_FLD( PU_INT_PC_AIB_MAX_DAT_CRD_REG_CH3_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CH3_LEN ); - -REG64_FLD( PU_INT_PC_CRD_INIT_TIMER_TIMER , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_TIMER ); -REG64_FLD( PU_INT_PC_CRD_INIT_TIMER_TIMER_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_TIMER_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_VLD ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_LVL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_CQ_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_DETAIL_LEN ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0 ); +REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , + SH_FLD_ERR_RSVD0_LEN ); + +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_1 ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_1_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH0_MAX , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH0_MAX ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH0_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH0_MAX_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_8_9 , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_9 ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_8_9_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_9_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH1_MAX , 10 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH1_MAX ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH1_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH1_MAX_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_16_17 , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_16_17 ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_16_17_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_16_17_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH2_MAX , 18 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH2_MAX ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH2_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH2_MAX_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_24_25 , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24_25 ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_24_25_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24_25_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH3_MAX , 26 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH3_MAX ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH3_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH3_MAX_LEN ); -REG64_FLD( PU_INT_PC_GEN_CFG_INDIRECT_MODE , 32 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_1 ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_1_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH0_MAX , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH0_MAX ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH0_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH0_MAX_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_8_9 , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_9 ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_8_9_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_9_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH1_MAX , 10 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH1_MAX ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH1_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH1_MAX_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_16_17 , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_16_17 ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_16_17_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_16_17_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH2_MAX , 18 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH2_MAX ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH2_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH2_MAX_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_24_25 , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24_25 ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_24_25_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24_25_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH3_MAX , 26 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH3_MAX ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH3_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CH3_MAX_LEN ); + +REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_INIT_REQUEST , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INIT_REQUEST ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_RESERVED_1_7 , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_7 ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_RESERVED_1_7_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_7_LEN ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_INIT_TIMER , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INIT_TIMER ); +REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_INIT_TIMER_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INIT_TIMER_LEN ); + +REG64_FLD( PU_INT_PC_AIB_TX_CRD_CRD_INIT_REQUEST , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CRD_INIT_REQUEST ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_25 , 25 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_25 ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_DMA_READ , 26 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RSD_DMA_READ ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_DMA_READ_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RSD_DMA_READ_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_LD_RMT , 28 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RSD_VPC_LD_RMT ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_LD_RMT_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RSD_VPC_LD_RMT_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_AT_MACRO , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RSD_AT_MACRO ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_AT_MACRO_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RSD_AT_MACRO_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_32_34 , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32_34 ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_32_34_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32_34_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_READ_POOL , 35 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_READ_POOL ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_READ_POOL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_READ_POOL_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_40_47 , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_40_47 ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_40_47_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_40_47_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_TCTXT_WRITE , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RSD_TCTXT_WRITE ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_TCTXT_WRITE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RSD_TCTXT_WRITE_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_50_51 , 50 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_50_51 ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_50_51_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_50_51_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_DMA_WRITE , 52 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RSD_DMA_WRITE ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_DMA_WRITE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RSD_DMA_WRITE_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT , 54 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RSD_VPC_ST_RMT ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RSD_VPC_ST_RMT_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_VC , 56 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RSD_VPC_ST_RMT_VC ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_VC_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RSD_VPC_ST_RMT_VC_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_58 , 58 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_58 ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_WRITE_POOL , 59 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WRITE_POOL ); +REG64_FLD( PU_INT_PC_AIB_TX_CRD_WRITE_POOL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WRITE_POOL_LEN ); + +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_REGS_ORDERING_TAG , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_REGS_ORDERING_TAG ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_REGS_ORDERING_TAG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_REGS_ORDERING_TAG_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_DMA_ORDERING_TAG , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VPC_DMA_ORDERING_TAG ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_DMA_ORDERING_TAG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VPC_DMA_ORDERING_TAG_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_LD_RSP_ORDERING_TAG , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VPC_LD_RSP_ORDERING_TAG ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_LD_RSP_ORDERING_TAG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VPC_LD_RSP_ORDERING_TAG_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_LD_RMT_ORDERING_TAG , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VPC_LD_RMT_ORDERING_TAG ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_LD_RMT_ORDERING_TAG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VPC_LD_RMT_ORDERING_TAG_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_ORDERING_TAG , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VPC_ST_RMT_ORDERING_TAG ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_ORDERING_TAG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VPC_ST_RMT_ORDERING_TAG_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_VC_ORDERING_TAG , 56 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG ); +REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_VC_ORDERING_TAG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG_LEN ); + +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_40_43 , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_40_43 ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_40_43_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_40_43_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_REGS , 44 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_REGS ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_REGS_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_REGS_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_TCTXT_RSP_WR , 46 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_TCTXT_RSP_WR ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_TCTXT_RSP_WR_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_TCTXT_RSP_WR_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_BLCK_UPD , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_BLCK_UPD ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_BLCK_UPD_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_BLCK_UPD_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_50_51 , 50 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_50_51 ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_50_51_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_50_51_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_SBC_EOI_RESP , 52 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_SBC_EOI_RESP ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_SBC_EOI_RESP_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_SBC_EOI_RESP_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_DMA , 54 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_VPC_DMA ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_DMA_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_VPC_DMA_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_LD_RMT , 56 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_VPC_LD_RMT ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_LD_RMT_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_VPC_LD_RMT_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_LCL_VC , 58 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_VPC_ST_LCL_VC ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_LCL_VC_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_VPC_ST_LCL_VC_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT , 60 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_VPC_ST_RMT ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_VPC_ST_RMT_LEN ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_VC , 62 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_VPC_ST_RMT_VC ); +REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_VC_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ATX_FOR_VPC_ST_RMT_VC_LEN ); + +REG64_FLD( PU_INT_PC_AT_KILL_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VALID ); +REG64_FLD( PU_INT_PC_AT_KILL_RESERVED_24_26 , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24_26 ); +REG64_FLD( PU_INT_PC_AT_KILL_RESERVED_24_26_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24_26_LEN ); +REG64_FLD( PU_INT_PC_AT_KILL_BLOCKID , 27 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BLOCKID ); +REG64_FLD( PU_INT_PC_AT_KILL_BLOCKID_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BLOCKID_LEN ); +REG64_FLD( PU_INT_PC_AT_KILL_OFFSET , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_OFFSET ); +REG64_FLD( PU_INT_PC_AT_KILL_OFFSET_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_OFFSET_LEN ); +REG64_FLD( PU_INT_PC_AT_KILL_RESERVED_61_63 , 61 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_61_63 ); +REG64_FLD( PU_INT_PC_AT_KILL_RESERVED_61_63_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_61_63_LEN ); + +REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_24_26 , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24_26 ); +REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_24_26_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24_26_LEN ); +REG64_FLD( PU_INT_PC_AT_KILL_MASK_BLOCKID , 27 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BLOCKID ); +REG64_FLD( PU_INT_PC_AT_KILL_MASK_BLOCKID_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BLOCKID_LEN ); +REG64_FLD( PU_INT_PC_AT_KILL_MASK_OFFSET , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_OFFSET ); +REG64_FLD( PU_INT_PC_AT_KILL_MASK_OFFSET_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_OFFSET_LEN ); +REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_61_63 , 61 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_61_63 ); +REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_61_63_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_61_63_LEN ); + +REG64_FLD( PU_INT_PC_EQD_BLOCK_MODE_MODE , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MODE ); +REG64_FLD( PU_INT_PC_EQD_BLOCK_MODE_MODE_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MODE_LEN ); + +REG64_FLD( PU_INT_PC_GLOBAL_CFG_INDIRECT_MODE , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIRECT_MODE ); -REG64_FLD( PU_INT_PC_GEN_CFG_RESERVED_33_63 , 33 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_33_63 ); -REG64_FLD( PU_INT_PC_GEN_CFG_RESERVED_33_63_LEN , 31 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_33_63_LEN ); +REG64_FLD( PU_INT_PC_GLOBAL_CFG_RESERVED_33_39 , 33 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_33_39 ); +REG64_FLD( PU_INT_PC_GLOBAL_CFG_RESERVED_33_39_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_33_39_LEN ); + +REG64_FLD( PU_INT_PC_IVE_BLOCK_MODE_MODE , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MODE ); +REG64_FLD( PU_INT_PC_IVE_BLOCK_MODE_MODE_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MODE_LEN ); -REG64_FLD( PU_INT_PC_INDIR0_REG_VLD , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_VLD ); -REG64_FLD( PU_INT_PC_INDIR0_REG_THRDID , 1 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_THRDID ); -REG64_FLD( PU_INT_PC_INDIR0_REG_THRDID_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_THRDID_LEN ); - -REG64_FLD( PU_INT_PC_INDIR1_REG_VLD , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_VLD ); -REG64_FLD( PU_INT_PC_INDIR1_REG_THRDID , 1 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_THRDID ); -REG64_FLD( PU_INT_PC_INDIR1_REG_THRDID_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_THRDID_LEN ); - -REG64_FLD( PU_INT_PC_INDIR2_REG_VLD , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_VLD ); -REG64_FLD( PU_INT_PC_INDIR2_REG_THRDID , 1 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_THRDID ); -REG64_FLD( PU_INT_PC_INDIR2_REG_THRDID_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_THRDID_LEN ); - -REG64_FLD( PU_INT_PC_INDIR3_REG_VLD , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_VLD ); -REG64_FLD( PU_INT_PC_INDIR3_REG_THRDID , 1 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_THRDID ); -REG64_FLD( PU_INT_PC_INDIR3_REG_THRDID_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_THRDID_LEN ); - -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PARSE_PULL_RR_SEL , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_SET_LD , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_LDST_PRIO_SET_LD ); +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_SET_LD_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_LDST_PRIO_SET_LD_LEN ); +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_RSP_LD , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_LDST_PRIO_RSP_LD ); +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_RSP_LD_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_LDST_PRIO_RSP_LD_LEN ); +REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_4_5 , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_4_5 ); +REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_4_5_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_4_5_LEN ); +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_PULL_RR_SEL , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PARSE_PULL_RR_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_PULL_RR_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL_LEN ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PARSE_IACK_RR_SEL , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_IACK_RR_SEL , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PARSE_IACK_RR_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_IACK_RR_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL_LEN ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PULL_PRIO_HYP , 4 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PULL_PRIO_HYP , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PULL_PRIO_HYP ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PULL_PRIO_HYP_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PULL_PRIO_HYP_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PULL_PRIO_HYP_LEN ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_IACK_PRIO_HYP , 7 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_IACK_PRIO_HYP , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_IACK_PRIO_HYP ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_IACK_PRIO_HYP_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_IACK_PRIO_HYP_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_IACK_PRIO_HYP_LEN ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PRIO_IACK , 10 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PRIO_IACK , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PRIO_IACK ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_DONE_PRIO_IACK_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PRIO_IACK_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PRIO_IACK_LEN ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_LDST_SET , 13 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_16 , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_16 ); +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_SET , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_LDST_SET ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_LDST_SET_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_SET_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_LDST_SET_LEN ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_LDST_RSP , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_20 , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_20 ); +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_RSP , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_LDST_RSP ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_LDST_RSP_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_RSP_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_LDST_RSP_LEN ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_DONE , 19 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_24 , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24 ); +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_DONE , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_DONE ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_DONE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_DONE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_DONE_LEN ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_RR , 22 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_28 , 28 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28 ); +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_RR , 29 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_RR ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_PCMD_PRIO_RR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_RR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_RR_LEN ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_LDST_PRIO_SET_LD , 25 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_LDST_PRIO_SET_LD ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_LDST_PRIO_SET_LD_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_LDST_PRIO_SET_LD_LEN ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_LDST_PRIO_RSP_LD , 28 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_LDST_PRIO_RSP_LD ); -REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_CFG_LDST_PRIO_RSP_LD_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_LDST_PRIO_RSP_LD_LEN ); -REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_LSI , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0 ); +REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_LSI , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_LSI ); -REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_LSI_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_LSI_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_LSI_LEN ); -REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_MMIO , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_4 , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_4 ); +REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_MMIO , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_MMIO ); -REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_MMIO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_MMIO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_MMIO_LEN ); -REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_VRQ_REQ , 6 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_8 , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8 ); +REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_REQ , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_VRQ_REQ ); -REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_VRQ_REQ_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_REQ_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_VRQ_REQ_LEN ); -REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_VRQ_RSP , 9 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_12 , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_12 ); +REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_RSP , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_VRQ_RSP ); -REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_VRQ_RSP_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_RSP_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_VRQ_RSP_LEN ); -REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_RR , 12 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_16 , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_16 ); +REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_RR , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RR ); -REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_CFG_PRIO_RR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_RR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RR_LEN ); REG64_FLD( PU_INT_PC_REGS_ERR_CFG_REG0_ERROR_CONFIG , 0 , SH_UNT , SH_ACS_SCOM_RW , @@ -36312,193 +46061,713 @@ REG64_FLD( PU_INT_PC_REGS_WOF_ERR_DETAIL_ERROR , 0 , SH_UN REG64_FLD( PU_INT_PC_REGS_WOF_ERR_DETAIL_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR_LEN ); -REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_CHIPID , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CHIPID ); -REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_CHIPID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CHIPID_LEN ); -REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_CHIPID_OVERRIDE , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CHIPID_OVERRIDE ); -REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_HARD_CHIPID_IN_BLOCK_EN , 5 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_HARD_CHIPID_IN_BLOCK_EN ); -REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_24CORE_EN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_24CORE_EN ); -REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_ACM_EN , 7 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ACM_EN ); -REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_BLOCK_TRACK_EN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_BLOCK_TRACK_EN ); -REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_LBS_IDX0_SEL , 9 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_LBS_IDX0_SEL ); -REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_WAKEUP_PULSE , 10 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_WAKEUP_PULSE ); -REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_WAKEUP_PULSE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_WAKEUP_PULSE_LEN ); -REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_BLOCK_GROUP_EN , 14 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_BLOCK_GROUP_EN ); -REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_BLOCK_TRACK_RESET_DELAY , 15 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_BLOCK_TRACK_RESET_DELAY ); -REG64_FLD( PU_INT_PC_TCTXT_CFG_REG_BLOCK_TRACK_RESET_DELAY_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_BLOCK_TRACK_RESET_DELAY_LEN ); - -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C0 , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C0 ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C0_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C0_LEN ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C1 , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C1 ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C1_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C1_LEN ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C2 , 16 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C2 ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C2_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C2_LEN ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C3 , 24 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C3 ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C3_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C3_LEN ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C4 , 32 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C4 ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C4_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C4_LEN ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C5 , 40 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C5 ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C5_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C5_LEN ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C6 , 48 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C6 ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C6_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C6_LEN ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C7 , 56 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C7 ); -REG64_FLD( PU_INT_PC_THRD_EN_REG0_CFG_C7_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C7_LEN ); - -REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C8 , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C8 ); -REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C8_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C8_LEN ); -REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C9 , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C9 ); -REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C9_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C9_LEN ); -REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C10 , 16 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C10 ); -REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C10_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C10_LEN ); -REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C11 , 24 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C11 ); -REG64_FLD( PU_INT_PC_THRD_EN_REG1_CFG_C11_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_C11_LEN ); - -REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_RSVD , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_P0_IS_IDLE , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_P0_IS_IDLE ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_P1_IS_IDLE , 1 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_P1_IS_IDLE ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_2_9 , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_2_9 ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_2_9_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_2_9_LEN ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MAX_PTAG_IN_USE ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MAX_PTAG_IN_USE_LEN ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_16_27 , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_16_27 ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_16_27_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_16_27_LEN ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO , 28 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MAX_UNLOCK_IN_FIFO ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MAX_UNLOCK_IN_FIFO_LEN ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_32_33 , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_32_33 ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_32_33_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_32_33_LEN ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_WB , 34 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MAX_OUTSTANDING_WB ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_WB_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MAX_OUTSTANDING_WB_LEN ); + +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_0_1 ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_0_1_LEN ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_VPD_FETCH , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MAX_OUTSTANDING_VPD_FETCH ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_VPD_FETCH_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MAX_OUTSTANDING_VPD_FETCH_LEN ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_8_9 , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_8_9 ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_8_9_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_8_9_LEN ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MAX_OUTSTANDING_CI_LOAD ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MAX_OUTSTANDING_CI_LOAD_LEN ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_16_17 , 16 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_16_17 ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_16_17_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_16_17_LEN ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT , 18 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MAX_OUTSTANDING_ST_RMT ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MAX_OUTSTANDING_ST_RMT_LEN ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_24_25 , 24 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_24_25 ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_24_25_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RESERVED_24_25_LEN ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_VC , 26 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MAX_OUTSTANDING_ST_RMT_VC ); +REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_VC_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MAX_OUTSTANDING_ST_RMT_VC_LEN ); + +REG64_FLD( PU_INT_PC_VPC_CACHE_EN_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ENABLE ); +REG64_FLD( PU_INT_PC_VPC_CACHE_EN_ENABLE_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ENABLE_LEN ); + +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_VP , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VP ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_SECURE , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_SECURE ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_PGOFFIRSTLS , 26 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PGOFFIRSTLS ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_PGOFFIRSTLS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PGOFFIRSTLS_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_BLOCK , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IVE_BLOCK ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_BLOCK_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IVE_BLOCK_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_INDEX , 36 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IVE_INDEX ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_INDEX_LEN , 28 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IVE_INDEX_LEN ); + +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA2_IPB , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IPB ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA2_IPB_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IPB_LEN ); + +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA3_MIG_REG , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MIG_REG ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA3_MIG_REG_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MIG_REG_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA3_CL , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CL ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA3_CL_LEN , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CL_LEN ); + +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_VG , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VG ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_PGOFNEXTLS , 26 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PGOFNEXTLS ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_PGOFNEXTLS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PGOFNEXTLS_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_BLOCK , 36 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EQD_BLOCK ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_BLOCK_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EQD_BLOCK_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_INDEX , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EQD_INDEX ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_INDEX_LEN , 21 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EQD_INDEX_LEN ); + +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG0 ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG0_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG0_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG1 , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG1 ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG1_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG1_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG2 , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG2 ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG2_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG2_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG3 , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG3 ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG3_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG3_LEN ); + +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG4 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG4 ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG4_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG4_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG5 , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG5 ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG5_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG5_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG6 , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG6 ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG6_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG6_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG7 , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG7 ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG7_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BKLG7_LEN ); + +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_CONFLICT , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CONFLICT ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_1_7 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_1_7 ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_1_7_LEN , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_1_7_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_FULL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_FULL ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_9_26 , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_9_26 ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_9_26_LEN , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_9_26_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_BLOCKID , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BLOCKID ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_BLOCKID_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_BLOCKID_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_32_44 , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_32_44 ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_32_44_LEN , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RESERVED_32_44_LEN ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_OFFSET , 45 , SH_UNT , SH_ACS_SCOM , + SH_FLD_OFFSET ); +REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_OFFSET_LEN , 19 , SH_UNT , SH_ACS_SCOM , + SH_FLD_OFFSET_LEN ); + +REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_32 , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32 ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_SYNC_DONE , 33 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_SYNC_DONE ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_SYNC_DONE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_SYNC_DONE_LEN ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_36_39 , 36 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_36_39 ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_36_39_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_36_39_LEN ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_LCL_FIRST_GRPSCAN_ENA , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_LCL_FIRST_GRPSCAN_ENA ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_LCL_FIRST_GRPSCAN_RMT_ENA , 41 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_LCL_FIRST_GRPSCAN_RMT_ENA ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_RMT_FIRST_GRPSCAN_ENA , 42 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RMT_FIRST_GRPSCAN_ENA ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_LSMFB_SCAN_ALL_PRIO_ENA , 43 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_LSMFB_SCAN_ALL_PRIO_ENA ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_44_51 , 44 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_44_51 ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_44_51_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_44_51_LEN ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_BG_SCAN_RATE , 52 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BG_SCAN_RATE ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_BG_SCAN_RATE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BG_SCAN_RATE_LEN ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_56_58 , 56 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_56_58 ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_56_58_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_56_58_LEN ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_MAX_ENTRIES_IN_MODIFIED , 59 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MAX_ENTRIES_IN_MODIFIED ); +REG64_FLD( PU_INT_PC_VPC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN ); + +REG64_FLD( PU_INT_PC_VPC_DEBUG_RESERVED_0_29 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_29 ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_RESERVED_0_29_LEN , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_29_LEN ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_LD_ECC_CORRECTION , 30 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_LD_ECC_CORRECTION ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_TAG_ECC_CORRECTION , 31 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_TAG_ECC_CORRECTION ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_TAG_ECC_CORRECTION_LEN ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_STATE_ECC_CORRECTION , 39 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_STATE_ECC_CORRECTION ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_STATE_ECC_CORRECTION_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_STATE_ECC_CORRECTION_LEN ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_PTAG_ECC_CORRECTION , 41 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_PTAG_ECC_CORRECTION ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_PTAG_ECC_CORRECTION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_PTAG_ECC_CORRECTION_LEN ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_DATA_ECC_CORRECTION , 44 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_DATA_ECC_CORRECTION ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DIS_DATA_ECC_CORRECTION_LEN ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_FORCE_SINGLE_BIT_ECC_ERR ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR , 49 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_PARTITION_SEL , 50 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ECC_ERR_INJ_PARTITION_SEL ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_PARTITION_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ECC_ERR_INJ_PARTITION_SEL_LEN ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_ARRAY_SEL , 52 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ECC_ERR_INJ_ARRAY_SEL ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_TRACE_ENABLE , 56 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_TRACE_ENABLE ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_PMC_ENABLE , 57 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PMC_ENABLE ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_RESERVED_58_59 , 58 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_58_59 ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_RESERVED_58_59_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_58_59_LEN ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_USE_WATCH_TO_READ_CTRL_ARY , 60 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_USE_WATCH_TO_READ_CTRL_ARY ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_CACHE_CTRL_ARY_SELECT , 61 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CACHE_CTRL_ARY_SELECT ); +REG64_FLD( PU_INT_PC_VPC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CACHE_CTRL_ARY_SELECT_LEN ); + +REG64_FLD( PU_INT_PC_VPC_ERR_CFG0_ERROR_CONFIG , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CONFIG ); +REG64_FLD( PU_INT_PC_VPC_ERR_CFG0_ERROR_CONFIG_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CONFIG_LEN ); + +REG64_FLD( PU_INT_PC_VPC_ERR_CFG1_ERROR_CONFIG , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CONFIG ); +REG64_FLD( PU_INT_PC_VPC_ERR_CFG1_ERROR_CONFIG_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CONFIG_LEN ); + +REG64_FLD( PU_INT_PC_VPC_ERR_CFG_REG_ERROR_CONFIG , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CONFIG ); +REG64_FLD( PU_INT_PC_VPC_ERR_CFG_REG_ERROR_CONFIG_LEN , 34 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ERROR_CONFIG_LEN ); + +REG64_FLD( PU_INT_PC_VPC_FATAL_ERR_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR ); +REG64_FLD( PU_INT_PC_VPC_FATAL_ERR_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR_LEN ); + +REG64_FLD( PU_INT_PC_VPC_INFO_ERR_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR ); +REG64_FLD( PU_INT_PC_VPC_INFO_ERR_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR_LEN ); + +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_0_25 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_25 ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_0_25_LEN , 26 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_25_LEN ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT , 26 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CI_STORE_RMT ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CI_STORE_RMT_LEN ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_32_33 , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32_33 ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_32_33_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32_33_LEN ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_VC , 34 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CI_STORE_RMT_VC ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_VC_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CI_STORE_RMT_VC_LEN ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_40_41 , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_40_41 ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_40_41_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_40_41_LEN ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_LOAD , 42 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CI_LOAD ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_LOAD_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CI_LOAD_LEN ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_48_49 , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_48_49 ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_48_49_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_48_49_LEN ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_READ , 50 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VPD_DMA_READ ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_READ_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VPD_DMA_READ_LEN ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_56_57 , 56 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_56_57 ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_56_57_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_56_57_LEN ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_WRITE , 58 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VPD_DMA_WRITE ); +REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_WRITE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VPD_DMA_WRITE_LEN ); + +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PULL , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VRQ_PULL ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PULL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VRQ_PULL_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_LOCAL , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VRQ_PUSH_LOCAL ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_LOCAL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VRQ_PUSH_LOCAL_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_REMOTE , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VRQ_PUSH_REMOTE ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_REMOTE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VRQ_PUSH_REMOTE_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_VC_LOAD , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_NON_SPEC_VC_LOAD ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_VC_LOAD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_NON_SPEC_VC_LOAD_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_SW_LOAD , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_NON_SPEC_SW_LOAD ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_SW_LOAD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_NON_SPEC_SW_LOAD_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_LOAD , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_NON_SPEC_LOAD ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_LOAD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_NON_SPEC_LOAD_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LOCAL_GROUP_SCAN , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LOCAL_GROUP_SCAN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LOCAL_GROUP_SCAN_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LOCAL_GROUP_SCAN_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_CACHE_HIT , 28 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VRQ_CACHE_HIT ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_CACHE_HIT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VRQ_CACHE_HIT_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LD_CACHE_HIT , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LD_CACHE_HIT ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LD_CACHE_HIT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LD_CACHE_HIT_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_GROUP_SCAN_CACHE_HIT , 36 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_GROUP_SCAN_CACHE_HIT ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_GROUP_SCAN_CACHE_HIT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_GROUP_SCAN_CACHE_HIT_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VICTIM_IS_LRU ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VICTIM_IS_LRU_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE , 44 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VICTIM_IS_FIRST_USABLE ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VICTIM_IS_FIRST_USABLE_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_RETRY , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RETRY ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_RETRY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RETRY_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES , 52 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_TOO_MANY_ENTRIES ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_TOO_MANY_ENTRIES_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_RESERVED_56_63 , 56 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_56_63 ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_RESERVED_56_63_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_56_63_LEN ); + +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_WB , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VPD_WB ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_WB_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VPD_WB_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_FETCH , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VPD_FETCH ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_FETCH_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VPD_FETCH_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_TCTXT , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RSP_LCL_TCTXT ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_TCTXT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RSP_LCL_TCTXT_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_VC , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RSP_LCL_VC ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_VC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RSP_LCL_VC_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RSP_RMT ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RSP_RMT_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_VC , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RSP_RMT_VC ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_VC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RSP_RMT_VC_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_SW_LD , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RSP_SW_LD ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_SW_LD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RSP_SW_LD_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STVP , 28 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RMT_PULL_1STVP ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STVP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RMT_PULL_1STVP_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STGRP , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RMT_PULL_1STGRP ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STGRP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RMT_PULL_1STGRP_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_VP , 36 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RMT_PULL_VP ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_VP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RMT_PULL_VP_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_GRP , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RMT_PULL_GRP ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_GRP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RMT_PULL_GRP_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_PRESS_RELIEF , 44 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LCL_PRESS_RELIEF ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_PRESS_RELIEF_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LCL_PRESS_RELIEF_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_REDIST , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LCL_REDIST ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_REDIST_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LCL_REDIST_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH , 52 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RMT_PUSH ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RMT_PUSH_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_VC , 56 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RMT_PUSH_VC ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_VC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RMT_PUSH_VC_LEN ); + +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LCL_GRPSCAN_REPLAY , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LCL_GRPSCAN_REPLAY ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LCL_GRPSCAN_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LCL_GRPSCAN_REPLAY_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_VPD_FETCH_REPLAY , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VPD_FETCH_REPLAY ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_VPD_FETCH_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_VPD_FETCH_REPLAY_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_TCTXT_REPLAY , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RSP_TCTXT_REPLAY ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_TCTXT_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RSP_TCTXT_REPLAY_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_ATX_REPLAY , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RSP_ATX_REPLAY ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_ATX_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_RSP_ATX_REPLAY_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LD_REQ_REPLAY , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LD_REQ_REPLAY ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LD_REQ_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_LD_REQ_REPLAY_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_LCL_REPLAY , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_ST_LCL_REPLAY ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_LCL_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_ST_LCL_REPLAY_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_REPLAY , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_ST_RMT_REPLAY ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_ST_RMT_REPLAY_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_VC_REPLAY , 28 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_ST_RMT_VC_REPLAY ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_VC_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_ST_RMT_VC_REPLAY_LEN ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_SAME_VPD_REPLAY , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_SAME_VPD_REPLAY ); +REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_SAME_VPD_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CNT_SAME_VPD_REPLAY_LEN ); + +REG64_FLD( PU_INT_PC_VPC_RECOV_ERR_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR ); +REG64_FLD( PU_INT_PC_VPC_RECOV_ERR_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR_LEN ); + +REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_BLOCKID , 27 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BLOCKID ); +REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_BLOCKID_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BLOCKID_LEN ); +REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_RESERVED_32_44 , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32_44 ); +REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_RESERVED_32_44_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32_44_LEN ); +REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_OFFSET , 45 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_OFFSET ); +REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_OFFSET_LEN , 19 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_OFFSET_LEN ); + +REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_VALID ); +REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_WANT_CACHE_DISABLE , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WANT_CACHE_DISABLE ); +REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_WANT_INVALIDATE , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WANT_INVALIDATE ); +REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_BLOCKID , 27 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BLOCKID ); +REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_BLOCKID_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_BLOCKID_LEN ); +REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_RESERVED_32_44 , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32_44 ); +REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_RESERVED_32_44_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32_44_LEN ); +REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_OFFSET , 45 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_OFFSET ); +REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_OFFSET_LEN , 19 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_OFFSET_LEN ); + +REG64_FLD( PU_INT_PC_VPC_WOF_ERR_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR ); +REG64_FLD( PU_INT_PC_VPC_WOF_ERR_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, + SH_FLD_ERROR_LEN ); + +REG64_FLD( PU_INT_PC_VPC_WOF_ERR_DETAIL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ERROR ); +REG64_FLD( PU_INT_PC_VPC_WOF_ERR_DETAIL_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ERROR_LEN ); + +REG64_FLD( PU_INT_PC_VPD_BLOCK_MODE_MODE , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MODE ); +REG64_FLD( PU_INT_PC_VPD_BLOCK_MODE_MODE_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MODE_LEN ); + +REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_CORE_PUSH_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_CORE_PUSH_EN ); +REG64_FLD( PU_INT_PC_VRQ_CFG_RESERVED_1_2 , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_2 ); +REG64_FLD( PU_INT_PC_VRQ_CFG_RESERVED_1_2_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_2_LEN ); +REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PULL , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_QUEUE_SIZE_PULL ); +REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PULL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_QUEUE_SIZE_PULL_LEN ); +REG64_FLD( PU_INT_PC_VRQ_CFG_RESERVED_8_10 , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_10 ); +REG64_FLD( PU_INT_PC_VRQ_CFG_RESERVED_8_10_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_10_LEN ); +REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PUSH_LCL , 11 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL ); +REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PUSH_LCL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL_LEN ); + +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_QUERY_RR_SEL , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PARSE_QUERY_RR_SEL ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_1 , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1 ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PULL_RR_SEL , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PARSE_PULL_RR_SEL ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PULL_RR_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PARSE_PULL_RR_SEL_LEN ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PUSH_RR_SEL , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PARSE_PUSH_RR_SEL ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PUSH_RR_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PARSE_PUSH_RR_SEL_LEN ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_6_7 , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_6_7 ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_6_7_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_6_7_LEN ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PULL_PRIO_HYP , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PULL_PRIO_HYP ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PULL_PRIO_HYP_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PULL_PRIO_HYP_LEN ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PUSH_PRIO_HYP , 10 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUSH_PRIO_HYP ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PUSH_PRIO_HYP_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUSH_PRIO_HYP_LEN ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_12_16 , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_12_16 ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_12_16_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_12_16_LEN ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_QUERY , 17 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRIO_QUERY ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_QUERY_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRIO_QUERY_LEN ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_20 , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_20 ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PUSH , 21 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRIO_PUSH ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PUSH_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRIO_PUSH_LEN ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_24 , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24 ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PULL , 25 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRIO_PULL ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PULL_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRIO_PULL_LEN ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_28 , 28 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_28 ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_RR , 29 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRIO_RR ); +REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_RR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PRIO_RR_LEN ); + +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0 ); +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RSVD , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RSVD ); -REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_RSVD_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RSVD_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RSVD_LEN ); -REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_PULL , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PULL , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_STALL_PULL ); +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PULL , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PULL ); -REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_PULL_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PULL_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PULL_LEN ); -REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_PUSH_LCL , 6 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PUSH_LCL , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_STALL_PUSH_LCL ); +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_LCL , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PUSH_LCL ); -REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_PUSH_LCL_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_LCL_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PUSH_LCL_LEN ); -REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_PUSH_ARX , 9 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PUSH_ARX , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_STALL_PUSH_ARX ); +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_ARX , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PUSH_ARX ); -REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_PUSH_ARX_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_ARX_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PUSH_ARX_LEN ); -REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_RR , 12 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_RESERVED_16 , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_16 ); +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RR , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RR ); -REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_PRIO_RR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RR_LEN ); -REG64_FLD( PU_INT_PC_VRQ_ARB_CFG_CFG_STALL , 15 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_STALL ); -REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_PULL_RSVD , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_1 ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_0_1_LEN ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_RSVD , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PULL_RSVD ); -REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_PULL_RSVD_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_RSVD_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PULL_RSVD_LEN ); -REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PULL_LMIT , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_VPC_PULL_LMIT ); -REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PULL_LMIT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_VPC_PULL_LMIT_LEN ); -REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PUSH_LCL_RSVD , 12 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_VPC_PUSH_LCL_RSVD ); -REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PUSH_LCL_RSVD_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_VPC_PUSH_LCL_RSVD_LEN ); -REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PUSH_LCL_LMIT , 18 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_VPC_PUSH_LCL_LMIT ); -REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PUSH_LCL_LMIT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_VPC_PUSH_LCL_LMIT_LEN ); -REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_PUSH_ARX_RSVD , 24 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_8_9 , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_9 ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_8_9_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_8_9_LEN ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_LMIT , 10 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PULL_LMIT ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_LMIT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PULL_LMIT_LEN ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_16_17 , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_16_17 ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_16_17_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_16_17_LEN ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_RSVD , 18 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUSH_LCL_RSVD ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_RSVD_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUSH_LCL_RSVD_LEN ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_24_25 , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24_25 ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_24_25_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24_25_LEN ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_LMIT , 26 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUSH_LCL_LMIT ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_LMIT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUSH_LCL_LMIT_LEN ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_32_33 , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32_33 ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_32_33_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_32_33_LEN ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_RSVD , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PUSH_ARX_RSVD ); -REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_PUSH_ARX_RSVD_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_RSVD_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PUSH_ARX_RSVD_LEN ); -REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PUSH_ARX_LMIT , 30 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_VPC_PUSH_ARX_LMIT ); -REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_VPC_PUSH_ARX_LMIT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_VPC_PUSH_ARX_LMIT_LEN ); -REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_MAX , 36 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_40_41 , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_40_41 ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_40_41_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_40_41_LEN ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_LMIT , 42 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUSH_ARX_LMIT ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_LMIT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PUSH_ARX_LMIT_LEN ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_48_49 , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_48_49 ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_48_49_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_48_49_LEN ); +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_MAX , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_MAX ); -REG64_FLD( PU_INT_PC_VRQ_CRD_CFG_CFG_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_MAX_LEN ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_PARSE_QUERY_RR_SEL , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_PARSE_QUERY_RR_SEL ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_PARSE_QUERY_RR_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_PARSE_QUERY_RR_SEL_LEN ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_PARSE_PULL_RR_SEL , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_PARSE_PULL_RR_SEL ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_PARSE_PULL_RR_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_PARSE_PULL_RR_SEL_LEN ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_PARSE_PUSH_RR_SEL , 4 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_PARSE_PUSH_RR_SEL ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_PARSE_PUSH_RR_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_PARSE_PUSH_RR_SEL_LEN ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PULL_PRIO_HYP , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_ARB_PULL_PRIO_HYP ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PULL_PRIO_HYP_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_ARB_PULL_PRIO_HYP_LEN ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PUSH_PRIO_HYP , 9 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_ARB_PUSH_PRIO_HYP ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PUSH_PRIO_HYP_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_ARB_PUSH_PRIO_HYP_LEN ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_QUERY , 12 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_ARB_PRIO_QUERY ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_QUERY_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_ARB_PRIO_QUERY_LEN ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_PUSH , 15 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_ARB_PRIO_PUSH ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_PUSH_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_ARB_PRIO_PUSH_LEN ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_PULL , 18 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_ARB_PRIO_PULL ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_PULL_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_ARB_PRIO_PULL_LEN ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_RR , 21 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_ARB_PRIO_RR ); -REG64_FLD( PU_INT_PC_VRQ_PEND_CFG_CFG_ARB_PRIO_RR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_ARB_PRIO_RR_LEN ); - -REG64_FLD( PU_INT_PC_VRQ_QUE_CFG_CFG_QUEUE_ECC_CORR_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_QUEUE_ECC_CORR_EN ); -REG64_FLD( PU_INT_PC_VRQ_QUE_CFG_CFG_QUEUE_SIZE_PULL , 1 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_QUEUE_SIZE_PULL ); -REG64_FLD( PU_INT_PC_VRQ_QUE_CFG_CFG_QUEUE_SIZE_PULL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_QUEUE_SIZE_PULL_LEN ); -REG64_FLD( PU_INT_PC_VRQ_QUE_CFG_CFG_QUEUE_SIZE_PUSH_LCL , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL ); -REG64_FLD( PU_INT_PC_VRQ_QUE_CFG_CFG_QUEUE_SIZE_PUSH_LCL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL_LEN ); - REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_AUTO_INCREMENT , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_AUTO_INCREMENT ); +REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_1_3 , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_3 ); +REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_1_3_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_1_3_LEN ); +REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_12 , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_12 ); REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_SELECT , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SELECT ); REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_SELECT_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SELECT_LEN ); -REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_16_26 , 16 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_16_26 ); -REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_16_26_LEN , 11 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_16_26_LEN ); +REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_24_26 , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24_26 ); +REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_24_26_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_24_26_LEN ); REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_ADDRESS , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_ADDRESS_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , @@ -36530,6 +46799,160 @@ REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_11 , 11 , SH_UN SH_FLD_INTERRUPT_11 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_12 , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_12 ); +REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_13 , 13 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_INTERRUPT_13 ); +REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_14 , 14 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_INTERRUPT_14 ); +REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_15 , 15 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_INTERRUPT_15 ); +REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_16 , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_INTERRUPT_16 ); +REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_17 , 17 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_INTERRUPT_17 ); +REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_18 , 18 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_INTERRUPT_18 ); +REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_19 , 19 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_INTERRUPT_19 ); +REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_20 , 20 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_INTERRUPT_20 ); +REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_21 , 21 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_INTERRUPT_21 ); +REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_22 , 22 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_INTERRUPT_22 ); + +REG64_FLD( PU_INT_TCTXT_CFG_CFG_BLOCK_GROUP_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_BLOCK_GROUP_EN ); +REG64_FLD( PU_INT_TCTXT_CFG_CFG_ACM_EN , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_ACM_EN ); +REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_2_3 , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_2_3 ); +REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_2_3_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_2_3_LEN ); +REG64_FLD( PU_INT_TCTXT_CFG_CFG_FUSE_CORE_EN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_FUSE_CORE_EN ); +REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_5 , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_5 ); +REG64_FLD( PU_INT_TCTXT_CFG_CFG_SMT_MODE , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_SMT_MODE ); +REG64_FLD( PU_INT_TCTXT_CFG_CFG_SMT_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_SMT_MODE_LEN ); +REG64_FLD( PU_INT_TCTXT_CFG_CFG_HARD_CHIPID_IN_BLOCK_EN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_HARD_CHIPID_IN_BLOCK_EN ); +REG64_FLD( PU_INT_TCTXT_CFG_CFG_CHIPID_OVERRIDE , 9 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_CHIPID_OVERRIDE ); +REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_10_11 , 10 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_10_11 ); +REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_10_11_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_10_11_LEN ); +REG64_FLD( PU_INT_TCTXT_CFG_CFG_CHIPID , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_CHIPID ); +REG64_FLD( PU_INT_TCTXT_CFG_CFG_CHIPID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_CHIPID_LEN ); +REG64_FLD( PU_INT_TCTXT_CFG_CFG_EN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_EN ); +REG64_FLD( PU_INT_TCTXT_CFG_CFG_MSGSND , 17 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_MSGSND ); +REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_18_19 , 18 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_18_19 ); +REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_18_19_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_18_19_LEN ); +REG64_FLD( PU_INT_TCTXT_CFG_CFG_PULSE_WIDTH , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PULSE_WIDTH ); +REG64_FLD( PU_INT_TCTXT_CFG_CFG_PULSE_WIDTH_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_PULSE_WIDTH_LEN ); + +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C0_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C0_EN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C0_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C0_EN_LEN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C1_EN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C1_EN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C1_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C1_EN_LEN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C2_EN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C2_EN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C2_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C2_EN_LEN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C3_EN , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C3_EN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C3_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C3_EN_LEN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C4_EN , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C4_EN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C4_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C4_EN_LEN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C5_EN , 40 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C5_EN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C5_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C5_EN_LEN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C6_EN , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C6_EN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C6_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C6_EN_LEN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C7_EN , 56 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C7_EN ); +REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C7_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C7_EN_LEN ); + +REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C8_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C8_EN ); +REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C8_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C8_EN_LEN ); +REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C9_EN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C9_EN ); +REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C9_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C9_EN_LEN ); +REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C10_EN , 16 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C10_EN ); +REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C10_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C10_EN_LEN ); +REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C11_EN , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C11_EN ); +REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C11_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_THRD_C11_EN_LEN ); + +REG64_FLD( PU_INT_TCTXT_INDIR0_INDIR_VLD , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INDIR_VLD ); +REG64_FLD( PU_INT_TCTXT_INDIR0_INDIR_THRDID , 9 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INDIR_THRDID ); +REG64_FLD( PU_INT_TCTXT_INDIR0_INDIR_THRDID_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INDIR_THRDID_LEN ); + +REG64_FLD( PU_INT_TCTXT_INDIR1_INDIR_VLD , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INDIR_VLD ); +REG64_FLD( PU_INT_TCTXT_INDIR1_INDIR_THRDID , 9 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INDIR_THRDID ); +REG64_FLD( PU_INT_TCTXT_INDIR1_INDIR_THRDID_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INDIR_THRDID_LEN ); + +REG64_FLD( PU_INT_TCTXT_INDIR2_INDIR_VLD , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INDIR_VLD ); +REG64_FLD( PU_INT_TCTXT_INDIR2_INDIR_THRDID , 9 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INDIR_THRDID ); +REG64_FLD( PU_INT_TCTXT_INDIR2_INDIR_THRDID_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INDIR_THRDID_LEN ); + +REG64_FLD( PU_INT_TCTXT_INDIR3_INDIR_VLD , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INDIR_VLD ); +REG64_FLD( PU_INT_TCTXT_INDIR3_INDIR_THRDID , 9 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INDIR_THRDID ); +REG64_FLD( PU_INT_TCTXT_INDIR3_INDIR_THRDID_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_INDIR_THRDID_LEN ); + +REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_BLOCK_EN ); +REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_VPD_EN , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_BLOCK_VPD_EN ); +REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RCMD_FILTER_EN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_BLOCK_RCMD_FILTER_EN ); +REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_3_9 , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_3_9 ); +REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_3_9_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_3_9_LEN ); +REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET_DELAY , 10 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_BLOCK_RESET_DELAY ); +REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET_DELAY_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CFG_BLOCK_RESET_DELAY_LEN ); REG64_FLD( PU_INT_VC_AIB_TIMEOUT_DELAY , 58 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DELAY ); @@ -36593,25 +47016,27 @@ REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_IVC , 40 , SH_UN SH_FLD_IVC ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_IVC_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVC_LEN ); -REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_RESERVED_48_55 , 48 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_48_55 ); -REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_RESERVED_48_55_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_48_55_LEN ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_DMA , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_SBC_DMA ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_DMA_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_SBC_DMA_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SBC_EOI ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SBC_EOI_LEN ); -REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20_22 , 20 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_20_22 ); -REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20_22_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_RESERVED_20_22_LEN ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20_21 , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_20_21 ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20_21_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RESERVED_20_21_LEN ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR , 22 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_RELAXED_WR ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_DISABLE_PTAG_IN_AIBTAG , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DISABLE_PTAG_IN_AIBTAG ); -REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_SBC_DMA , 24 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_SBC_DMA ); -REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_SBC_DMA_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_SBC_DMA_LEN ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_ESBE , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EQC_EOI_ESBE ); +REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_ESBE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EQC_EOI_ESBE_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CISTORE , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQC_CISTORE ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CISTORE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , @@ -38657,6 +49082,165 @@ REG64_FLD( PU_NPU_CTL_LCO_CONFIG_RAND_EVENT , 16 , SH_UN REG64_FLD( PU_NPU_CTL_LCO_CONFIG_RAND_EVENT_LEN , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RAND_EVENT_LEN ); +REG64_FLD( CAPP_LINK_DELAY_TIMER_VALUE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_VALUE ); +REG64_FLD( CAPP_LINK_DELAY_TIMER_VALUE_LEN , 29 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_VALUE_LEN ); +REG64_FLD( CAPP_LINK_DELAY_TIMER_VALID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_VALID ); +REG64_FLD( CAPP_LINK_DELAY_TIMER_RESP_PKT_RCV , 33 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESP_PKT_RCV ); +REG64_FLD( CAPP_LINK_DELAY_TIMER_SECURE_ERR , 34 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SECURE_ERR ); + +REG64_FLD( PEC_LOCAL_FIR_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN0 ); +REG64_FLD( PEC_LOCAL_FIR_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN1 ); +REG64_FLD( PEC_LOCAL_FIR_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN2 ); +REG64_FLD( PEC_LOCAL_FIR_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN3 ); +REG64_FLD( PEC_LOCAL_FIR_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN4 ); +REG64_FLD( PEC_LOCAL_FIR_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN5 ); +REG64_FLD( PEC_LOCAL_FIR_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN6 ); +REG64_FLD( PEC_LOCAL_FIR_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN7 ); +REG64_FLD( PEC_LOCAL_FIR_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN8 ); +REG64_FLD( PEC_LOCAL_FIR_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN9 ); +REG64_FLD( PEC_LOCAL_FIR_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN10 ); +REG64_FLD( PEC_LOCAL_FIR_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN11 ); +REG64_FLD( PEC_LOCAL_FIR_IN12 , 12 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN12 ); +REG64_FLD( PEC_LOCAL_FIR_IN13 , 13 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN13 ); +REG64_FLD( PEC_LOCAL_FIR_IN14 , 14 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN14 ); +REG64_FLD( PEC_LOCAL_FIR_IN15 , 15 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN15 ); +REG64_FLD( PEC_LOCAL_FIR_IN16 , 16 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN16 ); +REG64_FLD( PEC_LOCAL_FIR_IN17 , 17 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN17 ); +REG64_FLD( PEC_LOCAL_FIR_IN18 , 18 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN18 ); +REG64_FLD( PEC_LOCAL_FIR_IN19 , 19 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN19 ); +REG64_FLD( PEC_LOCAL_FIR_IN20 , 20 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN20 ); +REG64_FLD( PEC_LOCAL_FIR_IN21 , 21 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN21 ); +REG64_FLD( PEC_LOCAL_FIR_IN22 , 22 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN22 ); +REG64_FLD( PEC_LOCAL_FIR_IN23 , 23 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN23 ); +REG64_FLD( PEC_LOCAL_FIR_IN24 , 24 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN24 ); +REG64_FLD( PEC_LOCAL_FIR_IN25 , 25 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN25 ); +REG64_FLD( PEC_LOCAL_FIR_IN26 , 26 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN26 ); +REG64_FLD( PEC_LOCAL_FIR_IN27 , 27 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN27 ); +REG64_FLD( PEC_LOCAL_FIR_IN28 , 28 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN28 ); +REG64_FLD( PEC_LOCAL_FIR_IN29 , 29 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN29 ); +REG64_FLD( PEC_LOCAL_FIR_IN30 , 30 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN30 ); +REG64_FLD( PEC_LOCAL_FIR_IN31 , 31 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN31 ); +REG64_FLD( PEC_LOCAL_FIR_IN32 , 32 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN32 ); +REG64_FLD( PEC_LOCAL_FIR_IN33 , 33 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN33 ); +REG64_FLD( PEC_LOCAL_FIR_IN34 , 34 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN34 ); +REG64_FLD( PEC_LOCAL_FIR_IN35 , 35 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN35 ); +REG64_FLD( PEC_LOCAL_FIR_IN36 , 36 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN36 ); +REG64_FLD( PEC_LOCAL_FIR_IN37 , 37 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN37 ); +REG64_FLD( PEC_LOCAL_FIR_IN38 , 38 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN38 ); +REG64_FLD( PEC_LOCAL_FIR_IN39 , 39 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN39 ); +REG64_FLD( PEC_LOCAL_FIR_IN40 , 40 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_IN40 ); + +REG64_FLD( PEC_LOCAL_FIR_ACTION0_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN ); +REG64_FLD( PEC_LOCAL_FIR_ACTION0_IN_LEN , 41 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN_LEN ); + +REG64_FLD( PEC_LOCAL_FIR_ACTION1_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN ); +REG64_FLD( PEC_LOCAL_FIR_ACTION1_IN_LEN , 41 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN_LEN ); + +REG64_FLD( PEC_LOCAL_FIR_MASK_LFIR_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_LFIR_IN ); +REG64_FLD( PEC_LOCAL_FIR_MASK_LFIR_IN_LEN , 41 , SH_UNT_PEC , SH_ACS_SCOM2_OR , + SH_FLD_LFIR_IN_LEN ); + +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN0 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN1 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN2 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN3 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN4 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN5 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN6 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN7 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN8 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN9 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN10 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN11 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN12 , 12 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN12 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN13 , 13 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN13 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN14 , 14 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN14 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN15 , 15 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN15 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN16 , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN16 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN17 , 17 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN17 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN18 , 18 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN18 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN19 , 19 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN19 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN20 , 20 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN20 ); +REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN21 , 21 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_IN21 ); + +REG64_FLD( PEC_LOCAL_XSTOP_MASK_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN ); +REG64_FLD( PEC_LOCAL_XSTOP_MASK_IN_LEN , 22 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN_LEN ); + REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MODE_ENABLE , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_LP_MODE_ENABLE ); REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_ONLY_MODE , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , @@ -38748,9 +49332,15 @@ REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PRB1 , 36 , SH_UN SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); -REG64_FLD( PU_NPU0_SM0_LOW_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES ); +REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES_LEN ); +REG64_FLD( PU_NPU0_SM0_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , @@ -38781,9 +49371,15 @@ REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PRB1 , 36 , SH_UN SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); -REG64_FLD( PU_NPU1_SM2_LOW_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES ); +REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES_LEN ); +REG64_FLD( PU_NPU1_SM2_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , @@ -38814,9 +49410,15 @@ REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PRB1 , 36 , SH_UN SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); -REG64_FLD( PU_NPU2_SM3_LOW_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES ); +REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES_LEN ); +REG64_FLD( PU_NPU2_SM3_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , @@ -38847,9 +49449,15 @@ REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PRB1 , 36 , SH_UN SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); -REG64_FLD( PU_NPU1_SM3_LOW_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES ); +REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES_LEN ); +REG64_FLD( PU_NPU1_SM3_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , @@ -38880,9 +49488,15 @@ REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PRB1 , 36 , SH_UN SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); -REG64_FLD( PU_NPU0_SM3_LOW_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES ); +REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES_LEN ); +REG64_FLD( PU_NPU0_SM3_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , @@ -38913,9 +49527,15 @@ REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PRB1 , 36 , SH_UN SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); -REG64_FLD( PU_NPU1_SM1_LOW_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES ); +REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES_LEN ); +REG64_FLD( PU_NPU1_SM1_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , @@ -38946,9 +49566,15 @@ REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PRB1 , 36 , SH_UN SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); -REG64_FLD( PU_NPU2_SM2_LOW_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES ); +REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES_LEN ); +REG64_FLD( PU_NPU2_SM2_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , @@ -38979,9 +49605,15 @@ REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PRB1 , 36 , SH_UN SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); -REG64_FLD( PU_NPU2_SM1_LOW_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES ); +REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES_LEN ); +REG64_FLD( PU_NPU2_SM1_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , @@ -39012,9 +49644,15 @@ REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PRB1 , 36 , SH_UN SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); -REG64_FLD( PU_NPU0_SM2_LOW_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES ); +REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES_LEN ); +REG64_FLD( PU_NPU0_SM2_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , @@ -39045,9 +49683,15 @@ REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PRB1 , 36 , SH_UN SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); -REG64_FLD( PU_NPU2_SM0_LOW_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES ); +REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES_LEN ); +REG64_FLD( PU_NPU2_SM0_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , @@ -39078,9 +49722,15 @@ REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PRB1 , 36 , SH_UN SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); -REG64_FLD( PU_NPU0_SM1_LOW_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES ); +REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES_LEN ); +REG64_FLD( PU_NPU0_SM1_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , @@ -39111,9 +49761,15 @@ REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PRB1 , 36 , SH_UN SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); -REG64_FLD( PU_NPU1_SM0_LOW_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES ); +REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_MAX_MACHINES_LEN ); +REG64_FLD( PU_NPU1_SM0_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_BUSY_ENABLE , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , @@ -39185,133 +49841,207 @@ REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_RESERVED1 , 34 , SH_UN REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); -REG64_FLD( PEC_STACK2_LSIBAR_REG_PE_LSI_BAR , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , - SH_FLD_PE_LSI_BAR ); -REG64_FLD( PEC_STACK2_LSIBAR_REG_PE_LSI_BAR_LEN , 40 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , - SH_FLD_PE_LSI_BAR_LEN ); - -REG64_FLD( PEC_STACK1_LSIBAR_REG_PE_LSI_BAR , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , - SH_FLD_PE_LSI_BAR ); -REG64_FLD( PEC_STACK1_LSIBAR_REG_PE_LSI_BAR_LEN , 40 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , - SH_FLD_PE_LSI_BAR_LEN ); - -REG64_FLD( PHB_LSIBAR_REG_PE_LSI_BAR , 0 , SH_UNT_PHB , SH_ACS_SCOM , - SH_FLD_PE_LSI_BAR ); -REG64_FLD( PHB_LSIBAR_REG_PE_LSI_BAR_LEN , 40 , SH_UNT_PHB , SH_ACS_SCOM , - SH_FLD_PE_LSI_BAR_LEN ); - -REG64_FLD( PEC_STACK0_LSIBAR_REG_PE_LSI_BAR , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , - SH_FLD_PE_LSI_BAR ); -REG64_FLD( PEC_STACK0_LSIBAR_REG_PE_LSI_BAR_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , - SH_FLD_PE_LSI_BAR_LEN ); - -REG64_FLD( PU_NPU0_SM0_MAX_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM0_MAX_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_MAX_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM0_MAX_BAR_CONFIG_ADDR_LEN , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM0_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM0_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU0_SM0_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU1_SM2_MAX_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM2_MAX_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_MAX_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM2_MAX_BAR_CONFIG_ADDR_LEN , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM2_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM2_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU1_SM2_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU2_SM3_MAX_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM3_MAX_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_MAX_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM3_MAX_BAR_CONFIG_ADDR_LEN , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM3_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM3_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_SM3_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU1_SM3_MAX_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM3_MAX_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_MAX_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM3_MAX_BAR_CONFIG_ADDR_LEN , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM3_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM3_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU1_SM3_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU0_SM3_MAX_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM3_MAX_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_MAX_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM3_MAX_BAR_CONFIG_ADDR_LEN , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM3_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM3_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU0_SM3_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU1_SM1_MAX_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM1_MAX_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_MAX_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM1_MAX_BAR_CONFIG_ADDR_LEN , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM1_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM1_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU1_SM1_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU2_SM2_MAX_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM2_MAX_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_MAX_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM2_MAX_BAR_CONFIG_ADDR_LEN , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM2_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM2_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_SM2_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU2_SM1_MAX_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM1_MAX_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_MAX_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM1_MAX_BAR_CONFIG_ADDR_LEN , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM1_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM1_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_SM1_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU0_SM2_MAX_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM2_MAX_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_MAX_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM2_MAX_BAR_CONFIG_ADDR_LEN , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM2_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM2_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU0_SM2_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU2_SM0_MAX_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM0_MAX_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_MAX_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM0_MAX_BAR_CONFIG_ADDR_LEN , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU2_SM0_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM0_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_SM0_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU0_SM1_MAX_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM1_MAX_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_MAX_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM1_MAX_BAR_CONFIG_ADDR_LEN , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , +REG64_FLD( PU_NPU0_SM1_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM1_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU0_SM1_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); -REG64_FLD( PU_NPU1_SM0_MAX_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_MAX_PHY_BAR_CONFIG_ENABLE , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM0_MAX_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_MAX_PHY_BAR_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_MAX_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_MAX_PHY_BAR_CONFIG_ADDR , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM0_MAX_BAR_CONFIG_ADDR_LEN , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , +REG64_FLD( PU_NPU1_SM0_MAX_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM0_MAX_PHY_BAR_RESERVED2 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU1_SM0_MAX_PHY_BAR_RESERVED2_LEN , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); + +REG64_FLD( PU_MCC_FIR_REG_MCD_ARRAY_ECC_UE_ERR , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MCD_ARRAY_ECC_UE_ERR ); +REG64_FLD( PU_MCC_FIR_REG_MCD_ARRAY_ECC_CE_ERR , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MCD_ARRAY_ECC_CE_ERR ); +REG64_FLD( PU_MCC_FIR_REG_MCD_PB_ADDR_PARITY_ERR , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MCD_PB_ADDR_PARITY_ERR ); +REG64_FLD( PU_MCC_FIR_REG_MCD_SM_OR_CASE_ERR , 3 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MCD_SM_OR_CASE_ERR ); +REG64_FLD( PU_MCC_FIR_REG_MCD_CL_PROBE_PB_HANG_ERR , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MCD_CL_PROBE_PB_HANG_ERR ); +REG64_FLD( PU_MCC_FIR_REG_MCD_CRESP_ADDR_ERR , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MCD_CRESP_ADDR_ERR ); +REG64_FLD( PU_MCC_FIR_REG_MCD_UNSOLICITED_CRESP_ERR , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MCD_UNSOLICITED_CRESP_ERR ); +REG64_FLD( PU_MCC_FIR_REG_MCD_TTAG_PARITY_ERR , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MCD_TTAG_PARITY_ERR ); +REG64_FLD( PU_MCC_FIR_REG_MCD_UPDATE_ERR , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MCD_UPDATE_ERR ); +REG64_FLD( PU_MCC_FIR_REG_MCD_SCOM_ERR , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MCD_SCOM_ERR ); +REG64_FLD( PU_MCC_FIR_REG_MCD_SCOM_ERR_DUP , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_MCD_SCOM_ERR_DUP ); + +REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_ARRAY_ECC_UE_ERR , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_MCD_ARRAY_ECC_UE_ERR ); +REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_ARRAY_ECC_CE_ERR , 1 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_MCD_ARRAY_ECC_CE_ERR ); +REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_PB_ADDR_PARITY_ERR , 2 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_MCD_PB_ADDR_PARITY_ERR ); +REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_SM_OR_CASE_ERR , 3 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_MCD_SM_OR_CASE_ERR ); +REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_CL_PROBE_PB_HANG_ERR , 4 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_MCD_CL_PROBE_PB_HANG_ERR ); +REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_CRESP_ADDR_ERR , 5 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_MCD_CRESP_ADDR_ERR ); +REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_UNSOLICITED_CRESP_ERR , 6 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_MCD_UNSOLICITED_CRESP_ERR ); +REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_TTAG_PARITY_ERR , 7 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_MCD_TTAG_PARITY_ERR ); +REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_UPDATE_ERR , 8 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_MCD_UPDATE_ERR ); +REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_SCOM_ERR , 9 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_MCD_SCOM_ERR ); +REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_SCOM_ERR_DUP , 10 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_MCD_SCOM_ERR_DUP ); REG64_FLD( PU_MCD_DBG_TRACE_ENABLE , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_ENABLE ); @@ -39505,20 +50235,71 @@ REG64_FLD( PU_MCD1_MCD_ECAP_RDWR_UPDATE_ERROR , 53 , SH_UN REG64_FLD( PU_MCD1_MCD_ECAP_REC_UPDATE_ERROR , 54 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_REC_UPDATE_ERROR ); -REG64_FLD( PU_IOPPE_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_TAG_ADDR ); -REG64_FLD( PU_IOPPE_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_TAG_ADDR_LEN ); -REG64_FLD( PU_IOPPE_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_ERR ); -REG64_FLD( PU_IOPPE_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING , 34 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_XISIB_PIB_IFETCH_PENDING ); -REG64_FLD( PU_IOPPE_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_XIMEM_MEM_IFETCH_PENDING ); -REG64_FLD( PU_IOPPE_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_VALID ); -REG64_FLD( PU_IOPPE_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_ICACHE_VALID_LEN ); +REG64_FLD( PU_MCD_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION0 ); +REG64_FLD( PU_MCD_FIR_ACTION0_REG_ACTION0_LEN , 11 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION0_LEN ); + +REG64_FLD( PU_MCD1_MCD_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , + SH_FLD_ACTION0 ); +REG64_FLD( PU_MCD1_MCD_FIR_ACTION0_REG_ACTION0_LEN , 11 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , + SH_FLD_ACTION0_LEN ); + +REG64_FLD( PU_MCD_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION1 ); +REG64_FLD( PU_MCD_FIR_ACTION1_REG_ACTION1_LEN , 11 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION1_LEN ); + +REG64_FLD( PU_MCD1_MCD_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , + SH_FLD_ACTION1 ); +REG64_FLD( PU_MCD1_MCD_FIR_ACTION1_REG_ACTION1_LEN , 11 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , + SH_FLD_ACTION1_LEN ); + +REG64_FLD( PU_MCD_FIR_MASK_REG_ARRAY_ECC_UE , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ARRAY_ECC_UE ); +REG64_FLD( PU_MCD_FIR_MASK_REG_ARRAY_ECC_CE , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ARRAY_ECC_CE ); +REG64_FLD( PU_MCD_FIR_MASK_REG_PB_ADDR_PARITY , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PB_ADDR_PARITY ); +REG64_FLD( PU_MCD_FIR_MASK_REG_SM_OR_CASE , 3 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SM_OR_CASE ); +REG64_FLD( PU_MCD_FIR_MASK_REG_CL_PROBE_PB_HANG , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_CL_PROBE_PB_HANG ); +REG64_FLD( PU_MCD_FIR_MASK_REG_CRESP_ADDR , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_CRESP_ADDR ); +REG64_FLD( PU_MCD_FIR_MASK_REG_UNSOLICITED_CRESP , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UNSOLICITED_CRESP ); +REG64_FLD( PU_MCD_FIR_MASK_REG_TTAG_PARITY , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_TTAG_PARITY ); +REG64_FLD( PU_MCD_FIR_MASK_REG_UPDATE_ERR , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UPDATE_ERR ); +REG64_FLD( PU_MCD_FIR_MASK_REG_SCOM_ERR , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR ); +REG64_FLD( PU_MCD_FIR_MASK_REG_SCOM_ERR_DUP , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR_DUP ); + +REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_ARRAY_ECC_UE , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_ARRAY_ECC_UE ); +REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_ARRAY_ECC_CE , 1 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_ARRAY_ECC_CE ); +REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_PB_ADDR_PARITY , 2 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_PB_ADDR_PARITY ); +REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SM_OR_CASE , 3 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_SM_OR_CASE ); +REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_CL_PROBE_PB_HANG , 4 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_CL_PROBE_PB_HANG ); +REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_CRESP_ADDR , 5 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_CRESP_ADDR ); +REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_UNSOLICITED_CRESP , 6 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_UNSOLICITED_CRESP ); +REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_TTAG_PARITY , 7 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_TTAG_PARITY ); +REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_UPDATE_ERR , 8 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_UPDATE_ERR ); +REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR , 9 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR ); +REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR_DUP , 10 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); @@ -39526,8 +50307,6 @@ REG64_FLD( PU_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); -REG64_FLD( PU_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_XISIB_PIB_IFETCH_PENDING ); REG64_FLD( PU_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , @@ -39535,31 +50314,6 @@ REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID , 36 , SH_UN REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); -REG64_FLD( PU_IOPPE_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_MEM_ADDR ); -REG64_FLD( PU_IOPPE_MIB_XIMEM_MEM_ADDR_LEN , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_MEM_ADDR_LEN ); -REG64_FLD( PU_IOPPE_MIB_XIMEM_MEM_R_NW , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_MEM_R_NW ); -REG64_FLD( PU_IOPPE_MIB_XIMEM_MEM_BUSY , 33 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_MEM_BUSY ); -REG64_FLD( PU_IOPPE_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 34 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_MEM_IMPRECISE_ERROR_PENDING ); -REG64_FLD( PU_IOPPE_MIB_XIMEM_MEM_BYTE_ENABLE , 35 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_MEM_BYTE_ENABLE ); -REG64_FLD( PU_IOPPE_MIB_XIMEM_MEM_BYTE_ENABLE_LEN , 8 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_MEM_BYTE_ENABLE_LEN ); -REG64_FLD( PU_IOPPE_MIB_XIMEM_MEM_LINE_MODE , 43 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_MEM_LINE_MODE ); -REG64_FLD( PU_IOPPE_MIB_XIMEM_MEM_ERROR , 49 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_MEM_ERROR ); -REG64_FLD( PU_IOPPE_MIB_XIMEM_MEM_ERROR_LEN , 3 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_MEM_ERROR_LEN ); -REG64_FLD( PU_IOPPE_MIB_XIMEM_MEM_IFETCH_PENDING , 62 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_MEM_IFETCH_PENDING ); -REG64_FLD( PU_IOPPE_MIB_XIMEM_MEM_DATAOP_PENDING , 63 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_MEM_DATAOP_PENDING ); - REG64_FLD( PU_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); REG64_FLD( PU_MIB_XIMEM_MEM_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , @@ -39585,19 +50339,6 @@ REG64_FLD( PU_MIB_XIMEM_MEM_IFETCH_PENDING , 62 , SH_UN REG64_FLD( PU_MIB_XIMEM_MEM_DATAOP_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_DATAOP_PENDING ); -REG64_FLD( PU_IOPPE_MIB_XISGB_STORE_ADDRESS , 0 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_STORE_ADDRESS ); -REG64_FLD( PU_IOPPE_MIB_XISGB_STORE_ADDRESS_LEN , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_STORE_ADDRESS_LEN ); -REG64_FLD( PU_IOPPE_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 35 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING ); -REG64_FLD( PU_IOPPE_MIB_XISGB_SGB_BYTE_VALID , 36 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_SGB_BYTE_VALID ); -REG64_FLD( PU_IOPPE_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_SGB_BYTE_VALID_LEN ); -REG64_FLD( PU_IOPPE_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_SGB_FLUSH_PENDING ); - REG64_FLD( PU_MIB_XISGB_STORE_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS ); REG64_FLD( PU_MIB_XISGB_STORE_ADDRESS_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , @@ -39611,145 +50352,150 @@ REG64_FLD( PU_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PU_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); -REG64_FLD( PU_IOPPE_MIB_XISIB_PIB_ADDR , 0 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_PIB_ADDR ); -REG64_FLD( PU_IOPPE_MIB_XISIB_PIB_ADDR_LEN , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_PIB_ADDR_LEN ); -REG64_FLD( PU_IOPPE_MIB_XISIB_PIB_R_NW , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_PIB_R_NW ); -REG64_FLD( PU_IOPPE_MIB_XISIB_PIB_BUSY , 33 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_PIB_BUSY ); -REG64_FLD( PU_IOPPE_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING , 34 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_PIB_IMPRECISE_ERROR_PENDING ); -REG64_FLD( PU_IOPPE_MIB_XISIB_PIB_RSP_INFO , 49 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_PIB_RSP_INFO ); -REG64_FLD( PU_IOPPE_MIB_XISIB_PIB_RSP_INFO_LEN , 3 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_PIB_RSP_INFO_LEN ); -REG64_FLD( PU_IOPPE_MIB_XISIB_PIB_IFETCH_PENDING , 62 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_PIB_IFETCH_PENDING ); -REG64_FLD( PU_IOPPE_MIB_XISIB_PIB_DATAOP_PENDING , 63 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_RO , - SH_FLD_PIB_DATAOP_PENDING ); - -REG64_FLD( PU_MIB_XISIB_PIB_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_ADDR ); -REG64_FLD( PU_MIB_XISIB_PIB_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_ADDR_LEN ); -REG64_FLD( PU_MIB_XISIB_PIB_R_NW , 32 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_R_NW ); -REG64_FLD( PU_MIB_XISIB_PIB_BUSY , 33 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_BUSY ); -REG64_FLD( PU_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_IMPRECISE_ERROR_PENDING ); -REG64_FLD( PU_MIB_XISIB_PIB_RSP_INFO , 49 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_RSP_INFO ); -REG64_FLD( PU_MIB_XISIB_PIB_RSP_INFO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_RSP_INFO_LEN ); -REG64_FLD( PU_MIB_XISIB_PIB_IFETCH_PENDING , 62 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_IFETCH_PENDING ); -REG64_FLD( PU_MIB_XISIB_PIB_DATAOP_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , - SH_FLD_PIB_DATAOP_PENDING ); - REG64_FLD( PU_NPU_CTL_MISC_CONFIG_SYNC_WAIT , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_SYNC_WAIT ); REG64_FLD( PU_NPU_CTL_MISC_CONFIG_SYNC_WAIT_LEN , 5 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_SYNC_WAIT_LEN ); - -REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_ENABLE , 5 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_PERF_ENABLE ); +REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_PE_MASK , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_PERF_PE_MASK ); +REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_PE_MATCH , 7 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_PERF_PE_MATCH ); +REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_PE_MATCH_LEN , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_PERF_PE_MATCH_LEN ); +REG64_FLD( PU_NPU_CTL_MISC_CONFIG_RSVD , 11 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_RSVD ); +REG64_FLD( PU_NPU_CTL_MISC_CONFIG_RSVD_LEN , 53 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_RSVD_LEN ); + +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL0_STALL , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_NDL0_STALL ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL0_NOSTALL , 1 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_NDL0_NOSTALL ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL1_STALL , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_NDL1_STALL ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL1_NOSTALL , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_NDL1_NOSTALL ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL2_STALL , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_NDL2_STALL ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL2_NOSTALL , 5 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_NDL2_NOSTALL ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL3_STALL , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_NDL3_STALL ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL3_NOSTALL , 7 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_NDL3_NOSTALL ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL4_STALL , 8 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_NDL4_STALL ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL4_NOSTALL , 9 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_NDL4_NOSTALL ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL5_STALL , 10 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_NDL5_STALL ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL5_NOSTALL , 11 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_NDL5_NOSTALL ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_RING_ERRP , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_RING_ERRP ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_IBAR_ERRP , 13 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_IBAR_ERRP ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_SCOMDAA_ERRP , 14 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_SCOMDAA_ERRP ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_CNTL_ERRP , 15 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_CNTL_ERRP ); +REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_MM_LOCAL_XSTOP , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_IDIAL_MM_LOCAL_XSTOP ); + +REG64_FLD( PU_NPU_CTL_MISC_MASK_IDIAL , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); -REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_LEN , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , +REG64_FLD( PU_NPU_CTL_MISC_MASK_IDIAL_LEN , 17 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); -REG64_FLD( PU_NPU_CTL_MISC_MASK_IDIAL_MASK0 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_MASK0 ); -REG64_FLD( PU_NPU_CTL_MISC_MASK_IDIAL_MASK0_LEN , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , - SH_FLD_IDIAL_MASK0_LEN ); - -REG64_FLD( PEC_STACK2_MMIOBAR0_MASK_REG_PE_MMIO_MASK0 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , - SH_FLD_PE_MMIO_MASK0 ); -REG64_FLD( PEC_STACK2_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN , 40 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , - SH_FLD_PE_MMIO_MASK0_LEN ); - -REG64_FLD( PEC_STACK1_MMIOBAR0_MASK_REG_PE_MMIO_MASK0 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , - SH_FLD_PE_MMIO_MASK0 ); -REG64_FLD( PEC_STACK1_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN , 40 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , - SH_FLD_PE_MMIO_MASK0_LEN ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_LN , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DMA_WR_DISABLE_LN ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_GROUP , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DMA_WR_DISABLE_GROUP ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_VG_NOT_SYS , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DMA_WR_DISABLE_VG_NOT_SYS ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_NN_RN , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DMA_WR_DISABLE_NN_RN ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_LN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DMA_RD_DISABLE_LN ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_GROUP , 5 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DMA_RD_DISABLE_GROUP ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_VG_NOT_SYS , 6 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DMA_RD_DISABLE_VG_NOT_SYS ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_NN_RN , 7 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DMA_RD_DISABLE_NN_RN ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_CRED_MASK , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_LCO_CRED_MASK ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_CRED_MASK_LEN , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_LCO_CRED_MASK_LEN ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_MIN , 11 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_LCO_TARG_MIN ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_MIN_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_LCO_TARG_MIN_LEN ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_CONFIG , 15 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_LCO_TARG_CONFIG ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_CONFIG_LEN , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_LCO_TARG_CONFIG_LEN ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_UNUSED , 27 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_UNUSED_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_UNUSED_LEN ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_NX_FREEZE_MODES , 31 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NX_FREEZE_MODES ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_NX_FREEZE_MODES_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NX_FREEZE_MODES_LEN ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_ADDR_BAR , 33 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_ADDR_BAR ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_SKIP_G , 34 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_SKIP_G ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_RESERVED , 35 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_RESERVED_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RESERVED_LEN ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_NXCQ_HANG_SM_ON_ARE , 37 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NXCQ_HANG_SM_ON_ARE ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_NXCQ_HANG_SM_ON_LINK_FAIL , 38 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NXCQ_HANG_SM_ON_LINK_FAIL ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_CFG_PUMP , 39 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_CFG_PUMP ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DMA_RD_VG_RESET_TIMER_MASK ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK_LEN , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DMA_RD_VG_RESET_TIMER_MASK_LEN ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DMA_WR_VG_RESET_TIMER_MASK ); +REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK_LEN , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DMA_WR_VG_RESET_TIMER_MASK_LEN ); REG64_FLD( PHB_MMIOBAR0_MASK_REG_PE_MMIO_MASK0 , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK0 ); REG64_FLD( PHB_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN , 40 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK0_LEN ); -REG64_FLD( PEC_STACK0_MMIOBAR0_MASK_REG_PE_MMIO_MASK0 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , - SH_FLD_PE_MMIO_MASK0 ); -REG64_FLD( PEC_STACK0_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , - SH_FLD_PE_MMIO_MASK0_LEN ); - -REG64_FLD( PEC_STACK2_MMIOBAR0_REG_PE_MMIO_BAR0 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , - SH_FLD_PE_MMIO_BAR0 ); -REG64_FLD( PEC_STACK2_MMIOBAR0_REG_PE_MMIO_BAR0_LEN , 40 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , - SH_FLD_PE_MMIO_BAR0_LEN ); - -REG64_FLD( PEC_STACK1_MMIOBAR0_REG_PE_MMIO_BAR0 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , - SH_FLD_PE_MMIO_BAR0 ); -REG64_FLD( PEC_STACK1_MMIOBAR0_REG_PE_MMIO_BAR0_LEN , 40 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , - SH_FLD_PE_MMIO_BAR0_LEN ); - REG64_FLD( PHB_MMIOBAR0_REG_PE_MMIO_BAR0 , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR0 ); REG64_FLD( PHB_MMIOBAR0_REG_PE_MMIO_BAR0_LEN , 40 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR0_LEN ); -REG64_FLD( PEC_STACK0_MMIOBAR0_REG_PE_MMIO_BAR0 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , - SH_FLD_PE_MMIO_BAR0 ); -REG64_FLD( PEC_STACK0_MMIOBAR0_REG_PE_MMIO_BAR0_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , - SH_FLD_PE_MMIO_BAR0_LEN ); - -REG64_FLD( PEC_STACK2_MMIOBAR1_MASK_REG_PE_MMIO_MASK1 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , - SH_FLD_PE_MMIO_MASK1 ); -REG64_FLD( PEC_STACK2_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN , 40 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , - SH_FLD_PE_MMIO_MASK1_LEN ); - -REG64_FLD( PEC_STACK1_MMIOBAR1_MASK_REG_PE_MMIO_MASK1 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , - SH_FLD_PE_MMIO_MASK1 ); -REG64_FLD( PEC_STACK1_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN , 40 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , - SH_FLD_PE_MMIO_MASK1_LEN ); - REG64_FLD( PHB_MMIOBAR1_MASK_REG_PE_MMIO_MASK1 , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK1 ); REG64_FLD( PHB_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN , 40 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK1_LEN ); -REG64_FLD( PEC_STACK0_MMIOBAR1_MASK_REG_PE_MMIO_MASK1 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , - SH_FLD_PE_MMIO_MASK1 ); -REG64_FLD( PEC_STACK0_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , - SH_FLD_PE_MMIO_MASK1_LEN ); - -REG64_FLD( PEC_STACK2_MMIOBAR1_REG_PE_MMIO_BAR1 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , - SH_FLD_PE_MMIO_BAR1 ); -REG64_FLD( PEC_STACK2_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , - SH_FLD_PE_MMIO_BAR1_LEN ); - -REG64_FLD( PEC_STACK1_MMIOBAR1_REG_PE_MMIO_BAR1 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , - SH_FLD_PE_MMIO_BAR1 ); -REG64_FLD( PEC_STACK1_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , - SH_FLD_PE_MMIO_BAR1_LEN ); - REG64_FLD( PHB_MMIOBAR1_REG_PE_MMIO_BAR1 , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR1 ); REG64_FLD( PHB_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR1_LEN ); -REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , - SH_FLD_PE_MMIO_BAR1 ); -REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , - SH_FLD_PE_MMIO_BAR1_LEN ); - REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_BKINV_INTERLOCK_DIS , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_BKINV_INTERLOCK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_LFSR_DIS , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LFSR_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_LFSR_DIS , 9 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_LFSR_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_INV_AMORT_DIS , 10 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_FBC_INV_AMORT_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_DIN_ECC_CHK_DIS , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_DIN_ECC_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_ECC_CHK_DIS , 13 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -39770,6 +50516,28 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_INV_PROT_ERR_CHK_DIS , 20 , SH_UN SH_FLD_INV_PROT_ERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_INV_TIMEOUT_CHK_DIS , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_INV_TIMEOUT_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_TW_PROT_ERR_CHK_DIS , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_TW_PROT_ERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_TW_TIMEOUT_CHK_DIS , 23 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_TW_TIMEOUT_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_SNP_PROT_ERR_CHK_DIS , 24 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_FBC_SNP_PROT_ERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_SNP_TIMEOUT_CHK_DIS , 25 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_FBC_SNP_TIMEOUT_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_CMD_PROT_ERR_CHK_DIS , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_FBC_CMD_PROT_ERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_HANG_PLS_MULT , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_HANG_PLS_MULT ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_HANG_PLS_MULT_LEN , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_HANG_PLS_MULT_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_INC_RATE , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NCU_SNP_TLBIE_INC_RATE ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_INC_RATE_LEN , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NCU_SNP_TLBIE_INC_RATE_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_DEC_RATE , 56 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NCU_SNP_TLBIE_DEC_RATE ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_DEC_RATE_LEN , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NCU_SNP_TLBIE_DEC_RATE_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_MBR_DIS , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MBR_DIS ); @@ -39783,6 +50551,20 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DMAP_MODE_EN , 18 , SH_UN SH_FLD_DMAP_MODE_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ALT_SEGSZ_DIS , 19 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_ALT_SEGSZ_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DIR_PERR_CHK_DIS , 20 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DIR_PERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_CAC_PERR_CHK_DIS , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_CAC_PERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_LRU_PERR_CHK_DIS , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_LRU_PERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS0_STG0_SEL , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DBG_BUS0_STG0_SEL ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DBG_BUS0_STG0_SEL_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS1_STG0_SEL , 36 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DBG_BUS1_STG0_SEL ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS1_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DBG_BUS1_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TWSM_DIS , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TWSM_DIS ); @@ -39794,6 +50576,12 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_CKINSM_DIS_LEN , 8 , SH_UN SH_FLD_CKINSM_DIS_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_INV_SINGLE_THREAD_EN , 20 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_INV_SINGLE_THREAD_EN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_CXT_CAC_DIS , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_TW_CXT_CAC_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_CNT_THRESH , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NCU_SNP_TLBIE_CNT_THRESH ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_CNT_THRESH_LEN , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NCU_SNP_TLBIE_CNT_THRESH_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_HPT_SAO_FOLD_DIS , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_ATT_HPT_SAO_FOLD_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_RDX_SAO_FOLD_DIS , 41 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -39816,6 +50604,20 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PWC_L4_DIS , 49 , SH_UN SH_FLD_TW_LCO_RDX_PWC_L4_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PDE_EN , 50 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_LCO_RDX_PDE_EN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_DIS , 52 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_TW_RDX_PWC_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_INT_PWC_DIS , 53 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_TW_RDX_INT_PWC_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_INT_TLB_DIS , 54 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_TW_RDX_INT_TLB_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_SPLIT_EN , 55 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_TW_RDX_PWC_SPLIT_EN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_VA_HASH , 56 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_TW_RDX_PWC_VA_HASH ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_PTE_UPD_INTR_EN , 58 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_TW_PTE_UPD_INTR_EN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_PACING_CNT_EN , 59 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_NCU_SNP_TLBIE_PACING_CNT_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_MBR_DIS , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MBR_DIS ); @@ -39833,6 +50635,20 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_LPID_DIS , 20 , SH_UN SH_FLD_HASH_LPID_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HASH_PID_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DIR_PERR_CHK_DIS , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DIR_PERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_CAC_PERR_CHK_DIS , 23 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_CAC_PERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_LRU_PERR_CHK_DIS , 24 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_LRU_PERR_CHK_DIS ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DBG_BUS0_STG0_SEL ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DBG_BUS0_STG0_SEL_LEN ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL , 36 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DBG_BUS1_STG0_SEL ); +REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DBG_BUS1_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0_HRMOR , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HRMOR ); @@ -39849,6 +50665,25 @@ REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG2_SEIDBAR , 0 , SH_UN REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG2_SEIDBAR_LEN , 64 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_SEIDBAR_LEN ); +REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_CNT_VAL , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_WR_TIER_1_CNT_VAL ); +REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_CNT_VAL_LEN , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_WR_TIER_1_CNT_VAL_LEN ); +REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_DIV_VAL , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_WR_TIER_1_DIV_VAL ); +REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_DIV_VAL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_WR_TIER_1_DIV_VAL_LEN ); +REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_CNT_VAL , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_WR_TIER_2_CNT_VAL ); +REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_CNT_VAL_LEN , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_WR_TIER_2_CNT_VAL_LEN ); +REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_DIV_VAL , 28 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_WR_TIER_2_DIV_VAL ); +REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_DIV_VAL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_WR_TIER_2_DIV_VAL_LEN ); +REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_DISABLE , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_DISABLE ); + REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_EN , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_EN ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_PRV_BUS0_STG2_SEL , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -39903,6 +50738,38 @@ REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS0_STG1_SEL , 25 , SH_UN SH_FLD_TLB_BUS0_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS1_STG1_SEL , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TLB_BUS1_STG1_SEL ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG0_SEL , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_FBC_BUS0_STG0_SEL ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_FBC_BUS0_STG0_SEL_LEN ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG0_SEL , 36 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_FBC_BUS1_STG0_SEL ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_FBC_BUS1_STG0_SEL_LEN ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG0_SEL , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_MSC_BUS0_STG0_SEL ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_MSC_BUS0_STG0_SEL_LEN ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG0_SEL , 44 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_MSC_BUS1_STG0_SEL ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_MSC_BUS1_STG0_SEL_LEN ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG0_SEL , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_TW_BUS0_STG0_SEL ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG0_SEL_LEN , 6 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_TW_BUS0_STG0_SEL_LEN ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG0_SEL , 54 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_TW_BUS1_STG0_SEL ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG0_SEL_LEN , 6 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_TW_BUS1_STG0_SEL_LEN ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG0_SEL , 60 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RDX_BUS0_STG0_SEL ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG0_SEL_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RDX_BUS0_STG0_SEL_LEN ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG0_SEL , 62 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RDX_BUS1_STG0_SEL ); +REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG0_SEL_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , + SH_FLD_RDX_BUS1_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_NMMU_ERR_INJ_INJ , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_INJ ); @@ -39914,26 +50781,50 @@ REG64_FLD( PU_NMMU_MM_NMMU_ERR_LOG_LOG , 0 , SH_UN REG64_FLD( PU_NMMU_MM_NMMU_ERR_LOG_LOG_LEN , 64 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LOG_LEN ); -REG64_FLD( PU_NMMU_MM_NMMU_FIR_FIR , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , - SH_FLD_FIR ); -REG64_FLD( PU_NMMU_MM_NMMU_FIR_FIR_LEN , 64 , SH_UNT_PU_NMMU , SH_ACS_SCOM , - SH_FLD_FIR_LEN ); - -REG32_FLD( PU_MODE_REGISTER_DCOMP_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PEC_MODE_REG_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN0 ); +REG64_FLD( PEC_MODE_REG_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN1 ); +REG64_FLD( PEC_MODE_REG_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN2 ); +REG64_FLD( PEC_MODE_REG_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN3 ); +REG64_FLD( PEC_MODE_REG_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN4 ); +REG64_FLD( PEC_MODE_REG_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN5 ); +REG64_FLD( PEC_MODE_REG_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN6 ); +REG64_FLD( PEC_MODE_REG_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN7 ); +REG64_FLD( PEC_MODE_REG_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN8 ); +REG64_FLD( PEC_MODE_REG_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN9 ); +REG64_FLD( PEC_MODE_REG_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN10 ); +REG64_FLD( PEC_MODE_REG_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN11 ); +REG64_FLD( PEC_MODE_REG_IN , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN ); +REG64_FLD( PEC_MODE_REG_IN_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN_LEN ); + +REG64_FLD( PU_MODE_REGISTER_DCOMP_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DCOMP_ENABLE ); -REG32_FLD( PU_MODE_REGISTER_ECC_ENABLE , 1 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_MODE_REGISTER_ECC_ENABLE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_ENABLE ); -REG32_FLD( PU_MODE_REGISTER_PROGRAM_ENABLE , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_MODE_REGISTER_PROGRAM_ENABLE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PROGRAM_ENABLE ); -REG32_FLD( PU_MODE_REGISTER_ECC_CHK_DISABLE , 3 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_MODE_REGISTER_ECC_CHK_DISABLE , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CHK_DISABLE ); -REG32_FLD( PU_MODE_REGISTER_UNUSED_4_15 , 4 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_MODE_REGISTER_UNUSED_4_15 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_4_15 ); -REG32_FLD( PU_MODE_REGISTER_UNUSED_4_15_LEN , 12 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_MODE_REGISTER_UNUSED_4_15_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_4_15_LEN ); -REG32_FLD( PU_MODE_REGISTER_CLK_RATE_SEL , 16 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_MODE_REGISTER_CLK_RATE_SEL , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLK_RATE_SEL ); -REG32_FLD( PU_MODE_REGISTER_CLK_RATE_SEL_LEN , 16 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_MODE_REGISTER_CLK_RATE_SEL_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLK_RATE_SEL_LEN ); REG64_FLD( PU_MODE_REGISTER_B_BIT_RATE_DIVISOR_0 , 10 , SH_UNT , SH_ACS_SCOM , @@ -40036,451 +50927,336 @@ REG64_FLD( PU_MODE_REGISTER_E_PEEK_DATA1_3_LEN , 8 , SH_UN REG64_FLD( PU_MODE_REGISTER_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); -REG64_FLD( PEC_STACK2_MSIBAR_REG_PE_MSI_BAR , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , - SH_FLD_PE_MSI_BAR ); -REG64_FLD( PEC_STACK2_MSIBAR_REG_PE_MSI_BAR_LEN , 32 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , - SH_FLD_PE_MSI_BAR_LEN ); - -REG64_FLD( PEC_STACK1_MSIBAR_REG_PE_MSI_BAR , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , - SH_FLD_PE_MSI_BAR ); -REG64_FLD( PEC_STACK1_MSIBAR_REG_PE_MSI_BAR_LEN , 32 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , - SH_FLD_PE_MSI_BAR_LEN ); - -REG64_FLD( PHB_MSIBAR_REG_PE_MSI_BAR , 0 , SH_UNT_PHB , SH_ACS_SCOM , - SH_FLD_PE_MSI_BAR ); -REG64_FLD( PHB_MSIBAR_REG_PE_MSI_BAR_LEN , 32 , SH_UNT_PHB , SH_ACS_SCOM , - SH_FLD_PE_MSI_BAR_LEN ); - -REG64_FLD( PEC_STACK0_MSIBAR_REG_PE_MSI_BAR , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , - SH_FLD_PE_MSI_BAR ); -REG64_FLD( PEC_STACK0_MSIBAR_REG_PE_MSI_BAR_LEN , 32 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , - SH_FLD_PE_MSI_BAR_LEN ); - -REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM0_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM0_NDT0_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM2_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM2_NDT0_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM3_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM3_NDT0_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM3_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM3_NDT0_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM3_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM3_NDT0_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM1_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM1_NDT0_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM2_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM2_NDT0_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM1_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM1_NDT0_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM2_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM2_NDT0_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM0_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM0_NDT0_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM1_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM1_NDT0_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM0_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM0_NDT0_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM0_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM0_NDT1_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM2_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM2_NDT1_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM3_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM3_NDT1_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM3_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM3_NDT1_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM3_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM3_NDT1_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM1_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM1_NDT1_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM2_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM2_NDT1_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM1_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM1_NDT1_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM2_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM2_NDT1_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM0_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM0_NDT1_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM1_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM1_NDT1_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PEC_NESTTRC_REG_PE_ENABLENESTTRACE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , - SH_FLD_PE_ENABLENESTTRACE ); -REG64_FLD( PEC_NESTTRC_REG_PE_NESTTRACESEL , 1 , SH_UNT_PEC , SH_ACS_SCOM_RW , - SH_FLD_PE_NESTTRACESEL ); -REG64_FLD( PEC_NESTTRC_REG_PE_NESTTRACESEL_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , - SH_FLD_PE_NESTTRACESEL_LEN ); - -REG64_FLD( PEC_STACK2_NFIRACTION0_REG_NFIRACTION0 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , - SH_FLD_NFIRACTION0 ); -REG64_FLD( PEC_STACK2_NFIRACTION0_REG_NFIRACTION0_LEN , 30 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , - SH_FLD_NFIRACTION0_LEN ); - -REG64_FLD( PEC_STACK1_NFIRACTION0_REG_NFIRACTION0 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , - SH_FLD_NFIRACTION0 ); -REG64_FLD( PEC_STACK1_NFIRACTION0_REG_NFIRACTION0_LEN , 30 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , - SH_FLD_NFIRACTION0_LEN ); +REG64_FLD( PEC_MULTICAST_GROUP_1_MULTICAST1 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MULTICAST1 ); +REG64_FLD( PEC_MULTICAST_GROUP_1_MULTICAST1_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MULTICAST1_LEN ); + +REG64_FLD( PEC_MULTICAST_GROUP_2_MULTICAST2 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MULTICAST2 ); +REG64_FLD( PEC_MULTICAST_GROUP_2_MULTICAST2_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MULTICAST2_LEN ); + +REG64_FLD( PEC_MULTICAST_GROUP_3_MULTICAST3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MULTICAST3 ); +REG64_FLD( PEC_MULTICAST_GROUP_3_MULTICAST3_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MULTICAST3_LEN ); + +REG64_FLD( PEC_MULTICAST_GROUP_4_MULTICAST4 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MULTICAST4 ); +REG64_FLD( PEC_MULTICAST_GROUP_4_MULTICAST4_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MULTICAST4_LEN ); + +REG64_FLD( PU_NPU0_SM0_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ENABLE ); +REG64_FLD( PU_NPU0_SM0_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED1 ); +REG64_FLD( PU_NPU0_SM0_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR ); +REG64_FLD( PU_NPU0_SM0_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM0_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2 ); +REG64_FLD( PU_NPU0_SM0_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2_LEN ); +REG64_FLD( PU_NPU0_SM0_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ENABLE ); +REG64_FLD( PU_NPU0_SM0_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED1 ); +REG64_FLD( PU_NPU0_SM0_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR ); +REG64_FLD( PU_NPU0_SM0_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM0_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2 ); +REG64_FLD( PU_NPU0_SM0_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2_LEN ); + +REG64_FLD( PU_NPU1_SM2_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ENABLE ); +REG64_FLD( PU_NPU1_SM2_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED1 ); +REG64_FLD( PU_NPU1_SM2_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR ); +REG64_FLD( PU_NPU1_SM2_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM2_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2 ); +REG64_FLD( PU_NPU1_SM2_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2_LEN ); +REG64_FLD( PU_NPU1_SM2_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ENABLE ); +REG64_FLD( PU_NPU1_SM2_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED1 ); +REG64_FLD( PU_NPU1_SM2_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR ); +REG64_FLD( PU_NPU1_SM2_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM2_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2 ); +REG64_FLD( PU_NPU1_SM2_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2_LEN ); + +REG64_FLD( PU_NPU2_SM3_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ENABLE ); +REG64_FLD( PU_NPU2_SM3_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED1 ); +REG64_FLD( PU_NPU2_SM3_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR ); +REG64_FLD( PU_NPU2_SM3_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM3_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2 ); +REG64_FLD( PU_NPU2_SM3_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_SM3_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ENABLE ); +REG64_FLD( PU_NPU2_SM3_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED1 ); +REG64_FLD( PU_NPU2_SM3_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR ); +REG64_FLD( PU_NPU2_SM3_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM3_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2 ); +REG64_FLD( PU_NPU2_SM3_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2_LEN ); + +REG64_FLD( PU_NPU1_SM3_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ENABLE ); +REG64_FLD( PU_NPU1_SM3_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED1 ); +REG64_FLD( PU_NPU1_SM3_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR ); +REG64_FLD( PU_NPU1_SM3_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM3_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2 ); +REG64_FLD( PU_NPU1_SM3_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2_LEN ); +REG64_FLD( PU_NPU1_SM3_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ENABLE ); +REG64_FLD( PU_NPU1_SM3_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED1 ); +REG64_FLD( PU_NPU1_SM3_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR ); +REG64_FLD( PU_NPU1_SM3_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM3_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2 ); +REG64_FLD( PU_NPU1_SM3_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2_LEN ); + +REG64_FLD( PU_NPU0_SM3_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ENABLE ); +REG64_FLD( PU_NPU0_SM3_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED1 ); +REG64_FLD( PU_NPU0_SM3_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR ); +REG64_FLD( PU_NPU0_SM3_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM3_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2 ); +REG64_FLD( PU_NPU0_SM3_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2_LEN ); +REG64_FLD( PU_NPU0_SM3_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ENABLE ); +REG64_FLD( PU_NPU0_SM3_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED1 ); +REG64_FLD( PU_NPU0_SM3_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR ); +REG64_FLD( PU_NPU0_SM3_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM3_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2 ); +REG64_FLD( PU_NPU0_SM3_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2_LEN ); + +REG64_FLD( PU_NPU1_SM1_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ENABLE ); +REG64_FLD( PU_NPU1_SM1_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED1 ); +REG64_FLD( PU_NPU1_SM1_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR ); +REG64_FLD( PU_NPU1_SM1_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM1_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2 ); +REG64_FLD( PU_NPU1_SM1_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2_LEN ); +REG64_FLD( PU_NPU1_SM1_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ENABLE ); +REG64_FLD( PU_NPU1_SM1_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED1 ); +REG64_FLD( PU_NPU1_SM1_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR ); +REG64_FLD( PU_NPU1_SM1_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM1_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2 ); +REG64_FLD( PU_NPU1_SM1_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2_LEN ); + +REG64_FLD( PU_NPU2_SM2_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ENABLE ); +REG64_FLD( PU_NPU2_SM2_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED1 ); +REG64_FLD( PU_NPU2_SM2_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR ); +REG64_FLD( PU_NPU2_SM2_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM2_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2 ); +REG64_FLD( PU_NPU2_SM2_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_SM2_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ENABLE ); +REG64_FLD( PU_NPU2_SM2_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED1 ); +REG64_FLD( PU_NPU2_SM2_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR ); +REG64_FLD( PU_NPU2_SM2_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM2_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2 ); +REG64_FLD( PU_NPU2_SM2_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2_LEN ); + +REG64_FLD( PU_NPU2_SM1_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ENABLE ); +REG64_FLD( PU_NPU2_SM1_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED1 ); +REG64_FLD( PU_NPU2_SM1_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR ); +REG64_FLD( PU_NPU2_SM1_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM1_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2 ); +REG64_FLD( PU_NPU2_SM1_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_SM1_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ENABLE ); +REG64_FLD( PU_NPU2_SM1_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED1 ); +REG64_FLD( PU_NPU2_SM1_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR ); +REG64_FLD( PU_NPU2_SM1_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM1_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2 ); +REG64_FLD( PU_NPU2_SM1_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2_LEN ); + +REG64_FLD( PU_NPU0_SM2_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ENABLE ); +REG64_FLD( PU_NPU0_SM2_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED1 ); +REG64_FLD( PU_NPU0_SM2_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR ); +REG64_FLD( PU_NPU0_SM2_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM2_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2 ); +REG64_FLD( PU_NPU0_SM2_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2_LEN ); +REG64_FLD( PU_NPU0_SM2_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ENABLE ); +REG64_FLD( PU_NPU0_SM2_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED1 ); +REG64_FLD( PU_NPU0_SM2_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR ); +REG64_FLD( PU_NPU0_SM2_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM2_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2 ); +REG64_FLD( PU_NPU0_SM2_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2_LEN ); + +REG64_FLD( PU_NPU2_SM0_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ENABLE ); +REG64_FLD( PU_NPU2_SM0_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED1 ); +REG64_FLD( PU_NPU2_SM0_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR ); +REG64_FLD( PU_NPU2_SM0_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM0_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2 ); +REG64_FLD( PU_NPU2_SM0_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2_LEN ); +REG64_FLD( PU_NPU2_SM0_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ENABLE ); +REG64_FLD( PU_NPU2_SM0_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED1 ); +REG64_FLD( PU_NPU2_SM0_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR ); +REG64_FLD( PU_NPU2_SM0_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR_LEN ); +REG64_FLD( PU_NPU2_SM0_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2 ); +REG64_FLD( PU_NPU2_SM0_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2_LEN ); + +REG64_FLD( PU_NPU0_SM1_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ENABLE ); +REG64_FLD( PU_NPU0_SM1_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED1 ); +REG64_FLD( PU_NPU0_SM1_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR ); +REG64_FLD( PU_NPU0_SM1_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM1_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2 ); +REG64_FLD( PU_NPU0_SM1_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2_LEN ); +REG64_FLD( PU_NPU0_SM1_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ENABLE ); +REG64_FLD( PU_NPU0_SM1_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED1 ); +REG64_FLD( PU_NPU0_SM1_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR ); +REG64_FLD( PU_NPU0_SM1_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR_LEN ); +REG64_FLD( PU_NPU0_SM1_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2 ); +REG64_FLD( PU_NPU0_SM1_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2_LEN ); + +REG64_FLD( PU_NPU1_SM0_NDT_BAR_CONFIG_NDT0_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ENABLE ); +REG64_FLD( PU_NPU1_SM0_NDT_BAR_NDT0_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED1 ); +REG64_FLD( PU_NPU1_SM0_NDT_BAR_CONFIG_NDT0_ADDR , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR ); +REG64_FLD( PU_NPU1_SM0_NDT_BAR_CONFIG_NDT0_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT0_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM0_NDT_BAR_NDT0_RESERVED2 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2 ); +REG64_FLD( PU_NPU1_SM0_NDT_BAR_NDT0_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_NDT0_RESERVED2_LEN ); +REG64_FLD( PU_NPU1_SM0_NDT_BAR_CONFIG_NDT1_ENABLE , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ENABLE ); +REG64_FLD( PU_NPU1_SM0_NDT_BAR_NDT1_RESERVED1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED1 ); +REG64_FLD( PU_NPU1_SM0_NDT_BAR_CONFIG_NDT1_ADDR , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR ); +REG64_FLD( PU_NPU1_SM0_NDT_BAR_CONFIG_NDT1_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CONFIG_NDT1_ADDR_LEN ); +REG64_FLD( PU_NPU1_SM0_NDT_BAR_NDT1_RESERVED2 , 59 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2 ); +REG64_FLD( PU_NPU1_SM0_NDT_BAR_NDT1_RESERVED2_LEN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_NDT1_RESERVED2_LEN ); REG64_FLD( PHB_NFIRACTION0_REG_NFIRACTION0 , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_NFIRACTION0 ); REG64_FLD( PHB_NFIRACTION0_REG_NFIRACTION0_LEN , 30 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_NFIRACTION0_LEN ); -REG64_FLD( PEC_STACK0_NFIRACTION0_REG_NFIRACTION0 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , - SH_FLD_NFIRACTION0 ); -REG64_FLD( PEC_STACK0_NFIRACTION0_REG_NFIRACTION0_LEN , 30 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , - SH_FLD_NFIRACTION0_LEN ); - -REG64_FLD( PEC_STACK2_NFIRACTION1_REG_NFIRACTION1 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , - SH_FLD_NFIRACTION1 ); -REG64_FLD( PEC_STACK2_NFIRACTION1_REG_NFIRACTION1_LEN , 30 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , - SH_FLD_NFIRACTION1_LEN ); - -REG64_FLD( PEC_STACK1_NFIRACTION1_REG_NFIRACTION1 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , - SH_FLD_NFIRACTION1 ); -REG64_FLD( PEC_STACK1_NFIRACTION1_REG_NFIRACTION1_LEN , 30 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , - SH_FLD_NFIRACTION1_LEN ); - REG64_FLD( PHB_NFIRACTION1_REG_NFIRACTION1 , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_NFIRACTION1 ); REG64_FLD( PHB_NFIRACTION1_REG_NFIRACTION1_LEN , 30 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_NFIRACTION1_LEN ); -REG64_FLD( PEC_STACK0_NFIRACTION1_REG_NFIRACTION1 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , - SH_FLD_NFIRACTION1 ); -REG64_FLD( PEC_STACK0_NFIRACTION1_REG_NFIRACTION1_LEN , 30 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , - SH_FLD_NFIRACTION1_LEN ); - -REG64_FLD( PEC_STACK2_NFIRMASK_REG_BAR_PE_MASK , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_BAR_PE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_NONBAR_PE_MASK , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_NONBAR_PE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_TO_PEC_CE_MASK , 2 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_CE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_TO_PEC_UE_MASK , 3 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_UE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_TO_PEC_SUE_MASK , 4 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_SUE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_ARY_ECC_CE_MASK , 5 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_CE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_ARY_ECC_UE_MASK , 6 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_UE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_ARY_ECC_SUE_MASK , 7 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_SUE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_REGISTER_ARRAY_PE_MASK , 8 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_REGISTER_ARRAY_PE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_INTERFACE_PE_MASK , 9 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_INTERFACE_PE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_DATA_HANG_ERRORS_MASK , 10 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_DATA_HANG_ERRORS_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PB_HANG_ERRORS_MASK , 11 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_HANG_ERRORS_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_RD_ARE_ERRORS_MASK , 12 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_RD_ARE_ERRORS_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_NONRD_ARE_ERRORS_MASK , 13 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_NONRD_ARE_ERRORS_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PCI_HANG_ERROR_MASK , 14 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PCI_HANG_ERROR_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PCI_CLOCK_ERROR_MASK , 15 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PCI_CLOCK_ERROR_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_AIB_FENCE_MASK , 16 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_AIB_FENCE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_HW_ERRORS_MASK , 17 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_HW_ERRORS_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_UNSOLICITIEDPBDATA_MASK , 18 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_UNSOLICITIEDPBDATA_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_UNEXPECTEDCRESP_MASK , 19 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_UNEXPECTEDCRESP_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_INVALIDCRESP_MASK , 20 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_INVALIDCRESP_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PBUNSUPPORTEDSIZE_MASK , 21 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDSIZE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PBUNSUPPORTEDCMD_MASK , 22 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDCMD_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_AIB_PE_MASK , 23 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_AIB_PE_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_CAPP_ERROR_MASK , 24 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_CAPP_ERROR_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_PEC_SCOM_ERR_MASK , 27 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PEC_SCOM_ERR_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_STACK_SCOM_ERR0_MASK , 28 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR0_MASK ); -REG64_FLD( PEC_STACK2_NFIRMASK_REG_STACK_SCOM_ERR1_MASK , 29 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR1_MASK ); - -REG64_FLD( PEC_STACK1_NFIRMASK_REG_BAR_PE_MASK , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_BAR_PE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_NONBAR_PE_MASK , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_NONBAR_PE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_TO_PEC_CE_MASK , 2 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_CE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_TO_PEC_UE_MASK , 3 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_UE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_TO_PEC_SUE_MASK , 4 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_SUE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_ARY_ECC_CE_MASK , 5 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_CE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_ARY_ECC_UE_MASK , 6 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_UE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_ARY_ECC_SUE_MASK , 7 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_SUE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_REGISTER_ARRAY_PE_MASK , 8 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_REGISTER_ARRAY_PE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_INTERFACE_PE_MASK , 9 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_INTERFACE_PE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_DATA_HANG_ERRORS_MASK , 10 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_DATA_HANG_ERRORS_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PB_HANG_ERRORS_MASK , 11 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_HANG_ERRORS_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_RD_ARE_ERRORS_MASK , 12 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_RD_ARE_ERRORS_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_NONRD_ARE_ERRORS_MASK , 13 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_NONRD_ARE_ERRORS_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PCI_HANG_ERROR_MASK , 14 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PCI_HANG_ERROR_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PCI_CLOCK_ERROR_MASK , 15 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PCI_CLOCK_ERROR_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_AIB_FENCE_MASK , 16 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_AIB_FENCE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_HW_ERRORS_MASK , 17 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_HW_ERRORS_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_UNSOLICITIEDPBDATA_MASK , 18 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_UNSOLICITIEDPBDATA_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_UNEXPECTEDCRESP_MASK , 19 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_UNEXPECTEDCRESP_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_INVALIDCRESP_MASK , 20 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_INVALIDCRESP_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PBUNSUPPORTEDSIZE_MASK , 21 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDSIZE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PBUNSUPPORTEDCMD_MASK , 22 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDCMD_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_AIB_PE_MASK , 23 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_AIB_PE_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_CAPP_ERROR_MASK , 24 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_CAPP_ERROR_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_PEC_SCOM_ERR_MASK , 27 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PEC_SCOM_ERR_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_STACK_SCOM_ERR0_MASK , 28 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR0_MASK ); -REG64_FLD( PEC_STACK1_NFIRMASK_REG_STACK_SCOM_ERR1_MASK , 29 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR1_MASK ); - REG64_FLD( PHB_NFIRMASK_REG_BAR_PE_MASK , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_BAR_PE_MASK ); REG64_FLD( PHB_NFIRMASK_REG_NONBAR_PE_MASK , 1 , SH_UNT_PHB , SH_ACS_SCOM2_OR , @@ -40538,177 +51314,6 @@ REG64_FLD( PHB_NFIRMASK_REG_STACK_SCOM_ERR0_MASK , 28 , SH_UN REG64_FLD( PHB_NFIRMASK_REG_STACK_SCOM_ERR1_MASK , 29 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR1_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_BAR_PE_MASK , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_BAR_PE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_NONBAR_PE_MASK , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_NONBAR_PE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_TO_PEC_CE_MASK , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_CE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_TO_PEC_UE_MASK , 3 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_UE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_TO_PEC_SUE_MASK , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_SUE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_ARY_ECC_CE_MASK , 5 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_CE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_ARY_ECC_UE_MASK , 6 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_UE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_ARY_ECC_SUE_MASK , 7 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_SUE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_REGISTER_ARRAY_PE_MASK , 8 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_REGISTER_ARRAY_PE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_INTERFACE_PE_MASK , 9 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_INTERFACE_PE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_DATA_HANG_ERRORS_MASK , 10 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_DATA_HANG_ERRORS_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PB_HANG_ERRORS_MASK , 11 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_HANG_ERRORS_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_RD_ARE_ERRORS_MASK , 12 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_RD_ARE_ERRORS_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_NONRD_ARE_ERRORS_MASK , 13 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_NONRD_ARE_ERRORS_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PCI_HANG_ERROR_MASK , 14 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PCI_HANG_ERROR_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PCI_CLOCK_ERROR_MASK , 15 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PCI_CLOCK_ERROR_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_AIB_FENCE_MASK , 16 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_AIB_FENCE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_HW_ERRORS_MASK , 17 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_HW_ERRORS_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_UNSOLICITIEDPBDATA_MASK , 18 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_UNSOLICITIEDPBDATA_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_UNEXPECTEDCRESP_MASK , 19 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_UNEXPECTEDCRESP_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_INVALIDCRESP_MASK , 20 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_INVALIDCRESP_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PBUNSUPPORTEDSIZE_MASK , 21 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDSIZE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PBUNSUPPORTEDCMD_MASK , 22 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDCMD_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_AIB_PE_MASK , 23 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_AIB_PE_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_CAPP_ERROR_MASK , 24 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_CAPP_ERROR_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_PEC_SCOM_ERR_MASK , 27 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PEC_SCOM_ERR_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_STACK_SCOM_ERR0_MASK , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR0_MASK ); -REG64_FLD( PEC_STACK0_NFIRMASK_REG_STACK_SCOM_ERR1_MASK , 29 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR1_MASK ); - -REG64_FLD( PEC_STACK2_NFIR_REG_BAR_PE , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_BAR_PE ); -REG64_FLD( PEC_STACK2_NFIR_REG_NONBAR_PE , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_NONBAR_PE ); -REG64_FLD( PEC_STACK2_NFIR_REG_PB_TO_PEC_CE , 2 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_CE ); -REG64_FLD( PEC_STACK2_NFIR_REG_PB_TO_PEC_UE , 3 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_UE ); -REG64_FLD( PEC_STACK2_NFIR_REG_PB_TO_PEC_SUE , 4 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_SUE ); -REG64_FLD( PEC_STACK2_NFIR_REG_ARY_ECC_CE , 5 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_CE ); -REG64_FLD( PEC_STACK2_NFIR_REG_ARY_ECC_UE , 6 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_UE ); -REG64_FLD( PEC_STACK2_NFIR_REG_ARY_ECC_SUE , 7 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_SUE ); -REG64_FLD( PEC_STACK2_NFIR_REG_REGISTER_ARRAY_PE , 8 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_REGISTER_ARRAY_PE ); -REG64_FLD( PEC_STACK2_NFIR_REG_PB_INTERFACE_PE , 9 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_INTERFACE_PE ); -REG64_FLD( PEC_STACK2_NFIR_REG_PB_DATA_HANG_ERRORS , 10 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_DATA_HANG_ERRORS ); -REG64_FLD( PEC_STACK2_NFIR_REG_PB_HANG_ERRORS , 11 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PB_HANG_ERRORS ); -REG64_FLD( PEC_STACK2_NFIR_REG_RD_ARE_ERRORS , 12 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_RD_ARE_ERRORS ); -REG64_FLD( PEC_STACK2_NFIR_REG_NONRD_ARE_ERRORS , 13 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_NONRD_ARE_ERRORS ); -REG64_FLD( PEC_STACK2_NFIR_REG_PCI_HANG_ERROR , 14 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PCI_HANG_ERROR ); -REG64_FLD( PEC_STACK2_NFIR_REG_PCI_CLOCK_ERROR , 15 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PCI_CLOCK_ERROR ); -REG64_FLD( PEC_STACK2_NFIR_REG_AIB_FENCE , 16 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_AIB_FENCE ); -REG64_FLD( PEC_STACK2_NFIR_REG_HW_ERRORS , 17 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_HW_ERRORS ); -REG64_FLD( PEC_STACK2_NFIR_REG_UNSOLICITIEDPBDATA , 18 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_UNSOLICITIEDPBDATA ); -REG64_FLD( PEC_STACK2_NFIR_REG_UNEXPECTEDCRESP , 19 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_UNEXPECTEDCRESP ); -REG64_FLD( PEC_STACK2_NFIR_REG_INVALIDCRESP , 20 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_INVALIDCRESP ); -REG64_FLD( PEC_STACK2_NFIR_REG_PBUNSUPPORTEDSIZE , 21 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDSIZE ); -REG64_FLD( PEC_STACK2_NFIR_REG_PBUNSUPPORTEDCMD , 22 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDCMD ); -REG64_FLD( PEC_STACK2_NFIR_REG_AIB_PE , 23 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_AIB_PE ); -REG64_FLD( PEC_STACK2_NFIR_REG_CAPP_ERROR , 24 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_CAPP_ERROR ); -REG64_FLD( PEC_STACK2_NFIR_REG_PEC_SCOM_ERR , 27 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_PEC_SCOM_ERR ); -REG64_FLD( PEC_STACK2_NFIR_REG_STACK_SCOM_ERR0 , 28 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR0 ); -REG64_FLD( PEC_STACK2_NFIR_REG_STACK_SCOM_ERR1 , 29 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR1 ); - -REG64_FLD( PEC_STACK1_NFIR_REG_BAR_PE , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_BAR_PE ); -REG64_FLD( PEC_STACK1_NFIR_REG_NONBAR_PE , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_NONBAR_PE ); -REG64_FLD( PEC_STACK1_NFIR_REG_PB_TO_PEC_CE , 2 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_CE ); -REG64_FLD( PEC_STACK1_NFIR_REG_PB_TO_PEC_UE , 3 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_UE ); -REG64_FLD( PEC_STACK1_NFIR_REG_PB_TO_PEC_SUE , 4 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_SUE ); -REG64_FLD( PEC_STACK1_NFIR_REG_ARY_ECC_CE , 5 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_CE ); -REG64_FLD( PEC_STACK1_NFIR_REG_ARY_ECC_UE , 6 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_UE ); -REG64_FLD( PEC_STACK1_NFIR_REG_ARY_ECC_SUE , 7 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_SUE ); -REG64_FLD( PEC_STACK1_NFIR_REG_REGISTER_ARRAY_PE , 8 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_REGISTER_ARRAY_PE ); -REG64_FLD( PEC_STACK1_NFIR_REG_PB_INTERFACE_PE , 9 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_INTERFACE_PE ); -REG64_FLD( PEC_STACK1_NFIR_REG_PB_DATA_HANG_ERRORS , 10 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_DATA_HANG_ERRORS ); -REG64_FLD( PEC_STACK1_NFIR_REG_PB_HANG_ERRORS , 11 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PB_HANG_ERRORS ); -REG64_FLD( PEC_STACK1_NFIR_REG_RD_ARE_ERRORS , 12 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_RD_ARE_ERRORS ); -REG64_FLD( PEC_STACK1_NFIR_REG_NONRD_ARE_ERRORS , 13 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_NONRD_ARE_ERRORS ); -REG64_FLD( PEC_STACK1_NFIR_REG_PCI_HANG_ERROR , 14 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PCI_HANG_ERROR ); -REG64_FLD( PEC_STACK1_NFIR_REG_PCI_CLOCK_ERROR , 15 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PCI_CLOCK_ERROR ); -REG64_FLD( PEC_STACK1_NFIR_REG_AIB_FENCE , 16 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_AIB_FENCE ); -REG64_FLD( PEC_STACK1_NFIR_REG_HW_ERRORS , 17 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_HW_ERRORS ); -REG64_FLD( PEC_STACK1_NFIR_REG_UNSOLICITIEDPBDATA , 18 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_UNSOLICITIEDPBDATA ); -REG64_FLD( PEC_STACK1_NFIR_REG_UNEXPECTEDCRESP , 19 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_UNEXPECTEDCRESP ); -REG64_FLD( PEC_STACK1_NFIR_REG_INVALIDCRESP , 20 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_INVALIDCRESP ); -REG64_FLD( PEC_STACK1_NFIR_REG_PBUNSUPPORTEDSIZE , 21 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDSIZE ); -REG64_FLD( PEC_STACK1_NFIR_REG_PBUNSUPPORTEDCMD , 22 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDCMD ); -REG64_FLD( PEC_STACK1_NFIR_REG_AIB_PE , 23 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_AIB_PE ); -REG64_FLD( PEC_STACK1_NFIR_REG_CAPP_ERROR , 24 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_CAPP_ERROR ); -REG64_FLD( PEC_STACK1_NFIR_REG_PEC_SCOM_ERR , 27 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_PEC_SCOM_ERR ); -REG64_FLD( PEC_STACK1_NFIR_REG_STACK_SCOM_ERR0 , 28 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR0 ); -REG64_FLD( PEC_STACK1_NFIR_REG_STACK_SCOM_ERR1 , 29 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR1 ); - REG64_FLD( PHB_NFIR_REG_BAR_PE , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_BAR_PE ); REG64_FLD( PHB_NFIR_REG_NONBAR_PE , 1 , SH_UNT_PHB , SH_ACS_SCOM2_OR , @@ -40766,63 +51371,6 @@ REG64_FLD( PHB_NFIR_REG_STACK_SCOM_ERR0 , 28 , SH_UN REG64_FLD( PHB_NFIR_REG_STACK_SCOM_ERR1 , 29 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_STACK_SCOM_ERR1 ); -REG64_FLD( PEC_STACK0_NFIR_REG_BAR_PE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_BAR_PE ); -REG64_FLD( PEC_STACK0_NFIR_REG_NONBAR_PE , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_NONBAR_PE ); -REG64_FLD( PEC_STACK0_NFIR_REG_PB_TO_PEC_CE , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_CE ); -REG64_FLD( PEC_STACK0_NFIR_REG_PB_TO_PEC_UE , 3 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_UE ); -REG64_FLD( PEC_STACK0_NFIR_REG_PB_TO_PEC_SUE , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_TO_PEC_SUE ); -REG64_FLD( PEC_STACK0_NFIR_REG_ARY_ECC_CE , 5 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_CE ); -REG64_FLD( PEC_STACK0_NFIR_REG_ARY_ECC_UE , 6 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_UE ); -REG64_FLD( PEC_STACK0_NFIR_REG_ARY_ECC_SUE , 7 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_ARY_ECC_SUE ); -REG64_FLD( PEC_STACK0_NFIR_REG_REGISTER_ARRAY_PE , 8 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_REGISTER_ARRAY_PE ); -REG64_FLD( PEC_STACK0_NFIR_REG_PB_INTERFACE_PE , 9 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_INTERFACE_PE ); -REG64_FLD( PEC_STACK0_NFIR_REG_PB_DATA_HANG_ERRORS , 10 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_DATA_HANG_ERRORS ); -REG64_FLD( PEC_STACK0_NFIR_REG_PB_HANG_ERRORS , 11 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PB_HANG_ERRORS ); -REG64_FLD( PEC_STACK0_NFIR_REG_RD_ARE_ERRORS , 12 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_RD_ARE_ERRORS ); -REG64_FLD( PEC_STACK0_NFIR_REG_NONRD_ARE_ERRORS , 13 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_NONRD_ARE_ERRORS ); -REG64_FLD( PEC_STACK0_NFIR_REG_PCI_HANG_ERROR , 14 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PCI_HANG_ERROR ); -REG64_FLD( PEC_STACK0_NFIR_REG_PCI_CLOCK_ERROR , 15 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PCI_CLOCK_ERROR ); -REG64_FLD( PEC_STACK0_NFIR_REG_AIB_FENCE , 16 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_AIB_FENCE ); -REG64_FLD( PEC_STACK0_NFIR_REG_HW_ERRORS , 17 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_HW_ERRORS ); -REG64_FLD( PEC_STACK0_NFIR_REG_UNSOLICITIEDPBDATA , 18 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_UNSOLICITIEDPBDATA ); -REG64_FLD( PEC_STACK0_NFIR_REG_UNEXPECTEDCRESP , 19 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_UNEXPECTEDCRESP ); -REG64_FLD( PEC_STACK0_NFIR_REG_INVALIDCRESP , 20 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_INVALIDCRESP ); -REG64_FLD( PEC_STACK0_NFIR_REG_PBUNSUPPORTEDSIZE , 21 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDSIZE ); -REG64_FLD( PEC_STACK0_NFIR_REG_PBUNSUPPORTEDCMD , 22 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PBUNSUPPORTEDCMD ); -REG64_FLD( PEC_STACK0_NFIR_REG_AIB_PE , 23 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_AIB_PE ); -REG64_FLD( PEC_STACK0_NFIR_REG_CAPP_ERROR , 24 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_CAPP_ERROR ); -REG64_FLD( PEC_STACK0_NFIR_REG_PEC_SCOM_ERR , 27 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_PEC_SCOM_ERR ); -REG64_FLD( PEC_STACK0_NFIR_REG_STACK_SCOM_ERR0 , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR0 ); -REG64_FLD( PEC_STACK0_NFIR_REG_STACK_SCOM_ERR1 , 29 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , - SH_FLD_STACK_SCOM_ERR1 ); - REG64_FLD( PU_NOTRUST_BAR0_UNTRUSTED , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNTRUSTED ); REG64_FLD( PU_NOTRUST_BAR0_UNTRUSTED_LEN , 30 , SH_UNT , SH_ACS_SCOM , @@ -40916,78 +51464,68 @@ REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT3 , 48 , SH_UN REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT3_LEN , 16 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO , SH_FLD_CNT3_LEN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT0_EN , 0 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT0_EN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT1_EN , 1 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT1_EN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT2_EN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT2_EN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT3_EN , 3 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT3_EN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PRESCALER_SELECT , 4 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_PRESCALER_SELECT ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PRESCALER_SELECT_LEN , 3 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_PRESCALER_SELECT_LEN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT0_POS_EDGE_SELECT , 7 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT0_POS_EDGE_SELECT ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT1_POS_EDGE_SELECT , 8 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT1_POS_EDGE_SELECT ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT2_POS_EDGE_SELECT , 9 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT2_POS_EDGE_SELECT ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT3_POS_EDGE_SELECT , 10 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT3_POS_EDGE_SELECT ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_RESET , 11 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_RESET ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT0_EVENT_SELECT , 12 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT0_EVENT_SELECT ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT0_EVENT_SELECT_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT0_EVENT_SELECT_LEN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT0_BIT_PAIR_SELECT , 14 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT0_BIT_PAIR_SELECT ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT0_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT0_BIT_PAIR_SELECT_LEN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT1_EVENT_SELECT , 16 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT1_EVENT_SELECT ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT1_EVENT_SELECT_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT1_EVENT_SELECT_LEN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT1_BIT_PAIR_SELECT , 18 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT1_BIT_PAIR_SELECT ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT1_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT1_BIT_PAIR_SELECT_LEN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT2_EVENT_SELECT , 20 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT2_EVENT_SELECT ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT2_EVENT_SELECT_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT2_EVENT_SELECT_LEN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT2_BIT_PAIR_SELECT , 22 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT2_BIT_PAIR_SELECT ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT2_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT2_BIT_PAIR_SELECT_LEN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT3_EVENT_SELECT , 24 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT3_EVENT_SELECT ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT3_EVENT_SELECT_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT3_EVENT_SELECT_LEN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT3_BIT_PAIR_SELECT , 26 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT3_BIT_PAIR_SELECT ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CNT3_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_CNT3_BIT_PAIR_SELECT_LEN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_GROUP_SELECT , 28 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_GROUP_SELECT ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_GROUP_SELECT_LEN , 3 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_GROUP_SELECT_LEN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_FREEZE , 31 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_FREEZE ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PE_MASK0 , 32 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_PE_MASK0 ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PE_MATCH0 , 33 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_PE_MATCH0 ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PE_MATCH0_LEN , 4 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_PE_MATCH0_LEN ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PE_MASK1 , 37 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_PE_MASK1 ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PE_MATCH1 , 38 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_PE_MATCH1 ); -REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PE_MATCH1_LEN , 4 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , - SH_FLD_PE_MATCH1_LEN ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_ENABLE ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_RESETMODE , 1 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_RESETMODE ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_FREEZEMODE , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_FREEZEMODE ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_DISABLE_PMISC , 3 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_DISABLE_PMISC ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PMISC_MODE , 4 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_PMISC_MODE ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_CASCADE , 5 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_CASCADE ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_CASCADE_LEN , 3 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_CASCADE_LEN ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C0 , 8 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_PRESCALE_C0 ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C0_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_PRESCALE_C0_LEN ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C1 , 10 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_PRESCALE_C1 ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C1_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_PRESCALE_C1_LEN ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C2 , 12 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_PRESCALE_C2 ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C2_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_PRESCALE_C2_LEN ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C3 , 14 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_PRESCALE_C3 ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C3_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_PRESCALE_C3_LEN ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C0 , 16 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_OPERATION_C0 ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C0_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_OPERATION_C0_LEN ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C1 , 18 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_OPERATION_C1 ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C1_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_OPERATION_C1_LEN ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C2 , 20 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_OPERATION_C2 ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C2_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_OPERATION_C2_LEN ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C3 , 22 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_OPERATION_C3 ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C3_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_OPERATION_C3_LEN ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_EVENTS , 24 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_EVENTS ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_EVENTS_LEN , 3 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_EVENTS_LEN ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH0 , 27 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_CFG_PE_MATCH0 ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH0_LEN , 5 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_CFG_PE_MATCH0_LEN ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH1 , 32 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_CFG_PE_MATCH1 ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH1_LEN , 5 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_CFG_PE_MATCH1_LEN ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_SPARE , 37 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_SPARE ); +REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_SPARE_LEN , 5 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , + SH_FLD_PERF_CONFIG_SPARE_LEN ); REG64_FLD( PU_NPU_SM1_NPU_Q_DMA_R_QUIESCE , 0 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_QUIESCE ); @@ -40998,6 +51536,23 @@ REG64_FLD( PU_NPU_SM1_NPU_Q_DMA_R_RESPONSE , 4 , SH_UN REG64_FLD( PU_NPU_SM1_NPU_Q_DMA_R_TCE_RESPONSE , 6 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_TCE_RESPONSE ); +REG64_FLD( PU_NPU_CTL_NPU_VERSION_RSVD0 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_RSVD0 ); +REG64_FLD( PU_NPU_CTL_NPU_VERSION_RSVD0_LEN , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_RSVD0_LEN ); +REG64_FLD( PU_NPU_CTL_NPU_VERSION_MAJOR , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MAJOR ); +REG64_FLD( PU_NPU_CTL_NPU_VERSION_MAJOR_LEN , 8 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MAJOR_LEN ); +REG64_FLD( PU_NPU_CTL_NPU_VERSION_RSVD1 , 32 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_RSVD1 ); +REG64_FLD( PU_NPU_CTL_NPU_VERSION_RSVD1_LEN , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_RSVD1_LEN ); +REG64_FLD( PU_NPU_CTL_NPU_VERSION_MINOR , 48 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MINOR ); +REG64_FLD( PU_NPU_CTL_NPU_VERSION_MINOR_LEN , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , + SH_FLD_MINOR_LEN ); + REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_LN , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_WR_DISABLE_LN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_GROUP , 1 , SH_UNT , SH_ACS_SCOM , @@ -41379,13 +51934,6 @@ REG64_FLD( PU_NX_DMA_ENG_FIR_WOF_BITS , 0 , SH_UN REG64_FLD( PU_NX_DMA_ENG_FIR_WOF_BITS_LEN , 50 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_BITS_LEN ); -REG64_FLD( PU_NMMU_NX_EPSILON_COUNTER_VALUE_NXWR_CFG , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , - SH_FLD_NXWR_CFG ); -REG64_FLD( PU_NMMU_NX_EPSILON_COUNTER_VALUE_NXWR_CFG_LEN , 6 , SH_UNT_PU_NMMU , SH_ACS_SCOM , - SH_FLD_NXWR_CFG_LEN ); -REG64_FLD( PU_NMMU_NX_EPSILON_COUNTER_VALUE_NXWR_DISABLE_CP , 6 , SH_UNT_PU_NMMU , SH_ACS_SCOM , - SH_FLD_NXWR_DISABLE_CP ); - REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_ENA , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH0EFT_ENA ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_TYPE , 3 , SH_UNT , SH_ACS_SCOM_RW , @@ -41456,11 +52004,11 @@ REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_SELECT , 51 , SH_UN SH_FLD_CH4GZIP_SELECT ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_SELECT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH4GZIP_SELECT_LEN ); +REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_QW0_UEINJ_ENA , 59 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DMA_OUTWR_QW0_UEINJ_ENA ); +REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_QW4_UEINJ_ENA , 60 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_DMA_OUTWR_QW4_UEINJ_ENA ); -REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_INTERRUPT_ENABLE , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , - SH_FLD_INTERRUPT_ENABLE ); -REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_AS_INTERRUPT_ENABLE , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM , - SH_FLD_AS_INTERRUPT_ENABLE ); REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HANG_POLL_SCALE ); REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , @@ -41474,10 +52022,6 @@ REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE , 12 , SH_UN REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HANG_SHM_SCALE_LEN ); -REG64_FLD( PU_NX_MISC_CONTROL_REG_INTERRUPT_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , - SH_FLD_INTERRUPT_ENABLE ); -REG64_FLD( PU_NX_MISC_CONTROL_REG_AS_INTERRUPT_ENABLE , 1 , SH_UNT , SH_ACS_SCOM , - SH_FLD_AS_INTERRUPT_ENABLE ); REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_HANG_POLL_SCALE ); REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE_LEN , 4 , SH_UNT , SH_ACS_SCOM , @@ -41490,6 +52034,10 @@ REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE , 12 , SH_UN SH_FLD_HANG_SHM_SCALE ); REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_HANG_SHM_SCALE_LEN ); +REG64_FLD( PU_NX_MISC_CONTROL_REG_ERAT_DATA_POLL_SCALE , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERAT_DATA_POLL_SCALE ); +REG64_FLD( PU_NX_MISC_CONTROL_REG_ERAT_DATA_POLL_SCALE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ERAT_DATA_POLL_SCALE_LEN ); REG64_FLD( PU_NX_MMIO_BAR_BAR , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR ); @@ -42763,13 +53311,17 @@ REG64_FLD( PU_OCB_OCI_OCCMISC_PVREF_ERROR_GROSS , 6 , SH_UN SH_FLD_PVREF_ERROR_GROSS ); REG64_FLD( PU_OCB_OCI_OCCMISC_PVREF_ERROR_FINE , 7 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PVREF_ERROR_FINE ); -REG64_FLD( PU_OCB_OCI_OCCMISC_SPARE , 8 , SH_UNT , SH_ACS_SCOM2 , +REG64_FLD( PU_OCB_OCI_OCCMISC_FIRMWARE_FAULT , 8 , SH_UNT , SH_ACS_SCOM2 , + SH_FLD_FIRMWARE_FAULT ); +REG64_FLD( PU_OCB_OCI_OCCMISC_FIRMWARE_NOTIFY , 9 , SH_UNT , SH_ACS_SCOM2 , + SH_FLD_FIRMWARE_NOTIFY ); +REG64_FLD( PU_OCB_OCI_OCCMISC_SPARE , 10 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_SPARE ); -REG64_FLD( PU_OCB_OCI_OCCMISC_SPARE_LEN , 8 , SH_UNT , SH_ACS_SCOM2 , +REG64_FLD( PU_OCB_OCI_OCCMISC_SPARE_LEN , 6 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_SPARE_LEN ); REG64_FLD( PU_OCB_OCI_OCCMISC_I2CM_INTR_STATUS , 16 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_I2CM_INTR_STATUS ); -REG64_FLD( PU_OCB_OCI_OCCMISC_I2CM_INTR_STATUS_LEN , 4 , SH_UNT , SH_ACS_SCOM2 , +REG64_FLD( PU_OCB_OCI_OCCMISC_I2CM_INTR_STATUS_LEN , 3 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_I2CM_INTR_STATUS_LEN ); REG64_FLD( PU_OCB_OCI_OCCS0_OCC_SCRATCH_N , 0 , SH_UNT , SH_ACS_SCOM_RW , @@ -42865,6 +53417,10 @@ REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_EN , 8 , SH_UN SH_FLD_EVENT2HALT_EN ); REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_EN_LEN , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENT2HALT_EN_LEN ); +REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_GPE_SRC_SEL , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_HTM_GPE_SRC_SEL ); +REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_GPE_SRC_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_HTM_GPE_SRC_SEL_LEN ); REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_OCC , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENT2HALT_OCC ); REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE0 , 24 , SH_UNT , SH_ACS_SCOM , @@ -44138,23 +54694,35 @@ REG64_FLD( PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_4 , 4 , SH_UN REG64_FLD( PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_5 , 5 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 ); -REG64_FLD( PU_OCB_OCI_OPIT7Q0_PCB_INTR_TYPE_A_QUAD_N , 31 , SH_UNT , SH_ACS_SCOM1_RO , +REG64_FLD( PU_OCB_OCI_OPIT7Q0_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); +REG64_FLD( PU_OCB_OCI_OPIT7Q0_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , + SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); -REG64_FLD( PU_OCB_OCI_OPIT7Q1_PCB_INTR_TYPE_A_QUAD_N , 31 , SH_UNT , SH_ACS_SCOM1_RO , +REG64_FLD( PU_OCB_OCI_OPIT7Q1_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); +REG64_FLD( PU_OCB_OCI_OPIT7Q1_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , + SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); -REG64_FLD( PU_OCB_OCI_OPIT7Q2_PCB_INTR_TYPE_A_QUAD_N , 31 , SH_UNT , SH_ACS_SCOM1_RO , +REG64_FLD( PU_OCB_OCI_OPIT7Q2_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); +REG64_FLD( PU_OCB_OCI_OPIT7Q2_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , + SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); -REG64_FLD( PU_OCB_OCI_OPIT7Q3_PCB_INTR_TYPE_A_QUAD_N , 31 , SH_UNT , SH_ACS_SCOM1_RO , +REG64_FLD( PU_OCB_OCI_OPIT7Q3_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); +REG64_FLD( PU_OCB_OCI_OPIT7Q3_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , + SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); -REG64_FLD( PU_OCB_OCI_OPIT7Q4_PCB_INTR_TYPE_A_QUAD_N , 31 , SH_UNT , SH_ACS_SCOM1_RO , +REG64_FLD( PU_OCB_OCI_OPIT7Q4_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); +REG64_FLD( PU_OCB_OCI_OPIT7Q4_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , + SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); -REG64_FLD( PU_OCB_OCI_OPIT7Q5_PCB_INTR_TYPE_A_QUAD_N , 31 , SH_UNT , SH_ACS_SCOM1_RO , +REG64_FLD( PU_OCB_OCI_OPIT7Q5_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); +REG64_FLD( PU_OCB_OCI_OPIT7Q5_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , + SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); REG64_FLD( PU_OCB_OCI_OTBR_TIMEBASE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TIMEBASE ); @@ -44400,24 +54968,24 @@ REG64_FLD( PU_OCB_PIB_OCBCSR3_FSM_ERR , 14 , SH_UN REG64_FLD( PU_OCB_PIB_OCBCSR3_SPARE2 , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE2 ); -REG64_FLD( PU_OCB_PIB_OCBDR0_DATA , 0 , SH_UNT , SH_ACS_SCOM_WO , +REG64_FLD( PU_OCB_PIB_OCBDR0_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA ); -REG64_FLD( PU_OCB_PIB_OCBDR0_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_WO , +REG64_FLD( PU_OCB_PIB_OCBDR0_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); -REG64_FLD( PU_OCB_PIB_OCBDR1_DATA , 0 , SH_UNT , SH_ACS_SCOM_WO , +REG64_FLD( PU_OCB_PIB_OCBDR1_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA ); -REG64_FLD( PU_OCB_PIB_OCBDR1_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_WO , +REG64_FLD( PU_OCB_PIB_OCBDR1_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); -REG64_FLD( PU_OCB_PIB_OCBDR2_DATA , 0 , SH_UNT , SH_ACS_SCOM_WO , +REG64_FLD( PU_OCB_PIB_OCBDR2_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA ); -REG64_FLD( PU_OCB_PIB_OCBDR2_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_WO , +REG64_FLD( PU_OCB_PIB_OCBDR2_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); -REG64_FLD( PU_OCB_PIB_OCBDR3_DATA , 0 , SH_UNT , SH_ACS_SCOM_WO , +REG64_FLD( PU_OCB_PIB_OCBDR3_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA ); -REG64_FLD( PU_OCB_PIB_OCBDR3_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_WO , +REG64_FLD( PU_OCB_PIB_OCBDR3_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( PU_OCB_PIB_OCBEAR_ERROR_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_WCLRPART, @@ -44629,6 +55197,319 @@ REG64_FLD( PU_OCB_PIB_OTDCR_OCI_TRACE_MUX_SEL , 4 , SH_UN REG64_FLD( PU_OCB_PIB_OTDCR_OCI_TRACE_MUX_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_TRACE_MUX_SEL_LEN ); +REG64_FLD( PEC_OPCG_ALIGN_INOP , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INOP ); +REG64_FLD( PEC_OPCG_ALIGN_INOP_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INOP_LEN ); +REG64_FLD( PEC_OPCG_ALIGN_SNOP , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SNOP ); +REG64_FLD( PEC_OPCG_ALIGN_SNOP_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SNOP_LEN ); +REG64_FLD( PEC_OPCG_ALIGN_ENOP , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ENOP ); +REG64_FLD( PEC_OPCG_ALIGN_ENOP_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ENOP_LEN ); +REG64_FLD( PEC_OPCG_ALIGN_INOP_WAIT , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INOP_WAIT ); +REG64_FLD( PEC_OPCG_ALIGN_INOP_WAIT_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INOP_WAIT_LEN ); +REG64_FLD( PEC_OPCG_ALIGN_SNOP_WAIT , 20 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SNOP_WAIT ); +REG64_FLD( PEC_OPCG_ALIGN_SNOP_WAIT_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SNOP_WAIT_LEN ); +REG64_FLD( PEC_OPCG_ALIGN_ENOP_WAIT , 32 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ENOP_WAIT ); +REG64_FLD( PEC_OPCG_ALIGN_ENOP_WAIT_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ENOP_WAIT_LEN ); +REG64_FLD( PEC_OPCG_ALIGN_INOP_FORCE_SG , 40 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INOP_FORCE_SG ); +REG64_FLD( PEC_OPCG_ALIGN_SNOP_FORCE_SG , 41 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SNOP_FORCE_SG ); +REG64_FLD( PEC_OPCG_ALIGN_ENOP_FORCE_SG , 42 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ENOP_FORCE_SG ); +REG64_FLD( PEC_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD , 43 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_NO_WAIT_ON_CLK_CMD ); +REG64_FLD( PEC_OPCG_ALIGN_SOURCE_SELECT , 44 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SOURCE_SELECT ); +REG64_FLD( PEC_OPCG_ALIGN_SOURCE_SELECT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SOURCE_SELECT_LEN ); +REG64_FLD( PEC_OPCG_ALIGN_UNUSED46 , 46 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED46 ); +REG64_FLD( PEC_OPCG_ALIGN_SCAN_RATIO , 47 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCAN_RATIO ); +REG64_FLD( PEC_OPCG_ALIGN_SCAN_RATIO_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCAN_RATIO_LEN ); +REG64_FLD( PEC_OPCG_ALIGN_WAIT_CYCLES , 52 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WAIT_CYCLES ); +REG64_FLD( PEC_OPCG_ALIGN_WAIT_CYCLES_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WAIT_CYCLES_LEN ); + +REG64_FLD( PEC_OPCG_CAPT1_COUNT , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COUNT ); +REG64_FLD( PEC_OPCG_CAPT1_COUNT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COUNT_LEN ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_01 , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_01 ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_01_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_01_LEN ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_02 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_02 ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_02_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_02_LEN ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_03 , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_03 ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_03_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_03_LEN ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_04 , 19 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_04 ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_04_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_04_LEN ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_05 , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_05 ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_05_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_05_LEN ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_06 , 29 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_06 ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_06_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_06_LEN ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_07 , 34 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_07 ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_07_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_07_LEN ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_08 , 39 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_08 ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_08_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_08_LEN ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_09 , 44 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_09 ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_09_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_09_LEN ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_10 , 49 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_10 ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_10_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_10_LEN ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_11 , 54 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_11 ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_11_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_11_LEN ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_12 , 59 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_12 ); +REG64_FLD( PEC_OPCG_CAPT1_SEQ_12_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_12_LEN ); + +REG64_FLD( PEC_OPCG_CAPT2_UNUSED , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PEC_OPCG_CAPT2_UNUSED_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_LEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_13_01EVEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_13_01EVEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_13_01EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_13_01EVEN_LEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_14_01ODD , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_14_01ODD ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_14_01ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_14_01ODD_LEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_15_02EVEN , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_15_02EVEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_15_02EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_15_02EVEN_LEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_16_02ODD , 19 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_16_02ODD ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_16_02ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_16_02ODD_LEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_17_03EVEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_17_03EVEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_17_03EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_17_03EVEN_LEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_18_03ODD , 29 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_18_03ODD ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_18_03ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_18_03ODD_LEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_19_04EVEN , 34 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_19_04EVEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_19_04EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_19_04EVEN_LEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_20_04ODD , 39 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_20_04ODD ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_20_04ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_20_04ODD_LEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_21_05EVEN , 44 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_21_05EVEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_21_05EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_21_05EVEN_LEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_22_05ODD , 49 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_22_05ODD ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_22_05ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_22_05ODD_LEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_23_06EVEN , 54 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_23_06EVEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_23_06EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_23_06EVEN_LEN ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_24_06ODD , 59 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_24_06ODD ); +REG64_FLD( PEC_OPCG_CAPT2_SEQ_24_06ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_24_06ODD_LEN ); + +REG64_FLD( PEC_OPCG_CAPT3_UNUSED , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PEC_OPCG_CAPT3_UNUSED_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED_LEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_07EVEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_07EVEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_07EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_07EVEN_LEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_07ODD , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_07ODD ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_07ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_07ODD_LEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_08EVEN , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_08EVEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_08EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_08EVEN_LEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_08ODD , 19 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_08ODD ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_08ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_08ODD_LEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_09EVEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_09EVEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_09EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_09EVEN_LEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_09ODD , 29 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_09ODD ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_09ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_09ODD_LEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_10EVEN , 34 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_10EVEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_10EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_10EVEN_LEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_10ODD , 39 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_10ODD ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_10ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_10ODD_LEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_11EVEN , 44 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_11EVEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_11EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_11EVEN_LEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_11ODD , 49 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_11ODD ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_11ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_11ODD_LEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_12EVEN , 54 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_12EVEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_12EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_12EVEN_LEN ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_12ODD , 59 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_12ODD ); +REG64_FLD( PEC_OPCG_CAPT3_SEQ_12ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SEQ_12ODD_LEN ); + +REG64_FLD( PEC_OPCG_REG0_RUNN_MODE , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RUNN_MODE ); +REG64_FLD( PEC_OPCG_REG0_GO , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GO ); +REG64_FLD( PEC_OPCG_REG0_RUN_SCAN0 , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RUN_SCAN0 ); +REG64_FLD( PEC_OPCG_REG0_SCAN0_MODE , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCAN0_MODE ); +REG64_FLD( PEC_OPCG_REG0_IN_SLAVE_MODE , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN_SLAVE_MODE ); +REG64_FLD( PEC_OPCG_REG0_IN_MASTER_MODE , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN_MASTER_MODE ); +REG64_FLD( PEC_OPCG_REG0_KEEP_MS_MODE , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_KEEP_MS_MODE ); +REG64_FLD( PEC_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL ); +REG64_FLD( PEC_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL ); +REG64_FLD( PEC_OPCG_REG0_RUN_CHIPLET_SCAN0 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RUN_CHIPLET_SCAN0 ); +REG64_FLD( PEC_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL ); +REG64_FLD( PEC_OPCG_REG0_RUN_ON_UPDATE_DR , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RUN_ON_UPDATE_DR ); +REG64_FLD( PEC_OPCG_REG0_RUN_ON_CAPTURE_DR , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RUN_ON_CAPTURE_DR ); +REG64_FLD( PEC_OPCG_REG0_STOP_RUNN_ON_XSTOP , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STOP_RUNN_ON_XSTOP ); +REG64_FLD( PEC_OPCG_REG0_STARTS_BIST , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STARTS_BIST ); +REG64_FLD( PEC_OPCG_REG0_UNUSED1520 , 15 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED1520 ); +REG64_FLD( PEC_OPCG_REG0_UNUSED1520_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED1520_LEN ); +REG64_FLD( PEC_OPCG_REG0_LOOP_COUNT , 21 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LOOP_COUNT ); +REG64_FLD( PEC_OPCG_REG0_LOOP_COUNT_LEN , 43 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LOOP_COUNT_LEN ); + +REG64_FLD( PEC_OPCG_REG1_SCAN_COUNT , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCAN_COUNT ); +REG64_FLD( PEC_OPCG_REG1_SCAN_COUNT_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCAN_COUNT_LEN ); +REG64_FLD( PEC_OPCG_REG1_MISR_A_VAL , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MISR_A_VAL ); +REG64_FLD( PEC_OPCG_REG1_MISR_A_VAL_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MISR_A_VAL_LEN ); +REG64_FLD( PEC_OPCG_REG1_MISR_B_VAL , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MISR_B_VAL ); +REG64_FLD( PEC_OPCG_REG1_MISR_B_VAL_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MISR_B_VAL_LEN ); +REG64_FLD( PEC_OPCG_REG1_MISR_INIT_WAIT , 36 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MISR_INIT_WAIT ); +REG64_FLD( PEC_OPCG_REG1_MISR_INIT_WAIT_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MISR_INIT_WAIT_LEN ); +REG64_FLD( PEC_OPCG_REG1_SUPPRESS_EVEN_CLK , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SUPPRESS_EVEN_CLK ); +REG64_FLD( PEC_OPCG_REG1_SCAN_CLK_USE_EVEN , 49 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCAN_CLK_USE_EVEN ); +REG64_FLD( PEC_OPCG_REG1_UNUSED2 , 50 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED2 ); +REG64_FLD( PEC_OPCG_REG1_UNUSED2_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED2_LEN ); +REG64_FLD( PEC_OPCG_REG1_RTIM_THOLD_FORCE , 52 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RTIM_THOLD_FORCE ); +REG64_FLD( PEC_OPCG_REG1_USE_ARY_CLK_DURING_FILL , 53 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_USE_ARY_CLK_DURING_FILL ); +REG64_FLD( PEC_OPCG_REG1_SG_HIGH_DURING_FILL , 54 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SG_HIGH_DURING_FILL ); +REG64_FLD( PEC_OPCG_REG1_LBIST_SKITTER_CTL , 55 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LBIST_SKITTER_CTL ); +REG64_FLD( PEC_OPCG_REG1_LBIST_SKITTER_CTL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LBIST_SKITTER_CTL_LEN ); +REG64_FLD( PEC_OPCG_REG1_MISR_MODE , 57 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MISR_MODE ); +REG64_FLD( PEC_OPCG_REG1_INFINITE_MODE , 58 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INFINITE_MODE ); +REG64_FLD( PEC_OPCG_REG1_NSL_FILL_COUNT , 59 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_NSL_FILL_COUNT ); +REG64_FLD( PEC_OPCG_REG1_NSL_FILL_COUNT_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_NSL_FILL_COUNT_LEN ); + +REG64_FLD( PEC_OPCG_REG2_GO2 , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GO2 ); +REG64_FLD( PEC_OPCG_REG2_PRPG_WEIGHTING , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRPG_WEIGHTING ); +REG64_FLD( PEC_OPCG_REG2_PRPG_WEIGHTING_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRPG_WEIGHTING_LEN ); +REG64_FLD( PEC_OPCG_REG2_PRPG_VALUE , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRPG_VALUE ); +REG64_FLD( PEC_OPCG_REG2_PRPG_VALUE_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRPG_VALUE_LEN ); +REG64_FLD( PEC_OPCG_REG2_PRPG_A_VAL , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRPG_A_VAL ); +REG64_FLD( PEC_OPCG_REG2_PRPG_A_VAL_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRPG_A_VAL_LEN ); +REG64_FLD( PEC_OPCG_REG2_PRPG_B_VAL , 28 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRPG_B_VAL ); +REG64_FLD( PEC_OPCG_REG2_PRPG_B_VAL_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRPG_B_VAL_LEN ); +REG64_FLD( PEC_OPCG_REG2_PRPG_MODE , 40 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PRPG_MODE ); +REG64_FLD( PEC_OPCG_REG2_UNUSED41_63 , 41 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED41_63 ); +REG64_FLD( PEC_OPCG_REG2_UNUSED41_63_LEN , 23 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED41_63_LEN ); + REG64_FLD( PU_NPU_CTL_OPTICAL_IO_CONFIG_NDLMUX_BRK0TO2 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_NDLMUX_BRK0TO2 ); REG64_FLD( PU_NPU_CTL_OPTICAL_IO_CONFIG_NDLMUX_BRK0TO2_LEN , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , @@ -45934,26 +56815,11 @@ REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_MC_PREFETCH , 62 , SH_UN REG64_FLD( PEC_PBCQHWCFG_REG_PE_IGNORE_SFSTAT , 63 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_IGNORE_SFSTAT ); -REG64_FLD( PEC_STACK2_PBCQMODE_REG_PE_PEER2PEER_MODDE , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , - SH_FLD_PE_PEER2PEER_MODDE ); -REG64_FLD( PEC_STACK2_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , - SH_FLD_PE_ENHANCED_PEER2PEER_MODDE ); - -REG64_FLD( PEC_STACK1_PBCQMODE_REG_PE_PEER2PEER_MODDE , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , - SH_FLD_PE_PEER2PEER_MODDE ); -REG64_FLD( PEC_STACK1_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , - SH_FLD_PE_ENHANCED_PEER2PEER_MODDE ); - REG64_FLD( PHB_PBCQMODE_REG_PE_PEER2PEER_MODDE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_PEER2PEER_MODDE ); REG64_FLD( PHB_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE , 1 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_ENHANCED_PEER2PEER_MODDE ); -REG64_FLD( PEC_STACK0_PBCQMODE_REG_PE_PEER2PEER_MODDE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , - SH_FLD_PE_PEER2PEER_MODDE ); -REG64_FLD( PEC_STACK0_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , - SH_FLD_PE_ENHANCED_PEER2PEER_MODDE ); - REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_VALID , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MB_VALID ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_WR_NOT_RD , 1 , SH_UNT , SH_ACS_SCOM , @@ -46008,6 +56874,238 @@ REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_SPARE , 12 , SH_UN REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_SPARE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_SPARE_LEN ); +REG64_FLD( _SM0_PB_CENT_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT__SM0 , SH_ACS_SCOM_RW , + SH_FLD_ACTION0 ); +REG64_FLD( _SM0_PB_CENT_FIR_ACTION0_REG_ACTION0_LEN , 18 , SH_UNT__SM0 , SH_ACS_SCOM_RW , + SH_FLD_ACTION0_LEN ); + +REG64_FLD( _SM0_PB_CENT_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT__SM0 , SH_ACS_SCOM_RW , + SH_FLD_ACTION1 ); +REG64_FLD( _SM0_PB_CENT_FIR_ACTION1_REG_ACTION1_LEN , 18 , SH_UNT__SM0 , SH_ACS_SCOM_RW , + SH_FLD_ACTION1_LEN ); + +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_PROTOCOL_ERROR , 0 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PROTOCOL_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_OVERFLOW_ERROR , 1 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_OVERFLOW_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_HW_PARITY_ERROR , 2 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_HW_PARITY_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SPARE_3 , 3 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_3 ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_COHERENCY_ERROR , 4 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_COHERENCY_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_CRESP_ADDR_ERROR , 5 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_CRESP_ADDR_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_CRESP_ERROR , 6 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_CRESP_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_HANG_RECOVERY_LIMIT_ERROR , 7 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_HANG_RECOVERY_LIMIT_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_DATA_ROUTE_ERROR , 8 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_DATA_ROUTE_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_HANG_RECOVERY_GTE_LEVEL1 , 9 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_HANG_RECOVERY_GTE_LEVEL1 ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_FORCE_MP_IPL , 10 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_FORCE_MP_IPL ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SPARE_11 , 11 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_11 ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SPARE_12 , 12 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_12 ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SPARE_13 , 13 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_13 ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SPARE_14 , 14 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_14 ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SPARE_15 , 15 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_15 ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SCOM_ERR , 16 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR ); +REG64_FLD( _SM0_PB_CENT_FIR_MASK_REG_SCOM_ERR_DUP , 17 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR_DUP ); + +REG64_FLD( _SM0_PB_CENT_FIR_REG_PROTOCOL_ERROR , 0 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PROTOCOL_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_OVERFLOW_ERROR , 1 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_OVERFLOW_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_HW_PARITY_ERROR , 2 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_HW_PARITY_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_SPARE_3 , 3 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_3 ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_COHERENCY_ERROR , 4 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_COHERENCY_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_CRESP_ADDR_ERROR , 5 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_CRESP_ADDR_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_CRESP_ERROR , 6 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_CRESP_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_HANG_RECOVERY_LIMIT_ERROR , 7 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_HANG_RECOVERY_LIMIT_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_DATA_ROUTE_ERROR , 8 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_DATA_ROUTE_ERROR ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_HANG_RECOVERY_GTE_LEVEL1 , 9 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_HANG_RECOVERY_GTE_LEVEL1 ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_FORCE_MP_IPL , 10 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_FORCE_MP_IPL ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_SPARE_11 , 11 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_11 ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_SPARE_12 , 12 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_12 ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_SPARE_13 , 13 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_13 ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_SPARE_14 , 14 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_14 ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_SPARE_15 , 15 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_15 ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_SCOM_ERR , 16 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR ); +REG64_FLD( _SM0_PB_CENT_FIR_REG_SCOM_ERR_DUP , 17 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR_DUP ); + +REG64_FLD( PU_PB_EAST_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION0 ); +REG64_FLD( PU_PB_EAST_FIR_ACTION0_REG_ACTION0_LEN , 34 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION0_LEN ); + +REG64_FLD( PU_PB_EAST_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION1 ); +REG64_FLD( PU_PB_EAST_FIR_ACTION1_REG_ACTION1_LEN , 34 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ACTION1_LEN ); + +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_HW1_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ04_PBH_HW1_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_HW2_ERROR , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ04_PBH_HW2_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_PROTOCOL_ERROR , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ04_PBH_PROTOCOL_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_OVERFLOW_ERROR , 3 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ04_PBH_OVERFLOW_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_HW1_ERROR , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ05_PBH_HW1_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_HW2_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ05_PBH_HW2_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_PROTOCOL_ERROR , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ05_PBH_PROTOCOL_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_OVERFLOW_ERROR , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ05_PBH_OVERFLOW_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_8 , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_8 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_9 , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_9 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_10 , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_10 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_11 , 11 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_12 , 12 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_12 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_13 , 13 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_13 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_14 , 14 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_14 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_15 , 15 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_15 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_OVERFLOW_CHECKSTOP , 16 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_OVERFLOW_CHECKSTOP ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PROTOCOL_CHECKSTOP , 17 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PROTOCOL_CHECKSTOP ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_ROUTE_CHECKSTOP , 18 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ROUTE_CHECKSTOP ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_19 , 19 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_19 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_20 , 20 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_20 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_21 , 21 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_21 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_22 , 22 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_22 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_23 , 23 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_23 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_24 , 24 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_24 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_25 , 25 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_25 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_26 , 26 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_26 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_27 , 27 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_27 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_28 , 28 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_28 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_29 , 29 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_29 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_30 , 30 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_30 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_31 , 31 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_31 ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SCOM_ERR , 32 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR ); +REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SCOM_ERR_DUP , 33 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR_DUP ); + +REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ04_PBH_HW1_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ04_PBH_HW1_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ04_PBH_HW2_ERROR , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ04_PBH_HW2_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ04_PBH_PROTOCOL_ERROR , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ04_PBH_PROTOCOL_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ04_PBH_OVERFLOW_ERROR , 3 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ04_PBH_OVERFLOW_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ05_PBH_HW1_ERROR , 4 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ05_PBH_HW1_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ05_PBH_HW2_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ05_PBH_HW2_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ05_PBH_PROTOCOL_ERROR , 6 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ05_PBH_PROTOCOL_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ05_PBH_OVERFLOW_ERROR , 7 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ05_PBH_OVERFLOW_ERROR ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_8 , 8 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_8 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_9 , 9 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_9 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_10 , 10 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_10 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_11 , 11 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_11 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_12 , 12 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_12 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_13 , 13 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_13 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_14 , 14 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_14 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_15 , 15 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_15 ); +REG64_FLD( PU_PB_EAST_FIR_REG_OVERFLOW_CHECKSTOP , 16 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_OVERFLOW_CHECKSTOP ); +REG64_FLD( PU_PB_EAST_FIR_REG_PROTOCOL_CHECKSTOP , 17 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_PROTOCOL_CHECKSTOP ); +REG64_FLD( PU_PB_EAST_FIR_REG_ROUTE_CHECKSTOP , 18 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_ROUTE_CHECKSTOP ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_19 , 19 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_19 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_20 , 20 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_20 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_21 , 21 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_21 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_22 , 22 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_22 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_23 , 23 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_23 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_24 , 24 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_24 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_25 , 25 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_25 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_26 , 26 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_26 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_27 , 27 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_27 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_28 , 28 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_28 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_29 , 29 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_29 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_30 , 30 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_30 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_31 , 31 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_31 ); +REG64_FLD( PU_PB_EAST_FIR_REG_SCOM_ERR , 32 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR ); +REG64_FLD( PU_PB_EAST_FIR_REG_SCOM_ERR_DUP , 33 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR_DUP ); + REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK0_DOB_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , @@ -46095,140 +57193,140 @@ REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT , 49 , SH_UN REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_VC1_LIMIT_LEN ); -REG64_FLD( PU_PB_ELINK_PMU0_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU0_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_PB_ELINK_PMU0_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU0_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_PB_ELINK_PMU0_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU0_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_PB_ELINK_PMU0_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU0_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_PB_ELINK_PMU0_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU0_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_PB_ELINK_PMU0_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU0_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_PB_ELINK_PMU0_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU0_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_PB_ELINK_PMU0_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU0_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); -REG64_FLD( PU_PB_ELINK_PMU1_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU1_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_PB_ELINK_PMU1_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU1_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_PB_ELINK_PMU1_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU1_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_PB_ELINK_PMU1_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU1_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_PB_ELINK_PMU1_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU1_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_PB_ELINK_PMU1_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU1_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_PB_ELINK_PMU1_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU1_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_PB_ELINK_PMU1_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU1_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); -REG64_FLD( PU_PB_ELINK_PMU2_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU2_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_PB_ELINK_PMU2_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU2_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_PB_ELINK_PMU2_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU2_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_PB_ELINK_PMU2_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU2_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_PB_ELINK_PMU2_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU2_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_PB_ELINK_PMU2_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU2_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_PB_ELINK_PMU2_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU2_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_PB_ELINK_PMU2_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU2_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); -REG64_FLD( PU_PB_ELINK_PMU3_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU3_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_PB_ELINK_PMU3_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU3_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_PB_ELINK_PMU3_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU3_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_PB_ELINK_PMU3_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU3_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_PB_ELINK_PMU3_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU3_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_PB_ELINK_PMU3_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU3_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_PB_ELINK_PMU3_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU3_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_PB_ELINK_PMU3_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU3_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); -REG64_FLD( PU_PB_ELINK_PMU4_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU4_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_PB_ELINK_PMU4_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU4_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_PB_ELINK_PMU4_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU4_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_PB_ELINK_PMU4_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU4_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_PB_ELINK_PMU4_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU4_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_PB_ELINK_PMU4_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU4_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_PB_ELINK_PMU4_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU4_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_PB_ELINK_PMU4_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU4_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); -REG64_FLD( PU_PB_ELINK_PMU5_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU5_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_PB_ELINK_PMU5_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU5_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_PB_ELINK_PMU5_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU5_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_PB_ELINK_PMU5_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU5_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_PB_ELINK_PMU5_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU5_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_PB_ELINK_PMU5_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU5_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_PB_ELINK_PMU5_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU5_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_PB_ELINK_PMU5_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU5_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); -REG64_FLD( PU_PB_ELINK_PMU6_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU6_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_PB_ELINK_PMU6_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU6_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_PB_ELINK_PMU6_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU6_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_PB_ELINK_PMU6_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU6_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_PB_ELINK_PMU6_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU6_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_PB_ELINK_PMU6_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU6_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_PB_ELINK_PMU6_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU6_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_PB_ELINK_PMU6_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU6_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); -REG64_FLD( PU_PB_ELINK_PMU7_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU7_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_PB_ELINK_PMU7_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU7_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_PB_ELINK_PMU7_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU7_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_PB_ELINK_PMU7_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU7_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_PB_ELINK_PMU7_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU7_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_PB_ELINK_PMU7_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU7_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_PB_ELINK_PMU7_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU7_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_PB_ELINK_PMU7_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_PB_ELINK_PMU7_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , @@ -46334,11 +57432,11 @@ REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_SPARE_LEN , 10 , SH_UN REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_SET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_SET ); -REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_SET_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_SET_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_SET_LEN ); REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_STAT , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_STAT ); -REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_STAT_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_STAT_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_STAT_LEN ); REG64_FLD( PU_PB_FP01_CFG_FP0_CREDIT_PRIORITY_4_NOT_8 , 0 , SH_UNT , SH_ACS_SCOM_RW , @@ -46361,8 +57459,10 @@ REG64_FLD( PU_PB_FP01_CFG_FP0_FMR_DISABLE , 20 , SH_UN SH_FLD_FP0_FMR_DISABLE ); REG64_FLD( PU_PB_FP01_CFG_FP0_FMR_SPARE , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_FMR_SPARE ); -REG64_FLD( PU_PB_FP01_CFG_FP0_FMR_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_FP0_FMR_SPARE_LEN ); +REG64_FLD( PU_PB_FP01_CFG_CMD_EXP_TIME , 22 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CMD_EXP_TIME ); +REG64_FLD( PU_PB_FP01_CFG_CMD_EXP_TIME_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CMD_EXP_TIME_LEN ); REG64_FLD( PU_PB_FP01_CFG_FP0_RUN_AFTER_FRAME_ERROR , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_PB_FP01_CFG_FP0_PRS_DISABLE , 25 , SH_UNT , SH_ACS_SCOM_RW , @@ -46422,8 +57522,10 @@ REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_FMR_DISABLE , 20 , SH_UN SH_FLD_FP0_FMR_DISABLE ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_FMR_SPARE , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_FMR_SPARE ); -REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_FMR_SPARE_LEN , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , - SH_FLD_FP0_FMR_SPARE_LEN ); +REG64_FLD( PU_IOE_PB_FP01_CFG_CMD_EXP_TIME , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_CMD_EXP_TIME ); +REG64_FLD( PU_IOE_PB_FP01_CFG_CMD_EXP_TIME_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_CMD_EXP_TIME_LEN ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_RUN_AFTER_FRAME_ERROR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_PRS_DISABLE , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , @@ -46483,8 +57585,10 @@ REG64_FLD( PU_PB_FP23_CFG_FP2_FMR_DISABLE , 20 , SH_UN SH_FLD_FP2_FMR_DISABLE ); REG64_FLD( PU_PB_FP23_CFG_FP2_FMR_SPARE , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_FMR_SPARE ); -REG64_FLD( PU_PB_FP23_CFG_FP2_FMR_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_FP2_FMR_SPARE_LEN ); +REG64_FLD( PU_PB_FP23_CFG_CMD_EXP_TIME , 22 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CMD_EXP_TIME ); +REG64_FLD( PU_PB_FP23_CFG_CMD_EXP_TIME_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CMD_EXP_TIME_LEN ); REG64_FLD( PU_PB_FP23_CFG_FP2_RUN_AFTER_FRAME_ERROR , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_PB_FP23_CFG_FP2_PRS_DISABLE , 25 , SH_UNT , SH_ACS_SCOM_RW , @@ -46544,8 +57648,10 @@ REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_FMR_DISABLE , 20 , SH_UN SH_FLD_FP2_FMR_DISABLE ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_FMR_SPARE , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_FMR_SPARE ); -REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_FMR_SPARE_LEN , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , - SH_FLD_FP2_FMR_SPARE_LEN ); +REG64_FLD( PU_IOE_PB_FP23_CFG_CMD_EXP_TIME , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_CMD_EXP_TIME ); +REG64_FLD( PU_IOE_PB_FP23_CFG_CMD_EXP_TIME_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_CMD_EXP_TIME_LEN ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_RUN_AFTER_FRAME_ERROR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_PRS_DISABLE , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , @@ -46605,8 +57711,10 @@ REG64_FLD( PU_PB_FP45_CFG_FP4_FMR_DISABLE , 20 , SH_UN SH_FLD_FP4_FMR_DISABLE ); REG64_FLD( PU_PB_FP45_CFG_FP4_FMR_SPARE , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_FMR_SPARE ); -REG64_FLD( PU_PB_FP45_CFG_FP4_FMR_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_FP4_FMR_SPARE_LEN ); +REG64_FLD( PU_PB_FP45_CFG_CMD_EXP_TIME , 22 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CMD_EXP_TIME ); +REG64_FLD( PU_PB_FP45_CFG_CMD_EXP_TIME_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CMD_EXP_TIME_LEN ); REG64_FLD( PU_PB_FP45_CFG_FP4_RUN_AFTER_FRAME_ERROR , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_PB_FP45_CFG_FP4_PRS_DISABLE , 25 , SH_UNT , SH_ACS_SCOM_RW , @@ -46666,8 +57774,10 @@ REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_FMR_DISABLE , 20 , SH_UN SH_FLD_FP4_FMR_DISABLE ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_FMR_SPARE , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_FMR_SPARE ); -REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_FMR_SPARE_LEN , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , - SH_FLD_FP4_FMR_SPARE_LEN ); +REG64_FLD( PU_IOE_PB_FP45_CFG_CMD_EXP_TIME , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_CMD_EXP_TIME ); +REG64_FLD( PU_IOE_PB_FP45_CFG_CMD_EXP_TIME_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_CMD_EXP_TIME_LEN ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_RUN_AFTER_FRAME_ERROR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_PRS_DISABLE , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , @@ -46727,8 +57837,10 @@ REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_FMR_DISABLE , 20 , SH_UN SH_FLD_FP6_FMR_DISABLE ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_FMR_SPARE , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_FMR_SPARE ); -REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_FMR_SPARE_LEN , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , - SH_FLD_FP6_FMR_SPARE_LEN ); +REG64_FLD( PU_IOE_PB_FP67_CFG_CMD_EXP_TIME , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_CMD_EXP_TIME ); +REG64_FLD( PU_IOE_PB_FP67_CFG_CMD_EXP_TIME_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_CMD_EXP_TIME_LEN ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_RUN_AFTER_FRAME_ERROR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_PRS_DISABLE , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , @@ -47430,140 +58542,140 @@ REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT , 48 , SH_UN REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK7_DOB_VC1_LIMIT_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); -REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); -REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , +REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0_ENABLE , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , @@ -47676,6 +58788,56 @@ REG64_FLD( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_STAT , 8 , SH_UN REG64_FLD( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_STAT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_STAT_LEN ); +REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_HI_ENABLE ); +REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_FIXED_WINDOW_MODE , 1 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_HI_FIXED_WINDOW_MODE ); +REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_PRESCALE_MODE , 2 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_HI_PRESCALE_MODE ); +REG64_FLD( PU_PB_PERFTRACE_CFG_REG_PTSPARE6 , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PTSPARE6 ); +REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_ENABLE , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_LO_ENABLE ); +REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_FIXED_WINDOW_MODE , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_LO_FIXED_WINDOW_MODE ); +REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_PRESCALE_MODE , 6 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_LO_PRESCALE_MODE ); +REG64_FLD( PU_PB_PERFTRACE_CFG_REG_PTSPARE7 , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PTSPARE7 ); +REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_SELECT , 8 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_HI_SELECT ); +REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_HI_SELECT_LEN ); +REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_SELECT , 12 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_LO_SELECT ); +REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_LO_SELECT_LEN ); + +REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_ENABLE , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_HI_ENABLE ); +REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_FIXED_WINDOW_MODE , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_HI_FIXED_WINDOW_MODE ); +REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_PRESCALE_MODE , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_HI_PRESCALE_MODE ); +REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_PTSPARE6 , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_PTSPARE6 ); +REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_ENABLE , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_LO_ENABLE ); +REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_FIXED_WINDOW_MODE , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_LO_FIXED_WINDOW_MODE ); +REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_PRESCALE_MODE , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_LO_PRESCALE_MODE ); +REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_PTSPARE7 , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_PTSPARE7 ); +REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_SELECT , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_HI_SELECT ); +REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_SELECT_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_HI_SELECT_LEN ); +REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_SELECT , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_LO_SELECT ); +REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_SELECT_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , + SH_FLD_LO_SELECT_LEN ); + REG64_FLD( PU_PB_TRACE_CFG_LINK00_HI , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK00_HI ); REG64_FLD( PU_PB_TRACE_CFG_LINK00_HI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , @@ -47790,6 +58952,154 @@ REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK07_LO , 60 , SH_UN REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK07_LO_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK07_LO_LEN ); +REG64_FLD( _SM0_PB_WEST_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT__SM0 , SH_ACS_SCOM_RW , + SH_FLD_ACTION0 ); +REG64_FLD( _SM0_PB_WEST_FIR_ACTION0_REG_ACTION0_LEN , 34 , SH_UNT__SM0 , SH_ACS_SCOM_RW , + SH_FLD_ACTION0_LEN ); + +REG64_FLD( _SM0_PB_WEST_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT__SM0 , SH_ACS_SCOM_RW , + SH_FLD_ACTION1 ); +REG64_FLD( _SM0_PB_WEST_FIR_ACTION1_REG_ACTION1_LEN , 34 , SH_UNT__SM0 , SH_ACS_SCOM_RW , + SH_FLD_ACTION1_LEN ); + +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_HW1_ERROR , 0 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ00_PBH_HW1_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_HW2_ERROR , 1 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ00_PBH_HW2_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_PROTOCOL_ERROR , 2 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ00_PBH_PROTOCOL_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_OVERFLOW_ERROR , 3 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ00_PBH_OVERFLOW_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_HW1_ERROR , 4 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ01_PBH_HW1_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_HW2_ERROR , 5 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ01_PBH_HW2_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_PROTOCOL_ERROR , 6 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ01_PBH_PROTOCOL_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_OVERFLOW_ERROR , 7 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ01_PBH_OVERFLOW_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_HW1_ERROR , 8 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ02_PBH_HW1_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_HW2_ERROR , 9 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ02_PBH_HW2_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_PROTOCOL_ERROR , 10 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ02_PBH_PROTOCOL_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_OVERFLOW_ERROR , 11 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ02_PBH_OVERFLOW_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_HW1_ERROR , 12 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ03_PBH_HW1_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_HW2_ERROR , 13 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ03_PBH_HW2_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_PROTOCOL_ERROR , 14 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ03_PBH_PROTOCOL_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_OVERFLOW_ERROR , 15 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ03_PBH_OVERFLOW_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_16 , 16 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_16 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_17 , 17 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_17 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_18 , 18 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_18 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_19 , 19 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_19 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_20 , 20 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_20 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_21 , 21 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_21 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_22 , 22 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_22 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_23 , 23 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_23 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_24 , 24 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_24 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_25 , 25 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_25 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_26 , 26 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_26 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_27 , 27 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_27 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_28 , 28 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_28 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_29 , 29 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_29 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_30 , 30 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_30 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SPARE_31 , 31 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_31 ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SCOM_ERR , 32 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR ); +REG64_FLD( _SM0_PB_WEST_FIR_MASK_REG_SCOM_ERR_DUP , 33 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR_DUP ); + +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_HW1_ERROR , 0 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ00_PBH_HW1_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_HW2_ERROR , 1 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ00_PBH_HW2_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_PROTOCOL_ERROR , 2 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ00_PBH_PROTOCOL_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_OVERFLOW_ERROR , 3 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ00_PBH_OVERFLOW_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_HW1_ERROR , 4 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ01_PBH_HW1_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_HW2_ERROR , 5 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ01_PBH_HW2_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_PROTOCOL_ERROR , 6 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ01_PBH_PROTOCOL_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_OVERFLOW_ERROR , 7 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ01_PBH_OVERFLOW_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_HW1_ERROR , 8 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ02_PBH_HW1_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_HW2_ERROR , 9 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ02_PBH_HW2_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_PROTOCOL_ERROR , 10 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ02_PBH_PROTOCOL_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_OVERFLOW_ERROR , 11 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ02_PBH_OVERFLOW_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_HW1_ERROR , 12 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ03_PBH_HW1_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_HW2_ERROR , 13 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ03_PBH_HW2_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_PROTOCOL_ERROR , 14 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ03_PBH_PROTOCOL_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_OVERFLOW_ERROR , 15 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_PBIEQ03_PBH_OVERFLOW_ERROR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_16 , 16 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_16 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_17 , 17 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_17 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_18 , 18 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_18 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_19 , 19 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_19 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_20 , 20 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_20 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_21 , 21 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_21 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_22 , 22 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_22 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_23 , 23 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_23 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_24 , 24 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_24 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_25 , 25 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_25 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_26 , 26 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_26 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_27 , 27 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_27 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_28 , 28 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_28 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_29 , 29 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_29 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_30 , 30 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_30 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SPARE_31 , 31 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_31 ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SCOM_ERR , 32 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR ); +REG64_FLD( _SM0_PB_WEST_FIR_REG_SCOM_ERR_DUP , 33 , SH_UNT__SM0 , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_ERR_DUP ); + REG64_FLD( PEC_PCS_M1_CONTROL_REG_CONTROL , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONTROL ); REG64_FLD( PEC_PCS_M1_CONTROL_REG_CONTROL_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , @@ -47817,184 +59127,264 @@ REG64_FLD( PEC_PCS_SYS_CONTROL_REG_CONTROL_LEN , 16 , SH_UN REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_EN , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CAPP_EN ); -REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_DMA , 1 , SH_UNT_PEC , SH_ACS_SCOM_RW , - SH_FLD_PE_CAPP_DMA ); -REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_256 , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , - SH_FLD_PE_CAPP_256 ); -REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_P8_MODE , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , +REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_P8_MODE , 1 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CAPP_P8_MODE ); +REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_NUM_MSG_ENG , 12 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_PE_CAPP_NUM_MSG_ENG ); +REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_NUM_MSG_ENG_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_PE_CAPP_NUM_MSG_ENG_LEN ); +REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_APC_ENG , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_PE_CAPP_APC_ENG ); +REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_APC_ENG_LEN , 48 , SH_UNT_PEC , SH_ACS_SCOM_RW , + SH_FLD_PE_CAPP_APC_ENG_LEN ); REG64_FLD( PEC_PECAPP_SEC_BAR_PE_CAPP , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PE_CAPP ); REG64_FLD( PEC_PECAPP_SEC_BAR_PE_CAPP_LEN , 26 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PE_CAPP_LEN ); -REG64_FLD( PU_NPU0_SM0_PERF2_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_PERF2_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU1_SM2_PERF2_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_PERF2_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU2_SM3_PERF2_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_PERF2_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU1_SM3_PERF2_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_PERF2_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU0_SM3_PERF2_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_PERF2_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU1_SM1_PERF2_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_PERF2_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU2_SM2_PERF2_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_PERF2_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU2_SM1_PERF2_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_PERF2_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU0_SM2_PERF2_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_PERF2_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU2_SM0_PERF2_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_PERF2_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU0_SM1_PERF2_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_PERF2_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU1_SM0_PERF2_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_PERF2_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU0_SM0_PERF3_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_PERF3_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU1_SM2_PERF3_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_PERF3_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU2_SM3_PERF3_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_PERF3_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU1_SM3_PERF3_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_PERF3_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU0_SM3_PERF3_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_PERF3_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU1_SM1_PERF3_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_PERF3_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU2_SM2_PERF3_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_PERF3_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU2_SM1_PERF3_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_PERF3_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU0_SM2_PERF3_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_PERF3_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU2_SM0_PERF3_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_PERF3_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU0_SM1_PERF3_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_PERF3_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU1_SM0_PERF3_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_PERF3_CONFIG_RESERVED1_LEN , 64 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_RESERVED1_LEN , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_RESERVED1_LEN , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_RESERVED1_LEN , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_RESERVED1_LEN , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_RESERVED1_LEN , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_RESERVED1_LEN , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_RESERVED1_LEN , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_ACT ); @@ -48044,25 +59434,123 @@ REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT3 , 40 , SH_UN SH_FLD_EVENT3 ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATSTART , 48 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATSTART_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATCANCEL , 53 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATCANCEL_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATFINISH , 58 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATFINISH_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_RESERVED , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED ); -REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_RESERVED1_LEN , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_RESERVED1_LEN , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_RESERVED1_LEN , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_ACT ); @@ -48112,6 +59600,20 @@ REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT3 , 40 , SH_UN SH_FLD_EVENT3 ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATSTART , 48 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATSTART_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATCANCEL , 53 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATCANCEL_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATFINISH , 58 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATFINISH_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_RESERVED , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); @@ -48159,18 +59661,88 @@ REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT3 , 40 , SH_UN SH_FLD_EVENT3 ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATSTART , 48 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATSTART_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATCANCEL , 53 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATCANCEL_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATFINISH , 58 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATFINISH_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_RESERVED , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_RESERVED1_LEN , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_ACT ); -REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_RESERVED1_LEN , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_LATSTART ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_LATSTART_LEN ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_LATCANCEL ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_LATCANCEL_LEN ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_EVENT0 ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_EVENT0_LEN ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_EVENT1 ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_EVENT1_LEN ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_EVENT2 ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_EVENT2_LEN ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_EVENT3 ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_EVENT3_LEN ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_LATFINISH ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_LATFINISH_LEN ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2 ); +REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_ACT ); @@ -48225,6 +59797,168 @@ REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT3 , 48 , SH_UN REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT3_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT3_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_NMCMD , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NMCMD ); +REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_NMCMD_LEN , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NMCMD_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_NMEXCMD , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NMEXCMD ); +REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_NMEXCMD_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NMEXCMD_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_BE , 11 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_BE ); +REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_CS , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_CS ); +REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_CS_LEN , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_CS_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_AECS , 18 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_AECS ); +REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_AECS_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_AECS_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_PE , 34 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_PE ); +REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_PE_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_NMCMD , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NMCMD ); +REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_NMCMD_LEN , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NMCMD_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_NMEXCMD , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NMEXCMD ); +REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_NMEXCMD_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NMEXCMD_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_BE , 11 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_BE ); +REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_CS , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_CS ); +REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_CS_LEN , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_CS_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_AECS , 18 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_AECS ); +REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_AECS_LEN , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_AECS_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_PE , 34 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PE ); +REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PE_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_NMCMD , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NMCMD ); +REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_NMCMD_LEN , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NMCMD_LEN ); +REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_NMEXCMD , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NMEXCMD ); +REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_NMEXCMD_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NMEXCMD_LEN ); +REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_BE , 11 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_BE ); +REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_CS , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_CS ); +REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_CS_LEN , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_CS_LEN ); +REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_AECS , 18 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_AECS ); +REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_AECS_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_AECS_LEN ); +REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_PE , 34 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_PE ); +REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_PE_LEN ); +REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_NMCMD , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NMCMD ); +REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_NMCMD_LEN , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NMCMD_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_NMEXCMD , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NMEXCMD ); +REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_NMEXCMD_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_NMEXCMD_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_BE , 11 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_BE ); +REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_CS , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_CS ); +REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_CS_LEN , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_CS_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_AECS , 18 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_AECS ); +REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_AECS_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_AECS_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_PE , 34 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_PE ); +REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_PE_LEN ); +REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_NMCMD , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NMCMD ); +REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_NMCMD_LEN , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NMCMD_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_NMEXCMD , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NMEXCMD ); +REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_NMEXCMD_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_NMEXCMD_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_BE , 11 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_BE ); +REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_CS , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_CS ); +REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_CS_LEN , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_CS_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_AECS , 18 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_AECS ); +REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_AECS_LEN , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_AECS_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_PE , 34 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PE ); +REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_PE_LEN ); +REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_NMCMD , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NMCMD ); +REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_NMCMD_LEN , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NMCMD_LEN ); +REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_NMEXCMD , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NMEXCMD ); +REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_NMEXCMD_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_NMEXCMD_LEN ); +REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_BE , 11 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_BE ); +REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_CS , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_CS ); +REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_CS_LEN , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_CS_LEN ); +REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_AECS , 18 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_AECS ); +REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_AECS_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_AECS_LEN ); +REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_PE , 34 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_PE ); +REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_PE_LEN ); +REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE0_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE0_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , @@ -48353,26 +60087,16 @@ REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE8_DMA_STOPPED_STATE , 0 , SH_UN REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE9_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); -REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , - SH_FLD_PE_PHB_BAR ); -REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , - SH_FLD_PE_PHB_BAR_LEN ); - -REG64_FLD( PEC_STACK1_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , - SH_FLD_PE_PHB_BAR ); -REG64_FLD( PEC_STACK1_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , - SH_FLD_PE_PHB_BAR_LEN ); +REG64_FLD( PHB_PE_DFREEZE_REG_DFREEZE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_DFREEZE ); +REG64_FLD( PHB_PE_DFREEZE_REG_DFREEZE_LEN , 28 , SH_UNT_PHB , SH_ACS_SCOM_RW , + SH_FLD_DFREEZE_LEN ); REG64_FLD( PHB_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_PHB_BAR ); REG64_FLD( PHB_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_PHB_BAR_LEN ); -REG64_FLD( PEC_STACK0_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , - SH_FLD_PE_PHB_BAR ); -REG64_FLD( PEC_STACK0_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , - SH_FLD_PE_PHB_BAR_LEN ); - REG64_FLD( PU_PBAIB_STACK5_PHBRESET_REG_PE_ETU_RESET , 0 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW , SH_FLD_PE_ETU_RESET ); @@ -48385,137 +60109,69 @@ REG64_FLD( PU_PBAIB_STACK2_PHBRESET_REG_PE_ETU_RESET , 0 , SH_UN REG64_FLD( PU_PBAIB_STACK1_PHBRESET_REG_PE_ETU_RESET , 0 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW , SH_FLD_PE_ETU_RESET ); -REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM0_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM0_PHY_BAR_RESERVED2 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM2_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM2_PHY_BAR_RESERVED2 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM3_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM3_PHY_BAR_RESERVED2 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM3_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM3_PHY_BAR_RESERVED2 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM3_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM3_PHY_BAR_RESERVED2 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM1_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM1_PHY_BAR_RESERVED2 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM2_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM2_PHY_BAR_RESERVED2 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM1_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM1_PHY_BAR_RESERVED2 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM2_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM2_PHY_BAR_RESERVED2 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU2_SM0_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU2_SM0_PHY_BAR_RESERVED2 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU0_SM1_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU0_SM1_PHY_BAR_RESERVED2 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); - -REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ENABLE ); -REG64_FLD( PU_NPU1_SM0_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ADDR , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR ); -REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ADDR_LEN ); -REG64_FLD( PU_NPU1_SM0_PHY_BAR_RESERVED2 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED2 ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ENABLE_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ENABLE_0 ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ID_0 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ID_0 ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ID_0_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ID_0_LEN ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ACTIVITY_0 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ACTIVITY_0 ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ACTIVITY_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ACTIVITY_0_LEN ); + +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ENABLE_1 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ENABLE_1 ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ID_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ID_1 ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ID_1_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ID_1_LEN ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ACTIVITY_1 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ACTIVITY_1 ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ACTIVITY_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ACTIVITY_1_LEN ); + +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ENABLE_2 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ENABLE_2 ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ID_2 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ID_2 ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ID_2_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ID_2_LEN ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ACTIVITY_2 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ACTIVITY_2 ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ACTIVITY_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ACTIVITY_2_LEN ); + +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ENABLE_3 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ENABLE_3 ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ID_3 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ID_3 ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ID_3_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ID_3_LEN ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ACTIVITY_3 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ACTIVITY_3 ); +REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ACTIVITY_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_ACTIVITY_3_LEN ); + +REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_B_CC_READ_ENABLE_0 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_READ_ENABLE_0 ); +REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_B_CC_WRITE_ENABLE_0 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_WRITE_ENABLE_0 ); + +REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_C_CC_READ_ENABLE_1 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_READ_ENABLE_1 ); +REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_C_CC_WRITE_ENABLE_1 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_WRITE_ENABLE_1 ); + +REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_D_CC_READ_ENABLE_2 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_READ_ENABLE_2 ); +REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_D_CC_WRITE_ENABLE_2 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_WRITE_ENABLE_2 ); + +REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_E_CC_READ_ENABLE_3 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_READ_ENABLE_3 ); +REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_E_CC_WRITE_ENABLE_3 , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CC_WRITE_ENABLE_3 ); REG64_FLD( PU_PIBMEM_ADDRESS_REGISTER_POINTER , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_POINTER ); @@ -48540,7 +60196,7 @@ REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_POST_DECREMENT_FACES , 4 , SH_UN REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_0_DATA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA ); -REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_0_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_0_DATA_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_LEN ); REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_1_DATA , 0 , SH_UNT , SH_ACS_SCOM , @@ -48553,6 +60209,11 @@ REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_2_DATA , 0 , SH_UN REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_2_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_LEN ); +REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_3_DATA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA ); +REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_3_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DATA_LEN ); + REG64_FLD( PU_PIBMEM_RESET_REGISTER_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESET ); REG64_FLD( PU_PIBMEM_RESET_REGISTER_RESET_LEN , 2 , SH_UNT , SH_ACS_SCOM , @@ -48626,14 +60287,161 @@ REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE3 , 48 , SH_UN REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE3_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PMON_MUX_BYTE3_LEN ); -REG64_FLD( PU_IOPPE_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT_PU_IOPPE , SH_ACS_SCOM , - SH_FLD_NULL_MSR_SIBRC ); -REG64_FLD( PU_IOPPE_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT_PU_IOPPE , SH_ACS_SCOM , - SH_FLD_NULL_MSR_SIBRC_LEN ); -REG64_FLD( PU_IOPPE_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT_PU_IOPPE , SH_ACS_SCOM , - SH_FLD_NULL_MSR_WE ); -REG64_FLD( PU_IOPPE_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT_PU_IOPPE , SH_ACS_SCOM , - SH_FLD_NULL_MSR_LP ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_ENABLE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER0_ENABLE ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_ENABLE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER1_ENABLE ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_ENABLE , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER2_ENABLE ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_ENABLE , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER3_ENABLE ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_PRESCALER_SELECT , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_PRESCALER_SELECT ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_PRESCALER_SELECT_LEN , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_PRESCALER_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER_FREEZE_MODE , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER_FREEZE_MODE ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER_RESET_MODE , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER_RESET_MODE ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_EVENT_SELECT , 9 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER0_EVENT_SELECT ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER0_EVENT_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_POSEDGE_SELECT , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER0_POSEDGE_SELECT ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_BIT_PAIR_SELECT , 14 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_EVENT_SELECT , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER1_EVENT_SELECT ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER1_EVENT_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_POSEDGE_SELECT , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER1_POSEDGE_SELECT ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_BIT_PAIR_SELECT , 21 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_EVENT_SELECT , 23 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER2_EVENT_SELECT ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER2_EVENT_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_POSEDGE_SELECT , 27 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER2_POSEDGE_SELECT ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_BIT_PAIR_SELECT , 28 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_EVENT_SELECT , 30 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER3_EVENT_SELECT ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER3_EVENT_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_POSEDGE_SELECT , 34 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER3_POSEDGE_SELECT ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_BIT_PAIR_SELECT , 35 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_PORT_SELECT , 37 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_PORT_SELECT ); +REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_PORT_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUA_PORT_SELECT_LEN ); + +REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_0 , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERA_0 ); +REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_0_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERA_0_LEN ); +REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_1 , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERA_1 ); +REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_1_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERA_1_LEN ); +REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_2 , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERA_2 ); +REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_2_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERA_2_LEN ); +REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_3 , 48 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERA_3 ); +REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_3_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERA_3_LEN ); + +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_ENABLE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER0_ENABLE ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_ENABLE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER1_ENABLE ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_ENABLE , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER2_ENABLE ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_ENABLE , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER3_ENABLE ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_PRESCALER_SELECT , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_PRESCALER_SELECT ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_PRESCALER_SELECT_LEN , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_PRESCALER_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER_FREEZE_MODE , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER_FREEZE_MODE ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER_RESET_MODE , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER_RESET_MODE ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_EVENT_SELECT , 9 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER0_EVENT_SELECT ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER0_EVENT_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_POSEDGE_SELECT , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER0_POSEDGE_SELECT ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_BIT_PAIR_SELECT , 14 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_EVENT_SELECT , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER1_EVENT_SELECT ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER1_EVENT_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_POSEDGE_SELECT , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER1_POSEDGE_SELECT ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_BIT_PAIR_SELECT , 21 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_EVENT_SELECT , 23 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER2_EVENT_SELECT ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER2_EVENT_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_POSEDGE_SELECT , 27 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER2_POSEDGE_SELECT ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_BIT_PAIR_SELECT , 28 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_EVENT_SELECT , 30 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER3_EVENT_SELECT ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER3_EVENT_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_POSEDGE_SELECT , 34 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER3_POSEDGE_SELECT ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_BIT_PAIR_SELECT , 35 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT_LEN ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_PORT_SELECT , 37 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_PORT_SELECT ); +REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_PORT_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMUB_PORT_SELECT_LEN ); + +REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_0 , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERB_0 ); +REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_0_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERB_0_LEN ); +REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_1 , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERB_1 ); +REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_1_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERB_1_LEN ); +REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_2 , 32 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERB_2 ); +REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_2_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERB_2_LEN ); +REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_3 , 48 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERB_3 ); +REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_3_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_COUNTERB_3_LEN ); REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); @@ -48644,19 +60452,6 @@ REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UN REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); -REG64_FLD( PU_IOPPE_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT_PU_IOPPE , SH_ACS_SCOM , - SH_FLD_NULL_MSR_SIBRC ); -REG64_FLD( PU_IOPPE_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT_PU_IOPPE , SH_ACS_SCOM , - SH_FLD_NULL_MSR_SIBRC_LEN ); -REG64_FLD( PU_IOPPE_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT_PU_IOPPE , SH_ACS_SCOM , - SH_FLD_NULL_MSR_WE ); -REG64_FLD( PU_IOPPE_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT_PU_IOPPE , SH_ACS_SCOM , - SH_FLD_NULL_MSR_LP ); -REG64_FLD( PU_IOPPE_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM , - SH_FLD_XIRAMRA_SPRG0 ); -REG64_FLD( PU_IOPPE_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM , - SH_FLD_XIRAMRA_SPRG0_LEN ); - REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , @@ -48670,15 +60465,6 @@ REG64_FLD( PU_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UN REG64_FLD( PU_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0_LEN ); -REG64_FLD( PU_IOPPE_PPE_XIRAMEDR_XIRAMGA_IR , 0 , SH_UNT_PU_IOPPE , SH_ACS_SCOM , - SH_FLD_XIRAMGA_IR ); -REG64_FLD( PU_IOPPE_PPE_XIRAMEDR_XIRAMGA_IR_LEN , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM , - SH_FLD_XIRAMGA_IR_LEN ); -REG64_FLD( PU_IOPPE_PPE_XIRAMEDR_EDR , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM , - SH_FLD_EDR ); -REG64_FLD( PU_IOPPE_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM , - SH_FLD_EDR_LEN ); - REG64_FLD( PU_PPE_XIRAMEDR_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR ); REG64_FLD( PU_PPE_XIRAMEDR_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM , @@ -48688,15 +60474,6 @@ REG64_FLD( PU_PPE_XIRAMEDR_EDR , 32 , SH_UN REG64_FLD( PU_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_EDR_LEN ); -REG64_FLD( PU_IOPPE_PPE_XIRAMGA_IR , 0 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_WO , - SH_FLD_IR ); -REG64_FLD( PU_IOPPE_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_WO , - SH_FLD_IR_LEN ); -REG64_FLD( PU_IOPPE_PPE_XIRAMGA_XIRAMRA_SPRG0 , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_WO , - SH_FLD_XIRAMRA_SPRG0 ); -REG64_FLD( PU_IOPPE_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_WO , - SH_FLD_XIRAMRA_SPRG0_LEN ); - REG64_FLD( PU_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_IR ); REG64_FLD( PU_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , @@ -48706,15 +60483,6 @@ REG64_FLD( PU_PPE_XIRAMGA_XIRAMRA_SPRG0 , 32 , SH_UN REG64_FLD( PU_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0_LEN ); -REG64_FLD( PU_IOPPE_PPE_XIRAMRA_XIXCR_XCR , 1 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_WO , - SH_FLD_XIXCR_XCR ); -REG64_FLD( PU_IOPPE_PPE_XIRAMRA_XIXCR_XCR_LEN , 3 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_WO , - SH_FLD_XIXCR_XCR_LEN ); -REG64_FLD( PU_IOPPE_PPE_XIRAMRA_SPRG0 , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_WO , - SH_FLD_SPRG0 ); -REG64_FLD( PU_IOPPE_PPE_XIRAMRA_SPRG0_LEN , 32 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_WO , - SH_FLD_SPRG0_LEN ); - REG64_FLD( PU_PPE_XIRAMRA_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR ); REG64_FLD( PU_PPE_XIRAMRA_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , @@ -48724,11 +60492,6 @@ REG64_FLD( PU_PPE_XIRAMRA_SPRG0 , 32 , SH_UN REG64_FLD( PU_PPE_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_SPRG0_LEN ); -REG64_FLD( PU_IOPPE_PPE_XIXCR_XCR , 1 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_WO , - SH_FLD_XCR ); -REG64_FLD( PU_IOPPE_PPE_XIXCR_XCR_LEN , 3 , SH_UNT_PU_IOPPE , SH_ACS_SCOM_WO , - SH_FLD_XCR_LEN ); - REG64_FLD( PU_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR ); REG64_FLD( PU_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , @@ -48743,6 +60506,11 @@ REG64_FLD( PEC_PREDV_REG_PE_WR_TIMEOUT_MASK , 8 , SH_UN REG64_FLD( PEC_PREDV_REG_PE_WR_TIMEOUT_MASK_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_WR_TIMEOUT_MASK_LEN ); +REG64_FLD( PEC_PRE_COUNTER_REG_COUNTER , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COUNTER ); +REG64_FLD( PEC_PRE_COUNTER_REG_COUNTER_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_COUNTER_LEN ); + REG64_FLD( PU_PRGM_REGISTER_PRGM_ADDR , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRGM_ADDR ); REG64_FLD( PU_PRGM_REGISTER_PRGM_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM , @@ -48757,6 +60525,701 @@ REG64_FLD( PU_PROBE_PROTECT_STATUS_BITS , 0 , SH_UN REG64_FLD( PU_PROBE_PROTECT_STATUS_BITS_LEN , 42 , SH_UNT , SH_ACS_SCOM , SH_FLD_BITS_LEN ); +REG64_FLD( PEC_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_READ_ENABLE ); +REG64_FLD( PEC_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WRITE_ENABLE ); + +REG64_FLD( PU_PRV_MISC_RESERVED_18 , 0 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_18 ); +REG64_FLD( PU_PRV_MISC_TPSBE_TPBR_SBE_INTR , 1 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_TPSBE_TPBR_SBE_INTR ); +REG64_FLD( PU_PRV_MISC_SBE_EXTERNAL_FIRS , 2 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_SBE_EXTERNAL_FIRS ); +REG64_FLD( PU_PRV_MISC_SBE_EXTERNAL_FIRS_LEN , 4 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_SBE_EXTERNAL_FIRS_LEN ); +REG64_FLD( PU_PRV_MISC_RESERVED_17 , 6 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_17 ); +REG64_FLD( PU_PRV_MISC_RESERVED_17_LEN , 6 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_17_LEN ); +REG64_FLD( PU_PRV_MISC_TPSBE_TPIO_TPM_RESET , 12 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_TPSBE_TPIO_TPM_RESET ); +REG64_FLD( PU_PRV_MISC_TPSBE_TPOCC_HALT_COMPLEX , 13 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_TPSBE_TPOCC_HALT_COMPLEX ); +REG64_FLD( PU_PRV_MISC_RESERVED_16 , 14 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_16 ); +REG64_FLD( PU_PRV_MISC_RESERVED_16_LEN , 2 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_RESERVED_16_LEN ); +REG64_FLD( PU_PRV_MISC_I2C_TIMEOUT_VALUE , 16 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_I2C_TIMEOUT_VALUE ); +REG64_FLD( PU_PRV_MISC_I2C_TIMEOUT_VALUE_LEN , 32 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_I2C_TIMEOUT_VALUE_LEN ); + +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_PCB_WDATA_PARITY ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_DL_RETURN_P0 ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_UL_RDATA_PARITY ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_UL_P0 ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_PARALLEL_READ_NVLD ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_PCB_COMMAND_PARITY ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_GENERAL_TIMEOUT ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_N3_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_PCB_WDATA_PARITY ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_DL_RETURN_P0 ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_UL_RDATA_PARITY ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_UL_P0 ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_PARALLEL_READ_NVLD ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_PCB_COMMAND_PARITY ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_GENERAL_TIMEOUT ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_N1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_PCB_WDATA_PARITY ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_DL_RETURN_P0 ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_UL_RDATA_PARITY ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_UL_P0 ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_PARALLEL_READ_NVLD ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_PCB_COMMAND_PARITY ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_GENERAL_TIMEOUT ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_N2_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + +REG64_FLD( PEC_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_WDATA_PARITY ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_PARITY ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DL_RETURN_P0 ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UL_RDATA_PARITY ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UL_P0 ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARALLEL_WRITE_NVLD ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARALLEL_READ_NVLD ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PARALLEL_ADDR_INVALID ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PCB_COMMAND_PARITY ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_GENERAL_TIMEOUT ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PEC_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_PCB_WDATA_PARITY ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_DL_RETURN_P0 ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_UL_RDATA_PARITY ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_UL_P0 ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_PARALLEL_READ_NVLD ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_PCB_COMMAND_PARITY ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_GENERAL_TIMEOUT ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_N0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + +REG64_FLD( PU_N3_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); +REG64_FLD( PU_N3_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); +REG64_FLD( PU_N3_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); +REG64_FLD( PU_N3_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); +REG64_FLD( PU_N3_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_WATCHDOG_ENABLE ); +REG64_FLD( PU_N3_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT ); +REG64_FLD( PU_N3_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT_LEN ); +REG64_FLD( PU_N3_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_FORCE_ALL_RINGS ); +REG64_FLD( PU_N3_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); +REG64_FLD( PU_N3_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RESERVED_LT ); +REG64_FLD( PU_N3_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RESERVED_LT_LEN ); + +REG64_FLD( PU_N1_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); +REG64_FLD( PU_N1_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); +REG64_FLD( PU_N1_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); +REG64_FLD( PU_N1_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); +REG64_FLD( PU_N1_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_WATCHDOG_ENABLE ); +REG64_FLD( PU_N1_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT ); +REG64_FLD( PU_N1_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT_LEN ); +REG64_FLD( PU_N1_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_FORCE_ALL_RINGS ); +REG64_FLD( PU_N1_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); +REG64_FLD( PU_N1_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RESERVED_LT ); +REG64_FLD( PU_N1_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RESERVED_LT_LEN ); + +REG64_FLD( PU_N2_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); +REG64_FLD( PU_N2_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); +REG64_FLD( PU_N2_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); +REG64_FLD( PU_N2_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); +REG64_FLD( PU_N2_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_WATCHDOG_ENABLE ); +REG64_FLD( PU_N2_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT ); +REG64_FLD( PU_N2_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT_LEN ); +REG64_FLD( PU_N2_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_FORCE_ALL_RINGS ); +REG64_FLD( PU_N2_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); +REG64_FLD( PU_N2_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RESERVED_LT ); +REG64_FLD( PU_N2_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RESERVED_LT_LEN ); + +REG64_FLD( PEC_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); +REG64_FLD( PEC_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); +REG64_FLD( PEC_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); +REG64_FLD( PEC_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); +REG64_FLD( PEC_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WATCHDOG_ENABLE ); +REG64_FLD( PEC_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT ); +REG64_FLD( PEC_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT_LEN ); +REG64_FLD( PEC_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_ALL_RINGS ); +REG64_FLD( PEC_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); +REG64_FLD( PEC_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESERVED_LT ); +REG64_FLD( PEC_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESERVED_LT_LEN ); + +REG64_FLD( PU_N0_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); +REG64_FLD( PU_N0_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); +REG64_FLD( PU_N0_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); +REG64_FLD( PU_N0_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); +REG64_FLD( PU_N0_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_WATCHDOG_ENABLE ); +REG64_FLD( PU_N0_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT ); +REG64_FLD( PU_N0_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT_LEN ); +REG64_FLD( PU_N0_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_FORCE_ALL_RINGS ); +REG64_FLD( PU_N0_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); +REG64_FLD( PU_N0_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RESERVED_LT ); +REG64_FLD( PU_N0_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RESERVED_LT_LEN ); + +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_P0 ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_P0 ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_WDATA_PARITY ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_P0 ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_RDATA_PARITY ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_P0 ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_TRAPPED_GENERAL_TIMEOUT ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_PU_N3 , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_P0 ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_P0 ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_WDATA_PARITY ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_P0 ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_RDATA_PARITY ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_P0 ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_GENERAL_TIMEOUT ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_PU_N1 , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_P0 ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_P0 ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_WDATA_PARITY ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_P0 ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_RDATA_PARITY ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_P0 ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_TRAPPED_GENERAL_TIMEOUT ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_PU_N2 , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_P0 ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_P0 ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_WDATA_PARITY ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_P0 ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_RDATA_PARITY ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_P0 ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRAPPED_GENERAL_TIMEOUT ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_P0 ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_P0 ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_WDATA_PARITY ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_P0 ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_RDATA_PARITY ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_P0 ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_TRAPPED_GENERAL_TIMEOUT ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_PU_N0 , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ERR_BITS , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIHB2FSP_INJ_ERR_BITS ); REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ERR_BITS_LEN , 2 , SH_UNT , SH_ACS_SCOM , @@ -49121,10 +61584,90 @@ REG64_FLD( PU_PSI_TCE_ADDR_REG_ENTRIES , 61 , SH_UN REG64_FLD( PU_PSI_TCE_ADDR_REG_ENTRIES_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENTRIES_LEN ); -REG64_FLD( PU_PSU_HOST_DOORBELL_REG_DOORBELL , 0 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_DOORBELL ); -REG64_FLD( PU_PSU_HOST_DOORBELL_REG_FLAG , 1 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_FLAG ); +REG64_FLD( CAPP_PSLTTMAP0_VALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_VALID ); +REG64_FLD( CAPP_PSLTTMAP0_TTYPE_MATCH , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_MATCH ); +REG64_FLD( CAPP_PSLTTMAP0_TTYPE_MATCH_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_MATCH_LEN ); +REG64_FLD( CAPP_PSLTTMAP0_TSIZE_MATCH , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MATCH ); +REG64_FLD( CAPP_PSLTTMAP0_TSIZE_MATCH_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MATCH_LEN ); +REG64_FLD( CAPP_PSLTTMAP0_TSIZE_MASK , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MASK ); +REG64_FLD( CAPP_PSLTTMAP0_TSIZE_MASK_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MASK_LEN ); +REG64_FLD( CAPP_PSLTTMAP0_TTYPE_REPLACE , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_REPLACE ); +REG64_FLD( CAPP_PSLTTMAP0_TTYPE_REPLACE_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_REPLACE_LEN ); + +REG64_FLD( CAPP_PSLTTMAP1_VALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_VALID ); +REG64_FLD( CAPP_PSLTTMAP1_TTYPE_MATCH , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_MATCH ); +REG64_FLD( CAPP_PSLTTMAP1_TTYPE_MATCH_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_MATCH_LEN ); +REG64_FLD( CAPP_PSLTTMAP1_TSIZE_MATCH , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MATCH ); +REG64_FLD( CAPP_PSLTTMAP1_TSIZE_MATCH_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MATCH_LEN ); +REG64_FLD( CAPP_PSLTTMAP1_TSIZE_MASK , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MASK ); +REG64_FLD( CAPP_PSLTTMAP1_TSIZE_MASK_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MASK_LEN ); +REG64_FLD( CAPP_PSLTTMAP1_TTYPE_REPLACE , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_REPLACE ); +REG64_FLD( CAPP_PSLTTMAP1_TTYPE_REPLACE_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_REPLACE_LEN ); + +REG64_FLD( CAPP_PSLTTMAP2_VALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_VALID ); +REG64_FLD( CAPP_PSLTTMAP2_TTYPE_MATCH , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_MATCH ); +REG64_FLD( CAPP_PSLTTMAP2_TTYPE_MATCH_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_MATCH_LEN ); +REG64_FLD( CAPP_PSLTTMAP2_TSIZE_MATCH , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MATCH ); +REG64_FLD( CAPP_PSLTTMAP2_TSIZE_MATCH_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MATCH_LEN ); +REG64_FLD( CAPP_PSLTTMAP2_TSIZE_MASK , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MASK ); +REG64_FLD( CAPP_PSLTTMAP2_TSIZE_MASK_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MASK_LEN ); +REG64_FLD( CAPP_PSLTTMAP2_TTYPE_REPLACE , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_REPLACE ); +REG64_FLD( CAPP_PSLTTMAP2_TTYPE_REPLACE_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_REPLACE_LEN ); + +REG64_FLD( CAPP_PSLTTMAP3_VALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_VALID ); +REG64_FLD( CAPP_PSLTTMAP3_TTYPE_MATCH , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_MATCH ); +REG64_FLD( CAPP_PSLTTMAP3_TTYPE_MATCH_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_MATCH_LEN ); +REG64_FLD( CAPP_PSLTTMAP3_TSIZE_MATCH , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MATCH ); +REG64_FLD( CAPP_PSLTTMAP3_TSIZE_MATCH_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MATCH_LEN ); +REG64_FLD( CAPP_PSLTTMAP3_TSIZE_MASK , 13 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MASK ); +REG64_FLD( CAPP_PSLTTMAP3_TSIZE_MASK_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TSIZE_MASK_LEN ); +REG64_FLD( CAPP_PSLTTMAP3_TTYPE_REPLACE , 20 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_REPLACE ); +REG64_FLD( CAPP_PSLTTMAP3_TTYPE_REPLACE_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TTYPE_REPLACE_LEN ); + +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_0 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_1 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_2 , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_2 ); +REG64_FLD( PU_PSU_HOST_DOORBELL_REG_3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_3 ); REG64_FLD( PU_PSU_HOST_SBE_MBOX0_REG_MBOX0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX0 ); @@ -49414,802 +61957,194 @@ REG64_FLD( PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG_HIST , 0 , SH_UN REG64_FLD( PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG_HIST_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_LEN ); -REG64_FLD( PU_PSU_SBE_DOORBELL_REG_DOORBELL , 0 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_DOORBELL ); -REG64_FLD( PU_PSU_SBE_DOORBELL_REG_FLAG , 1 , SH_UNT , SH_ACS_SCOM2_OR , - SH_FLD_FLAG ); - -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_CL_DMA_W , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W_HP ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_CL_DMA_INJ , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_INJ ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_U ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_S ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_U ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_S ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_U ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_S ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_U ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_S ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_PR_DMA_INJ , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_PR_DMA_INJ ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_DMA_PR_W , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_DMA_PR_W ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_ADD , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_ADD ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_AND , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_AND ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_OR , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_OR ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMW_XOR , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_XOR ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_ADD , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_ADD ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_AND , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_AND ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_OR , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_OR ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_XOR , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_XOR ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_E ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_U ); -REG64_FLD( PU_NPU0_SM0_RELAXED_CMD_RESERVED1 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); - -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_CL_DMA_W , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W_HP ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_CL_DMA_INJ , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_INJ ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_U ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_S ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_U ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_S ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_U ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_S ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_U ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_S ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_PR_DMA_INJ , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_PR_DMA_INJ ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_DMA_PR_W , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_DMA_PR_W ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_ADD , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_ADD ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_AND , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_AND ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_OR , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_OR ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMW_XOR , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_XOR ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_ADD , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_ADD ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_AND , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_AND ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_OR , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_OR ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_XOR , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_XOR ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_E ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_U ); -REG64_FLD( PU_NPU1_SM2_RELAXED_CMD_RESERVED1 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); - -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_CL_DMA_W , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W_HP ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_CL_DMA_INJ , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_INJ ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_U ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_S ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_U ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_S ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_U ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_S ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_U ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_S ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_PR_DMA_INJ , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_PR_DMA_INJ ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_DMA_PR_W , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_DMA_PR_W ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_ADD , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_ADD ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_AND , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_AND ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_OR , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_OR ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMW_XOR , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_XOR ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_ADD , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_ADD ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_AND , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_AND ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_OR , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_OR ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_XOR , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_XOR ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_E ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_U ); -REG64_FLD( PU_NPU2_SM3_RELAXED_CMD_RESERVED1 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); - -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_CL_DMA_W , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W_HP ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_CL_DMA_INJ , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_INJ ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_U ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_S ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_U ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_S ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_U ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_S ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_U ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_S ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_PR_DMA_INJ , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_PR_DMA_INJ ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_DMA_PR_W , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_DMA_PR_W ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_ADD , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_ADD ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_AND , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_AND ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_OR , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_OR ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMW_XOR , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_XOR ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_ADD , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_ADD ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_AND , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_AND ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_OR , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_OR ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_XOR , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_XOR ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_E ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_U ); -REG64_FLD( PU_NPU1_SM3_RELAXED_CMD_RESERVED1 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); - -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_CL_DMA_W , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W_HP ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_CL_DMA_INJ , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_INJ ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_U ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_S ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_U ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_S ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_U ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_S ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_U ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_S ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_PR_DMA_INJ , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_PR_DMA_INJ ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_DMA_PR_W , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_DMA_PR_W ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_ADD , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_ADD ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_AND , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_AND ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_OR , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_OR ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMW_XOR , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_XOR ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_ADD , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_ADD ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_AND , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_AND ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_OR , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_OR ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_XOR , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_XOR ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_E ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_CONFIG_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_U ); -REG64_FLD( PU_NPU0_SM3_RELAXED_CMD_RESERVED1 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); - -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_CL_DMA_W , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W_HP ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_CL_DMA_INJ , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_INJ ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_U ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_S ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_U ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_S ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_U ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_S ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_U ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_S ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_PR_DMA_INJ , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_PR_DMA_INJ ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_DMA_PR_W , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_DMA_PR_W ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_ADD , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_ADD ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_AND , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_AND ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_OR , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_OR ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMW_XOR , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_XOR ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_ADD , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_ADD ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_AND , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_AND ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_OR , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_OR ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_XOR , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_XOR ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_E ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_U ); -REG64_FLD( PU_NPU1_SM1_RELAXED_CMD_RESERVED1 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); - -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_CL_DMA_W , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W_HP ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_CL_DMA_INJ , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_INJ ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_U ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_S ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_U ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_S ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_U ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_S ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_U ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_S ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_PR_DMA_INJ , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_PR_DMA_INJ ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_DMA_PR_W , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_DMA_PR_W ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_ADD , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_ADD ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_AND , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_AND ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_OR , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_OR ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMW_XOR , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_XOR ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_ADD , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_ADD ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_AND , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_AND ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_OR , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_OR ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_XOR , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_XOR ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_E ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_U ); -REG64_FLD( PU_NPU2_SM2_RELAXED_CMD_RESERVED1 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); - -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_CL_DMA_W , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W_HP ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_CL_DMA_INJ , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_INJ ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_U ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_S ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_U ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_S ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_U ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_S ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_U ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_S ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_PR_DMA_INJ , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_PR_DMA_INJ ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_DMA_PR_W , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_DMA_PR_W ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_ADD , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_ADD ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_AND , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_AND ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_OR , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_OR ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMW_XOR , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_XOR ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_ADD , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_ADD ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_AND , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_AND ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_OR , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_OR ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_XOR , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_XOR ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_E ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_U ); -REG64_FLD( PU_NPU2_SM1_RELAXED_CMD_RESERVED1 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); - -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_CL_DMA_W , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W_HP ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_CL_DMA_INJ , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_INJ ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_U ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_S ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_U ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_S ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_U ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_S ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_U ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_S ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_PR_DMA_INJ , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_PR_DMA_INJ ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_DMA_PR_W , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_DMA_PR_W ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_ADD , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_ADD ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_AND , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_AND ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_OR , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_OR ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMW_XOR , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_XOR ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_ADD , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_ADD ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_AND , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_AND ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_OR , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_OR ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_XOR , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_XOR ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_E ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_CONFIG_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_U ); -REG64_FLD( PU_NPU0_SM2_RELAXED_CMD_RESERVED1 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); - -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_CL_DMA_W , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W_HP ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_CL_DMA_INJ , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_INJ ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_U ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_S ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_U ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_S ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_U ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_S ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_U ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_S ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_PR_DMA_INJ , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_PR_DMA_INJ ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_DMA_PR_W , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_DMA_PR_W ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_ADD , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_ADD ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_AND , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_AND ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_OR , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_OR ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMW_XOR , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_XOR ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_ADD , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_ADD ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_AND , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_AND ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_OR , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_OR ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_XOR , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_XOR ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_E ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_U ); -REG64_FLD( PU_NPU2_SM0_RELAXED_CMD_RESERVED1 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); - -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_CL_DMA_W , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W_HP ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_CL_DMA_INJ , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_INJ ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_U ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_S ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_U ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_S ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_U ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_S ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_U ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_S ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_PR_DMA_INJ , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_PR_DMA_INJ ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_DMA_PR_W , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_DMA_PR_W ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_ADD , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_ADD ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_AND , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_AND ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_OR , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_OR ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMW_XOR , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_XOR ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_ADD , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_ADD ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_AND , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_AND ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_OR , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_OR ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_XOR , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_XOR ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_E ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_CONFIG_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_U ); -REG64_FLD( PU_NPU0_SM1_RELAXED_CMD_RESERVED1 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); - -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_CL_DMA_W , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_W_HP ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_CL_DMA_INJ , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_CL_DMA_INJ ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_U ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMAX_S ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_U ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_CAS_IMIN_S ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_U ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMAX_S ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_U ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_IMIN_S ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_PR_DMA_INJ , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_PR_DMA_INJ ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_DMA_PR_W , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_DMA_PR_W ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_ADD , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_ADD ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_AND , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_AND ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_OR , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_OR ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMW_XOR , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMW_XOR ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_ADD , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_ADD ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_AND , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_AND ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_OR , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_OR ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_XOR , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_XOR ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_E ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_CONFIG_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_ARMWF_CAS_U ); -REG64_FLD( PU_NPU1_SM0_RELAXED_CMD_RESERVED1 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); - -REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_CONFIG_PCIE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE ); -REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_CONFIG_PCIE_LEN , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE_LEN ); -REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_CONFIG_NPU , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NPU ); -REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_CONFIG_VAS , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_VAS ); -REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_CONFIG_NX , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NX ); -REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_CONFIG_L2L3NCU , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_L2L3NCU ); -REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_RESERVED1 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_RELAXED_SOURCE_RESERVED1_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_CONFIG_PCIE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE ); -REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_CONFIG_PCIE_LEN , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE_LEN ); -REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_CONFIG_NPU , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NPU ); -REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_CONFIG_VAS , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_VAS ); -REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_CONFIG_NX , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NX ); -REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_CONFIG_L2L3NCU , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_L2L3NCU ); -REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_RESERVED1 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_RELAXED_SOURCE_RESERVED1_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_CONFIG_PCIE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE ); -REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_CONFIG_PCIE_LEN , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE_LEN ); -REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_CONFIG_NPU , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NPU ); -REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_CONFIG_VAS , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_VAS ); -REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_CONFIG_NX , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NX ); -REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_CONFIG_L2L3NCU , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_L2L3NCU ); -REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_RESERVED1 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_RELAXED_SOURCE_RESERVED1_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_CONFIG_PCIE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE ); -REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_CONFIG_PCIE_LEN , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE_LEN ); -REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_CONFIG_NPU , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NPU ); -REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_CONFIG_VAS , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_VAS ); -REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_CONFIG_NX , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NX ); -REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_CONFIG_L2L3NCU , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_L2L3NCU ); -REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_RESERVED1 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_RELAXED_SOURCE_RESERVED1_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_CONFIG_PCIE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE ); -REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_CONFIG_PCIE_LEN , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE_LEN ); -REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_CONFIG_NPU , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NPU ); -REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_CONFIG_VAS , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_VAS ); -REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_CONFIG_NX , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_NX ); -REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_CONFIG_L2L3NCU , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_CONFIG_L2L3NCU ); -REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_RESERVED1 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_RELAXED_SOURCE_RESERVED1_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_CONFIG_PCIE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE ); -REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_CONFIG_PCIE_LEN , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE_LEN ); -REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_CONFIG_NPU , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NPU ); -REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_CONFIG_VAS , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_VAS ); -REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_CONFIG_NX , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NX ); -REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_CONFIG_L2L3NCU , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_L2L3NCU ); -REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_RESERVED1 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_RELAXED_SOURCE_RESERVED1_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_CONFIG_PCIE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE ); -REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_CONFIG_PCIE_LEN , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE_LEN ); -REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_CONFIG_NPU , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NPU ); -REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_CONFIG_VAS , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_VAS ); -REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_CONFIG_NX , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NX ); -REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_CONFIG_L2L3NCU , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_L2L3NCU ); -REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_RESERVED1 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_RELAXED_SOURCE_RESERVED1_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_CONFIG_PCIE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE ); -REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_CONFIG_PCIE_LEN , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE_LEN ); -REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_CONFIG_NPU , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NPU ); -REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_CONFIG_VAS , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_VAS ); -REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_CONFIG_NX , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NX ); -REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_CONFIG_L2L3NCU , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_L2L3NCU ); -REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_RESERVED1 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_RELAXED_SOURCE_RESERVED1_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_CONFIG_PCIE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE ); -REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_CONFIG_PCIE_LEN , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE_LEN ); -REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_CONFIG_NPU , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NPU ); -REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_CONFIG_VAS , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_VAS ); -REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_CONFIG_NX , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_NX ); -REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_CONFIG_L2L3NCU , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_CONFIG_L2L3NCU ); -REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_RESERVED1 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_RELAXED_SOURCE_RESERVED1_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_CONFIG_PCIE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE ); -REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_CONFIG_PCIE_LEN , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE_LEN ); -REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_CONFIG_NPU , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NPU ); -REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_CONFIG_VAS , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_VAS ); -REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_CONFIG_NX , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NX ); -REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_CONFIG_L2L3NCU , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_L2L3NCU ); -REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_RESERVED1 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_RELAXED_SOURCE_RESERVED1_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); - -REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_CONFIG_PCIE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE ); -REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_CONFIG_PCIE_LEN , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE_LEN ); -REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_CONFIG_NPU , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NPU ); -REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_CONFIG_VAS , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_VAS ); -REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_CONFIG_NX , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_NX ); -REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_CONFIG_L2L3NCU , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_CONFIG_L2L3NCU ); -REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_RESERVED1 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_RELAXED_SOURCE_RESERVED1_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_0 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_1 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_2 , 2 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_2 ); +REG64_FLD( PU_PSU_SBE_DOORBELL_REG_3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_3 ); -REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_CONFIG_PCIE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE ); -REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_CONFIG_PCIE_LEN , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_PCIE_LEN ); -REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_CONFIG_NPU , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NPU ); -REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_CONFIG_VAS , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_VAS ); -REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_CONFIG_NX , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_NX ); -REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_CONFIG_L2L3NCU , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_CONFIG_L2L3NCU ); -REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_RESERVED1 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_RELAXED_SOURCE_RESERVED1_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_REM0_IBUF_WSRC , 17 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IBUF_WSRC ); +REG64_FLD( PU_NPU0_REM0_IBUF_WSRC_LEN , 5 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IBUF_WSRC_LEN ); +REG64_FLD( PU_NPU0_REM0_IBUF_RSRC , 22 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IBUF_RSRC ); +REG64_FLD( PU_NPU0_REM0_IBUF_RSRC_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IBUF_RSRC_LEN ); +REG64_FLD( PU_NPU0_REM0_IBUF_AIDX , 24 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IBUF_AIDX ); +REG64_FLD( PU_NPU0_REM0_IBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IBUF_AIDX_LEN ); +REG64_FLD( PU_NPU0_REM0_IBUF_ABANK , 32 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IBUF_ABANK ); +REG64_FLD( PU_NPU0_REM0_IBUF_ABANK_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_IBUF_ABANK_LEN ); +REG64_FLD( PU_NPU0_REM0_OBUF_WSRC , 34 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_OBUF_WSRC ); +REG64_FLD( PU_NPU0_REM0_OBUF_WSRC_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_OBUF_WSRC_LEN ); +REG64_FLD( PU_NPU0_REM0_OBUF_RSRC , 36 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_OBUF_RSRC ); +REG64_FLD( PU_NPU0_REM0_OBUF_RSRC_LEN , 6 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_OBUF_RSRC_LEN ); +REG64_FLD( PU_NPU0_REM0_OBUF_AIDX , 42 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_OBUF_AIDX ); +REG64_FLD( PU_NPU0_REM0_OBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_OBUF_AIDX_LEN ); +REG64_FLD( PU_NPU0_REM0_OBUF_ABANK , 50 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_OBUF_ABANK ); +REG64_FLD( PU_NPU0_REM0_OBUF_ABANK_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_OBUF_ABANK_LEN ); +REG64_FLD( PU_NPU0_REM0_BBUF_WSRC , 52 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_BBUF_WSRC ); +REG64_FLD( PU_NPU0_REM0_BBUF_WSRC_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_BBUF_WSRC_LEN ); +REG64_FLD( PU_NPU0_REM0_BBUF_RSRC , 54 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_BBUF_RSRC ); +REG64_FLD( PU_NPU0_REM0_BBUF_RSRC_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_BBUF_RSRC_LEN ); +REG64_FLD( PU_NPU0_REM0_BBUF_AIDX , 56 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_BBUF_AIDX ); +REG64_FLD( PU_NPU0_REM0_BBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_BBUF_AIDX_LEN ); + +REG64_FLD( PU_NPU1_REM0_IBUF_WSRC , 17 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IBUF_WSRC ); +REG64_FLD( PU_NPU1_REM0_IBUF_WSRC_LEN , 5 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IBUF_WSRC_LEN ); +REG64_FLD( PU_NPU1_REM0_IBUF_RSRC , 22 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IBUF_RSRC ); +REG64_FLD( PU_NPU1_REM0_IBUF_RSRC_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IBUF_RSRC_LEN ); +REG64_FLD( PU_NPU1_REM0_IBUF_AIDX , 24 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IBUF_AIDX ); +REG64_FLD( PU_NPU1_REM0_IBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IBUF_AIDX_LEN ); +REG64_FLD( PU_NPU1_REM0_IBUF_ABANK , 32 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IBUF_ABANK ); +REG64_FLD( PU_NPU1_REM0_IBUF_ABANK_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_IBUF_ABANK_LEN ); +REG64_FLD( PU_NPU1_REM0_OBUF_WSRC , 34 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_OBUF_WSRC ); +REG64_FLD( PU_NPU1_REM0_OBUF_WSRC_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_OBUF_WSRC_LEN ); +REG64_FLD( PU_NPU1_REM0_OBUF_RSRC , 36 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_OBUF_RSRC ); +REG64_FLD( PU_NPU1_REM0_OBUF_RSRC_LEN , 6 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_OBUF_RSRC_LEN ); +REG64_FLD( PU_NPU1_REM0_OBUF_AIDX , 42 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_OBUF_AIDX ); +REG64_FLD( PU_NPU1_REM0_OBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_OBUF_AIDX_LEN ); +REG64_FLD( PU_NPU1_REM0_OBUF_ABANK , 50 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_OBUF_ABANK ); +REG64_FLD( PU_NPU1_REM0_OBUF_ABANK_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_OBUF_ABANK_LEN ); +REG64_FLD( PU_NPU1_REM0_BBUF_WSRC , 52 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_BBUF_WSRC ); +REG64_FLD( PU_NPU1_REM0_BBUF_WSRC_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_BBUF_WSRC_LEN ); +REG64_FLD( PU_NPU1_REM0_BBUF_RSRC , 54 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_BBUF_RSRC ); +REG64_FLD( PU_NPU1_REM0_BBUF_RSRC_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_BBUF_RSRC_LEN ); +REG64_FLD( PU_NPU1_REM0_BBUF_AIDX , 56 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_BBUF_AIDX ); +REG64_FLD( PU_NPU1_REM0_BBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_BBUF_AIDX_LEN ); + +REG64_FLD( PU_NPU2_REM0_IBUF_WSRC , 17 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IBUF_WSRC ); +REG64_FLD( PU_NPU2_REM0_IBUF_WSRC_LEN , 5 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IBUF_WSRC_LEN ); +REG64_FLD( PU_NPU2_REM0_IBUF_RSRC , 22 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IBUF_RSRC ); +REG64_FLD( PU_NPU2_REM0_IBUF_RSRC_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IBUF_RSRC_LEN ); +REG64_FLD( PU_NPU2_REM0_IBUF_AIDX , 24 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IBUF_AIDX ); +REG64_FLD( PU_NPU2_REM0_IBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IBUF_AIDX_LEN ); +REG64_FLD( PU_NPU2_REM0_IBUF_ABANK , 32 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IBUF_ABANK ); +REG64_FLD( PU_NPU2_REM0_IBUF_ABANK_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_IBUF_ABANK_LEN ); +REG64_FLD( PU_NPU2_REM0_OBUF_WSRC , 34 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_OBUF_WSRC ); +REG64_FLD( PU_NPU2_REM0_OBUF_WSRC_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_OBUF_WSRC_LEN ); +REG64_FLD( PU_NPU2_REM0_OBUF_RSRC , 36 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_OBUF_RSRC ); +REG64_FLD( PU_NPU2_REM0_OBUF_RSRC_LEN , 6 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_OBUF_RSRC_LEN ); +REG64_FLD( PU_NPU2_REM0_OBUF_AIDX , 42 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_OBUF_AIDX ); +REG64_FLD( PU_NPU2_REM0_OBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_OBUF_AIDX_LEN ); +REG64_FLD( PU_NPU2_REM0_OBUF_ABANK , 50 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_OBUF_ABANK ); +REG64_FLD( PU_NPU2_REM0_OBUF_ABANK_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_OBUF_ABANK_LEN ); +REG64_FLD( PU_NPU2_REM0_BBUF_WSRC , 52 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_BBUF_WSRC ); +REG64_FLD( PU_NPU2_REM0_BBUF_WSRC_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_BBUF_WSRC_LEN ); +REG64_FLD( PU_NPU2_REM0_BBUF_RSRC , 54 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_BBUF_RSRC ); +REG64_FLD( PU_NPU2_REM0_BBUF_RSRC_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_BBUF_RSRC_LEN ); +REG64_FLD( PU_NPU2_REM0_BBUF_AIDX , 56 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_BBUF_AIDX ); +REG64_FLD( PU_NPU2_REM0_BBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_BBUF_AIDX_LEN ); + +REG64_FLD( PU_NPU0_REM1_PBRX_RTAG , 34 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_PBRX_RTAG ); +REG64_FLD( PU_NPU0_REM1_PBRX_RTAG_LEN , 22 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_PBRX_RTAG_LEN ); +REG64_FLD( PU_NPU0_REM1_ALU_ADR , 56 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_ALU_ADR ); +REG64_FLD( PU_NPU0_REM1_ALU_ADR_LEN , 3 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_ALU_ADR_LEN ); +REG64_FLD( PU_NPU0_REM1_ALU_TYPE , 59 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_ALU_TYPE ); +REG64_FLD( PU_NPU0_REM1_ALU_TYPE_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_ALU_TYPE_LEN ); +REG64_FLD( PU_NPU0_REM1_ALU_SZ , 63 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , + SH_FLD_ALU_SZ ); + +REG64_FLD( PU_NPU1_REM1_PBRX_RTAG , 34 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_PBRX_RTAG ); +REG64_FLD( PU_NPU1_REM1_PBRX_RTAG_LEN , 22 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_PBRX_RTAG_LEN ); +REG64_FLD( PU_NPU1_REM1_ALU_ADR , 56 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_ALU_ADR ); +REG64_FLD( PU_NPU1_REM1_ALU_ADR_LEN , 3 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_ALU_ADR_LEN ); +REG64_FLD( PU_NPU1_REM1_ALU_TYPE , 59 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_ALU_TYPE ); +REG64_FLD( PU_NPU1_REM1_ALU_TYPE_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_ALU_TYPE_LEN ); +REG64_FLD( PU_NPU1_REM1_ALU_SZ , 63 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , + SH_FLD_ALU_SZ ); + +REG64_FLD( PU_NPU2_REM1_PBRX_RTAG , 34 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_PBRX_RTAG ); +REG64_FLD( PU_NPU2_REM1_PBRX_RTAG_LEN , 22 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_PBRX_RTAG_LEN ); +REG64_FLD( PU_NPU2_REM1_ALU_ADR , 56 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_ALU_ADR ); +REG64_FLD( PU_NPU2_REM1_ALU_ADR_LEN , 3 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_ALU_ADR_LEN ); +REG64_FLD( PU_NPU2_REM1_ALU_TYPE , 59 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_ALU_TYPE ); +REG64_FLD( PU_NPU2_REM1_ALU_TYPE_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_ALU_TYPE_LEN ); +REG64_FLD( PU_NPU2_REM1_ALU_SZ , 63 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , + SH_FLD_ALU_SZ ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_RESID_FE_LEN_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESID_FE_LEN_0 ); @@ -50255,6 +62190,44 @@ REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_PEEK_DATA1_3_LEN , 8 , SH_U REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); +REG64_FLD( PEC_RFIR_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN0 ); +REG64_FLD( PEC_RFIR_LFIR_RECOV_ERR , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LFIR_RECOV_ERR ); +REG64_FLD( PEC_RFIR_IN4 , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN4 ); +REG64_FLD( PEC_RFIR_IN5 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN5 ); +REG64_FLD( PEC_RFIR_IN6 , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN6 ); +REG64_FLD( PEC_RFIR_IN6_LEN , 20 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN6_LEN ); + +REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_ENABLE_LEN ); + +REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_ENABLE_LEN ); + +REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_ENABLE_LEN ); + +REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ENABLE_LEN ); + +REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_ENABLE_LEN ); + REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK0_CLUSTER , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK0_CLUSTER ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK0_CLUSTER_LEN , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , @@ -50420,11 +62393,95 @@ REG64_FLD( PU_RX_PSI_STATUS_SPARE , 10 , SH_UN REG64_FLD( PU_RX_PSI_STATUS_SPARE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); +REG64_FLD( PEC_SCAN_REGION_TYPE_SYSTEM_FAST_INIT , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SYSTEM_FAST_INIT ); +REG64_FLD( PEC_SCAN_REGION_TYPE_VITL , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_VITL ); +REG64_FLD( PEC_SCAN_REGION_TYPE_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PERV ); +REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT1 ); +REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT2 ); +REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT3 ); +REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT4 ); +REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT5 ); +REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT6 ); +REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT7 ); +REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT8 ); +REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT9 ); +REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT10 ); +REG64_FLD( PEC_SCAN_REGION_TYPE_FUNC , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FUNC ); +REG64_FLD( PEC_SCAN_REGION_TYPE_CFG , 49 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CFG ); +REG64_FLD( PEC_SCAN_REGION_TYPE_CCFG_GPTR , 50 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CCFG_GPTR ); +REG64_FLD( PEC_SCAN_REGION_TYPE_REGF , 51 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_REGF ); +REG64_FLD( PEC_SCAN_REGION_TYPE_LBIST , 52 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LBIST ); +REG64_FLD( PEC_SCAN_REGION_TYPE_ABIST , 53 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ABIST ); +REG64_FLD( PEC_SCAN_REGION_TYPE_REPR , 54 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_REPR ); +REG64_FLD( PEC_SCAN_REGION_TYPE_TIME , 55 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TIME ); +REG64_FLD( PEC_SCAN_REGION_TYPE_BNDY , 56 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_BNDY ); +REG64_FLD( PEC_SCAN_REGION_TYPE_FARR , 57 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FARR ); +REG64_FLD( PEC_SCAN_REGION_TYPE_CMSK , 58 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CMSK ); +REG64_FLD( PEC_SCAN_REGION_TYPE_INEX , 59 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_INEX ); + +REG64_FLD( PU_SCOM_PPE_CNTL_IORESET , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IORESET ); +REG64_FLD( PU_SCOM_PPE_CNTL_PDWN , 1 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PDWN ); +REG64_FLD( PU_SCOM_PPE_CNTL_INTERRUPT , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_INTERRUPT ); +REG64_FLD( PU_SCOM_PPE_CNTL_ARB_ECC_INJECT_ERR , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_ARB_ECC_INJECT_ERR ); +REG64_FLD( PU_SCOM_PPE_CNTL_SPARES , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARES ); +REG64_FLD( PU_SCOM_PPE_CNTL_SPARES_LEN , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SPARES_LEN ); + +REG64_FLD( PU_SCOM_PPE_FLAGS_FIELD , 0 , SH_UNT , SH_ACS_SCOM2_CLEAR, + SH_FLD_FIELD ); +REG64_FLD( PU_SCOM_PPE_FLAGS_FIELD_LEN , 16 , SH_UNT , SH_ACS_SCOM2_CLEAR, + SH_FLD_FIELD_LEN ); + +REG64_FLD( PU_SCOM_PPE_WORK_REG1_WORK1 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WORK1 ); +REG64_FLD( PU_SCOM_PPE_WORK_REG1_WORK1_LEN , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WORK1_LEN ); + +REG64_FLD( PU_SCOM_PPE_WORK_REG2_WORK2 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WORK2 ); +REG64_FLD( PU_SCOM_PPE_WORK_REG2_WORK2_LEN , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WORK2_LEN ); + REG64_FLD( PU_NPU0_SCRATCH0_IDIAL , 0 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU0_SCRATCH0_IDIAL_LEN , 64 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); +REG64_FLD( PU_SCRATCH0_SCRATCH_N , 0 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_SCRATCH_N ); +REG64_FLD( PU_SCRATCH0_SCRATCH_N_LEN , 64 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_SCRATCH_N_LEN ); + REG64_FLD( PU_NPU1_SCRATCH0_IDIAL , 0 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU1_SCRATCH0_IDIAL_LEN , 64 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , @@ -50440,6 +62497,11 @@ REG64_FLD( PU_NPU2_NTL0_SCRATCH1_IDIAL , 0 , SH_UN REG64_FLD( PU_NPU2_NTL0_SCRATCH1_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); +REG64_FLD( PU_SCRATCH1_SCRATCH_N , 0 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_SCRATCH_N ); +REG64_FLD( PU_SCRATCH1_SCRATCH_N_LEN , 64 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_SCRATCH_N_LEN ); + REG64_FLD( NV_SCRATCH1_IDIAL , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( NV_SCRATCH1_IDIAL_LEN , 64 , SH_UNT_NV , SH_ACS_SCOM , @@ -50470,6 +62532,11 @@ REG64_FLD( PU_NPU2_NTL0_SCRATCH2_IDIAL , 0 , SH_UN REG64_FLD( PU_NPU2_NTL0_SCRATCH2_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); +REG64_FLD( PU_SCRATCH2_SCRATCH_N , 0 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_SCRATCH_N ); +REG64_FLD( PU_SCRATCH2_SCRATCH_N_LEN , 64 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_SCRATCH_N_LEN ); + REG64_FLD( NV_SCRATCH2_IDIAL , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( NV_SCRATCH2_IDIAL_LEN , 64 , SH_UNT_NV , SH_ACS_SCOM , @@ -50485,6 +62552,11 @@ REG64_FLD( PU_NPU2_NTL0_SCRATCH3_IDIAL , 0 , SH_UN REG64_FLD( PU_NPU2_NTL0_SCRATCH3_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); +REG64_FLD( PU_SCRATCH3_SCRATCH_N , 0 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_SCRATCH_N ); +REG64_FLD( PU_SCRATCH3_SCRATCH_N_LEN , 64 , SH_UNT , SH_ACS_PPE2 , + SH_FLD_SCRATCH_N_LEN ); + REG64_FLD( NV_SCRATCH3_IDIAL , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( NV_SCRATCH3_IDIAL_LEN , 64 , SH_UNT_NV , SH_ACS_SCOM , @@ -50495,6 +62567,31 @@ REG64_FLD( PU_NPU2_NTL1_SCRATCH3_IDIAL , 0 , SH_UN REG64_FLD( PU_NPU2_NTL1_SCRATCH3_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); +REG64_FLD( PU_N3_SECURE_PIB_MASTER_ID_REG_MASTERS , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_MASTERS ); +REG64_FLD( PU_N3_SECURE_PIB_MASTER_ID_REG_MASTERS_LEN , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_MASTERS_LEN ); + +REG64_FLD( PU_N1_SECURE_PIB_MASTER_ID_REG_MASTERS , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_MASTERS ); +REG64_FLD( PU_N1_SECURE_PIB_MASTER_ID_REG_MASTERS_LEN , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_MASTERS_LEN ); + +REG64_FLD( PU_N2_SECURE_PIB_MASTER_ID_REG_MASTERS , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_MASTERS ); +REG64_FLD( PU_N2_SECURE_PIB_MASTER_ID_REG_MASTERS_LEN , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_MASTERS_LEN ); + +REG64_FLD( PEC_SECURE_PIB_MASTER_ID_REG_MASTERS , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASTERS ); +REG64_FLD( PEC_SECURE_PIB_MASTER_ID_REG_MASTERS_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASTERS_LEN ); + +REG64_FLD( PU_N0_SECURE_PIB_MASTER_ID_REG_MASTERS , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_MASTERS ); +REG64_FLD( PU_N0_SECURE_PIB_MASTER_ID_REG_MASTERS_LEN , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_MASTERS_LEN ); + REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SECURE_ACCESS , 0 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_SECURE_ACCESS ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_PRIMARY , 1 , SH_UNT , SH_ACS_SCOM1_CLEAR, @@ -50533,6 +62630,874 @@ REG64_FLD( PU_SEND_WC_BASE_ADDR_BAR , 8 , SH_UN REG64_FLD( PU_SEND_WC_BASE_ADDR_BAR_LEN , 33 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR_LEN ); +REG64_FLD( PEC_SKITTER_CLKSRC_REG_SKITTER0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SKITTER0 ); +REG64_FLD( PEC_SKITTER_CLKSRC_REG_SKITTER0_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SKITTER0_LEN ); + +REG64_FLD( PEC_SKITTER_FORCE_REG_F_READ , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_F_READ ); + +REG64_FLD( PEC_SKITTER_MODE_REG_HOLD_SAMPLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_HOLD_SAMPLE ); +REG64_FLD( PEC_SKITTER_MODE_REG_DISABLE_STICKINESS , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DISABLE_STICKINESS ); +REG64_FLD( PEC_SKITTER_MODE_REG_UNUSED1 , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED1 ); +REG64_FLD( PEC_SKITTER_MODE_REG_UNUSED1_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED1_LEN ); +REG64_FLD( PEC_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_HOLD_DBGTRIG_SEL ); +REG64_FLD( PEC_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_HOLD_DBGTRIG_SEL_LEN ); +REG64_FLD( PEC_SKITTER_MODE_REG_RESET_TRIG_SEL , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_TRIG_SEL ); +REG64_FLD( PEC_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESET_TRIG_SEL_LEN ); +REG64_FLD( PEC_SKITTER_MODE_REG_SAMPLE_GUTS , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SAMPLE_GUTS ); +REG64_FLD( PEC_SKITTER_MODE_REG_SAMPLE_GUTS_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SAMPLE_GUTS_LEN ); +REG64_FLD( PEC_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER , 44 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_HOLD_SAMPLE_WITH_TRIGGER ); +REG64_FLD( PEC_SKITTER_MODE_REG_DATA_V_LT , 45 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DATA_V_LT ); + +REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK ); +REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CFG_DISABLE_MALF_PULSE_GEN ); +REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP ); +REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK ); +REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CFG_DISABLE_HEARTBEAT ); +REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CFG_DISABLE_FORCE_TO_ZERO ); +REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_PM_DISABLE , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CFG_PM_DISABLE ); +REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CFG_PM_MUX_DISABLE ); +REG64_FLD( PEC_SLAVE_CONFIG_REG_ERROR_MASK , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ERROR_MASK ); +REG64_FLD( PEC_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ERROR_MASK_LEN ); + +REG64_FLD( PU_NPU0_SM0_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CREQ0 ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_PRB0 ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CREQ1 ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_PRB1 ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_XATS ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_PWR0 ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_PWR1 ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_CHGRATE ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_N0REQ ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_N0DGD ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_N1REQ ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_N1DGD ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_ATSXLATE ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_PBRSP ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_N0RSP ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_N1RSP ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_XARSP ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_SACOLL ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_FREE ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM0_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU1_SM2_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CREQ0 ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_PRB0 ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CREQ1 ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_PRB1 ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_XATS ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_PWR0 ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_PWR1 ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_CHGRATE ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_N0REQ ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_N0DGD ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_N1REQ ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_N1DGD ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_ATSXLATE ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_PBRSP ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_N0RSP ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_N1RSP ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_XARSP ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_SACOLL ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_FREE ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM2_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU2_SM3_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CREQ0 ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_PRB0 ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CREQ1 ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_PRB1 ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_XATS ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_PWR0 ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_PWR1 ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_CHGRATE ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_N0REQ ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_N0DGD ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_N1REQ ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_N1DGD ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_ATSXLATE ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_PBRSP ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_N0RSP ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_N1RSP ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_XARSP ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_SACOLL ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_FREE ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM3_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU1_SM3_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CREQ0 ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_PRB0 ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CREQ1 ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_PRB1 ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_XATS ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_PWR0 ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_PWR1 ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_CHGRATE ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_N0REQ ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_N0DGD ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_N1REQ ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_N1DGD ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_ATSXLATE ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_PBRSP ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_N0RSP ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_N1RSP ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_XARSP ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_SACOLL ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_FREE ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM3_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU0_SM3_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CREQ0 ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_PRB0 ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CREQ1 ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_PRB1 ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_XATS ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_PWR0 ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_PWR1 ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_CHGRATE ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_N0REQ ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_N0DGD ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_N1REQ ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_N1DGD ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_ATSXLATE ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_PBRSP ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_N0RSP ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_N1RSP ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_XARSP ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_SACOLL ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_FREE ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM3_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU1_SM1_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CREQ0 ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_PRB0 ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CREQ1 ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_PRB1 ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_XATS ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_PWR0 ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_PWR1 ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_CHGRATE ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_N0REQ ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_N0DGD ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_N1REQ ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_N1DGD ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_ATSXLATE ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_PBRSP ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_N0RSP ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_N1RSP ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_XARSP ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_SACOLL ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_FREE ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM1_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU2_SM2_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CREQ0 ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_PRB0 ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CREQ1 ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_PRB1 ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_XATS ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_PWR0 ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_PWR1 ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_CHGRATE ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_N0REQ ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_N0DGD ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_N1REQ ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_N1DGD ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_ATSXLATE ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_PBRSP ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_N0RSP ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_N1RSP ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_XARSP ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_SACOLL ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_FREE ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM2_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU2_SM1_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CREQ0 ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_PRB0 ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CREQ1 ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_PRB1 ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_XATS ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_PWR0 ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_PWR1 ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_CHGRATE ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_N0REQ ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_N0DGD ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_N1REQ ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_N1DGD ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_ATSXLATE ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_PBRSP ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_N0RSP ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_N1RSP ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_XARSP ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_SACOLL ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_FREE ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM1_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU0_SM2_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CREQ0 ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_PRB0 ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CREQ1 ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_PRB1 ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_XATS ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_PWR0 ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_PWR1 ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_CHGRATE ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_N0REQ ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_N0DGD ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_N1REQ ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_N1DGD ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_ATSXLATE ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_PBRSP ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_N0RSP ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_N1RSP ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_XARSP ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_SACOLL ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_FREE ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM2_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU2_SM0_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CREQ0 ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_PRB0 ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CREQ1 ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_PRB1 ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_XATS ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_PWR0 ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_PWR1 ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_CHGRATE ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_N0REQ ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_N0DGD ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_N1REQ ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_N1DGD ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_ATSXLATE ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_PBRSP ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_N0RSP ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_N1RSP ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_XARSP ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_SACOLL ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_FREE ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU2_SM0_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU0_SM1_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CREQ0 ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_PRB0 ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CREQ1 ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_PRB1 ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_XATS ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_PWR0 ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_PWR1 ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_CHGRATE ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_N0REQ ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_N0DGD ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_N1REQ ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_N1DGD ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_ATSXLATE ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_PBRSP ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_N0RSP ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_N1RSP ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_XARSP ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_SACOLL ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_FREE ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU0_SM1_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PU_NPU1_SM0_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CREQ0 ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_PRB0 ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CREQ1 ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_PRB1 ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_XATS ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_PWR0 ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_PWR1 ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_CHGRATE ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MRBGP ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MRBGP_LEN ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MRBSP ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MRBSP_LEN ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_FENCE0 ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE0_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_FENCE0_LEN ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE1 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_FENCE1 ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE1_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_FENCE1_LEN ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBLN , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_PBLN ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBNNG , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_PBNNG ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBRNVG , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_PBRNVG ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0REQ , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_N0REQ ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0DGD , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_N0DGD ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1REQ , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_N1REQ ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1DGD , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_N1DGD ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_MMIO , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_MMIO ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_ATSXLATE , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_ATSXLATE ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBRSP , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_PBRSP ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0RSP , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_N0RSP ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1RSP , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_N1RSP ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_XARSP , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_XARSP ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_SACOLL , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_SACOLL ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_FREE , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_FREE ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_RESERVED1 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1 ); +REG64_FLD( PU_NPU1_SM0_SM_STATUS_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_RESERVED1_LEN ); + +REG64_FLD( PEC_SPATTN_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM2_NC , + SH_FLD_IN ); +REG64_FLD( PEC_SPATTN_IN_LEN , 10 , SH_UNT_PEC , SH_ACS_SCOM2_NC , + SH_FLD_IN_LEN ); + +REG64_FLD( PEC_SPA_MASK_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN ); +REG64_FLD( PEC_SPA_MASK_IN_LEN , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN_LEN ); + REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_FRAME_SIZE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_FRAME_SIZE ); REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_FRAME_SIZE_LEN , 6 , SH_UNT , SH_ACS_SCOM , @@ -50770,7 +63735,7 @@ REG64_FLD( PU_SRAM_SRCHSW_CHKSW_SO_SPARE_LEN , 2 , SH_UN REG64_FLD( PU_SRAM_SREAR_ERROR_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_ADDRESS ); -REG64_FLD( PU_SRAM_SREAR_ERROR_ADDRESS_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_SRAM_SREAR_ERROR_ADDRESS_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_ADDRESS_LEN ); REG64_FLD( PU_SRAM_SRMAP_REMAP_SOURCE , 0 , SH_UNT , SH_ACS_SCOM_RW , @@ -50803,47 +63768,47 @@ REG64_FLD( PU_SRAM_SRMR_SPARE , 11 , SH_UN REG64_FLD( PU_SRAM_SRMR_SPARE_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_LEN ); -REG32_FLD( PU_STATUS_REGISTER_ADDR_NVLD , 0 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_ADDR_NVLD , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_NVLD ); -REG32_FLD( PU_STATUS_REGISTER_WRITE_NVLD , 1 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_WRITE_NVLD , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRITE_NVLD ); -REG32_FLD( PU_STATUS_REGISTER_READ_NVLD , 2 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_READ_NVLD , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_READ_NVLD ); -REG32_FLD( PU_STATUS_REGISTER_INVLD_CMD_ERR , 3 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_INVLD_CMD_ERR , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVLD_CMD_ERR ); -REG32_FLD( PU_STATUS_REGISTER_CORR_ERR , 4 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_CORR_ERR , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CORR_ERR ); -REG32_FLD( PU_STATUS_REGISTER_UNCORR_ERROR , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_UNCORR_ERROR , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNCORR_ERROR ); -REG32_FLD( PU_STATUS_REGISTER_DATA_REG_0_31 , 6 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_DATA_REG_0_31 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_REG_0_31 ); -REG32_FLD( PU_STATUS_REGISTER_DATA_REG_0_31_LEN , 32 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_DATA_REG_0_31_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_REG_0_31_LEN ); -REG32_FLD( PU_STATUS_REGISTER_UNUSED_39_43 , 39 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_UNUSED_39_43 , 39 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_39_43 ); -REG32_FLD( PU_STATUS_REGISTER_UNUSED_39_43_LEN , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_UNUSED_39_43_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_39_43_LEN ); -REG32_FLD( PU_STATUS_REGISTER_CTRL_BUSY , 44 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_CTRL_BUSY , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_CTRL_BUSY ); -REG32_FLD( PU_STATUS_REGISTER_DCOMP_ERR , 45 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_DCOMP_ERR , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_DCOMP_ERR ); -REG32_FLD( PU_STATUS_REGISTER_INVLD_PRGM_ERR , 46 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_INVLD_PRGM_ERR , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVLD_PRGM_ERR ); -REG32_FLD( PU_STATUS_REGISTER_UNUSED_47_51 , 47 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_UNUSED_47_51 , 47 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_47_51 ); -REG32_FLD( PU_STATUS_REGISTER_UNUSED_47_51_LEN , 5 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_UNUSED_47_51_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_47_51_LEN ); -REG32_FLD( PU_STATUS_REGISTER_COMMAND_COMPLETE , 52 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_COMMAND_COMPLETE , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_COMMAND_COMPLETE ); -REG32_FLD( PU_STATUS_REGISTER_UNUSED_53 , 53 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_UNUSED_53 , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_53 ); -REG32_FLD( PU_STATUS_REGISTER_RDWR_OP_BUSY , 54 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_RDWR_OP_BUSY , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDWR_OP_BUSY ); -REG32_FLD( PU_STATUS_REGISTER_DCOMP_ENGINE_BUSY , 55 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_DCOMP_ENGINE_BUSY , 55 , SH_UNT , SH_ACS_SCOM , SH_FLD_DCOMP_ENGINE_BUSY ); -REG32_FLD( PU_STATUS_REGISTER_RD_DATA_COUNT , 56 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_RD_DATA_COUNT , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_RD_DATA_COUNT ); -REG32_FLD( PU_STATUS_REGISTER_RD_DATA_COUNT_LEN , 8 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_STATUS_REGISTER_RD_DATA_COUNT_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_RD_DATA_COUNT_LEN ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_ADDR_NVLD_0 , 0 , SH_UNT , SH_ACS_SCOM , @@ -51080,6 +64045,10 @@ REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_PEEK_DATA1_0_LEN , 8 , SH_UN SH_FLD_PEEK_DATA1_0_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_LBUS_PARITY_ERR1_0 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_0 ); +REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_I2CM_STEERED_INTERRUPTS_0 , 44 , SH_UNT , SH_ACS_SCOM , + SH_FLD_I2CM_STEERED_INTERRUPTS_0 ); +REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_I2CM_STEERED_INTERRUPTS_0_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_I2CM_STEERED_INTERRUPTS_0_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_INVALID_CMD_1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVALID_CMD_1 ); @@ -51111,6 +64080,10 @@ REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_PEEK_DATA1_1_LEN , 8 , SH_UN SH_FLD_PEEK_DATA1_1_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_LBUS_PARITY_ERR1_1 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_1 ); +REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_I2CM_STEERED_INTERRUPTS_1 , 44 , SH_UNT , SH_ACS_SCOM , + SH_FLD_I2CM_STEERED_INTERRUPTS_1 ); +REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_I2CM_STEERED_INTERRUPTS_1_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_I2CM_STEERED_INTERRUPTS_1_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_INVALID_CMD_2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVALID_CMD_2 ); @@ -51142,6 +64115,10 @@ REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_PEEK_DATA1_2_LEN , 8 , SH_UN SH_FLD_PEEK_DATA1_2_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_LBUS_PARITY_ERR1_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_2 ); +REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_I2CM_STEERED_INTERRUPTS_2 , 44 , SH_UNT , SH_ACS_SCOM , + SH_FLD_I2CM_STEERED_INTERRUPTS_2 ); +REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_I2CM_STEERED_INTERRUPTS_2_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_I2CM_STEERED_INTERRUPTS_2_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_INVALID_CMD_3 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVALID_CMD_3 ); @@ -51173,6 +64150,21 @@ REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_PEEK_DATA1_3_LEN , 8 , SH_UN SH_FLD_PEEK_DATA1_3_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); +REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_I2CM_STEERED_INTERRUPTS_3 , 44 , SH_UNT , SH_ACS_SCOM , + SH_FLD_I2CM_STEERED_INTERRUPTS_3 ); +REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_I2CM_STEERED_INTERRUPTS_3_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_I2CM_STEERED_INTERRUPTS_3_LEN ); + +REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SMASK_IN0 ); +REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SMASK_IN1 ); +REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SMASK_IN2 ); +REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SMASK_IN3 ); +REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SMASK_IN4 ); REG64_FLD( PU_SU_CRB_KILL_REQ_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE ); @@ -51204,7 +64196,7 @@ REG64_FLD( PU_SU_DMA_ERROR_REPORT_0_0_LEN , 64 , SH_UN REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_1 ); -REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1_LEN , 7 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1_LEN , 17 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_1_LEN ); REG64_FLD( PU_SU_ENGINE_ENABLE_ALLOW_CRYPTO , 0 , SH_UNT , SH_ACS_SCOM , @@ -51222,7 +64214,7 @@ REG64_FLD( PU_SU_ENGINE_ENABLE_CH0_EFT , 63 , SH_UN REG64_FLD( PU_SU_ERAT_ERROR_RPT_RPT , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RPT ); -REG64_FLD( PU_SU_ERAT_ERROR_RPT_RPT_LEN , 46 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_SU_ERAT_ERROR_RPT_RPT_LEN , 47 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RPT_LEN ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIPCOMP_MAX_INRD , 8 , SH_UNT , SH_ACS_SCOM_RW , @@ -51337,12 +64329,12 @@ REG64_FLD( PU_SU_STATUS_DMA_CH4_IDLE , 60 , SH_UN REG64_FLD( PU_SU_UMAC_ERROR_RPT_RPT , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RPT ); -REG64_FLD( PU_SU_UMAC_ERROR_RPT_RPT_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_SU_UMAC_ERROR_RPT_RPT_LEN , 56 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RPT_LEN ); REG64_FLD( PU_SU_UMAC_ERROR_RPT1_RPT1 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RPT1 ); -REG64_FLD( PU_SU_UMAC_ERROR_RPT1_RPT1_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_SU_UMAC_ERROR_RPT1_RPT1_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RPT1_LEN ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID , 4 , SH_UNT , SH_ACS_SCOM , @@ -51428,6 +64420,29 @@ REG64_FLD( PU_SYM_MAX_BYTE_CNT_TARGET_DDE , 13 , SH_UN REG64_FLD( PU_SYM_MAX_BYTE_CNT_TARGET_DDE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TARGET_DDE_LEN ); +REG64_FLD( PEC_SYNC_CONFIG_PULSE_DELAY , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PULSE_DELAY ); +REG64_FLD( PEC_SYNC_CONFIG_PULSE_DELAY_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PULSE_DELAY_LEN ); +REG64_FLD( PEC_SYNC_CONFIG_LISTEN_TO_PULSE_DIS , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_LISTEN_TO_PULSE_DIS ); +REG64_FLD( PEC_SYNC_CONFIG_PULSE_INPUT_SEL , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PULSE_INPUT_SEL ); +REG64_FLD( PEC_SYNC_CONFIG_USE_FOR_SCAN , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_USE_FOR_SCAN ); +REG64_FLD( PEC_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CLEAR_CHIPLET_IS_ALIGNED ); +REG64_FLD( PEC_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT_REGION_CLKCMD_ENABLE ); +REG64_FLD( PEC_SYNC_CONFIG_DISABLE_PCB_ITR , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DISABLE_PCB_ITR ); +REG64_FLD( PEC_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_ENABLE_VITL_ALIGN_CHECK ); +REG64_FLD( PEC_SYNC_CONFIG_UNUSED1119 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED1119 ); +REG64_FLD( PEC_SYNC_CONFIG_UNUSED1119_LEN , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED1119_LEN ); + REG64_FLD( PU_SYNC_FIR_ACTION0_REG_INVALID_TRANSFER_SIZE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INVALID_TRANSFER_SIZE ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_INVALID_COMMAND , 1 , SH_UNT , SH_ACS_SCOM_RO , @@ -51541,6 +64556,3358 @@ REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ADDRESS , 15 , SH_UN REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ADDRESS_LEN , 37 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_INVALIDATE_ADDRESS_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_PEC , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PU_NPU_SM2_TEST_CERR_ATR_ERR_INJ_PEND , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATR_ERR_INJ_PEND ); +REG64_FLD( PU_NPU_SM2_TEST_CERR_MAP_ERR_INJ_PEND , 1 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_MAP_ERR_INJ_PEND ); REG64_FLD( PU_NPU_SM2_TEST_CERR_REGSEL , 56 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_REGSEL ); REG64_FLD( PU_NPU_SM2_TEST_CERR_REGSEL_LEN , 2 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , @@ -51550,32 +67917,74 @@ REG64_FLD( PU_NPU_SM2_TEST_CERR_BITSEL , 58 , SH_UN REG64_FLD( PU_NPU_SM2_TEST_CERR_BITSEL_LEN , 6 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BITSEL_LEN ); -REG64_FLD( PU_NPU0_TEST_CERR_REGSEL , 56 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_REGSEL ); -REG64_FLD( PU_NPU0_TEST_CERR_REGSEL_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_REGSEL_LEN ); -REG64_FLD( PU_NPU0_TEST_CERR_BITSEL , 58 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_BITSEL ); -REG64_FLD( PU_NPU0_TEST_CERR_BITSEL_LEN , 6 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , - SH_FLD_BITSEL_LEN ); - -REG64_FLD( PU_NPU1_TEST_CERR_REGSEL , 56 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_REGSEL ); -REG64_FLD( PU_NPU1_TEST_CERR_REGSEL_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_REGSEL_LEN ); -REG64_FLD( PU_NPU1_TEST_CERR_BITSEL , 58 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_BITSEL ); -REG64_FLD( PU_NPU1_TEST_CERR_BITSEL_LEN , 6 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , - SH_FLD_BITSEL_LEN ); - -REG64_FLD( PU_NPU2_TEST_CERR_REGSEL , 56 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_REGSEL ); -REG64_FLD( PU_NPU2_TEST_CERR_REGSEL_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_REGSEL_LEN ); -REG64_FLD( PU_NPU2_TEST_CERR_BITSEL , 58 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_BITSEL ); -REG64_FLD( PU_NPU2_TEST_CERR_BITSEL_LEN , 6 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , - SH_FLD_BITSEL_LEN ); +REG64_FLD( CAPP_TFMR_CHIP_TOD_STATUS , 47 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CHIP_TOD_STATUS ); +REG64_FLD( CAPP_TFMR_CHIP_TOD_STATUS_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CHIP_TOD_STATUS_LEN ); + +REG64_FLD( PEC_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DIS_CPM_BUBBLE_CORR ); +REG64_FLD( PEC_THERM_MODE_REG_FORCE_THRES_ACT , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_FORCE_THRES_ACT ); +REG64_FLD( PEC_THERM_MODE_REG_THRES_TRIP_ENA , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_THRES_TRIP_ENA ); +REG64_FLD( PEC_THERM_MODE_REG_THRES_TRIP_ENA_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_THRES_TRIP_ENA_LEN ); +REG64_FLD( PEC_THERM_MODE_REG_DTS_SAMPLE_ENA , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DTS_SAMPLE_ENA ); +REG64_FLD( PEC_THERM_MODE_REG_SAMPLE_PULSE_CNT , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SAMPLE_PULSE_CNT ); +REG64_FLD( PEC_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_SAMPLE_PULSE_CNT_LEN ); +REG64_FLD( PEC_THERM_MODE_REG_THRES_ENA , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_THRES_ENA ); +REG64_FLD( PEC_THERM_MODE_REG_THRES_ENA_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_THRES_ENA_LEN ); +REG64_FLD( PEC_THERM_MODE_REG_DTS_TRIGGER , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DTS_TRIGGER ); +REG64_FLD( PEC_THERM_MODE_REG_DTS_TRIGGER_SEL , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DTS_TRIGGER_SEL ); +REG64_FLD( PEC_THERM_MODE_REG_THRES_OVERFLOW_MASK , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_THRES_OVERFLOW_MASK ); +REG64_FLD( PEC_THERM_MODE_REG_UNUSED , 15 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PEC_THERM_MODE_REG_DTS_READ_SEL , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DTS_READ_SEL ); +REG64_FLD( PEC_THERM_MODE_REG_DTS_READ_SEL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DTS_READ_SEL_LEN ); +REG64_FLD( PEC_THERM_MODE_REG_DTS_ENABLE_L1 , 20 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DTS_ENABLE_L1 ); +REG64_FLD( PEC_THERM_MODE_REG_DTS_ENABLE_L1_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_DTS_ENABLE_L1_LEN ); + +REG64_FLD( PEC_TIMESTAMP_COUNTER_READ_VALUE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_VALUE ); +REG64_FLD( PEC_TIMESTAMP_COUNTER_READ_VALUE_LEN , 44 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_VALUE_LEN ); +REG64_FLD( PEC_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR , 44 , SH_UNT_PEC , SH_ACS_SCOM_RO , + SH_FLD_OVERFLOW_ERR ); + +REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_TIMEOUT , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_IN_TIMEOUT ); +REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SEQ_ERR , 1 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_IN_SEQ_ERR ); +REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SEQ_PERR , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_IN_SEQ_PERR ); +REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_BAD_OP_ERR , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_IN_BAD_OP_ERR ); +REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SNP_ADDR_PERR , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_IN_SNP_ADDR_PERR ); +REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SNP_TTAG_PERR , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_IN_SNP_TTAG_PERR ); + +REG64_FLD( CAPP_TOD_SYNC000_TIMEBASE , 55 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TIMEBASE ); +REG64_FLD( CAPP_TOD_SYNC000_TIMEBASE_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TIMEBASE_LEN ); +REG64_FLD( CAPP_TOD_SYNC000_CHIP_STATUS , 60 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CHIP_STATUS ); +REG64_FLD( CAPP_TOD_SYNC000_CHIP_STATUS_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( PU_TRUST_CONTROL_FSP_TCE_ENABLE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_FSP_TCE_ENABLE ); @@ -51763,12 +68172,95 @@ REG64_FLD( PU_VAS_BUFCTL_CONSUMED_BUF_COUNT , 57 , SH_UN REG64_FLD( PU_VAS_BUFCTL_CONSUMED_BUF_COUNT_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CONSUMED_BUF_COUNT_LEN ); +REG64_FLD( PU_VAS_CAMDATA0_CAM_DISPLAY_REG_0 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_CAM_DISPLAY_REG_0 ); +REG64_FLD( PU_VAS_CAMDATA0_CAM_DISPLAY_REG_0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_CAM_DISPLAY_REG_0_LEN ); + +REG64_FLD( PU_VAS_CAMDATA1_CAM_DISPLAY_REG_1 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_CAM_DISPLAY_REG_1 ); +REG64_FLD( PU_VAS_CAMDATA1_CAM_DISPLAY_REG_1_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_CAM_DISPLAY_REG_1_LEN ); + REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_RESET ); -REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BITS , 4 , SH_UNT , SH_ACS_SCOM , - SH_FLD_CQ_CERR_BITS ); -REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BITS_LEN , 20 , SH_UNT , SH_ACS_SCOM , - SH_FLD_CQ_CERR_BITS_LEN ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT4 , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT4 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT5 , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT5 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT6 , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT6 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT7 , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT7 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT8 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT8 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT9 , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT9 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT10 , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT10 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT11 , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT11 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT12 , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT12 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT13 , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT13 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT14 , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT14 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT15 , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT15 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT16 , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT16 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT17 , 17 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT17 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT18 , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT18 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT19 , 19 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT19 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT20 , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT20 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT21 , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT21 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT22 , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT22 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT23 , 23 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT23 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT24 , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT24 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT25 , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT25 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT26 , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT26 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT27 , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT27 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT28 , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT28 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT29 , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT29 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT30 , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT30 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT31 , 31 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT31 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT32 , 32 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT32 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT33 , 33 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT33 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT34 , 34 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT34 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT35 , 35 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT35 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT36 , 36 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT36 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT37 , 37 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT37 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT38 , 38 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT38 ); +REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT39 , 39 , SH_UNT , SH_ACS_SCOM , + SH_FLD_CQ_CERR_BIT39 ); + +REG64_FLD( PU_VAS_DBGCONT_TRACE_BUS_BITS_0_63 , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TRACE_BUS_BITS_0_63 ); +REG64_FLD( PU_VAS_DBGCONT_TRACE_BUS_BITS_0_63_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_TRACE_BUS_BITS_0_63_LEN ); REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_LO , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SEL_RG_TRACE_DATA_LO ); @@ -51822,18 +68314,16 @@ REG64_FLD( PU_VAS_DBGNORTH_ENABLE_IN_TRACE , 32 , SH_UN SH_FLD_ENABLE_IN_TRACE ); REG64_FLD( PU_VAS_DBGNORTH_ENABLE_RG_TRACE , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_RG_TRACE ); -REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_PMU_DATA_LO , 36 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_SEL_RG_PMU_DATA_LO ); -REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_PMU_DATA_LO_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_SEL_RG_PMU_DATA_LO_LEN ); -REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_PMU_DATA_HI , 38 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_SEL_RG_PMU_DATA_HI ); -REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_PMU_DATA_HI_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_SEL_RG_PMU_DATA_HI_LEN ); +REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_PMU_DATA , 36 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_SEL_RG_PMU_DATA ); REG64_FLD( PU_VAS_DBGNORTH_ENABLE_IN_PMU_COUNTING , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_IN_PMU_COUNTING ); REG64_FLD( PU_VAS_DBGNORTH_ENABLE_RG_PMU_COUNTING , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_RG_PMU_COUNTING ); +REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_INT_DATA_LO , 42 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IN_TRACE_INT_DATA_LO ); +REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_INT_DATA_HI , 43 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_IN_TRACE_INT_DATA_HI ); REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_DATA_LO , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PASS_WC_INT_TRACE_DATA_LO ); @@ -51853,19 +68343,19 @@ REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_TRIG_23 , 7 , SH_UN SH_FLD_PASS_CQ_INT_TRACE_TRIG_23 ); REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_LO , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_GROUP_SEL_LO ); -REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_LO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_LO_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_GROUP_SEL_LO_LEN ); -REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_HI , 11 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_HI , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_GROUP_SEL_HI ); -REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_HI_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_HI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_GROUP_SEL_HI_LEN ); -REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_01 , 14 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_01 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_TRIGGER_SEL_01 ); -REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_01_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_TRIGGER_SEL_01_LEN ); -REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_23 , 17 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_23 , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_TRIGGER_SEL_23 ); -REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_23_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_23_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_TRIGGER_SEL_23_LEN ); REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_LO , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_TRACE_GROUP_SEL_LO ); @@ -51905,20 +68395,24 @@ REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_WC_TRACE , 45 , SH_UN SH_FLD_ENABLE_WC_TRACE ); REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_CQ_TRACE , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_CQ_TRACE ); -REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_PMU_DATA_LO , 48 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_PASS_WC_INT_PMU_DATA_LO ); -REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_PMU_DATA_HI , 49 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_PASS_WC_INT_PMU_DATA_HI ); +REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_INT_DATA_LO , 47 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WC_TRACE_INT_DATA_LO ); +REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_INT_DATA_HI , 48 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WC_TRACE_INT_DATA_HI ); +REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_INT_DATA_LO , 49 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EG_TRACE_INT_DATA_LO ); REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_PMU_DATA_LO , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PASS_CQ_INT_PMU_DATA_LO ); REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_PMU_DATA_HI , 51 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PASS_CQ_INT_PMU_DATA_HI ); REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_EG_PMU_COUNTING , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_EG_PMU_COUNTING ); -REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_WC_PMU_COUNTING , 53 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_ENABLE_WC_PMU_COUNTING ); +REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_INT_DATA_HI , 53 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_EG_TRACE_INT_DATA_HI ); REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_CQ_PMU_COUNTING , 54 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_CQ_PMU_COUNTING ); +REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_INT_DATA_LO , 55 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_CQ_TRACE_INT_DATA_LO ); REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_BITS_64_87 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TRACE_BUS_BITS_64_87 ); @@ -51926,15 +68420,31 @@ REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_BITS_64_87_LEN , 24 , SH_UN SH_FLD_TRACE_BUS_BITS_64_87_LEN ); REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_TRIGGER_BITS , 24 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TRACE_BUS_TRIGGER_BITS ); -REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_TRIGGER_BITS_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , +REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_TRIGGER_BITS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TRACE_BUS_TRIGGER_BITS_LEN ); REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_EG_CERR_RESET ); -REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BITS , 4 , SH_UNT , SH_ACS_SCOM , - SH_FLD_EG_CERR_BITS ); -REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BITS_LEN , 20 , SH_UNT , SH_ACS_SCOM , - SH_FLD_EG_CERR_BITS_LEN ); +REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT4 , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EG_CERR_BIT4 ); +REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT5 , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EG_CERR_BIT5 ); +REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT6 , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EG_CERR_BIT6 ); +REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT7 , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EG_CERR_BIT7 ); +REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT8 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EG_CERR_BIT8 ); +REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT9 , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EG_CERR_BIT9 ); +REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT10 , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EG_CERR_BIT10 ); +REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT11 , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EG_CERR_BIT11 ); +REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_UNUSEDBITS , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EG_CERR_UNUSEDBITS ); +REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_UNUSEDBITS_LEN , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_EG_CERR_UNUSEDBITS_LEN ); REG64_FLD( PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_ENA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_NORTH_WC_ENA ); @@ -51944,6 +68454,8 @@ REG64_FLD( PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_FRQ , 2 , SH_UN SH_FLD_ECC_ERR_INJ_NORTH_WC_FRQ ); REG64_FLD( PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_UNUSED , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED ); +REG64_FLD( PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_UNUSED_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED_LEN ); REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_ENA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SOUTH_WC_ENA ); @@ -51963,6 +68475,10 @@ REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_FRQ , 7 , SH_UN SH_FLD_ECC_ERR_INJ_SOUTH_EG_FRQ ); REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_SEL , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SOUTH_EG_SEL ); +REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_UNUSED , 9 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ECC_ERR_INJ_SOUTH_UNUSED ); +REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_UNUSED_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_ECC_ERR_INJ_SOUTH_UNUSED_LEN ); REG64_FLD( PU_VAS_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); @@ -52072,6 +68588,10 @@ REG64_FLD( PU_VAS_FIR_MASK_REG_NX_LOCAL_XSTOP , 48 , SH_UN SH_FLD_NX_LOCAL_XSTOP ); REG64_FLD( PU_VAS_FIR_MASK_REG_SCOM_MMIO_ADDR_ERR , 49 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_MMIO_ADDR_ERR ); +REG64_FLD( PU_VAS_FIR_MASK_REG_UNUSED50 , 50 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED50 ); +REG64_FLD( PU_VAS_FIR_MASK_REG_UNUSED51 , 51 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED51 ); REG64_FLD( PU_VAS_FIR_REG_EG_LOGIC_HW_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EG_LOGIC_HW_ERROR ); @@ -52171,6 +68691,10 @@ REG64_FLD( PU_VAS_FIR_REG_NX_LOCAL_XSTOP , 48 , SH_UN SH_FLD_NX_LOCAL_XSTOP ); REG64_FLD( PU_VAS_FIR_REG_SCOM_MMIO_ADDR_ERR , 49 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_MMIO_ADDR_ERR ); +REG64_FLD( PU_VAS_FIR_REG_UNUSED50 , 50 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED50 ); +REG64_FLD( PU_VAS_FIR_REG_UNUSED51 , 51 , SH_UNT , SH_ACS_SCOM2_OR , + SH_FLD_UNUSED51 ); REG64_FLD( PU_VAS_FIR_WOF_REG_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF ); @@ -52179,10 +68703,62 @@ REG64_FLD( PU_VAS_FIR_WOF_REG_WOF_LEN , 52 , SH_UN REG64_FLD( PU_VAS_INERRRPT_IN_CERR_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_RESET ); -REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BITS , 4 , SH_UNT , SH_ACS_SCOM , - SH_FLD_IN_CERR_BITS ); -REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BITS_LEN , 20 , SH_UNT , SH_ACS_SCOM , - SH_FLD_IN_CERR_BITS_LEN ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT4 , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT4 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT5 , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT5 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT6 , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT6 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT7 , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT7 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT8 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT8 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT9 , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT9 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT10 , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT10 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT11 , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT11 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT12 , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT12 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT13 , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT13 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT14 , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT14 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT15 , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT15 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT16 , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT16 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT17 , 17 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT17 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT18 , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT18 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT19 , 19 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT19 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT20 , 20 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT20 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT21 , 21 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT21 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT22 , 22 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT22 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT23 , 23 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT23 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT24 , 24 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT24 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT25 , 25 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT25 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT26 , 26 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT26 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT27 , 27 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT27 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT28 , 28 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT28 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT29 , 29 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_BIT29 ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_UNUSED_BITS , 30 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_UNUSED_BITS ); +REG64_FLD( PU_VAS_INERRRPT_IN_CERR_UNUSED_BITS_LEN , 2 , SH_UNT , SH_ACS_SCOM , + SH_FLD_IN_CERR_UNUSED_BITS_LEN ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_4VS64 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_4VS64 ); @@ -52190,6 +68766,14 @@ REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_ACCEPT_PASTE , 1 , SH_UN SH_FLD_MISC_CTL_ACCEPT_PASTE ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_ENABLE_WRMON , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_ENABLE_WRMON ); +REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_DISABLE_PUSH2MEM_LIMIT , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MISC_CTL_DISABLE_PUSH2MEM_LIMIT ); +REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_QUIESCE_REQUEST , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MISC_CTL_QUIESCE_REQUEST ); +REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MISC_CTL_UNUSED_BITS ); +REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS_LEN , 3 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MISC_CTL_UNUSED_BITS_LEN ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_INVALIDATE_CAM_LOC , 47 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_INVALIDATE_CAM_LOC ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_INVALIDATE_CAM_ALL , 48 , SH_UNT , SH_ACS_SCOM , @@ -52198,16 +68782,14 @@ REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_CAM_LOCATION , 49 , SH_UN SH_FLD_MISC_CTL_CAM_LOCATION ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_CAM_LOCATION_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_CAM_LOCATION_LEN ); +REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_CAM_INVAL_DONE , 56 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MISC_CTL_CAM_INVAL_DONE ); +REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS2 , 57 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MISC_CTL_UNUSED_BITS2 ); +REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_HMI_ACTIVE , 58 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MISC_CTL_HMI_ACTIVE ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_RG_IS_IDLE , 59 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_RG_IS_IDLE ); -REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_IN_IS_IDLE , 60 , SH_UNT , SH_ACS_SCOM , - SH_FLD_MISC_CTL_IN_IS_IDLE ); -REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_WC_IS_IDLE , 61 , SH_UNT , SH_ACS_SCOM , - SH_FLD_MISC_CTL_WC_IS_IDLE ); -REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_CQ_IS_IDLE , 62 , SH_UNT , SH_ACS_SCOM , - SH_FLD_MISC_CTL_CQ_IS_IDLE ); -REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_EG_IS_IDLE , 63 , SH_UNT , SH_ACS_SCOM , - SH_FLD_MISC_CTL_EG_IS_IDLE ); REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_INIT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_INIT ); @@ -52217,9 +68799,11 @@ REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_OPTYPE , 2 , SH_UN SH_FLD_MMIO_CTL_OPTYPE ); REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_ACTYPE , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_ACTYPE ); -REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_UNUSED , 4 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_OP_ERR , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_MMIO_CTL_OP_ERR ); +REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_UNUSED , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_UNUSED ); -REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_UNUSED_LEN , 4 , SH_UNT , SH_ACS_SCOM , +REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_UNUSED_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_UNUSED_LEN ); REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_OFFSET , 36 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_OFFSET ); @@ -52230,6 +68814,16 @@ REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_WINID , 48 , SH_UN REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_WINID_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_WINID_LEN ); +REG64_FLD( PU_VAS_MMIODATA_MMIO_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MMIO_DATA ); +REG64_FLD( PU_VAS_MMIODATA_MMIO_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_MMIO_DATA_LEN ); + +REG64_FLD( PU_VAS_MMIOECC_MMIO_ECC , 0 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MMIO_ECC ); +REG64_FLD( PU_VAS_MMIOECC_MMIO_ECC_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , + SH_FLD_MMIO_ECC_LEN ); + REG64_FLD( PU_VAS_MMIO_BASE_ADDR_BAR , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR ); REG64_FLD( PU_VAS_MMIO_BASE_ADDR_BAR_LEN , 31 , SH_UNT , SH_ACS_SCOM , @@ -52251,14 +68845,22 @@ REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_HANG_NX_MAX_CNT , 15 , SH_UN SH_FLD_PBCFG_0_HANG_NX_MAX_CNT ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_HANG_NX_MAX_CNT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_HANG_NX_MAX_CNT_LEN ); -REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED2 , 19 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_DISABLE_WR_RD_PUSH , 19 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PBCFG_0_DISABLE_WR_RD_PUSH ); +REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_CE , 20 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PBCFG_0_INJ_CE ); +REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_UE , 21 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PBCFG_0_INJ_UE ); +REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_SUE , 22 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PBCFG_0_INJ_SUE ); +REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_ARRAY_SEL , 23 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PBCFG_0_INJ_ARRAY_SEL ); +REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_FREQ , 24 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PBCFG_0_INJ_FREQ ); +REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED2 , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_UNUSED2 ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED2_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_UNUSED2_LEN ); -REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED3 , 26 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_PBCFG_0_UNUSED3 ); -REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED3_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , - SH_FLD_PBCFG_0_UNUSED3_LEN ); REG64_FLD( PU_VAS_PBCFG1_DISABLE_LN_WR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DISABLE_LN_WR ); @@ -52313,7 +68915,7 @@ REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_VAL , 0 , SH_UN SH_FLD_PGMIGR1_VAL ); REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR1_BAR ); -REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_BAR_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_BAR_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR1_BAR_LEN ); REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_PGSZ , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR1_PGSZ ); @@ -52324,7 +68926,7 @@ REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_VAL , 0 , SH_UN SH_FLD_PGMIGR2_VAL ); REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR2_BAR ); -REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_BAR_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_BAR_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR2_BAR_LEN ); REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_PGSZ , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR2_PGSZ ); @@ -52335,7 +68937,7 @@ REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_VAL , 0 , SH_UN SH_FLD_PGMIGR3_VAL ); REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR3_BAR ); -REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_BAR_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_BAR_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR3_BAR_LEN ); REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_PGSZ , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR3_PGSZ ); @@ -52346,7 +68948,7 @@ REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_VAL , 0 , SH_UN SH_FLD_PGMIGR4_VAL ); REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR4_BAR ); -REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_BAR_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_BAR_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR4_BAR_LEN ); REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_PGSZ , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR4_PGSZ ); @@ -52357,7 +68959,7 @@ REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_VAL , 0 , SH_UN SH_FLD_PGMIGR5_VAL ); REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR5_BAR ); -REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_BAR_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_BAR_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR5_BAR_LEN ); REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_PGSZ , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR5_PGSZ ); @@ -52368,7 +68970,7 @@ REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_VAL , 0 , SH_UN SH_FLD_PGMIGR6_VAL ); REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR6_BAR ); -REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_BAR_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_BAR_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR6_BAR_LEN ); REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_PGSZ , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR6_PGSZ ); @@ -52379,7 +68981,7 @@ REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_VAL , 0 , SH_UN SH_FLD_PGMIGR7_VAL ); REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR7_BAR ); -REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_BAR_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_BAR_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR7_BAR_LEN ); REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_PGSZ , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR7_PGSZ ); @@ -52390,13 +68992,33 @@ REG64_FLD( PU_VAS_PMCNTL_PU_BIT_ENABLES , 0 , SH_UN SH_FLD_PU_BIT_ENABLES ); REG64_FLD( PU_VAS_PMCNTL_PU_BIT_ENABLES_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PU_BIT_ENABLES_LEN ); +REG64_FLD( PU_VAS_PMCNTL_PU_CNTL_UNUSED , 32 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PU_CNTL_UNUSED ); +REG64_FLD( PU_VAS_PMCNTL_PU_CNTL_UNUSED_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_PU_CNTL_UNUSED_LEN ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_RESET ); -REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BITS , 4 , SH_UNT , SH_ACS_SCOM , - SH_FLD_RG_CERR_BITS ); -REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BITS_LEN , 20 , SH_UNT , SH_ACS_SCOM , - SH_FLD_RG_CERR_BITS_LEN ); +REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT4 , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RG_CERR_BIT4 ); +REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT5 , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RG_CERR_BIT5 ); +REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT6 , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RG_CERR_BIT6 ); +REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT7 , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RG_CERR_BIT7 ); +REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT8 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RG_CERR_BIT8 ); +REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT9 , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RG_CERR_BIT9 ); +REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT10 , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RG_CERR_BIT10 ); +REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT11 , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RG_CERR_BIT11 ); +REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_UNUSED_BITS , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RG_CERR_UNUSED_BITS ); +REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_UNUSED_BITS_LEN , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_RG_CERR_UNUSED_BITS_LEN ); REG64_FLD( PU_VAS_RMABAR_RMA_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RMA_BAR ); @@ -52418,6 +69040,22 @@ REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE , 3 , SH_UN SH_FLD_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE ); REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EG_STAMP_DEBUG , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOUTH_CTL_EG_STAMP_DEBUG ); +REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EN_FAST_SCRUB , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SOUTH_CTL_EN_FAST_SCRUB ); +REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_DIS_SIMULT_RD_WR , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SOUTH_CTL_DIS_SIMULT_RD_WR ); +REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_ENA_NOTIFY_ORDER , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SOUTH_CTL_ENA_NOTIFY_ORDER ); +REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_WC_IDLE_BIT , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SOUTH_CTL_WC_IDLE_BIT ); +REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_CQ_IDLE_BIT , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SOUTH_CTL_CQ_IDLE_BIT ); +REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EG_IDLE_BIT , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SOUTH_CTL_EG_IDLE_BIT ); +REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_UNUSED , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SOUTH_CTL_UNUSED ); +REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_UNUSED_LEN , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_SOUTH_CTL_UNUSED_LEN ); REG64_FLD( PU_VAS_UWMBAR_BASE_ADDR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BASE_ADDR ); @@ -52431,10 +69069,38 @@ REG64_FLD( PU_VAS_WCBSBAR_WC_BS_BAR_LEN , 33 , SH_UN REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_RESET ); -REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BITS , 4 , SH_UNT , SH_ACS_SCOM , - SH_FLD_WC_CERR_BITS ); -REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BITS_LEN , 20 , SH_UNT , SH_ACS_SCOM , - SH_FLD_WC_CERR_BITS_LEN ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT4 , 4 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT4 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT5 , 5 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT5 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT6 , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT6 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT7 , 7 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT7 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT8 , 8 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT8 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT9 , 9 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT9 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT10 , 10 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT10 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT11 , 11 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT11 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT12 , 12 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT12 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT13 , 13 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT13 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT14 , 14 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT14 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT15 , 15 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT15 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT16 , 16 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT16 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT17 , 17 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_BIT17 ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_UNUSEDBITS , 18 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_UNUSEDBITS ); +REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_UNUSEDBITS_LEN , 6 , SH_UNT , SH_ACS_SCOM , + SH_FLD_WC_CERR_UNUSEDBITS_LEN ); REG64_FLD( PU_VAS_WCMBAR_BASE_ADDR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BASE_ADDR ); @@ -52443,7 +69109,7 @@ REG64_FLD( PU_VAS_WCMBAR_BASE_ADDR_LEN , 31 , SH_UN REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR0_BA ); -REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_BA_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR0_BA_LEN ); REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR0_SIZE ); @@ -52456,6 +69122,8 @@ REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPEDIS , 1 , SH_UN SH_FLD_WRMON_CMP0_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_TTYPEDIS_LEN ); +REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WRMON_CMP0_UNUSED ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , @@ -52482,7 +69150,7 @@ REG64_FLD( PU_VAS_WRMON0WID_WRMON_WID0_LEN , 16 , SH_UN REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR1_BA ); -REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_BA_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR1_BA_LEN ); REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR1_SIZE ); @@ -52495,6 +69163,8 @@ REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPEDIS , 1 , SH_UN SH_FLD_WRMON_CMP1_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_TTYPEDIS_LEN ); +REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WRMON_CMP1_UNUSED ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , @@ -52521,7 +69191,7 @@ REG64_FLD( PU_VAS_WRMON1WID_WRMON_WID1_LEN , 16 , SH_UN REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR2_BA ); -REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_BA_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR2_BA_LEN ); REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR2_SIZE ); @@ -52534,6 +69204,8 @@ REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPEDIS , 1 , SH_UN SH_FLD_WRMON_CMP2_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_TTYPEDIS_LEN ); +REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WRMON_CMP2_UNUSED ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , @@ -52560,7 +69232,7 @@ REG64_FLD( PU_VAS_WRMON2WID_WRMON_WID2_LEN , 16 , SH_UN REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR3_BA ); -REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_BA_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR3_BA_LEN ); REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR3_SIZE ); @@ -52573,6 +69245,8 @@ REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPEDIS , 1 , SH_UN SH_FLD_WRMON_CMP3_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_TTYPEDIS_LEN ); +REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WRMON_CMP3_UNUSED ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , @@ -52599,7 +69273,7 @@ REG64_FLD( PU_VAS_WRMON3WID_WRMON_WID3_LEN , 16 , SH_UN REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR4_BA ); -REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_BA_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR4_BA_LEN ); REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR4_SIZE ); @@ -52612,6 +69286,8 @@ REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPEDIS , 1 , SH_UN SH_FLD_WRMON_CMP4_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_TTYPEDIS_LEN ); +REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WRMON_CMP4_UNUSED ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , @@ -52638,7 +69314,7 @@ REG64_FLD( PU_VAS_WRMON4WID_WRMON_WID4_LEN , 16 , SH_UN REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR5_BA ); -REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_BA_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR5_BA_LEN ); REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR5_SIZE ); @@ -52651,6 +69327,8 @@ REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPEDIS , 1 , SH_UN SH_FLD_WRMON_CMP5_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_TTYPEDIS_LEN ); +REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WRMON_CMP5_UNUSED ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , @@ -52677,7 +69355,7 @@ REG64_FLD( PU_VAS_WRMON5WID_WRMON_WID5_LEN , 16 , SH_UN REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR6_BA ); -REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_BA_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR6_BA_LEN ); REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR6_SIZE ); @@ -52690,6 +69368,8 @@ REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPEDIS , 1 , SH_UN SH_FLD_WRMON_CMP6_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_TTYPEDIS_LEN ); +REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WRMON_CMP6_UNUSED ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , @@ -52716,7 +69396,7 @@ REG64_FLD( PU_VAS_WRMON6WID_WRMON_WID6_LEN , 16 , SH_UN REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR7_BA ); -REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_BA_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , +REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR7_BA_LEN ); REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR7_SIZE ); @@ -52729,6 +69409,8 @@ REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPEDIS , 1 , SH_UN SH_FLD_WRMON_CMP7_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_TTYPEDIS_LEN ); +REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , + SH_FLD_WRMON_CMP7_UNUSED ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , @@ -52834,6 +69516,238 @@ REG64_FLD( PU_WATER_MARK_REGISTER_E_PEEK_DATA1_3_LEN , 8 , SH_UN REG64_FLD( PU_WATER_MARK_REGISTER_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); +REG64_FLD( PU_N3_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RING_LOCKING ); +REG64_FLD( PU_N3_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RESERVED_RING_LOCKING ); + +REG64_FLD( PU_N1_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RING_LOCKING ); +REG64_FLD( PU_N1_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RESERVED_RING_LOCKING ); + +REG64_FLD( PU_N2_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RING_LOCKING ); +REG64_FLD( PU_N2_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RESERVED_RING_LOCKING ); + +REG64_FLD( PEC_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RING_LOCKING ); +REG64_FLD( PEC_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RESERVED_RING_LOCKING ); + +REG64_FLD( PU_N0_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RING_LOCKING ); +REG64_FLD( PU_N0_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RESERVED_RING_LOCKING ); + +REG64_FLD( PU_N3_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RINGS ); +REG64_FLD( PU_N3_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , + SH_FLD_RINGS_LEN ); + +REG64_FLD( PU_N1_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RINGS ); +REG64_FLD( PU_N1_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , + SH_FLD_RINGS_LEN ); + +REG64_FLD( PU_N2_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RINGS ); +REG64_FLD( PU_N2_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , + SH_FLD_RINGS_LEN ); + +REG64_FLD( PEC_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RINGS ); +REG64_FLD( PEC_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_RINGS_LEN ); + +REG64_FLD( PU_N0_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RINGS ); +REG64_FLD( PU_N0_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , + SH_FLD_RINGS_LEN ); + +REG64_FLD( PEC_XFIR_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN0 ); +REG64_FLD( PEC_XFIR_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN1 ); +REG64_FLD( PEC_XFIR_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN2 ); +REG64_FLD( PEC_XFIR_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN3 ); +REG64_FLD( PEC_XFIR_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN4 ); +REG64_FLD( PEC_XFIR_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN5 ); +REG64_FLD( PEC_XFIR_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN6 ); +REG64_FLD( PEC_XFIR_IN6_LEN , 20 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN6_LEN ); +REG64_FLD( PEC_XFIR_IN26 , 26 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_IN26 ); + +REG64_FLD( CAPP_XPT_CONTROL_SEND_PACKET_TIMER_VALUE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SEND_PACKET_TIMER_VALUE ); +REG64_FLD( CAPP_XPT_CONTROL_SEND_PACKET_TIMER_VALUE_LEN , 10 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SEND_PACKET_TIMER_VALUE_LEN ); +REG64_FLD( CAPP_XPT_CONTROL_CI_STORE_BUFFER_THRESHOLD , 10 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CI_STORE_BUFFER_THRESHOLD ); +REG64_FLD( CAPP_XPT_CONTROL_CI_STORE_BUFFER_THRESHOLD_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CI_STORE_BUFFER_THRESHOLD_LEN ); +REG64_FLD( CAPP_XPT_CONTROL_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS , 14 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS ); +REG64_FLD( CAPP_XPT_CONTROL_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS_LEN ); +REG64_FLD( CAPP_XPT_CONTROL_TLBI_DATA_POLL_PULSE_DIV , 18 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBI_DATA_POLL_PULSE_DIV ); +REG64_FLD( CAPP_XPT_CONTROL_TLBI_DATA_POLL_PULSE_DIV_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBI_DATA_POLL_PULSE_DIV_LEN ); +REG64_FLD( CAPP_XPT_CONTROL_SN_WRT_DBUF_MAX_CREDIT , 22 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SN_WRT_DBUF_MAX_CREDIT ); +REG64_FLD( CAPP_XPT_CONTROL_SN_WRT_DBUF_MAX_CREDIT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SN_WRT_DBUF_MAX_CREDIT_LEN ); +REG64_FLD( CAPP_XPT_CONTROL_RESERVED , 26 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED ); +REG64_FLD( CAPP_XPT_CONTROL_RESERVED_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_RESERVED_LEN ); +REG64_FLD( CAPP_XPT_CONTROL_SN_MSG_MAX_CREDIT , 28 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SN_MSG_MAX_CREDIT ); +REG64_FLD( CAPP_XPT_CONTROL_SN_MSG_MAX_CREDIT_LEN , 9 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_SN_MSG_MAX_CREDIT_LEN ); +REG64_FLD( CAPP_XPT_CONTROL_BENIGN_PTR_DATA , 37 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_BENIGN_PTR_DATA ); +REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_EN , 38 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBIE_STALL_EN ); +REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_THRESHOLD , 39 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBIE_STALL_THRESHOLD ); +REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_THRESHOLD_LEN , 3 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBIE_STALL_THRESHOLD_LEN ); +REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_CMPLT_CNT , 42 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBIE_STALL_CMPLT_CNT ); +REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_CMPLT_CNT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBIE_STALL_CMPLT_CNT_LEN ); +REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_DELAY_CNT , 46 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBIE_STALL_DELAY_CNT ); +REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_DELAY_CNT_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_TLBIE_STALL_DELAY_CNT_LEN ); +REG64_FLD( CAPP_XPT_CONTROL_CI_BUFF_MIN , 58 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CI_BUFF_MIN ); +REG64_FLD( CAPP_XPT_CONTROL_CI_BUFF_MIN_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CI_BUFF_MIN_LEN ); +REG64_FLD( CAPP_XPT_CONTROL_CI_BUFF_AVAIL , 62 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_CI_BUFF_AVAIL ); +REG64_FLD( CAPP_XPT_CONTROL_LOAD_CI_BUFF , 63 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_LOAD_CI_BUFF ); + +REG64_FLD( CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT , 0 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMON_GROUP_SELECT ); +REG64_FLD( CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , + SH_FLD_PMON_GROUP_SELECT_LEN ); + +REG64_FLD( PEC_XSTOP1_MASK_B , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASK_B ); +REG64_FLD( PEC_XSTOP1_KEEP_EDRAM_ENABLED_ON , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_KEEP_EDRAM_ENABLED_ON ); +REG64_FLD( PEC_XSTOP1_TRIGGER_OPCG_ON , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIGGER_OPCG_ON ); +REG64_FLD( PEC_XSTOP1_WAIT_ALLWAYS , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WAIT_ALLWAYS ); +REG64_FLD( PEC_XSTOP1_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PERV ); +REG64_FLD( PEC_XSTOP1_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT1 ); +REG64_FLD( PEC_XSTOP1_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT2 ); +REG64_FLD( PEC_XSTOP1_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT3 ); +REG64_FLD( PEC_XSTOP1_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT4 ); +REG64_FLD( PEC_XSTOP1_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT5 ); +REG64_FLD( PEC_XSTOP1_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT6 ); +REG64_FLD( PEC_XSTOP1_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT7 ); +REG64_FLD( PEC_XSTOP1_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT8 ); +REG64_FLD( PEC_XSTOP1_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT9 ); +REG64_FLD( PEC_XSTOP1_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT10 ); +REG64_FLD( PEC_XSTOP1_WAIT_CYCLES , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WAIT_CYCLES ); +REG64_FLD( PEC_XSTOP1_WAIT_CYCLES_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WAIT_CYCLES_LEN ); + +REG64_FLD( PEC_XSTOP2_MASK_B , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASK_B ); +REG64_FLD( PEC_XSTOP2_KEEP_EDRAM_ENABLED_ON , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_KEEP_EDRAM_ENABLED_ON ); +REG64_FLD( PEC_XSTOP2_TRIGGER_OPCG_ON , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIGGER_OPCG_ON ); +REG64_FLD( PEC_XSTOP2_WAIT_ALLWAYS , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WAIT_ALLWAYS ); +REG64_FLD( PEC_XSTOP2_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PERV ); +REG64_FLD( PEC_XSTOP2_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT1 ); +REG64_FLD( PEC_XSTOP2_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT2 ); +REG64_FLD( PEC_XSTOP2_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT3 ); +REG64_FLD( PEC_XSTOP2_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT4 ); +REG64_FLD( PEC_XSTOP2_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT5 ); +REG64_FLD( PEC_XSTOP2_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT6 ); +REG64_FLD( PEC_XSTOP2_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT7 ); +REG64_FLD( PEC_XSTOP2_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT8 ); +REG64_FLD( PEC_XSTOP2_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT9 ); +REG64_FLD( PEC_XSTOP2_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT10 ); +REG64_FLD( PEC_XSTOP2_WAIT_CYCLES , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WAIT_CYCLES ); +REG64_FLD( PEC_XSTOP2_WAIT_CYCLES_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WAIT_CYCLES_LEN ); + +REG64_FLD( PEC_XSTOP3_MASK_B , 0 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_MASK_B ); +REG64_FLD( PEC_XSTOP3_KEEP_EDRAM_ENABLED_ON , 1 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_KEEP_EDRAM_ENABLED_ON ); +REG64_FLD( PEC_XSTOP3_TRIGGER_OPCG_ON , 2 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_TRIGGER_OPCG_ON ); +REG64_FLD( PEC_XSTOP3_WAIT_ALLWAYS , 3 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WAIT_ALLWAYS ); +REG64_FLD( PEC_XSTOP3_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_PERV ); +REG64_FLD( PEC_XSTOP3_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT1 ); +REG64_FLD( PEC_XSTOP3_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT2 ); +REG64_FLD( PEC_XSTOP3_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT3 ); +REG64_FLD( PEC_XSTOP3_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT4 ); +REG64_FLD( PEC_XSTOP3_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT5 ); +REG64_FLD( PEC_XSTOP3_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT6 ); +REG64_FLD( PEC_XSTOP3_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT7 ); +REG64_FLD( PEC_XSTOP3_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT8 ); +REG64_FLD( PEC_XSTOP3_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT9 ); +REG64_FLD( PEC_XSTOP3_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_UNIT10 ); +REG64_FLD( PEC_XSTOP3_WAIT_CYCLES , 48 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WAIT_CYCLES ); +REG64_FLD( PEC_XSTOP3_WAIT_CYCLES_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , + SH_FLD_WAIT_CYCLES_LEN ); + REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , @@ -52862,10 +69776,18 @@ REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_INH1_TICK , 32 , SH_UN SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); -REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1 ); +REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1_LEN ); +REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2 ); +REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2_LEN ); +REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1 ); +REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); @@ -52895,10 +69817,18 @@ REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_INH1_TICK , 32 , SH_UN SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); -REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1 ); +REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1_LEN ); +REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2 ); +REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2_LEN ); +REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1 ); +REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); @@ -52928,10 +69858,18 @@ REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_INH1_TICK , 32 , SH_UN SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); -REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1 ); +REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1_LEN ); +REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2 ); +REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2_LEN ); +REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1 ); +REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); @@ -52961,10 +69899,18 @@ REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_INH1_TICK , 32 , SH_UN SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); -REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1 ); +REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1_LEN ); +REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2 ); +REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2_LEN ); +REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1 ); +REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); @@ -52994,10 +69940,18 @@ REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_INH1_TICK , 32 , SH_UN SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); -REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1 ); +REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1_LEN ); +REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2 ); +REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2_LEN ); +REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1 ); +REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); @@ -53027,10 +69981,18 @@ REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_INH1_TICK , 32 , SH_UN SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); -REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1 ); +REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1_LEN ); +REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2 ); +REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2_LEN ); +REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1 ); +REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); @@ -53060,10 +70022,18 @@ REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_INH1_TICK , 32 , SH_UN SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); -REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1 ); +REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1_LEN ); +REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2 ); +REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2_LEN ); +REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1 ); +REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); @@ -53093,10 +70063,18 @@ REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_INH1_TICK , 32 , SH_UN SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); -REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1 ); +REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1_LEN ); +REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2 ); +REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2_LEN ); +REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1 ); +REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); @@ -53126,10 +70104,18 @@ REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_INH1_TICK , 32 , SH_UN SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); -REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1 ); +REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1_LEN ); +REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2 ); +REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2_LEN ); +REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1 ); +REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); @@ -53159,10 +70145,18 @@ REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_INH1_TICK , 32 , SH_UN SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); -REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1 ); +REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1_LEN ); +REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2 ); +REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2_LEN ); +REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1 ); +REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); @@ -53192,10 +70186,18 @@ REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_INH1_TICK , 32 , SH_UN SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); -REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1 ); +REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1_LEN ); +REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2 ); +REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2_LEN ); +REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1 ); +REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); @@ -53225,10 +70227,18 @@ REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_INH1_TICK , 32 , SH_UN SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); -REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1 ); -REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , - SH_FLD_RESERVED1_LEN ); +REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1 ); +REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE1_LEN ); +REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2 ); +REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_NV_RESP_RATE2_LEN ); +REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1 ); +REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , + SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_BRAZOS , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BRAZOS ); @@ -53248,9 +70258,13 @@ REG64_FLD( PU_NPU_SM2_XTS_CONFIG_SPLURGE , 7 , SH_UN SH_FLD_SPLURGE ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_LIM_PS , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_LIM_PS ); -REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1 , 9 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF2DMD , 9 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PREF2DMD ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREFEVOD , 10 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PREFEVOD ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1 , 11 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED1 ); -REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1_LEN , 7 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , +REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED1_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_DEC_RATE , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_TLBIE_DEC_RATE ); @@ -53291,5 +70305,64 @@ REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH3 , 60 , SH_UN REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH3_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREF_THRSH3_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_ENABLE , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_ENABLE ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_RESETMODE , 1 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_RESETMODE ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_FREEZEMODE , 2 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_FREEZEMODE ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_DISABLE_PMISC , 3 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_DISABLE_PMISC ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PMISC_MODE , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_PMISC_MODE ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_CASCADE , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_CASCADE ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_CASCADE_LEN , 3 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_CASCADE_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C0 , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_PRESCALE_C0 ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C0_LEN , 2 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_PRESCALE_C0_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C1 , 10 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_PRESCALE_C1 ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C1_LEN , 2 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_PRESCALE_C1_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C2 , 12 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_PRESCALE_C2 ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C2_LEN , 2 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_PRESCALE_C2_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C3 , 14 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_PRESCALE_C3 ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C3_LEN , 2 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_PRESCALE_C3_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT0 , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_EVENT0 ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT0_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_EVENT0_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT1 , 24 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_EVENT1 ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT1_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_EVENT1_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT2 , 32 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_EVENT2 ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT2_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_EVENT2_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT3 , 40 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_EVENT3 ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT3_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_PERF_EVENT3_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_UNUSED , 48 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_UNUSED ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_UNUSED_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_UNUSED_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_ATSD_TIMEOUT , 56 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATSD_TIMEOUT ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_ATSD_TIMEOUT_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATSD_TIMEOUT_LEN ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_ATR_TIMEOUT , 60 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATR_TIMEOUT ); +REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_ATR_TIMEOUT_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , + SH_FLD_ATR_TIMEOUT_LEN ); + #endif diff --git a/import/chips/p9/common/include/p9_perv_scom_addresses.H b/import/chips/p9/common/include/p9_perv_scom_addresses.H index 794a5f9a..1fcede2d 100644 --- a/import/chips/p9/common/include/p9_perv_scom_addresses.H +++ b/import/chips/p9/common/include/p9_perv_scom_addresses.H @@ -232,6 +232,19 @@ #include <p9_perv_scom_addresses_fixes.H> +REG64( PERV_ACT0_REG , RULL(0x0000090E), SH_UNT_PERV , + SH_ACS_SCOM_RW ); //DUPS: 0000090E, 0000094E, 0000090E, 0000094E, 0000098E, +REG64( PERV_PIB_ACT0_REG , RULL(0x0000090E), SH_UNT_PERV_0 , + SH_ACS_SCOM_RW ); //DUPS: 0000090E, 0000094E, 0000090E, 0000094E, 0000098E, + +REG64( PERV_ACTION1_REG , RULL(0x0000090F), SH_UNT_PERV , + SH_ACS_SCOM_RW ); //DUPS: 0000090F, 0000094F, 0000090F, 0000094F, 0000098F, +REG64( PERV_PIB_ACTION1_REG , RULL(0x0000090F), SH_UNT_PERV_0 , + SH_ACS_SCOM_RW ); //DUPS: 0000090F, 0000094F, 0000090F, 0000094F, 0000098F, + +REG64( PERV_ADDR_TRAP_REG , RULL(0x00010003), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_ADDR_TRAP_REG , RULL(0x01010003), SH_UNT_PERV_1 , SH_ACS_SCOM ); + REG64( PERV_N3_ADS_XSCOM_CMD_REG , RULL(0x0500281C), SH_UNT_PERV_5 , SH_ACS_SCOM ); REG64( PERV_N3_ADU_HANG_DIV_REG , RULL(0x05002850), SH_UNT_PERV_5 , SH_ACS_SCOM_RW ); @@ -291,6 +304,9 @@ REG64( PERV_EC21_ASSIST_INTERRUPT_REG , RULL(0x350F0011 REG64( PERV_EC22_ASSIST_INTERRUPT_REG , RULL(0x360F0011), SH_UNT_PERV_54 , SH_ACS_SCOM ); REG64( PERV_EC23_ASSIST_INTERRUPT_REG , RULL(0x370F0011), SH_UNT_PERV_55 , SH_ACS_SCOM ); +REG64( PERV_ATOMIC_LOCK_MASK_LATCH_REG , RULL(0x00010007), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_ATOMIC_LOCK_MASK_LATCH_REG , RULL(0x01010007), SH_UNT_PERV_1 , SH_ACS_SCOM ); + REG64( PERV_ATOMIC_LOCK_REG , RULL(0x000F03FF), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_TP_ATOMIC_LOCK_REG , RULL(0x010F03FF), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_N0_ATOMIC_LOCK_REG , RULL(0x020F03FF), SH_UNT_PERV_2 , SH_ACS_SCOM ); @@ -559,6 +575,11 @@ REG32( PERV_FSISHIFT_CHIP_ID_FSI , RULL(0x00000C09 REG32( PERV_FSISHIFT_CHIP_ID_FSI_BYTE , RULL(0x00000C24), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ); +REG64( PERV_CLKRATIO , RULL(0x000003F0), SH_UNT_PERV , + SH_ACS_SCOM_RO ); //DUPS: 000003F0, +REG64( PERV_PIB_CLKRATIO , RULL(0x000003F0), SH_UNT_PERV_0 , + SH_ACS_SCOM_RO ); //DUPS: 000003F0, + REG64( PERV_CLK_REGION , RULL(0x00030006), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_TP_CLK_REGION , RULL(0x01030006), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_N0_CLK_REGION , RULL(0x02030006), SH_UNT_PERV_2 , SH_ACS_SCOM ); @@ -750,19 +771,20 @@ REG64( PERV_PIB2OPB0_CMD_WRDAT , RULL(0x00020000 REG64( PERV_PIB2OPB1_CMD_WRDAT , RULL(0x00020010), SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM ); -REG64( PERV_0_FSII2C_COMMAND_REGISTER , RULL(0x00001801), SH_UNT_PERV_0_FSII2C, - SH_ACS_SCOM ); REG32( PERV_FSI2PIB_COMMAND_REGISTER_FSI , RULL(0x00001002), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI ); REG32( PERV_FSI2PIB_COMMAND_REGISTER_FSI_BYTE , RULL(0x00001008), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE ); -REG32( PERV_FSII2C_COMMAND_REGISTER , RULL(0x00001801), SH_UNT_PERV_FSII2C, - SH_ACS_SCOM ); REG32( PERV_FSISHIFT_COMMAND_REGISTER_FSI , RULL(0x00000C01), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI ); REG32( PERV_FSISHIFT_COMMAND_REGISTER_FSI_BYTE , RULL(0x00000C04), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ); +REG64( PERV_0_FSII2C_COMMAND_REGISTER_A , RULL(0x00001801), SH_UNT_PERV_0_FSII2C, + SH_ACS_SCOM ); +REG32( PERV_FSII2C_COMMAND_REGISTER_A , RULL(0x00001801), SH_UNT_PERV_FSII2C, + SH_ACS_SCOM ); + REG32( PERV_FSI2PIB_COMPLEMENT_MASK_FSI , RULL(0x0000100C), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI ); REG32( PERV_FSI2PIB_COMPLEMENT_MASK_FSI_BYTE , RULL(0x00001030), SH_UNT_PERV_FSI2PIB, @@ -1737,6 +1759,31 @@ REG64( PERV_EC21_CPPM_CACSR , RULL(0x350F016B REG64( PERV_EC22_CPPM_CACSR , RULL(0x360F016B), SH_UNT_PERV_54 , SH_ACS_SCOM_RO ); REG64( PERV_EC23_CPPM_CACSR , RULL(0x370F016B), SH_UNT_PERV_55 , SH_ACS_SCOM_RO ); +REG64( PERV_EC00_CPPM_CIIR , RULL(0x200F01AD), SH_UNT_PERV_32 , SH_ACS_SCOM_4P ); +REG64( PERV_EC01_CPPM_CIIR , RULL(0x210F01AD), SH_UNT_PERV_33 , SH_ACS_SCOM_4P ); +REG64( PERV_EC02_CPPM_CIIR , RULL(0x220F01AD), SH_UNT_PERV_34 , SH_ACS_SCOM_4P ); +REG64( PERV_EC03_CPPM_CIIR , RULL(0x230F01AD), SH_UNT_PERV_35 , SH_ACS_SCOM_4P ); +REG64( PERV_EC04_CPPM_CIIR , RULL(0x240F01AD), SH_UNT_PERV_36 , SH_ACS_SCOM_4P ); +REG64( PERV_EC05_CPPM_CIIR , RULL(0x250F01AD), SH_UNT_PERV_37 , SH_ACS_SCOM_4P ); +REG64( PERV_EC06_CPPM_CIIR , RULL(0x260F01AD), SH_UNT_PERV_38 , SH_ACS_SCOM_4P ); +REG64( PERV_EC07_CPPM_CIIR , RULL(0x270F01AD), SH_UNT_PERV_39 , SH_ACS_SCOM_4P ); +REG64( PERV_EC08_CPPM_CIIR , RULL(0x280F01AD), SH_UNT_PERV_40 , SH_ACS_SCOM_4P ); +REG64( PERV_EC09_CPPM_CIIR , RULL(0x290F01AD), SH_UNT_PERV_41 , SH_ACS_SCOM_4P ); +REG64( PERV_EC10_CPPM_CIIR , RULL(0x2A0F01AD), SH_UNT_PERV_42 , SH_ACS_SCOM_4P ); +REG64( PERV_EC11_CPPM_CIIR , RULL(0x2B0F01AD), SH_UNT_PERV_43 , SH_ACS_SCOM_4P ); +REG64( PERV_EC12_CPPM_CIIR , RULL(0x2C0F01AD), SH_UNT_PERV_44 , SH_ACS_SCOM_4P ); +REG64( PERV_EC13_CPPM_CIIR , RULL(0x2D0F01AD), SH_UNT_PERV_45 , SH_ACS_SCOM_4P ); +REG64( PERV_EC14_CPPM_CIIR , RULL(0x2E0F01AD), SH_UNT_PERV_46 , SH_ACS_SCOM_4P ); +REG64( PERV_EC15_CPPM_CIIR , RULL(0x2F0F01AD), SH_UNT_PERV_47 , SH_ACS_SCOM_4P ); +REG64( PERV_EC16_CPPM_CIIR , RULL(0x300F01AD), SH_UNT_PERV_48 , SH_ACS_SCOM_4P ); +REG64( PERV_EC17_CPPM_CIIR , RULL(0x310F01AD), SH_UNT_PERV_49 , SH_ACS_SCOM_4P ); +REG64( PERV_EC18_CPPM_CIIR , RULL(0x320F01AD), SH_UNT_PERV_50 , SH_ACS_SCOM_4P ); +REG64( PERV_EC19_CPPM_CIIR , RULL(0x330F01AD), SH_UNT_PERV_51 , SH_ACS_SCOM_4P ); +REG64( PERV_EC20_CPPM_CIIR , RULL(0x340F01AD), SH_UNT_PERV_52 , SH_ACS_SCOM_4P ); +REG64( PERV_EC21_CPPM_CIIR , RULL(0x350F01AD), SH_UNT_PERV_53 , SH_ACS_SCOM_4P ); +REG64( PERV_EC22_CPPM_CIIR , RULL(0x360F01AD), SH_UNT_PERV_54 , SH_ACS_SCOM_4P ); +REG64( PERV_EC23_CPPM_CIIR , RULL(0x370F01AD), SH_UNT_PERV_55 , SH_ACS_SCOM_4P ); + REG64( PERV_EC00_CPPM_CISR , RULL(0x200F01AE), SH_UNT_PERV_32 , SH_ACS_SCOM_RO ); REG64( PERV_EC01_CPPM_CISR , RULL(0x210F01AE), SH_UNT_PERV_33 , SH_ACS_SCOM_RO ); REG64( PERV_EC02_CPPM_CISR , RULL(0x220F01AE), SH_UNT_PERV_34 , SH_ACS_SCOM_RO ); @@ -2813,53 +2860,53 @@ REG64( PERV_EC22_CPPM_PECES , RULL(0x360F01AF REG64( PERV_EC23_CPPM_PECES , RULL(0x370F01AF), SH_UNT_PERV_55 , SH_ACS_SCOM ); REG64( PERV_EC00_CPPM_PERRSUM , RULL(0x200F0120), SH_UNT_PERV_32 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC01_CPPM_PERRSUM , RULL(0x210F0120), SH_UNT_PERV_33 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC02_CPPM_PERRSUM , RULL(0x220F0120), SH_UNT_PERV_34 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC03_CPPM_PERRSUM , RULL(0x230F0120), SH_UNT_PERV_35 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC04_CPPM_PERRSUM , RULL(0x240F0120), SH_UNT_PERV_36 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC05_CPPM_PERRSUM , RULL(0x250F0120), SH_UNT_PERV_37 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC06_CPPM_PERRSUM , RULL(0x260F0120), SH_UNT_PERV_38 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC07_CPPM_PERRSUM , RULL(0x270F0120), SH_UNT_PERV_39 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC08_CPPM_PERRSUM , RULL(0x280F0120), SH_UNT_PERV_40 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC09_CPPM_PERRSUM , RULL(0x290F0120), SH_UNT_PERV_41 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC10_CPPM_PERRSUM , RULL(0x2A0F0120), SH_UNT_PERV_42 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC11_CPPM_PERRSUM , RULL(0x2B0F0120), SH_UNT_PERV_43 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC12_CPPM_PERRSUM , RULL(0x2C0F0120), SH_UNT_PERV_44 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC13_CPPM_PERRSUM , RULL(0x2D0F0120), SH_UNT_PERV_45 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC14_CPPM_PERRSUM , RULL(0x2E0F0120), SH_UNT_PERV_46 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC15_CPPM_PERRSUM , RULL(0x2F0F0120), SH_UNT_PERV_47 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC16_CPPM_PERRSUM , RULL(0x300F0120), SH_UNT_PERV_48 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC17_CPPM_PERRSUM , RULL(0x310F0120), SH_UNT_PERV_49 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC18_CPPM_PERRSUM , RULL(0x320F0120), SH_UNT_PERV_50 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC19_CPPM_PERRSUM , RULL(0x330F0120), SH_UNT_PERV_51 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC20_CPPM_PERRSUM , RULL(0x340F0120), SH_UNT_PERV_52 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC21_CPPM_PERRSUM , RULL(0x350F0120), SH_UNT_PERV_53 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC22_CPPM_PERRSUM , RULL(0x360F0120), SH_UNT_PERV_54 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EC23_CPPM_PERRSUM , RULL(0x370F0120), SH_UNT_PERV_55 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_CRSIC , RULL(0x00030005), SH_UNT_PERV , SH_ACS_SCOM_WCLEAR ); @@ -2896,6 +2943,21 @@ REG64( PERV_PIB2OPB0_CRSIS , RULL(0x00020007 REG64( PERV_PIB2OPB1_CRSIS , RULL(0x00020017), SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO ); +REG64( PERV_CSAR , RULL(0x0000040D), SH_UNT_PERV , SH_ACS_SCOM_RW ); +REG64( PERV_PIB_CSAR , RULL(0x0000040D), SH_UNT_PERV_0 , SH_ACS_SCOM_RW ); + +REG64( PERV_CSCR , RULL(0x0000040A), SH_UNT_PERV , SH_ACS_SCOM_RW ); +REG64( PERV_CSCR_CLEAR , RULL(0x0000040B), SH_UNT_PERV , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_CSCR_OR , RULL(0x0000040C), SH_UNT_PERV , SH_ACS_SCOM2_OR ); +REG64( PERV_PIB_CSCR , RULL(0x0000040A), SH_UNT_PERV_0 , SH_ACS_SCOM_RW ); +REG64( PERV_PIB_CSCR_CLEAR , RULL(0x0000040B), SH_UNT_PERV_0 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_PIB_CSCR_OR , RULL(0x0000040C), SH_UNT_PERV_0 , SH_ACS_SCOM2_OR ); + +REG64( PERV_CSDR , RULL(0x0000040E), SH_UNT_PERV , SH_ACS_SCOM_RW ); +REG64( PERV_PIB_CSDR , RULL(0x0000040E), SH_UNT_PERV_0 , SH_ACS_SCOM_RW ); + REG64( PERV_CTRL_ATOMIC_LOCK_REG , RULL(0x000003FF), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_TP_CTRL_ATOMIC_LOCK_REG , RULL(0x010003FF), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_N0_CTRL_ATOMIC_LOCK_REG , RULL(0x020003FF), SH_UNT_PERV_2 , SH_ACS_SCOM ); @@ -3039,6 +3101,33 @@ REG64( PERV_EC21_DBG_CBS_CC , RULL(0x35030013 REG64( PERV_EC22_DBG_CBS_CC , RULL(0x36030013), SH_UNT_PERV_54 , SH_ACS_SCOM ); REG64( PERV_EC23_DBG_CBS_CC , RULL(0x37030013), SH_UNT_PERV_55 , SH_ACS_SCOM ); +REG64( PERV_DBG_INST1_COND_REG_1 , RULL(0x000107C1), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_DBG_INST1_COND_REG_1 , RULL(0x010107C1), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_DBG_INST1_COND_REG_2 , RULL(0x000107C2), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_DBG_INST1_COND_REG_2 , RULL(0x010107C2), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_DBG_INST2_COND_REG_1 , RULL(0x000107C3), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_DBG_INST2_COND_REG_1 , RULL(0x010107C3), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_DBG_INST2_COND_REG_2 , RULL(0x000107C4), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_DBG_INST2_COND_REG_2 , RULL(0x010107C4), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_DBG_MODE_REG , RULL(0x000107C0), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_DBG_MODE_REG , RULL(0x010107C0), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_DBG_TRACE_MODE_REG_2 , RULL(0x000107CB), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_DBG_TRACE_MODE_REG_2 , RULL(0x010107CB), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_DBG_TRACE_REG_0 , RULL(0x000107C9), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_DBG_TRACE_REG_0 , RULL(0x010107C9), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_DBG_TRACE_REG_1 , RULL(0x000107CA), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_DBG_TRACE_REG_1 , RULL(0x010107CA), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_DEBUG_STATUS_REG , RULL(0x00010004), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_DEBUG_STATUS_REG , RULL(0x01010004), SH_UNT_PERV_1 , SH_ACS_SCOM ); + REG64( PERV_DEVICE_ID_REG , RULL(0x000F000F), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_DEVICE_ID_REG , RULL(0x000F000F), SH_UNT_PERV_0 , SH_ACS_SCOM ); @@ -3331,40 +3420,19 @@ REG64( PERV_EC21_ERR_STATUS_REG , RULL(0x35050013 REG64( PERV_EC22_ERR_STATUS_REG , RULL(0x36050013), SH_UNT_PERV_54 , SH_ACS_SCOM_RO ); REG64( PERV_EC23_ERR_STATUS_REG , RULL(0x37050013), SH_UNT_PERV_55 , SH_ACS_SCOM_RO ); -REG64( PERV_0_FSII2C_EXTENDED_STATUS , RULL(0x00001808), SH_UNT_PERV_0_FSII2C, - SH_ACS_SCOM ); -REG32( PERV_FSII2C_EXTENDED_STATUS , RULL(0x00001808), SH_UNT_PERV_FSII2C, - SH_ACS_SCOM ); REG32( PERV_FSISHIFT_EXTENDED_STATUS_FSI , RULL(0x00000C08), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI ); REG32( PERV_FSISHIFT_EXTENDED_STATUS_FSI_BYTE , RULL(0x00000C20), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ); -REG64( PERV_FI2C_CFG_PPE , RULL(0x00000800), SH_UNT_PERV , SH_ACS_PPE ); -REG64( PERV_FI2C_CFG_PPE1 , RULL(0x00000810), SH_UNT_PERV , SH_ACS_PPE1 ); -REG64( PERV_FI2C_CFG_PPE2 , RULL(0x00000818), SH_UNT_PERV , SH_ACS_PPE2 ); - -REG64( PERV_FI2C_SCFG0_PPE , RULL(0x00000860), SH_UNT_PERV , SH_ACS_PPE ); -REG64( PERV_FI2C_SCFG0_PPE1 , RULL(0x00000870), SH_UNT_PERV , SH_ACS_PPE1 ); -REG64( PERV_FI2C_SCFG0_PPE2 , RULL(0x00000878), SH_UNT_PERV , SH_ACS_PPE2 ); - -REG64( PERV_FI2C_SCFG1_PPE , RULL(0x00000880), SH_UNT_PERV , SH_ACS_PPE ); -REG64( PERV_FI2C_SCFG1_PPE1 , RULL(0x00000890), SH_UNT_PERV , SH_ACS_PPE1 ); -REG64( PERV_FI2C_SCFG1_PPE2 , RULL(0x00000898), SH_UNT_PERV , SH_ACS_PPE2 ); - -REG64( PERV_FI2C_SCFG2_PPE , RULL(0x000008A0), SH_UNT_PERV , SH_ACS_PPE ); -REG64( PERV_FI2C_SCFG2_PPE1 , RULL(0x000008B0), SH_UNT_PERV , SH_ACS_PPE1 ); -REG64( PERV_FI2C_SCFG2_PPE2 , RULL(0x000008B8), SH_UNT_PERV , SH_ACS_PPE2 ); - -REG64( PERV_FI2C_SCFG3_PPE , RULL(0x000008C0), SH_UNT_PERV , SH_ACS_PPE ); -REG64( PERV_FI2C_SCFG3_PPE1 , RULL(0x000008D0), SH_UNT_PERV , SH_ACS_PPE1 ); -REG64( PERV_FI2C_SCFG3_PPE2 , RULL(0x000008D8), SH_UNT_PERV , SH_ACS_PPE2 ); - -REG64( PERV_FI2C_STAT_PPE , RULL(0x00000820), SH_UNT_PERV , SH_ACS_PPE ); +REG64( PERV_0_FSII2C_EXTENDED_STATUS_A , RULL(0x00001808), SH_UNT_PERV_0_FSII2C, + SH_ACS_SCOM ); +REG32( PERV_FSII2C_EXTENDED_STATUS_A , RULL(0x00001808), SH_UNT_PERV_FSII2C, + SH_ACS_SCOM ); -REG64( PERV_0_FSII2C_FIFO_REGISTER , RULL(0x00001800), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_FIFO1_REGISTER_READ_A , RULL(0x00001800), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM ); -REG32( PERV_FSII2C_FIFO_REGISTER , RULL(0x00001800), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_FIFO1_REGISTER_READ_A , RULL(0x00001800), SH_UNT_PERV_FSII2C, SH_ACS_SCOM ); REG64( PERV_FIRST_ERR_REG , RULL(0x000F001E), SH_UNT_PERV , SH_ACS_SCOM ); @@ -3375,6 +3443,61 @@ REG64( PERV_PIB_FIRST_REPLY_REG , RULL(0x000F0018 REG64( PERV_FIR_MASK , RULL(0x00040002), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_TP_FIR_MASK , RULL(0x01040002), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_N0_FIR_MASK , RULL(0x02040002), SH_UNT_PERV_2 , SH_ACS_SCOM ); +REG64( PERV_N1_FIR_MASK , RULL(0x03040002), SH_UNT_PERV_3 , SH_ACS_SCOM ); +REG64( PERV_N2_FIR_MASK , RULL(0x04040002), SH_UNT_PERV_4 , SH_ACS_SCOM ); +REG64( PERV_N3_FIR_MASK , RULL(0x05040002), SH_UNT_PERV_5 , SH_ACS_SCOM ); +REG64( PERV_XB_FIR_MASK , RULL(0x06040002), SH_UNT_PERV_6 , SH_ACS_SCOM ); +REG64( PERV_MC01_FIR_MASK , RULL(0x07040002), SH_UNT_PERV_7 , SH_ACS_SCOM ); +REG64( PERV_MC23_FIR_MASK , RULL(0x08040002), SH_UNT_PERV_8 , SH_ACS_SCOM ); +REG64( PERV_OB0_FIR_MASK , RULL(0x09040002), SH_UNT_PERV_9 , SH_ACS_SCOM ); +REG64( PERV_OB3_FIR_MASK , RULL(0x0C040002), SH_UNT_PERV_12 , SH_ACS_SCOM ); +REG64( PERV_PCI0_FIR_MASK , RULL(0x0D040002), SH_UNT_PERV_13 , SH_ACS_SCOM ); +REG64( PERV_PCI1_FIR_MASK , RULL(0x0E040002), SH_UNT_PERV_14 , SH_ACS_SCOM ); +REG64( PERV_PCI2_FIR_MASK , RULL(0x0F040002), SH_UNT_PERV_15 , SH_ACS_SCOM ); +REG64( PERV_EP00_FIR_MASK , RULL(0x10040002), SH_UNT_PERV_16 , SH_ACS_SCOM ); +REG64( PERV_EP01_FIR_MASK , RULL(0x11040002), SH_UNT_PERV_17 , SH_ACS_SCOM ); +REG64( PERV_EP02_FIR_MASK , RULL(0x12040002), SH_UNT_PERV_18 , SH_ACS_SCOM ); +REG64( PERV_EP03_FIR_MASK , RULL(0x13040002), SH_UNT_PERV_19 , SH_ACS_SCOM ); +REG64( PERV_EP04_FIR_MASK , RULL(0x14040002), SH_UNT_PERV_20 , SH_ACS_SCOM ); +REG64( PERV_EP05_FIR_MASK , RULL(0x15040002), SH_UNT_PERV_21 , SH_ACS_SCOM ); +REG64( PERV_EC00_FIR_MASK , RULL(0x20040002), SH_UNT_PERV_32 , SH_ACS_SCOM ); +REG64( PERV_EC01_FIR_MASK , RULL(0x21040002), SH_UNT_PERV_33 , SH_ACS_SCOM ); +REG64( PERV_EC02_FIR_MASK , RULL(0x22040002), SH_UNT_PERV_34 , SH_ACS_SCOM ); +REG64( PERV_EC03_FIR_MASK , RULL(0x23040002), SH_UNT_PERV_35 , SH_ACS_SCOM ); +REG64( PERV_EC04_FIR_MASK , RULL(0x24040002), SH_UNT_PERV_36 , SH_ACS_SCOM ); +REG64( PERV_EC05_FIR_MASK , RULL(0x25040002), SH_UNT_PERV_37 , SH_ACS_SCOM ); +REG64( PERV_EC06_FIR_MASK , RULL(0x26040002), SH_UNT_PERV_38 , SH_ACS_SCOM ); +REG64( PERV_EC07_FIR_MASK , RULL(0x27040002), SH_UNT_PERV_39 , SH_ACS_SCOM ); +REG64( PERV_EC08_FIR_MASK , RULL(0x28040002), SH_UNT_PERV_40 , SH_ACS_SCOM ); +REG64( PERV_EC09_FIR_MASK , RULL(0x29040002), SH_UNT_PERV_41 , SH_ACS_SCOM ); +REG64( PERV_EC10_FIR_MASK , RULL(0x2A040002), SH_UNT_PERV_42 , SH_ACS_SCOM ); +REG64( PERV_EC11_FIR_MASK , RULL(0x2B040002), SH_UNT_PERV_43 , SH_ACS_SCOM ); +REG64( PERV_EC12_FIR_MASK , RULL(0x2C040002), SH_UNT_PERV_44 , SH_ACS_SCOM ); +REG64( PERV_EC13_FIR_MASK , RULL(0x2D040002), SH_UNT_PERV_45 , SH_ACS_SCOM ); +REG64( PERV_EC14_FIR_MASK , RULL(0x2E040002), SH_UNT_PERV_46 , SH_ACS_SCOM ); +REG64( PERV_EC15_FIR_MASK , RULL(0x2F040002), SH_UNT_PERV_47 , SH_ACS_SCOM ); +REG64( PERV_EC16_FIR_MASK , RULL(0x30040002), SH_UNT_PERV_48 , SH_ACS_SCOM ); +REG64( PERV_EC17_FIR_MASK , RULL(0x31040002), SH_UNT_PERV_49 , SH_ACS_SCOM ); +REG64( PERV_EC18_FIR_MASK , RULL(0x32040002), SH_UNT_PERV_50 , SH_ACS_SCOM ); +REG64( PERV_EC19_FIR_MASK , RULL(0x33040002), SH_UNT_PERV_51 , SH_ACS_SCOM ); +REG64( PERV_EC20_FIR_MASK , RULL(0x34040002), SH_UNT_PERV_52 , SH_ACS_SCOM ); +REG64( PERV_EC21_FIR_MASK , RULL(0x35040002), SH_UNT_PERV_53 , SH_ACS_SCOM ); +REG64( PERV_EC22_FIR_MASK , RULL(0x36040002), SH_UNT_PERV_54 , SH_ACS_SCOM ); +REG64( PERV_EC23_FIR_MASK , RULL(0x37040002), SH_UNT_PERV_55 , SH_ACS_SCOM ); + +REG64( PERV_FIR_REG , RULL(0x00000908), SH_UNT_PERV , + SH_ACS_SCOM_RW ); //DUPS: 00000908, 00000948, 00000908, 00000948, 00000988, +REG64( PERV_FIR_REG_AND , RULL(0x00000909), SH_UNT_PERV , + SH_ACS_SCOM1_AND ); //DUPS: 00000909, 00000949, 00000909, 00000949, 00000989, +REG64( PERV_FIR_REG_OR , RULL(0x0000090A), SH_UNT_PERV , + SH_ACS_SCOM2_OR ); //DUPS: 0000090A, 0000094A, 0000090A, 0000094A, 0000098A, +REG64( PERV_PIB_FIR_REG , RULL(0x00000908), SH_UNT_PERV_0 , + SH_ACS_SCOM_RW ); //DUPS: 00000908, 00000948, 00000908, 00000948, 00000988, +REG64( PERV_PIB_FIR_REG_AND , RULL(0x00000909), SH_UNT_PERV_0 , + SH_ACS_SCOM1_AND ); //DUPS: 00000909, 00000949, 00000909, 00000949, 00000989, +REG64( PERV_PIB_FIR_REG_OR , RULL(0x0000090A), SH_UNT_PERV_0 , + SH_ACS_SCOM2_OR ); //DUPS: 0000090A, 0000094A, 0000090A, 0000094A, 0000098A, REG64( PERV_FMU_FORCE_OP_REG , RULL(0x00020003), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_TP_FMU_FORCE_OP_REG , RULL(0x01020003), SH_UNT_PERV_1 , SH_ACS_SCOM ); @@ -3396,11 +3519,11 @@ REG64( PERV_FMU_PULSE_GEN_REG , RULL(0x00020001 REG64( PERV_TP_FMU_PULSE_GEN_REG , RULL(0x01020001), SH_UNT_PERV_1 , SH_ACS_SCOM ); //WARNING - VALUE SET SAME AS ANOTHER REG -REG64( PERV_FMU_VMEAS_MAX_RESULT , RULL(0x00020008), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_TP_FMU_VMEAS_MAX_RESULT , RULL(0x01020008), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_FMU_VMEAS_MAX_RESULT , RULL(0x00020008), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); +REG64( PERV_TP_FMU_VMEAS_MAX_RESULT , RULL(0x01020008), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); -REG64( PERV_FMU_VMEAS_MIN_RESULT , RULL(0x00020009), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_TP_FMU_VMEAS_MIN_RESULT , RULL(0x01020009), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_FMU_VMEAS_MIN_RESULT , RULL(0x00020009), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); +REG64( PERV_TP_FMU_VMEAS_MIN_RESULT , RULL(0x01020009), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); REG64( PERV_N3_FORCE_ECC_REG , RULL(0x0500280D), SH_UNT_PERV_5 , SH_ACS_SCOM_RW ); @@ -4487,320 +4610,320 @@ REG64( PERV_EC21_GXSTOP_TRIG_REG , RULL(0x35040013 REG64( PERV_EC22_GXSTOP_TRIG_REG , RULL(0x36040013), SH_UNT_PERV_54 , SH_ACS_SCOM ); REG64( PERV_EC23_GXSTOP_TRIG_REG , RULL(0x37040013), SH_UNT_PERV_55 , SH_ACS_SCOM ); -REG64( PERV_HANG_PULSE_0_REG , RULL(0x000F0020), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_TP_HANG_PULSE_0_REG , RULL(0x010F0020), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_N0_HANG_PULSE_0_REG , RULL(0x020F0020), SH_UNT_PERV_2 , SH_ACS_SCOM ); -REG64( PERV_N1_HANG_PULSE_0_REG , RULL(0x030F0020), SH_UNT_PERV_3 , SH_ACS_SCOM ); -REG64( PERV_N2_HANG_PULSE_0_REG , RULL(0x040F0020), SH_UNT_PERV_4 , SH_ACS_SCOM ); -REG64( PERV_N3_HANG_PULSE_0_REG , RULL(0x050F0020), SH_UNT_PERV_5 , SH_ACS_SCOM ); -REG64( PERV_XB_HANG_PULSE_0_REG , RULL(0x060F0020), SH_UNT_PERV_6 , SH_ACS_SCOM ); -REG64( PERV_MC01_HANG_PULSE_0_REG , RULL(0x070F0020), SH_UNT_PERV_7 , SH_ACS_SCOM ); -REG64( PERV_MC23_HANG_PULSE_0_REG , RULL(0x080F0020), SH_UNT_PERV_8 , SH_ACS_SCOM ); -REG64( PERV_OB0_HANG_PULSE_0_REG , RULL(0x090F0020), SH_UNT_PERV_9 , SH_ACS_SCOM ); -REG64( PERV_OB3_HANG_PULSE_0_REG , RULL(0x0C0F0020), SH_UNT_PERV_12 , SH_ACS_SCOM ); -REG64( PERV_PCI0_HANG_PULSE_0_REG , RULL(0x0D0F0020), SH_UNT_PERV_13 , SH_ACS_SCOM ); -REG64( PERV_PCI1_HANG_PULSE_0_REG , RULL(0x0E0F0020), SH_UNT_PERV_14 , SH_ACS_SCOM ); -REG64( PERV_PCI2_HANG_PULSE_0_REG , RULL(0x0F0F0020), SH_UNT_PERV_15 , SH_ACS_SCOM ); -REG64( PERV_EP00_HANG_PULSE_0_REG , RULL(0x100F0020), SH_UNT_PERV_16 , SH_ACS_SCOM ); -REG64( PERV_EP01_HANG_PULSE_0_REG , RULL(0x110F0020), SH_UNT_PERV_17 , SH_ACS_SCOM ); -REG64( PERV_EP02_HANG_PULSE_0_REG , RULL(0x120F0020), SH_UNT_PERV_18 , SH_ACS_SCOM ); -REG64( PERV_EP03_HANG_PULSE_0_REG , RULL(0x130F0020), SH_UNT_PERV_19 , SH_ACS_SCOM ); -REG64( PERV_EP04_HANG_PULSE_0_REG , RULL(0x140F0020), SH_UNT_PERV_20 , SH_ACS_SCOM ); -REG64( PERV_EP05_HANG_PULSE_0_REG , RULL(0x150F0020), SH_UNT_PERV_21 , SH_ACS_SCOM ); -REG64( PERV_EC00_HANG_PULSE_0_REG , RULL(0x200F0020), SH_UNT_PERV_32 , SH_ACS_SCOM ); -REG64( PERV_EC01_HANG_PULSE_0_REG , RULL(0x210F0020), SH_UNT_PERV_33 , SH_ACS_SCOM ); -REG64( PERV_EC02_HANG_PULSE_0_REG , RULL(0x220F0020), SH_UNT_PERV_34 , SH_ACS_SCOM ); -REG64( PERV_EC03_HANG_PULSE_0_REG , RULL(0x230F0020), SH_UNT_PERV_35 , SH_ACS_SCOM ); -REG64( PERV_EC04_HANG_PULSE_0_REG , RULL(0x240F0020), SH_UNT_PERV_36 , SH_ACS_SCOM ); -REG64( PERV_EC05_HANG_PULSE_0_REG , RULL(0x250F0020), SH_UNT_PERV_37 , SH_ACS_SCOM ); -REG64( PERV_EC06_HANG_PULSE_0_REG , RULL(0x260F0020), SH_UNT_PERV_38 , SH_ACS_SCOM ); -REG64( PERV_EC07_HANG_PULSE_0_REG , RULL(0x270F0020), SH_UNT_PERV_39 , SH_ACS_SCOM ); -REG64( PERV_EC08_HANG_PULSE_0_REG , RULL(0x280F0020), SH_UNT_PERV_40 , SH_ACS_SCOM ); -REG64( PERV_EC09_HANG_PULSE_0_REG , RULL(0x290F0020), SH_UNT_PERV_41 , SH_ACS_SCOM ); -REG64( PERV_EC10_HANG_PULSE_0_REG , RULL(0x2A0F0020), SH_UNT_PERV_42 , SH_ACS_SCOM ); -REG64( PERV_EC11_HANG_PULSE_0_REG , RULL(0x2B0F0020), SH_UNT_PERV_43 , SH_ACS_SCOM ); -REG64( PERV_EC12_HANG_PULSE_0_REG , RULL(0x2C0F0020), SH_UNT_PERV_44 , SH_ACS_SCOM ); -REG64( PERV_EC13_HANG_PULSE_0_REG , RULL(0x2D0F0020), SH_UNT_PERV_45 , SH_ACS_SCOM ); -REG64( PERV_EC14_HANG_PULSE_0_REG , RULL(0x2E0F0020), SH_UNT_PERV_46 , SH_ACS_SCOM ); -REG64( PERV_EC15_HANG_PULSE_0_REG , RULL(0x2F0F0020), SH_UNT_PERV_47 , SH_ACS_SCOM ); -REG64( PERV_EC16_HANG_PULSE_0_REG , RULL(0x300F0020), SH_UNT_PERV_48 , SH_ACS_SCOM ); -REG64( PERV_EC17_HANG_PULSE_0_REG , RULL(0x310F0020), SH_UNT_PERV_49 , SH_ACS_SCOM ); -REG64( PERV_EC18_HANG_PULSE_0_REG , RULL(0x320F0020), SH_UNT_PERV_50 , SH_ACS_SCOM ); -REG64( PERV_EC19_HANG_PULSE_0_REG , RULL(0x330F0020), SH_UNT_PERV_51 , SH_ACS_SCOM ); -REG64( PERV_EC20_HANG_PULSE_0_REG , RULL(0x340F0020), SH_UNT_PERV_52 , SH_ACS_SCOM ); -REG64( PERV_EC21_HANG_PULSE_0_REG , RULL(0x350F0020), SH_UNT_PERV_53 , SH_ACS_SCOM ); -REG64( PERV_EC22_HANG_PULSE_0_REG , RULL(0x360F0020), SH_UNT_PERV_54 , SH_ACS_SCOM ); -REG64( PERV_EC23_HANG_PULSE_0_REG , RULL(0x370F0020), SH_UNT_PERV_55 , SH_ACS_SCOM ); - -REG64( PERV_HANG_PULSE_1_REG , RULL(0x000F0021), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_TP_HANG_PULSE_1_REG , RULL(0x010F0021), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_N0_HANG_PULSE_1_REG , RULL(0x020F0021), SH_UNT_PERV_2 , SH_ACS_SCOM ); -REG64( PERV_N1_HANG_PULSE_1_REG , RULL(0x030F0021), SH_UNT_PERV_3 , SH_ACS_SCOM ); -REG64( PERV_N2_HANG_PULSE_1_REG , RULL(0x040F0021), SH_UNT_PERV_4 , SH_ACS_SCOM ); -REG64( PERV_N3_HANG_PULSE_1_REG , RULL(0x050F0021), SH_UNT_PERV_5 , SH_ACS_SCOM ); -REG64( PERV_XB_HANG_PULSE_1_REG , RULL(0x060F0021), SH_UNT_PERV_6 , SH_ACS_SCOM ); -REG64( PERV_MC01_HANG_PULSE_1_REG , RULL(0x070F0021), SH_UNT_PERV_7 , SH_ACS_SCOM ); -REG64( PERV_MC23_HANG_PULSE_1_REG , RULL(0x080F0021), SH_UNT_PERV_8 , SH_ACS_SCOM ); -REG64( PERV_OB0_HANG_PULSE_1_REG , RULL(0x090F0021), SH_UNT_PERV_9 , SH_ACS_SCOM ); -REG64( PERV_OB3_HANG_PULSE_1_REG , RULL(0x0C0F0021), SH_UNT_PERV_12 , SH_ACS_SCOM ); -REG64( PERV_PCI0_HANG_PULSE_1_REG , RULL(0x0D0F0021), SH_UNT_PERV_13 , SH_ACS_SCOM ); -REG64( PERV_PCI1_HANG_PULSE_1_REG , RULL(0x0E0F0021), SH_UNT_PERV_14 , SH_ACS_SCOM ); -REG64( PERV_PCI2_HANG_PULSE_1_REG , RULL(0x0F0F0021), SH_UNT_PERV_15 , SH_ACS_SCOM ); -REG64( PERV_EP00_HANG_PULSE_1_REG , RULL(0x100F0021), SH_UNT_PERV_16 , SH_ACS_SCOM ); -REG64( PERV_EP01_HANG_PULSE_1_REG , RULL(0x110F0021), SH_UNT_PERV_17 , SH_ACS_SCOM ); -REG64( PERV_EP02_HANG_PULSE_1_REG , RULL(0x120F0021), SH_UNT_PERV_18 , SH_ACS_SCOM ); -REG64( PERV_EP03_HANG_PULSE_1_REG , RULL(0x130F0021), SH_UNT_PERV_19 , SH_ACS_SCOM ); -REG64( PERV_EP04_HANG_PULSE_1_REG , RULL(0x140F0021), SH_UNT_PERV_20 , SH_ACS_SCOM ); -REG64( PERV_EP05_HANG_PULSE_1_REG , RULL(0x150F0021), SH_UNT_PERV_21 , SH_ACS_SCOM ); -REG64( PERV_EC00_HANG_PULSE_1_REG , RULL(0x200F0021), SH_UNT_PERV_32 , SH_ACS_SCOM ); -REG64( PERV_EC01_HANG_PULSE_1_REG , RULL(0x210F0021), SH_UNT_PERV_33 , SH_ACS_SCOM ); -REG64( PERV_EC02_HANG_PULSE_1_REG , RULL(0x220F0021), SH_UNT_PERV_34 , SH_ACS_SCOM ); -REG64( PERV_EC03_HANG_PULSE_1_REG , RULL(0x230F0021), SH_UNT_PERV_35 , SH_ACS_SCOM ); -REG64( PERV_EC04_HANG_PULSE_1_REG , RULL(0x240F0021), SH_UNT_PERV_36 , SH_ACS_SCOM ); -REG64( PERV_EC05_HANG_PULSE_1_REG , RULL(0x250F0021), SH_UNT_PERV_37 , SH_ACS_SCOM ); -REG64( PERV_EC06_HANG_PULSE_1_REG , RULL(0x260F0021), SH_UNT_PERV_38 , SH_ACS_SCOM ); -REG64( PERV_EC07_HANG_PULSE_1_REG , RULL(0x270F0021), SH_UNT_PERV_39 , SH_ACS_SCOM ); -REG64( PERV_EC08_HANG_PULSE_1_REG , RULL(0x280F0021), SH_UNT_PERV_40 , SH_ACS_SCOM ); -REG64( PERV_EC09_HANG_PULSE_1_REG , RULL(0x290F0021), SH_UNT_PERV_41 , SH_ACS_SCOM ); -REG64( PERV_EC10_HANG_PULSE_1_REG , RULL(0x2A0F0021), SH_UNT_PERV_42 , SH_ACS_SCOM ); -REG64( PERV_EC11_HANG_PULSE_1_REG , RULL(0x2B0F0021), SH_UNT_PERV_43 , SH_ACS_SCOM ); -REG64( PERV_EC12_HANG_PULSE_1_REG , RULL(0x2C0F0021), SH_UNT_PERV_44 , SH_ACS_SCOM ); -REG64( PERV_EC13_HANG_PULSE_1_REG , RULL(0x2D0F0021), SH_UNT_PERV_45 , SH_ACS_SCOM ); -REG64( PERV_EC14_HANG_PULSE_1_REG , RULL(0x2E0F0021), SH_UNT_PERV_46 , SH_ACS_SCOM ); -REG64( PERV_EC15_HANG_PULSE_1_REG , RULL(0x2F0F0021), SH_UNT_PERV_47 , SH_ACS_SCOM ); -REG64( PERV_EC16_HANG_PULSE_1_REG , RULL(0x300F0021), SH_UNT_PERV_48 , SH_ACS_SCOM ); -REG64( PERV_EC17_HANG_PULSE_1_REG , RULL(0x310F0021), SH_UNT_PERV_49 , SH_ACS_SCOM ); -REG64( PERV_EC18_HANG_PULSE_1_REG , RULL(0x320F0021), SH_UNT_PERV_50 , SH_ACS_SCOM ); -REG64( PERV_EC19_HANG_PULSE_1_REG , RULL(0x330F0021), SH_UNT_PERV_51 , SH_ACS_SCOM ); -REG64( PERV_EC20_HANG_PULSE_1_REG , RULL(0x340F0021), SH_UNT_PERV_52 , SH_ACS_SCOM ); -REG64( PERV_EC21_HANG_PULSE_1_REG , RULL(0x350F0021), SH_UNT_PERV_53 , SH_ACS_SCOM ); -REG64( PERV_EC22_HANG_PULSE_1_REG , RULL(0x360F0021), SH_UNT_PERV_54 , SH_ACS_SCOM ); -REG64( PERV_EC23_HANG_PULSE_1_REG , RULL(0x370F0021), SH_UNT_PERV_55 , SH_ACS_SCOM ); - -REG64( PERV_HANG_PULSE_2_REG , RULL(0x000F0022), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_TP_HANG_PULSE_2_REG , RULL(0x010F0022), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_N0_HANG_PULSE_2_REG , RULL(0x020F0022), SH_UNT_PERV_2 , SH_ACS_SCOM ); -REG64( PERV_N1_HANG_PULSE_2_REG , RULL(0x030F0022), SH_UNT_PERV_3 , SH_ACS_SCOM ); -REG64( PERV_N2_HANG_PULSE_2_REG , RULL(0x040F0022), SH_UNT_PERV_4 , SH_ACS_SCOM ); -REG64( PERV_N3_HANG_PULSE_2_REG , RULL(0x050F0022), SH_UNT_PERV_5 , SH_ACS_SCOM ); -REG64( PERV_XB_HANG_PULSE_2_REG , RULL(0x060F0022), SH_UNT_PERV_6 , SH_ACS_SCOM ); -REG64( PERV_MC01_HANG_PULSE_2_REG , RULL(0x070F0022), SH_UNT_PERV_7 , SH_ACS_SCOM ); -REG64( PERV_MC23_HANG_PULSE_2_REG , RULL(0x080F0022), SH_UNT_PERV_8 , SH_ACS_SCOM ); -REG64( PERV_OB0_HANG_PULSE_2_REG , RULL(0x090F0022), SH_UNT_PERV_9 , SH_ACS_SCOM ); -REG64( PERV_OB3_HANG_PULSE_2_REG , RULL(0x0C0F0022), SH_UNT_PERV_12 , SH_ACS_SCOM ); -REG64( PERV_PCI0_HANG_PULSE_2_REG , RULL(0x0D0F0022), SH_UNT_PERV_13 , SH_ACS_SCOM ); -REG64( PERV_PCI1_HANG_PULSE_2_REG , RULL(0x0E0F0022), SH_UNT_PERV_14 , SH_ACS_SCOM ); -REG64( PERV_PCI2_HANG_PULSE_2_REG , RULL(0x0F0F0022), SH_UNT_PERV_15 , SH_ACS_SCOM ); -REG64( PERV_EP00_HANG_PULSE_2_REG , RULL(0x100F0022), SH_UNT_PERV_16 , SH_ACS_SCOM ); -REG64( PERV_EP01_HANG_PULSE_2_REG , RULL(0x110F0022), SH_UNT_PERV_17 , SH_ACS_SCOM ); -REG64( PERV_EP02_HANG_PULSE_2_REG , RULL(0x120F0022), SH_UNT_PERV_18 , SH_ACS_SCOM ); -REG64( PERV_EP03_HANG_PULSE_2_REG , RULL(0x130F0022), SH_UNT_PERV_19 , SH_ACS_SCOM ); -REG64( PERV_EP04_HANG_PULSE_2_REG , RULL(0x140F0022), SH_UNT_PERV_20 , SH_ACS_SCOM ); -REG64( PERV_EP05_HANG_PULSE_2_REG , RULL(0x150F0022), SH_UNT_PERV_21 , SH_ACS_SCOM ); -REG64( PERV_EC00_HANG_PULSE_2_REG , RULL(0x200F0022), SH_UNT_PERV_32 , SH_ACS_SCOM ); -REG64( PERV_EC01_HANG_PULSE_2_REG , RULL(0x210F0022), SH_UNT_PERV_33 , SH_ACS_SCOM ); -REG64( PERV_EC02_HANG_PULSE_2_REG , RULL(0x220F0022), SH_UNT_PERV_34 , SH_ACS_SCOM ); -REG64( PERV_EC03_HANG_PULSE_2_REG , RULL(0x230F0022), SH_UNT_PERV_35 , SH_ACS_SCOM ); -REG64( PERV_EC04_HANG_PULSE_2_REG , RULL(0x240F0022), SH_UNT_PERV_36 , SH_ACS_SCOM ); -REG64( PERV_EC05_HANG_PULSE_2_REG , RULL(0x250F0022), SH_UNT_PERV_37 , SH_ACS_SCOM ); -REG64( PERV_EC06_HANG_PULSE_2_REG , RULL(0x260F0022), SH_UNT_PERV_38 , SH_ACS_SCOM ); -REG64( PERV_EC07_HANG_PULSE_2_REG , RULL(0x270F0022), SH_UNT_PERV_39 , SH_ACS_SCOM ); -REG64( PERV_EC08_HANG_PULSE_2_REG , RULL(0x280F0022), SH_UNT_PERV_40 , SH_ACS_SCOM ); -REG64( PERV_EC09_HANG_PULSE_2_REG , RULL(0x290F0022), SH_UNT_PERV_41 , SH_ACS_SCOM ); -REG64( PERV_EC10_HANG_PULSE_2_REG , RULL(0x2A0F0022), SH_UNT_PERV_42 , SH_ACS_SCOM ); -REG64( PERV_EC11_HANG_PULSE_2_REG , RULL(0x2B0F0022), SH_UNT_PERV_43 , SH_ACS_SCOM ); -REG64( PERV_EC12_HANG_PULSE_2_REG , RULL(0x2C0F0022), SH_UNT_PERV_44 , SH_ACS_SCOM ); -REG64( PERV_EC13_HANG_PULSE_2_REG , RULL(0x2D0F0022), SH_UNT_PERV_45 , SH_ACS_SCOM ); -REG64( PERV_EC14_HANG_PULSE_2_REG , RULL(0x2E0F0022), SH_UNT_PERV_46 , SH_ACS_SCOM ); -REG64( PERV_EC15_HANG_PULSE_2_REG , RULL(0x2F0F0022), SH_UNT_PERV_47 , SH_ACS_SCOM ); -REG64( PERV_EC16_HANG_PULSE_2_REG , RULL(0x300F0022), SH_UNT_PERV_48 , SH_ACS_SCOM ); -REG64( PERV_EC17_HANG_PULSE_2_REG , RULL(0x310F0022), SH_UNT_PERV_49 , SH_ACS_SCOM ); -REG64( PERV_EC18_HANG_PULSE_2_REG , RULL(0x320F0022), SH_UNT_PERV_50 , SH_ACS_SCOM ); -REG64( PERV_EC19_HANG_PULSE_2_REG , RULL(0x330F0022), SH_UNT_PERV_51 , SH_ACS_SCOM ); -REG64( PERV_EC20_HANG_PULSE_2_REG , RULL(0x340F0022), SH_UNT_PERV_52 , SH_ACS_SCOM ); -REG64( PERV_EC21_HANG_PULSE_2_REG , RULL(0x350F0022), SH_UNT_PERV_53 , SH_ACS_SCOM ); -REG64( PERV_EC22_HANG_PULSE_2_REG , RULL(0x360F0022), SH_UNT_PERV_54 , SH_ACS_SCOM ); -REG64( PERV_EC23_HANG_PULSE_2_REG , RULL(0x370F0022), SH_UNT_PERV_55 , SH_ACS_SCOM ); - -REG64( PERV_HANG_PULSE_3_REG , RULL(0x000F0023), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_TP_HANG_PULSE_3_REG , RULL(0x010F0023), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_N0_HANG_PULSE_3_REG , RULL(0x020F0023), SH_UNT_PERV_2 , SH_ACS_SCOM ); -REG64( PERV_N1_HANG_PULSE_3_REG , RULL(0x030F0023), SH_UNT_PERV_3 , SH_ACS_SCOM ); -REG64( PERV_N2_HANG_PULSE_3_REG , RULL(0x040F0023), SH_UNT_PERV_4 , SH_ACS_SCOM ); -REG64( PERV_N3_HANG_PULSE_3_REG , RULL(0x050F0023), SH_UNT_PERV_5 , SH_ACS_SCOM ); -REG64( PERV_XB_HANG_PULSE_3_REG , RULL(0x060F0023), SH_UNT_PERV_6 , SH_ACS_SCOM ); -REG64( PERV_MC01_HANG_PULSE_3_REG , RULL(0x070F0023), SH_UNT_PERV_7 , SH_ACS_SCOM ); -REG64( PERV_MC23_HANG_PULSE_3_REG , RULL(0x080F0023), SH_UNT_PERV_8 , SH_ACS_SCOM ); -REG64( PERV_OB0_HANG_PULSE_3_REG , RULL(0x090F0023), SH_UNT_PERV_9 , SH_ACS_SCOM ); -REG64( PERV_OB3_HANG_PULSE_3_REG , RULL(0x0C0F0023), SH_UNT_PERV_12 , SH_ACS_SCOM ); -REG64( PERV_PCI0_HANG_PULSE_3_REG , RULL(0x0D0F0023), SH_UNT_PERV_13 , SH_ACS_SCOM ); -REG64( PERV_PCI1_HANG_PULSE_3_REG , RULL(0x0E0F0023), SH_UNT_PERV_14 , SH_ACS_SCOM ); -REG64( PERV_PCI2_HANG_PULSE_3_REG , RULL(0x0F0F0023), SH_UNT_PERV_15 , SH_ACS_SCOM ); -REG64( PERV_EP00_HANG_PULSE_3_REG , RULL(0x100F0023), SH_UNT_PERV_16 , SH_ACS_SCOM ); -REG64( PERV_EP01_HANG_PULSE_3_REG , RULL(0x110F0023), SH_UNT_PERV_17 , SH_ACS_SCOM ); -REG64( PERV_EP02_HANG_PULSE_3_REG , RULL(0x120F0023), SH_UNT_PERV_18 , SH_ACS_SCOM ); -REG64( PERV_EP03_HANG_PULSE_3_REG , RULL(0x130F0023), SH_UNT_PERV_19 , SH_ACS_SCOM ); -REG64( PERV_EP04_HANG_PULSE_3_REG , RULL(0x140F0023), SH_UNT_PERV_20 , SH_ACS_SCOM ); -REG64( PERV_EP05_HANG_PULSE_3_REG , RULL(0x150F0023), SH_UNT_PERV_21 , SH_ACS_SCOM ); -REG64( PERV_EC00_HANG_PULSE_3_REG , RULL(0x200F0023), SH_UNT_PERV_32 , SH_ACS_SCOM ); -REG64( PERV_EC01_HANG_PULSE_3_REG , RULL(0x210F0023), SH_UNT_PERV_33 , SH_ACS_SCOM ); -REG64( PERV_EC02_HANG_PULSE_3_REG , RULL(0x220F0023), SH_UNT_PERV_34 , SH_ACS_SCOM ); -REG64( PERV_EC03_HANG_PULSE_3_REG , RULL(0x230F0023), SH_UNT_PERV_35 , SH_ACS_SCOM ); -REG64( PERV_EC04_HANG_PULSE_3_REG , RULL(0x240F0023), SH_UNT_PERV_36 , SH_ACS_SCOM ); -REG64( PERV_EC05_HANG_PULSE_3_REG , RULL(0x250F0023), SH_UNT_PERV_37 , SH_ACS_SCOM ); -REG64( PERV_EC06_HANG_PULSE_3_REG , RULL(0x260F0023), SH_UNT_PERV_38 , SH_ACS_SCOM ); -REG64( PERV_EC07_HANG_PULSE_3_REG , RULL(0x270F0023), SH_UNT_PERV_39 , SH_ACS_SCOM ); -REG64( PERV_EC08_HANG_PULSE_3_REG , RULL(0x280F0023), SH_UNT_PERV_40 , SH_ACS_SCOM ); -REG64( PERV_EC09_HANG_PULSE_3_REG , RULL(0x290F0023), SH_UNT_PERV_41 , SH_ACS_SCOM ); -REG64( PERV_EC10_HANG_PULSE_3_REG , RULL(0x2A0F0023), SH_UNT_PERV_42 , SH_ACS_SCOM ); -REG64( PERV_EC11_HANG_PULSE_3_REG , RULL(0x2B0F0023), SH_UNT_PERV_43 , SH_ACS_SCOM ); -REG64( PERV_EC12_HANG_PULSE_3_REG , RULL(0x2C0F0023), SH_UNT_PERV_44 , SH_ACS_SCOM ); -REG64( PERV_EC13_HANG_PULSE_3_REG , RULL(0x2D0F0023), SH_UNT_PERV_45 , SH_ACS_SCOM ); -REG64( PERV_EC14_HANG_PULSE_3_REG , RULL(0x2E0F0023), SH_UNT_PERV_46 , SH_ACS_SCOM ); -REG64( PERV_EC15_HANG_PULSE_3_REG , RULL(0x2F0F0023), SH_UNT_PERV_47 , SH_ACS_SCOM ); -REG64( PERV_EC16_HANG_PULSE_3_REG , RULL(0x300F0023), SH_UNT_PERV_48 , SH_ACS_SCOM ); -REG64( PERV_EC17_HANG_PULSE_3_REG , RULL(0x310F0023), SH_UNT_PERV_49 , SH_ACS_SCOM ); -REG64( PERV_EC18_HANG_PULSE_3_REG , RULL(0x320F0023), SH_UNT_PERV_50 , SH_ACS_SCOM ); -REG64( PERV_EC19_HANG_PULSE_3_REG , RULL(0x330F0023), SH_UNT_PERV_51 , SH_ACS_SCOM ); -REG64( PERV_EC20_HANG_PULSE_3_REG , RULL(0x340F0023), SH_UNT_PERV_52 , SH_ACS_SCOM ); -REG64( PERV_EC21_HANG_PULSE_3_REG , RULL(0x350F0023), SH_UNT_PERV_53 , SH_ACS_SCOM ); -REG64( PERV_EC22_HANG_PULSE_3_REG , RULL(0x360F0023), SH_UNT_PERV_54 , SH_ACS_SCOM ); -REG64( PERV_EC23_HANG_PULSE_3_REG , RULL(0x370F0023), SH_UNT_PERV_55 , SH_ACS_SCOM ); - -REG64( PERV_HANG_PULSE_4_REG , RULL(0x000F0024), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_TP_HANG_PULSE_4_REG , RULL(0x010F0024), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_N0_HANG_PULSE_4_REG , RULL(0x020F0024), SH_UNT_PERV_2 , SH_ACS_SCOM ); -REG64( PERV_N1_HANG_PULSE_4_REG , RULL(0x030F0024), SH_UNT_PERV_3 , SH_ACS_SCOM ); -REG64( PERV_N2_HANG_PULSE_4_REG , RULL(0x040F0024), SH_UNT_PERV_4 , SH_ACS_SCOM ); -REG64( PERV_N3_HANG_PULSE_4_REG , RULL(0x050F0024), SH_UNT_PERV_5 , SH_ACS_SCOM ); -REG64( PERV_XB_HANG_PULSE_4_REG , RULL(0x060F0024), SH_UNT_PERV_6 , SH_ACS_SCOM ); -REG64( PERV_MC01_HANG_PULSE_4_REG , RULL(0x070F0024), SH_UNT_PERV_7 , SH_ACS_SCOM ); -REG64( PERV_MC23_HANG_PULSE_4_REG , RULL(0x080F0024), SH_UNT_PERV_8 , SH_ACS_SCOM ); -REG64( PERV_OB0_HANG_PULSE_4_REG , RULL(0x090F0024), SH_UNT_PERV_9 , SH_ACS_SCOM ); -REG64( PERV_OB3_HANG_PULSE_4_REG , RULL(0x0C0F0024), SH_UNT_PERV_12 , SH_ACS_SCOM ); -REG64( PERV_PCI0_HANG_PULSE_4_REG , RULL(0x0D0F0024), SH_UNT_PERV_13 , SH_ACS_SCOM ); -REG64( PERV_PCI1_HANG_PULSE_4_REG , RULL(0x0E0F0024), SH_UNT_PERV_14 , SH_ACS_SCOM ); -REG64( PERV_PCI2_HANG_PULSE_4_REG , RULL(0x0F0F0024), SH_UNT_PERV_15 , SH_ACS_SCOM ); -REG64( PERV_EP00_HANG_PULSE_4_REG , RULL(0x100F0024), SH_UNT_PERV_16 , SH_ACS_SCOM ); -REG64( PERV_EP01_HANG_PULSE_4_REG , RULL(0x110F0024), SH_UNT_PERV_17 , SH_ACS_SCOM ); -REG64( PERV_EP02_HANG_PULSE_4_REG , RULL(0x120F0024), SH_UNT_PERV_18 , SH_ACS_SCOM ); -REG64( PERV_EP03_HANG_PULSE_4_REG , RULL(0x130F0024), SH_UNT_PERV_19 , SH_ACS_SCOM ); -REG64( PERV_EP04_HANG_PULSE_4_REG , RULL(0x140F0024), SH_UNT_PERV_20 , SH_ACS_SCOM ); -REG64( PERV_EP05_HANG_PULSE_4_REG , RULL(0x150F0024), SH_UNT_PERV_21 , SH_ACS_SCOM ); -REG64( PERV_EC00_HANG_PULSE_4_REG , RULL(0x200F0024), SH_UNT_PERV_32 , SH_ACS_SCOM ); -REG64( PERV_EC01_HANG_PULSE_4_REG , RULL(0x210F0024), SH_UNT_PERV_33 , SH_ACS_SCOM ); -REG64( PERV_EC02_HANG_PULSE_4_REG , RULL(0x220F0024), SH_UNT_PERV_34 , SH_ACS_SCOM ); -REG64( PERV_EC03_HANG_PULSE_4_REG , RULL(0x230F0024), SH_UNT_PERV_35 , SH_ACS_SCOM ); -REG64( PERV_EC04_HANG_PULSE_4_REG , RULL(0x240F0024), SH_UNT_PERV_36 , SH_ACS_SCOM ); -REG64( PERV_EC05_HANG_PULSE_4_REG , RULL(0x250F0024), SH_UNT_PERV_37 , SH_ACS_SCOM ); -REG64( PERV_EC06_HANG_PULSE_4_REG , RULL(0x260F0024), SH_UNT_PERV_38 , SH_ACS_SCOM ); -REG64( PERV_EC07_HANG_PULSE_4_REG , RULL(0x270F0024), SH_UNT_PERV_39 , SH_ACS_SCOM ); -REG64( PERV_EC08_HANG_PULSE_4_REG , RULL(0x280F0024), SH_UNT_PERV_40 , SH_ACS_SCOM ); -REG64( PERV_EC09_HANG_PULSE_4_REG , RULL(0x290F0024), SH_UNT_PERV_41 , SH_ACS_SCOM ); -REG64( PERV_EC10_HANG_PULSE_4_REG , RULL(0x2A0F0024), SH_UNT_PERV_42 , SH_ACS_SCOM ); -REG64( PERV_EC11_HANG_PULSE_4_REG , RULL(0x2B0F0024), SH_UNT_PERV_43 , SH_ACS_SCOM ); -REG64( PERV_EC12_HANG_PULSE_4_REG , RULL(0x2C0F0024), SH_UNT_PERV_44 , SH_ACS_SCOM ); -REG64( PERV_EC13_HANG_PULSE_4_REG , RULL(0x2D0F0024), SH_UNT_PERV_45 , SH_ACS_SCOM ); -REG64( PERV_EC14_HANG_PULSE_4_REG , RULL(0x2E0F0024), SH_UNT_PERV_46 , SH_ACS_SCOM ); -REG64( PERV_EC15_HANG_PULSE_4_REG , RULL(0x2F0F0024), SH_UNT_PERV_47 , SH_ACS_SCOM ); -REG64( PERV_EC16_HANG_PULSE_4_REG , RULL(0x300F0024), SH_UNT_PERV_48 , SH_ACS_SCOM ); -REG64( PERV_EC17_HANG_PULSE_4_REG , RULL(0x310F0024), SH_UNT_PERV_49 , SH_ACS_SCOM ); -REG64( PERV_EC18_HANG_PULSE_4_REG , RULL(0x320F0024), SH_UNT_PERV_50 , SH_ACS_SCOM ); -REG64( PERV_EC19_HANG_PULSE_4_REG , RULL(0x330F0024), SH_UNT_PERV_51 , SH_ACS_SCOM ); -REG64( PERV_EC20_HANG_PULSE_4_REG , RULL(0x340F0024), SH_UNT_PERV_52 , SH_ACS_SCOM ); -REG64( PERV_EC21_HANG_PULSE_4_REG , RULL(0x350F0024), SH_UNT_PERV_53 , SH_ACS_SCOM ); -REG64( PERV_EC22_HANG_PULSE_4_REG , RULL(0x360F0024), SH_UNT_PERV_54 , SH_ACS_SCOM ); -REG64( PERV_EC23_HANG_PULSE_4_REG , RULL(0x370F0024), SH_UNT_PERV_55 , SH_ACS_SCOM ); - -REG64( PERV_HANG_PULSE_5_REG , RULL(0x000F0025), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_TP_HANG_PULSE_5_REG , RULL(0x010F0025), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_N0_HANG_PULSE_5_REG , RULL(0x020F0025), SH_UNT_PERV_2 , SH_ACS_SCOM ); -REG64( PERV_N1_HANG_PULSE_5_REG , RULL(0x030F0025), SH_UNT_PERV_3 , SH_ACS_SCOM ); -REG64( PERV_N2_HANG_PULSE_5_REG , RULL(0x040F0025), SH_UNT_PERV_4 , SH_ACS_SCOM ); -REG64( PERV_N3_HANG_PULSE_5_REG , RULL(0x050F0025), SH_UNT_PERV_5 , SH_ACS_SCOM ); -REG64( PERV_XB_HANG_PULSE_5_REG , RULL(0x060F0025), SH_UNT_PERV_6 , SH_ACS_SCOM ); -REG64( PERV_MC01_HANG_PULSE_5_REG , RULL(0x070F0025), SH_UNT_PERV_7 , SH_ACS_SCOM ); -REG64( PERV_MC23_HANG_PULSE_5_REG , RULL(0x080F0025), SH_UNT_PERV_8 , SH_ACS_SCOM ); -REG64( PERV_OB0_HANG_PULSE_5_REG , RULL(0x090F0025), SH_UNT_PERV_9 , SH_ACS_SCOM ); -REG64( PERV_OB3_HANG_PULSE_5_REG , RULL(0x0C0F0025), SH_UNT_PERV_12 , SH_ACS_SCOM ); -REG64( PERV_PCI0_HANG_PULSE_5_REG , RULL(0x0D0F0025), SH_UNT_PERV_13 , SH_ACS_SCOM ); -REG64( PERV_PCI1_HANG_PULSE_5_REG , RULL(0x0E0F0025), SH_UNT_PERV_14 , SH_ACS_SCOM ); -REG64( PERV_PCI2_HANG_PULSE_5_REG , RULL(0x0F0F0025), SH_UNT_PERV_15 , SH_ACS_SCOM ); -REG64( PERV_EP00_HANG_PULSE_5_REG , RULL(0x100F0025), SH_UNT_PERV_16 , SH_ACS_SCOM ); -REG64( PERV_EP01_HANG_PULSE_5_REG , RULL(0x110F0025), SH_UNT_PERV_17 , SH_ACS_SCOM ); -REG64( PERV_EP02_HANG_PULSE_5_REG , RULL(0x120F0025), SH_UNT_PERV_18 , SH_ACS_SCOM ); -REG64( PERV_EP03_HANG_PULSE_5_REG , RULL(0x130F0025), SH_UNT_PERV_19 , SH_ACS_SCOM ); -REG64( PERV_EP04_HANG_PULSE_5_REG , RULL(0x140F0025), SH_UNT_PERV_20 , SH_ACS_SCOM ); -REG64( PERV_EP05_HANG_PULSE_5_REG , RULL(0x150F0025), SH_UNT_PERV_21 , SH_ACS_SCOM ); -REG64( PERV_EC00_HANG_PULSE_5_REG , RULL(0x200F0025), SH_UNT_PERV_32 , SH_ACS_SCOM ); -REG64( PERV_EC01_HANG_PULSE_5_REG , RULL(0x210F0025), SH_UNT_PERV_33 , SH_ACS_SCOM ); -REG64( PERV_EC02_HANG_PULSE_5_REG , RULL(0x220F0025), SH_UNT_PERV_34 , SH_ACS_SCOM ); -REG64( PERV_EC03_HANG_PULSE_5_REG , RULL(0x230F0025), SH_UNT_PERV_35 , SH_ACS_SCOM ); -REG64( PERV_EC04_HANG_PULSE_5_REG , RULL(0x240F0025), SH_UNT_PERV_36 , SH_ACS_SCOM ); -REG64( PERV_EC05_HANG_PULSE_5_REG , RULL(0x250F0025), SH_UNT_PERV_37 , SH_ACS_SCOM ); -REG64( PERV_EC06_HANG_PULSE_5_REG , RULL(0x260F0025), SH_UNT_PERV_38 , SH_ACS_SCOM ); -REG64( PERV_EC07_HANG_PULSE_5_REG , RULL(0x270F0025), SH_UNT_PERV_39 , SH_ACS_SCOM ); -REG64( PERV_EC08_HANG_PULSE_5_REG , RULL(0x280F0025), SH_UNT_PERV_40 , SH_ACS_SCOM ); -REG64( PERV_EC09_HANG_PULSE_5_REG , RULL(0x290F0025), SH_UNT_PERV_41 , SH_ACS_SCOM ); -REG64( PERV_EC10_HANG_PULSE_5_REG , RULL(0x2A0F0025), SH_UNT_PERV_42 , SH_ACS_SCOM ); -REG64( PERV_EC11_HANG_PULSE_5_REG , RULL(0x2B0F0025), SH_UNT_PERV_43 , SH_ACS_SCOM ); -REG64( PERV_EC12_HANG_PULSE_5_REG , RULL(0x2C0F0025), SH_UNT_PERV_44 , SH_ACS_SCOM ); -REG64( PERV_EC13_HANG_PULSE_5_REG , RULL(0x2D0F0025), SH_UNT_PERV_45 , SH_ACS_SCOM ); -REG64( PERV_EC14_HANG_PULSE_5_REG , RULL(0x2E0F0025), SH_UNT_PERV_46 , SH_ACS_SCOM ); -REG64( PERV_EC15_HANG_PULSE_5_REG , RULL(0x2F0F0025), SH_UNT_PERV_47 , SH_ACS_SCOM ); -REG64( PERV_EC16_HANG_PULSE_5_REG , RULL(0x300F0025), SH_UNT_PERV_48 , SH_ACS_SCOM ); -REG64( PERV_EC17_HANG_PULSE_5_REG , RULL(0x310F0025), SH_UNT_PERV_49 , SH_ACS_SCOM ); -REG64( PERV_EC18_HANG_PULSE_5_REG , RULL(0x320F0025), SH_UNT_PERV_50 , SH_ACS_SCOM ); -REG64( PERV_EC19_HANG_PULSE_5_REG , RULL(0x330F0025), SH_UNT_PERV_51 , SH_ACS_SCOM ); -REG64( PERV_EC20_HANG_PULSE_5_REG , RULL(0x340F0025), SH_UNT_PERV_52 , SH_ACS_SCOM ); -REG64( PERV_EC21_HANG_PULSE_5_REG , RULL(0x350F0025), SH_UNT_PERV_53 , SH_ACS_SCOM ); -REG64( PERV_EC22_HANG_PULSE_5_REG , RULL(0x360F0025), SH_UNT_PERV_54 , SH_ACS_SCOM ); -REG64( PERV_EC23_HANG_PULSE_5_REG , RULL(0x370F0025), SH_UNT_PERV_55 , SH_ACS_SCOM ); - -REG64( PERV_HANG_PULSE_6_REG , RULL(0x000F0026), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_TP_HANG_PULSE_6_REG , RULL(0x010F0026), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_N0_HANG_PULSE_6_REG , RULL(0x020F0026), SH_UNT_PERV_2 , SH_ACS_SCOM ); -REG64( PERV_N1_HANG_PULSE_6_REG , RULL(0x030F0026), SH_UNT_PERV_3 , SH_ACS_SCOM ); -REG64( PERV_N2_HANG_PULSE_6_REG , RULL(0x040F0026), SH_UNT_PERV_4 , SH_ACS_SCOM ); -REG64( PERV_N3_HANG_PULSE_6_REG , RULL(0x050F0026), SH_UNT_PERV_5 , SH_ACS_SCOM ); -REG64( PERV_XB_HANG_PULSE_6_REG , RULL(0x060F0026), SH_UNT_PERV_6 , SH_ACS_SCOM ); -REG64( PERV_MC01_HANG_PULSE_6_REG , RULL(0x070F0026), SH_UNT_PERV_7 , SH_ACS_SCOM ); -REG64( PERV_MC23_HANG_PULSE_6_REG , RULL(0x080F0026), SH_UNT_PERV_8 , SH_ACS_SCOM ); -REG64( PERV_OB0_HANG_PULSE_6_REG , RULL(0x090F0026), SH_UNT_PERV_9 , SH_ACS_SCOM ); -REG64( PERV_OB3_HANG_PULSE_6_REG , RULL(0x0C0F0026), SH_UNT_PERV_12 , SH_ACS_SCOM ); -REG64( PERV_PCI0_HANG_PULSE_6_REG , RULL(0x0D0F0026), SH_UNT_PERV_13 , SH_ACS_SCOM ); -REG64( PERV_PCI1_HANG_PULSE_6_REG , RULL(0x0E0F0026), SH_UNT_PERV_14 , SH_ACS_SCOM ); -REG64( PERV_PCI2_HANG_PULSE_6_REG , RULL(0x0F0F0026), SH_UNT_PERV_15 , SH_ACS_SCOM ); -REG64( PERV_EP00_HANG_PULSE_6_REG , RULL(0x100F0026), SH_UNT_PERV_16 , SH_ACS_SCOM ); -REG64( PERV_EP01_HANG_PULSE_6_REG , RULL(0x110F0026), SH_UNT_PERV_17 , SH_ACS_SCOM ); -REG64( PERV_EP02_HANG_PULSE_6_REG , RULL(0x120F0026), SH_UNT_PERV_18 , SH_ACS_SCOM ); -REG64( PERV_EP03_HANG_PULSE_6_REG , RULL(0x130F0026), SH_UNT_PERV_19 , SH_ACS_SCOM ); -REG64( PERV_EP04_HANG_PULSE_6_REG , RULL(0x140F0026), SH_UNT_PERV_20 , SH_ACS_SCOM ); -REG64( PERV_EP05_HANG_PULSE_6_REG , RULL(0x150F0026), SH_UNT_PERV_21 , SH_ACS_SCOM ); -REG64( PERV_EC00_HANG_PULSE_6_REG , RULL(0x200F0026), SH_UNT_PERV_32 , SH_ACS_SCOM ); -REG64( PERV_EC01_HANG_PULSE_6_REG , RULL(0x210F0026), SH_UNT_PERV_33 , SH_ACS_SCOM ); -REG64( PERV_EC02_HANG_PULSE_6_REG , RULL(0x220F0026), SH_UNT_PERV_34 , SH_ACS_SCOM ); -REG64( PERV_EC03_HANG_PULSE_6_REG , RULL(0x230F0026), SH_UNT_PERV_35 , SH_ACS_SCOM ); -REG64( PERV_EC04_HANG_PULSE_6_REG , RULL(0x240F0026), SH_UNT_PERV_36 , SH_ACS_SCOM ); -REG64( PERV_EC05_HANG_PULSE_6_REG , RULL(0x250F0026), SH_UNT_PERV_37 , SH_ACS_SCOM ); -REG64( PERV_EC06_HANG_PULSE_6_REG , RULL(0x260F0026), SH_UNT_PERV_38 , SH_ACS_SCOM ); -REG64( PERV_EC07_HANG_PULSE_6_REG , RULL(0x270F0026), SH_UNT_PERV_39 , SH_ACS_SCOM ); -REG64( PERV_EC08_HANG_PULSE_6_REG , RULL(0x280F0026), SH_UNT_PERV_40 , SH_ACS_SCOM ); -REG64( PERV_EC09_HANG_PULSE_6_REG , RULL(0x290F0026), SH_UNT_PERV_41 , SH_ACS_SCOM ); -REG64( PERV_EC10_HANG_PULSE_6_REG , RULL(0x2A0F0026), SH_UNT_PERV_42 , SH_ACS_SCOM ); -REG64( PERV_EC11_HANG_PULSE_6_REG , RULL(0x2B0F0026), SH_UNT_PERV_43 , SH_ACS_SCOM ); -REG64( PERV_EC12_HANG_PULSE_6_REG , RULL(0x2C0F0026), SH_UNT_PERV_44 , SH_ACS_SCOM ); -REG64( PERV_EC13_HANG_PULSE_6_REG , RULL(0x2D0F0026), SH_UNT_PERV_45 , SH_ACS_SCOM ); -REG64( PERV_EC14_HANG_PULSE_6_REG , RULL(0x2E0F0026), SH_UNT_PERV_46 , SH_ACS_SCOM ); -REG64( PERV_EC15_HANG_PULSE_6_REG , RULL(0x2F0F0026), SH_UNT_PERV_47 , SH_ACS_SCOM ); -REG64( PERV_EC16_HANG_PULSE_6_REG , RULL(0x300F0026), SH_UNT_PERV_48 , SH_ACS_SCOM ); -REG64( PERV_EC17_HANG_PULSE_6_REG , RULL(0x310F0026), SH_UNT_PERV_49 , SH_ACS_SCOM ); -REG64( PERV_EC18_HANG_PULSE_6_REG , RULL(0x320F0026), SH_UNT_PERV_50 , SH_ACS_SCOM ); -REG64( PERV_EC19_HANG_PULSE_6_REG , RULL(0x330F0026), SH_UNT_PERV_51 , SH_ACS_SCOM ); -REG64( PERV_EC20_HANG_PULSE_6_REG , RULL(0x340F0026), SH_UNT_PERV_52 , SH_ACS_SCOM ); -REG64( PERV_EC21_HANG_PULSE_6_REG , RULL(0x350F0026), SH_UNT_PERV_53 , SH_ACS_SCOM ); -REG64( PERV_EC22_HANG_PULSE_6_REG , RULL(0x360F0026), SH_UNT_PERV_54 , SH_ACS_SCOM ); -REG64( PERV_EC23_HANG_PULSE_6_REG , RULL(0x370F0026), SH_UNT_PERV_55 , SH_ACS_SCOM ); +REG64( PERV_HANG_PULSE_0_REG , RULL(0x000F0020), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_TP_HANG_PULSE_0_REG , RULL(0x010F0020), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_N0_HANG_PULSE_0_REG , RULL(0x020F0020), SH_UNT_PERV_2 , SH_ACS_SCOM_RW ); +REG64( PERV_N1_HANG_PULSE_0_REG , RULL(0x030F0020), SH_UNT_PERV_3 , SH_ACS_SCOM_RW ); +REG64( PERV_N2_HANG_PULSE_0_REG , RULL(0x040F0020), SH_UNT_PERV_4 , SH_ACS_SCOM_RW ); +REG64( PERV_N3_HANG_PULSE_0_REG , RULL(0x050F0020), SH_UNT_PERV_5 , SH_ACS_SCOM_RW ); +REG64( PERV_XB_HANG_PULSE_0_REG , RULL(0x060F0020), SH_UNT_PERV_6 , SH_ACS_SCOM_RW ); +REG64( PERV_MC01_HANG_PULSE_0_REG , RULL(0x070F0020), SH_UNT_PERV_7 , SH_ACS_SCOM_RW ); +REG64( PERV_MC23_HANG_PULSE_0_REG , RULL(0x080F0020), SH_UNT_PERV_8 , SH_ACS_SCOM_RW ); +REG64( PERV_OB0_HANG_PULSE_0_REG , RULL(0x090F0020), SH_UNT_PERV_9 , SH_ACS_SCOM_RW ); +REG64( PERV_OB3_HANG_PULSE_0_REG , RULL(0x0C0F0020), SH_UNT_PERV_12 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI0_HANG_PULSE_0_REG , RULL(0x0D0F0020), SH_UNT_PERV_13 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI1_HANG_PULSE_0_REG , RULL(0x0E0F0020), SH_UNT_PERV_14 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI2_HANG_PULSE_0_REG , RULL(0x0F0F0020), SH_UNT_PERV_15 , SH_ACS_SCOM_RW ); +REG64( PERV_EP00_HANG_PULSE_0_REG , RULL(0x100F0020), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); +REG64( PERV_EP01_HANG_PULSE_0_REG , RULL(0x110F0020), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); +REG64( PERV_EP02_HANG_PULSE_0_REG , RULL(0x120F0020), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); +REG64( PERV_EP03_HANG_PULSE_0_REG , RULL(0x130F0020), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); +REG64( PERV_EP04_HANG_PULSE_0_REG , RULL(0x140F0020), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); +REG64( PERV_EP05_HANG_PULSE_0_REG , RULL(0x150F0020), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); +REG64( PERV_EC00_HANG_PULSE_0_REG , RULL(0x200F0020), SH_UNT_PERV_32 , SH_ACS_SCOM_RW ); +REG64( PERV_EC01_HANG_PULSE_0_REG , RULL(0x210F0020), SH_UNT_PERV_33 , SH_ACS_SCOM_RW ); +REG64( PERV_EC02_HANG_PULSE_0_REG , RULL(0x220F0020), SH_UNT_PERV_34 , SH_ACS_SCOM_RW ); +REG64( PERV_EC03_HANG_PULSE_0_REG , RULL(0x230F0020), SH_UNT_PERV_35 , SH_ACS_SCOM_RW ); +REG64( PERV_EC04_HANG_PULSE_0_REG , RULL(0x240F0020), SH_UNT_PERV_36 , SH_ACS_SCOM_RW ); +REG64( PERV_EC05_HANG_PULSE_0_REG , RULL(0x250F0020), SH_UNT_PERV_37 , SH_ACS_SCOM_RW ); +REG64( PERV_EC06_HANG_PULSE_0_REG , RULL(0x260F0020), SH_UNT_PERV_38 , SH_ACS_SCOM_RW ); +REG64( PERV_EC07_HANG_PULSE_0_REG , RULL(0x270F0020), SH_UNT_PERV_39 , SH_ACS_SCOM_RW ); +REG64( PERV_EC08_HANG_PULSE_0_REG , RULL(0x280F0020), SH_UNT_PERV_40 , SH_ACS_SCOM_RW ); +REG64( PERV_EC09_HANG_PULSE_0_REG , RULL(0x290F0020), SH_UNT_PERV_41 , SH_ACS_SCOM_RW ); +REG64( PERV_EC10_HANG_PULSE_0_REG , RULL(0x2A0F0020), SH_UNT_PERV_42 , SH_ACS_SCOM_RW ); +REG64( PERV_EC11_HANG_PULSE_0_REG , RULL(0x2B0F0020), SH_UNT_PERV_43 , SH_ACS_SCOM_RW ); +REG64( PERV_EC12_HANG_PULSE_0_REG , RULL(0x2C0F0020), SH_UNT_PERV_44 , SH_ACS_SCOM_RW ); +REG64( PERV_EC13_HANG_PULSE_0_REG , RULL(0x2D0F0020), SH_UNT_PERV_45 , SH_ACS_SCOM_RW ); +REG64( PERV_EC14_HANG_PULSE_0_REG , RULL(0x2E0F0020), SH_UNT_PERV_46 , SH_ACS_SCOM_RW ); +REG64( PERV_EC15_HANG_PULSE_0_REG , RULL(0x2F0F0020), SH_UNT_PERV_47 , SH_ACS_SCOM_RW ); +REG64( PERV_EC16_HANG_PULSE_0_REG , RULL(0x300F0020), SH_UNT_PERV_48 , SH_ACS_SCOM_RW ); +REG64( PERV_EC17_HANG_PULSE_0_REG , RULL(0x310F0020), SH_UNT_PERV_49 , SH_ACS_SCOM_RW ); +REG64( PERV_EC18_HANG_PULSE_0_REG , RULL(0x320F0020), SH_UNT_PERV_50 , SH_ACS_SCOM_RW ); +REG64( PERV_EC19_HANG_PULSE_0_REG , RULL(0x330F0020), SH_UNT_PERV_51 , SH_ACS_SCOM_RW ); +REG64( PERV_EC20_HANG_PULSE_0_REG , RULL(0x340F0020), SH_UNT_PERV_52 , SH_ACS_SCOM_RW ); +REG64( PERV_EC21_HANG_PULSE_0_REG , RULL(0x350F0020), SH_UNT_PERV_53 , SH_ACS_SCOM_RW ); +REG64( PERV_EC22_HANG_PULSE_0_REG , RULL(0x360F0020), SH_UNT_PERV_54 , SH_ACS_SCOM_RW ); +REG64( PERV_EC23_HANG_PULSE_0_REG , RULL(0x370F0020), SH_UNT_PERV_55 , SH_ACS_SCOM_RW ); + +REG64( PERV_HANG_PULSE_1_REG , RULL(0x000F0021), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_TP_HANG_PULSE_1_REG , RULL(0x010F0021), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_N0_HANG_PULSE_1_REG , RULL(0x020F0021), SH_UNT_PERV_2 , SH_ACS_SCOM_RW ); +REG64( PERV_N1_HANG_PULSE_1_REG , RULL(0x030F0021), SH_UNT_PERV_3 , SH_ACS_SCOM_RW ); +REG64( PERV_N2_HANG_PULSE_1_REG , RULL(0x040F0021), SH_UNT_PERV_4 , SH_ACS_SCOM_RW ); +REG64( PERV_N3_HANG_PULSE_1_REG , RULL(0x050F0021), SH_UNT_PERV_5 , SH_ACS_SCOM_RW ); +REG64( PERV_XB_HANG_PULSE_1_REG , RULL(0x060F0021), SH_UNT_PERV_6 , SH_ACS_SCOM_RW ); +REG64( PERV_MC01_HANG_PULSE_1_REG , RULL(0x070F0021), SH_UNT_PERV_7 , SH_ACS_SCOM_RW ); +REG64( PERV_MC23_HANG_PULSE_1_REG , RULL(0x080F0021), SH_UNT_PERV_8 , SH_ACS_SCOM_RW ); +REG64( PERV_OB0_HANG_PULSE_1_REG , RULL(0x090F0021), SH_UNT_PERV_9 , SH_ACS_SCOM_RW ); +REG64( PERV_OB3_HANG_PULSE_1_REG , RULL(0x0C0F0021), SH_UNT_PERV_12 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI0_HANG_PULSE_1_REG , RULL(0x0D0F0021), SH_UNT_PERV_13 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI1_HANG_PULSE_1_REG , RULL(0x0E0F0021), SH_UNT_PERV_14 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI2_HANG_PULSE_1_REG , RULL(0x0F0F0021), SH_UNT_PERV_15 , SH_ACS_SCOM_RW ); +REG64( PERV_EP00_HANG_PULSE_1_REG , RULL(0x100F0021), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); +REG64( PERV_EP01_HANG_PULSE_1_REG , RULL(0x110F0021), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); +REG64( PERV_EP02_HANG_PULSE_1_REG , RULL(0x120F0021), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); +REG64( PERV_EP03_HANG_PULSE_1_REG , RULL(0x130F0021), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); +REG64( PERV_EP04_HANG_PULSE_1_REG , RULL(0x140F0021), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); +REG64( PERV_EP05_HANG_PULSE_1_REG , RULL(0x150F0021), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); +REG64( PERV_EC00_HANG_PULSE_1_REG , RULL(0x200F0021), SH_UNT_PERV_32 , SH_ACS_SCOM_RW ); +REG64( PERV_EC01_HANG_PULSE_1_REG , RULL(0x210F0021), SH_UNT_PERV_33 , SH_ACS_SCOM_RW ); +REG64( PERV_EC02_HANG_PULSE_1_REG , RULL(0x220F0021), SH_UNT_PERV_34 , SH_ACS_SCOM_RW ); +REG64( PERV_EC03_HANG_PULSE_1_REG , RULL(0x230F0021), SH_UNT_PERV_35 , SH_ACS_SCOM_RW ); +REG64( PERV_EC04_HANG_PULSE_1_REG , RULL(0x240F0021), SH_UNT_PERV_36 , SH_ACS_SCOM_RW ); +REG64( PERV_EC05_HANG_PULSE_1_REG , RULL(0x250F0021), SH_UNT_PERV_37 , SH_ACS_SCOM_RW ); +REG64( PERV_EC06_HANG_PULSE_1_REG , RULL(0x260F0021), SH_UNT_PERV_38 , SH_ACS_SCOM_RW ); +REG64( PERV_EC07_HANG_PULSE_1_REG , RULL(0x270F0021), SH_UNT_PERV_39 , SH_ACS_SCOM_RW ); +REG64( PERV_EC08_HANG_PULSE_1_REG , RULL(0x280F0021), SH_UNT_PERV_40 , SH_ACS_SCOM_RW ); +REG64( PERV_EC09_HANG_PULSE_1_REG , RULL(0x290F0021), SH_UNT_PERV_41 , SH_ACS_SCOM_RW ); +REG64( PERV_EC10_HANG_PULSE_1_REG , RULL(0x2A0F0021), SH_UNT_PERV_42 , SH_ACS_SCOM_RW ); +REG64( PERV_EC11_HANG_PULSE_1_REG , RULL(0x2B0F0021), SH_UNT_PERV_43 , SH_ACS_SCOM_RW ); +REG64( PERV_EC12_HANG_PULSE_1_REG , RULL(0x2C0F0021), SH_UNT_PERV_44 , SH_ACS_SCOM_RW ); +REG64( PERV_EC13_HANG_PULSE_1_REG , RULL(0x2D0F0021), SH_UNT_PERV_45 , SH_ACS_SCOM_RW ); +REG64( PERV_EC14_HANG_PULSE_1_REG , RULL(0x2E0F0021), SH_UNT_PERV_46 , SH_ACS_SCOM_RW ); +REG64( PERV_EC15_HANG_PULSE_1_REG , RULL(0x2F0F0021), SH_UNT_PERV_47 , SH_ACS_SCOM_RW ); +REG64( PERV_EC16_HANG_PULSE_1_REG , RULL(0x300F0021), SH_UNT_PERV_48 , SH_ACS_SCOM_RW ); +REG64( PERV_EC17_HANG_PULSE_1_REG , RULL(0x310F0021), SH_UNT_PERV_49 , SH_ACS_SCOM_RW ); +REG64( PERV_EC18_HANG_PULSE_1_REG , RULL(0x320F0021), SH_UNT_PERV_50 , SH_ACS_SCOM_RW ); +REG64( PERV_EC19_HANG_PULSE_1_REG , RULL(0x330F0021), SH_UNT_PERV_51 , SH_ACS_SCOM_RW ); +REG64( PERV_EC20_HANG_PULSE_1_REG , RULL(0x340F0021), SH_UNT_PERV_52 , SH_ACS_SCOM_RW ); +REG64( PERV_EC21_HANG_PULSE_1_REG , RULL(0x350F0021), SH_UNT_PERV_53 , SH_ACS_SCOM_RW ); +REG64( PERV_EC22_HANG_PULSE_1_REG , RULL(0x360F0021), SH_UNT_PERV_54 , SH_ACS_SCOM_RW ); +REG64( PERV_EC23_HANG_PULSE_1_REG , RULL(0x370F0021), SH_UNT_PERV_55 , SH_ACS_SCOM_RW ); + +REG64( PERV_HANG_PULSE_2_REG , RULL(0x000F0022), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_TP_HANG_PULSE_2_REG , RULL(0x010F0022), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_N0_HANG_PULSE_2_REG , RULL(0x020F0022), SH_UNT_PERV_2 , SH_ACS_SCOM_RW ); +REG64( PERV_N1_HANG_PULSE_2_REG , RULL(0x030F0022), SH_UNT_PERV_3 , SH_ACS_SCOM_RW ); +REG64( PERV_N2_HANG_PULSE_2_REG , RULL(0x040F0022), SH_UNT_PERV_4 , SH_ACS_SCOM_RW ); +REG64( PERV_N3_HANG_PULSE_2_REG , RULL(0x050F0022), SH_UNT_PERV_5 , SH_ACS_SCOM_RW ); +REG64( PERV_XB_HANG_PULSE_2_REG , RULL(0x060F0022), SH_UNT_PERV_6 , SH_ACS_SCOM_RW ); +REG64( PERV_MC01_HANG_PULSE_2_REG , RULL(0x070F0022), SH_UNT_PERV_7 , SH_ACS_SCOM_RW ); +REG64( PERV_MC23_HANG_PULSE_2_REG , RULL(0x080F0022), SH_UNT_PERV_8 , SH_ACS_SCOM_RW ); +REG64( PERV_OB0_HANG_PULSE_2_REG , RULL(0x090F0022), SH_UNT_PERV_9 , SH_ACS_SCOM_RW ); +REG64( PERV_OB3_HANG_PULSE_2_REG , RULL(0x0C0F0022), SH_UNT_PERV_12 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI0_HANG_PULSE_2_REG , RULL(0x0D0F0022), SH_UNT_PERV_13 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI1_HANG_PULSE_2_REG , RULL(0x0E0F0022), SH_UNT_PERV_14 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI2_HANG_PULSE_2_REG , RULL(0x0F0F0022), SH_UNT_PERV_15 , SH_ACS_SCOM_RW ); +REG64( PERV_EP00_HANG_PULSE_2_REG , RULL(0x100F0022), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); +REG64( PERV_EP01_HANG_PULSE_2_REG , RULL(0x110F0022), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); +REG64( PERV_EP02_HANG_PULSE_2_REG , RULL(0x120F0022), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); +REG64( PERV_EP03_HANG_PULSE_2_REG , RULL(0x130F0022), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); +REG64( PERV_EP04_HANG_PULSE_2_REG , RULL(0x140F0022), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); +REG64( PERV_EP05_HANG_PULSE_2_REG , RULL(0x150F0022), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); +REG64( PERV_EC00_HANG_PULSE_2_REG , RULL(0x200F0022), SH_UNT_PERV_32 , SH_ACS_SCOM_RW ); +REG64( PERV_EC01_HANG_PULSE_2_REG , RULL(0x210F0022), SH_UNT_PERV_33 , SH_ACS_SCOM_RW ); +REG64( PERV_EC02_HANG_PULSE_2_REG , RULL(0x220F0022), SH_UNT_PERV_34 , SH_ACS_SCOM_RW ); +REG64( PERV_EC03_HANG_PULSE_2_REG , RULL(0x230F0022), SH_UNT_PERV_35 , SH_ACS_SCOM_RW ); +REG64( PERV_EC04_HANG_PULSE_2_REG , RULL(0x240F0022), SH_UNT_PERV_36 , SH_ACS_SCOM_RW ); +REG64( PERV_EC05_HANG_PULSE_2_REG , RULL(0x250F0022), SH_UNT_PERV_37 , SH_ACS_SCOM_RW ); +REG64( PERV_EC06_HANG_PULSE_2_REG , RULL(0x260F0022), SH_UNT_PERV_38 , SH_ACS_SCOM_RW ); +REG64( PERV_EC07_HANG_PULSE_2_REG , RULL(0x270F0022), SH_UNT_PERV_39 , SH_ACS_SCOM_RW ); +REG64( PERV_EC08_HANG_PULSE_2_REG , RULL(0x280F0022), SH_UNT_PERV_40 , SH_ACS_SCOM_RW ); +REG64( PERV_EC09_HANG_PULSE_2_REG , RULL(0x290F0022), SH_UNT_PERV_41 , SH_ACS_SCOM_RW ); +REG64( PERV_EC10_HANG_PULSE_2_REG , RULL(0x2A0F0022), SH_UNT_PERV_42 , SH_ACS_SCOM_RW ); +REG64( PERV_EC11_HANG_PULSE_2_REG , RULL(0x2B0F0022), SH_UNT_PERV_43 , SH_ACS_SCOM_RW ); +REG64( PERV_EC12_HANG_PULSE_2_REG , RULL(0x2C0F0022), SH_UNT_PERV_44 , SH_ACS_SCOM_RW ); +REG64( PERV_EC13_HANG_PULSE_2_REG , RULL(0x2D0F0022), SH_UNT_PERV_45 , SH_ACS_SCOM_RW ); +REG64( PERV_EC14_HANG_PULSE_2_REG , RULL(0x2E0F0022), SH_UNT_PERV_46 , SH_ACS_SCOM_RW ); +REG64( PERV_EC15_HANG_PULSE_2_REG , RULL(0x2F0F0022), SH_UNT_PERV_47 , SH_ACS_SCOM_RW ); +REG64( PERV_EC16_HANG_PULSE_2_REG , RULL(0x300F0022), SH_UNT_PERV_48 , SH_ACS_SCOM_RW ); +REG64( PERV_EC17_HANG_PULSE_2_REG , RULL(0x310F0022), SH_UNT_PERV_49 , SH_ACS_SCOM_RW ); +REG64( PERV_EC18_HANG_PULSE_2_REG , RULL(0x320F0022), SH_UNT_PERV_50 , SH_ACS_SCOM_RW ); +REG64( PERV_EC19_HANG_PULSE_2_REG , RULL(0x330F0022), SH_UNT_PERV_51 , SH_ACS_SCOM_RW ); +REG64( PERV_EC20_HANG_PULSE_2_REG , RULL(0x340F0022), SH_UNT_PERV_52 , SH_ACS_SCOM_RW ); +REG64( PERV_EC21_HANG_PULSE_2_REG , RULL(0x350F0022), SH_UNT_PERV_53 , SH_ACS_SCOM_RW ); +REG64( PERV_EC22_HANG_PULSE_2_REG , RULL(0x360F0022), SH_UNT_PERV_54 , SH_ACS_SCOM_RW ); +REG64( PERV_EC23_HANG_PULSE_2_REG , RULL(0x370F0022), SH_UNT_PERV_55 , SH_ACS_SCOM_RW ); + +REG64( PERV_HANG_PULSE_3_REG , RULL(0x000F0023), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_TP_HANG_PULSE_3_REG , RULL(0x010F0023), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_N0_HANG_PULSE_3_REG , RULL(0x020F0023), SH_UNT_PERV_2 , SH_ACS_SCOM_RW ); +REG64( PERV_N1_HANG_PULSE_3_REG , RULL(0x030F0023), SH_UNT_PERV_3 , SH_ACS_SCOM_RW ); +REG64( PERV_N2_HANG_PULSE_3_REG , RULL(0x040F0023), SH_UNT_PERV_4 , SH_ACS_SCOM_RW ); +REG64( PERV_N3_HANG_PULSE_3_REG , RULL(0x050F0023), SH_UNT_PERV_5 , SH_ACS_SCOM_RW ); +REG64( PERV_XB_HANG_PULSE_3_REG , RULL(0x060F0023), SH_UNT_PERV_6 , SH_ACS_SCOM_RW ); +REG64( PERV_MC01_HANG_PULSE_3_REG , RULL(0x070F0023), SH_UNT_PERV_7 , SH_ACS_SCOM_RW ); +REG64( PERV_MC23_HANG_PULSE_3_REG , RULL(0x080F0023), SH_UNT_PERV_8 , SH_ACS_SCOM_RW ); +REG64( PERV_OB0_HANG_PULSE_3_REG , RULL(0x090F0023), SH_UNT_PERV_9 , SH_ACS_SCOM_RW ); +REG64( PERV_OB3_HANG_PULSE_3_REG , RULL(0x0C0F0023), SH_UNT_PERV_12 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI0_HANG_PULSE_3_REG , RULL(0x0D0F0023), SH_UNT_PERV_13 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI1_HANG_PULSE_3_REG , RULL(0x0E0F0023), SH_UNT_PERV_14 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI2_HANG_PULSE_3_REG , RULL(0x0F0F0023), SH_UNT_PERV_15 , SH_ACS_SCOM_RW ); +REG64( PERV_EP00_HANG_PULSE_3_REG , RULL(0x100F0023), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); +REG64( PERV_EP01_HANG_PULSE_3_REG , RULL(0x110F0023), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); +REG64( PERV_EP02_HANG_PULSE_3_REG , RULL(0x120F0023), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); +REG64( PERV_EP03_HANG_PULSE_3_REG , RULL(0x130F0023), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); +REG64( PERV_EP04_HANG_PULSE_3_REG , RULL(0x140F0023), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); +REG64( PERV_EP05_HANG_PULSE_3_REG , RULL(0x150F0023), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); +REG64( PERV_EC00_HANG_PULSE_3_REG , RULL(0x200F0023), SH_UNT_PERV_32 , SH_ACS_SCOM_RW ); +REG64( PERV_EC01_HANG_PULSE_3_REG , RULL(0x210F0023), SH_UNT_PERV_33 , SH_ACS_SCOM_RW ); +REG64( PERV_EC02_HANG_PULSE_3_REG , RULL(0x220F0023), SH_UNT_PERV_34 , SH_ACS_SCOM_RW ); +REG64( PERV_EC03_HANG_PULSE_3_REG , RULL(0x230F0023), SH_UNT_PERV_35 , SH_ACS_SCOM_RW ); +REG64( PERV_EC04_HANG_PULSE_3_REG , RULL(0x240F0023), SH_UNT_PERV_36 , SH_ACS_SCOM_RW ); +REG64( PERV_EC05_HANG_PULSE_3_REG , RULL(0x250F0023), SH_UNT_PERV_37 , SH_ACS_SCOM_RW ); +REG64( PERV_EC06_HANG_PULSE_3_REG , RULL(0x260F0023), SH_UNT_PERV_38 , SH_ACS_SCOM_RW ); +REG64( PERV_EC07_HANG_PULSE_3_REG , RULL(0x270F0023), SH_UNT_PERV_39 , SH_ACS_SCOM_RW ); +REG64( PERV_EC08_HANG_PULSE_3_REG , RULL(0x280F0023), SH_UNT_PERV_40 , SH_ACS_SCOM_RW ); +REG64( PERV_EC09_HANG_PULSE_3_REG , RULL(0x290F0023), SH_UNT_PERV_41 , SH_ACS_SCOM_RW ); +REG64( PERV_EC10_HANG_PULSE_3_REG , RULL(0x2A0F0023), SH_UNT_PERV_42 , SH_ACS_SCOM_RW ); +REG64( PERV_EC11_HANG_PULSE_3_REG , RULL(0x2B0F0023), SH_UNT_PERV_43 , SH_ACS_SCOM_RW ); +REG64( PERV_EC12_HANG_PULSE_3_REG , RULL(0x2C0F0023), SH_UNT_PERV_44 , SH_ACS_SCOM_RW ); +REG64( PERV_EC13_HANG_PULSE_3_REG , RULL(0x2D0F0023), SH_UNT_PERV_45 , SH_ACS_SCOM_RW ); +REG64( PERV_EC14_HANG_PULSE_3_REG , RULL(0x2E0F0023), SH_UNT_PERV_46 , SH_ACS_SCOM_RW ); +REG64( PERV_EC15_HANG_PULSE_3_REG , RULL(0x2F0F0023), SH_UNT_PERV_47 , SH_ACS_SCOM_RW ); +REG64( PERV_EC16_HANG_PULSE_3_REG , RULL(0x300F0023), SH_UNT_PERV_48 , SH_ACS_SCOM_RW ); +REG64( PERV_EC17_HANG_PULSE_3_REG , RULL(0x310F0023), SH_UNT_PERV_49 , SH_ACS_SCOM_RW ); +REG64( PERV_EC18_HANG_PULSE_3_REG , RULL(0x320F0023), SH_UNT_PERV_50 , SH_ACS_SCOM_RW ); +REG64( PERV_EC19_HANG_PULSE_3_REG , RULL(0x330F0023), SH_UNT_PERV_51 , SH_ACS_SCOM_RW ); +REG64( PERV_EC20_HANG_PULSE_3_REG , RULL(0x340F0023), SH_UNT_PERV_52 , SH_ACS_SCOM_RW ); +REG64( PERV_EC21_HANG_PULSE_3_REG , RULL(0x350F0023), SH_UNT_PERV_53 , SH_ACS_SCOM_RW ); +REG64( PERV_EC22_HANG_PULSE_3_REG , RULL(0x360F0023), SH_UNT_PERV_54 , SH_ACS_SCOM_RW ); +REG64( PERV_EC23_HANG_PULSE_3_REG , RULL(0x370F0023), SH_UNT_PERV_55 , SH_ACS_SCOM_RW ); + +REG64( PERV_HANG_PULSE_4_REG , RULL(0x000F0024), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_TP_HANG_PULSE_4_REG , RULL(0x010F0024), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_N0_HANG_PULSE_4_REG , RULL(0x020F0024), SH_UNT_PERV_2 , SH_ACS_SCOM_RW ); +REG64( PERV_N1_HANG_PULSE_4_REG , RULL(0x030F0024), SH_UNT_PERV_3 , SH_ACS_SCOM_RW ); +REG64( PERV_N2_HANG_PULSE_4_REG , RULL(0x040F0024), SH_UNT_PERV_4 , SH_ACS_SCOM_RW ); +REG64( PERV_N3_HANG_PULSE_4_REG , RULL(0x050F0024), SH_UNT_PERV_5 , SH_ACS_SCOM_RW ); +REG64( PERV_XB_HANG_PULSE_4_REG , RULL(0x060F0024), SH_UNT_PERV_6 , SH_ACS_SCOM_RW ); +REG64( PERV_MC01_HANG_PULSE_4_REG , RULL(0x070F0024), SH_UNT_PERV_7 , SH_ACS_SCOM_RW ); +REG64( PERV_MC23_HANG_PULSE_4_REG , RULL(0x080F0024), SH_UNT_PERV_8 , SH_ACS_SCOM_RW ); +REG64( PERV_OB0_HANG_PULSE_4_REG , RULL(0x090F0024), SH_UNT_PERV_9 , SH_ACS_SCOM_RW ); +REG64( PERV_OB3_HANG_PULSE_4_REG , RULL(0x0C0F0024), SH_UNT_PERV_12 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI0_HANG_PULSE_4_REG , RULL(0x0D0F0024), SH_UNT_PERV_13 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI1_HANG_PULSE_4_REG , RULL(0x0E0F0024), SH_UNT_PERV_14 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI2_HANG_PULSE_4_REG , RULL(0x0F0F0024), SH_UNT_PERV_15 , SH_ACS_SCOM_RW ); +REG64( PERV_EP00_HANG_PULSE_4_REG , RULL(0x100F0024), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); +REG64( PERV_EP01_HANG_PULSE_4_REG , RULL(0x110F0024), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); +REG64( PERV_EP02_HANG_PULSE_4_REG , RULL(0x120F0024), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); +REG64( PERV_EP03_HANG_PULSE_4_REG , RULL(0x130F0024), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); +REG64( PERV_EP04_HANG_PULSE_4_REG , RULL(0x140F0024), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); +REG64( PERV_EP05_HANG_PULSE_4_REG , RULL(0x150F0024), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); +REG64( PERV_EC00_HANG_PULSE_4_REG , RULL(0x200F0024), SH_UNT_PERV_32 , SH_ACS_SCOM_RW ); +REG64( PERV_EC01_HANG_PULSE_4_REG , RULL(0x210F0024), SH_UNT_PERV_33 , SH_ACS_SCOM_RW ); +REG64( PERV_EC02_HANG_PULSE_4_REG , RULL(0x220F0024), SH_UNT_PERV_34 , SH_ACS_SCOM_RW ); +REG64( PERV_EC03_HANG_PULSE_4_REG , RULL(0x230F0024), SH_UNT_PERV_35 , SH_ACS_SCOM_RW ); +REG64( PERV_EC04_HANG_PULSE_4_REG , RULL(0x240F0024), SH_UNT_PERV_36 , SH_ACS_SCOM_RW ); +REG64( PERV_EC05_HANG_PULSE_4_REG , RULL(0x250F0024), SH_UNT_PERV_37 , SH_ACS_SCOM_RW ); +REG64( PERV_EC06_HANG_PULSE_4_REG , RULL(0x260F0024), SH_UNT_PERV_38 , SH_ACS_SCOM_RW ); +REG64( PERV_EC07_HANG_PULSE_4_REG , RULL(0x270F0024), SH_UNT_PERV_39 , SH_ACS_SCOM_RW ); +REG64( PERV_EC08_HANG_PULSE_4_REG , RULL(0x280F0024), SH_UNT_PERV_40 , SH_ACS_SCOM_RW ); +REG64( PERV_EC09_HANG_PULSE_4_REG , RULL(0x290F0024), SH_UNT_PERV_41 , SH_ACS_SCOM_RW ); +REG64( PERV_EC10_HANG_PULSE_4_REG , RULL(0x2A0F0024), SH_UNT_PERV_42 , SH_ACS_SCOM_RW ); +REG64( PERV_EC11_HANG_PULSE_4_REG , RULL(0x2B0F0024), SH_UNT_PERV_43 , SH_ACS_SCOM_RW ); +REG64( PERV_EC12_HANG_PULSE_4_REG , RULL(0x2C0F0024), SH_UNT_PERV_44 , SH_ACS_SCOM_RW ); +REG64( PERV_EC13_HANG_PULSE_4_REG , RULL(0x2D0F0024), SH_UNT_PERV_45 , SH_ACS_SCOM_RW ); +REG64( PERV_EC14_HANG_PULSE_4_REG , RULL(0x2E0F0024), SH_UNT_PERV_46 , SH_ACS_SCOM_RW ); +REG64( PERV_EC15_HANG_PULSE_4_REG , RULL(0x2F0F0024), SH_UNT_PERV_47 , SH_ACS_SCOM_RW ); +REG64( PERV_EC16_HANG_PULSE_4_REG , RULL(0x300F0024), SH_UNT_PERV_48 , SH_ACS_SCOM_RW ); +REG64( PERV_EC17_HANG_PULSE_4_REG , RULL(0x310F0024), SH_UNT_PERV_49 , SH_ACS_SCOM_RW ); +REG64( PERV_EC18_HANG_PULSE_4_REG , RULL(0x320F0024), SH_UNT_PERV_50 , SH_ACS_SCOM_RW ); +REG64( PERV_EC19_HANG_PULSE_4_REG , RULL(0x330F0024), SH_UNT_PERV_51 , SH_ACS_SCOM_RW ); +REG64( PERV_EC20_HANG_PULSE_4_REG , RULL(0x340F0024), SH_UNT_PERV_52 , SH_ACS_SCOM_RW ); +REG64( PERV_EC21_HANG_PULSE_4_REG , RULL(0x350F0024), SH_UNT_PERV_53 , SH_ACS_SCOM_RW ); +REG64( PERV_EC22_HANG_PULSE_4_REG , RULL(0x360F0024), SH_UNT_PERV_54 , SH_ACS_SCOM_RW ); +REG64( PERV_EC23_HANG_PULSE_4_REG , RULL(0x370F0024), SH_UNT_PERV_55 , SH_ACS_SCOM_RW ); + +REG64( PERV_HANG_PULSE_5_REG , RULL(0x000F0025), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_TP_HANG_PULSE_5_REG , RULL(0x010F0025), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_N0_HANG_PULSE_5_REG , RULL(0x020F0025), SH_UNT_PERV_2 , SH_ACS_SCOM_RW ); +REG64( PERV_N1_HANG_PULSE_5_REG , RULL(0x030F0025), SH_UNT_PERV_3 , SH_ACS_SCOM_RW ); +REG64( PERV_N2_HANG_PULSE_5_REG , RULL(0x040F0025), SH_UNT_PERV_4 , SH_ACS_SCOM_RW ); +REG64( PERV_N3_HANG_PULSE_5_REG , RULL(0x050F0025), SH_UNT_PERV_5 , SH_ACS_SCOM_RW ); +REG64( PERV_XB_HANG_PULSE_5_REG , RULL(0x060F0025), SH_UNT_PERV_6 , SH_ACS_SCOM_RW ); +REG64( PERV_MC01_HANG_PULSE_5_REG , RULL(0x070F0025), SH_UNT_PERV_7 , SH_ACS_SCOM_RW ); +REG64( PERV_MC23_HANG_PULSE_5_REG , RULL(0x080F0025), SH_UNT_PERV_8 , SH_ACS_SCOM_RW ); +REG64( PERV_OB0_HANG_PULSE_5_REG , RULL(0x090F0025), SH_UNT_PERV_9 , SH_ACS_SCOM_RW ); +REG64( PERV_OB3_HANG_PULSE_5_REG , RULL(0x0C0F0025), SH_UNT_PERV_12 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI0_HANG_PULSE_5_REG , RULL(0x0D0F0025), SH_UNT_PERV_13 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI1_HANG_PULSE_5_REG , RULL(0x0E0F0025), SH_UNT_PERV_14 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI2_HANG_PULSE_5_REG , RULL(0x0F0F0025), SH_UNT_PERV_15 , SH_ACS_SCOM_RW ); +REG64( PERV_EP00_HANG_PULSE_5_REG , RULL(0x100F0025), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); +REG64( PERV_EP01_HANG_PULSE_5_REG , RULL(0x110F0025), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); +REG64( PERV_EP02_HANG_PULSE_5_REG , RULL(0x120F0025), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); +REG64( PERV_EP03_HANG_PULSE_5_REG , RULL(0x130F0025), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); +REG64( PERV_EP04_HANG_PULSE_5_REG , RULL(0x140F0025), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); +REG64( PERV_EP05_HANG_PULSE_5_REG , RULL(0x150F0025), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); +REG64( PERV_EC00_HANG_PULSE_5_REG , RULL(0x200F0025), SH_UNT_PERV_32 , SH_ACS_SCOM_RW ); +REG64( PERV_EC01_HANG_PULSE_5_REG , RULL(0x210F0025), SH_UNT_PERV_33 , SH_ACS_SCOM_RW ); +REG64( PERV_EC02_HANG_PULSE_5_REG , RULL(0x220F0025), SH_UNT_PERV_34 , SH_ACS_SCOM_RW ); +REG64( PERV_EC03_HANG_PULSE_5_REG , RULL(0x230F0025), SH_UNT_PERV_35 , SH_ACS_SCOM_RW ); +REG64( PERV_EC04_HANG_PULSE_5_REG , RULL(0x240F0025), SH_UNT_PERV_36 , SH_ACS_SCOM_RW ); +REG64( PERV_EC05_HANG_PULSE_5_REG , RULL(0x250F0025), SH_UNT_PERV_37 , SH_ACS_SCOM_RW ); +REG64( PERV_EC06_HANG_PULSE_5_REG , RULL(0x260F0025), SH_UNT_PERV_38 , SH_ACS_SCOM_RW ); +REG64( PERV_EC07_HANG_PULSE_5_REG , RULL(0x270F0025), SH_UNT_PERV_39 , SH_ACS_SCOM_RW ); +REG64( PERV_EC08_HANG_PULSE_5_REG , RULL(0x280F0025), SH_UNT_PERV_40 , SH_ACS_SCOM_RW ); +REG64( PERV_EC09_HANG_PULSE_5_REG , RULL(0x290F0025), SH_UNT_PERV_41 , SH_ACS_SCOM_RW ); +REG64( PERV_EC10_HANG_PULSE_5_REG , RULL(0x2A0F0025), SH_UNT_PERV_42 , SH_ACS_SCOM_RW ); +REG64( PERV_EC11_HANG_PULSE_5_REG , RULL(0x2B0F0025), SH_UNT_PERV_43 , SH_ACS_SCOM_RW ); +REG64( PERV_EC12_HANG_PULSE_5_REG , RULL(0x2C0F0025), SH_UNT_PERV_44 , SH_ACS_SCOM_RW ); +REG64( PERV_EC13_HANG_PULSE_5_REG , RULL(0x2D0F0025), SH_UNT_PERV_45 , SH_ACS_SCOM_RW ); +REG64( PERV_EC14_HANG_PULSE_5_REG , RULL(0x2E0F0025), SH_UNT_PERV_46 , SH_ACS_SCOM_RW ); +REG64( PERV_EC15_HANG_PULSE_5_REG , RULL(0x2F0F0025), SH_UNT_PERV_47 , SH_ACS_SCOM_RW ); +REG64( PERV_EC16_HANG_PULSE_5_REG , RULL(0x300F0025), SH_UNT_PERV_48 , SH_ACS_SCOM_RW ); +REG64( PERV_EC17_HANG_PULSE_5_REG , RULL(0x310F0025), SH_UNT_PERV_49 , SH_ACS_SCOM_RW ); +REG64( PERV_EC18_HANG_PULSE_5_REG , RULL(0x320F0025), SH_UNT_PERV_50 , SH_ACS_SCOM_RW ); +REG64( PERV_EC19_HANG_PULSE_5_REG , RULL(0x330F0025), SH_UNT_PERV_51 , SH_ACS_SCOM_RW ); +REG64( PERV_EC20_HANG_PULSE_5_REG , RULL(0x340F0025), SH_UNT_PERV_52 , SH_ACS_SCOM_RW ); +REG64( PERV_EC21_HANG_PULSE_5_REG , RULL(0x350F0025), SH_UNT_PERV_53 , SH_ACS_SCOM_RW ); +REG64( PERV_EC22_HANG_PULSE_5_REG , RULL(0x360F0025), SH_UNT_PERV_54 , SH_ACS_SCOM_RW ); +REG64( PERV_EC23_HANG_PULSE_5_REG , RULL(0x370F0025), SH_UNT_PERV_55 , SH_ACS_SCOM_RW ); + +REG64( PERV_HANG_PULSE_6_REG , RULL(0x000F0026), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_TP_HANG_PULSE_6_REG , RULL(0x010F0026), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_N0_HANG_PULSE_6_REG , RULL(0x020F0026), SH_UNT_PERV_2 , SH_ACS_SCOM_RW ); +REG64( PERV_N1_HANG_PULSE_6_REG , RULL(0x030F0026), SH_UNT_PERV_3 , SH_ACS_SCOM_RW ); +REG64( PERV_N2_HANG_PULSE_6_REG , RULL(0x040F0026), SH_UNT_PERV_4 , SH_ACS_SCOM_RW ); +REG64( PERV_N3_HANG_PULSE_6_REG , RULL(0x050F0026), SH_UNT_PERV_5 , SH_ACS_SCOM_RW ); +REG64( PERV_XB_HANG_PULSE_6_REG , RULL(0x060F0026), SH_UNT_PERV_6 , SH_ACS_SCOM_RW ); +REG64( PERV_MC01_HANG_PULSE_6_REG , RULL(0x070F0026), SH_UNT_PERV_7 , SH_ACS_SCOM_RW ); +REG64( PERV_MC23_HANG_PULSE_6_REG , RULL(0x080F0026), SH_UNT_PERV_8 , SH_ACS_SCOM_RW ); +REG64( PERV_OB0_HANG_PULSE_6_REG , RULL(0x090F0026), SH_UNT_PERV_9 , SH_ACS_SCOM_RW ); +REG64( PERV_OB3_HANG_PULSE_6_REG , RULL(0x0C0F0026), SH_UNT_PERV_12 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI0_HANG_PULSE_6_REG , RULL(0x0D0F0026), SH_UNT_PERV_13 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI1_HANG_PULSE_6_REG , RULL(0x0E0F0026), SH_UNT_PERV_14 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI2_HANG_PULSE_6_REG , RULL(0x0F0F0026), SH_UNT_PERV_15 , SH_ACS_SCOM_RW ); +REG64( PERV_EP00_HANG_PULSE_6_REG , RULL(0x100F0026), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); +REG64( PERV_EP01_HANG_PULSE_6_REG , RULL(0x110F0026), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); +REG64( PERV_EP02_HANG_PULSE_6_REG , RULL(0x120F0026), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); +REG64( PERV_EP03_HANG_PULSE_6_REG , RULL(0x130F0026), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); +REG64( PERV_EP04_HANG_PULSE_6_REG , RULL(0x140F0026), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); +REG64( PERV_EP05_HANG_PULSE_6_REG , RULL(0x150F0026), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); +REG64( PERV_EC00_HANG_PULSE_6_REG , RULL(0x200F0026), SH_UNT_PERV_32 , SH_ACS_SCOM_RW ); +REG64( PERV_EC01_HANG_PULSE_6_REG , RULL(0x210F0026), SH_UNT_PERV_33 , SH_ACS_SCOM_RW ); +REG64( PERV_EC02_HANG_PULSE_6_REG , RULL(0x220F0026), SH_UNT_PERV_34 , SH_ACS_SCOM_RW ); +REG64( PERV_EC03_HANG_PULSE_6_REG , RULL(0x230F0026), SH_UNT_PERV_35 , SH_ACS_SCOM_RW ); +REG64( PERV_EC04_HANG_PULSE_6_REG , RULL(0x240F0026), SH_UNT_PERV_36 , SH_ACS_SCOM_RW ); +REG64( PERV_EC05_HANG_PULSE_6_REG , RULL(0x250F0026), SH_UNT_PERV_37 , SH_ACS_SCOM_RW ); +REG64( PERV_EC06_HANG_PULSE_6_REG , RULL(0x260F0026), SH_UNT_PERV_38 , SH_ACS_SCOM_RW ); +REG64( PERV_EC07_HANG_PULSE_6_REG , RULL(0x270F0026), SH_UNT_PERV_39 , SH_ACS_SCOM_RW ); +REG64( PERV_EC08_HANG_PULSE_6_REG , RULL(0x280F0026), SH_UNT_PERV_40 , SH_ACS_SCOM_RW ); +REG64( PERV_EC09_HANG_PULSE_6_REG , RULL(0x290F0026), SH_UNT_PERV_41 , SH_ACS_SCOM_RW ); +REG64( PERV_EC10_HANG_PULSE_6_REG , RULL(0x2A0F0026), SH_UNT_PERV_42 , SH_ACS_SCOM_RW ); +REG64( PERV_EC11_HANG_PULSE_6_REG , RULL(0x2B0F0026), SH_UNT_PERV_43 , SH_ACS_SCOM_RW ); +REG64( PERV_EC12_HANG_PULSE_6_REG , RULL(0x2C0F0026), SH_UNT_PERV_44 , SH_ACS_SCOM_RW ); +REG64( PERV_EC13_HANG_PULSE_6_REG , RULL(0x2D0F0026), SH_UNT_PERV_45 , SH_ACS_SCOM_RW ); +REG64( PERV_EC14_HANG_PULSE_6_REG , RULL(0x2E0F0026), SH_UNT_PERV_46 , SH_ACS_SCOM_RW ); +REG64( PERV_EC15_HANG_PULSE_6_REG , RULL(0x2F0F0026), SH_UNT_PERV_47 , SH_ACS_SCOM_RW ); +REG64( PERV_EC16_HANG_PULSE_6_REG , RULL(0x300F0026), SH_UNT_PERV_48 , SH_ACS_SCOM_RW ); +REG64( PERV_EC17_HANG_PULSE_6_REG , RULL(0x310F0026), SH_UNT_PERV_49 , SH_ACS_SCOM_RW ); +REG64( PERV_EC18_HANG_PULSE_6_REG , RULL(0x320F0026), SH_UNT_PERV_50 , SH_ACS_SCOM_RW ); +REG64( PERV_EC19_HANG_PULSE_6_REG , RULL(0x330F0026), SH_UNT_PERV_51 , SH_ACS_SCOM_RW ); +REG64( PERV_EC20_HANG_PULSE_6_REG , RULL(0x340F0026), SH_UNT_PERV_52 , SH_ACS_SCOM_RW ); +REG64( PERV_EC21_HANG_PULSE_6_REG , RULL(0x350F0026), SH_UNT_PERV_53 , SH_ACS_SCOM_RW ); +REG64( PERV_EC22_HANG_PULSE_6_REG , RULL(0x360F0026), SH_UNT_PERV_54 , SH_ACS_SCOM_RW ); +REG64( PERV_EC23_HANG_PULSE_6_REG , RULL(0x370F0026), SH_UNT_PERV_55 , SH_ACS_SCOM_RW ); REG64( PERV_HEARTBEAT_REG , RULL(0x000F0018), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_TP_HEARTBEAT_REG , RULL(0x010F0018), SH_UNT_PERV_1 , SH_ACS_SCOM ); @@ -4847,40 +4970,135 @@ REG64( PERV_EC21_HEARTBEAT_REG , RULL(0x350F0018 REG64( PERV_EC22_HEARTBEAT_REG , RULL(0x360F0018), SH_UNT_PERV_54 , SH_ACS_SCOM ); REG64( PERV_EC23_HEARTBEAT_REG , RULL(0x370F0018), SH_UNT_PERV_55 , SH_ACS_SCOM ); +REG64( PERV_HOSTATTN , RULL(0x00040009), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); +REG64( PERV_TP_HOSTATTN , RULL(0x01040009), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); +REG64( PERV_N0_HOSTATTN , RULL(0x02040009), SH_UNT_PERV_2 , SH_ACS_SCOM_RO ); +REG64( PERV_N1_HOSTATTN , RULL(0x03040009), SH_UNT_PERV_3 , SH_ACS_SCOM_RO ); +REG64( PERV_N2_HOSTATTN , RULL(0x04040009), SH_UNT_PERV_4 , SH_ACS_SCOM_RO ); +REG64( PERV_N3_HOSTATTN , RULL(0x05040009), SH_UNT_PERV_5 , SH_ACS_SCOM_RO ); +REG64( PERV_XB_HOSTATTN , RULL(0x06040009), SH_UNT_PERV_6 , SH_ACS_SCOM_RO ); +REG64( PERV_MC01_HOSTATTN , RULL(0x07040009), SH_UNT_PERV_7 , SH_ACS_SCOM_RO ); +REG64( PERV_MC23_HOSTATTN , RULL(0x08040009), SH_UNT_PERV_8 , SH_ACS_SCOM_RO ); +REG64( PERV_OB0_HOSTATTN , RULL(0x09040009), SH_UNT_PERV_9 , SH_ACS_SCOM_RO ); +REG64( PERV_OB3_HOSTATTN , RULL(0x0C040009), SH_UNT_PERV_12 , SH_ACS_SCOM_RO ); +REG64( PERV_PCI0_HOSTATTN , RULL(0x0D040009), SH_UNT_PERV_13 , SH_ACS_SCOM_RO ); +REG64( PERV_PCI1_HOSTATTN , RULL(0x0E040009), SH_UNT_PERV_14 , SH_ACS_SCOM_RO ); +REG64( PERV_PCI2_HOSTATTN , RULL(0x0F040009), SH_UNT_PERV_15 , SH_ACS_SCOM_RO ); +REG64( PERV_EP00_HOSTATTN , RULL(0x10040009), SH_UNT_PERV_16 , SH_ACS_SCOM_RO ); +REG64( PERV_EP01_HOSTATTN , RULL(0x11040009), SH_UNT_PERV_17 , SH_ACS_SCOM_RO ); +REG64( PERV_EP02_HOSTATTN , RULL(0x12040009), SH_UNT_PERV_18 , SH_ACS_SCOM_RO ); +REG64( PERV_EP03_HOSTATTN , RULL(0x13040009), SH_UNT_PERV_19 , SH_ACS_SCOM_RO ); +REG64( PERV_EP04_HOSTATTN , RULL(0x14040009), SH_UNT_PERV_20 , SH_ACS_SCOM_RO ); +REG64( PERV_EP05_HOSTATTN , RULL(0x15040009), SH_UNT_PERV_21 , SH_ACS_SCOM_RO ); +REG64( PERV_EC00_HOSTATTN , RULL(0x20040009), SH_UNT_PERV_32 , SH_ACS_SCOM_RO ); +REG64( PERV_EC01_HOSTATTN , RULL(0x21040009), SH_UNT_PERV_33 , SH_ACS_SCOM_RO ); +REG64( PERV_EC02_HOSTATTN , RULL(0x22040009), SH_UNT_PERV_34 , SH_ACS_SCOM_RO ); +REG64( PERV_EC03_HOSTATTN , RULL(0x23040009), SH_UNT_PERV_35 , SH_ACS_SCOM_RO ); +REG64( PERV_EC04_HOSTATTN , RULL(0x24040009), SH_UNT_PERV_36 , SH_ACS_SCOM_RO ); +REG64( PERV_EC05_HOSTATTN , RULL(0x25040009), SH_UNT_PERV_37 , SH_ACS_SCOM_RO ); +REG64( PERV_EC06_HOSTATTN , RULL(0x26040009), SH_UNT_PERV_38 , SH_ACS_SCOM_RO ); +REG64( PERV_EC07_HOSTATTN , RULL(0x27040009), SH_UNT_PERV_39 , SH_ACS_SCOM_RO ); +REG64( PERV_EC08_HOSTATTN , RULL(0x28040009), SH_UNT_PERV_40 , SH_ACS_SCOM_RO ); +REG64( PERV_EC09_HOSTATTN , RULL(0x29040009), SH_UNT_PERV_41 , SH_ACS_SCOM_RO ); +REG64( PERV_EC10_HOSTATTN , RULL(0x2A040009), SH_UNT_PERV_42 , SH_ACS_SCOM_RO ); +REG64( PERV_EC11_HOSTATTN , RULL(0x2B040009), SH_UNT_PERV_43 , SH_ACS_SCOM_RO ); +REG64( PERV_EC12_HOSTATTN , RULL(0x2C040009), SH_UNT_PERV_44 , SH_ACS_SCOM_RO ); +REG64( PERV_EC13_HOSTATTN , RULL(0x2D040009), SH_UNT_PERV_45 , SH_ACS_SCOM_RO ); +REG64( PERV_EC14_HOSTATTN , RULL(0x2E040009), SH_UNT_PERV_46 , SH_ACS_SCOM_RO ); +REG64( PERV_EC15_HOSTATTN , RULL(0x2F040009), SH_UNT_PERV_47 , SH_ACS_SCOM_RO ); +REG64( PERV_EC16_HOSTATTN , RULL(0x30040009), SH_UNT_PERV_48 , SH_ACS_SCOM_RO ); +REG64( PERV_EC17_HOSTATTN , RULL(0x31040009), SH_UNT_PERV_49 , SH_ACS_SCOM_RO ); +REG64( PERV_EC18_HOSTATTN , RULL(0x32040009), SH_UNT_PERV_50 , SH_ACS_SCOM_RO ); +REG64( PERV_EC19_HOSTATTN , RULL(0x33040009), SH_UNT_PERV_51 , SH_ACS_SCOM_RO ); +REG64( PERV_EC20_HOSTATTN , RULL(0x34040009), SH_UNT_PERV_52 , SH_ACS_SCOM_RO ); +REG64( PERV_EC21_HOSTATTN , RULL(0x35040009), SH_UNT_PERV_53 , SH_ACS_SCOM_RO ); +REG64( PERV_EC22_HOSTATTN , RULL(0x36040009), SH_UNT_PERV_54 , SH_ACS_SCOM_RO ); +REG64( PERV_EC23_HOSTATTN , RULL(0x37040009), SH_UNT_PERV_55 , SH_ACS_SCOM_RO ); + +REG64( PERV_HOSTATTN_MASK , RULL(0x00040020), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_HOSTATTN_MASK , RULL(0x01040020), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_N0_HOSTATTN_MASK , RULL(0x02040020), SH_UNT_PERV_2 , SH_ACS_SCOM ); +REG64( PERV_N1_HOSTATTN_MASK , RULL(0x03040020), SH_UNT_PERV_3 , SH_ACS_SCOM ); +REG64( PERV_N2_HOSTATTN_MASK , RULL(0x04040020), SH_UNT_PERV_4 , SH_ACS_SCOM ); +REG64( PERV_N3_HOSTATTN_MASK , RULL(0x05040020), SH_UNT_PERV_5 , SH_ACS_SCOM ); +REG64( PERV_XB_HOSTATTN_MASK , RULL(0x06040020), SH_UNT_PERV_6 , SH_ACS_SCOM ); +REG64( PERV_MC01_HOSTATTN_MASK , RULL(0x07040020), SH_UNT_PERV_7 , SH_ACS_SCOM ); +REG64( PERV_MC23_HOSTATTN_MASK , RULL(0x08040020), SH_UNT_PERV_8 , SH_ACS_SCOM ); +REG64( PERV_OB0_HOSTATTN_MASK , RULL(0x09040020), SH_UNT_PERV_9 , SH_ACS_SCOM ); +REG64( PERV_OB3_HOSTATTN_MASK , RULL(0x0C040020), SH_UNT_PERV_12 , SH_ACS_SCOM ); +REG64( PERV_PCI0_HOSTATTN_MASK , RULL(0x0D040020), SH_UNT_PERV_13 , SH_ACS_SCOM ); +REG64( PERV_PCI1_HOSTATTN_MASK , RULL(0x0E040020), SH_UNT_PERV_14 , SH_ACS_SCOM ); +REG64( PERV_PCI2_HOSTATTN_MASK , RULL(0x0F040020), SH_UNT_PERV_15 , SH_ACS_SCOM ); +REG64( PERV_EP00_HOSTATTN_MASK , RULL(0x10040020), SH_UNT_PERV_16 , SH_ACS_SCOM ); +REG64( PERV_EP01_HOSTATTN_MASK , RULL(0x11040020), SH_UNT_PERV_17 , SH_ACS_SCOM ); +REG64( PERV_EP02_HOSTATTN_MASK , RULL(0x12040020), SH_UNT_PERV_18 , SH_ACS_SCOM ); +REG64( PERV_EP03_HOSTATTN_MASK , RULL(0x13040020), SH_UNT_PERV_19 , SH_ACS_SCOM ); +REG64( PERV_EP04_HOSTATTN_MASK , RULL(0x14040020), SH_UNT_PERV_20 , SH_ACS_SCOM ); +REG64( PERV_EP05_HOSTATTN_MASK , RULL(0x15040020), SH_UNT_PERV_21 , SH_ACS_SCOM ); +REG64( PERV_EC00_HOSTATTN_MASK , RULL(0x20040020), SH_UNT_PERV_32 , SH_ACS_SCOM ); +REG64( PERV_EC01_HOSTATTN_MASK , RULL(0x21040020), SH_UNT_PERV_33 , SH_ACS_SCOM ); +REG64( PERV_EC02_HOSTATTN_MASK , RULL(0x22040020), SH_UNT_PERV_34 , SH_ACS_SCOM ); +REG64( PERV_EC03_HOSTATTN_MASK , RULL(0x23040020), SH_UNT_PERV_35 , SH_ACS_SCOM ); +REG64( PERV_EC04_HOSTATTN_MASK , RULL(0x24040020), SH_UNT_PERV_36 , SH_ACS_SCOM ); +REG64( PERV_EC05_HOSTATTN_MASK , RULL(0x25040020), SH_UNT_PERV_37 , SH_ACS_SCOM ); +REG64( PERV_EC06_HOSTATTN_MASK , RULL(0x26040020), SH_UNT_PERV_38 , SH_ACS_SCOM ); +REG64( PERV_EC07_HOSTATTN_MASK , RULL(0x27040020), SH_UNT_PERV_39 , SH_ACS_SCOM ); +REG64( PERV_EC08_HOSTATTN_MASK , RULL(0x28040020), SH_UNT_PERV_40 , SH_ACS_SCOM ); +REG64( PERV_EC09_HOSTATTN_MASK , RULL(0x29040020), SH_UNT_PERV_41 , SH_ACS_SCOM ); +REG64( PERV_EC10_HOSTATTN_MASK , RULL(0x2A040020), SH_UNT_PERV_42 , SH_ACS_SCOM ); +REG64( PERV_EC11_HOSTATTN_MASK , RULL(0x2B040020), SH_UNT_PERV_43 , SH_ACS_SCOM ); +REG64( PERV_EC12_HOSTATTN_MASK , RULL(0x2C040020), SH_UNT_PERV_44 , SH_ACS_SCOM ); +REG64( PERV_EC13_HOSTATTN_MASK , RULL(0x2D040020), SH_UNT_PERV_45 , SH_ACS_SCOM ); +REG64( PERV_EC14_HOSTATTN_MASK , RULL(0x2E040020), SH_UNT_PERV_46 , SH_ACS_SCOM ); +REG64( PERV_EC15_HOSTATTN_MASK , RULL(0x2F040020), SH_UNT_PERV_47 , SH_ACS_SCOM ); +REG64( PERV_EC16_HOSTATTN_MASK , RULL(0x30040020), SH_UNT_PERV_48 , SH_ACS_SCOM ); +REG64( PERV_EC17_HOSTATTN_MASK , RULL(0x31040020), SH_UNT_PERV_49 , SH_ACS_SCOM ); +REG64( PERV_EC18_HOSTATTN_MASK , RULL(0x32040020), SH_UNT_PERV_50 , SH_ACS_SCOM ); +REG64( PERV_EC19_HOSTATTN_MASK , RULL(0x33040020), SH_UNT_PERV_51 , SH_ACS_SCOM ); +REG64( PERV_EC20_HOSTATTN_MASK , RULL(0x34040020), SH_UNT_PERV_52 , SH_ACS_SCOM ); +REG64( PERV_EC21_HOSTATTN_MASK , RULL(0x35040020), SH_UNT_PERV_53 , SH_ACS_SCOM ); +REG64( PERV_EC22_HOSTATTN_MASK , RULL(0x36040020), SH_UNT_PERV_54 , SH_ACS_SCOM ); +REG64( PERV_EC23_HOSTATTN_MASK , RULL(0x37040020), SH_UNT_PERV_55 , SH_ACS_SCOM ); + REG64( PERV_HOST_MASK_REG , RULL(0x000F0033), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_HOST_MASK_REG , RULL(0x000F0033), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG64( PERV_0_FSII2C_I2C_BUSY_REGISTER_A , RULL(0x0000180A), SH_UNT_PERV_0_FSII2C, + SH_ACS_SCOM ); +REG32( PERV_FSII2C_I2C_BUSY_REGISTER_A , RULL(0x0000180A), SH_UNT_PERV_FSII2C, + SH_ACS_SCOM ); + REG64( PERV_IGNORE_PAR_REG , RULL(0x000F001C), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_IGNORE_PAR_REG , RULL(0x000F001C), SH_UNT_PERV_0 , SH_ACS_SCOM ); -REG64( PERV_0_FSII2C_IMM_RESET_ERR , RULL(0x00001808), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_IMM_RESET_ERR_A , RULL(0x00001808), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM ); //WARNING - VALUE SET SAME AS ANOTHER REG -REG32( PERV_FSII2C_IMM_RESET_ERR , RULL(0x00001808), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_IMM_RESET_ERR_A , RULL(0x00001808), SH_UNT_PERV_FSII2C, SH_ACS_SCOM ); //WARNING - VALUE SET SAME AS ANOTHER REG -REG64( PERV_0_FSII2C_IMM_RESET_I2C , RULL(0x00001807), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_IMM_RESET_I2C_A , RULL(0x00001807), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM ); -REG32( PERV_FSII2C_IMM_RESET_I2C , RULL(0x00001807), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_IMM_RESET_I2C_A , RULL(0x00001807), SH_UNT_PERV_FSII2C, SH_ACS_SCOM ); -REG64( PERV_0_FSII2C_IMM_RESET_S_SCL , RULL(0x0000180B), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_IMM_RESET_S_SCL_A , RULL(0x0000180B), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM ); -REG32( PERV_FSII2C_IMM_RESET_S_SCL , RULL(0x0000180B), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_IMM_RESET_S_SCL_A , RULL(0x0000180B), SH_UNT_PERV_FSII2C, SH_ACS_SCOM ); -REG64( PERV_0_FSII2C_IMM_RESET_S_SDA , RULL(0x0000180D), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_IMM_RESET_S_SDA_A , RULL(0x0000180D), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM ); -REG32( PERV_FSII2C_IMM_RESET_S_SDA , RULL(0x0000180D), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_IMM_RESET_S_SDA_A , RULL(0x0000180D), SH_UNT_PERV_FSII2C, SH_ACS_SCOM ); -REG64( PERV_0_FSII2C_IMM_SET_S_SCL , RULL(0x00001809), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_IMM_SET_S_SCL_A , RULL(0x00001809), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM ); -REG32( PERV_FSII2C_IMM_SET_S_SCL , RULL(0x00001809), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_IMM_SET_S_SCL_A , RULL(0x00001809), SH_UNT_PERV_FSII2C, SH_ACS_SCOM ); -REG64( PERV_0_FSII2C_IMM_SET_S_SDA , RULL(0x0000180C), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_IMM_SET_S_SDA_A , RULL(0x0000180C), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM ); -REG32( PERV_FSII2C_IMM_SET_S_SDA , RULL(0x0000180C), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_IMM_SET_S_SDA_A , RULL(0x0000180C), SH_UNT_PERV_FSII2C, SH_ACS_SCOM ); REG64( PERV_INJECT_REG , RULL(0x00050011), SH_UNT_PERV_1 , SH_ACS_SCOM ); @@ -4961,14 +5179,14 @@ REG64( PERV_PIB_INTERRUPT4_REG , RULL(0x000F0029 REG64( PERV_PIB_INTERRUPT4_REG_OR , RULL(0x000F002A), SH_UNT_PERV_0 , SH_ACS_SCOM1_OR ); REG64( PERV_PIB_INTERRUPT4_REG_AND , RULL(0x000F002B), SH_UNT_PERV_0 , SH_ACS_SCOM2_AND ); -REG64( PERV_0_FSII2C_INTERRUPTS , RULL(0x00001806), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_INTERRUPTS_A , RULL(0x00001806), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM ); -REG32( PERV_FSII2C_INTERRUPTS , RULL(0x00001806), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_INTERRUPTS_A , RULL(0x00001806), SH_UNT_PERV_FSII2C, SH_ACS_SCOM ); -REG64( PERV_0_FSII2C_INTERRUPT_COND , RULL(0x00001805), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_INTERRUPT_COND_A , RULL(0x00001805), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM ); -REG32( PERV_FSII2C_INTERRUPT_COND , RULL(0x00001805), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_INTERRUPT_COND_A , RULL(0x00001805), SH_UNT_PERV_FSII2C, SH_ACS_SCOM ); REG64( PERV_INTERRUPT_CONF_REG , RULL(0x000F002F), SH_UNT_PERV , SH_ACS_SCOM_RW ); @@ -4983,19 +5201,24 @@ REG64( PERV_PIB_INTERRUPT_CONF_REG_WAND , RULL(0x000F0031 REG64( PERV_INTERRUPT_HOLD_REG , RULL(0x000F0032), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_INTERRUPT_HOLD_REG , RULL(0x000F0032), SH_UNT_PERV_0 , SH_ACS_SCOM ); -REG64( PERV_0_FSII2C_INTERRUPT_MASK_REGISTER , RULL(0x00001804), SH_UNT_PERV_0_FSII2C, - SH_ACS_SCOM_RW ); -REG64( PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_OR , RULL(0x00001805), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_A_WO , RULL(0x00001804), SH_UNT_PERV_0_FSII2C, + SH_ACS_SCOM_WO ); +REG64( PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_A_OR , RULL(0x00001805), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM1_OR ); -REG64( PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_AND , RULL(0x00001806), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_A_AND , RULL(0x00001806), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM2_AND ); -REG32( PERV_FSII2C_INTERRUPT_MASK_REGISTER , RULL(0x00001804), SH_UNT_PERV_FSII2C, - SH_ACS_SCOM_RW ); -REG32( PERV_FSII2C_INTERRUPT_MASK_REGISTER_OR , RULL(0x00001805), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_WO , RULL(0x00001804), SH_UNT_PERV_FSII2C, + SH_ACS_SCOM_WO ); +REG32( PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_OR , RULL(0x00001805), SH_UNT_PERV_FSII2C, SH_ACS_SCOM1_OR ); -REG32( PERV_FSII2C_INTERRUPT_MASK_REGISTER_AND , RULL(0x00001806), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_AND , RULL(0x00001806), SH_UNT_PERV_FSII2C, SH_ACS_SCOM2_AND ); +REG64( PERV_0_FSII2C_INTERRUPT_MASK_REGISTER_READ_A , RULL(0x00001804), SH_UNT_PERV_0_FSII2C, + SH_ACS_SCOM ); +REG32( PERV_FSII2C_INTERRUPT_MASK_REGISTER_READ_A , RULL(0x00001804), SH_UNT_PERV_FSII2C, + SH_ACS_SCOM ); + REG64( PERV_INTERRUPT_TYPE_MASK_REG , RULL(0x000F002C), SH_UNT_PERV , SH_ACS_SCOM_RW ); REG64( PERV_INTERRUPT_TYPE_MASK_REG_WOR , RULL(0x000F002D), SH_UNT_PERV , SH_ACS_SCOM1_WOR ); REG64( PERV_INTERRUPT_TYPE_MASK_REG_WAND , RULL(0x000F002E), SH_UNT_PERV , @@ -5020,11 +5243,11 @@ REG64( PERV_IODA_XLT_EA_IODA , RULL(0x00004000 REG64( PERV_N3_IO_DATA_REG , RULL(0x05002830), SH_UNT_PERV_5 , SH_ACS_SCOM_RO ); -REG64( PERV_KVREF_AND_VMEAS_MODE_REG , RULL(0x00020007), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_TP_KVREF_AND_VMEAS_MODE_REG , RULL(0x01020007), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_KVREF_AND_VMEAS_MODE_STATUS_REG , RULL(0x00020007), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_KVREF_AND_VMEAS_MODE_STATUS_REG , RULL(0x01020007), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_KVREF_VMEAS_STATUS_REG , RULL(0x00020005), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); -REG64( PERV_TP_KVREF_VMEAS_STATUS_REG , RULL(0x01020005), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); +REG64( PERV_KVREF_TUNE_DATA , RULL(0x00020005), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); +REG64( PERV_TP_KVREF_TUNE_DATA , RULL(0x01020005), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); REG64( PERV_LOCAL_FIR , RULL(0x0004000A), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); REG64( PERV_TP_LOCAL_FIR , RULL(0x0104000A), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); @@ -5032,6 +5255,132 @@ REG64( PERV_LOCAL_FIR_AND , RULL(0x0004000B REG64( PERV_TP_LOCAL_FIR_AND , RULL(0x0104000B), SH_UNT_PERV_1 , SH_ACS_SCOM1_AND ); REG64( PERV_LOCAL_FIR_OR , RULL(0x0004000C), SH_UNT_PERV_1 , SH_ACS_SCOM2_OR ); REG64( PERV_TP_LOCAL_FIR_OR , RULL(0x0104000C), SH_UNT_PERV_1 , SH_ACS_SCOM2_OR ); +REG64( PERV_N0_LOCAL_FIR , RULL(0x0204000A), SH_UNT_PERV_2 , SH_ACS_SCOM_RW ); +REG64( PERV_N0_LOCAL_FIR_AND , RULL(0x0204000B), SH_UNT_PERV_2 , SH_ACS_SCOM1_AND ); +REG64( PERV_N0_LOCAL_FIR_OR , RULL(0x0204000C), SH_UNT_PERV_2 , SH_ACS_SCOM2_OR ); +REG64( PERV_N1_LOCAL_FIR , RULL(0x0304000A), SH_UNT_PERV_3 , SH_ACS_SCOM_RW ); +REG64( PERV_N1_LOCAL_FIR_AND , RULL(0x0304000B), SH_UNT_PERV_3 , SH_ACS_SCOM1_AND ); +REG64( PERV_N1_LOCAL_FIR_OR , RULL(0x0304000C), SH_UNT_PERV_3 , SH_ACS_SCOM2_OR ); +REG64( PERV_N2_LOCAL_FIR , RULL(0x0404000A), SH_UNT_PERV_4 , SH_ACS_SCOM_RW ); +REG64( PERV_N2_LOCAL_FIR_AND , RULL(0x0404000B), SH_UNT_PERV_4 , SH_ACS_SCOM1_AND ); +REG64( PERV_N2_LOCAL_FIR_OR , RULL(0x0404000C), SH_UNT_PERV_4 , SH_ACS_SCOM2_OR ); +REG64( PERV_N3_LOCAL_FIR , RULL(0x0504000A), SH_UNT_PERV_5 , SH_ACS_SCOM_RW ); +REG64( PERV_N3_LOCAL_FIR_AND , RULL(0x0504000B), SH_UNT_PERV_5 , SH_ACS_SCOM1_AND ); +REG64( PERV_N3_LOCAL_FIR_OR , RULL(0x0504000C), SH_UNT_PERV_5 , SH_ACS_SCOM2_OR ); +REG64( PERV_XB_LOCAL_FIR , RULL(0x0604000A), SH_UNT_PERV_6 , SH_ACS_SCOM_RW ); +REG64( PERV_XB_LOCAL_FIR_AND , RULL(0x0604000B), SH_UNT_PERV_6 , SH_ACS_SCOM1_AND ); +REG64( PERV_XB_LOCAL_FIR_OR , RULL(0x0604000C), SH_UNT_PERV_6 , SH_ACS_SCOM2_OR ); +REG64( PERV_MC01_LOCAL_FIR , RULL(0x0704000A), SH_UNT_PERV_7 , SH_ACS_SCOM_RW ); +REG64( PERV_MC01_LOCAL_FIR_AND , RULL(0x0704000B), SH_UNT_PERV_7 , SH_ACS_SCOM1_AND ); +REG64( PERV_MC01_LOCAL_FIR_OR , RULL(0x0704000C), SH_UNT_PERV_7 , SH_ACS_SCOM2_OR ); +REG64( PERV_MC23_LOCAL_FIR , RULL(0x0804000A), SH_UNT_PERV_8 , SH_ACS_SCOM_RW ); +REG64( PERV_MC23_LOCAL_FIR_AND , RULL(0x0804000B), SH_UNT_PERV_8 , SH_ACS_SCOM1_AND ); +REG64( PERV_MC23_LOCAL_FIR_OR , RULL(0x0804000C), SH_UNT_PERV_8 , SH_ACS_SCOM2_OR ); +REG64( PERV_OB0_LOCAL_FIR , RULL(0x0904000A), SH_UNT_PERV_9 , SH_ACS_SCOM_RW ); +REG64( PERV_OB0_LOCAL_FIR_AND , RULL(0x0904000B), SH_UNT_PERV_9 , SH_ACS_SCOM1_AND ); +REG64( PERV_OB0_LOCAL_FIR_OR , RULL(0x0904000C), SH_UNT_PERV_9 , SH_ACS_SCOM2_OR ); +REG64( PERV_OB3_LOCAL_FIR , RULL(0x0C04000A), SH_UNT_PERV_12 , SH_ACS_SCOM_RW ); +REG64( PERV_OB3_LOCAL_FIR_AND , RULL(0x0C04000B), SH_UNT_PERV_12 , SH_ACS_SCOM1_AND ); +REG64( PERV_OB3_LOCAL_FIR_OR , RULL(0x0C04000C), SH_UNT_PERV_12 , SH_ACS_SCOM2_OR ); +REG64( PERV_PCI0_LOCAL_FIR , RULL(0x0D04000A), SH_UNT_PERV_13 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI0_LOCAL_FIR_AND , RULL(0x0D04000B), SH_UNT_PERV_13 , SH_ACS_SCOM1_AND ); +REG64( PERV_PCI0_LOCAL_FIR_OR , RULL(0x0D04000C), SH_UNT_PERV_13 , SH_ACS_SCOM2_OR ); +REG64( PERV_PCI1_LOCAL_FIR , RULL(0x0E04000A), SH_UNT_PERV_14 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI1_LOCAL_FIR_AND , RULL(0x0E04000B), SH_UNT_PERV_14 , SH_ACS_SCOM1_AND ); +REG64( PERV_PCI1_LOCAL_FIR_OR , RULL(0x0E04000C), SH_UNT_PERV_14 , SH_ACS_SCOM2_OR ); +REG64( PERV_PCI2_LOCAL_FIR , RULL(0x0F04000A), SH_UNT_PERV_15 , SH_ACS_SCOM_RW ); +REG64( PERV_PCI2_LOCAL_FIR_AND , RULL(0x0F04000B), SH_UNT_PERV_15 , SH_ACS_SCOM1_AND ); +REG64( PERV_PCI2_LOCAL_FIR_OR , RULL(0x0F04000C), SH_UNT_PERV_15 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP00_LOCAL_FIR , RULL(0x1004000A), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); +REG64( PERV_EP00_LOCAL_FIR_AND , RULL(0x1004000B), SH_UNT_PERV_16 , SH_ACS_SCOM1_AND ); +REG64( PERV_EP00_LOCAL_FIR_OR , RULL(0x1004000C), SH_UNT_PERV_16 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP01_LOCAL_FIR , RULL(0x1104000A), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); +REG64( PERV_EP01_LOCAL_FIR_AND , RULL(0x1104000B), SH_UNT_PERV_17 , SH_ACS_SCOM1_AND ); +REG64( PERV_EP01_LOCAL_FIR_OR , RULL(0x1104000C), SH_UNT_PERV_17 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP02_LOCAL_FIR , RULL(0x1204000A), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); +REG64( PERV_EP02_LOCAL_FIR_AND , RULL(0x1204000B), SH_UNT_PERV_18 , SH_ACS_SCOM1_AND ); +REG64( PERV_EP02_LOCAL_FIR_OR , RULL(0x1204000C), SH_UNT_PERV_18 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP03_LOCAL_FIR , RULL(0x1304000A), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); +REG64( PERV_EP03_LOCAL_FIR_AND , RULL(0x1304000B), SH_UNT_PERV_19 , SH_ACS_SCOM1_AND ); +REG64( PERV_EP03_LOCAL_FIR_OR , RULL(0x1304000C), SH_UNT_PERV_19 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP04_LOCAL_FIR , RULL(0x1404000A), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); +REG64( PERV_EP04_LOCAL_FIR_AND , RULL(0x1404000B), SH_UNT_PERV_20 , SH_ACS_SCOM1_AND ); +REG64( PERV_EP04_LOCAL_FIR_OR , RULL(0x1404000C), SH_UNT_PERV_20 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP05_LOCAL_FIR , RULL(0x1504000A), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); +REG64( PERV_EP05_LOCAL_FIR_AND , RULL(0x1504000B), SH_UNT_PERV_21 , SH_ACS_SCOM1_AND ); +REG64( PERV_EP05_LOCAL_FIR_OR , RULL(0x1504000C), SH_UNT_PERV_21 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC00_LOCAL_FIR , RULL(0x2004000A), SH_UNT_PERV_32 , SH_ACS_SCOM_RW ); +REG64( PERV_EC00_LOCAL_FIR_AND , RULL(0x2004000B), SH_UNT_PERV_32 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC00_LOCAL_FIR_OR , RULL(0x2004000C), SH_UNT_PERV_32 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC01_LOCAL_FIR , RULL(0x2104000A), SH_UNT_PERV_33 , SH_ACS_SCOM_RW ); +REG64( PERV_EC01_LOCAL_FIR_AND , RULL(0x2104000B), SH_UNT_PERV_33 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC01_LOCAL_FIR_OR , RULL(0x2104000C), SH_UNT_PERV_33 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC02_LOCAL_FIR , RULL(0x2204000A), SH_UNT_PERV_34 , SH_ACS_SCOM_RW ); +REG64( PERV_EC02_LOCAL_FIR_AND , RULL(0x2204000B), SH_UNT_PERV_34 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC02_LOCAL_FIR_OR , RULL(0x2204000C), SH_UNT_PERV_34 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC03_LOCAL_FIR , RULL(0x2304000A), SH_UNT_PERV_35 , SH_ACS_SCOM_RW ); +REG64( PERV_EC03_LOCAL_FIR_AND , RULL(0x2304000B), SH_UNT_PERV_35 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC03_LOCAL_FIR_OR , RULL(0x2304000C), SH_UNT_PERV_35 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC04_LOCAL_FIR , RULL(0x2404000A), SH_UNT_PERV_36 , SH_ACS_SCOM_RW ); +REG64( PERV_EC04_LOCAL_FIR_AND , RULL(0x2404000B), SH_UNT_PERV_36 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC04_LOCAL_FIR_OR , RULL(0x2404000C), SH_UNT_PERV_36 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC05_LOCAL_FIR , RULL(0x2504000A), SH_UNT_PERV_37 , SH_ACS_SCOM_RW ); +REG64( PERV_EC05_LOCAL_FIR_AND , RULL(0x2504000B), SH_UNT_PERV_37 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC05_LOCAL_FIR_OR , RULL(0x2504000C), SH_UNT_PERV_37 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC06_LOCAL_FIR , RULL(0x2604000A), SH_UNT_PERV_38 , SH_ACS_SCOM_RW ); +REG64( PERV_EC06_LOCAL_FIR_AND , RULL(0x2604000B), SH_UNT_PERV_38 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC06_LOCAL_FIR_OR , RULL(0x2604000C), SH_UNT_PERV_38 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC07_LOCAL_FIR , RULL(0x2704000A), SH_UNT_PERV_39 , SH_ACS_SCOM_RW ); +REG64( PERV_EC07_LOCAL_FIR_AND , RULL(0x2704000B), SH_UNT_PERV_39 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC07_LOCAL_FIR_OR , RULL(0x2704000C), SH_UNT_PERV_39 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC08_LOCAL_FIR , RULL(0x2804000A), SH_UNT_PERV_40 , SH_ACS_SCOM_RW ); +REG64( PERV_EC08_LOCAL_FIR_AND , RULL(0x2804000B), SH_UNT_PERV_40 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC08_LOCAL_FIR_OR , RULL(0x2804000C), SH_UNT_PERV_40 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC09_LOCAL_FIR , RULL(0x2904000A), SH_UNT_PERV_41 , SH_ACS_SCOM_RW ); +REG64( PERV_EC09_LOCAL_FIR_AND , RULL(0x2904000B), SH_UNT_PERV_41 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC09_LOCAL_FIR_OR , RULL(0x2904000C), SH_UNT_PERV_41 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC10_LOCAL_FIR , RULL(0x2A04000A), SH_UNT_PERV_42 , SH_ACS_SCOM_RW ); +REG64( PERV_EC10_LOCAL_FIR_AND , RULL(0x2A04000B), SH_UNT_PERV_42 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC10_LOCAL_FIR_OR , RULL(0x2A04000C), SH_UNT_PERV_42 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC11_LOCAL_FIR , RULL(0x2B04000A), SH_UNT_PERV_43 , SH_ACS_SCOM_RW ); +REG64( PERV_EC11_LOCAL_FIR_AND , RULL(0x2B04000B), SH_UNT_PERV_43 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC11_LOCAL_FIR_OR , RULL(0x2B04000C), SH_UNT_PERV_43 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC12_LOCAL_FIR , RULL(0x2C04000A), SH_UNT_PERV_44 , SH_ACS_SCOM_RW ); +REG64( PERV_EC12_LOCAL_FIR_AND , RULL(0x2C04000B), SH_UNT_PERV_44 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC12_LOCAL_FIR_OR , RULL(0x2C04000C), SH_UNT_PERV_44 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC13_LOCAL_FIR , RULL(0x2D04000A), SH_UNT_PERV_45 , SH_ACS_SCOM_RW ); +REG64( PERV_EC13_LOCAL_FIR_AND , RULL(0x2D04000B), SH_UNT_PERV_45 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC13_LOCAL_FIR_OR , RULL(0x2D04000C), SH_UNT_PERV_45 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC14_LOCAL_FIR , RULL(0x2E04000A), SH_UNT_PERV_46 , SH_ACS_SCOM_RW ); +REG64( PERV_EC14_LOCAL_FIR_AND , RULL(0x2E04000B), SH_UNT_PERV_46 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC14_LOCAL_FIR_OR , RULL(0x2E04000C), SH_UNT_PERV_46 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC15_LOCAL_FIR , RULL(0x2F04000A), SH_UNT_PERV_47 , SH_ACS_SCOM_RW ); +REG64( PERV_EC15_LOCAL_FIR_AND , RULL(0x2F04000B), SH_UNT_PERV_47 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC15_LOCAL_FIR_OR , RULL(0x2F04000C), SH_UNT_PERV_47 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC16_LOCAL_FIR , RULL(0x3004000A), SH_UNT_PERV_48 , SH_ACS_SCOM_RW ); +REG64( PERV_EC16_LOCAL_FIR_AND , RULL(0x3004000B), SH_UNT_PERV_48 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC16_LOCAL_FIR_OR , RULL(0x3004000C), SH_UNT_PERV_48 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC17_LOCAL_FIR , RULL(0x3104000A), SH_UNT_PERV_49 , SH_ACS_SCOM_RW ); +REG64( PERV_EC17_LOCAL_FIR_AND , RULL(0x3104000B), SH_UNT_PERV_49 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC17_LOCAL_FIR_OR , RULL(0x3104000C), SH_UNT_PERV_49 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC18_LOCAL_FIR , RULL(0x3204000A), SH_UNT_PERV_50 , SH_ACS_SCOM_RW ); +REG64( PERV_EC18_LOCAL_FIR_AND , RULL(0x3204000B), SH_UNT_PERV_50 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC18_LOCAL_FIR_OR , RULL(0x3204000C), SH_UNT_PERV_50 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC19_LOCAL_FIR , RULL(0x3304000A), SH_UNT_PERV_51 , SH_ACS_SCOM_RW ); +REG64( PERV_EC19_LOCAL_FIR_AND , RULL(0x3304000B), SH_UNT_PERV_51 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC19_LOCAL_FIR_OR , RULL(0x3304000C), SH_UNT_PERV_51 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC20_LOCAL_FIR , RULL(0x3404000A), SH_UNT_PERV_52 , SH_ACS_SCOM_RW ); +REG64( PERV_EC20_LOCAL_FIR_AND , RULL(0x3404000B), SH_UNT_PERV_52 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC20_LOCAL_FIR_OR , RULL(0x3404000C), SH_UNT_PERV_52 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC21_LOCAL_FIR , RULL(0x3504000A), SH_UNT_PERV_53 , SH_ACS_SCOM_RW ); +REG64( PERV_EC21_LOCAL_FIR_AND , RULL(0x3504000B), SH_UNT_PERV_53 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC21_LOCAL_FIR_OR , RULL(0x3504000C), SH_UNT_PERV_53 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC22_LOCAL_FIR , RULL(0x3604000A), SH_UNT_PERV_54 , SH_ACS_SCOM_RW ); +REG64( PERV_EC22_LOCAL_FIR_AND , RULL(0x3604000B), SH_UNT_PERV_54 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC22_LOCAL_FIR_OR , RULL(0x3604000C), SH_UNT_PERV_54 , SH_ACS_SCOM2_OR ); +REG64( PERV_EC23_LOCAL_FIR , RULL(0x3704000A), SH_UNT_PERV_55 , SH_ACS_SCOM_RW ); +REG64( PERV_EC23_LOCAL_FIR_AND , RULL(0x3704000B), SH_UNT_PERV_55 , SH_ACS_SCOM1_AND ); +REG64( PERV_EC23_LOCAL_FIR_OR , RULL(0x3704000C), SH_UNT_PERV_55 , SH_ACS_SCOM2_OR ); REG64( PERV_LOCAL_FIR_ACTION0 , RULL(0x00040010), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_TP_LOCAL_FIR_ACTION0 , RULL(0x01040010), SH_UNT_PERV_1 , SH_ACS_SCOM ); @@ -5256,6 +5605,96 @@ REG64( PERV_EC23_LOCAL_FIR_MASK , RULL(0x3704000D REG64( PERV_EC23_LOCAL_FIR_MASK_AND , RULL(0x3704000E), SH_UNT_PERV_55 , SH_ACS_SCOM1_AND ); REG64( PERV_EC23_LOCAL_FIR_MASK_OR , RULL(0x3704000F), SH_UNT_PERV_55 , SH_ACS_SCOM2_OR ); +REG64( PERV_LOCAL_XSTOP_ERR , RULL(0x00040018), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); +REG64( PERV_TP_LOCAL_XSTOP_ERR , RULL(0x01040018), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); +REG64( PERV_N0_LOCAL_XSTOP_ERR , RULL(0x02040018), SH_UNT_PERV_2 , SH_ACS_SCOM_RO ); +REG64( PERV_N1_LOCAL_XSTOP_ERR , RULL(0x03040018), SH_UNT_PERV_3 , SH_ACS_SCOM_RO ); +REG64( PERV_N2_LOCAL_XSTOP_ERR , RULL(0x04040018), SH_UNT_PERV_4 , SH_ACS_SCOM_RO ); +REG64( PERV_N3_LOCAL_XSTOP_ERR , RULL(0x05040018), SH_UNT_PERV_5 , SH_ACS_SCOM_RO ); +REG64( PERV_XB_LOCAL_XSTOP_ERR , RULL(0x06040018), SH_UNT_PERV_6 , SH_ACS_SCOM_RO ); +REG64( PERV_MC01_LOCAL_XSTOP_ERR , RULL(0x07040018), SH_UNT_PERV_7 , SH_ACS_SCOM_RO ); +REG64( PERV_MC23_LOCAL_XSTOP_ERR , RULL(0x08040018), SH_UNT_PERV_8 , SH_ACS_SCOM_RO ); +REG64( PERV_OB0_LOCAL_XSTOP_ERR , RULL(0x09040018), SH_UNT_PERV_9 , SH_ACS_SCOM_RO ); +REG64( PERV_OB3_LOCAL_XSTOP_ERR , RULL(0x0C040018), SH_UNT_PERV_12 , SH_ACS_SCOM_RO ); +REG64( PERV_PCI0_LOCAL_XSTOP_ERR , RULL(0x0D040018), SH_UNT_PERV_13 , SH_ACS_SCOM_RO ); +REG64( PERV_PCI1_LOCAL_XSTOP_ERR , RULL(0x0E040018), SH_UNT_PERV_14 , SH_ACS_SCOM_RO ); +REG64( PERV_PCI2_LOCAL_XSTOP_ERR , RULL(0x0F040018), SH_UNT_PERV_15 , SH_ACS_SCOM_RO ); +REG64( PERV_EP00_LOCAL_XSTOP_ERR , RULL(0x10040018), SH_UNT_PERV_16 , SH_ACS_SCOM_RO ); +REG64( PERV_EP01_LOCAL_XSTOP_ERR , RULL(0x11040018), SH_UNT_PERV_17 , SH_ACS_SCOM_RO ); +REG64( PERV_EP02_LOCAL_XSTOP_ERR , RULL(0x12040018), SH_UNT_PERV_18 , SH_ACS_SCOM_RO ); +REG64( PERV_EP03_LOCAL_XSTOP_ERR , RULL(0x13040018), SH_UNT_PERV_19 , SH_ACS_SCOM_RO ); +REG64( PERV_EP04_LOCAL_XSTOP_ERR , RULL(0x14040018), SH_UNT_PERV_20 , SH_ACS_SCOM_RO ); +REG64( PERV_EP05_LOCAL_XSTOP_ERR , RULL(0x15040018), SH_UNT_PERV_21 , SH_ACS_SCOM_RO ); +REG64( PERV_EC00_LOCAL_XSTOP_ERR , RULL(0x20040018), SH_UNT_PERV_32 , SH_ACS_SCOM_RO ); +REG64( PERV_EC01_LOCAL_XSTOP_ERR , RULL(0x21040018), SH_UNT_PERV_33 , SH_ACS_SCOM_RO ); +REG64( PERV_EC02_LOCAL_XSTOP_ERR , RULL(0x22040018), SH_UNT_PERV_34 , SH_ACS_SCOM_RO ); +REG64( PERV_EC03_LOCAL_XSTOP_ERR , RULL(0x23040018), SH_UNT_PERV_35 , SH_ACS_SCOM_RO ); +REG64( PERV_EC04_LOCAL_XSTOP_ERR , RULL(0x24040018), SH_UNT_PERV_36 , SH_ACS_SCOM_RO ); +REG64( PERV_EC05_LOCAL_XSTOP_ERR , RULL(0x25040018), SH_UNT_PERV_37 , SH_ACS_SCOM_RO ); +REG64( PERV_EC06_LOCAL_XSTOP_ERR , RULL(0x26040018), SH_UNT_PERV_38 , SH_ACS_SCOM_RO ); +REG64( PERV_EC07_LOCAL_XSTOP_ERR , RULL(0x27040018), SH_UNT_PERV_39 , SH_ACS_SCOM_RO ); +REG64( PERV_EC08_LOCAL_XSTOP_ERR , RULL(0x28040018), SH_UNT_PERV_40 , SH_ACS_SCOM_RO ); +REG64( PERV_EC09_LOCAL_XSTOP_ERR , RULL(0x29040018), SH_UNT_PERV_41 , SH_ACS_SCOM_RO ); +REG64( PERV_EC10_LOCAL_XSTOP_ERR , RULL(0x2A040018), SH_UNT_PERV_42 , SH_ACS_SCOM_RO ); +REG64( PERV_EC11_LOCAL_XSTOP_ERR , RULL(0x2B040018), SH_UNT_PERV_43 , SH_ACS_SCOM_RO ); +REG64( PERV_EC12_LOCAL_XSTOP_ERR , RULL(0x2C040018), SH_UNT_PERV_44 , SH_ACS_SCOM_RO ); +REG64( PERV_EC13_LOCAL_XSTOP_ERR , RULL(0x2D040018), SH_UNT_PERV_45 , SH_ACS_SCOM_RO ); +REG64( PERV_EC14_LOCAL_XSTOP_ERR , RULL(0x2E040018), SH_UNT_PERV_46 , SH_ACS_SCOM_RO ); +REG64( PERV_EC15_LOCAL_XSTOP_ERR , RULL(0x2F040018), SH_UNT_PERV_47 , SH_ACS_SCOM_RO ); +REG64( PERV_EC16_LOCAL_XSTOP_ERR , RULL(0x30040018), SH_UNT_PERV_48 , SH_ACS_SCOM_RO ); +REG64( PERV_EC17_LOCAL_XSTOP_ERR , RULL(0x31040018), SH_UNT_PERV_49 , SH_ACS_SCOM_RO ); +REG64( PERV_EC18_LOCAL_XSTOP_ERR , RULL(0x32040018), SH_UNT_PERV_50 , SH_ACS_SCOM_RO ); +REG64( PERV_EC19_LOCAL_XSTOP_ERR , RULL(0x33040018), SH_UNT_PERV_51 , SH_ACS_SCOM_RO ); +REG64( PERV_EC20_LOCAL_XSTOP_ERR , RULL(0x34040018), SH_UNT_PERV_52 , SH_ACS_SCOM_RO ); +REG64( PERV_EC21_LOCAL_XSTOP_ERR , RULL(0x35040018), SH_UNT_PERV_53 , SH_ACS_SCOM_RO ); +REG64( PERV_EC22_LOCAL_XSTOP_ERR , RULL(0x36040018), SH_UNT_PERV_54 , SH_ACS_SCOM_RO ); +REG64( PERV_EC23_LOCAL_XSTOP_ERR , RULL(0x37040018), SH_UNT_PERV_55 , SH_ACS_SCOM_RO ); + +REG64( PERV_LOCAL_XSTOP_MASK , RULL(0x00040019), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_LOCAL_XSTOP_MASK , RULL(0x01040019), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_N0_LOCAL_XSTOP_MASK , RULL(0x02040019), SH_UNT_PERV_2 , SH_ACS_SCOM ); +REG64( PERV_N1_LOCAL_XSTOP_MASK , RULL(0x03040019), SH_UNT_PERV_3 , SH_ACS_SCOM ); +REG64( PERV_N2_LOCAL_XSTOP_MASK , RULL(0x04040019), SH_UNT_PERV_4 , SH_ACS_SCOM ); +REG64( PERV_N3_LOCAL_XSTOP_MASK , RULL(0x05040019), SH_UNT_PERV_5 , SH_ACS_SCOM ); +REG64( PERV_XB_LOCAL_XSTOP_MASK , RULL(0x06040019), SH_UNT_PERV_6 , SH_ACS_SCOM ); +REG64( PERV_MC01_LOCAL_XSTOP_MASK , RULL(0x07040019), SH_UNT_PERV_7 , SH_ACS_SCOM ); +REG64( PERV_MC23_LOCAL_XSTOP_MASK , RULL(0x08040019), SH_UNT_PERV_8 , SH_ACS_SCOM ); +REG64( PERV_OB0_LOCAL_XSTOP_MASK , RULL(0x09040019), SH_UNT_PERV_9 , SH_ACS_SCOM ); +REG64( PERV_OB3_LOCAL_XSTOP_MASK , RULL(0x0C040019), SH_UNT_PERV_12 , SH_ACS_SCOM ); +REG64( PERV_PCI0_LOCAL_XSTOP_MASK , RULL(0x0D040019), SH_UNT_PERV_13 , SH_ACS_SCOM ); +REG64( PERV_PCI1_LOCAL_XSTOP_MASK , RULL(0x0E040019), SH_UNT_PERV_14 , SH_ACS_SCOM ); +REG64( PERV_PCI2_LOCAL_XSTOP_MASK , RULL(0x0F040019), SH_UNT_PERV_15 , SH_ACS_SCOM ); +REG64( PERV_EP00_LOCAL_XSTOP_MASK , RULL(0x10040019), SH_UNT_PERV_16 , SH_ACS_SCOM ); +REG64( PERV_EP01_LOCAL_XSTOP_MASK , RULL(0x11040019), SH_UNT_PERV_17 , SH_ACS_SCOM ); +REG64( PERV_EP02_LOCAL_XSTOP_MASK , RULL(0x12040019), SH_UNT_PERV_18 , SH_ACS_SCOM ); +REG64( PERV_EP03_LOCAL_XSTOP_MASK , RULL(0x13040019), SH_UNT_PERV_19 , SH_ACS_SCOM ); +REG64( PERV_EP04_LOCAL_XSTOP_MASK , RULL(0x14040019), SH_UNT_PERV_20 , SH_ACS_SCOM ); +REG64( PERV_EP05_LOCAL_XSTOP_MASK , RULL(0x15040019), SH_UNT_PERV_21 , SH_ACS_SCOM ); +REG64( PERV_EC00_LOCAL_XSTOP_MASK , RULL(0x20040019), SH_UNT_PERV_32 , SH_ACS_SCOM ); +REG64( PERV_EC01_LOCAL_XSTOP_MASK , RULL(0x21040019), SH_UNT_PERV_33 , SH_ACS_SCOM ); +REG64( PERV_EC02_LOCAL_XSTOP_MASK , RULL(0x22040019), SH_UNT_PERV_34 , SH_ACS_SCOM ); +REG64( PERV_EC03_LOCAL_XSTOP_MASK , RULL(0x23040019), SH_UNT_PERV_35 , SH_ACS_SCOM ); +REG64( PERV_EC04_LOCAL_XSTOP_MASK , RULL(0x24040019), SH_UNT_PERV_36 , SH_ACS_SCOM ); +REG64( PERV_EC05_LOCAL_XSTOP_MASK , RULL(0x25040019), SH_UNT_PERV_37 , SH_ACS_SCOM ); +REG64( PERV_EC06_LOCAL_XSTOP_MASK , RULL(0x26040019), SH_UNT_PERV_38 , SH_ACS_SCOM ); +REG64( PERV_EC07_LOCAL_XSTOP_MASK , RULL(0x27040019), SH_UNT_PERV_39 , SH_ACS_SCOM ); +REG64( PERV_EC08_LOCAL_XSTOP_MASK , RULL(0x28040019), SH_UNT_PERV_40 , SH_ACS_SCOM ); +REG64( PERV_EC09_LOCAL_XSTOP_MASK , RULL(0x29040019), SH_UNT_PERV_41 , SH_ACS_SCOM ); +REG64( PERV_EC10_LOCAL_XSTOP_MASK , RULL(0x2A040019), SH_UNT_PERV_42 , SH_ACS_SCOM ); +REG64( PERV_EC11_LOCAL_XSTOP_MASK , RULL(0x2B040019), SH_UNT_PERV_43 , SH_ACS_SCOM ); +REG64( PERV_EC12_LOCAL_XSTOP_MASK , RULL(0x2C040019), SH_UNT_PERV_44 , SH_ACS_SCOM ); +REG64( PERV_EC13_LOCAL_XSTOP_MASK , RULL(0x2D040019), SH_UNT_PERV_45 , SH_ACS_SCOM ); +REG64( PERV_EC14_LOCAL_XSTOP_MASK , RULL(0x2E040019), SH_UNT_PERV_46 , SH_ACS_SCOM ); +REG64( PERV_EC15_LOCAL_XSTOP_MASK , RULL(0x2F040019), SH_UNT_PERV_47 , SH_ACS_SCOM ); +REG64( PERV_EC16_LOCAL_XSTOP_MASK , RULL(0x30040019), SH_UNT_PERV_48 , SH_ACS_SCOM ); +REG64( PERV_EC17_LOCAL_XSTOP_MASK , RULL(0x31040019), SH_UNT_PERV_49 , SH_ACS_SCOM ); +REG64( PERV_EC18_LOCAL_XSTOP_MASK , RULL(0x32040019), SH_UNT_PERV_50 , SH_ACS_SCOM ); +REG64( PERV_EC19_LOCAL_XSTOP_MASK , RULL(0x33040019), SH_UNT_PERV_51 , SH_ACS_SCOM ); +REG64( PERV_EC20_LOCAL_XSTOP_MASK , RULL(0x34040019), SH_UNT_PERV_52 , SH_ACS_SCOM ); +REG64( PERV_EC21_LOCAL_XSTOP_MASK , RULL(0x35040019), SH_UNT_PERV_53 , SH_ACS_SCOM ); +REG64( PERV_EC22_LOCAL_XSTOP_MASK , RULL(0x36040019), SH_UNT_PERV_54 , SH_ACS_SCOM ); +REG64( PERV_EC23_LOCAL_XSTOP_MASK , RULL(0x37040019), SH_UNT_PERV_55 , SH_ACS_SCOM ); + REG64( PERV_N3_LPC_BASE_REG , RULL(0x05002840), SH_UNT_PERV_5 , SH_ACS_SCOM ); REG64( PERV_N3_LPC_CMD_REG , RULL(0x05002841), SH_UNT_PERV_5 , SH_ACS_SCOM ); @@ -5692,6 +6131,19 @@ REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_FSI_BYTE , RULL(0x000028D8 REG64( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_SCOM , RULL(0x00050036), SH_UNT_PERV , SH_ACS_SCOM_RO ); REG64( PERV_PIB_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1 , RULL(0x00050036), SH_UNT_PERV_0 , SH_ACS_SCOM_RO ); +REG64( PERV_MASK_REG , RULL(0x0000090B), SH_UNT_PERV , + SH_ACS_SCOM_RW ); //DUPS: 0000090B, 0000094B, 0000090B, 0000094B, 0000098B, +REG64( PERV_MASK_REG_AND , RULL(0x0000090C), SH_UNT_PERV , + SH_ACS_SCOM1_AND ); //DUPS: 0000090C, 0000094C, 0000090C, 0000094C, 0000098C, +REG64( PERV_MASK_REG_OR , RULL(0x0000090D), SH_UNT_PERV , + SH_ACS_SCOM2_OR ); //DUPS: 0000090D, 0000094D, 0000090D, 0000094D, 0000098D, +REG64( PERV_PIB_MASK_REG , RULL(0x0000090B), SH_UNT_PERV_0 , + SH_ACS_SCOM_RW ); //DUPS: 0000090B, 0000094B, 0000090B, 0000094B, 0000098B, +REG64( PERV_PIB_MASK_REG_AND , RULL(0x0000090C), SH_UNT_PERV_0 , + SH_ACS_SCOM1_AND ); //DUPS: 0000090C, 0000094C, 0000090C, 0000094C, 0000098C, +REG64( PERV_PIB_MASK_REG_OR , RULL(0x0000090D), SH_UNT_PERV_0 , + SH_ACS_SCOM2_OR ); //DUPS: 0000090D, 0000094D, 0000090D, 0000094D, 0000098D, + REG64( PERV_MCAST_COMP_MASK_REG , RULL(0x000F0017), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_MCAST_COMP_MASK_REG , RULL(0x000F0017), SH_UNT_PERV_0 , SH_ACS_SCOM ); @@ -5731,9 +6183,6 @@ REG64( PERV_PIB_MIB_XIMEM , RULL(0x00000417 REG64( PERV_MIB_XISGB , RULL(0x00000418), SH_UNT_PERV , SH_ACS_SCOM_RO ); REG64( PERV_PIB_MIB_XISGB , RULL(0x00000418), SH_UNT_PERV_0 , SH_ACS_SCOM_RO ); -REG64( PERV_MIB_XISIB , RULL(0x00000416), SH_UNT_PERV , SH_ACS_SCOM_RO ); -REG64( PERV_PIB_MIB_XISIB , RULL(0x00000416), SH_UNT_PERV_0 , SH_ACS_SCOM_RO ); - REG64( PERV_MODE_REG , RULL(0x00040008), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_TP_MODE_REG , RULL(0x01040008), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_N0_MODE_REG , RULL(0x02040008), SH_UNT_PERV_2 , SH_ACS_SCOM ); @@ -5779,9 +6228,9 @@ REG64( PERV_EC21_MODE_REG , RULL(0x35040008 REG64( PERV_EC22_MODE_REG , RULL(0x36040008), SH_UNT_PERV_54 , SH_ACS_SCOM ); REG64( PERV_EC23_MODE_REG , RULL(0x37040008), SH_UNT_PERV_55 , SH_ACS_SCOM ); -REG64( PERV_0_FSII2C_MODE_REGISTER , RULL(0x00001802), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_MODE_REGISTER_A , RULL(0x00001802), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM ); -REG32( PERV_FSII2C_MODE_REGISTER , RULL(0x00001802), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_MODE_REGISTER_A , RULL(0x00001802), SH_UNT_PERV_FSII2C, SH_ACS_SCOM ); REG64( PERV_MULTICAST_GROUP_1 , RULL(0x000F0001), SH_UNT_PERV_1 , SH_ACS_SCOM ); @@ -6318,6 +6767,31 @@ REG64( PERV_EC23_NET_CTRL1_WAND , RULL(0x370F0045 SH_ACS_SCOM1_WAND ); REG64( PERV_EC23_NET_CTRL1_WOR , RULL(0x370F0046), SH_UNT_PERV_55 , SH_ACS_SCOM2_WOR ); +REG64( PERV_OCC_SCOM_OCCERRRPT , RULL(0x0001080A), SH_UNT_PERV_1 , + SH_ACS_SCOM_WCLRPART ); +REG64( PERV_TP_OCC_SCOM_OCCERRRPT , RULL(0x0101080A), SH_UNT_PERV_1 , + SH_ACS_SCOM_WCLRPART ); + +REG64( PERV_OCC_SCOM_OCCLFIR , RULL(0x00010800), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_TP_OCC_SCOM_OCCLFIR , RULL(0x01010800), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_OCC_SCOM_OCCLFIR_AND , RULL(0x00010801), SH_UNT_PERV_1 , SH_ACS_SCOM1_AND ); +REG64( PERV_TP_OCC_SCOM_OCCLFIR_AND , RULL(0x01010801), SH_UNT_PERV_1 , SH_ACS_SCOM1_AND ); +REG64( PERV_OCC_SCOM_OCCLFIR_OR , RULL(0x00010802), SH_UNT_PERV_1 , SH_ACS_SCOM2_OR ); +REG64( PERV_TP_OCC_SCOM_OCCLFIR_OR , RULL(0x01010802), SH_UNT_PERV_1 , SH_ACS_SCOM2_OR ); + +REG64( PERV_OCC_SCOM_OCCLFIRACT0 , RULL(0x00010806), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_TP_OCC_SCOM_OCCLFIRACT0 , RULL(0x01010806), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); + +REG64( PERV_OCC_SCOM_OCCLFIRACT1 , RULL(0x00010807), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_TP_OCC_SCOM_OCCLFIRACT1 , RULL(0x01010807), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); + +REG64( PERV_OCC_SCOM_OCCLFIRMASK , RULL(0x00010803), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_TP_OCC_SCOM_OCCLFIRMASK , RULL(0x01010803), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( PERV_OCC_SCOM_OCCLFIRMASK_AND , RULL(0x00010804), SH_UNT_PERV_1 , SH_ACS_SCOM1_AND ); +REG64( PERV_TP_OCC_SCOM_OCCLFIRMASK_AND , RULL(0x01010804), SH_UNT_PERV_1 , SH_ACS_SCOM1_AND ); +REG64( PERV_OCC_SCOM_OCCLFIRMASK_OR , RULL(0x00010805), SH_UNT_PERV_1 , SH_ACS_SCOM2_OR ); +REG64( PERV_TP_OCC_SCOM_OCCLFIRMASK_OR , RULL(0x01010805), SH_UNT_PERV_1 , SH_ACS_SCOM2_OR ); + REG64( PERV_OPCG_ALIGN , RULL(0x00030001), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_TP_OPCG_ALIGN , RULL(0x01030001), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_N0_OPCG_ALIGN , RULL(0x02030001), SH_UNT_PERV_2 , SH_ACS_SCOM ); @@ -6642,8 +7116,20 @@ REG64( PERV_TP_OSCERR_MASK , RULL(0x0102001A REG64( PERV_OSCERR_MCODE , RULL(0x0002001B), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_TP_OSCERR_MCODE , RULL(0x0102001B), SH_UNT_PERV_1 , SH_ACS_SCOM ); -REG64( PERV_PB_PSAVE_CFG , RULL(0x0000040F), SH_UNT_PERV , SH_ACS_SCOM ); -REG64( PERV_PIB_PB_PSAVE_CFG , RULL(0x0000040F), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG64( PERV_PB_PSAVE_CFG , RULL(0x0000041A), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_PB_PSAVE_CFG , RULL(0x0000041A), SH_UNT_PERV_0 , SH_ACS_SCOM ); + +REG64( PERV_PB_PSAVE_MON_CFG , RULL(0x0000041B), SH_UNT_PERV , SH_ACS_SCOM_RW ); +REG64( PERV_PIB_PB_PSAVE_MON_CFG , RULL(0x0000041B), SH_UNT_PERV_0 , SH_ACS_SCOM_RW ); + +REG64( PERV_EC00_PB_PSAVE_TDM_HIST , RULL(0x2000041F), SH_UNT_PERV_32 , SH_ACS_SCOM_RO ); + +REG64( PERV_PB_PSAVE_X0_HIST , RULL(0x0000041C), SH_UNT_PERV , SH_ACS_SCOM_RO ); +REG64( PERV_PIB_PB_PSAVE_X0_HIST , RULL(0x0000041C), SH_UNT_PERV_0 , SH_ACS_SCOM_RO ); + +REG64( PERV_EP00_PB_PSAVE_X1_HIST , RULL(0x1000041D), SH_UNT_PERV_16 , SH_ACS_SCOM_RO ); + +REG64( PERV_EC00_PB_PSAVE_X2_HIST , RULL(0x2000041E), SH_UNT_PERV_32 , SH_ACS_SCOM_RO ); REG32( PERV_PEEK4A0_FSI , RULL(0x000004A0), SH_UNT_PERV , SH_ACS_FSI ); @@ -6664,21 +7150,41 @@ REG64( PERV_PERV_CTRL0_FSI_BYTE , RULL(0x00002868 REG64( PERV_PERV_CTRL0_SCOM , RULL(0x0005001A), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_PERV_CTRL0 , RULL(0x0005001A), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_PERV_CTRL0_CLEAR_FSI , RULL(0x0000293A), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_PERV_CTRL0_CLEAR_FSI_BYTE , RULL(0x00002CE8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_PERV_CTRL0_CLEAR_SCOM , RULL(0x0005013A), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_PERV_CTRL0_CLEAR , RULL(0x0005013A), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_PERV_CTRL0_COPY_FSI , RULL(0x0000291A), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_PERV_CTRL0_COPY_FSI_BYTE , RULL(0x00002C68), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_PERV_CTRL0_COPY_SCOM , RULL(0x0005011A), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_PERV_CTRL0_COPY , RULL(0x0005011A), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_PERV_CTRL0_SET_FSI , RULL(0x0000292A), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_PERV_CTRL0_SET_FSI_BYTE , RULL(0x00002CA8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_PERV_CTRL0_SET_SCOM , RULL(0x0005012A), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_PERV_CTRL0_SET , RULL(0x0005012A), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_PERV_CTRL1_FSI , RULL(0x0000281B), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_PERV_CTRL1_FSI_BYTE , RULL(0x0000286C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_PERV_CTRL1_SCOM , RULL(0x0005001B), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_PERV_CTRL1 , RULL(0x0005001B), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_PERV_CTRL1_CLEAR_FSI , RULL(0x0000293B), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_PERV_CTRL1_CLEAR_FSI_BYTE , RULL(0x00002CEC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_PERV_CTRL1_CLEAR_SCOM , RULL(0x0005013B), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_PERV_CTRL1_CLEAR , RULL(0x0005013B), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_PERV_CTRL1_COPY_FSI , RULL(0x0000291B), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_PERV_CTRL1_COPY_FSI_BYTE , RULL(0x00002C6C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_PERV_CTRL1_COPY_SCOM , RULL(0x0005011B), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_PERV_CTRL1_COPY , RULL(0x0005011B), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_PERV_CTRL1_SET_FSI , RULL(0x0000292B), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_PERV_CTRL1_SET_FSI_BYTE , RULL(0x00002CAC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_PERV_CTRL1_SET_SCOM , RULL(0x0005012B), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_PERV_CTRL1_SET , RULL(0x0005012B), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG64( PERV_N3_PIB_CMD_REG , RULL(0x05002831), SH_UNT_PERV_5 , SH_ACS_SCOM ); REG64( PERV_N3_PIB_DATA_REG , RULL(0x05002832), SH_UNT_PERV_5 , SH_ACS_SCOM_RO ); @@ -6748,126 +7254,36 @@ REG64( PERV_PIB_PPE_XIRAMRA , RULL(0x00000411 REG64( PERV_PPE_XIXCR , RULL(0x00000410), SH_UNT_PERV , SH_ACS_SCOM_WO ); REG64( PERV_PIB_PPE_XIXCR , RULL(0x00000410), SH_UNT_PERV_0 , SH_ACS_SCOM_WO ); -REG64( PERV_EP00_PPM_CGCR , RULL(0x100F0165), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); -REG64( PERV_EP00_PPM_CGCR_CLEAR , RULL(0x100F0166), SH_UNT_PERV_16 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EP00_PPM_CGCR_OR , RULL(0x100F0167), SH_UNT_PERV_16 , SH_ACS_SCOM2_OR ); -REG64( PERV_EP01_PPM_CGCR , RULL(0x110F0165), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); -REG64( PERV_EP01_PPM_CGCR_CLEAR , RULL(0x110F0166), SH_UNT_PERV_17 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EP01_PPM_CGCR_OR , RULL(0x110F0167), SH_UNT_PERV_17 , SH_ACS_SCOM2_OR ); -REG64( PERV_EP02_PPM_CGCR , RULL(0x120F0165), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); -REG64( PERV_EP02_PPM_CGCR_CLEAR , RULL(0x120F0166), SH_UNT_PERV_18 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EP02_PPM_CGCR_OR , RULL(0x120F0167), SH_UNT_PERV_18 , SH_ACS_SCOM2_OR ); -REG64( PERV_EP03_PPM_CGCR , RULL(0x130F0165), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); -REG64( PERV_EP03_PPM_CGCR_CLEAR , RULL(0x130F0166), SH_UNT_PERV_19 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EP03_PPM_CGCR_OR , RULL(0x130F0167), SH_UNT_PERV_19 , SH_ACS_SCOM2_OR ); -REG64( PERV_EP04_PPM_CGCR , RULL(0x140F0165), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); -REG64( PERV_EP04_PPM_CGCR_CLEAR , RULL(0x140F0166), SH_UNT_PERV_20 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EP04_PPM_CGCR_OR , RULL(0x140F0167), SH_UNT_PERV_20 , SH_ACS_SCOM2_OR ); -REG64( PERV_EP05_PPM_CGCR , RULL(0x150F0165), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); -REG64( PERV_EP05_PPM_CGCR_CLEAR , RULL(0x150F0166), SH_UNT_PERV_21 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EP05_PPM_CGCR_OR , RULL(0x150F0167), SH_UNT_PERV_21 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC00_PPM_CGCR , RULL(0x200F0165), SH_UNT_PERV_32 , SH_ACS_SCOM_RW ); -REG64( PERV_EC00_PPM_CGCR_CLEAR , RULL(0x200F0166), SH_UNT_PERV_32 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC00_PPM_CGCR_OR , RULL(0x200F0167), SH_UNT_PERV_32 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC01_PPM_CGCR , RULL(0x210F0165), SH_UNT_PERV_33 , SH_ACS_SCOM_RW ); -REG64( PERV_EC01_PPM_CGCR_CLEAR , RULL(0x210F0166), SH_UNT_PERV_33 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC01_PPM_CGCR_OR , RULL(0x210F0167), SH_UNT_PERV_33 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC02_PPM_CGCR , RULL(0x220F0165), SH_UNT_PERV_34 , SH_ACS_SCOM_RW ); -REG64( PERV_EC02_PPM_CGCR_CLEAR , RULL(0x220F0166), SH_UNT_PERV_34 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC02_PPM_CGCR_OR , RULL(0x220F0167), SH_UNT_PERV_34 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC03_PPM_CGCR , RULL(0x230F0165), SH_UNT_PERV_35 , SH_ACS_SCOM_RW ); -REG64( PERV_EC03_PPM_CGCR_CLEAR , RULL(0x230F0166), SH_UNT_PERV_35 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC03_PPM_CGCR_OR , RULL(0x230F0167), SH_UNT_PERV_35 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC04_PPM_CGCR , RULL(0x240F0165), SH_UNT_PERV_36 , SH_ACS_SCOM_RW ); -REG64( PERV_EC04_PPM_CGCR_CLEAR , RULL(0x240F0166), SH_UNT_PERV_36 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC04_PPM_CGCR_OR , RULL(0x240F0167), SH_UNT_PERV_36 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC05_PPM_CGCR , RULL(0x250F0165), SH_UNT_PERV_37 , SH_ACS_SCOM_RW ); -REG64( PERV_EC05_PPM_CGCR_CLEAR , RULL(0x250F0166), SH_UNT_PERV_37 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC05_PPM_CGCR_OR , RULL(0x250F0167), SH_UNT_PERV_37 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC06_PPM_CGCR , RULL(0x260F0165), SH_UNT_PERV_38 , SH_ACS_SCOM_RW ); -REG64( PERV_EC06_PPM_CGCR_CLEAR , RULL(0x260F0166), SH_UNT_PERV_38 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC06_PPM_CGCR_OR , RULL(0x260F0167), SH_UNT_PERV_38 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC07_PPM_CGCR , RULL(0x270F0165), SH_UNT_PERV_39 , SH_ACS_SCOM_RW ); -REG64( PERV_EC07_PPM_CGCR_CLEAR , RULL(0x270F0166), SH_UNT_PERV_39 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC07_PPM_CGCR_OR , RULL(0x270F0167), SH_UNT_PERV_39 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC08_PPM_CGCR , RULL(0x280F0165), SH_UNT_PERV_40 , SH_ACS_SCOM_RW ); -REG64( PERV_EC08_PPM_CGCR_CLEAR , RULL(0x280F0166), SH_UNT_PERV_40 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC08_PPM_CGCR_OR , RULL(0x280F0167), SH_UNT_PERV_40 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC09_PPM_CGCR , RULL(0x290F0165), SH_UNT_PERV_41 , SH_ACS_SCOM_RW ); -REG64( PERV_EC09_PPM_CGCR_CLEAR , RULL(0x290F0166), SH_UNT_PERV_41 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC09_PPM_CGCR_OR , RULL(0x290F0167), SH_UNT_PERV_41 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC10_PPM_CGCR , RULL(0x2A0F0165), SH_UNT_PERV_42 , SH_ACS_SCOM_RW ); -REG64( PERV_EC10_PPM_CGCR_CLEAR , RULL(0x2A0F0166), SH_UNT_PERV_42 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC10_PPM_CGCR_OR , RULL(0x2A0F0167), SH_UNT_PERV_42 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC11_PPM_CGCR , RULL(0x2B0F0165), SH_UNT_PERV_43 , SH_ACS_SCOM_RW ); -REG64( PERV_EC11_PPM_CGCR_CLEAR , RULL(0x2B0F0166), SH_UNT_PERV_43 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC11_PPM_CGCR_OR , RULL(0x2B0F0167), SH_UNT_PERV_43 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC12_PPM_CGCR , RULL(0x2C0F0165), SH_UNT_PERV_44 , SH_ACS_SCOM_RW ); -REG64( PERV_EC12_PPM_CGCR_CLEAR , RULL(0x2C0F0166), SH_UNT_PERV_44 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC12_PPM_CGCR_OR , RULL(0x2C0F0167), SH_UNT_PERV_44 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC13_PPM_CGCR , RULL(0x2D0F0165), SH_UNT_PERV_45 , SH_ACS_SCOM_RW ); -REG64( PERV_EC13_PPM_CGCR_CLEAR , RULL(0x2D0F0166), SH_UNT_PERV_45 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC13_PPM_CGCR_OR , RULL(0x2D0F0167), SH_UNT_PERV_45 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC14_PPM_CGCR , RULL(0x2E0F0165), SH_UNT_PERV_46 , SH_ACS_SCOM_RW ); -REG64( PERV_EC14_PPM_CGCR_CLEAR , RULL(0x2E0F0166), SH_UNT_PERV_46 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC14_PPM_CGCR_OR , RULL(0x2E0F0167), SH_UNT_PERV_46 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC15_PPM_CGCR , RULL(0x2F0F0165), SH_UNT_PERV_47 , SH_ACS_SCOM_RW ); -REG64( PERV_EC15_PPM_CGCR_CLEAR , RULL(0x2F0F0166), SH_UNT_PERV_47 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC15_PPM_CGCR_OR , RULL(0x2F0F0167), SH_UNT_PERV_47 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC16_PPM_CGCR , RULL(0x300F0165), SH_UNT_PERV_48 , SH_ACS_SCOM_RW ); -REG64( PERV_EC16_PPM_CGCR_CLEAR , RULL(0x300F0166), SH_UNT_PERV_48 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC16_PPM_CGCR_OR , RULL(0x300F0167), SH_UNT_PERV_48 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC17_PPM_CGCR , RULL(0x310F0165), SH_UNT_PERV_49 , SH_ACS_SCOM_RW ); -REG64( PERV_EC17_PPM_CGCR_CLEAR , RULL(0x310F0166), SH_UNT_PERV_49 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC17_PPM_CGCR_OR , RULL(0x310F0167), SH_UNT_PERV_49 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC18_PPM_CGCR , RULL(0x320F0165), SH_UNT_PERV_50 , SH_ACS_SCOM_RW ); -REG64( PERV_EC18_PPM_CGCR_CLEAR , RULL(0x320F0166), SH_UNT_PERV_50 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC18_PPM_CGCR_OR , RULL(0x320F0167), SH_UNT_PERV_50 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC19_PPM_CGCR , RULL(0x330F0165), SH_UNT_PERV_51 , SH_ACS_SCOM_RW ); -REG64( PERV_EC19_PPM_CGCR_CLEAR , RULL(0x330F0166), SH_UNT_PERV_51 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC19_PPM_CGCR_OR , RULL(0x330F0167), SH_UNT_PERV_51 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC20_PPM_CGCR , RULL(0x340F0165), SH_UNT_PERV_52 , SH_ACS_SCOM_RW ); -REG64( PERV_EC20_PPM_CGCR_CLEAR , RULL(0x340F0166), SH_UNT_PERV_52 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC20_PPM_CGCR_OR , RULL(0x340F0167), SH_UNT_PERV_52 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC21_PPM_CGCR , RULL(0x350F0165), SH_UNT_PERV_53 , SH_ACS_SCOM_RW ); -REG64( PERV_EC21_PPM_CGCR_CLEAR , RULL(0x350F0166), SH_UNT_PERV_53 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC21_PPM_CGCR_OR , RULL(0x350F0167), SH_UNT_PERV_53 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC22_PPM_CGCR , RULL(0x360F0165), SH_UNT_PERV_54 , SH_ACS_SCOM_RW ); -REG64( PERV_EC22_PPM_CGCR_CLEAR , RULL(0x360F0166), SH_UNT_PERV_54 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC22_PPM_CGCR_OR , RULL(0x360F0167), SH_UNT_PERV_54 , SH_ACS_SCOM2_OR ); -REG64( PERV_EC23_PPM_CGCR , RULL(0x370F0165), SH_UNT_PERV_55 , SH_ACS_SCOM_RW ); -REG64( PERV_EC23_PPM_CGCR_CLEAR , RULL(0x370F0166), SH_UNT_PERV_55 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EC23_PPM_CGCR_OR , RULL(0x370F0167), SH_UNT_PERV_55 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP00_PPM_CGCR , RULL(0x100F0164), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); +REG64( PERV_EP01_PPM_CGCR , RULL(0x110F0164), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); +REG64( PERV_EP02_PPM_CGCR , RULL(0x120F0164), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); +REG64( PERV_EP03_PPM_CGCR , RULL(0x130F0164), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); +REG64( PERV_EP04_PPM_CGCR , RULL(0x140F0164), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); +REG64( PERV_EP05_PPM_CGCR , RULL(0x150F0164), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); +REG64( PERV_EC00_PPM_CGCR , RULL(0x200F0164), SH_UNT_PERV_32 , SH_ACS_SCOM_RW ); +REG64( PERV_EC01_PPM_CGCR , RULL(0x210F0164), SH_UNT_PERV_33 , SH_ACS_SCOM_RW ); +REG64( PERV_EC02_PPM_CGCR , RULL(0x220F0164), SH_UNT_PERV_34 , SH_ACS_SCOM_RW ); +REG64( PERV_EC03_PPM_CGCR , RULL(0x230F0164), SH_UNT_PERV_35 , SH_ACS_SCOM_RW ); +REG64( PERV_EC04_PPM_CGCR , RULL(0x240F0164), SH_UNT_PERV_36 , SH_ACS_SCOM_RW ); +REG64( PERV_EC05_PPM_CGCR , RULL(0x250F0164), SH_UNT_PERV_37 , SH_ACS_SCOM_RW ); +REG64( PERV_EC06_PPM_CGCR , RULL(0x260F0164), SH_UNT_PERV_38 , SH_ACS_SCOM_RW ); +REG64( PERV_EC07_PPM_CGCR , RULL(0x270F0164), SH_UNT_PERV_39 , SH_ACS_SCOM_RW ); +REG64( PERV_EC08_PPM_CGCR , RULL(0x280F0164), SH_UNT_PERV_40 , SH_ACS_SCOM_RW ); +REG64( PERV_EC09_PPM_CGCR , RULL(0x290F0164), SH_UNT_PERV_41 , SH_ACS_SCOM_RW ); +REG64( PERV_EC10_PPM_CGCR , RULL(0x2A0F0164), SH_UNT_PERV_42 , SH_ACS_SCOM_RW ); +REG64( PERV_EC11_PPM_CGCR , RULL(0x2B0F0164), SH_UNT_PERV_43 , SH_ACS_SCOM_RW ); +REG64( PERV_EC12_PPM_CGCR , RULL(0x2C0F0164), SH_UNT_PERV_44 , SH_ACS_SCOM_RW ); +REG64( PERV_EC13_PPM_CGCR , RULL(0x2D0F0164), SH_UNT_PERV_45 , SH_ACS_SCOM_RW ); +REG64( PERV_EC14_PPM_CGCR , RULL(0x2E0F0164), SH_UNT_PERV_46 , SH_ACS_SCOM_RW ); +REG64( PERV_EC15_PPM_CGCR , RULL(0x2F0F0164), SH_UNT_PERV_47 , SH_ACS_SCOM_RW ); +REG64( PERV_EC16_PPM_CGCR , RULL(0x300F0164), SH_UNT_PERV_48 , SH_ACS_SCOM_RW ); +REG64( PERV_EC17_PPM_CGCR , RULL(0x310F0164), SH_UNT_PERV_49 , SH_ACS_SCOM_RW ); +REG64( PERV_EC18_PPM_CGCR , RULL(0x320F0164), SH_UNT_PERV_50 , SH_ACS_SCOM_RW ); +REG64( PERV_EC19_PPM_CGCR , RULL(0x330F0164), SH_UNT_PERV_51 , SH_ACS_SCOM_RW ); +REG64( PERV_EC20_PPM_CGCR , RULL(0x340F0164), SH_UNT_PERV_52 , SH_ACS_SCOM_RW ); +REG64( PERV_EC21_PPM_CGCR , RULL(0x350F0164), SH_UNT_PERV_53 , SH_ACS_SCOM_RW ); +REG64( PERV_EC22_PPM_CGCR , RULL(0x360F0164), SH_UNT_PERV_54 , SH_ACS_SCOM_RW ); +REG64( PERV_EC23_PPM_CGCR , RULL(0x370F0164), SH_UNT_PERV_55 , SH_ACS_SCOM_RW ); REG64( PERV_EP00_PPM_GPMMR_SCOM , RULL(0x100F0100), SH_UNT_PERV_16 , SH_ACS_SCOM ); REG64( PERV_EP00_PPM_GPMMR_SCOM1 , RULL(0x100F0101), SH_UNT_PERV_16 , SH_ACS_SCOM1 ); @@ -6960,36 +7376,36 @@ REG64( PERV_EC23_PPM_GPMMR_SCOM , RULL(0x370F0100 REG64( PERV_EC23_PPM_GPMMR_SCOM1 , RULL(0x370F0101), SH_UNT_PERV_55 , SH_ACS_SCOM1 ); REG64( PERV_EC23_PPM_GPMMR_SCOM2 , RULL(0x370F0102), SH_UNT_PERV_55 , SH_ACS_SCOM2 ); -REG64( PERV_EP00_PPM_IVRMAVR , RULL(0x100F01B5), SH_UNT_PERV_16 , SH_ACS_SCOM ); -REG64( PERV_EP01_PPM_IVRMAVR , RULL(0x110F01B5), SH_UNT_PERV_17 , SH_ACS_SCOM ); -REG64( PERV_EP02_PPM_IVRMAVR , RULL(0x120F01B5), SH_UNT_PERV_18 , SH_ACS_SCOM ); -REG64( PERV_EP03_PPM_IVRMAVR , RULL(0x130F01B5), SH_UNT_PERV_19 , SH_ACS_SCOM ); -REG64( PERV_EP04_PPM_IVRMAVR , RULL(0x140F01B5), SH_UNT_PERV_20 , SH_ACS_SCOM ); -REG64( PERV_EP05_PPM_IVRMAVR , RULL(0x150F01B5), SH_UNT_PERV_21 , SH_ACS_SCOM ); -REG64( PERV_EC00_PPM_IVRMAVR , RULL(0x200F01B5), SH_UNT_PERV_32 , SH_ACS_SCOM ); -REG64( PERV_EC01_PPM_IVRMAVR , RULL(0x210F01B5), SH_UNT_PERV_33 , SH_ACS_SCOM ); -REG64( PERV_EC02_PPM_IVRMAVR , RULL(0x220F01B5), SH_UNT_PERV_34 , SH_ACS_SCOM ); -REG64( PERV_EC03_PPM_IVRMAVR , RULL(0x230F01B5), SH_UNT_PERV_35 , SH_ACS_SCOM ); -REG64( PERV_EC04_PPM_IVRMAVR , RULL(0x240F01B5), SH_UNT_PERV_36 , SH_ACS_SCOM ); -REG64( PERV_EC05_PPM_IVRMAVR , RULL(0x250F01B5), SH_UNT_PERV_37 , SH_ACS_SCOM ); -REG64( PERV_EC06_PPM_IVRMAVR , RULL(0x260F01B5), SH_UNT_PERV_38 , SH_ACS_SCOM ); -REG64( PERV_EC07_PPM_IVRMAVR , RULL(0x270F01B5), SH_UNT_PERV_39 , SH_ACS_SCOM ); -REG64( PERV_EC08_PPM_IVRMAVR , RULL(0x280F01B5), SH_UNT_PERV_40 , SH_ACS_SCOM ); -REG64( PERV_EC09_PPM_IVRMAVR , RULL(0x290F01B5), SH_UNT_PERV_41 , SH_ACS_SCOM ); -REG64( PERV_EC10_PPM_IVRMAVR , RULL(0x2A0F01B5), SH_UNT_PERV_42 , SH_ACS_SCOM ); -REG64( PERV_EC11_PPM_IVRMAVR , RULL(0x2B0F01B5), SH_UNT_PERV_43 , SH_ACS_SCOM ); -REG64( PERV_EC12_PPM_IVRMAVR , RULL(0x2C0F01B5), SH_UNT_PERV_44 , SH_ACS_SCOM ); -REG64( PERV_EC13_PPM_IVRMAVR , RULL(0x2D0F01B5), SH_UNT_PERV_45 , SH_ACS_SCOM ); -REG64( PERV_EC14_PPM_IVRMAVR , RULL(0x2E0F01B5), SH_UNT_PERV_46 , SH_ACS_SCOM ); -REG64( PERV_EC15_PPM_IVRMAVR , RULL(0x2F0F01B5), SH_UNT_PERV_47 , SH_ACS_SCOM ); -REG64( PERV_EC16_PPM_IVRMAVR , RULL(0x300F01B5), SH_UNT_PERV_48 , SH_ACS_SCOM ); -REG64( PERV_EC17_PPM_IVRMAVR , RULL(0x310F01B5), SH_UNT_PERV_49 , SH_ACS_SCOM ); -REG64( PERV_EC18_PPM_IVRMAVR , RULL(0x320F01B5), SH_UNT_PERV_50 , SH_ACS_SCOM ); -REG64( PERV_EC19_PPM_IVRMAVR , RULL(0x330F01B5), SH_UNT_PERV_51 , SH_ACS_SCOM ); -REG64( PERV_EC20_PPM_IVRMAVR , RULL(0x340F01B5), SH_UNT_PERV_52 , SH_ACS_SCOM ); -REG64( PERV_EC21_PPM_IVRMAVR , RULL(0x350F01B5), SH_UNT_PERV_53 , SH_ACS_SCOM ); -REG64( PERV_EC22_PPM_IVRMAVR , RULL(0x360F01B5), SH_UNT_PERV_54 , SH_ACS_SCOM ); -REG64( PERV_EC23_PPM_IVRMAVR , RULL(0x370F01B5), SH_UNT_PERV_55 , SH_ACS_SCOM ); +REG64( PERV_EP00_PPM_IVRMAVR , RULL(0x100F01B5), SH_UNT_PERV_16 , SH_ACS_SCOM_RO ); +REG64( PERV_EP01_PPM_IVRMAVR , RULL(0x110F01B5), SH_UNT_PERV_17 , SH_ACS_SCOM_RO ); +REG64( PERV_EP02_PPM_IVRMAVR , RULL(0x120F01B5), SH_UNT_PERV_18 , SH_ACS_SCOM_RO ); +REG64( PERV_EP03_PPM_IVRMAVR , RULL(0x130F01B5), SH_UNT_PERV_19 , SH_ACS_SCOM_RO ); +REG64( PERV_EP04_PPM_IVRMAVR , RULL(0x140F01B5), SH_UNT_PERV_20 , SH_ACS_SCOM_RO ); +REG64( PERV_EP05_PPM_IVRMAVR , RULL(0x150F01B5), SH_UNT_PERV_21 , SH_ACS_SCOM_RO ); +REG64( PERV_EC00_PPM_IVRMAVR , RULL(0x200F01B5), SH_UNT_PERV_32 , SH_ACS_SCOM_RO ); +REG64( PERV_EC01_PPM_IVRMAVR , RULL(0x210F01B5), SH_UNT_PERV_33 , SH_ACS_SCOM_RO ); +REG64( PERV_EC02_PPM_IVRMAVR , RULL(0x220F01B5), SH_UNT_PERV_34 , SH_ACS_SCOM_RO ); +REG64( PERV_EC03_PPM_IVRMAVR , RULL(0x230F01B5), SH_UNT_PERV_35 , SH_ACS_SCOM_RO ); +REG64( PERV_EC04_PPM_IVRMAVR , RULL(0x240F01B5), SH_UNT_PERV_36 , SH_ACS_SCOM_RO ); +REG64( PERV_EC05_PPM_IVRMAVR , RULL(0x250F01B5), SH_UNT_PERV_37 , SH_ACS_SCOM_RO ); +REG64( PERV_EC06_PPM_IVRMAVR , RULL(0x260F01B5), SH_UNT_PERV_38 , SH_ACS_SCOM_RO ); +REG64( PERV_EC07_PPM_IVRMAVR , RULL(0x270F01B5), SH_UNT_PERV_39 , SH_ACS_SCOM_RO ); +REG64( PERV_EC08_PPM_IVRMAVR , RULL(0x280F01B5), SH_UNT_PERV_40 , SH_ACS_SCOM_RO ); +REG64( PERV_EC09_PPM_IVRMAVR , RULL(0x290F01B5), SH_UNT_PERV_41 , SH_ACS_SCOM_RO ); +REG64( PERV_EC10_PPM_IVRMAVR , RULL(0x2A0F01B5), SH_UNT_PERV_42 , SH_ACS_SCOM_RO ); +REG64( PERV_EC11_PPM_IVRMAVR , RULL(0x2B0F01B5), SH_UNT_PERV_43 , SH_ACS_SCOM_RO ); +REG64( PERV_EC12_PPM_IVRMAVR , RULL(0x2C0F01B5), SH_UNT_PERV_44 , SH_ACS_SCOM_RO ); +REG64( PERV_EC13_PPM_IVRMAVR , RULL(0x2D0F01B5), SH_UNT_PERV_45 , SH_ACS_SCOM_RO ); +REG64( PERV_EC14_PPM_IVRMAVR , RULL(0x2E0F01B5), SH_UNT_PERV_46 , SH_ACS_SCOM_RO ); +REG64( PERV_EC15_PPM_IVRMAVR , RULL(0x2F0F01B5), SH_UNT_PERV_47 , SH_ACS_SCOM_RO ); +REG64( PERV_EC16_PPM_IVRMAVR , RULL(0x300F01B5), SH_UNT_PERV_48 , SH_ACS_SCOM_RO ); +REG64( PERV_EC17_PPM_IVRMAVR , RULL(0x310F01B5), SH_UNT_PERV_49 , SH_ACS_SCOM_RO ); +REG64( PERV_EC18_PPM_IVRMAVR , RULL(0x320F01B5), SH_UNT_PERV_50 , SH_ACS_SCOM_RO ); +REG64( PERV_EC19_PPM_IVRMAVR , RULL(0x330F01B5), SH_UNT_PERV_51 , SH_ACS_SCOM_RO ); +REG64( PERV_EC20_PPM_IVRMAVR , RULL(0x340F01B5), SH_UNT_PERV_52 , SH_ACS_SCOM_RO ); +REG64( PERV_EC21_PPM_IVRMAVR , RULL(0x350F01B5), SH_UNT_PERV_53 , SH_ACS_SCOM_RO ); +REG64( PERV_EC22_PPM_IVRMAVR , RULL(0x360F01B5), SH_UNT_PERV_54 , SH_ACS_SCOM_RO ); +REG64( PERV_EC23_PPM_IVRMAVR , RULL(0x370F01B5), SH_UNT_PERV_55 , SH_ACS_SCOM_RO ); REG64( PERV_EP00_PPM_IVRMCR , RULL(0x100F01B0), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); REG64( PERV_EP00_PPM_IVRMCR_CLEAR , RULL(0x100F01B1), SH_UNT_PERV_16 , @@ -7986,9 +8402,14 @@ REG64( PERV_EC21_PROTECT_MODE_REG , RULL(0x350F03FE REG64( PERV_EC22_PROTECT_MODE_REG , RULL(0x360F03FE), SH_UNT_PERV_54 , SH_ACS_SCOM ); REG64( PERV_EC23_PROTECT_MODE_REG , RULL(0x370F03FE), SH_UNT_PERV_55 , SH_ACS_SCOM ); -REG64( PERV_PRV_DBG_PPE , RULL(0x00002000), SH_UNT_PERV , SH_ACS_PPE ); -REG64( PERV_PRV_DBG_PPE1 , RULL(0x00002010), SH_UNT_PERV , SH_ACS_PPE1 ); -REG64( PERV_PRV_DBG_PPE2 , RULL(0x00002018), SH_UNT_PERV , SH_ACS_PPE2 ); +REG64( PERV_PSCOM_ERROR_MASK , RULL(0x00010002), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_PSCOM_ERROR_MASK , RULL(0x01010002), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_PSCOM_MODE_REG , RULL(0x00010000), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_PSCOM_MODE_REG , RULL(0x01010000), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_PSCOM_STATUS_ERROR_REG , RULL(0x00010001), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_PSCOM_STATUS_ERROR_REG , RULL(0x01010001), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_EP00_QPPM_DPLL_CTRL , RULL(0x100F0152), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); REG64( PERV_EP00_QPPM_DPLL_CTRL_CLEAR , RULL(0x100F0153), SH_UNT_PERV_16 , @@ -8043,43 +8464,18 @@ REG64( PERV_EP03_QPPM_DPLL_STAT , RULL(0x130F0155 REG64( PERV_EP04_QPPM_DPLL_STAT , RULL(0x140F0155), SH_UNT_PERV_20 , SH_ACS_SCOM_RO ); REG64( PERV_EP05_QPPM_DPLL_STAT , RULL(0x150F0155), SH_UNT_PERV_21 , SH_ACS_SCOM_RO ); -REG64( PERV_EP00_QPPM_EDRAM_CTRL , RULL(0x100F01BD), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); -REG64( PERV_EP00_QPPM_EDRAM_CTRL_CLEAR , RULL(0x100F01BE), SH_UNT_PERV_16 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EP00_QPPM_EDRAM_CTRL_OR , RULL(0x100F01BF), SH_UNT_PERV_16 , SH_ACS_SCOM2_OR ); -REG64( PERV_EP01_QPPM_EDRAM_CTRL , RULL(0x110F01BD), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); -REG64( PERV_EP01_QPPM_EDRAM_CTRL_CLEAR , RULL(0x110F01BE), SH_UNT_PERV_17 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EP01_QPPM_EDRAM_CTRL_OR , RULL(0x110F01BF), SH_UNT_PERV_17 , SH_ACS_SCOM2_OR ); -REG64( PERV_EP02_QPPM_EDRAM_CTRL , RULL(0x120F01BD), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); -REG64( PERV_EP02_QPPM_EDRAM_CTRL_CLEAR , RULL(0x120F01BE), SH_UNT_PERV_18 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EP02_QPPM_EDRAM_CTRL_OR , RULL(0x120F01BF), SH_UNT_PERV_18 , SH_ACS_SCOM2_OR ); -REG64( PERV_EP03_QPPM_EDRAM_CTRL , RULL(0x130F01BD), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); -REG64( PERV_EP03_QPPM_EDRAM_CTRL_CLEAR , RULL(0x130F01BE), SH_UNT_PERV_19 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EP03_QPPM_EDRAM_CTRL_OR , RULL(0x130F01BF), SH_UNT_PERV_19 , SH_ACS_SCOM2_OR ); -REG64( PERV_EP04_QPPM_EDRAM_CTRL , RULL(0x140F01BD), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); -REG64( PERV_EP04_QPPM_EDRAM_CTRL_CLEAR , RULL(0x140F01BE), SH_UNT_PERV_20 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EP04_QPPM_EDRAM_CTRL_OR , RULL(0x140F01BF), SH_UNT_PERV_20 , SH_ACS_SCOM2_OR ); -REG64( PERV_EP05_QPPM_EDRAM_CTRL , RULL(0x150F01BD), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); -REG64( PERV_EP05_QPPM_EDRAM_CTRL_CLEAR , RULL(0x150F01BE), SH_UNT_PERV_21 , - SH_ACS_SCOM1_CLEAR ); -REG64( PERV_EP05_QPPM_EDRAM_CTRL_OR , RULL(0x150F01BF), SH_UNT_PERV_21 , SH_ACS_SCOM2_OR ); - REG64( PERV_EP00_QPPM_ERR , RULL(0x100F0121), SH_UNT_PERV_16 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EP01_QPPM_ERR , RULL(0x110F0121), SH_UNT_PERV_17 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EP02_QPPM_ERR , RULL(0x120F0121), SH_UNT_PERV_18 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EP03_QPPM_ERR , RULL(0x130F0121), SH_UNT_PERV_19 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EP04_QPPM_ERR , RULL(0x140F0121), SH_UNT_PERV_20 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EP05_QPPM_ERR , RULL(0x150F0121), SH_UNT_PERV_21 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EP00_QPPM_ERRMSK , RULL(0x100F0122), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); REG64( PERV_EP01_QPPM_ERRMSK , RULL(0x110F0122), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); @@ -8089,17 +8485,42 @@ REG64( PERV_EP04_QPPM_ERRMSK , RULL(0x140F0122 REG64( PERV_EP05_QPPM_ERRMSK , RULL(0x150F0122), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); REG64( PERV_EP00_QPPM_ERRSUM , RULL(0x100F0120), SH_UNT_PERV_16 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EP01_QPPM_ERRSUM , RULL(0x110F0120), SH_UNT_PERV_17 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EP02_QPPM_ERRSUM , RULL(0x120F0120), SH_UNT_PERV_18 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EP03_QPPM_ERRSUM , RULL(0x130F0120), SH_UNT_PERV_19 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EP04_QPPM_ERRSUM , RULL(0x140F0120), SH_UNT_PERV_20 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); REG64( PERV_EP05_QPPM_ERRSUM , RULL(0x150F0120), SH_UNT_PERV_21 , - SH_ACS_SCOM_WCLRPART ); + SH_ACS_SCOM_WCLEAR ); + +REG64( PERV_EP00_QPPM_EXCGCR , RULL(0x100F0165), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); +REG64( PERV_EP00_QPPM_EXCGCR_CLEAR , RULL(0x100F0166), SH_UNT_PERV_16 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP00_QPPM_EXCGCR_OR , RULL(0x100F0167), SH_UNT_PERV_16 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP01_QPPM_EXCGCR , RULL(0x110F0165), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); +REG64( PERV_EP01_QPPM_EXCGCR_CLEAR , RULL(0x110F0166), SH_UNT_PERV_17 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP01_QPPM_EXCGCR_OR , RULL(0x110F0167), SH_UNT_PERV_17 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP02_QPPM_EXCGCR , RULL(0x120F0165), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); +REG64( PERV_EP02_QPPM_EXCGCR_CLEAR , RULL(0x120F0166), SH_UNT_PERV_18 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP02_QPPM_EXCGCR_OR , RULL(0x120F0167), SH_UNT_PERV_18 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP03_QPPM_EXCGCR , RULL(0x130F0165), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); +REG64( PERV_EP03_QPPM_EXCGCR_CLEAR , RULL(0x130F0166), SH_UNT_PERV_19 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP03_QPPM_EXCGCR_OR , RULL(0x130F0167), SH_UNT_PERV_19 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP04_QPPM_EXCGCR , RULL(0x140F0165), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); +REG64( PERV_EP04_QPPM_EXCGCR_CLEAR , RULL(0x140F0166), SH_UNT_PERV_20 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP04_QPPM_EXCGCR_OR , RULL(0x140F0167), SH_UNT_PERV_20 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP05_QPPM_EXCGCR , RULL(0x150F0165), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); +REG64( PERV_EP05_QPPM_EXCGCR_CLEAR , RULL(0x150F0166), SH_UNT_PERV_21 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP05_QPPM_EXCGCR_OR , RULL(0x150F0167), SH_UNT_PERV_21 , SH_ACS_SCOM2_OR ); REG64( PERV_EP00_QPPM_OCCHB , RULL(0x100F015F), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); REG64( PERV_EP01_QPPM_OCCHB , RULL(0x110F015F), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); @@ -8108,24 +8529,30 @@ REG64( PERV_EP03_QPPM_OCCHB , RULL(0x130F015F REG64( PERV_EP04_QPPM_OCCHB , RULL(0x140F015F), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); REG64( PERV_EP05_QPPM_OCCHB , RULL(0x150F015F), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); -REG64( PERV_EP00_QPPM_QACCR_SCOM , RULL(0x100F0160), SH_UNT_PERV_16 , SH_ACS_SCOM ); -REG64( PERV_EP00_QPPM_QACCR_SCOM1 , RULL(0x100F0161), SH_UNT_PERV_16 , SH_ACS_SCOM1 ); -REG64( PERV_EP00_QPPM_QACCR_SCOM2 , RULL(0x100F0162), SH_UNT_PERV_16 , SH_ACS_SCOM2 ); -REG64( PERV_EP01_QPPM_QACCR_SCOM , RULL(0x110F0160), SH_UNT_PERV_17 , SH_ACS_SCOM ); -REG64( PERV_EP01_QPPM_QACCR_SCOM1 , RULL(0x110F0161), SH_UNT_PERV_17 , SH_ACS_SCOM1 ); -REG64( PERV_EP01_QPPM_QACCR_SCOM2 , RULL(0x110F0162), SH_UNT_PERV_17 , SH_ACS_SCOM2 ); -REG64( PERV_EP02_QPPM_QACCR_SCOM , RULL(0x120F0160), SH_UNT_PERV_18 , SH_ACS_SCOM ); -REG64( PERV_EP02_QPPM_QACCR_SCOM1 , RULL(0x120F0161), SH_UNT_PERV_18 , SH_ACS_SCOM1 ); -REG64( PERV_EP02_QPPM_QACCR_SCOM2 , RULL(0x120F0162), SH_UNT_PERV_18 , SH_ACS_SCOM2 ); -REG64( PERV_EP03_QPPM_QACCR_SCOM , RULL(0x130F0160), SH_UNT_PERV_19 , SH_ACS_SCOM ); -REG64( PERV_EP03_QPPM_QACCR_SCOM1 , RULL(0x130F0161), SH_UNT_PERV_19 , SH_ACS_SCOM1 ); -REG64( PERV_EP03_QPPM_QACCR_SCOM2 , RULL(0x130F0162), SH_UNT_PERV_19 , SH_ACS_SCOM2 ); -REG64( PERV_EP04_QPPM_QACCR_SCOM , RULL(0x140F0160), SH_UNT_PERV_20 , SH_ACS_SCOM ); -REG64( PERV_EP04_QPPM_QACCR_SCOM1 , RULL(0x140F0161), SH_UNT_PERV_20 , SH_ACS_SCOM1 ); -REG64( PERV_EP04_QPPM_QACCR_SCOM2 , RULL(0x140F0162), SH_UNT_PERV_20 , SH_ACS_SCOM2 ); -REG64( PERV_EP05_QPPM_QACCR_SCOM , RULL(0x150F0160), SH_UNT_PERV_21 , SH_ACS_SCOM ); -REG64( PERV_EP05_QPPM_QACCR_SCOM1 , RULL(0x150F0161), SH_UNT_PERV_21 , SH_ACS_SCOM1 ); -REG64( PERV_EP05_QPPM_QACCR_SCOM2 , RULL(0x150F0162), SH_UNT_PERV_21 , SH_ACS_SCOM2 ); +REG64( PERV_EP00_QPPM_QACCR , RULL(0x100F0160), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); +REG64( PERV_EP00_QPPM_QACCR_CLEAR , RULL(0x100F0161), SH_UNT_PERV_16 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP00_QPPM_QACCR_OR , RULL(0x100F0162), SH_UNT_PERV_16 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP01_QPPM_QACCR , RULL(0x110F0160), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); +REG64( PERV_EP01_QPPM_QACCR_CLEAR , RULL(0x110F0161), SH_UNT_PERV_17 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP01_QPPM_QACCR_OR , RULL(0x110F0162), SH_UNT_PERV_17 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP02_QPPM_QACCR , RULL(0x120F0160), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); +REG64( PERV_EP02_QPPM_QACCR_CLEAR , RULL(0x120F0161), SH_UNT_PERV_18 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP02_QPPM_QACCR_OR , RULL(0x120F0162), SH_UNT_PERV_18 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP03_QPPM_QACCR , RULL(0x130F0160), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); +REG64( PERV_EP03_QPPM_QACCR_CLEAR , RULL(0x130F0161), SH_UNT_PERV_19 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP03_QPPM_QACCR_OR , RULL(0x130F0162), SH_UNT_PERV_19 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP04_QPPM_QACCR , RULL(0x140F0160), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); +REG64( PERV_EP04_QPPM_QACCR_CLEAR , RULL(0x140F0161), SH_UNT_PERV_20 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP04_QPPM_QACCR_OR , RULL(0x140F0162), SH_UNT_PERV_20 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP05_QPPM_QACCR , RULL(0x150F0160), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); +REG64( PERV_EP05_QPPM_QACCR_CLEAR , RULL(0x150F0161), SH_UNT_PERV_21 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP05_QPPM_QACCR_OR , RULL(0x150F0162), SH_UNT_PERV_21 , SH_ACS_SCOM2_OR ); REG64( PERV_EP00_QPPM_QACSR , RULL(0x100F0163), SH_UNT_PERV_16 , SH_ACS_SCOM_RO ); REG64( PERV_EP01_QPPM_QACSR , RULL(0x110F0163), SH_UNT_PERV_17 , SH_ACS_SCOM_RO ); @@ -8134,31 +8561,63 @@ REG64( PERV_EP03_QPPM_QACSR , RULL(0x130F0163 REG64( PERV_EP04_QPPM_QACSR , RULL(0x140F0163), SH_UNT_PERV_20 , SH_ACS_SCOM_RO ); REG64( PERV_EP05_QPPM_QACSR , RULL(0x150F0163), SH_UNT_PERV_21 , SH_ACS_SCOM_RO ); -REG64( PERV_EP00_QPPM_QPMMR_SCOM , RULL(0x100F0103), SH_UNT_PERV_16 , SH_ACS_SCOM ); -REG64( PERV_EP00_QPPM_QPMMR_SCOM1 , RULL(0x100F0104), SH_UNT_PERV_16 , SH_ACS_SCOM1 ); -REG64( PERV_EP00_QPPM_QPMMR_SCOM2 , RULL(0x100F0105), SH_UNT_PERV_16 , SH_ACS_SCOM2 ); -REG64( PERV_EP01_QPPM_QPMMR_SCOM , RULL(0x110F0103), SH_UNT_PERV_17 , SH_ACS_SCOM ); -REG64( PERV_EP01_QPPM_QPMMR_SCOM1 , RULL(0x110F0104), SH_UNT_PERV_17 , SH_ACS_SCOM1 ); -REG64( PERV_EP01_QPPM_QPMMR_SCOM2 , RULL(0x110F0105), SH_UNT_PERV_17 , SH_ACS_SCOM2 ); -REG64( PERV_EP02_QPPM_QPMMR_SCOM , RULL(0x120F0103), SH_UNT_PERV_18 , SH_ACS_SCOM ); -REG64( PERV_EP02_QPPM_QPMMR_SCOM1 , RULL(0x120F0104), SH_UNT_PERV_18 , SH_ACS_SCOM1 ); -REG64( PERV_EP02_QPPM_QPMMR_SCOM2 , RULL(0x120F0105), SH_UNT_PERV_18 , SH_ACS_SCOM2 ); -REG64( PERV_EP03_QPPM_QPMMR_SCOM , RULL(0x130F0103), SH_UNT_PERV_19 , SH_ACS_SCOM ); -REG64( PERV_EP03_QPPM_QPMMR_SCOM1 , RULL(0x130F0104), SH_UNT_PERV_19 , SH_ACS_SCOM1 ); -REG64( PERV_EP03_QPPM_QPMMR_SCOM2 , RULL(0x130F0105), SH_UNT_PERV_19 , SH_ACS_SCOM2 ); -REG64( PERV_EP04_QPPM_QPMMR_SCOM , RULL(0x140F0103), SH_UNT_PERV_20 , SH_ACS_SCOM ); -REG64( PERV_EP04_QPPM_QPMMR_SCOM1 , RULL(0x140F0104), SH_UNT_PERV_20 , SH_ACS_SCOM1 ); -REG64( PERV_EP04_QPPM_QPMMR_SCOM2 , RULL(0x140F0105), SH_UNT_PERV_20 , SH_ACS_SCOM2 ); -REG64( PERV_EP05_QPPM_QPMMR_SCOM , RULL(0x150F0103), SH_UNT_PERV_21 , SH_ACS_SCOM ); -REG64( PERV_EP05_QPPM_QPMMR_SCOM1 , RULL(0x150F0104), SH_UNT_PERV_21 , SH_ACS_SCOM1 ); -REG64( PERV_EP05_QPPM_QPMMR_SCOM2 , RULL(0x150F0105), SH_UNT_PERV_21 , SH_ACS_SCOM2 ); - -REG64( PERV_EP00_QPPM_VDMCFGR , RULL(0x100F01B6), SH_UNT_PERV_16 , SH_ACS_SCOM ); -REG64( PERV_EP01_QPPM_VDMCFGR , RULL(0x110F01B6), SH_UNT_PERV_17 , SH_ACS_SCOM ); -REG64( PERV_EP02_QPPM_VDMCFGR , RULL(0x120F01B6), SH_UNT_PERV_18 , SH_ACS_SCOM ); -REG64( PERV_EP03_QPPM_VDMCFGR , RULL(0x130F01B6), SH_UNT_PERV_19 , SH_ACS_SCOM ); -REG64( PERV_EP04_QPPM_VDMCFGR , RULL(0x140F01B6), SH_UNT_PERV_20 , SH_ACS_SCOM ); -REG64( PERV_EP05_QPPM_VDMCFGR , RULL(0x150F01B6), SH_UNT_PERV_21 , SH_ACS_SCOM ); +REG64( PERV_EP00_QPPM_QCCR_SCOM , RULL(0x100F01BD), SH_UNT_PERV_16 , SH_ACS_SCOM ); +REG64( PERV_EP00_QPPM_QCCR_SCOM1 , RULL(0x100F01BE), SH_UNT_PERV_16 , SH_ACS_SCOM1 ); +REG64( PERV_EP00_QPPM_QCCR_SCOM2 , RULL(0x100F01BF), SH_UNT_PERV_16 , SH_ACS_SCOM2 ); +REG64( PERV_EP01_QPPM_QCCR_SCOM , RULL(0x110F01BD), SH_UNT_PERV_17 , SH_ACS_SCOM ); +REG64( PERV_EP01_QPPM_QCCR_SCOM1 , RULL(0x110F01BE), SH_UNT_PERV_17 , SH_ACS_SCOM1 ); +REG64( PERV_EP01_QPPM_QCCR_SCOM2 , RULL(0x110F01BF), SH_UNT_PERV_17 , SH_ACS_SCOM2 ); +REG64( PERV_EP02_QPPM_QCCR_SCOM , RULL(0x120F01BD), SH_UNT_PERV_18 , SH_ACS_SCOM ); +REG64( PERV_EP02_QPPM_QCCR_SCOM1 , RULL(0x120F01BE), SH_UNT_PERV_18 , SH_ACS_SCOM1 ); +REG64( PERV_EP02_QPPM_QCCR_SCOM2 , RULL(0x120F01BF), SH_UNT_PERV_18 , SH_ACS_SCOM2 ); +REG64( PERV_EP03_QPPM_QCCR_SCOM , RULL(0x130F01BD), SH_UNT_PERV_19 , SH_ACS_SCOM ); +REG64( PERV_EP03_QPPM_QCCR_SCOM1 , RULL(0x130F01BE), SH_UNT_PERV_19 , SH_ACS_SCOM1 ); +REG64( PERV_EP03_QPPM_QCCR_SCOM2 , RULL(0x130F01BF), SH_UNT_PERV_19 , SH_ACS_SCOM2 ); +REG64( PERV_EP04_QPPM_QCCR_SCOM , RULL(0x140F01BD), SH_UNT_PERV_20 , SH_ACS_SCOM ); +REG64( PERV_EP04_QPPM_QCCR_SCOM1 , RULL(0x140F01BE), SH_UNT_PERV_20 , SH_ACS_SCOM1 ); +REG64( PERV_EP04_QPPM_QCCR_SCOM2 , RULL(0x140F01BF), SH_UNT_PERV_20 , SH_ACS_SCOM2 ); +REG64( PERV_EP05_QPPM_QCCR_SCOM , RULL(0x150F01BD), SH_UNT_PERV_21 , SH_ACS_SCOM ); +REG64( PERV_EP05_QPPM_QCCR_SCOM1 , RULL(0x150F01BE), SH_UNT_PERV_21 , SH_ACS_SCOM1 ); +REG64( PERV_EP05_QPPM_QCCR_SCOM2 , RULL(0x150F01BF), SH_UNT_PERV_21 , SH_ACS_SCOM2 ); + +REG64( PERV_EP00_QPPM_QPMMR , RULL(0x100F0103), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); +REG64( PERV_EP00_QPPM_QPMMR_CLEAR , RULL(0x100F0104), SH_UNT_PERV_16 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP00_QPPM_QPMMR_OR , RULL(0x100F0105), SH_UNT_PERV_16 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP01_QPPM_QPMMR , RULL(0x110F0103), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); +REG64( PERV_EP01_QPPM_QPMMR_CLEAR , RULL(0x110F0104), SH_UNT_PERV_17 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP01_QPPM_QPMMR_OR , RULL(0x110F0105), SH_UNT_PERV_17 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP02_QPPM_QPMMR , RULL(0x120F0103), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); +REG64( PERV_EP02_QPPM_QPMMR_CLEAR , RULL(0x120F0104), SH_UNT_PERV_18 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP02_QPPM_QPMMR_OR , RULL(0x120F0105), SH_UNT_PERV_18 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP03_QPPM_QPMMR , RULL(0x130F0103), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); +REG64( PERV_EP03_QPPM_QPMMR_CLEAR , RULL(0x130F0104), SH_UNT_PERV_19 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP03_QPPM_QPMMR_OR , RULL(0x130F0105), SH_UNT_PERV_19 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP04_QPPM_QPMMR , RULL(0x140F0103), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); +REG64( PERV_EP04_QPPM_QPMMR_CLEAR , RULL(0x140F0104), SH_UNT_PERV_20 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP04_QPPM_QPMMR_OR , RULL(0x140F0105), SH_UNT_PERV_20 , SH_ACS_SCOM2_OR ); +REG64( PERV_EP05_QPPM_QPMMR , RULL(0x150F0103), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); +REG64( PERV_EP05_QPPM_QPMMR_CLEAR , RULL(0x150F0104), SH_UNT_PERV_21 , + SH_ACS_SCOM1_CLEAR ); +REG64( PERV_EP05_QPPM_QPMMR_OR , RULL(0x150F0105), SH_UNT_PERV_21 , SH_ACS_SCOM2_OR ); + +REG64( PERV_EP00_QPPM_VDMCFGR , RULL(0x100F01B6), SH_UNT_PERV_16 , SH_ACS_SCOM_RW ); +REG64( PERV_EP01_QPPM_VDMCFGR , RULL(0x110F01B6), SH_UNT_PERV_17 , SH_ACS_SCOM_RW ); +REG64( PERV_EP02_QPPM_VDMCFGR , RULL(0x120F01B6), SH_UNT_PERV_18 , SH_ACS_SCOM_RW ); +REG64( PERV_EP03_QPPM_VDMCFGR , RULL(0x130F01B6), SH_UNT_PERV_19 , SH_ACS_SCOM_RW ); +REG64( PERV_EP04_QPPM_VDMCFGR , RULL(0x140F01B6), SH_UNT_PERV_20 , SH_ACS_SCOM_RW ); +REG64( PERV_EP05_QPPM_VDMCFGR , RULL(0x150F01B6), SH_UNT_PERV_21 , SH_ACS_SCOM_RW ); + +REG64( PERV_EP00_QPPM_VOLT_CHAR , RULL(0x100F01BB), SH_UNT_PERV_16 , SH_ACS_SCOM_RO ); +REG64( PERV_EP01_QPPM_VOLT_CHAR , RULL(0x110F01BB), SH_UNT_PERV_17 , SH_ACS_SCOM_RO ); +REG64( PERV_EP02_QPPM_VOLT_CHAR , RULL(0x120F01BB), SH_UNT_PERV_18 , SH_ACS_SCOM_RO ); +REG64( PERV_EP03_QPPM_VOLT_CHAR , RULL(0x130F01BB), SH_UNT_PERV_19 , SH_ACS_SCOM_RO ); +REG64( PERV_EP04_QPPM_VOLT_CHAR , RULL(0x140F01BB), SH_UNT_PERV_20 , SH_ACS_SCOM_RO ); +REG64( PERV_EP05_QPPM_VOLT_CHAR , RULL(0x150F01BB), SH_UNT_PERV_21 , SH_ACS_SCOM_RO ); REG64( PERV_N3_RCV_ERRLOG0_REG , RULL(0x05002822), SH_UNT_PERV_5 , SH_ACS_SCOM_WAND ); @@ -8256,104 +8715,239 @@ REG32( PERV_FSISHIFT_RESET_ERRORS_FSI_BYTE , RULL(0x00000C1C REG64( PERV_RESET_REG , RULL(0x000F001D), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_RESET_REG , RULL(0x000F001D), SH_UNT_PERV_0 , SH_ACS_SCOM ); -REG64( PERV_0_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH , RULL(0x00001809), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH_A , RULL(0x00001809), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM ); //WARNING - VALUE SET SAME AS ANOTHER REG -REG32( PERV_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH , RULL(0x00001809), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH_A , RULL(0x00001809), SH_UNT_PERV_FSII2C, SH_ACS_SCOM ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( PERV_RFIR , RULL(0x00040001), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_TP_RFIR , RULL(0x01040001), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_N0_RFIR , RULL(0x02040001), SH_UNT_PERV_2 , SH_ACS_SCOM ); +REG64( PERV_N1_RFIR , RULL(0x03040001), SH_UNT_PERV_3 , SH_ACS_SCOM ); +REG64( PERV_N2_RFIR , RULL(0x04040001), SH_UNT_PERV_4 , SH_ACS_SCOM ); +REG64( PERV_N3_RFIR , RULL(0x05040001), SH_UNT_PERV_5 , SH_ACS_SCOM ); +REG64( PERV_XB_RFIR , RULL(0x06040001), SH_UNT_PERV_6 , SH_ACS_SCOM ); +REG64( PERV_MC01_RFIR , RULL(0x07040001), SH_UNT_PERV_7 , SH_ACS_SCOM ); +REG64( PERV_MC23_RFIR , RULL(0x08040001), SH_UNT_PERV_8 , SH_ACS_SCOM ); +REG64( PERV_OB0_RFIR , RULL(0x09040001), SH_UNT_PERV_9 , SH_ACS_SCOM ); +REG64( PERV_OB3_RFIR , RULL(0x0C040001), SH_UNT_PERV_12 , SH_ACS_SCOM ); +REG64( PERV_PCI0_RFIR , RULL(0x0D040001), SH_UNT_PERV_13 , SH_ACS_SCOM ); +REG64( PERV_PCI1_RFIR , RULL(0x0E040001), SH_UNT_PERV_14 , SH_ACS_SCOM ); +REG64( PERV_PCI2_RFIR , RULL(0x0F040001), SH_UNT_PERV_15 , SH_ACS_SCOM ); +REG64( PERV_EP00_RFIR , RULL(0x10040001), SH_UNT_PERV_16 , SH_ACS_SCOM ); +REG64( PERV_EP01_RFIR , RULL(0x11040001), SH_UNT_PERV_17 , SH_ACS_SCOM ); +REG64( PERV_EP02_RFIR , RULL(0x12040001), SH_UNT_PERV_18 , SH_ACS_SCOM ); +REG64( PERV_EP03_RFIR , RULL(0x13040001), SH_UNT_PERV_19 , SH_ACS_SCOM ); +REG64( PERV_EP04_RFIR , RULL(0x14040001), SH_UNT_PERV_20 , SH_ACS_SCOM ); +REG64( PERV_EP05_RFIR , RULL(0x15040001), SH_UNT_PERV_21 , SH_ACS_SCOM ); +REG64( PERV_EC00_RFIR , RULL(0x20040001), SH_UNT_PERV_32 , SH_ACS_SCOM ); +REG64( PERV_EC01_RFIR , RULL(0x21040001), SH_UNT_PERV_33 , SH_ACS_SCOM ); +REG64( PERV_EC02_RFIR , RULL(0x22040001), SH_UNT_PERV_34 , SH_ACS_SCOM ); +REG64( PERV_EC03_RFIR , RULL(0x23040001), SH_UNT_PERV_35 , SH_ACS_SCOM ); +REG64( PERV_EC04_RFIR , RULL(0x24040001), SH_UNT_PERV_36 , SH_ACS_SCOM ); +REG64( PERV_EC05_RFIR , RULL(0x25040001), SH_UNT_PERV_37 , SH_ACS_SCOM ); +REG64( PERV_EC06_RFIR , RULL(0x26040001), SH_UNT_PERV_38 , SH_ACS_SCOM ); +REG64( PERV_EC07_RFIR , RULL(0x27040001), SH_UNT_PERV_39 , SH_ACS_SCOM ); +REG64( PERV_EC08_RFIR , RULL(0x28040001), SH_UNT_PERV_40 , SH_ACS_SCOM ); +REG64( PERV_EC09_RFIR , RULL(0x29040001), SH_UNT_PERV_41 , SH_ACS_SCOM ); +REG64( PERV_EC10_RFIR , RULL(0x2A040001), SH_UNT_PERV_42 , SH_ACS_SCOM ); +REG64( PERV_EC11_RFIR , RULL(0x2B040001), SH_UNT_PERV_43 , SH_ACS_SCOM ); +REG64( PERV_EC12_RFIR , RULL(0x2C040001), SH_UNT_PERV_44 , SH_ACS_SCOM ); +REG64( PERV_EC13_RFIR , RULL(0x2D040001), SH_UNT_PERV_45 , SH_ACS_SCOM ); +REG64( PERV_EC14_RFIR , RULL(0x2E040001), SH_UNT_PERV_46 , SH_ACS_SCOM ); +REG64( PERV_EC15_RFIR , RULL(0x2F040001), SH_UNT_PERV_47 , SH_ACS_SCOM ); +REG64( PERV_EC16_RFIR , RULL(0x30040001), SH_UNT_PERV_48 , SH_ACS_SCOM ); +REG64( PERV_EC17_RFIR , RULL(0x31040001), SH_UNT_PERV_49 , SH_ACS_SCOM ); +REG64( PERV_EC18_RFIR , RULL(0x32040001), SH_UNT_PERV_50 , SH_ACS_SCOM ); +REG64( PERV_EC19_RFIR , RULL(0x33040001), SH_UNT_PERV_51 , SH_ACS_SCOM ); +REG64( PERV_EC20_RFIR , RULL(0x34040001), SH_UNT_PERV_52 , SH_ACS_SCOM ); +REG64( PERV_EC21_RFIR , RULL(0x35040001), SH_UNT_PERV_53 , SH_ACS_SCOM ); +REG64( PERV_EC22_RFIR , RULL(0x36040001), SH_UNT_PERV_54 , SH_ACS_SCOM ); +REG64( PERV_EC23_RFIR , RULL(0x37040001), SH_UNT_PERV_55 , SH_ACS_SCOM ); + +REG64( PERV_RING_FENCE_MASK_LATCH_REG , RULL(0x00010008), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_RING_FENCE_MASK_LATCH_REG , RULL(0x01010008), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG32( PERV_ROOT_CTRL0_FSI , RULL(0x00002810), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL0_FSI_BYTE , RULL(0x00002840), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL0_SCOM , RULL(0x00050010), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL0 , RULL(0x00050010), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL0_CLEAR_FSI , RULL(0x00002930), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL0_CLEAR_FSI_BYTE , RULL(0x00002CC0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL0_CLEAR_SCOM , RULL(0x00050130), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL0_CLEAR , RULL(0x00050130), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL0_COPY_FSI , RULL(0x00002910), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL0_COPY_FSI_BYTE , RULL(0x00002C40), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL0_COPY_SCOM , RULL(0x00050110), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL0_COPY , RULL(0x00050110), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL0_SET_FSI , RULL(0x00002920), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL0_SET_FSI_BYTE , RULL(0x00002C80), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL0_SET_SCOM , RULL(0x00050120), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL0_SET , RULL(0x00050120), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL1_FSI , RULL(0x00002811), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL1_FSI_BYTE , RULL(0x00002844), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL1_SCOM , RULL(0x00050011), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL1 , RULL(0x00050011), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL1_CLEAR_FSI , RULL(0x00002931), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL1_CLEAR_FSI_BYTE , RULL(0x00002CC4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL1_CLEAR_SCOM , RULL(0x00050131), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL1_CLEAR , RULL(0x00050131), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL1_COPY_FSI , RULL(0x00002911), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL1_COPY_FSI_BYTE , RULL(0x00002C44), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL1_COPY_SCOM , RULL(0x00050111), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL1_COPY , RULL(0x00050111), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL1_SET_FSI , RULL(0x00002921), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL1_SET_FSI_BYTE , RULL(0x00002C84), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL1_SET_SCOM , RULL(0x00050121), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL1_SET , RULL(0x00050121), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL2_FSI , RULL(0x00002812), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL2_FSI_BYTE , RULL(0x00002848), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL2_SCOM , RULL(0x00050012), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL2 , RULL(0x00050012), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL2_CLEAR_FSI , RULL(0x00002932), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL2_CLEAR_FSI_BYTE , RULL(0x00002CC8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL2_CLEAR_SCOM , RULL(0x00050132), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL2_CLEAR , RULL(0x00050132), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL2_COPY_FSI , RULL(0x00002912), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL2_COPY_FSI_BYTE , RULL(0x00002C48), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL2_COPY_SCOM , RULL(0x00050112), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL2_COPY , RULL(0x00050112), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL2_SET_FSI , RULL(0x00002922), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL2_SET_FSI_BYTE , RULL(0x00002C88), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL2_SET_SCOM , RULL(0x00050122), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL2_SET , RULL(0x00050122), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL3_FSI , RULL(0x00002813), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL3_FSI_BYTE , RULL(0x0000284C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL3_SCOM , RULL(0x00050013), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL3 , RULL(0x00050013), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL3_CLEAR_FSI , RULL(0x00002933), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL3_CLEAR_FSI_BYTE , RULL(0x00002CCC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL3_CLEAR_SCOM , RULL(0x00050133), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL3_CLEAR , RULL(0x00050133), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL3_COPY_FSI , RULL(0x00002913), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL3_COPY_FSI_BYTE , RULL(0x00002C4C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL3_COPY_SCOM , RULL(0x00050113), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL3_COPY , RULL(0x00050113), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL3_SET_FSI , RULL(0x00002923), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL3_SET_FSI_BYTE , RULL(0x00002C8C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL3_SET_SCOM , RULL(0x00050123), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL3_SET , RULL(0x00050123), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL4_FSI , RULL(0x00002814), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL4_FSI_BYTE , RULL(0x00002850), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL4_SCOM , RULL(0x00050014), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL4 , RULL(0x00050014), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL4_CLEAR_FSI , RULL(0x00002934), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL4_CLEAR_FSI_BYTE , RULL(0x00002CD0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL4_CLEAR_SCOM , RULL(0x00050134), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL4_CLEAR , RULL(0x00050134), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL4_COPY_FSI , RULL(0x00002914), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL4_COPY_FSI_BYTE , RULL(0x00002C50), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL4_COPY_SCOM , RULL(0x00050114), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL4_COPY , RULL(0x00050114), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL4_SET_FSI , RULL(0x00002924), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL4_SET_FSI_BYTE , RULL(0x00002C90), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL4_SET_SCOM , RULL(0x00050124), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL4_SET , RULL(0x00050124), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL5_FSI , RULL(0x00002815), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL5_FSI_BYTE , RULL(0x00002854), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL5_SCOM , RULL(0x00050015), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL5 , RULL(0x00050015), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL5_CLEAR_FSI , RULL(0x00002935), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL5_CLEAR_FSI_BYTE , RULL(0x00002CD4), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL5_CLEAR_SCOM , RULL(0x00050135), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL5_CLEAR , RULL(0x00050135), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL5_COPY_FSI , RULL(0x00002915), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL5_COPY_FSI_BYTE , RULL(0x00002C54), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL5_COPY_SCOM , RULL(0x00050115), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL5_COPY , RULL(0x00050115), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL5_SET_FSI , RULL(0x00002925), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL5_SET_FSI_BYTE , RULL(0x00002C94), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL5_SET_SCOM , RULL(0x00050125), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL5_SET , RULL(0x00050125), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL6_FSI , RULL(0x00002816), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL6_FSI_BYTE , RULL(0x00002858), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL6_SCOM , RULL(0x00050016), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL6 , RULL(0x00050016), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL6_CLEAR_FSI , RULL(0x00002936), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL6_CLEAR_FSI_BYTE , RULL(0x00002CD8), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL6_CLEAR_SCOM , RULL(0x00050136), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL6_CLEAR , RULL(0x00050136), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL6_COPY_FSI , RULL(0x00002916), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL6_COPY_FSI_BYTE , RULL(0x00002C58), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL6_COPY_SCOM , RULL(0x00050116), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL6_COPY , RULL(0x00050116), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL6_SET_FSI , RULL(0x00002926), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL6_SET_FSI_BYTE , RULL(0x00002C98), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL6_SET_SCOM , RULL(0x00050126), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL6_SET , RULL(0x00050126), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL7_FSI , RULL(0x00002817), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL7_FSI_BYTE , RULL(0x0000285C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL7_SCOM , RULL(0x00050017), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL7 , RULL(0x00050017), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL7_CLEAR_FSI , RULL(0x00002937), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL7_CLEAR_FSI_BYTE , RULL(0x00002CDC), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL7_CLEAR_SCOM , RULL(0x00050137), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL7_CLEAR , RULL(0x00050137), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL7_COPY_FSI , RULL(0x00002917), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL7_COPY_FSI_BYTE , RULL(0x00002C5C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL7_COPY_SCOM , RULL(0x00050117), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL7_COPY , RULL(0x00050117), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL7_SET_FSI , RULL(0x00002927), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL7_SET_FSI_BYTE , RULL(0x00002C9C), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL7_SET_SCOM , RULL(0x00050127), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL7_SET , RULL(0x00050127), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL8_FSI , RULL(0x00002818), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL8_FSI_BYTE , RULL(0x00002860), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL8_SCOM , RULL(0x00050018), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL8 , RULL(0x00050018), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL8_CLEAR_FSI , RULL(0x00002938), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL8_CLEAR_FSI_BYTE , RULL(0x00002CE0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL8_CLEAR_SCOM , RULL(0x00050138), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL8_CLEAR , RULL(0x00050138), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG32( PERV_ROOT_CTRL8_COPY_FSI , RULL(0x00002918), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_ROOT_CTRL8_COPY_FSI_BYTE , RULL(0x00002C60), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_ROOT_CTRL8_COPY_SCOM , RULL(0x00050118), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_ROOT_CTRL8_COPY , RULL(0x00050118), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG32( PERV_ROOT_CTRL8_SET_FSI , RULL(0x00002928), SH_UNT_PERV , SH_ACS_FSI ); +REG64( PERV_ROOT_CTRL8_SET_FSI_BYTE , RULL(0x00002CA0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); +REG64( PERV_ROOT_CTRL8_SET_SCOM , RULL(0x00050128), SH_UNT_PERV , SH_ACS_SCOM ); +REG64( PERV_PIB_ROOT_CTRL8_SET , RULL(0x00050128), SH_UNT_PERV_0 , SH_ACS_SCOM ); + REG64( PERV_RSIC , RULL(0x00030008), SH_UNT_PERV , SH_ACS_SCOM_WCLEAR ); REG64( PERV_PIB_RSIC , RULL(0x00030008), SH_UNT_PERV_0 , @@ -8474,34 +9068,6 @@ REG64( PERV_EC23_SCAN_REGION_TYPE , RULL(0x37030005 REG32( PERV_SCPSIZE_FSI , RULL(0x00001400), SH_UNT_PERV , SH_ACS_FSI ); -REG32( PERV_FSI2PIB_SCRATCH0_PPE , RULL(0x00001000), SH_UNT_PERV_FSI2PIB, - SH_ACS_PPE ); -REG32( PERV_FSI2PIB_SCRATCH0_PPE1 , RULL(0x00001010), SH_UNT_PERV_FSI2PIB, - SH_ACS_PPE1 ); -REG32( PERV_FSI2PIB_SCRATCH0_PPE2 , RULL(0x00001018), SH_UNT_PERV_FSI2PIB, - SH_ACS_PPE2 ); - -REG32( PERV_FSI2PIB_SCRATCH1_PPE , RULL(0x00001020), SH_UNT_PERV_FSI2PIB, - SH_ACS_PPE ); -REG32( PERV_FSI2PIB_SCRATCH1_PPE1 , RULL(0x00001030), SH_UNT_PERV_FSI2PIB, - SH_ACS_PPE1 ); -REG32( PERV_FSI2PIB_SCRATCH1_PPE2 , RULL(0x00001038), SH_UNT_PERV_FSI2PIB, - SH_ACS_PPE2 ); - -REG32( PERV_FSI2PIB_SCRATCH2_PPE , RULL(0x00001040), SH_UNT_PERV_FSI2PIB, - SH_ACS_PPE ); -REG32( PERV_FSI2PIB_SCRATCH2_PPE1 , RULL(0x00001050), SH_UNT_PERV_FSI2PIB, - SH_ACS_PPE1 ); -REG32( PERV_FSI2PIB_SCRATCH2_PPE2 , RULL(0x00001058), SH_UNT_PERV_FSI2PIB, - SH_ACS_PPE2 ); - -REG32( PERV_FSI2PIB_SCRATCH3_PPE , RULL(0x00001060), SH_UNT_PERV_FSI2PIB, - SH_ACS_PPE ); -REG32( PERV_FSI2PIB_SCRATCH3_PPE1 , RULL(0x00001070), SH_UNT_PERV_FSI2PIB, - SH_ACS_PPE1 ); -REG32( PERV_FSI2PIB_SCRATCH3_PPE2 , RULL(0x00001078), SH_UNT_PERV_FSI2PIB, - SH_ACS_PPE2 ); - REG32( PERV_SCRATCH_REGISTER_1_FSI , RULL(0x00002838), SH_UNT_PERV , SH_ACS_FSI ); REG64( PERV_SCRATCH_REGISTER_1_FSI_BYTE , RULL(0x000028E0), SH_UNT_PERV , SH_ACS_FSI_BYTE ); REG64( PERV_SCRATCH_REGISTER_1_SCOM , RULL(0x00050038), SH_UNT_PERV , SH_ACS_SCOM ); @@ -8542,6 +9108,9 @@ REG64( PERV_SCRATCH_REGISTER_8_FSI_BYTE , RULL(0x000028FC REG64( PERV_SCRATCH_REGISTER_8_SCOM , RULL(0x0005003F), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_SCRATCH_REGISTER_8 , RULL(0x0005003F), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG64( PERV_SECURE_PIB_MASTER_ID_REG , RULL(0x00010009), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_SECURE_PIB_MASTER_ID_REG , RULL(0x01010009), SH_UNT_PERV_1 , SH_ACS_SCOM ); + REG32( PERV_FSI2PIB_SET_PIB_RESET_FSI , RULL(0x00001007), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI ); REG32( PERV_FSI2PIB_SET_PIB_RESET_FSI_BYTE , RULL(0x0000101C), SH_UNT_PERV_FSI2PIB, @@ -8887,9 +9456,177 @@ REG64( PERV_SPATTN_SCOM1 , RULL(0x00040005 REG64( PERV_TP_SPATTN_SCOM1 , RULL(0x01040005), SH_UNT_PERV_1 , SH_ACS_SCOM1_NC ); REG64( PERV_SPATTN_SCOM2 , RULL(0x00040006), SH_UNT_PERV_1 , SH_ACS_SCOM2_NC ); REG64( PERV_TP_SPATTN_SCOM2 , RULL(0x01040006), SH_UNT_PERV_1 , SH_ACS_SCOM2_NC ); +REG64( PERV_N0_SPATTN_SCOM , RULL(0x02040004), SH_UNT_PERV_2 , SH_ACS_SCOM_RO ); +REG64( PERV_N0_SPATTN_SCOM1 , RULL(0x02040005), SH_UNT_PERV_2 , SH_ACS_SCOM1_NC ); +REG64( PERV_N0_SPATTN_SCOM2 , RULL(0x02040006), SH_UNT_PERV_2 , SH_ACS_SCOM2_NC ); +REG64( PERV_N1_SPATTN_SCOM , RULL(0x03040004), SH_UNT_PERV_3 , SH_ACS_SCOM_RO ); +REG64( PERV_N1_SPATTN_SCOM1 , RULL(0x03040005), SH_UNT_PERV_3 , SH_ACS_SCOM1_NC ); +REG64( PERV_N1_SPATTN_SCOM2 , RULL(0x03040006), SH_UNT_PERV_3 , SH_ACS_SCOM2_NC ); +REG64( PERV_N2_SPATTN_SCOM , RULL(0x04040004), SH_UNT_PERV_4 , SH_ACS_SCOM_RO ); +REG64( PERV_N2_SPATTN_SCOM1 , RULL(0x04040005), SH_UNT_PERV_4 , SH_ACS_SCOM1_NC ); +REG64( PERV_N2_SPATTN_SCOM2 , RULL(0x04040006), SH_UNT_PERV_4 , SH_ACS_SCOM2_NC ); +REG64( PERV_N3_SPATTN_SCOM , RULL(0x05040004), SH_UNT_PERV_5 , SH_ACS_SCOM_RO ); +REG64( PERV_N3_SPATTN_SCOM1 , RULL(0x05040005), SH_UNT_PERV_5 , SH_ACS_SCOM1_NC ); +REG64( PERV_N3_SPATTN_SCOM2 , RULL(0x05040006), SH_UNT_PERV_5 , SH_ACS_SCOM2_NC ); +REG64( PERV_XB_SPATTN_SCOM , RULL(0x06040004), SH_UNT_PERV_6 , SH_ACS_SCOM_RO ); +REG64( PERV_XB_SPATTN_SCOM1 , RULL(0x06040005), SH_UNT_PERV_6 , SH_ACS_SCOM1_NC ); +REG64( PERV_XB_SPATTN_SCOM2 , RULL(0x06040006), SH_UNT_PERV_6 , SH_ACS_SCOM2_NC ); +REG64( PERV_MC01_SPATTN_SCOM , RULL(0x07040004), SH_UNT_PERV_7 , SH_ACS_SCOM_RO ); +REG64( PERV_MC01_SPATTN_SCOM1 , RULL(0x07040005), SH_UNT_PERV_7 , SH_ACS_SCOM1_NC ); +REG64( PERV_MC01_SPATTN_SCOM2 , RULL(0x07040006), SH_UNT_PERV_7 , SH_ACS_SCOM2_NC ); +REG64( PERV_MC23_SPATTN_SCOM , RULL(0x08040004), SH_UNT_PERV_8 , SH_ACS_SCOM_RO ); +REG64( PERV_MC23_SPATTN_SCOM1 , RULL(0x08040005), SH_UNT_PERV_8 , SH_ACS_SCOM1_NC ); +REG64( PERV_MC23_SPATTN_SCOM2 , RULL(0x08040006), SH_UNT_PERV_8 , SH_ACS_SCOM2_NC ); +REG64( PERV_OB0_SPATTN_SCOM , RULL(0x09040004), SH_UNT_PERV_9 , SH_ACS_SCOM_RO ); +REG64( PERV_OB0_SPATTN_SCOM1 , RULL(0x09040005), SH_UNT_PERV_9 , SH_ACS_SCOM1_NC ); +REG64( PERV_OB0_SPATTN_SCOM2 , RULL(0x09040006), SH_UNT_PERV_9 , SH_ACS_SCOM2_NC ); +REG64( PERV_OB3_SPATTN_SCOM , RULL(0x0C040004), SH_UNT_PERV_12 , SH_ACS_SCOM_RO ); +REG64( PERV_OB3_SPATTN_SCOM1 , RULL(0x0C040005), SH_UNT_PERV_12 , SH_ACS_SCOM1_NC ); +REG64( PERV_OB3_SPATTN_SCOM2 , RULL(0x0C040006), SH_UNT_PERV_12 , SH_ACS_SCOM2_NC ); +REG64( PERV_PCI0_SPATTN_SCOM , RULL(0x0D040004), SH_UNT_PERV_13 , SH_ACS_SCOM_RO ); +REG64( PERV_PCI0_SPATTN_SCOM1 , RULL(0x0D040005), SH_UNT_PERV_13 , SH_ACS_SCOM1_NC ); +REG64( PERV_PCI0_SPATTN_SCOM2 , RULL(0x0D040006), SH_UNT_PERV_13 , SH_ACS_SCOM2_NC ); +REG64( PERV_PCI1_SPATTN_SCOM , RULL(0x0E040004), SH_UNT_PERV_14 , SH_ACS_SCOM_RO ); +REG64( PERV_PCI1_SPATTN_SCOM1 , RULL(0x0E040005), SH_UNT_PERV_14 , SH_ACS_SCOM1_NC ); +REG64( PERV_PCI1_SPATTN_SCOM2 , RULL(0x0E040006), SH_UNT_PERV_14 , SH_ACS_SCOM2_NC ); +REG64( PERV_PCI2_SPATTN_SCOM , RULL(0x0F040004), SH_UNT_PERV_15 , SH_ACS_SCOM_RO ); +REG64( PERV_PCI2_SPATTN_SCOM1 , RULL(0x0F040005), SH_UNT_PERV_15 , SH_ACS_SCOM1_NC ); +REG64( PERV_PCI2_SPATTN_SCOM2 , RULL(0x0F040006), SH_UNT_PERV_15 , SH_ACS_SCOM2_NC ); +REG64( PERV_EP00_SPATTN_SCOM , RULL(0x10040004), SH_UNT_PERV_16 , SH_ACS_SCOM_RO ); +REG64( PERV_EP00_SPATTN_SCOM1 , RULL(0x10040005), SH_UNT_PERV_16 , SH_ACS_SCOM1_NC ); +REG64( PERV_EP00_SPATTN_SCOM2 , RULL(0x10040006), SH_UNT_PERV_16 , SH_ACS_SCOM2_NC ); +REG64( PERV_EP01_SPATTN_SCOM , RULL(0x11040004), SH_UNT_PERV_17 , SH_ACS_SCOM_RO ); +REG64( PERV_EP01_SPATTN_SCOM1 , RULL(0x11040005), SH_UNT_PERV_17 , SH_ACS_SCOM1_NC ); +REG64( PERV_EP01_SPATTN_SCOM2 , RULL(0x11040006), SH_UNT_PERV_17 , SH_ACS_SCOM2_NC ); +REG64( PERV_EP02_SPATTN_SCOM , RULL(0x12040004), SH_UNT_PERV_18 , SH_ACS_SCOM_RO ); +REG64( PERV_EP02_SPATTN_SCOM1 , RULL(0x12040005), SH_UNT_PERV_18 , SH_ACS_SCOM1_NC ); +REG64( PERV_EP02_SPATTN_SCOM2 , RULL(0x12040006), SH_UNT_PERV_18 , SH_ACS_SCOM2_NC ); +REG64( PERV_EP03_SPATTN_SCOM , RULL(0x13040004), SH_UNT_PERV_19 , SH_ACS_SCOM_RO ); +REG64( PERV_EP03_SPATTN_SCOM1 , RULL(0x13040005), SH_UNT_PERV_19 , SH_ACS_SCOM1_NC ); +REG64( PERV_EP03_SPATTN_SCOM2 , RULL(0x13040006), SH_UNT_PERV_19 , SH_ACS_SCOM2_NC ); +REG64( PERV_EP04_SPATTN_SCOM , RULL(0x14040004), SH_UNT_PERV_20 , SH_ACS_SCOM_RO ); +REG64( PERV_EP04_SPATTN_SCOM1 , RULL(0x14040005), SH_UNT_PERV_20 , SH_ACS_SCOM1_NC ); +REG64( PERV_EP04_SPATTN_SCOM2 , RULL(0x14040006), SH_UNT_PERV_20 , SH_ACS_SCOM2_NC ); +REG64( PERV_EP05_SPATTN_SCOM , RULL(0x15040004), SH_UNT_PERV_21 , SH_ACS_SCOM_RO ); +REG64( PERV_EP05_SPATTN_SCOM1 , RULL(0x15040005), SH_UNT_PERV_21 , SH_ACS_SCOM1_NC ); +REG64( PERV_EP05_SPATTN_SCOM2 , RULL(0x15040006), SH_UNT_PERV_21 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC00_SPATTN_SCOM , RULL(0x20040004), SH_UNT_PERV_32 , SH_ACS_SCOM_RO ); +REG64( PERV_EC00_SPATTN_SCOM1 , RULL(0x20040005), SH_UNT_PERV_32 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC00_SPATTN_SCOM2 , RULL(0x20040006), SH_UNT_PERV_32 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC01_SPATTN_SCOM , RULL(0x21040004), SH_UNT_PERV_33 , SH_ACS_SCOM_RO ); +REG64( PERV_EC01_SPATTN_SCOM1 , RULL(0x21040005), SH_UNT_PERV_33 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC01_SPATTN_SCOM2 , RULL(0x21040006), SH_UNT_PERV_33 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC02_SPATTN_SCOM , RULL(0x22040004), SH_UNT_PERV_34 , SH_ACS_SCOM_RO ); +REG64( PERV_EC02_SPATTN_SCOM1 , RULL(0x22040005), SH_UNT_PERV_34 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC02_SPATTN_SCOM2 , RULL(0x22040006), SH_UNT_PERV_34 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC03_SPATTN_SCOM , RULL(0x23040004), SH_UNT_PERV_35 , SH_ACS_SCOM_RO ); +REG64( PERV_EC03_SPATTN_SCOM1 , RULL(0x23040005), SH_UNT_PERV_35 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC03_SPATTN_SCOM2 , RULL(0x23040006), SH_UNT_PERV_35 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC04_SPATTN_SCOM , RULL(0x24040004), SH_UNT_PERV_36 , SH_ACS_SCOM_RO ); +REG64( PERV_EC04_SPATTN_SCOM1 , RULL(0x24040005), SH_UNT_PERV_36 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC04_SPATTN_SCOM2 , RULL(0x24040006), SH_UNT_PERV_36 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC05_SPATTN_SCOM , RULL(0x25040004), SH_UNT_PERV_37 , SH_ACS_SCOM_RO ); +REG64( PERV_EC05_SPATTN_SCOM1 , RULL(0x25040005), SH_UNT_PERV_37 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC05_SPATTN_SCOM2 , RULL(0x25040006), SH_UNT_PERV_37 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC06_SPATTN_SCOM , RULL(0x26040004), SH_UNT_PERV_38 , SH_ACS_SCOM_RO ); +REG64( PERV_EC06_SPATTN_SCOM1 , RULL(0x26040005), SH_UNT_PERV_38 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC06_SPATTN_SCOM2 , RULL(0x26040006), SH_UNT_PERV_38 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC07_SPATTN_SCOM , RULL(0x27040004), SH_UNT_PERV_39 , SH_ACS_SCOM_RO ); +REG64( PERV_EC07_SPATTN_SCOM1 , RULL(0x27040005), SH_UNT_PERV_39 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC07_SPATTN_SCOM2 , RULL(0x27040006), SH_UNT_PERV_39 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC08_SPATTN_SCOM , RULL(0x28040004), SH_UNT_PERV_40 , SH_ACS_SCOM_RO ); +REG64( PERV_EC08_SPATTN_SCOM1 , RULL(0x28040005), SH_UNT_PERV_40 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC08_SPATTN_SCOM2 , RULL(0x28040006), SH_UNT_PERV_40 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC09_SPATTN_SCOM , RULL(0x29040004), SH_UNT_PERV_41 , SH_ACS_SCOM_RO ); +REG64( PERV_EC09_SPATTN_SCOM1 , RULL(0x29040005), SH_UNT_PERV_41 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC09_SPATTN_SCOM2 , RULL(0x29040006), SH_UNT_PERV_41 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC10_SPATTN_SCOM , RULL(0x2A040004), SH_UNT_PERV_42 , SH_ACS_SCOM_RO ); +REG64( PERV_EC10_SPATTN_SCOM1 , RULL(0x2A040005), SH_UNT_PERV_42 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC10_SPATTN_SCOM2 , RULL(0x2A040006), SH_UNT_PERV_42 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC11_SPATTN_SCOM , RULL(0x2B040004), SH_UNT_PERV_43 , SH_ACS_SCOM_RO ); +REG64( PERV_EC11_SPATTN_SCOM1 , RULL(0x2B040005), SH_UNT_PERV_43 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC11_SPATTN_SCOM2 , RULL(0x2B040006), SH_UNT_PERV_43 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC12_SPATTN_SCOM , RULL(0x2C040004), SH_UNT_PERV_44 , SH_ACS_SCOM_RO ); +REG64( PERV_EC12_SPATTN_SCOM1 , RULL(0x2C040005), SH_UNT_PERV_44 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC12_SPATTN_SCOM2 , RULL(0x2C040006), SH_UNT_PERV_44 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC13_SPATTN_SCOM , RULL(0x2D040004), SH_UNT_PERV_45 , SH_ACS_SCOM_RO ); +REG64( PERV_EC13_SPATTN_SCOM1 , RULL(0x2D040005), SH_UNT_PERV_45 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC13_SPATTN_SCOM2 , RULL(0x2D040006), SH_UNT_PERV_45 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC14_SPATTN_SCOM , RULL(0x2E040004), SH_UNT_PERV_46 , SH_ACS_SCOM_RO ); +REG64( PERV_EC14_SPATTN_SCOM1 , RULL(0x2E040005), SH_UNT_PERV_46 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC14_SPATTN_SCOM2 , RULL(0x2E040006), SH_UNT_PERV_46 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC15_SPATTN_SCOM , RULL(0x2F040004), SH_UNT_PERV_47 , SH_ACS_SCOM_RO ); +REG64( PERV_EC15_SPATTN_SCOM1 , RULL(0x2F040005), SH_UNT_PERV_47 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC15_SPATTN_SCOM2 , RULL(0x2F040006), SH_UNT_PERV_47 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC16_SPATTN_SCOM , RULL(0x30040004), SH_UNT_PERV_48 , SH_ACS_SCOM_RO ); +REG64( PERV_EC16_SPATTN_SCOM1 , RULL(0x30040005), SH_UNT_PERV_48 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC16_SPATTN_SCOM2 , RULL(0x30040006), SH_UNT_PERV_48 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC17_SPATTN_SCOM , RULL(0x31040004), SH_UNT_PERV_49 , SH_ACS_SCOM_RO ); +REG64( PERV_EC17_SPATTN_SCOM1 , RULL(0x31040005), SH_UNT_PERV_49 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC17_SPATTN_SCOM2 , RULL(0x31040006), SH_UNT_PERV_49 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC18_SPATTN_SCOM , RULL(0x32040004), SH_UNT_PERV_50 , SH_ACS_SCOM_RO ); +REG64( PERV_EC18_SPATTN_SCOM1 , RULL(0x32040005), SH_UNT_PERV_50 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC18_SPATTN_SCOM2 , RULL(0x32040006), SH_UNT_PERV_50 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC19_SPATTN_SCOM , RULL(0x33040004), SH_UNT_PERV_51 , SH_ACS_SCOM_RO ); +REG64( PERV_EC19_SPATTN_SCOM1 , RULL(0x33040005), SH_UNT_PERV_51 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC19_SPATTN_SCOM2 , RULL(0x33040006), SH_UNT_PERV_51 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC20_SPATTN_SCOM , RULL(0x34040004), SH_UNT_PERV_52 , SH_ACS_SCOM_RO ); +REG64( PERV_EC20_SPATTN_SCOM1 , RULL(0x34040005), SH_UNT_PERV_52 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC20_SPATTN_SCOM2 , RULL(0x34040006), SH_UNT_PERV_52 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC21_SPATTN_SCOM , RULL(0x35040004), SH_UNT_PERV_53 , SH_ACS_SCOM_RO ); +REG64( PERV_EC21_SPATTN_SCOM1 , RULL(0x35040005), SH_UNT_PERV_53 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC21_SPATTN_SCOM2 , RULL(0x35040006), SH_UNT_PERV_53 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC22_SPATTN_SCOM , RULL(0x36040004), SH_UNT_PERV_54 , SH_ACS_SCOM_RO ); +REG64( PERV_EC22_SPATTN_SCOM1 , RULL(0x36040005), SH_UNT_PERV_54 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC22_SPATTN_SCOM2 , RULL(0x36040006), SH_UNT_PERV_54 , SH_ACS_SCOM2_NC ); +REG64( PERV_EC23_SPATTN_SCOM , RULL(0x37040004), SH_UNT_PERV_55 , SH_ACS_SCOM_RO ); +REG64( PERV_EC23_SPATTN_SCOM1 , RULL(0x37040005), SH_UNT_PERV_55 , SH_ACS_SCOM1_NC ); +REG64( PERV_EC23_SPATTN_SCOM2 , RULL(0x37040006), SH_UNT_PERV_55 , SH_ACS_SCOM2_NC ); REG64( PERV_SPA_MASK , RULL(0x00040007), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_TP_SPA_MASK , RULL(0x01040007), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_N0_SPA_MASK , RULL(0x02040007), SH_UNT_PERV_2 , SH_ACS_SCOM ); +REG64( PERV_N1_SPA_MASK , RULL(0x03040007), SH_UNT_PERV_3 , SH_ACS_SCOM ); +REG64( PERV_N2_SPA_MASK , RULL(0x04040007), SH_UNT_PERV_4 , SH_ACS_SCOM ); +REG64( PERV_N3_SPA_MASK , RULL(0x05040007), SH_UNT_PERV_5 , SH_ACS_SCOM ); +REG64( PERV_XB_SPA_MASK , RULL(0x06040007), SH_UNT_PERV_6 , SH_ACS_SCOM ); +REG64( PERV_MC01_SPA_MASK , RULL(0x07040007), SH_UNT_PERV_7 , SH_ACS_SCOM ); +REG64( PERV_MC23_SPA_MASK , RULL(0x08040007), SH_UNT_PERV_8 , SH_ACS_SCOM ); +REG64( PERV_OB0_SPA_MASK , RULL(0x09040007), SH_UNT_PERV_9 , SH_ACS_SCOM ); +REG64( PERV_OB3_SPA_MASK , RULL(0x0C040007), SH_UNT_PERV_12 , SH_ACS_SCOM ); +REG64( PERV_PCI0_SPA_MASK , RULL(0x0D040007), SH_UNT_PERV_13 , SH_ACS_SCOM ); +REG64( PERV_PCI1_SPA_MASK , RULL(0x0E040007), SH_UNT_PERV_14 , SH_ACS_SCOM ); +REG64( PERV_PCI2_SPA_MASK , RULL(0x0F040007), SH_UNT_PERV_15 , SH_ACS_SCOM ); +REG64( PERV_EP00_SPA_MASK , RULL(0x10040007), SH_UNT_PERV_16 , SH_ACS_SCOM ); +REG64( PERV_EP01_SPA_MASK , RULL(0x11040007), SH_UNT_PERV_17 , SH_ACS_SCOM ); +REG64( PERV_EP02_SPA_MASK , RULL(0x12040007), SH_UNT_PERV_18 , SH_ACS_SCOM ); +REG64( PERV_EP03_SPA_MASK , RULL(0x13040007), SH_UNT_PERV_19 , SH_ACS_SCOM ); +REG64( PERV_EP04_SPA_MASK , RULL(0x14040007), SH_UNT_PERV_20 , SH_ACS_SCOM ); +REG64( PERV_EP05_SPA_MASK , RULL(0x15040007), SH_UNT_PERV_21 , SH_ACS_SCOM ); +REG64( PERV_EC00_SPA_MASK , RULL(0x20040007), SH_UNT_PERV_32 , SH_ACS_SCOM ); +REG64( PERV_EC01_SPA_MASK , RULL(0x21040007), SH_UNT_PERV_33 , SH_ACS_SCOM ); +REG64( PERV_EC02_SPA_MASK , RULL(0x22040007), SH_UNT_PERV_34 , SH_ACS_SCOM ); +REG64( PERV_EC03_SPA_MASK , RULL(0x23040007), SH_UNT_PERV_35 , SH_ACS_SCOM ); +REG64( PERV_EC04_SPA_MASK , RULL(0x24040007), SH_UNT_PERV_36 , SH_ACS_SCOM ); +REG64( PERV_EC05_SPA_MASK , RULL(0x25040007), SH_UNT_PERV_37 , SH_ACS_SCOM ); +REG64( PERV_EC06_SPA_MASK , RULL(0x26040007), SH_UNT_PERV_38 , SH_ACS_SCOM ); +REG64( PERV_EC07_SPA_MASK , RULL(0x27040007), SH_UNT_PERV_39 , SH_ACS_SCOM ); +REG64( PERV_EC08_SPA_MASK , RULL(0x28040007), SH_UNT_PERV_40 , SH_ACS_SCOM ); +REG64( PERV_EC09_SPA_MASK , RULL(0x29040007), SH_UNT_PERV_41 , SH_ACS_SCOM ); +REG64( PERV_EC10_SPA_MASK , RULL(0x2A040007), SH_UNT_PERV_42 , SH_ACS_SCOM ); +REG64( PERV_EC11_SPA_MASK , RULL(0x2B040007), SH_UNT_PERV_43 , SH_ACS_SCOM ); +REG64( PERV_EC12_SPA_MASK , RULL(0x2C040007), SH_UNT_PERV_44 , SH_ACS_SCOM ); +REG64( PERV_EC13_SPA_MASK , RULL(0x2D040007), SH_UNT_PERV_45 , SH_ACS_SCOM ); +REG64( PERV_EC14_SPA_MASK , RULL(0x2E040007), SH_UNT_PERV_46 , SH_ACS_SCOM ); +REG64( PERV_EC15_SPA_MASK , RULL(0x2F040007), SH_UNT_PERV_47 , SH_ACS_SCOM ); +REG64( PERV_EC16_SPA_MASK , RULL(0x30040007), SH_UNT_PERV_48 , SH_ACS_SCOM ); +REG64( PERV_EC17_SPA_MASK , RULL(0x31040007), SH_UNT_PERV_49 , SH_ACS_SCOM ); +REG64( PERV_EC18_SPA_MASK , RULL(0x32040007), SH_UNT_PERV_50 , SH_ACS_SCOM ); +REG64( PERV_EC19_SPA_MASK , RULL(0x33040007), SH_UNT_PERV_51 , SH_ACS_SCOM ); +REG64( PERV_EC20_SPA_MASK , RULL(0x34040007), SH_UNT_PERV_52 , SH_ACS_SCOM ); +REG64( PERV_EC21_SPA_MASK , RULL(0x35040007), SH_UNT_PERV_53 , SH_ACS_SCOM ); +REG64( PERV_EC22_SPA_MASK , RULL(0x36040007), SH_UNT_PERV_54 , SH_ACS_SCOM ); +REG64( PERV_EC23_SPA_MASK , RULL(0x37040007), SH_UNT_PERV_55 , SH_ACS_SCOM ); REG32( PERV_FSI2PIB_STATUS_FSI , RULL(0x00001007), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI ); //WARNING - VALUE SET SAME AS ANOTHER REG @@ -8900,9 +9637,9 @@ REG32( PERV_FSISHIFT_STATUS_FSI , RULL(0x00000C07 REG32( PERV_FSISHIFT_STATUS_FSI_BYTE , RULL(0x00000C1C), SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE ); //WARNING - VALUE SET SAME AS ANOTHER REG -REG64( PERV_0_FSII2C_STATUS_REGISTER , RULL(0x00001807), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_STATUS_REGISTER_ENGINE_A , RULL(0x00001807), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM ); //WARNING - VALUE SET SAME AS ANOTHER REG -REG32( PERV_FSII2C_STATUS_REGISTER , RULL(0x00001807), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_STATUS_REGISTER_ENGINE_A , RULL(0x00001807), SH_UNT_PERV_FSII2C, SH_ACS_SCOM ); //WARNING - VALUE SET SAME AS ANOTHER REG REG64( PERV_STAT_RDDAT_ERRES , RULL(0x00030001), SH_UNT_PERV , SH_ACS_SCOM_RO ); @@ -9265,6 +10002,66 @@ REG64( PERV_PIB_TOD_TX_TTYPE_CTRL_REG , RULL(0x00040027 REG64( PERV_TOD_VALUE_REG , RULL(0x00040020), SH_UNT_PERV , SH_ACS_SCOM ); REG64( PERV_PIB_TOD_VALUE_REG , RULL(0x00040020), SH_UNT_PERV_0 , SH_ACS_SCOM ); +REG64( PERV_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG , RULL(0x00010400), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); +REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG , RULL(0x01010400), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); + +REG64( PERV_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG , RULL(0x00010401), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); +REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG , RULL(0x01010401), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); + +REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG , RULL(0x00010402), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG , RULL(0x01010402), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x00010403), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_0 , RULL(0x01010403), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x00010404), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_1 , RULL(0x01010404), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x00010405), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2 , RULL(0x01010405), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x00010406), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3 , RULL(0x01010406), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x00010407), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4 , RULL(0x01010407), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x00010408), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5 , RULL(0x01010408), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x00010409), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9 , RULL(0x01010409), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG , RULL(0x00010440), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); +REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG , RULL(0x01010440), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); + +REG64( PERV_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG , RULL(0x00010441), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); +REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG , RULL(0x01010441), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); + +REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG , RULL(0x00010442), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG , RULL(0x01010442), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x00010443), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_0 , RULL(0x01010443), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x00010444), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_1 , RULL(0x01010444), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x00010445), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2 , RULL(0x01010445), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x00010446), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3 , RULL(0x01010446), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x00010447), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4 , RULL(0x01010447), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x00010448), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5 , RULL(0x01010448), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x00010449), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9 , RULL(0x01010449), SH_UNT_PERV_1 , SH_ACS_SCOM ); + REG32( PERV_FSI2PIB_TRUE_MASK_FSI , RULL(0x0000100D), SH_UNT_PERV_FSI2PIB, SH_ACS_FSI ); REG32( PERV_FSI2PIB_TRUE_MASK_FSI_BYTE , RULL(0x00001034), SH_UNT_PERV_FSI2PIB, @@ -9322,13 +10119,66 @@ REG64( PERV_EC23_VITAL_SCAN_OUT , RULL(0x370F0017 REG64( PERV_VMEAS_RESULT_REG , RULL(0x00020006), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); REG64( PERV_TP_VMEAS_RESULT_REG , RULL(0x01020006), SH_UNT_PERV_1 , SH_ACS_SCOM_RO ); -REG64( PERV_0_FSII2C_WATER_MARK_REGISTER , RULL(0x00001803), SH_UNT_PERV_0_FSII2C, +REG64( PERV_0_FSII2C_WATER_MARK_REGISTER_A , RULL(0x00001803), SH_UNT_PERV_0_FSII2C, SH_ACS_SCOM ); -REG32( PERV_FSII2C_WATER_MARK_REGISTER , RULL(0x00001803), SH_UNT_PERV_FSII2C, +REG32( PERV_FSII2C_WATER_MARK_REGISTER_A , RULL(0x00001803), SH_UNT_PERV_FSII2C, SH_ACS_SCOM ); +REG64( PERV_WOF_REG , RULL(0x00000910), SH_UNT_PERV , + SH_ACS_SCOM_WCLRREG ); //DUPS: 00000910, 00000950, 00000910, 00000950, 00000990, +REG64( PERV_PIB_WOF_REG , RULL(0x00000910), SH_UNT_PERV_0 , + SH_ACS_SCOM_WCLRREG ); //DUPS: 00000910, 00000950, 00000910, 00000950, 00000990, + +REG64( PERV_WRITE_PROTECT_ENABLE_REG , RULL(0x00010005), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_WRITE_PROTECT_ENABLE_REG , RULL(0x01010005), SH_UNT_PERV_1 , SH_ACS_SCOM ); + +REG64( PERV_WRITE_PROTECT_RINGS_REG , RULL(0x00010006), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_TP_WRITE_PROTECT_RINGS_REG , RULL(0x01010006), SH_UNT_PERV_1 , SH_ACS_SCOM ); + REG64( PERV_XFIR , RULL(0x00040000), SH_UNT_PERV_1 , SH_ACS_SCOM ); REG64( PERV_TP_XFIR , RULL(0x01040000), SH_UNT_PERV_1 , SH_ACS_SCOM ); +REG64( PERV_N0_XFIR , RULL(0x02040000), SH_UNT_PERV_2 , SH_ACS_SCOM ); +REG64( PERV_N1_XFIR , RULL(0x03040000), SH_UNT_PERV_3 , SH_ACS_SCOM ); +REG64( PERV_N2_XFIR , RULL(0x04040000), SH_UNT_PERV_4 , SH_ACS_SCOM ); +REG64( PERV_N3_XFIR , RULL(0x05040000), SH_UNT_PERV_5 , SH_ACS_SCOM ); +REG64( PERV_XB_XFIR , RULL(0x06040000), SH_UNT_PERV_6 , SH_ACS_SCOM ); +REG64( PERV_MC01_XFIR , RULL(0x07040000), SH_UNT_PERV_7 , SH_ACS_SCOM ); +REG64( PERV_MC23_XFIR , RULL(0x08040000), SH_UNT_PERV_8 , SH_ACS_SCOM ); +REG64( PERV_OB0_XFIR , RULL(0x09040000), SH_UNT_PERV_9 , SH_ACS_SCOM ); +REG64( PERV_OB3_XFIR , RULL(0x0C040000), SH_UNT_PERV_12 , SH_ACS_SCOM ); +REG64( PERV_PCI0_XFIR , RULL(0x0D040000), SH_UNT_PERV_13 , SH_ACS_SCOM ); +REG64( PERV_PCI1_XFIR , RULL(0x0E040000), SH_UNT_PERV_14 , SH_ACS_SCOM ); +REG64( PERV_PCI2_XFIR , RULL(0x0F040000), SH_UNT_PERV_15 , SH_ACS_SCOM ); +REG64( PERV_EP00_XFIR , RULL(0x10040000), SH_UNT_PERV_16 , SH_ACS_SCOM ); +REG64( PERV_EP01_XFIR , RULL(0x11040000), SH_UNT_PERV_17 , SH_ACS_SCOM ); +REG64( PERV_EP02_XFIR , RULL(0x12040000), SH_UNT_PERV_18 , SH_ACS_SCOM ); +REG64( PERV_EP03_XFIR , RULL(0x13040000), SH_UNT_PERV_19 , SH_ACS_SCOM ); +REG64( PERV_EP04_XFIR , RULL(0x14040000), SH_UNT_PERV_20 , SH_ACS_SCOM ); +REG64( PERV_EP05_XFIR , RULL(0x15040000), SH_UNT_PERV_21 , SH_ACS_SCOM ); +REG64( PERV_EC00_XFIR , RULL(0x20040000), SH_UNT_PERV_32 , SH_ACS_SCOM ); +REG64( PERV_EC01_XFIR , RULL(0x21040000), SH_UNT_PERV_33 , SH_ACS_SCOM ); +REG64( PERV_EC02_XFIR , RULL(0x22040000), SH_UNT_PERV_34 , SH_ACS_SCOM ); +REG64( PERV_EC03_XFIR , RULL(0x23040000), SH_UNT_PERV_35 , SH_ACS_SCOM ); +REG64( PERV_EC04_XFIR , RULL(0x24040000), SH_UNT_PERV_36 , SH_ACS_SCOM ); +REG64( PERV_EC05_XFIR , RULL(0x25040000), SH_UNT_PERV_37 , SH_ACS_SCOM ); +REG64( PERV_EC06_XFIR , RULL(0x26040000), SH_UNT_PERV_38 , SH_ACS_SCOM ); +REG64( PERV_EC07_XFIR , RULL(0x27040000), SH_UNT_PERV_39 , SH_ACS_SCOM ); +REG64( PERV_EC08_XFIR , RULL(0x28040000), SH_UNT_PERV_40 , SH_ACS_SCOM ); +REG64( PERV_EC09_XFIR , RULL(0x29040000), SH_UNT_PERV_41 , SH_ACS_SCOM ); +REG64( PERV_EC10_XFIR , RULL(0x2A040000), SH_UNT_PERV_42 , SH_ACS_SCOM ); +REG64( PERV_EC11_XFIR , RULL(0x2B040000), SH_UNT_PERV_43 , SH_ACS_SCOM ); +REG64( PERV_EC12_XFIR , RULL(0x2C040000), SH_UNT_PERV_44 , SH_ACS_SCOM ); +REG64( PERV_EC13_XFIR , RULL(0x2D040000), SH_UNT_PERV_45 , SH_ACS_SCOM ); +REG64( PERV_EC14_XFIR , RULL(0x2E040000), SH_UNT_PERV_46 , SH_ACS_SCOM ); +REG64( PERV_EC15_XFIR , RULL(0x2F040000), SH_UNT_PERV_47 , SH_ACS_SCOM ); +REG64( PERV_EC16_XFIR , RULL(0x30040000), SH_UNT_PERV_48 , SH_ACS_SCOM ); +REG64( PERV_EC17_XFIR , RULL(0x31040000), SH_UNT_PERV_49 , SH_ACS_SCOM ); +REG64( PERV_EC18_XFIR , RULL(0x32040000), SH_UNT_PERV_50 , SH_ACS_SCOM ); +REG64( PERV_EC19_XFIR , RULL(0x33040000), SH_UNT_PERV_51 , SH_ACS_SCOM ); +REG64( PERV_EC20_XFIR , RULL(0x34040000), SH_UNT_PERV_52 , SH_ACS_SCOM ); +REG64( PERV_EC21_XFIR , RULL(0x35040000), SH_UNT_PERV_53 , SH_ACS_SCOM ); +REG64( PERV_EC22_XFIR , RULL(0x36040000), SH_UNT_PERV_54 , SH_ACS_SCOM ); +REG64( PERV_EC23_XFIR , RULL(0x37040000), SH_UNT_PERV_55 , SH_ACS_SCOM ); REG64( PERV_N3_XSCOM_BASE_REG , RULL(0x05002810), SH_UNT_PERV_5 , SH_ACS_SCOM ); diff --git a/import/chips/p9/common/include/p9_perv_scom_addresses_fld.H b/import/chips/p9/common/include/p9_perv_scom_addresses_fld.H index 30ebe40c..7ef9bbd1 100644 --- a/import/chips/p9/common/include/p9_perv_scom_addresses_fld.H +++ b/import/chips/p9/common/include/p9_perv_scom_addresses_fld.H @@ -32,6 +32,32 @@ #include <p9_scom_template_consts.H> #include <p9_perv_scom_addresses_fld_fixes.H> +REG64_FLD( PERV_1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( PERV_1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); +REG64_FLD( PERV_1_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); +REG64_FLD( PERV_1_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESERVED_LAST_LT ); +REG64_FLD( PERV_1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); +REG64_FLD( PERV_1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); +REG64_FLD( PERV_1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); +REG64_FLD( PERV_1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); +REG64_FLD( PERV_1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); +REG64_FLD( PERV_1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); + +REG64_FLD( PERV_1_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASK ); +REG64_FLD( PERV_1_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASK_LEN ); + REG64_FLD( PERV_1_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PERV_1_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -176,6 +202,11 @@ REG64_FLD( PERV_1_CC_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UN REG64_FLD( PERV_1_CC_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); +REG64_FLD( PERV_CLKRATIO_RATIO , 0 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_RATIO ); +REG64_FLD( PERV_CLKRATIO_RATIO_LEN , 12 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_RATIO_LEN ); + REG64_FLD( PERV_1_CLK_REGION_CLOCK_CMD , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_CLOCK_CMD ); REG64_FLD( PERV_1_CLK_REGION_CLOCK_CMD_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -293,11 +324,6 @@ REG64_FLD( PERV_CMD_WRDAT_WRITE_NOT_READ , 0 , SH_UN REG64_FLD( PERV_PIB2OPB0_CMD_WRDAT_WRITE_NOT_READ , 0 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM , SH_FLD_WRITE_NOT_READ ); -REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_CMD_REG , 0 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , - SH_FLD_CMD_REG ); -REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_CMD_REG_LEN , 32 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , - SH_FLD_CMD_REG_LEN ); - REG32_FLD( PERV_FSI2PIB_COMMAND_REGISTER_CMD_REG , 0 , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_CMD_REG ); REG32_FLD( PERV_FSI2PIB_COMMAND_REGISTER_CMD_REG_LEN , 32 , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , @@ -320,6 +346,29 @@ REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_TYPE , 28 , SH_UN REG32_FLD( PERV_FSISHIFT_COMMAND_REGISTER_CMDREG_SCAN_TYPE_LEN , 4 , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_CMDREG_SCAN_TYPE_LEN ); +REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_WITH_START_0 , 0 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_WITH_START_0 ); +REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_WITH_ADDRESS_0 , 1 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_WITH_ADDRESS_0 ); +REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_READ_CONTINUE_0 , 2 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_READ_CONTINUE_0 ); +REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_WITH_STOP_0 , 3 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_WITH_STOP_0 ); +REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_NOT_USED_0 , 4 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_NOT_USED_0 ); +REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_NOT_USED_0_LEN , 4 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_NOT_USED_0_LEN ); +REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_DEVICE_ADDRESS_0 , 8 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_DEVICE_ADDRESS_0 ); +REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_DEVICE_ADDRESS_0_LEN , 7 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_DEVICE_ADDRESS_0_LEN ); +REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_READ_NOT_WRITE_0 , 15 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_READ_NOT_WRITE_0 ); +REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_LENGTH_IN_BYTES_0 , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_LENGTH_IN_BYTES_0 ); +REG32_FLD( PERV_FSII2C_COMMAND_REGISTER_A_LENGTH_IN_BYTES_0_LEN , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_LENGTH_IN_BYTES_0_LEN ); + REG32_FLD( PERV_FSI2PIB_COMPLEMENT_MASK_REG , 0 , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_REG ); REG32_FLD( PERV_FSI2PIB_COMPLEMENT_MASK_REG_LEN , 32 , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , @@ -712,6 +761,37 @@ REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_22E , 22 , SH_UN REG64_FLD( PERV_1_CPLT_STAT0_FREE_USAGE_23E , 23 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_FREE_USAGE_23E ); +REG64_FLD( PERV_CSAR_SRAM_ADDRESS , 16 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_SRAM_ADDRESS ); +REG64_FLD( PERV_CSAR_SRAM_ADDRESS_LEN , 13 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_SRAM_ADDRESS_LEN ); + +REG64_FLD( PERV_CSCR_SRAM_ACCESS_MODE , 0 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_ACCESS_MODE ); +REG64_FLD( PERV_CSCR_SRAM_SCRUB_ENABLE , 1 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_SCRUB_ENABLE ); +REG64_FLD( PERV_CSCR_ECC_CORRECT_DIS , 2 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ECC_CORRECT_DIS ); +REG64_FLD( PERV_CSCR_ECC_DETECT_DIS , 3 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ECC_DETECT_DIS ); +REG64_FLD( PERV_CSCR_ECC_INJECT_TYPE , 4 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ECC_INJECT_TYPE ); +REG64_FLD( PERV_CSCR_ECC_INJECT_ERR , 5 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ECC_INJECT_ERR ); +REG64_FLD( PERV_CSCR_SPARE_6_7 , 6 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_6_7 ); +REG64_FLD( PERV_CSCR_SPARE_6_7_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_6_7_LEN ); +REG64_FLD( PERV_CSCR_SRAM_SCRUB_INDEX , 47 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_SCRUB_INDEX ); +REG64_FLD( PERV_CSCR_SRAM_SCRUB_INDEX_LEN , 13 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_SCRUB_INDEX_LEN ); + +REG64_FLD( PERV_CSDR_SRAM_DATA , 0 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_SRAM_DATA ); +REG64_FLD( PERV_CSDR_SRAM_DATA_LEN , 64 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_SRAM_DATA_LEN ); + REG64_FLD( PERV_1_CTRL_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PERV_1_CTRL_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -787,6 +867,398 @@ REG64_FLD( PERV_1_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE , 30 , SH_UN REG64_FLD( PERV_1_DBG_CBS_CC_TP_TPFSI_ACK , 31 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_TP_TPFSI_ACK ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A_LEN ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B_LEN ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A_LEN ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B_LEN ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_C1_INAROW_MODE ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE1 ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE1 ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE1 ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1 ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1_LEN ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_C2_INAROW_MODE ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE2 ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE2 ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE2 ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2 ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2_LEN ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND3_ENABLE_RESET ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_EXACT_TO_MODE ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESET_C2TIMER_ON_C1 ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESET_C3_ON_C0 ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SLOW_TO_MODE ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_EXACT_RESET_C3_ON_TO ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT_LEN ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT_LEN ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT_LEN ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); + +REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE_LEN ); +REG64_FLD( PERV_1_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST_MODE ); + +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_A_LEN ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND1_SEL_B , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND1_SEL_B_LEN ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND2_SEL_A , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_A_LEN ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND2_SEL_B , 21 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND2_SEL_B_LEN ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 28 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_C1_INAROW_MODE ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 29 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE1 ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 30 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE1 ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 31 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE1 ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1 , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1 ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_X_COUPLE_SELECT1_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT1_LEN ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 35 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_C2_INAROW_MODE ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 36 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_AND_TRIGGER_MODE2 ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 37 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_NOT_TRIGGER_MODE2 ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 38 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_EDGE_TRIGGER_MODE2 ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2 , 39 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2 ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_X_COUPLE_SELECT2_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_X_COUPLE_SELECT2_LEN ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 42 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND3_ENABLE_RESET ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 43 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_EXACT_TO_MODE ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 44 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESET_C2TIMER_ON_C1 ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 45 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESET_C3_ON_C0 ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 46 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SLOW_TO_MODE ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 47 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_EXACT_RESET_C3_ON_TO ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_C1_COUNT_LT , 48 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_C1_COUNT_LT_LEN ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_C2_COUNT_LT , 52 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_C2_COUNT_LT_LEN ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 56 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESET_C3_SELECT_LEN ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A , 59 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_1_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); + +REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_SP_COUNT_LT , 15 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_SP_COUNT_LT_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SP_COUNT_LT_LEN ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE , 39 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_TO_CMP_LT_VALUE_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TO_CMP_LT_VALUE_LEN ); +REG64_FLD( PERV_1_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 63 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST_MODE ); + +REG64_FLD( PERV_1_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GLB_BRCST ); +REG64_FLD( PERV_1_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GLB_BRCST_LEN ); +REG64_FLD( PERV_1_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL ); +REG64_FLD( PERV_1_DBG_MODE_REG_TRACE_SEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRACE_SEL_LEN ); +REG64_FLD( PERV_1_DBG_MODE_REG_TRIG_SEL , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL ); +REG64_FLD( PERV_1_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG_SEL_LEN ); +REG64_FLD( PERV_1_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_STOP_ON_XSTOP_SELECTION ); +REG64_FLD( PERV_1_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); +REG64_FLD( PERV_1_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_STOP_ON_SPATTN_SELECTION ); +REG64_FLD( PERV_1_DBG_MODE_REG_FREEZE_SEL , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FREEZE_SEL ); + +REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RUNN_COUNT_COMPARE_VALUE ); +REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_IMM_FREEZE , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_IMM_FREEZE ); +REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_STOP_ON_ERR , 17 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_STOP_ON_ERR ); +REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_BANK_ON_RUNN_MATCH ); +REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_FORCE_TEST , 19 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FORCE_TEST ); +REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_ACCUM_HIST , 20 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ACCUM_HIST ); +REG64_FLD( PERV_1_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ , 21 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FRZ_COUNT_ON_FRZ ); + +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_COND3_ENABLE , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_COND3_ENABLE ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_COND3_ENABLE , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_COND3_ENABLE ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST3_COND3_ENABLE , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST3_COND3_ENABLE ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST4_COND3_ENABLE , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST4_COND3_ENABLE ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_SLOW_LFSR_MODE ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_SLOW_LFSR_MODE ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST3_SLOW_LFSR_MODE ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST4_SLOW_LFSR_MODE ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_TRIG_SEL ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_TRIG_SEL ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_TRIG_SEL ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_TRIG_SEL ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_EXT_TRIG_ON_STOP ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE , 33 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_EXT_TRIG_ON_FREEZE ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL , 34 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CORE_RAS0_TRIG_SEL ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CORE_RAS0_TRIG_SEL_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL , 39 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CORE_RAS1_TRIG_SEL ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CORE_RAS1_TRIG_SEL_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL , 44 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PC_TP_TRIG_SEL ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PC_TP_TRIG_SEL_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_ARM_SEL , 46 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ARM_SEL ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_ARM_SEL_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ARM_SEL_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL , 50 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG0_LEVEL_SEL ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG0_LEVEL_SEL_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL , 54 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG1_LEVEL_SEL ); +REG64_FLD( PERV_1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG1_LEVEL_SEL_LEN ); + +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_DO ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_DO_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_DO ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_DO_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_DO ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_DO ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_DO_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_DO ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_DO_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_DO ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_WAITN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_WAITN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_WAITN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_WAITN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION1_ACTION_BANK ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CONDITION2_ACTION_BANK ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION1_ACTION_BANK ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CONDITION2_ACTION_BANK ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT , 48 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_LT ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT , 52 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_LT ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN ); +REG64_FLD( PERV_1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); + +REG64_FLD( PERV_1_DEBUG_STATUS_REG_LOCAL_TRACE_RUN_IN , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_LOCAL_TRACE_RUN_IN ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_TRACE_STATE_LAT , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRACE_STATE_LAT ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_TRACE_STATE_LAT_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRACE_STATE_LAT_LEN ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_TRACE_FREEZE , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRACE_FREEZE ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_COND3_STATE_LT , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND3_STATE_LT ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_COND3_STATE_LT_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND3_STATE_LT_LEN ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_COND5_STATE_LT , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND5_STATE_LT ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_COND5_STATE_LT_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_COND5_STATE_LT_LEN ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_HISTORY_CONDITION0_LT , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_HISTORY_CONDITION0_LT ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_HISTORY_CONDITION1_LT , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_HISTORY_CONDITION1_LT ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_HISTORY_COND2_3_EVENT , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND2_3_EVENT ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_HISTORY_COND2_TIMEOUT , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND2_TIMEOUT ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_HISTORY_COND4_5_EVENT , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND4_5_EVENT ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_HISTORY_COND4_TIMEOUT , 13 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_HISTORY_COND4_TIMEOUT ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_RESERVED_TCDBG_LT , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESERVED_TCDBG_LT ); +REG64_FLD( PERV_1_DEBUG_STATUS_REG_RESERVED_TCDBG_LT_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESERVED_TCDBG_LT_LEN ); + +REG64_FLD( PERV_DEVICE_ID_REG_SOCKET , 36 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SOCKET ); +REG64_FLD( PERV_DEVICE_ID_REG_SOCKET_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SOCKET_LEN ); +REG64_FLD( PERV_DEVICE_ID_REG_CHIPPOS , 39 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_CHIPPOS ); + REG32_FLD( PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER_REG , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG ); REG32_FLD( PERV_FSISHIFT_DMA_ERROR_PTR_REGISTER_REG_LEN , 32 , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , @@ -984,207 +1456,17 @@ REG64_FLD( PERV_1_ERR_STATUS_REG_F_SKITTER_READ_MASK , 30 , SH_UN REG64_FLD( PERV_1_ERR_STATUS_REG_PCB_MASK , 31 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , SH_FLD_PCB_MASK ); -REG64_FLD( PERV_FI2C_CFG_PIBI2CM_PIB_SLAVE_ID , 0 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_PIBI2CM_PIB_SLAVE_ID ); -REG64_FLD( PERV_FI2C_CFG_PIBI2CM_PIB_SLAVE_ID_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_PIBI2CM_PIB_SLAVE_ID_LEN ); -REG64_FLD( PERV_FI2C_CFG_ECC_ENABLE , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_ECC_ENABLE ); -REG64_FLD( PERV_FI2C_CFG_DISABLE_ECC_CHK , 17 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_DISABLE_ECC_CHK ); -REG64_FLD( PERV_FI2C_CFG_I2C_SPEED_MUX , 18 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_I2C_SPEED_MUX ); -REG64_FLD( PERV_FI2C_CFG_I2C_SPEED_MUX_LEN , 2 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_I2C_SPEED_MUX_LEN ); -REG64_FLD( PERV_FI2C_CFG_BIT_RATE_DIVISOR_VALUE , 20 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_BIT_RATE_DIVISOR_VALUE ); -REG64_FLD( PERV_FI2C_CFG_BIT_RATE_DIVISOR_VALUE_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_BIT_RATE_DIVISOR_VALUE_LEN ); -REG64_FLD( PERV_FI2C_CFG_I2C_BUS_HELD_MODE_ENABLE , 36 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_I2C_BUS_HELD_MODE_ENABLE ); -REG64_FLD( PERV_FI2C_CFG_PIPELINE_ENABLE , 37 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_PIPELINE_ENABLE ); -REG64_FLD( PERV_FI2C_CFG_BACKUP_SEEPROM_SELECT , 38 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_BACKUP_SEEPROM_SELECT ); -REG64_FLD( PERV_FI2C_CFG_FORCE_RESET , 39 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_FORCE_RESET ); -REG64_FLD( PERV_FI2C_CFG_RESET_PIB , 40 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESET_PIB ); -REG64_FLD( PERV_FI2C_CFG_RESERVED_FOR_CONFIGS , 41 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_FOR_CONFIGS ); -REG64_FLD( PERV_FI2C_CFG_RESERVED_FOR_CONFIGS_LEN , 3 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_FOR_CONFIGS_LEN ); -REG64_FLD( PERV_FI2C_CFG_I2C_TIMEOUT , 44 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_I2C_TIMEOUT ); -REG64_FLD( PERV_FI2C_CFG_I2C_TIMEOUT_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_I2C_TIMEOUT_LEN ); - -REG64_FLD( PERV_FI2C_SCFG0_REGISTER_VALID , 0 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_REGISTER_VALID ); -REG64_FLD( PERV_FI2C_SCFG0_RESERVED_3 , 1 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_3 ); -REG64_FLD( PERV_FI2C_SCFG0_RESERVED_4 , 2 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_4 ); -REG64_FLD( PERV_FI2C_SCFG0_RESERVED_4_LEN , 2 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_4_LEN ); -REG64_FLD( PERV_FI2C_SCFG0_RESERVED_5 , 4 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_5 ); -REG64_FLD( PERV_FI2C_SCFG0_RESERVED_5_LEN , 4 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_5_LEN ); -REG64_FLD( PERV_FI2C_SCFG0_DEVICE_ID , 8 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_DEVICE_ID ); -REG64_FLD( PERV_FI2C_SCFG0_DEVICE_ID_LEN , 7 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_DEVICE_ID_LEN ); -REG64_FLD( PERV_FI2C_SCFG0_ECC_ENABLE , 15 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_ECC_ENABLE ); -REG64_FLD( PERV_FI2C_SCFG0_MEMORY_SIZE_IN_PPE_ADDR_MAP , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP ); -REG64_FLD( PERV_FI2C_SCFG0_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN ); -REG64_FLD( PERV_FI2C_SCFG0_START_SEEPROM_ADDRESS , 32 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_SEEPROM_ADDRESS ); -REG64_FLD( PERV_FI2C_SCFG0_START_SEEPROM_ADDRESS_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_SEEPROM_ADDRESS_LEN ); -REG64_FLD( PERV_FI2C_SCFG0_START_PPE_ADDR , 48 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_PPE_ADDR ); -REG64_FLD( PERV_FI2C_SCFG0_START_PPE_ADDR_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_PPE_ADDR_LEN ); - -REG64_FLD( PERV_FI2C_SCFG1_REGISTER_VALID , 0 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_REGISTER_VALID ); -REG64_FLD( PERV_FI2C_SCFG1_RESERVED_6 , 1 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_6 ); -REG64_FLD( PERV_FI2C_SCFG1_RESERVED_7 , 2 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_7 ); -REG64_FLD( PERV_FI2C_SCFG1_RESERVED_7_LEN , 2 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_7_LEN ); -REG64_FLD( PERV_FI2C_SCFG1_RESERVED_8 , 4 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_8 ); -REG64_FLD( PERV_FI2C_SCFG1_RESERVED_8_LEN , 4 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_8_LEN ); -REG64_FLD( PERV_FI2C_SCFG1_DEVICE_ID , 8 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_DEVICE_ID ); -REG64_FLD( PERV_FI2C_SCFG1_DEVICE_ID_LEN , 7 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_DEVICE_ID_LEN ); -REG64_FLD( PERV_FI2C_SCFG1_ECC_ENABLE , 15 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_ECC_ENABLE ); -REG64_FLD( PERV_FI2C_SCFG1_MEMORY_SIZE_IN_PPE_ADDR_MAP , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP ); -REG64_FLD( PERV_FI2C_SCFG1_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN ); -REG64_FLD( PERV_FI2C_SCFG1_START_SEEPROM_ADDRESS , 32 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_SEEPROM_ADDRESS ); -REG64_FLD( PERV_FI2C_SCFG1_START_SEEPROM_ADDRESS_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_SEEPROM_ADDRESS_LEN ); -REG64_FLD( PERV_FI2C_SCFG1_START_PPE_ADDR , 48 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_PPE_ADDR ); -REG64_FLD( PERV_FI2C_SCFG1_START_PPE_ADDR_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_PPE_ADDR_LEN ); - -REG64_FLD( PERV_FI2C_SCFG2_REGISTER_VALID , 0 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_REGISTER_VALID ); -REG64_FLD( PERV_FI2C_SCFG2_RESERVED_9 , 1 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_9 ); -REG64_FLD( PERV_FI2C_SCFG2_RESERVED_10 , 2 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_10 ); -REG64_FLD( PERV_FI2C_SCFG2_RESERVED_10_LEN , 2 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_10_LEN ); -REG64_FLD( PERV_FI2C_SCFG2_RESERVED_11 , 4 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_11 ); -REG64_FLD( PERV_FI2C_SCFG2_RESERVED_11_LEN , 4 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_11_LEN ); -REG64_FLD( PERV_FI2C_SCFG2_DEVICE_ID , 8 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_DEVICE_ID ); -REG64_FLD( PERV_FI2C_SCFG2_DEVICE_ID_LEN , 7 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_DEVICE_ID_LEN ); -REG64_FLD( PERV_FI2C_SCFG2_ECC_ENABLE , 15 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_ECC_ENABLE ); -REG64_FLD( PERV_FI2C_SCFG2_MEMORY_SIZE_IN_PPE_ADDR_MAP , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP ); -REG64_FLD( PERV_FI2C_SCFG2_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN ); -REG64_FLD( PERV_FI2C_SCFG2_START_SEEPROM_ADDRESS , 32 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_SEEPROM_ADDRESS ); -REG64_FLD( PERV_FI2C_SCFG2_START_SEEPROM_ADDRESS_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_SEEPROM_ADDRESS_LEN ); -REG64_FLD( PERV_FI2C_SCFG2_START_PPE_ADDR , 48 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_PPE_ADDR ); -REG64_FLD( PERV_FI2C_SCFG2_START_PPE_ADDR_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_PPE_ADDR_LEN ); - -REG64_FLD( PERV_FI2C_SCFG3_REGISTER_VALID , 0 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_REGISTER_VALID ); -REG64_FLD( PERV_FI2C_SCFG3_RESERVED_12 , 1 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_12 ); -REG64_FLD( PERV_FI2C_SCFG3_RESERVED_13 , 2 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_13 ); -REG64_FLD( PERV_FI2C_SCFG3_RESERVED_13_LEN , 2 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_13_LEN ); -REG64_FLD( PERV_FI2C_SCFG3_RESERVED_14 , 4 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_14 ); -REG64_FLD( PERV_FI2C_SCFG3_RESERVED_14_LEN , 4 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_14_LEN ); -REG64_FLD( PERV_FI2C_SCFG3_DEVICE_ID , 8 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_DEVICE_ID ); -REG64_FLD( PERV_FI2C_SCFG3_DEVICE_ID_LEN , 7 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_DEVICE_ID_LEN ); -REG64_FLD( PERV_FI2C_SCFG3_ECC_ENABLE , 15 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_ECC_ENABLE ); -REG64_FLD( PERV_FI2C_SCFG3_MEMORY_SIZE_IN_PPE_ADDR_MAP , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP ); -REG64_FLD( PERV_FI2C_SCFG3_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN ); -REG64_FLD( PERV_FI2C_SCFG3_START_SEEPROM_ADDRESS , 32 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_SEEPROM_ADDRESS ); -REG64_FLD( PERV_FI2C_SCFG3_START_SEEPROM_ADDRESS_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_SEEPROM_ADDRESS_LEN ); -REG64_FLD( PERV_FI2C_SCFG3_START_PPE_ADDR , 48 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_PPE_ADDR ); -REG64_FLD( PERV_FI2C_SCFG3_START_PPE_ADDR_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_START_PPE_ADDR_LEN ); - -REG64_FLD( PERV_FI2C_STAT_PIB_RESPONSE_INFO , 0 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_PIB_RESPONSE_INFO ); -REG64_FLD( PERV_FI2C_STAT_PIB_RESPONSE_INFO_LEN , 3 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_PIB_RESPONSE_INFO_LEN ); -REG64_FLD( PERV_FI2C_STAT_I2CM_PIB_ERRORS , 3 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_I2CM_PIB_ERRORS ); -REG64_FLD( PERV_FI2C_STAT_I2CM_PIB_ERRORS_LEN , 6 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_I2CM_PIB_ERRORS_LEN ); -REG64_FLD( PERV_FI2C_STAT_I2CM_ECC_ERRORS , 9 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_I2CM_ECC_ERRORS ); -REG64_FLD( PERV_FI2C_STAT_I2CM_ECC_ERRORS_LEN , 3 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_I2CM_ECC_ERRORS_LEN ); -REG64_FLD( PERV_FI2C_STAT_I2CM_I2C_ERRORS , 12 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_I2CM_I2C_ERRORS ); -REG64_FLD( PERV_FI2C_STAT_I2CM_I2C_ERRORS_LEN , 7 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_I2CM_I2C_ERRORS_LEN ); -REG64_FLD( PERV_FI2C_STAT_ERR_ADDR_BEYOND_RANGE , 19 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_ERR_ADDR_BEYOND_RANGE ); -REG64_FLD( PERV_FI2C_STAT_ERR_ADDR_OVERLAP , 20 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_ERR_ADDR_OVERLAP ); -REG64_FLD( PERV_FI2C_STAT_PIB_ABORT , 21 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_PIB_ABORT ); -REG64_FLD( PERV_FI2C_STAT_RESERVED_FOR_ERRS , 22 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_RESERVED_FOR_ERRS ); -REG64_FLD( PERV_FI2C_STAT_RESERVED_FOR_ERRS_LEN , 10 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_RESERVED_FOR_ERRS_LEN ); -REG64_FLD( PERV_FI2C_STAT_LOCKED_PIBM_ADDR , 32 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_LOCKED_PIBM_ADDR ); -REG64_FLD( PERV_FI2C_STAT_LOCKED_PIBM_ADDR_LEN , 8 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_LOCKED_PIBM_ADDR_LEN ); -REG64_FLD( PERV_FI2C_STAT_RESERVED_FOR_ADDRESS , 40 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_RESERVED_FOR_ADDRESS ); -REG64_FLD( PERV_FI2C_STAT_RESERVED_FOR_ADDRESS_LEN , 3 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_RESERVED_FOR_ADDRESS_LEN ); -REG64_FLD( PERV_FI2C_STAT_LOCKED_FSM_STATE , 43 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_LOCKED_FSM_STATE ); -REG64_FLD( PERV_FI2C_STAT_LOCKED_FSM_STATE_LEN , 5 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_LOCKED_FSM_STATE_LEN ); -REG64_FLD( PERV_FI2C_STAT_LOCKED_SEEPROM_ADDRESS , 48 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_LOCKED_SEEPROM_ADDRESS ); -REG64_FLD( PERV_FI2C_STAT_LOCKED_SEEPROM_ADDRESS_LEN , 16 , SH_UNT_PERV , SH_ACS_PPE , - SH_FLD_LOCKED_SEEPROM_ADDRESS_LEN ); +REG32_FLD( PERV_FSII2C_EXTENDED_STATUS_A_MSM_CURR_STATE_0 , 11 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_MSM_CURR_STATE_0 ); +REG32_FLD( PERV_FSII2C_EXTENDED_STATUS_A_MSM_CURR_STATE_0_LEN , 5 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_MSM_CURR_STATE_0_LEN ); +REG32_FLD( PERV_FSII2C_EXTENDED_STATUS_A_SELF_BUSY_0 , 25 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_SELF_BUSY_0 ); + +REG32_FLD( PERV_FSII2C_FIFO1_REGISTER_READ_A_FIFO_BITS_READ0_0 , 0 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ0_0 ); +REG32_FLD( PERV_FSII2C_FIFO1_REGISTER_READ_A_FIFO_BITS_READ0_0_LEN , 8 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_FIFO_BITS_READ0_0_LEN ); REG64_FLD( PERV_FIRST_ERR_REG_TIMEOUT_ACTIVE , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TIMEOUT_ACTIVE ); @@ -1257,6 +1539,127 @@ REG64_FLD( PERV_1_FIR_MASK_IN21_LEN , 5 , SH_UN REG64_FLD( PERV_1_FIR_MASK_IN26 , 26 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_IN26 ); +REG64_FLD( PERV_FIR_REG_AIB_COMMAND_INVALID , 0 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_AIB_COMMAND_INVALID ); +REG64_FLD( PERV_FIR_REG_AIB_ADDRESS_INVALID , 1 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_AIB_ADDRESS_INVALID ); +REG64_FLD( PERV_FIR_REG_AIB_ACCESS_ERROR , 2 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_AIB_ACCESS_ERROR ); +REG64_FLD( PERV_FIR_REG_PAPR_OUTBOUND_INJECT_ERROR , 3 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_PAPR_OUTBOUND_INJECT_ERROR ); +REG64_FLD( PERV_FIR_REG_AIB_FATAL_CLASS_ERROR , 4 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_AIB_FATAL_CLASS_ERROR ); +REG64_FLD( PERV_FIR_REG_AIB_INF_CLASS_ERROR , 6 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_AIB_INF_CLASS_ERROR ); +REG64_FLD( PERV_FIR_REG_PE_STOP_STATE_SIGNALED , 7 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_PE_STOP_STATE_SIGNALED ); +REG64_FLD( PERV_FIR_REG_OUT_COMMON_ARRAY_FATAL_ERROR , 8 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR ); +REG64_FLD( PERV_FIR_REG_OUT_COMMON_LATCH_FATAL_ERROR , 9 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR ); +REG64_FLD( PERV_FIR_REG_OUT_COMMON_LOGIC_FATAL_ERROR , 10 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR ); +REG64_FLD( PERV_FIR_REG_BLIF_OUT_INTERFACE_PARITY_ERROR , 11 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR ); +REG64_FLD( PERV_FIR_REG_CFG_WRITE_CA_OR_UR_RESPONSE , 12 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_CFG_WRITE_CA_OR_UR_RESPONSE ); +REG64_FLD( PERV_FIR_REG_MMIO_REQUEST_TIMEOUT , 13 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_MMIO_REQUEST_TIMEOUT ); +REG64_FLD( PERV_FIR_REG_OUT_RRB_SOURCED_ERROR , 14 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_OUT_RRB_SOURCED_ERROR ); +REG64_FLD( PERV_FIR_REG_CFG_LOGIC_SIGNALED_ERROR , 15 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_CFG_LOGIC_SIGNALED_ERROR ); +REG64_FLD( PERV_FIR_REG_RSB_REQUEST_ADDRESS_ERROR , 16 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_RSB_REQUEST_ADDRESS_ERROR ); +REG64_FLD( PERV_FIR_REG_RSB_FDA_FATAL_ERROR , 17 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDA_FATAL_ERROR ); +REG64_FLD( PERV_FIR_REG_RSB_FDA_INF_ERROR , 18 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDA_INF_ERROR ); +REG64_FLD( PERV_FIR_REG_RSB_FDB_FATAL_ERROR , 19 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDB_FATAL_ERROR ); +REG64_FLD( PERV_FIR_REG_RSB_FDB_INF_ERROR , 20 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_RSB_FDB_INF_ERROR ); +REG64_FLD( PERV_FIR_REG_RSB_ERR_FATAL_ERROR , 21 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_RSB_ERR_FATAL_ERROR ); +REG64_FLD( PERV_FIR_REG_RSB_ERR_INF_ERROR , 22 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_RSB_ERR_INF_ERROR ); +REG64_FLD( PERV_FIR_REG_RSB_DBG_FATAL_ERROR , 23 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_RSB_DBG_FATAL_ERROR ); +REG64_FLD( PERV_FIR_REG_RSB_DBG_INF_ERROR , 24 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_RSB_DBG_INF_ERROR ); +REG64_FLD( PERV_FIR_REG_PCIE_REQUEST_ACCESS_ERROR , 25 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_PCIE_REQUEST_ACCESS_ERROR ); +REG64_FLD( PERV_FIR_REG_RSB_BUS_LOGIC_ERROR , 26 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_RSB_BUS_LOGIC_ERROR ); +REG64_FLD( PERV_FIR_REG_RSB_UVI_FATAL_ERROR , 27 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_RSB_UVI_FATAL_ERROR ); +REG64_FLD( PERV_FIR_REG_RSB_UVI_INF_ERROR , 28 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_RSB_UVI_INF_ERROR ); +REG64_FLD( PERV_FIR_REG_SCOM_FATAL_ERROR , 29 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_FATAL_ERROR ); +REG64_FLD( PERV_FIR_REG_SCOM_INF_ERROR , 30 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_SCOM_INF_ERROR ); +REG64_FLD( PERV_FIR_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS , 31 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS ); +REG64_FLD( PERV_FIR_REG_ARB_IODA_FATAL_ERROR , 32 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_IODA_FATAL_ERROR ); +REG64_FLD( PERV_FIR_REG_ARB_MSI_PE_MATCH_ERROR , 33 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_MSI_PE_MATCH_ERROR ); +REG64_FLD( PERV_FIR_REG_ARB_MSI_ADDRESS_ERROR , 34 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_MSI_ADDRESS_ERROR ); +REG64_FLD( PERV_FIR_REG_ARB_TVT_ERROR , 35 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_TVT_ERROR ); +REG64_FLD( PERV_FIR_REG_ARB_RCVD_FATAL_ERROR_MSG , 36 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RCVD_FATAL_ERROR_MSG ); +REG64_FLD( PERV_FIR_REG_ARB_RCVD_NONFATAL_ERROR_MSG , 37 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG ); +REG64_FLD( PERV_FIR_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG , 38 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG ); +REG64_FLD( PERV_FIR_REG_PAPR_INBOUND_INJECT_ERROR , 39 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_PAPR_INBOUND_INJECT_ERROR ); +REG64_FLD( PERV_FIR_REG_ARB_COMMON_FATAL_ERROR , 40 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_COMMON_FATAL_ERROR ); +REG64_FLD( PERV_FIR_REG_ARB_TABLE_BAR_DISABLED_ERROR , 41 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PERV_FIR_REG_ARB_BLIF_COMPLETION_ERROR , 42 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_BLIF_COMPLETION_ERROR ); +REG64_FLD( PERV_FIR_REG_ARB_PCT_TIMEOUT_ERROR , 43 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_PCT_TIMEOUT_ERROR ); +REG64_FLD( PERV_FIR_REG_ARB_ECC_CORRECTABLE_ERROR , 44 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PERV_FIR_REG_ARB_ECC_UNCORRECTABLE_ERROR , 45 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PERV_FIR_REG_ARB_TLP_POISON_SIGNALED , 46 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_TLP_POISON_SIGNALED ); +REG64_FLD( PERV_FIR_REG_ARB_RTT_PENUM_INVALID_ERROR , 47 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_ARB_RTT_PENUM_INVALID_ERROR ); +REG64_FLD( PERV_FIR_REG_MRG_COMMON_FATAL_ERROR , 48 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_MRG_COMMON_FATAL_ERROR ); +REG64_FLD( PERV_FIR_REG_MRG_TABLE_BAR_DISABLED_ERROR , 49 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR ); +REG64_FLD( PERV_FIR_REG_MRG_ECC_CORRECTABLE_ERROR , 50 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_MRG_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PERV_FIR_REG_MRG_ECC_UNCORRECTABLE_ERROR , 51 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PERV_FIR_REG_MRG_AIB2_TX_TIMEOUT_ERROR , 52 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR ); +REG64_FLD( PERV_FIR_REG_MRG_MRT_ERROR , 53 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_MRG_MRT_ERROR ); +REG64_FLD( PERV_FIR_REG_TCE_IODA_PAGE_ACCESS_ERROR , 56 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR ); +REG64_FLD( PERV_FIR_REG_TCE_REQUEST_TIMEOUT_ERROR , 57 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_TCE_REQUEST_TIMEOUT_ERROR ); +REG64_FLD( PERV_FIR_REG_TCE_UNEXPECTED_RESPONSE_ERROR , 58 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR ); +REG64_FLD( PERV_FIR_REG_TCE_COMMON_FATAL_ERROR , 59 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_TCE_COMMON_FATAL_ERROR ); +REG64_FLD( PERV_FIR_REG_TCE_ECC_CORRECTABLE_ERROR , 60 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_TCE_ECC_CORRECTABLE_ERROR ); +REG64_FLD( PERV_FIR_REG_TCE_ECC_UNCORRECTABLE_ERROR , 61 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR ); +REG64_FLD( PERV_FIR_REG_INTERNAL_PARITY_ERROR , 63 , SH_UNT_PERV , SH_ACS_SCOM2_OR , + SH_FLD_INTERNAL_PARITY_ERROR ); + REG64_FLD( PERV_1_FMU_MODE_REG_TOD_CNTR_REF , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_TOD_CNTR_REF ); REG64_FLD( PERV_1_FMU_MODE_REG_TOD_CNTR_REF_LEN , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -2409,78 +2812,210 @@ REG64_FLD( PERV_GPWRP_EN_OR_DIS_WRITE_PROTECTION , 16 , SH_UN REG64_FLD( PERV_GPWRP_EN_OR_DIS_WRITE_PROTECTION_LEN , 16 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_EN_OR_DIS_WRITE_PROTECTION_LEN ); -REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_XSTOP_IN , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_GXSTP0_XSTOP_IN ); -REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_XSTOP_IN_LEN , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_GXSTP0_XSTOP_IN_LEN ); - -REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_XSTOP_IN , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_GXSTP1_XSTOP_IN ); -REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_XSTOP_IN_LEN , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_GXSTP1_XSTOP_IN_LEN ); - -REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_XSTOP_IN , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_GXSTP2_XSTOP_IN ); -REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_XSTOP_IN_LEN , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_GXSTP2_XSTOP_IN_LEN ); - -REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_GXSTP_IN ); -REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN_LEN , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_GXSTP_IN_LEN ); - -REG64_FLD( PERV_1_HANG_PULSE_0_REG_0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN0 ); +REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1 , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN1 ); +REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2 , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN2 ); +REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3 , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN3 ); +REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4 , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN4 ); +REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5 , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN5 ); +REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6 , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN6 ); +REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7 , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN7 ); +REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8 , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN8 ); +REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9 , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN9 ); +REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10 , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN10 ); +REG64_FLD( PERV_1_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11 , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP0_TRIG_IN11 ); + +REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN0 ); +REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1 , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN1 ); +REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2 , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN2 ); +REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3 , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN3 ); +REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4 , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN4 ); +REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5 , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN5 ); +REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6 , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN6 ); +REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7 , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN7 ); +REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8 , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN8 ); +REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9 , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN9 ); +REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10 , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN10 ); +REG64_FLD( PERV_1_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11 , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP1_TRIG_IN11 ); + +REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN0 ); +REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1 , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN1 ); +REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2 , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN2 ); +REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3 , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN3 ); +REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4 , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN4 ); +REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5 , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN5 ); +REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6 , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN6 ); +REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7 , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN7 ); +REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8 , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN8 ); +REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9 , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN9 ); +REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10 , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN10 ); +REG64_FLD( PERV_1_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11 , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP2_TRIG_IN11 ); + +REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP_IN0 ); +REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN1 , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP_IN1 ); +REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN2 , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP_IN2 ); +REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN3 , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP_IN3 ); +REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN4 , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP_IN4 ); +REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN5 , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP_IN5 ); +REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN6 , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP_IN6 ); +REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN7 , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP_IN7 ); +REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN8 , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP_IN8 ); +REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN9 , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP_IN9 ); +REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN10 , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP_IN10 ); +REG64_FLD( PERV_1_GXSTOP_TRIG_REG_GXSTP_IN11 , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GXSTP_IN11 ); + +REG64_FLD( PERV_1_HANG_PULSE_0_REG_0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_0 ); -REG64_FLD( PERV_1_HANG_PULSE_0_REG_0_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_0_REG_0_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_0_LEN ); -REG64_FLD( PERV_1_HANG_PULSE_0_REG_SUPPRESS , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_0_REG_SUPPRESS , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); -REG64_FLD( PERV_1_HANG_PULSE_1_REG_1 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_1_REG_1 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_1 ); -REG64_FLD( PERV_1_HANG_PULSE_1_REG_1_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_1_REG_1_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_1_LEN ); -REG64_FLD( PERV_1_HANG_PULSE_1_REG_SUPPRESS , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_1_REG_SUPPRESS , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); -REG64_FLD( PERV_1_HANG_PULSE_2_REG_2 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_2_REG_2 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_2 ); -REG64_FLD( PERV_1_HANG_PULSE_2_REG_2_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_2_REG_2_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_2_LEN ); -REG64_FLD( PERV_1_HANG_PULSE_2_REG_SUPPRESS , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_2_REG_SUPPRESS , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); -REG64_FLD( PERV_1_HANG_PULSE_3_REG_3 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_3_REG_3 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_3 ); -REG64_FLD( PERV_1_HANG_PULSE_3_REG_3_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_3_REG_3_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_3_LEN ); -REG64_FLD( PERV_1_HANG_PULSE_3_REG_SUPPRESS , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_3_REG_SUPPRESS , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); -REG64_FLD( PERV_1_HANG_PULSE_4_REG_4 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_4_REG_4 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_4 ); -REG64_FLD( PERV_1_HANG_PULSE_4_REG_4_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_4_REG_4_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_4_LEN ); -REG64_FLD( PERV_1_HANG_PULSE_4_REG_SUPPRESS , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_4_REG_SUPPRESS , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); -REG64_FLD( PERV_1_HANG_PULSE_5_REG_5 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_5_REG_5 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_5 ); -REG64_FLD( PERV_1_HANG_PULSE_5_REG_5_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_5_REG_5_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_5_LEN ); -REG64_FLD( PERV_1_HANG_PULSE_5_REG_SUPPRESS , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_5_REG_SUPPRESS , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); -REG64_FLD( PERV_1_HANG_PULSE_6_REG_6 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_6_REG_6 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_6 ); -REG64_FLD( PERV_1_HANG_PULSE_6_REG_6_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_6_REG_6_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_6_LEN ); -REG64_FLD( PERV_1_HANG_PULSE_6_REG_SUPPRESS , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_HANG_PULSE_6_REG_SUPPRESS , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( PERV_1_HEARTBEAT_REG_DEAD , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_DEAD ); +REG64_FLD( PERV_1_HOSTATTN_IN0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN0 ); +REG64_FLD( PERV_1_HOSTATTN_IN1 , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN1 ); +REG64_FLD( PERV_1_HOSTATTN_IN2 , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN2 ); +REG64_FLD( PERV_1_HOSTATTN_IN3 , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN3 ); +REG64_FLD( PERV_1_HOSTATTN_IN4 , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN4 ); +REG64_FLD( PERV_1_HOSTATTN_IN5 , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN5 ); +REG64_FLD( PERV_1_HOSTATTN_IN6 , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN6 ); +REG64_FLD( PERV_1_HOSTATTN_IN7 , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN7 ); +REG64_FLD( PERV_1_HOSTATTN_IN8 , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN8 ); +REG64_FLD( PERV_1_HOSTATTN_IN9 , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN9 ); +REG64_FLD( PERV_1_HOSTATTN_IN10 , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN10 ); +REG64_FLD( PERV_1_HOSTATTN_IN11 , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN11 ); +REG64_FLD( PERV_1_HOSTATTN_IN12 , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN12 ); +REG64_FLD( PERV_1_HOSTATTN_IN13 , 13 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN13 ); +REG64_FLD( PERV_1_HOSTATTN_IN14 , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN14 ); +REG64_FLD( PERV_1_HOSTATTN_IN15 , 15 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN15 ); +REG64_FLD( PERV_1_HOSTATTN_IN16 , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN16 ); +REG64_FLD( PERV_1_HOSTATTN_IN17 , 17 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN17 ); +REG64_FLD( PERV_1_HOSTATTN_IN18 , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN18 ); +REG64_FLD( PERV_1_HOSTATTN_IN19 , 19 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN19 ); +REG64_FLD( PERV_1_HOSTATTN_IN20 , 20 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN20 ); +REG64_FLD( PERV_1_HOSTATTN_IN21 , 21 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN21 ); +REG64_FLD( PERV_1_HOSTATTN_IN22 , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN22 ); + +REG64_FLD( PERV_1_HOSTATTN_MASK_IN , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_IN ); +REG64_FLD( PERV_1_HOSTATTN_MASK_IN_LEN , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_IN_LEN ); + REG64_FLD( PERV_HOST_MASK_REG_IPOLL_0 , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_IPOLL_0 ); REG64_FLD( PERV_HOST_MASK_REG_IPOLL_1 , 1 , SH_UNT_PERV , SH_ACS_SCOM , @@ -2532,21 +3067,38 @@ REG64_FLD( PERV_INTERRUPT1_REG_INTERRUPT1 , 0 , SH_UN REG64_FLD( PERV_INTERRUPT1_REG_INTERRUPT1_LEN , 56 , SH_UNT_PERV , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT1_LEN ); -REG64_FLD( PERV_INTERRUPT2_REG_INTERRUPT2 , 32 , SH_UNT_PERV , SH_ACS_SCOM2_AND, +REG64_FLD( PERV_INTERRUPT2_REG_INTERRUPT2 , 0 , SH_UNT_PERV , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT2 ); -REG64_FLD( PERV_INTERRUPT2_REG_INTERRUPT2_LEN , 22 , SH_UNT_PERV , SH_ACS_SCOM2_AND, +REG64_FLD( PERV_INTERRUPT2_REG_INTERRUPT2_LEN , 56 , SH_UNT_PERV , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT2_LEN ); -REG64_FLD( PERV_INTERRUPT3_REG_INTERRUPT3 , 32 , SH_UNT_PERV , SH_ACS_SCOM2_AND, +REG64_FLD( PERV_INTERRUPT3_REG_INTERRUPT3 , 0 , SH_UNT_PERV , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT3 ); -REG64_FLD( PERV_INTERRUPT3_REG_INTERRUPT3_LEN , 23 , SH_UNT_PERV , SH_ACS_SCOM2_AND, +REG64_FLD( PERV_INTERRUPT3_REG_INTERRUPT3_LEN , 56 , SH_UNT_PERV , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT3_LEN ); -REG64_FLD( PERV_INTERRUPT4_REG_INTERRUPT4 , 32 , SH_UNT_PERV , SH_ACS_SCOM2_AND, +REG64_FLD( PERV_INTERRUPT4_REG_INTERRUPT4 , 0 , SH_UNT_PERV , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT4 ); -REG64_FLD( PERV_INTERRUPT4_REG_INTERRUPT4_LEN , 23 , SH_UNT_PERV , SH_ACS_SCOM2_AND, +REG64_FLD( PERV_INTERRUPT4_REG_INTERRUPT4_LEN , 56 , SH_UNT_PERV , SH_ACS_SCOM2_AND, SH_FLD_INTERRUPT4_LEN ); +REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_INVALID_CMD_0 , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_INVALID_CMD_0 ); +REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_LBUS_PARITY_ERROR_0 , 17 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_LBUS_PARITY_ERROR_0 ); +REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_BE_OV_ERROR_0 , 18 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_BE_OV_ERROR_0 ); +REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_BE_ACC_ERROR_0 , 19 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_BE_ACC_ERROR_0 ); +REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_ARBITRATION_LOST_ERROR_0 , 20 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_ARBITRATION_LOST_ERROR_0 ); +REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_NACK_RECEIVED_ERROR_0 , 21 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_NACK_RECEIVED_ERROR_0 ); +REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_DATA_REQUEST_0 , 22 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_DATA_REQUEST_0 ); +REG32_FLD( PERV_FSII2C_INTERRUPT_COND_A_STOP_ERROR_0 , 24 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_STOP_ERROR_0 ); + REG64_FLD( PERV_INTERRUPT_CONF_REG_UNUSED0 , 0 , SH_UNT_PERV , SH_ACS_SCOM2_WAND, SH_FLD_UNUSED0 ); REG64_FLD( PERV_INTERRUPT_CONF_REG_SEL0 , 1 , SH_UNT_PERV , SH_ACS_SCOM2_WAND, @@ -2573,10 +3125,15 @@ REG64_FLD( PERV_INTERRUPT_HOLD_REG_HOLD , 0 , SH_UN REG64_FLD( PERV_INTERRUPT_HOLD_REG_HOLD_LEN , 26 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_HOLD_LEN ); -REG32_FLD( PERV_FSII2C_INTERRUPT_MASK_REGISTER_INT , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM2_AND, - SH_FLD_INT ); -REG32_FLD( PERV_FSII2C_INTERRUPT_MASK_REGISTER_INT_LEN , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM2_AND, - SH_FLD_INT_LEN ); +REG32_FLD( PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_INT_0 , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM2_AND, + SH_FLD_INT_0 ); +REG32_FLD( PERV_FSII2C_INTERRUPT_MASK_REGISTER_A_INT_0_LEN , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM2_AND, + SH_FLD_INT_0_LEN ); + +REG32_FLD( PERV_FSII2C_INTERRUPT_MASK_REGISTER_READ_A_INT_0 , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_INT_0 ); +REG32_FLD( PERV_FSII2C_INTERRUPT_MASK_REGISTER_READ_A_INT_0_LEN , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_INT_0_LEN ); REG64_FLD( PERV_INTERRUPT_TYPE_MASK_REG_GP , 0 , SH_UNT_PERV , SH_ACS_SCOM2_WAND, SH_FLD_GP ); @@ -2713,16 +3270,18 @@ REG64_FLD( PERV_1_LOCAL_FIR_IN11 , 11 , SH_UN SH_FLD_IN11 ); REG64_FLD( PERV_1_LOCAL_FIR_IN12 , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_IN12 ); -REG64_FLD( PERV_1_LOCAL_FIR_IN12_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , - SH_FLD_IN12_LEN ); +REG64_FLD( PERV_1_LOCAL_FIR_IN13 , 13 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_IN13 ); REG64_FLD( PERV_1_LOCAL_FIR_IN14 , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_IN14 ); REG64_FLD( PERV_1_LOCAL_FIR_IN15 , 15 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_IN15 ); REG64_FLD( PERV_1_LOCAL_FIR_IN16 , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_IN16 ); -REG64_FLD( PERV_1_LOCAL_FIR_IN16_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , - SH_FLD_IN16_LEN ); +REG64_FLD( PERV_1_LOCAL_FIR_IN17 , 17 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_IN17 ); +REG64_FLD( PERV_1_LOCAL_FIR_IN18 , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_IN18 ); REG64_FLD( PERV_1_LOCAL_FIR_IN19 , 19 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_IN19 ); REG64_FLD( PERV_1_LOCAL_FIR_IN20 , 20 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , @@ -2731,8 +3290,8 @@ REG64_FLD( PERV_1_LOCAL_FIR_IN21 , 21 , SH_UN SH_FLD_IN21 ); REG64_FLD( PERV_1_LOCAL_FIR_IN22 , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_IN22 ); -REG64_FLD( PERV_1_LOCAL_FIR_IN22_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , - SH_FLD_IN22_LEN ); +REG64_FLD( PERV_1_LOCAL_FIR_IN23 , 23 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_IN23 ); REG64_FLD( PERV_1_LOCAL_FIR_IN24 , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_IN24 ); REG64_FLD( PERV_1_LOCAL_FIR_IN25 , 25 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , @@ -2745,22 +3304,26 @@ REG64_FLD( PERV_1_LOCAL_FIR_IN28 , 28 , SH_UN SH_FLD_IN28 ); REG64_FLD( PERV_1_LOCAL_FIR_IN29 , 29 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_IN29 ); -REG64_FLD( PERV_1_LOCAL_FIR_IN29_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , - SH_FLD_IN29_LEN ); +REG64_FLD( PERV_1_LOCAL_FIR_IN30 , 30 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_IN30 ); REG64_FLD( PERV_1_LOCAL_FIR_IN31 , 31 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_IN31 ); -REG64_FLD( PERV_1_LOCAL_FIR_IN31_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , - SH_FLD_IN31_LEN ); +REG64_FLD( PERV_1_LOCAL_FIR_IN32 , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_IN32 ); REG64_FLD( PERV_1_LOCAL_FIR_IN33 , 33 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_IN33 ); -REG64_FLD( PERV_1_LOCAL_FIR_IN33_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , - SH_FLD_IN33_LEN ); +REG64_FLD( PERV_1_LOCAL_FIR_IN34 , 34 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_IN34 ); REG64_FLD( PERV_1_LOCAL_FIR_IN35 , 35 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_IN35 ); REG64_FLD( PERV_1_LOCAL_FIR_IN36 , 36 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_IN36 ); -REG64_FLD( PERV_1_LOCAL_FIR_IN36_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , - SH_FLD_IN36_LEN ); +REG64_FLD( PERV_1_LOCAL_FIR_IN37 , 37 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_IN37 ); +REG64_FLD( PERV_1_LOCAL_FIR_IN38 , 38 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_IN38 ); +REG64_FLD( PERV_1_LOCAL_FIR_IN39 , 39 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_IN39 ); REG64_FLD( PERV_1_LOCAL_FIR_IN40 , 40 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_IN40 ); @@ -2779,6 +3342,56 @@ REG64_FLD( PERV_1_LOCAL_FIR_MASK_LFIR_IN , 0 , SH_UN REG64_FLD( PERV_1_LOCAL_FIR_MASK_LFIR_IN_LEN , 41 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , SH_FLD_LFIR_IN_LEN ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN0 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN1 , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN1 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN2 , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN2 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN3 , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN3 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN4 , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN4 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN5 , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN5 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN6 , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN6 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN7 , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN7 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN8 , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN8 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN9 , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN9 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN10 , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN10 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN11 , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN11 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN12 , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN12 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN13 , 13 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN13 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN14 , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN14 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN15 , 15 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN15 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN16 , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN16 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN17 , 17 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN17 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN18 , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN18 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN19 , 19 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN19 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN20 , 20 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN20 ); +REG64_FLD( PERV_1_LOCAL_XSTOP_ERR_IN21 , 21 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_IN21 ); + +REG64_FLD( PERV_1_LOCAL_XSTOP_MASK_IN , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_IN ); +REG64_FLD( PERV_1_LOCAL_XSTOP_MASK_IN_LEN , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_IN_LEN ); + REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_0_A_M1HC0A , 0 , SH_UNT_PERV , SH_ACS_SCOM_RW , SH_FLD_M1HC0A ); REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_0_A_M1HC0A_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM_RW , @@ -2809,12 +3422,12 @@ REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_2_B_M1HC2B , 0 , SH_UN REG64_FLD( PERV_MAILBOX_1_HEADER_COMMAND_2_B_M1HC2B_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM_RO , SH_FLD_M1HC2B_LEN ); -REG64_FLD( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_M1SASIM1_ENABLE_PIB_PENDING , 29 , SH_UNT_PERV , - SH_ACS_SCOM1_CLEAR, SH_FLD_M1SASIM1_ENABLE_PIB_PENDING ); +REG64_FLD( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_M1SASIM1_ENABLE_PIB_ERROR , 29 , SH_UNT_PERV , + SH_ACS_SCOM1_CLEAR, SH_FLD_M1SASIM1_ENABLE_PIB_ERROR ); REG64_FLD( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_M1SASIM1_ENABLE_XUP , 30 , SH_UNT_PERV , SH_ACS_SCOM1_CLEAR, SH_FLD_M1SASIM1_ENABLE_XUP ); -REG64_FLD( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_M1SASIM1_ENABLE_PIB_ERROR , 31 , SH_UNT_PERV , - SH_ACS_SCOM1_CLEAR, SH_FLD_M1SASIM1_ENABLE_PIB_ERROR ); +REG64_FLD( PERV_MAILBOX_1_SLAVE_A_DOORBELL_INTERRUPT_MASK_1_M1SASIM1_ENABLE_PIB_PENDING , 31 , SH_UNT_PERV , + SH_ACS_SCOM1_CLEAR, SH_FLD_M1SASIM1_ENABLE_PIB_PENDING ); REG64_FLD( PERV_MAILBOX_2_HEADER_COMMAND_0_A_M2HC0A , 0 , SH_UNT_PERV , SH_ACS_SCOM_RW , SH_FLD_M2HC0A ); @@ -2860,11 +3473,13 @@ REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_LBUS_B_RAM_PARITY_D SH_ACS_SCOM , SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_1 ); REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_1 , 8 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1 ); -REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_1_LEN , 6 , SH_UNT_PERV , +REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_1_LEN , 7 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1_LEN ); -REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_15_12 , 14 , SH_UNT_PERV , SH_ACS_SCOM , +REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_CLEAR_1 , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MSADES_CLEAR_1 ); +REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_15_12 , 16 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSADES_UNUSED_15_12 ); -REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_15_12_LEN , 6 , SH_UNT_PERV , +REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_UNUSED_15_12_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSADES_UNUSED_15_12_LEN ); REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ILLEGAL_OPERATION_ATTEMPTED_2 , 20 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_2 ); @@ -2876,12 +3491,10 @@ REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_LBUS_B_RAM_PARITY_D SH_ACS_SCOM , SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_2 ); REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_2 , 24 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2 ); -REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_2_LEN , 6 , SH_UNT_PERV , +REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_ADDRESS_OF_LBUS_PARITY_2_LEN , 7 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2_LEN ); -REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_1_0 , 30 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_MSBDES_UNUSED_1_0 ); -REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_1_0_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_MSBDES_UNUSED_1_0_LEN ); +REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_ERROR_STATUS_MSADES_CLEAR_2 , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MSADES_CLEAR_2 ); REG64_FLD( PERV_MAILBOX_SLAVE_A_DOORBELL_INTERRUPT_MSADI_UNUSED_31_11 , 11 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSADI_UNUSED_31_11 ); @@ -2918,12 +3531,14 @@ REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_PIB_A_RAM_PARITY_DE SH_ACS_SCOM , SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_1 ); REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_1 , 8 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1 ); -REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_1_LEN , 6 , SH_UNT_PERV , +REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_1_LEN , 7 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1_LEN ); -REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_17_12 , 14 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_MSBDES_UNUSED_17_12 ); -REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_17_12_LEN , 6 , SH_UNT_PERV , - SH_ACS_SCOM , SH_FLD_MSBDES_UNUSED_17_12_LEN ); +REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_CLEAR_1 , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MSBDES_CLEAR_1 ); +REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_15_12 , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MSBDES_UNUSED_15_12 ); +REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_15_12_LEN , 4 , SH_UNT_PERV , + SH_ACS_SCOM , SH_FLD_MSBDES_UNUSED_15_12_LEN ); REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_2 , 20 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_2 ); REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_WRITE_FULL_PIB_A_2 , 21 , SH_UNT_PERV , @@ -2934,25 +3549,23 @@ REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_PIB_A_RAM_PARITY_DE SH_ACS_SCOM , SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_2 ); REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_2 , 24 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2 ); -REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_2_LEN , 6 , SH_UNT_PERV , +REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_ADDRESS_OF_PIB_PARITY_2_LEN , 7 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2_LEN ); -REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_1_0 , 30 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_MSBDES_UNUSED_1_0 ); -REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_UNUSED_1_0_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_MSBDES_UNUSED_1_0_LEN ); +REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_ERROR_STATUS_MSBDES_CLEAR_2 , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MSBDES_CLEAR_2 ); -REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_PENDING_1 , 24 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_MSBDI_LBUS_PENDING_1 ); -REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_PENDING_2 , 25 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_MSBDI_LBUS_PENDING_2 ); -REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_XDN_1 , 26 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_MSBDI_XDN_1 ); -REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_XDN_2 , 27 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_MSBDI_XDN_2 ); -REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_ERROR_1 , 28 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_MSBDI_LBUS_ERROR_1 ); -REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_ERROR_2 , 29 , SH_UNT_PERV , SH_ACS_SCOM , +REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_ERROR_2 , 26 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_MSBDI_LBUS_ERROR_2 ); +REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_ERROR_1 , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MSBDI_LBUS_ERROR_1 ); +REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_XDN_2 , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MSBDI_XDN_2 ); +REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_XDN_1 , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MSBDI_XDN_1 ); +REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_PENDING_2 , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MSBDI_LBUS_PENDING_2 ); +REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MSBDI_LBUS_PENDING_1 , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_MSBDI_LBUS_PENDING_1 ); REG64_FLD( PERV_MAILBOX_SLAVE_B_DOORBELL_INTERRUPT_MASK_1_MSBDIM1_ENABLE_LBUS_PENDING , 24 , SH_UNT_PERV , SH_ACS_SCOM_RO , SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING ); @@ -3027,8 +3640,6 @@ REG64_FLD( PERV_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UN SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PERV_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT_PERV , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); -REG64_FLD( PERV_MIB_XIICAC_XISIB_PIB_IFETCH_PENDING , 34 , SH_UNT_PERV , SH_ACS_SCOM_RO , - SH_FLD_XISIB_PIB_IFETCH_PENDING ); REG64_FLD( PERV_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT_PERV , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PERV_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT_PERV , SH_ACS_SCOM_RO , @@ -3074,25 +3685,6 @@ REG64_FLD( PERV_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UN REG64_FLD( PERV_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT_PERV , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); -REG64_FLD( PERV_MIB_XISIB_PIB_ADDR , 0 , SH_UNT_PERV , SH_ACS_SCOM_RO , - SH_FLD_PIB_ADDR ); -REG64_FLD( PERV_MIB_XISIB_PIB_ADDR_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM_RO , - SH_FLD_PIB_ADDR_LEN ); -REG64_FLD( PERV_MIB_XISIB_PIB_R_NW , 32 , SH_UNT_PERV , SH_ACS_SCOM_RO , - SH_FLD_PIB_R_NW ); -REG64_FLD( PERV_MIB_XISIB_PIB_BUSY , 33 , SH_UNT_PERV , SH_ACS_SCOM_RO , - SH_FLD_PIB_BUSY ); -REG64_FLD( PERV_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING , 34 , SH_UNT_PERV , SH_ACS_SCOM_RO , - SH_FLD_PIB_IMPRECISE_ERROR_PENDING ); -REG64_FLD( PERV_MIB_XISIB_PIB_RSP_INFO , 49 , SH_UNT_PERV , SH_ACS_SCOM_RO , - SH_FLD_PIB_RSP_INFO ); -REG64_FLD( PERV_MIB_XISIB_PIB_RSP_INFO_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM_RO , - SH_FLD_PIB_RSP_INFO_LEN ); -REG64_FLD( PERV_MIB_XISIB_PIB_IFETCH_PENDING , 62 , SH_UNT_PERV , SH_ACS_SCOM_RO , - SH_FLD_PIB_IFETCH_PENDING ); -REG64_FLD( PERV_MIB_XISIB_PIB_DATAOP_PENDING , 63 , SH_UNT_PERV , SH_ACS_SCOM_RO , - SH_FLD_PIB_DATAOP_PENDING ); - REG64_FLD( PERV_1_MODE_REG_IN0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( PERV_1_MODE_REG_IN1 , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -3122,24 +3714,24 @@ REG64_FLD( PERV_1_MODE_REG_IN , 12 , SH_UN REG64_FLD( PERV_1_MODE_REG_IN_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_IN_LEN ); -REG32_FLD( PERV_FSII2C_MODE_REGISTER_BIT_RATE_DIVISOR , 0 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , - SH_FLD_BIT_RATE_DIVISOR ); -REG32_FLD( PERV_FSII2C_MODE_REGISTER_BIT_RATE_DIVISOR_LEN , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , - SH_FLD_BIT_RATE_DIVISOR_LEN ); -REG32_FLD( PERV_FSII2C_MODE_REGISTER_PORT_NUMBER , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , - SH_FLD_PORT_NUMBER ); -REG32_FLD( PERV_FSII2C_MODE_REGISTER_PORT_NUMBER_LEN , 6 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , - SH_FLD_PORT_NUMBER_LEN ); -REG32_FLD( PERV_FSII2C_MODE_REGISTER_CHKSW_I2C_BUSY , 27 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , - SH_FLD_CHKSW_I2C_BUSY ); -REG32_FLD( PERV_FSII2C_MODE_REGISTER_FGAT , 28 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , - SH_FLD_FGAT ); -REG32_FLD( PERV_FSII2C_MODE_REGISTER_DIAG , 29 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , - SH_FLD_DIAG ); -REG32_FLD( PERV_FSII2C_MODE_REGISTER_PACING_ALLOW , 30 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , - SH_FLD_PACING_ALLOW ); -REG32_FLD( PERV_FSII2C_MODE_REGISTER_WRAP , 31 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , - SH_FLD_WRAP ); +REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_BIT_RATE_DIVISOR_0 , 10 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_BIT_RATE_DIVISOR_0 ); +REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_BIT_RATE_DIVISOR_0_LEN , 6 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_BIT_RATE_DIVISOR_0_LEN ); +REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_PORT_NUMBER_0 , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_PORT_NUMBER_0 ); +REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_PORT_NUMBER_0_LEN , 6 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_PORT_NUMBER_0_LEN ); +REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_CHKSW_I2C_BUSY_0 , 27 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_CHKSW_I2C_BUSY_0 ); +REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_FGAT_0 , 28 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_FGAT_0 ); +REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_DIAG_0 , 29 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_DIAG_0 ); +REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_PACING_ALLOW_0 , 30 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_PACING_ALLOW_0 ); +REG32_FLD( PERV_FSII2C_MODE_REGISTER_A_WRAP_0 , 31 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_WRAP_0 ); REG64_FLD( PERV_1_MULTICAST_GROUP_1_MULTICAST1 , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_MULTICAST1 ); @@ -3177,10 +3769,12 @@ REG64_FLD( PERV_1_NET_CTRL0_VITAL_SCAN , 6 , SH_UN SH_FLD_VITAL_SCAN ); REG64_FLD( PERV_1_NET_CTRL0_VITAL_SCAN_IN , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_SCAN_IN ); +REG64_FLD( PERV_1_NET_CTRL0_VITAL_PHASE , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_VITAL_PHASE ); REG64_FLD( PERV_1_NET_CTRL0_FLUSH_ALIGN_OVR , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_FLUSH_ALIGN_OVR ); -REG64_FLD( PERV_1_NET_CTRL0_ARRAY_WRITE_ASSIST_EN , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, - SH_FLD_ARRAY_WRITE_ASSIST_EN ); +REG64_FLD( PERV_1_NET_CTRL0_VITAL_AL , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_VITAL_AL ); REG64_FLD( PERV_1_NET_CTRL0_ACT_DIS , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_ACT_DIS ); REG64_FLD( PERV_1_NET_CTRL0_MPW1 , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, @@ -3197,18 +3791,20 @@ REG64_FLD( PERV_1_NET_CTRL0_FLUSH_SCAN_N , 17 , SH_UN SH_FLD_FLUSH_SCAN_N ); REG64_FLD( PERV_1_NET_CTRL0_FENCE_EN , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_FENCE_EN ); -REG64_FLD( PERV_1_NET_CTRL0_RI_N , 19 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, - SH_FLD_RI_N ); -REG64_FLD( PERV_1_NET_CTRL0_DI1_N , 20 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, - SH_FLD_DI1_N ); -REG64_FLD( PERV_1_NET_CTRL0_DI2_N , 21 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, - SH_FLD_DI2_N ); +REG64_FLD( PERV_1_NET_CTRL0_CPLT_RCTRL , 19 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_CPLT_RCTRL ); +REG64_FLD( PERV_1_NET_CTRL0_CPLT_DCTRL , 20 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_CPLT_DCTRL ); +REG64_FLD( PERV_1_NET_CTRL0_L3_EDRAM_ENABLE0 , 23 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_L3_EDRAM_ENABLE0 ); +REG64_FLD( PERV_1_NET_CTRL0_L3_EDRAM_ENABLE1 , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_L3_EDRAM_ENABLE1 ); REG64_FLD( PERV_1_NET_CTRL0_TP_FENCE_PCB , 25 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_TP_FENCE_PCB ); REG64_FLD( PERV_1_NET_CTRL0_LVLTRANS_FENCE , 26 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_LVLTRANS_FENCE ); -REG64_FLD( PERV_1_NET_CTRL0_L3_EDRAM_ENABLE , 27 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, - SH_FLD_L3_EDRAM_ENABLE ); +REG64_FLD( PERV_1_NET_CTRL0_ARRAY_WRITE_ASSIST_EN , 27 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_ARRAY_WRITE_ASSIST_EN ); REG64_FLD( PERV_1_NET_CTRL0_HTB_INTEST , 28 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_HTB_INTEST ); REG64_FLD( PERV_1_NET_CTRL0_HTB_EXTEST , 29 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, @@ -3216,24 +3812,335 @@ REG64_FLD( PERV_1_NET_CTRL0_HTB_EXTEST , 29 , SH_UN REG64_FLD( PERV_1_NET_CTRL1_PLL_CLKIN_SEL , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_PLL_CLKIN_SEL ); -REG64_FLD( PERV_1_NET_CTRL1_CLK_DIV_BYPASS_EN , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, - SH_FLD_CLK_DIV_BYPASS_EN ); +REG64_FLD( PERV_1_NET_CTRL1_CLK_DCC_BYPASS_EN , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_CLK_DCC_BYPASS_EN ); REG64_FLD( PERV_1_NET_CTRL1_CLK_PDLY_BYPASS_EN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PDLY_BYPASS_EN ); +REG64_FLD( PERV_1_NET_CTRL1_CLK_DIV_BYPASS_EN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_CLK_DIV_BYPASS_EN ); +REG64_FLD( PERV_1_NET_CTRL1_REFCLK_CLKMUX0_SEL , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_REFCLK_CLKMUX0_SEL ); +REG64_FLD( PERV_1_NET_CTRL1_REFCLK_CLKMUX1_SEL , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_REFCLK_CLKMUX1_SEL ); +REG64_FLD( PERV_1_NET_CTRL1_PLL_BNDY_BYPASS_EN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_PLL_BNDY_BYPASS_EN ); +REG64_FLD( PERV_1_NET_CTRL1_DPLL_TEST_SEL , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_DPLL_TEST_SEL ); +REG64_FLD( PERV_1_NET_CTRL1_DPLL_TEST_SEL_LEN , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_DPLL_TEST_SEL_LEN ); REG64_FLD( PERV_1_NET_CTRL1_SB_STRENGTH , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_SB_STRENGTH ); REG64_FLD( PERV_1_NET_CTRL1_SB_STRENGTH_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_SB_STRENGTH_LEN ); +REG64_FLD( PERV_1_NET_CTRL1_ASYNC_TYPE , 20 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_ASYNC_TYPE ); +REG64_FLD( PERV_1_NET_CTRL1_ASYNC_OBS , 21 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_ASYNC_OBS ); +REG64_FLD( PERV_1_NET_CTRL1_CPM_CAL_SET , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, + SH_FLD_CPM_CAL_SET ); REG64_FLD( PERV_1_NET_CTRL1_CLK_PULSE_EN , 25 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_EN ); REG64_FLD( PERV_1_NET_CTRL1_CLK_PULSE_MODE , 26 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE ); REG64_FLD( PERV_1_NET_CTRL1_CLK_PULSE_MODE_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE_LEN ); -REG64_FLD( PERV_1_NET_CTRL1_RESCLK_DIS , 28 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, - SH_FLD_RESCLK_DIS ); -REG64_FLD( PERV_1_NET_CTRL1_CPM_CAL_SET , 29 , SH_UNT_PERV_1 , SH_ACS_SCOM2_WOR, - SH_FLD_CPM_CAL_SET ); + +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_SRAM_CERRRPT , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_SRAM_CERRRPT ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_SRAM_CERRRPT_LEN , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_SRAM_CERRRPT_LEN ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_JTAGACC_CERRPT , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_JTAGACC_CERRPT ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_JTAGACC_CERRPT_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_JTAGACC_CERRPT_LEN ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_C405_DCU_ECC_UE , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_C405_DCU_ECC_UE ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_C405_DCU_ECC_CE , 17 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_C405_DCU_ECC_CE ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_C405_ICU_ECC_UE , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_C405_ICU_ECC_UE ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_C405_ICU_ECC_CE , 19 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_C405_ICU_ECC_CE ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE0_OCISLV_ERR , 20 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_GPE0_OCISLV_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE0_OCISLV_ERR_LEN , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_GPE0_OCISLV_ERR_LEN ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE1_OCISLV_ERR , 28 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_GPE1_OCISLV_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE1_OCISLV_ERR_LEN , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_GPE1_OCISLV_ERR_LEN ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE2_OCISLV_ERR , 36 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_GPE2_OCISLV_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE2_OCISLV_ERR_LEN , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_GPE2_OCISLV_ERR_LEN ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE3_OCISLV_ERR , 44 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_GPE3_OCISLV_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_GPE3_OCISLV_ERR_LEN , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_GPE3_OCISLV_ERR_LEN ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_OCB_OCISLV_ERR , 52 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_OCB_OCISLV_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCERRRPT_OCB_OCISLV_ERR_LEN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM_WCLRPART, + SH_FLD_OCB_OCISLV_ERR_LEN ); + +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_FW0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_FW0 ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_FW1 , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_FW1 ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_CME_ERROR_NOTIFY , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_CME_ERROR_NOTIFY ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_STOP_RECOVERY_NOTIFY_PRD , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_STOP_RECOVERY_NOTIFY_PRD ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_HB_ERROR , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_HB_ERROR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE0_WATCHDOG_TIMEOUT , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE0_WATCHDOG_TIMEOUT ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE1_WATCHDOG_TIMEOUT , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE1_WATCHDOG_TIMEOUT ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE2_WATCHDOG_TIMEOUT , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE2_WATCHDOG_TIMEOUT ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE3_WATCHDOG_TIMEOUT , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE3_WATCHDOG_TIMEOUT ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE0_ERROR , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE0_ERROR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE1_ERROR , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE1_ERROR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE2_ERROR , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE2_ERROR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE3_ERROR , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE3_ERROR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_ERROR , 13 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_ERROR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_UE , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_UE ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_CE , 15 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_CE ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_READ_ERROR , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_READ_ERROR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_WRITE_ERROR , 17 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_WRITE_ERROR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_DATAOUT_PERR , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_DATAOUT_PERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_OCI_WRITE_DATA_PARITY , 19 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_OCI_WRITE_DATA_PARITY ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_OCI_BE_PARITY_ERR , 20 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_OCI_BE_PARITY_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_OCI_ADDR_PARITY_ERR , 21 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_OCI_ADDR_PARITY_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE0_HALTED , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE0_HALTED ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE1_HALTED , 23 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE1_HALTED ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE2_HALTED , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE2_HALTED ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE3_HALTED , 25 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE3_HALTED ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_EXTERNAL_TRAP , 26 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_EXTERNAL_TRAP ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_PPC405_CORE_RESET , 27 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_PPC405_CORE_RESET ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_PPC405_CHIP_RESET , 28 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_PPC405_CHIP_RESET ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_PPC405_SYSTEM_RESET , 29 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_PPC405_SYSTEM_RESET ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_PPC405_DBGMSRWE , 30 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_PPC405_DBGMSRWE ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_PPC405_DBGSTOPACK , 31 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_PPC405_DBGSTOPACK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_DB_OCI_TIMEOUT , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_DB_OCI_TIMEOUT ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_DB_OCI_READ_DATA_PARITY , 33 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_DB_OCI_READ_DATA_PARITY ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_DB_OCI_SLAVE_ERROR , 34 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_DB_OCI_SLAVE_ERROR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_PIB_ADDR_PARITY_ERR , 35 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_PIB_ADDR_PARITY_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_DB_PIB_DATA_PARITY_ERR , 36 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_DB_PIB_DATA_PARITY_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_IDC0_ERROR , 37 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_IDC0_ERROR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_IDC1_ERROR , 38 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_IDC1_ERROR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_IDC2_ERROR , 39 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_IDC2_ERROR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_OCB_IDC3_ERROR , 40 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_IDC3_ERROR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRT_FSM_ERR , 41 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_FSM_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_JTAGACC_ERR , 42 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_JTAGACC_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SPARE_ERR_38 , 43 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_ERR_38 ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_C405_ECC_UE , 44 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_C405_ECC_UE ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_C405_ECC_CE , 45 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_C405_ECC_CE ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_C405_OCI_MACHINECHECK , 46 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_C405_OCI_MACHINECHECK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRAM_SPARE_DIRECT_ERROR0 , 47 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_SPARE_DIRECT_ERROR0 ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRAM_SPARE_DIRECT_ERROR1 , 48 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_SPARE_DIRECT_ERROR1 ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRAM_SPARE_DIRECT_ERROR2 , 49 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_SPARE_DIRECT_ERROR2 ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SRAM_SPARE_DIRECT_ERROR3 , 50 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_SPARE_DIRECT_ERROR3 ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE0_OCISLV_ERR , 51 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE0_OCISLV_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE1_OCISLV_ERR , 52 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE1_OCISLV_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE2_OCISLV_ERR , 53 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE2_OCISLV_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_GPE3_OCISLV_ERR , 54 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE3_OCISLV_ERR ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_C405ICU_M_TIMEOUT , 55 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_C405ICU_M_TIMEOUT ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_C405DCU_M_TIMEOUT , 56 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_C405DCU_M_TIMEOUT ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_COMPLEX_FAULT_SAFE , 57 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_COMPLEX_FAULT_SAFE ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SPARE_58_61 , 59 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_58_61 ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_SPARE_58_61_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_58_61_LEN ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_FIR_PARITY_ERR_DUP , 62 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_FIR_PARITY_ERR_DUP ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIR_FIR_PARITY_ERR , 63 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_FIR_PARITY_ERR ); + +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRACT0_FIR_ACTION0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , + SH_FLD_FIR_ACTION0 ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRACT0_FIR_ACTION0_LEN , 64 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , + SH_FLD_FIR_ACTION0_LEN ); + +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRACT1_FIR_ACTION1 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , + SH_FLD_FIR_ACTION1 ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRACT1_FIR_ACTION1_LEN , 64 , SH_UNT_PERV_1 , SH_ACS_SCOM_RW , + SH_FLD_FIR_ACTION1_LEN ); + +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_FW0_MASK , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_FW0_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_FW1_MASK , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_FW1_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_2_MASK , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_2_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_3_MASK , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_3_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_HB_MALF_MASK , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_HB_MALF_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE0_WATCHDOG_TIMEOUT_MASK , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE0_WATCHDOG_TIMEOUT_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE1_WATCHDOG_TIMEOUT_MASK , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE1_WATCHDOG_TIMEOUT_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE2_WATCHDOG_TIMEOUT_MASK , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE2_WATCHDOG_TIMEOUT_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE3_WATCHDOG_TIMEOUT_MASK , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE3_WATCHDOG_TIMEOUT_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE0_ERROR_MASK , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE0_ERROR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE1_ERROR_MASK , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE1_ERROR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE2_ERROR_MASK , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE2_ERROR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE3_ERROR_MASK , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE3_ERROR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_ERROR_MASK , 13 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_ERROR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_UE_MASK , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_UE_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_CE_MASK , 15 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_CE_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_READ_ERROR_MASK , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_READ_ERROR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_WRITE_ERROR_MASK , 17 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_WRITE_ERROR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_DATAOUT_PERR_MASK , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_DATAOUT_PERR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_OCI_WRITE_DATA_PARITY_MASK , 19 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_OCI_WRITE_DATA_PARITY_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_OCI_BE_PARITY_ERR_MASK , 20 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_OCI_BE_PARITY_ERR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_OCI_ADDR_PARITY_ERR_MASK , 21 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_OCI_ADDR_PARITY_ERR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE0_HALTED_MASK , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE0_HALTED_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE1_HALTED_MASK , 23 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE1_HALTED_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE2_HALTED_MASK , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE2_HALTED_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE3_HALTED_MASK , 25 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE3_HALTED_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_EXTERNAL_TRAP_MASK , 26 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_EXTERNAL_TRAP_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_CORE_RESET_MASK , 27 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_PPC405_CORE_RESET_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_CHIP_RESET_MASK , 28 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_PPC405_CHIP_RESET_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_SYSTEM_RESET_MASK , 29 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_PPC405_SYSTEM_RESET_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_DBGMSRWE_MASK , 30 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_PPC405_DBGMSRWE_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_PPC405_DBGSTOPACK_MASK , 31 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_PPC405_DBGSTOPACK_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_DB_OCI_TIMEOUT_MASK , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_DB_OCI_TIMEOUT_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_DB_OCI_READ_DATA_PARITY_MASK , 33 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_DB_OCI_READ_DATA_PARITY_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_DB_OCI_SLAVE_ERROR_MASK , 34 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_DB_OCI_SLAVE_ERROR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_PIB_ADDR_PARITY_ERR_MASK , 35 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_PIB_ADDR_PARITY_ERR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_DB_PIB_DATA_PARITY_ERR_MASK , 36 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_DB_PIB_DATA_PARITY_ERR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_IDC0_ERROR_MASK , 37 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_IDC0_ERROR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_IDC1_ERROR_MASK , 38 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_IDC1_ERROR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_IDC2_ERROR_MASK , 39 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_IDC2_ERROR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_OCB_IDC3_ERROR_MASK , 40 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_OCB_IDC3_ERROR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRT_FSM_ERR_MASK , 41 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRT_FSM_ERR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_JTAGACC_ERR_MASK , 42 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_JTAGACC_ERR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_ERR_38_MASK , 43 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_ERR_38_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_C405_ECC_UE_MASK , 44 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_C405_ECC_UE_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_C405_ECC_CE_MASK , 45 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_C405_ECC_CE_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_C405_OCI_MACHINECHECK_MASK , 46 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_C405_OCI_MACHINECHECK_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRAM_SPARE_DIRECT_ERROR0_MASK , 47 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_SPARE_DIRECT_ERROR0_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRAM_SPARE_DIRECT_ERROR1_MASK , 48 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_SPARE_DIRECT_ERROR1_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRAM_SPARE_DIRECT_ERROR2_MASK , 49 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_SPARE_DIRECT_ERROR2_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SRAM_SPARE_DIRECT_ERROR3_MASK , 50 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SRAM_SPARE_DIRECT_ERROR3_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE0_OCISLV_ERR_MASK , 51 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE0_OCISLV_ERR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE1_OCISLV_ERR_MASK , 52 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE1_OCISLV_ERR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE2_OCISLV_ERR_MASK , 53 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE2_OCISLV_ERR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_GPE3_OCISLV_ERR_MASK , 54 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_GPE3_OCISLV_ERR_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_C405ICU_M_TIMEOUT_MASK , 55 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_C405ICU_M_TIMEOUT_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_C405DCU_M_TIMEOUT_MASK , 56 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_C405DCU_M_TIMEOUT_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_COMPLEX_FAULT_SAFE_MASK , 57 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_COMPLEX_FAULT_SAFE_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_58_61_MASK , 58 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_58_61_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_SPARE_58_61_MASK_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_SPARE_58_61_MASK_LEN ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_FIR_PARITY_ERR_DUP_MASK , 62 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_FIR_PARITY_ERR_DUP_MASK ); +REG64_FLD( PERV_1_OCC_SCOM_OCCLFIRMASK_FIR_PARITY_ERR_MASK , 63 , SH_UNT_PERV_1 , SH_ACS_SCOM2_OR , + SH_FLD_FIR_PARITY_ERR_MASK ); REG64_FLD( PERV_1_OPCG_ALIGN_INOP , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_INOP ); @@ -3455,10 +4362,10 @@ REG64_FLD( PERV_1_OPCG_REG0_IN_MASTER_MODE , 5 , SH_UN SH_FLD_IN_MASTER_MODE ); REG64_FLD( PERV_1_OPCG_REG0_KEEP_MS_MODE , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_KEEP_MS_MODE ); -REG64_FLD( PERV_1_OPCG_REG0_UNUSED78 , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_UNUSED78 ); -REG64_FLD( PERV_1_OPCG_REG0_UNUSED78_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_UNUSED78_LEN ); +REG64_FLD( PERV_1_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL ); +REG64_FLD( PERV_1_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL ); REG64_FLD( PERV_1_OPCG_REG0_RUN_CHIPLET_SCAN0 , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_RUN_CHIPLET_SCAN0 ); REG64_FLD( PERV_1_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -3502,16 +4409,18 @@ REG64_FLD( PERV_1_OPCG_REG1_SCAN_CLK_USE_EVEN , 49 , SH_UN SH_FLD_SCAN_CLK_USE_EVEN ); REG64_FLD( PERV_1_OPCG_REG1_UNUSED2 , 50 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_UNUSED2 ); -REG64_FLD( PERV_1_OPCG_REG1_UNUSED2_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_OPCG_REG1_UNUSED2_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_UNUSED2_LEN ); +REG64_FLD( PERV_1_OPCG_REG1_RTIM_THOLD_FORCE , 52 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RTIM_THOLD_FORCE ); REG64_FLD( PERV_1_OPCG_REG1_USE_ARY_CLK_DURING_FILL , 53 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_USE_ARY_CLK_DURING_FILL ); REG64_FLD( PERV_1_OPCG_REG1_SG_HIGH_DURING_FILL , 54 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_SG_HIGH_DURING_FILL ); -REG64_FLD( PERV_1_OPCG_REG1_RTIM_THOLD_FORCE , 55 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_RTIM_THOLD_FORCE ); -REG64_FLD( PERV_1_OPCG_REG1_LBIST_SKITTER_CTL , 56 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_OPCG_REG1_LBIST_SKITTER_CTL , 55 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_LBIST_SKITTER_CTL ); +REG64_FLD( PERV_1_OPCG_REG1_LBIST_SKITTER_CTL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_LBIST_SKITTER_CTL_LEN ); REG64_FLD( PERV_1_OPCG_REG1_MISR_MODE , 57 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_MISR_MODE ); REG64_FLD( PERV_1_OPCG_REG1_INFINITE_MODE , 58 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -3616,6 +4525,48 @@ REG64_FLD( PERV_PB_PSAVE_CFG_HUT , 32 , SH_UN REG64_FLD( PERV_PB_PSAVE_CFG_HUT_LEN , 8 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_HUT_LEN ); +REG64_FLD( PERV_PB_PSAVE_MON_CFG_X0_LO , 3 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_X0_LO ); +REG64_FLD( PERV_PB_PSAVE_MON_CFG_X0_LO_LEN , 5 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_X0_LO_LEN ); +REG64_FLD( PERV_PB_PSAVE_MON_CFG_X0_HI , 11 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_X0_HI ); +REG64_FLD( PERV_PB_PSAVE_MON_CFG_X0_HI_LEN , 5 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_X0_HI_LEN ); +REG64_FLD( PERV_PB_PSAVE_MON_CFG_X1_LO , 19 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_X1_LO ); +REG64_FLD( PERV_PB_PSAVE_MON_CFG_X1_LO_LEN , 5 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_X1_LO_LEN ); +REG64_FLD( PERV_PB_PSAVE_MON_CFG_X1_HI , 27 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_X1_HI ); +REG64_FLD( PERV_PB_PSAVE_MON_CFG_X1_HI_LEN , 5 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_X1_HI_LEN ); +REG64_FLD( PERV_PB_PSAVE_MON_CFG_X2_LO , 35 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_X2_LO ); +REG64_FLD( PERV_PB_PSAVE_MON_CFG_X2_LO_LEN , 5 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_X2_LO_LEN ); +REG64_FLD( PERV_PB_PSAVE_MON_CFG_X2_HI , 43 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_X2_HI ); +REG64_FLD( PERV_PB_PSAVE_MON_CFG_X2_HI_LEN , 5 , SH_UNT_PERV , SH_ACS_SCOM_RW , + SH_FLD_X2_HI_LEN ); + +REG64_FLD( PERV_PB_PSAVE_X0_HIST_F0_LUT_HISTORY , 0 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_F0_LUT_HISTORY ); +REG64_FLD( PERV_PB_PSAVE_X0_HIST_F0_LUT_HISTORY_LEN , 16 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_F0_LUT_HISTORY_LEN ); +REG64_FLD( PERV_PB_PSAVE_X0_HIST_F0_HUT_HISTORY , 16 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_F0_HUT_HISTORY ); +REG64_FLD( PERV_PB_PSAVE_X0_HIST_F0_HUT_HISTORY_LEN , 16 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_F0_HUT_HISTORY_LEN ); +REG64_FLD( PERV_PB_PSAVE_X0_HIST_F1_LUT_HISTORY , 32 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_F1_LUT_HISTORY ); +REG64_FLD( PERV_PB_PSAVE_X0_HIST_F1_LUT_HISTORY_LEN , 16 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_F1_LUT_HISTORY_LEN ); +REG64_FLD( PERV_PB_PSAVE_X0_HIST_F1_HUT_HISTORY , 48 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_F1_HUT_HISTORY ); +REG64_FLD( PERV_PB_PSAVE_X0_HIST_F1_HUT_HISTORY_LEN , 16 , SH_UNT_PERV , SH_ACS_SCOM_RO , + SH_FLD_F1_HUT_HISTORY_LEN ); + REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_ACTUAL_ERROR , 4 , SH_UNT_PERV , SH_ACS_FSI , SH_FLD_FSI_A_MST_0_ACTUAL_ERROR ); REG32_FLD( PERV_PEEK4A0_FSI_A_MST_0_ACTUAL_ERROR_LEN , 4 , SH_UNT_PERV , SH_ACS_FSI , @@ -3739,6 +4690,136 @@ REG64_FLD( PERV_PERV_CTRL0_30_RESERVED_FOR_HTB , 30 , SH_UN REG64_FLD( PERV_PERV_CTRL0_31_RESERVED_FOR_HTB , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_31_RESERVED_FOR_HTB ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_CHIPLET_EN_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CHIPLET_EN_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_PCB_EP_RESET_DC , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PCB_EP_RESET_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_2_RESERVED , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_2_RESERVED ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_PLL_TEST_EN_DC , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_TEST_EN_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_PLLRST_DC , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLLRST_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_PLLBYP_DC , 5 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLLBYP_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_SCAN_CLK_DC , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_SCAN_CLK_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_SCIN_DC , 7 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_SCIN_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_8_RESERVED , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_8_RESERVED ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_FLUSH_ALIGN_OVERWRITE , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FLUSH_ALIGN_OVERWRITE ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_ARRAY_WRITE_ASSIST_EN_DC , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_ARRAY_WRITE_ASSIST_EN_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_ACT_DIS_DC , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_ACT_DIS_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_MPW1_DC_N , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_MPW1_DC_N ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_MPW2_DC_N , 13 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_MPW2_DC_N ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_MPW3_DC_N , 14 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_MPW3_DC_N ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_DELAY_LCLKR_DC , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_DELAY_LCLKR_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_VITL_CLKOFF_DC , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_CLKOFF_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_FLUSH_SCAN_DC_N , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FLUSH_SCAN_DC_N ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_FENCE_EN_DC , 18 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FENCE_EN_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_RI_DC_N , 19 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_RI_DC_N ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_DI1_DC_N , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_DI1_DC_N ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_DI2_DC_N , 21 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_DI2_DC_N ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_22_RESERVED , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_22_RESERVED ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_23_RESERVED , 23 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_23_RESERVED ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_24_RESERVED , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_24_RESERVED ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_FENCE_PCB_DC , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FENCE_PCB_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_LVLTRANS_FENCE_DC , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_LVLTRANS_FENCE_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_TP_EDRAM_ENABLE_DC , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_EDRAM_ENABLE_DC ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_28_RESERVED_FOR_HTB , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_28_RESERVED_FOR_HTB ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_29_RESERVED_FOR_HTB , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_29_RESERVED_FOR_HTB ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_30_RESERVED_FOR_HTB , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_30_RESERVED_FOR_HTB ); +REG64_FLD( PERV_PERV_CTRL0_CLEAR_31_RESERVED_FOR_HTB , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_31_RESERVED_FOR_HTB ); + +REG64_FLD( PERV_PERV_CTRL0_SET_TP_CHIPLET_EN_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CHIPLET_EN_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_PCB_EP_RESET_DC , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PCB_EP_RESET_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_2_RESERVED , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_2_RESERVED ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_PLL_TEST_EN_DC , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_TEST_EN_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_PLLRST_DC , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLLRST_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_PLLBYP_DC , 5 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLLBYP_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_SCAN_CLK_DC , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_SCAN_CLK_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_SCIN_DC , 7 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_SCIN_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_8_RESERVED , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_8_RESERVED ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_FLUSH_ALIGN_OVERWRITE , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FLUSH_ALIGN_OVERWRITE ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_ARRAY_WRITE_ASSIST_EN_DC , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_ARRAY_WRITE_ASSIST_EN_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_ACT_DIS_DC , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_ACT_DIS_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_MPW1_DC_N , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_MPW1_DC_N ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_MPW2_DC_N , 13 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_MPW2_DC_N ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_MPW3_DC_N , 14 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_MPW3_DC_N ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_DELAY_LCLKR_DC , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_DELAY_LCLKR_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_VITL_CLKOFF_DC , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_VITL_CLKOFF_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_FLUSH_SCAN_DC_N , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FLUSH_SCAN_DC_N ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_FENCE_EN_DC , 18 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FENCE_EN_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_RI_DC_N , 19 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_RI_DC_N ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_DI1_DC_N , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_DI1_DC_N ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_DI2_DC_N , 21 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_DI2_DC_N ); +REG64_FLD( PERV_PERV_CTRL0_SET_22_RESERVED , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_22_RESERVED ); +REG64_FLD( PERV_PERV_CTRL0_SET_23_RESERVED , 23 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_23_RESERVED ); +REG64_FLD( PERV_PERV_CTRL0_SET_24_RESERVED , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_24_RESERVED ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_FENCE_PCB_DC , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FENCE_PCB_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_LVLTRANS_FENCE_DC , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_LVLTRANS_FENCE_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_TP_EDRAM_ENABLE_DC , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_EDRAM_ENABLE_DC ); +REG64_FLD( PERV_PERV_CTRL0_SET_28_RESERVED_FOR_HTB , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_28_RESERVED_FOR_HTB ); +REG64_FLD( PERV_PERV_CTRL0_SET_29_RESERVED_FOR_HTB , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_29_RESERVED_FOR_HTB ); +REG64_FLD( PERV_PERV_CTRL0_SET_30_RESERVED_FOR_HTB , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_30_RESERVED_FOR_HTB ); +REG64_FLD( PERV_PERV_CTRL0_SET_31_RESERVED_FOR_HTB , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_31_RESERVED_FOR_HTB ); + REG64_FLD( PERV_PERV_CTRL1_UNUSED1 , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_UNUSED1 ); REG64_FLD( PERV_PERV_CTRL1_UNUSED2 , 1 , SH_UNT_PERV , SH_ACS_SCOM , @@ -3800,6 +4881,128 @@ REG64_FLD( PERV_PERV_CTRL1_30_RESERVED , 30 , SH_UN REG64_FLD( PERV_PERV_CTRL1_TP_PCB_PM_MUX_SEL_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_PCB_PM_MUX_SEL_DC ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_UNUSED1 , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_UNUSED1 ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_UNUSED2 , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_UNUSED2 ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_UNUSED3 , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_UNUSED3 ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_3_RESERVED , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_3_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_4_RESERVED , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_4_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_5_RESERVED , 5 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_5_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_6_RESERVED , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_6_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_7_RESERVED , 7 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_7_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_8_RESERVED , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_8_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_9_RESERVED , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_9_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_10_RESERVED , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_10_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_11_RESERVED , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_11_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_12_RESERVED , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_12_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_13_RESERVED , 13 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_13_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_14_RESERVED , 14 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_14_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_15_RESERVED , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_15_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_SEC_BUF_DRV_STRENGTH_DC , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_SEC_BUF_DRV_STRENGTH_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC_LEN ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_20_RESERVED , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_20_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_21_RESERVED , 21 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_21_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_22_RESERVED , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_22_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_23_RESERVED , 23 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_23_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_24_RESERVED , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_24_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_CLK_PULSE_ENABLE_DC , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CLK_PULSE_ENABLE_DC ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_CLK_PULSE_MODE_DC , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CLK_PULSE_MODE_DC ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_CLK_PULSE_MODE_DC_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CLK_PULSE_MODE_DC_LEN ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_RESCLK_DIS_DC , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_RESCLK_DIS_DC ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_CPM_CAL_SET , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CPM_CAL_SET ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_30_RESERVED , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_30_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_CLEAR_TP_PCB_PM_MUX_SEL_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PCB_PM_MUX_SEL_DC ); + +REG64_FLD( PERV_PERV_CTRL1_SET_UNUSED1 , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_UNUSED1 ); +REG64_FLD( PERV_PERV_CTRL1_SET_UNUSED2 , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_UNUSED2 ); +REG64_FLD( PERV_PERV_CTRL1_SET_UNUSED3 , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_UNUSED3 ); +REG64_FLD( PERV_PERV_CTRL1_SET_3_RESERVED , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_3_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_4_RESERVED , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_4_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_5_RESERVED , 5 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_5_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_6_RESERVED , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_6_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_7_RESERVED , 7 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_7_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_8_RESERVED , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_8_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_9_RESERVED , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_9_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_10_RESERVED , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_10_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_11_RESERVED , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_11_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_12_RESERVED , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_12_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_13_RESERVED , 13 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_13_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_14_RESERVED , 14 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_14_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_15_RESERVED , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_15_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_TP_SEC_BUF_DRV_STRENGTH_DC , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC ); +REG64_FLD( PERV_PERV_CTRL1_SET_TP_SEC_BUF_DRV_STRENGTH_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC_LEN ); +REG64_FLD( PERV_PERV_CTRL1_SET_20_RESERVED , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_20_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_21_RESERVED , 21 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_21_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_22_RESERVED , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_22_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_23_RESERVED , 23 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_23_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_24_RESERVED , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_24_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_TP_CLK_PULSE_ENABLE_DC , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CLK_PULSE_ENABLE_DC ); +REG64_FLD( PERV_PERV_CTRL1_SET_TP_CLK_PULSE_MODE_DC , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CLK_PULSE_MODE_DC ); +REG64_FLD( PERV_PERV_CTRL1_SET_TP_CLK_PULSE_MODE_DC_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CLK_PULSE_MODE_DC_LEN ); +REG64_FLD( PERV_PERV_CTRL1_SET_TP_RESCLK_DIS_DC , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_RESCLK_DIS_DC ); +REG64_FLD( PERV_PERV_CTRL1_SET_TP_CPM_CAL , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CPM_CAL ); +REG64_FLD( PERV_PERV_CTRL1_SET_30_RESERVED , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_30_RESERVED ); +REG64_FLD( PERV_PERV_CTRL1_SET_TP_PCB_PM_MUX_SEL_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PCB_PM_MUX_SEL_DC ); + REG64_FLD( PERV_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PERV_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , @@ -3864,18 +5067,138 @@ REG64_FLD( PERV_1_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UN REG64_FLD( PERV_1_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); -REG64_FLD( PERV_PRV_DBG_PIB_RESET , 0 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_PIB_RESET ); -REG64_FLD( PERV_PRV_DBG_RESERVED_15 , 1 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_15 ); -REG64_FLD( PERV_PRV_DBG_RESERVED_16 , 2 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_16 ); -REG64_FLD( PERV_PRV_DBG_RESERVED_16_LEN , 4 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_16_LEN ); -REG64_FLD( PERV_PRV_DBG_RESERVED_17 , 6 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_17 ); -REG64_FLD( PERV_PRV_DBG_RESERVED_17_LEN , 3 , SH_UNT_PERV , SH_ACS_PPE2 , - SH_FLD_RESERVED_17_LEN ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PCB_WDATA_PARITY ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PCB_ADDRESS_PARITY ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_DL_RETURN_P0 ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UL_RDATA_PARITY ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UL_P0 ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PARALLEL_WRITE_NVLD ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PARALLEL_READ_NVLD ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PARALLEL_ADDR_INVALID ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PCB_COMMAND_PARITY ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_GENERAL_TIMEOUT ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PERV_1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); + +REG64_FLD( PERV_1_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); +REG64_FLD( PERV_1_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); +REG64_FLD( PERV_1_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); +REG64_FLD( PERV_1_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); +REG64_FLD( PERV_1_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_WATCHDOG_ENABLE ); +REG64_FLD( PERV_1_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT ); +REG64_FLD( PERV_1_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SCOM_HANG_LIMIT_LEN ); +REG64_FLD( PERV_1_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_FORCE_ALL_RINGS ); +REG64_FLD( PERV_1_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); +REG64_FLD( PERV_1_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESERVED_LT ); +REG64_FLD( PERV_1_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESERVED_LT_LEN ); + +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_DL_RETURN_P0 ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_UL_P0 ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_WDATA_PARITY ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_DL_RETURN_P0 ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_RDATA_PARITY ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_UL_P0 ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRAPPED_GENERAL_TIMEOUT ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); +REG64_FLD( PERV_1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG32_FLD( PERV_FSISHIFT_READ_BUFFER_REG , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG ); @@ -4282,6 +5605,11 @@ REG64_FLD( PERV_RESET_REG_ENDPOINTS , 1 , SH_UN REG64_FLD( PERV_RESET_REG_TIMEOUT_EN , 2 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TIMEOUT_EN ); +REG32_FLD( PERV_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH_A_RESID_FE_LEN_0 , 0 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_RESID_FE_LEN_0 ); +REG32_FLD( PERV_FSII2C_RESIDUAL_FRONT_END_BACK_END_LENGTH_A_RESID_FE_LEN_0_LEN , 16 , SH_UNT_PERV_FSII2C, + SH_ACS_SCOM , SH_FLD_RESID_FE_LEN_0_LEN ); + REG64_FLD( PERV_1_RFIR_IN0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( PERV_1_RFIR_LFIR_RECOV_ERR , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , @@ -4325,8 +5653,13 @@ REG64_FLD( PERV_1_RFIR_IN21 , 19 , SH_UN REG64_FLD( PERV_1_RFIR_IN21_LEN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_IN21_LEN ); -REG64_FLD( PERV_ROOT_CTRL0_TPFSI_SBE_FENCE_VTLIO_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_TPFSI_SBE_FENCE_VTLIO_DC ); +REG64_FLD( PERV_1_RING_FENCE_MASK_LATCH_REG_ENABLE , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ENABLE ); +REG64_FLD( PERV_1_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ENABLE_LEN ); + +REG64_FLD( PERV_ROOT_CTRL0_TPFSI_SBE_FENCE_VTLIO_DC_UNUSED , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_SBE_FENCE_VTLIO_DC_UNUSED ); REG64_FLD( PERV_ROOT_CTRL0_TPFSI_TP_FENCE_VTLIO_DC , 1 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TPFSI_TP_FENCE_VTLIO_DC ); REG64_FLD( PERV_ROOT_CTRL0_TPFSI_TPI2C_BUS_FENCE_DC , 2 , SH_UNT_PERV , SH_ACS_SCOM , @@ -4386,6 +5719,128 @@ REG64_FLD( PERV_ROOT_CTRL0_PCB_RESET_DC , 30 , SH_UN REG64_FLD( PERV_ROOT_CTRL0_GLOBAL_EP_RESET_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_GLOBAL_EP_RESET_DC ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_TPFSI_SBE_FENCE_VTLIO_DC_UNUSED , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_SBE_FENCE_VTLIO_DC_UNUSED ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_TPFSI_TP_FENCE_VTLIO_DC , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_FENCE_VTLIO_DC ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_TPFSI_TPI2C_BUS_FENCE_DC , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TPI2C_BUS_FENCE_DC ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_TPCFSI_OPB_SW0_FENCE_DC , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPCFSI_OPB_SW0_FENCE_DC ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_TPCFSI_OPB_SW0_FENCE_DC_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPCFSI_OPB_SW0_FENCE_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_TPCFSI_OPB_SW1_FENCE_DC , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPCFSI_OPB_SW1_FENCE_DC ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_TPCFSI_OPB_SW1_FENCE_DC_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPCFSI_OPB_SW1_FENCE_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FENCE1_DC , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FENCE1_DC ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FENCE2_DC , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FENCE2_DC ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FENCE3_DC , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FENCE3_DC ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FENCE4_DC , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FENCE4_DC ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FENCE5_DC , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FENCE5_DC ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FENCE6_DC , 13 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FENCE6_DC ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_SPARE_FENCE_CONTROL , 14 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SPARE_FENCE_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_VDD2VIO_LVL_FENCE_DC , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_VDD2VIO_LVL_FENCE_DC ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_PIB2PCB_DC , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_PIB2PCB_DC ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_OOB_MUX , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_OOB_MUX ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_18_SPARE_MUX_CONTROL , 18 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_18_SPARE_MUX_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_19_SPARE_MUX_CONTROL , 19 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_19_SPARE_MUX_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FSI_CC_VSB_CBS_REQ , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FSI_CC_VSB_CBS_REQ ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FSI_CC_VSB_CBS_CMD , 21 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FSI_CC_VSB_CBS_CMD ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_FSI_CC_VSB_CBS_CMD_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FSI_CC_VSB_CBS_CMD_LEN ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_24_SPARE_CBS_CONTROL , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_24_SPARE_CBS_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_25_SPARE_CBS_CONTROL , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_25_SPARE_CBS_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_26_SPARE_CBS_CONTROL , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_26_SPARE_CBS_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_27_SPARE_CBS_CONTROL , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_27_SPARE_CBS_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_28_SPARE_RESET , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_28_SPARE_RESET ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_29_SPARE_RESET , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_29_SPARE_RESET ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_PCB_RESET_DC , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_PCB_RESET_DC ); +REG64_FLD( PERV_ROOT_CTRL0_CLEAR_GLOBAL_EP_RESET_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_GLOBAL_EP_RESET_DC ); + +REG64_FLD( PERV_ROOT_CTRL0_SET_TPFSI_SBE_FENCE_VTLIO_DC_UNUSED , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_SBE_FENCE_VTLIO_DC_UNUSED ); +REG64_FLD( PERV_ROOT_CTRL0_SET_TPFSI_TP_FENCE_VTLIO_DC , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_FENCE_VTLIO_DC ); +REG64_FLD( PERV_ROOT_CTRL0_SET_TPFSI_TPI2C_BUS_FENCE_DC , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TPI2C_BUS_FENCE_DC ); +REG64_FLD( PERV_ROOT_CTRL0_SET_TPCFSI_OPB_SW0_FENCE_DC , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPCFSI_OPB_SW0_FENCE_DC ); +REG64_FLD( PERV_ROOT_CTRL0_SET_TPCFSI_OPB_SW0_FENCE_DC_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPCFSI_OPB_SW0_FENCE_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL0_SET_TPCFSI_OPB_SW1_FENCE_DC , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPCFSI_OPB_SW1_FENCE_DC ); +REG64_FLD( PERV_ROOT_CTRL0_SET_TPCFSI_OPB_SW1_FENCE_DC_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPCFSI_OPB_SW1_FENCE_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL0_SET_FENCE1_DC , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FENCE1_DC ); +REG64_FLD( PERV_ROOT_CTRL0_SET_FENCE2_DC , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FENCE2_DC ); +REG64_FLD( PERV_ROOT_CTRL0_SET_FENCE3_DC , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FENCE3_DC ); +REG64_FLD( PERV_ROOT_CTRL0_SET_FENCE4_DC , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FENCE4_DC ); +REG64_FLD( PERV_ROOT_CTRL0_SET_FENCE5_DC , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FENCE5_DC ); +REG64_FLD( PERV_ROOT_CTRL0_SET_FENCE6_DC , 13 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FENCE6_DC ); +REG64_FLD( PERV_ROOT_CTRL0_SET_SPARE_FENCE_CONTROL , 14 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SPARE_FENCE_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL0_SET_VDD2VIO_LVL_FENCE_DC , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_VDD2VIO_LVL_FENCE_DC ); +REG64_FLD( PERV_ROOT_CTRL0_SET_PIB2PCB_DC , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_PIB2PCB_DC ); +REG64_FLD( PERV_ROOT_CTRL0_SET_OOB_MUX , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_OOB_MUX ); +REG64_FLD( PERV_ROOT_CTRL0_SET_18_SPARE_MUX_CONTROL , 18 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_18_SPARE_MUX_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL0_SET_19_SPARE_MUX_CONTROL , 19 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_19_SPARE_MUX_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL0_SET_FSI_CC_VSB_CBS_REQ , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FSI_CC_VSB_CBS_REQ ); +REG64_FLD( PERV_ROOT_CTRL0_SET_FSI_CC_VSB_CBS_CMD , 21 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FSI_CC_VSB_CBS_CMD ); +REG64_FLD( PERV_ROOT_CTRL0_SET_FSI_CC_VSB_CBS_CMD_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_FSI_CC_VSB_CBS_CMD_LEN ); +REG64_FLD( PERV_ROOT_CTRL0_SET_24_SPARE_CBS_CONTROL , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_24_SPARE_CBS_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL0_SET_25_SPARE_CBS_CONTROL , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_25_SPARE_CBS_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL0_SET_26_SPARE_CBS_CONTROL , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_26_SPARE_CBS_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL0_SET_27_SPARE_CBS_CONTROL , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_27_SPARE_CBS_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL0_SET_28_SPARE_RESET , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_28_SPARE_RESET ); +REG64_FLD( PERV_ROOT_CTRL0_SET_29_SPARE_RESET , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_29_SPARE_RESET ); +REG64_FLD( PERV_ROOT_CTRL0_SET_PCB_RESET_DC , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_PCB_RESET_DC ); +REG64_FLD( PERV_ROOT_CTRL0_SET_GLOBAL_EP_RESET_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_GLOBAL_EP_RESET_DC ); + REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE0_SEL_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_PROBE0_SEL_DC ); REG64_FLD( PERV_ROOT_CTRL1_TP_PROBE0_SEL_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , @@ -4430,8 +5885,8 @@ REG64_FLD( PERV_ROOT_CTRL1_TP_TEST_BURNIN_MODE_DC , 24 , SH_UN SH_FLD_TP_TEST_BURNIN_MODE_DC ); REG64_FLD( PERV_ROOT_CTRL1_TPFSI_ARRAY_SET_VBL_TO_VDD_DC , 25 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TPFSI_ARRAY_SET_VBL_TO_VDD_DC ); -REG64_FLD( PERV_ROOT_CTRL1_TPFSI_TP_LOWFREQTEST_REFCLK_DC , 26 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_TPFSI_TP_LOWFREQTEST_REFCLK_DC ); +REG64_FLD( PERV_ROOT_CTRL1_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED ); REG64_FLD( PERV_ROOT_CTRL1_TP_GLBCK_MEM_TESTCLK_SEL_DC , 27 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_GLBCK_MEM_TESTCLK_SEL_DC ); REG64_FLD( PERV_ROOT_CTRL1_28_SPARE_TEST_CONTROL , 28 , SH_UNT_PERV , SH_ACS_SCOM , @@ -4443,6 +5898,120 @@ REG64_FLD( PERV_ROOT_CTRL1_30_SPARE_TEST_CONTROL , 30 , SH_UN REG64_FLD( PERV_ROOT_CTRL1_31_SPARE_TEST_CONTROL , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_31_SPARE_TEST_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_PROBE0_SEL_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PROBE0_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_PROBE0_SEL_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PROBE0_SEL_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_PROBE1_SEL_DC , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PROBE1_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_PROBE1_SEL_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PROBE1_SEL_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_PROBE_MESH_SEL_DC , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PROBE_MESH_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_PROBE_DRV_EN_DC , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PROBE_DRV_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_PROBE_HIGHDRIVE_DC , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PROBE_HIGHDRIVE_DC ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_FSI_PROBE_SEL_DC , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FSI_PROBE_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_FSI_PROBE_SEL_DC_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FSI_PROBE_SEL_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_13_SPARE_PROBE , 13 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_13_SPARE_PROBE ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_14_SPARE_PROBE , 14 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_14_SPARE_PROBE ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_15_SPARE_PROBE , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_15_SPARE_PROBE ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_IDDQ_DC , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IDDQ_DC ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_SPARE_RI_CONTROL , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SPARE_RI_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_SPARE_DI_CONTROL , 18 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SPARE_DI_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_RI_DC_B , 19 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_RI_DC_B ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_DI1_DC_B , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_DI1_DC_B ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_DI2_DC_B , 21 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_DI2_DC_B ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_22_SPARE_TEST , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_22_SPARE_TEST ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_23_SPARE_TEST , 23 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_23_SPARE_TEST ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_TEST_BURNIN_MODE_DC , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_TEST_BURNIN_MODE_DC ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TPFSI_ARRAY_SET_VBL_TO_VDD_DC , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_ARRAY_SET_VBL_TO_VDD_DC ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_TP_GLBCK_MEM_TESTCLK_SEL_DC , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GLBCK_MEM_TESTCLK_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_28_SPARE_TEST_CONTROL , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_28_SPARE_TEST_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_29_SPARE_TEST_CONTROL , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_29_SPARE_TEST_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_30_SPARE_TEST_CONTROL , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_30_SPARE_TEST_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL1_CLEAR_31_SPARE_TEST_CONTROL , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_31_SPARE_TEST_CONTROL ); + +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE0_SEL_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PROBE0_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE0_SEL_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PROBE0_SEL_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE1_SEL_DC , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PROBE1_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE1_SEL_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PROBE1_SEL_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE_MESH_SEL_DC , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PROBE_MESH_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE_DRV_EN_DC , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PROBE_DRV_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_PROBE_HIGHDRIVE_DC , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PROBE_HIGHDRIVE_DC ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_FSI_PROBE_SEL_DC , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FSI_PROBE_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_FSI_PROBE_SEL_DC_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FSI_PROBE_SEL_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL1_SET_13_SPARE_PROBE , 13 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_13_SPARE_PROBE ); +REG64_FLD( PERV_ROOT_CTRL1_SET_14_SPARE_PROBE , 14 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_14_SPARE_PROBE ); +REG64_FLD( PERV_ROOT_CTRL1_SET_15_SPARE_PROBE , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_15_SPARE_PROBE ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_IDDQ_DC , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IDDQ_DC ); +REG64_FLD( PERV_ROOT_CTRL1_SET_SPARE_RI_CONTROL , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SPARE_RI_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL1_SET_SPARE_DI_CONTROL , 18 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SPARE_DI_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_RI_DC_B , 19 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_RI_DC_B ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_DI1_DC_B , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_DI1_DC_B ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_DI2_DC_B , 21 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_DI2_DC_B ); +REG64_FLD( PERV_ROOT_CTRL1_SET_22_SPARE_TEST , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_22_SPARE_TEST ); +REG64_FLD( PERV_ROOT_CTRL1_SET_23_SPARE_TEST , 23 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_23_SPARE_TEST ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_TEST_BURNIN_MODE_DC , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_TEST_BURNIN_MODE_DC ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TPFSI_ARRAY_VBL_TO_VDD_DC , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_ARRAY_VBL_TO_VDD_DC ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED ); +REG64_FLD( PERV_ROOT_CTRL1_SET_TP_GLBCK_MEM_TESTCLK_SEL_DC , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GLBCK_MEM_TESTCLK_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL1_SET_28_SPARE_TEST_CONTROL , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_28_SPARE_TEST_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL1_SET_29_SPARE_TEST_CONTROL , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_29_SPARE_TEST_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL1_SET_30_SPARE_TEST_CONTROL , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_30_SPARE_TEST_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL1_SET_31_SPARE_TEST_CONTROL , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_31_SPARE_TEST_CONTROL ); + REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC ); REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC , 1 , SH_UNT_PERV , SH_ACS_SCOM , @@ -4481,18 +6050,18 @@ REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_PFET_FORCE_OFF_DC , 18 , SH_UN SH_FLD_TPFSI_TP_PFET_FORCE_OFF_DC ); REG64_FLD( PERV_ROOT_CTRL2_TPFSI_TP_PFET_OVERRIDE_ON_DC_N , 19 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TPFSI_TP_PFET_OVERRIDE_ON_DC_N ); -REG64_FLD( PERV_ROOT_CTRL2_20_FREE_USAGE , 20 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_20_FREE_USAGE ); -REG64_FLD( PERV_ROOT_CTRL2_21_FREE_USAGE , 21 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_21_FREE_USAGE ); -REG64_FLD( PERV_ROOT_CTRL2_22_FREE_USAGE , 22 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_22_FREE_USAGE ); -REG64_FLD( PERV_ROOT_CTRL2_23_FREE_USAGE , 23 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_23_FREE_USAGE ); -REG64_FLD( PERV_ROOT_CTRL2_24_FREE_USAGE , 24 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_24_FREE_USAGE ); -REG64_FLD( PERV_ROOT_CTRL2_25_FREE_USAGE , 25 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_25_FREE_USAGE ); +REG64_FLD( PERV_ROOT_CTRL2_TP_IO_GPIO0_MCPRECOMP , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO0_MCPRECOMP ); +REG64_FLD( PERV_ROOT_CTRL2_TP_IO_GPIO0_MCPRECOMP_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO0_MCPRECOMP_LEN ); +REG64_FLD( PERV_ROOT_CTRL2_TP_IO_GPIO1_MCPRECOMP , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO1_MCPRECOMP ); +REG64_FLD( PERV_ROOT_CTRL2_TP_IO_GPIO1_MCPRECOMP_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO1_MCPRECOMP_LEN ); +REG64_FLD( PERV_ROOT_CTRL2_TP_IO_GPIO2_MCPRECOMP , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO2_MCPRECOMP ); +REG64_FLD( PERV_ROOT_CTRL2_TP_IO_GPIO2_MCPRECOMP_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO2_MCPRECOMP_LEN ); REG64_FLD( PERV_ROOT_CTRL2_26_FREE_USAGE , 26 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_26_FREE_USAGE ); REG64_FLD( PERV_ROOT_CTRL2_27_FREE_USAGE , 27 , SH_UNT_PERV , SH_ACS_SCOM , @@ -4506,6 +6075,132 @@ REG64_FLD( PERV_ROOT_CTRL2_30_FREE_USAGE , 30 , SH_UN REG64_FLD( PERV_ROOT_CTRL2_31_FREE_USAGE , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_31_FREE_USAGE ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_PIB_VSB_DISABLE_PARITY_DC , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PIB_VSB_DISABLE_PARITY_DC ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_PIB_TRACE_MODE_DATA_DC , 5 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PIB_TRACE_MODE_DATA_DC ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_PIB_VSB_SBE_TRACE_MODE , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PIB_VSB_SBE_TRACE_MODE ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_TPCPERV_VSB_TRACE_STOP , 7 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_TPCPERV_VSB_TRACE_STOP ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_GPIO_PIB_TIMEOUT , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GPIO_PIB_TIMEOUT ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_GPIO_PIB_TIMEOUT_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GPIO_PIB_TIMEOUT_LEN ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_SPARE_PIB_CONTROL , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SPARE_PIB_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPCFSI_OPB_SW_RESET_DC , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPCFSI_OPB_SW_RESET_DC ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_13_SPARE_OPB_CONTROL , 13 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_13_SPARE_OPB_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_14_SPARE_OPB_CONTROL , 14 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_14_SPARE_OPB_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_15_SPARE_OPB_CONTROL , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_15_SPARE_OPB_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_16_FREE_USAGE , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_16_FREE_USAGE ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_PFET_FORCE_OFF_DC , 18 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_PFET_FORCE_OFF_DC ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TPFSI_TP_PFET_OVERRIDE_ON_DC_N , 19 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_PFET_OVERRIDE_ON_DC_N ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_IO_GPIO0_MCPRECOMP , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO0_MCPRECOMP ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_IO_GPIO0_MCPRECOMP_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO0_MCPRECOMP_LEN ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_IO_GPIO1_MCPRECOMP , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO1_MCPRECOMP ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_IO_GPIO1_MCPRECOMP_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO1_MCPRECOMP_LEN ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_IO_GPIO2_MCPRECOMP , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO2_MCPRECOMP ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_TP_IO_GPIO2_MCPRECOMP_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO2_MCPRECOMP_LEN ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_26_FREE_USAGE , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_26_FREE_USAGE ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_27_FREE_USAGE , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_27_FREE_USAGE ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_28_FREE_USAGE , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_28_FREE_USAGE ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_29_FREE_USAGE , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_29_FREE_USAGE ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_30_FREE_USAGE , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_30_FREE_USAGE ); +REG64_FLD( PERV_ROOT_CTRL2_CLEAR_31_FREE_USAGE , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_31_FREE_USAGE ); + +REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TP_PIB_VSB_DISABLE_PARITY_DC , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PIB_VSB_DISABLE_PARITY_DC ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TP_PIB_TRACE_MODE_DATA_DC , 5 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PIB_TRACE_MODE_DATA_DC ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TP_PIB_VSB_SBE_TRACE_MODE , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PIB_VSB_SBE_TRACE_MODE ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TP_TPCPERV_VSB_TRACE_STOP , 7 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_TPCPERV_VSB_TRACE_STOP ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TP_GPIO_PIB_TIMEOUT , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GPIO_PIB_TIMEOUT ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TP_GPIO_PIB_TIMEOUT_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GPIO_PIB_TIMEOUT_LEN ); +REG64_FLD( PERV_ROOT_CTRL2_SET_SPARE_PIB_CONTROL , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SPARE_PIB_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TPCFSI_OPB_SW_RESET_DC , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPCFSI_OPB_SW_RESET_DC ); +REG64_FLD( PERV_ROOT_CTRL2_SET_13_SPARE_OPB_CONTROL , 13 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_13_SPARE_OPB_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL2_SET_14_SPARE_OPB_CONTROL , 14 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_14_SPARE_OPB_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL2_SET_15_SPARE_OPB_CONTROL , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_15_SPARE_OPB_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL2_SET_16_FREE_USAGE , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_16_FREE_USAGE ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_PFET_FORCE_OFF_DC , 18 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_PFET_FORCE_OFF_DC ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TPFSI_TP_PFET_OVERRIDE_ON_DC_N , 19 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_TP_PFET_OVERRIDE_ON_DC_N ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TP_IO_GPIO0_MCPRECOMP , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO0_MCPRECOMP ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TP_IO_GPIO0_MCPRECOMP_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO0_MCPRECOMP_LEN ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TP_IO_GPIO1_MCPRECOMP , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO1_MCPRECOMP ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TP_IO_GPIO1_MCPRECOMP_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO1_MCPRECOMP_LEN ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TP_IO_GPIO2_MCPRECOMP , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO2_MCPRECOMP ); +REG64_FLD( PERV_ROOT_CTRL2_SET_TP_IO_GPIO2_MCPRECOMP_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_IO_GPIO2_MCPRECOMP_LEN ); +REG64_FLD( PERV_ROOT_CTRL2_SET_26_FREE_USAGE , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_26_FREE_USAGE ); +REG64_FLD( PERV_ROOT_CTRL2_SET_27_FREE_USAGE , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_27_FREE_USAGE ); +REG64_FLD( PERV_ROOT_CTRL2_SET_28_FREE_USAGE , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_28_FREE_USAGE ); +REG64_FLD( PERV_ROOT_CTRL2_SET_29_FREE_USAGE , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_29_FREE_USAGE ); +REG64_FLD( PERV_ROOT_CTRL2_SET_30_FREE_USAGE , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_30_FREE_USAGE ); +REG64_FLD( PERV_ROOT_CTRL2_SET_31_FREE_USAGE , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_31_FREE_USAGE ); + REG64_FLD( PERV_ROOT_CTRL3_OSCSWITCH_CNTL0_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_OSCSWITCH_CNTL0_DC ); REG64_FLD( PERV_ROOT_CTRL3_OSCSWITCH_CNTL0_DC_LEN , 16 , SH_UNT_PERV , SH_ACS_SCOM , @@ -4523,11 +6218,55 @@ REG64_FLD( PERV_ROOT_CTRL3_OSCSWITCH_CNTL1_DC , 24 , SH_UN REG64_FLD( PERV_ROOT_CTRL3_OSCSWITCH_CNTL1_DC_LEN , 8 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_OSCSWITCH_CNTL1_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL3_CLEAR_OSCSWITCH_CNTL0_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_OSCSWITCH_CNTL0_DC ); +REG64_FLD( PERV_ROOT_CTRL3_CLEAR_OSCSWITCH_CNTL0_DC_LEN , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_OSCSWITCH_CNTL0_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL3_CLEAR_TP_GLBCK_VSB_PCIESW_USEOSC_DC , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC ); +REG64_FLD( PERV_ROOT_CTRL3_CLEAR_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL3_CLEAR_TP_GLBCK_VSB_PCIESW_TWEAK_DC , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC ); +REG64_FLD( PERV_ROOT_CTRL3_CLEAR_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL3_CLEAR_OSCSWITCH_CNTL1_DC , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_OSCSWITCH_CNTL1_DC ); +REG64_FLD( PERV_ROOT_CTRL3_CLEAR_OSCSWITCH_CNTL1_DC_LEN , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_OSCSWITCH_CNTL1_DC_LEN ); + +REG64_FLD( PERV_ROOT_CTRL3_SET_OSCSWITCH_CNTL0_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_OSCSWITCH_CNTL0_DC ); +REG64_FLD( PERV_ROOT_CTRL3_SET_OSCSWITCH_CNTL0_DC_LEN , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_OSCSWITCH_CNTL0_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL3_SET_TP_GLBCK_VSB_PCIESW_USEOSC_DC , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC ); +REG64_FLD( PERV_ROOT_CTRL3_SET_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL3_SET_TP_GLBCK_VSB_PCIESW_TWEAK_DC , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC ); +REG64_FLD( PERV_ROOT_CTRL3_SET_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL3_SET_OSCSWITCH_CNTL1_DC , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_OSCSWITCH_CNTL1_DC ); +REG64_FLD( PERV_ROOT_CTRL3_SET_OSCSWITCH_CNTL1_DC_LEN , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_OSCSWITCH_CNTL1_DC_LEN ); + REG64_FLD( PERV_ROOT_CTRL4_TP_OSCSWITCH_VSB , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_OSCSWITCH_VSB ); REG64_FLD( PERV_ROOT_CTRL4_TP_OSCSWITCH_VSB_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_OSCSWITCH_VSB_LEN ); +REG64_FLD( PERV_ROOT_CTRL4_CLEAR_TP_OSCSWITCH_VSB , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_OSCSWITCH_VSB ); +REG64_FLD( PERV_ROOT_CTRL4_CLEAR_TP_OSCSWITCH_VSB_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_OSCSWITCH_VSB_LEN ); + +REG64_FLD( PERV_ROOT_CTRL4_SET_TP_OSCSWITCH_VSB , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_OSCSWITCH_VSB ); +REG64_FLD( PERV_ROOT_CTRL4_SET_TP_OSCSWITCH_VSB_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_OSCSWITCH_VSB_LEN ); + REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_ERRINJ0_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TPFSI_OSCSW_ERRINJ0_DC ); REG64_FLD( PERV_ROOT_CTRL5_TPFSI_OSCSW_ERRINJ0_DC_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , @@ -4583,6 +6322,116 @@ REG64_FLD( PERV_ROOT_CTRL5_30_SPARE_OSC , 30 , SH_UN REG64_FLD( PERV_ROOT_CTRL5_31_SPARE_OSC , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_31_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_ERRINJ0_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_ERRINJ0_DC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_ERRINJ0_DC_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_ERRINJ0_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_ERRINJ1_DC , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_ERRINJ1_DC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_ERRINJ1_DC_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_ERRINJ1_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_TWEAK_DC , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_TWEAK_DC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_TWEAK_DC_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_TWEAK_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_SKEW_ADJUST_DC , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_SNS_CONTENT_SEL_DC , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_15_SPARE_OSC , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_15_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_16_SPARE_OSC , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_16_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_17_SPARE_OSC , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_17_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_18_SPARE_OSC , 18 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_18_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_19_SPARE_OSC , 19 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_19_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_20_SPARE_OSC , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_20_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_21_SPARE_OSC , 21 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_21_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_22_SPARE_OSC , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_22_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_23_SPARE_OSC , 23 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_23_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_24_SPARE_OSC , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_24_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_25_SPARE_OSC , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_25_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_26_SPARE_OSC , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_26_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_27_SPARE_OSC , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_27_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_28_SPARE_OSC , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_28_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_29_SPARE_OSC , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_29_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_30_SPARE_OSC , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_30_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_CLEAR_31_SPARE_OSC , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_31_SPARE_OSC ); + +REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_ERRINJ0_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_ERRINJ0_DC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_ERRINJ0_DC_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_ERRINJ0_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_ERRINJ1_DC , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_ERRINJ1_DC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_ERRINJ1_DC_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_ERRINJ1_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_TWEAK_DC , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_TWEAK_DC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_TWEAK_DC_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_TWEAK_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_SKEW_ADJUST_DC , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_SNS_CONTENT_SEL_DC , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL5_SET_15_SPARE_OSC , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_15_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_16_SPARE_OSC , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_16_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_17_SPARE_OSC , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_17_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_18_SPARE_OSC , 18 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_18_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_19_SPARE_OSC , 19 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_19_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_20_SPARE_OSC , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_20_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_21_SPARE_OSC , 21 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_21_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_22_SPARE_OSC , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_22_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_23_SPARE_OSC , 23 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_23_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_24_SPARE_OSC , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_24_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_25_SPARE_OSC , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_25_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_26_SPARE_OSC , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_26_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_27_SPARE_OSC , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_27_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_28_SPARE_OSC , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_28_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_29_SPARE_OSC , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_29_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_30_SPARE_OSC , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_30_SPARE_OSC ); +REG64_FLD( PERV_ROOT_CTRL5_SET_31_SPARE_OSC , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_31_SPARE_OSC ); + REG64_FLD( PERV_ROOT_CTRL6_TP_PLLREFCLK_RCVR_TERM_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC ); REG64_FLD( PERV_ROOT_CTRL6_TP_PLLREFCLK_RCVR_TERM_DC_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , @@ -4628,6 +6477,96 @@ REG64_FLD( PERV_ROOT_CTRL6_30_SPARE_REFCLOCK_CONTROL , 30 , SH_UN REG64_FLD( PERV_ROOT_CTRL6_31_SPARE_REFCLOCK_CONTROL , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_31_SPARE_REFCLOCK_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TP_PLLREFCLK_RCVR_TERM_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TP_PLLREFCLK_RCVR_TERM_DC_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TP_PCIREFCLK_RCVR_TERM_DC , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TP_PCIREFCLK_RCVR_TERM_DC_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_REFCLK_0_TERM_DIS_DC , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_REFCLK_0_TERM_DIS_DC ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_REFCLK_1_TERM_DIS_DC , 5 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_REFCLK_1_TERM_DIS_DC ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_6_SPARE_TERM_DIS , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_6_SPARE_TERM_DIS ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_7_SPARE_TERM_DIS , 7 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_7_SPARE_TERM_DIS ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TPFSI_OSCSW0_PGOOD_N , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW0_PGOOD_N ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TPFSI_OSCSW1_PGOOD , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW1_PGOOD ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_10_SPARE_REFCLOCK , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_10_SPARE_REFCLOCK ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_11_SPARE_REFCLOCK , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_11_SPARE_REFCLOCK ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TPFSI_OFFCHIP_REFCLK_EN_DC , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_25_SPARE_REFCLOCK_CONTROL , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_25_SPARE_REFCLOCK_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_26_SPARE_REFCLOCK_CONTROL , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_26_SPARE_REFCLOCK_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TPFSI_ALTREFCLK_SEL , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_ALTREFCLK_SEL ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_TPFSI_ALTREFCLK_SE1 , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_ALTREFCLK_SE1 ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_29_SPARE_REFCLOCK_CONTROL , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_29_SPARE_REFCLOCK_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_30_SPARE_REFCLOCK_CONTROL , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_30_SPARE_REFCLOCK_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL6_CLEAR_31_SPARE_REFCLOCK_CONTROL , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_31_SPARE_REFCLOCK_CONTROL ); + +REG64_FLD( PERV_ROOT_CTRL6_SET_TP_PLLREFCLK_RCVR_TERM_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC ); +REG64_FLD( PERV_ROOT_CTRL6_SET_TP_PLLREFCLK_RCVR_TERM_DC_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL6_SET_TP_PCIREFCLK_RCVR_TERM_DC , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC ); +REG64_FLD( PERV_ROOT_CTRL6_SET_TP_PCIREFCLK_RCVR_TERM_DC_LEN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL6_SET_REFCLK_0_TERM_DIS_DC , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_REFCLK_0_TERM_DIS_DC ); +REG64_FLD( PERV_ROOT_CTRL6_SET_REFCLK_1_TERM_DIS_DC , 5 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_REFCLK_1_TERM_DIS_DC ); +REG64_FLD( PERV_ROOT_CTRL6_SET_6_SPARE_TERM_DIS , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_6_SPARE_TERM_DIS ); +REG64_FLD( PERV_ROOT_CTRL6_SET_7_SPARE_TERM_DIS , 7 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_7_SPARE_TERM_DIS ); +REG64_FLD( PERV_ROOT_CTRL6_SET_TPFSI_OSCSW0_PGOOD_N , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW0_PGOOD_N ); +REG64_FLD( PERV_ROOT_CTRL6_SET_TPFSI_OSCSW1_PGOOD , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OSCSW1_PGOOD ); +REG64_FLD( PERV_ROOT_CTRL6_SET_10_SPARE_REFCLOCK , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_10_SPARE_REFCLOCK ); +REG64_FLD( PERV_ROOT_CTRL6_SET_11_SPARE_REFCLOCK , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_11_SPARE_REFCLOCK ); +REG64_FLD( PERV_ROOT_CTRL6_SET_TPFSI_OFFCHIP_REFCLK_EN_DC , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL6_SET_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN ); +REG64_FLD( PERV_ROOT_CTRL6_SET_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL6_SET_25_SPARE_REFCLOCK_CONTROL , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_25_SPARE_REFCLOCK_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL6_SET_26_SPARE_REFCLOCK_CONTROL , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_26_SPARE_REFCLOCK_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL6_SET_TPFSI_ALTREFCLK_SEL , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_ALTREFCLK_SEL ); +REG64_FLD( PERV_ROOT_CTRL6_SET_TPFSI_ALTREFCLK_SE1 , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TPFSI_ALTREFCLK_SE1 ); +REG64_FLD( PERV_ROOT_CTRL6_SET_29_SPARE_REFCLOCK_CONTROL , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_29_SPARE_REFCLOCK_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL6_SET_30_SPARE_REFCLOCK_CONTROL , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_30_SPARE_REFCLOCK_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL6_SET_31_SPARE_REFCLOCK_CONTROL , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_31_SPARE_REFCLOCK_CONTROL ); + REG64_FLD( PERV_ROOT_CTRL7_0_SPARE_SECTOR_BUFFER_CONTROL , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_0_SPARE_SECTOR_BUFFER_CONTROL ); REG64_FLD( PERV_ROOT_CTRL7_1_SPARE_SECTOR_BUFFER_CONTROL , 1 , SH_UNT_PERV , SH_ACS_SCOM , @@ -4693,32 +6632,162 @@ REG64_FLD( PERV_ROOT_CTRL7_30_SPARE_RESONANT_CLOCKING_CONTROL , 30 , SH_UN REG64_FLD( PERV_ROOT_CTRL7_31_SPARE_RESONANT_CLOCKING_CONTROL , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_31_SPARE_RESONANT_CLOCKING_CONTROL ); -REG64_FLD( PERV_ROOT_CTRL8_TP_SSPLL_PLL_RESET0_DC , 0 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_TP_SSPLL_PLL_RESET0_DC ); -REG64_FLD( PERV_ROOT_CTRL8_TP_SSPLL_PLL_BYPASS0_DC , 1 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_TP_SSPLL_PLL_BYPASS0_DC ); -REG64_FLD( PERV_ROOT_CTRL8_2_SPARE_SS_PLL_CONTROL , 2 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_2_SPARE_SS_PLL_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_0_SPARE_SECTOR_BUFFER_CONTROL , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_0_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_1_SPARE_SECTOR_BUFFER_CONTROL , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_1_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_2_SPARE_SECTOR_BUFFER_CONTROL , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_2_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_3_SPARE_SECTOR_BUFFER_CONTROL , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_3_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_4_SPARE_SECTOR_BUFFER_CONTROL , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_4_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_5_SPARE_SECTOR_BUFFER_CONTROL , 5 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_5_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_6_SPARE_SECTOR_BUFFER_CONTROL , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_6_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_7_SPARE_SECTOR_BUFFER_CONTROL , 7 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_7_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_8_SPARE_SECTOR_BUFFER_CONTROL , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_8_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_9_SPARE_SECTOR_BUFFER_CONTROL , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_9_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_10_SPARE_SECTOR_BUFFER_CONTROL , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_10_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_11_SPARE_SECTOR_BUFFER_CONTROL , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_11_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_12_SPARE_SECTOR_BUFFER_CONTROL , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_12_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_13_SPARE_SECTOR_BUFFER_CONTROL , 13 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_13_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_14_SPARE_SECTOR_BUFFER_CONTROL , 14 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_14_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_15_SPARE_SECTOR_BUFFER_CONTROL , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_15_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_16_SPARE_RESONANT_CLOCKING_CONTROL , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_16_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_17_SPARE_RESONANT_CLOCKING_CONTROL , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_17_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_18_SPARE_RESONANT_CLOCKING_CONTROL , 18 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_18_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_19_SPARE_RESONANT_CLOCKING_CONTROL , 19 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_19_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_20_SPARE_RESONANT_CLOCKING_CONTROL , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_20_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_21_SPARE_RESONANT_CLOCKING_CONTROL , 21 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_21_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_22_SPARE_RESONANT_CLOCKING_CONTROL , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_22_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_23_SPARE_RESONANT_CLOCKING_CONTROL , 23 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_23_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_24_SPARE_RESONANT_CLOCKING_CONTROL , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_24_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_25_SPARE_RESONANT_CLOCKING_CONTROL , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_25_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_26_SPARE_RESONANT_CLOCKING_CONTROL , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_26_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_27_SPARE_RESONANT_CLOCKING_CONTROL , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_27_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_28_SPARE_RESONANT_CLOCKING_CONTROL , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_28_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_29_SPARE_RESONANT_CLOCKING_CONTROL , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_29_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_30_SPARE_RESONANT_CLOCKING_CONTROL , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_30_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_CLEAR_31_SPARE_RESONANT_CLOCKING_CONTROL , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_31_SPARE_RESONANT_CLOCKING_CONTROL ); + +REG64_FLD( PERV_ROOT_CTRL7_SET_0_SPARE_SECTOR_BUFFER_CONTROL , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_0_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_1_SPARE_SECTOR_BUFFER_CONTROL , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_1_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_2_SPARE_SECTOR_BUFFER_CONTROL , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_2_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_3_SPARE_SECTOR_BUFFER_CONTROL , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_3_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_4_SPARE_SECTOR_BUFFER_CONTROL , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_4_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_5_SPARE_SECTOR_BUFFER_CONTROL , 5 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_5_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_6_SPARE_SECTOR_BUFFER_CONTROL , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_6_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_7_SPARE_SECTOR_BUFFER_CONTROL , 7 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_7_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_8_SPARE_SECTOR_BUFFER_CONTROL , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_8_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_9_SPARE_SECTOR_BUFFER_CONTROL , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_9_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_10_SPARE_SECTOR_BUFFER_CONTROL , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_10_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_11_SPARE_SECTOR_BUFFER_CONTROL , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_11_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_12_SPARE_SECTOR_BUFFER_CONTROL , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_12_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_13_SPARE_SECTOR_BUFFER_CONTROL , 13 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_13_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_14_SPARE_SECTOR_BUFFER_CONTROL , 14 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_14_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_15_SPARE_SECTOR_BUFFER_CONTROL , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_15_SPARE_SECTOR_BUFFER_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_16_SPARE_RESONANT_CLOCKING_CONTROL , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_16_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_17_SPARE_RESONANT_CLOCKING_CONTROL , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_17_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_18_SPARE_RESONANT_CLOCKING_CONTROL , 18 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_18_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_19_SPARE_RESONANT_CLOCKING_CONTROL , 19 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_19_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_20_SPARE_RESONANT_CLOCKING_CONTROL , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_20_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_21_SPARE_RESONANT_CLOCKING_CONTROL , 21 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_21_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_22_SPARE_RESONANT_CLOCKING_CONTROL , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_22_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_23_SPARE_RESONANT_CLOCKING_CONTROL , 23 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_23_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_24_SPARE_RESONANT_CLOCKING_CONTROL , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_24_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_25_SPARE_RESONANT_CLOCKING_CONTROL , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_25_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_26_SPARE_RESONANT_CLOCKING_CONTROL , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_26_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_27_SPARE_RESONANT_CLOCKING_CONTROL , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_27_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_28_SPARE_RESONANT_CLOCKING_CONTROL , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_28_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_29_SPARE_RESONANT_CLOCKING_CONTROL , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_29_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_30_SPARE_RESONANT_CLOCKING_CONTROL , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_30_SPARE_RESONANT_CLOCKING_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL7_SET_31_SPARE_RESONANT_CLOCKING_CONTROL , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_31_SPARE_RESONANT_CLOCKING_CONTROL ); + +REG64_FLD( PERV_ROOT_CTRL8_TP_SS0_PLL_RESET , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_SS0_PLL_RESET ); +REG64_FLD( PERV_ROOT_CTRL8_TP_SS0_PLL_BYPASS , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_SS0_PLL_BYPASS ); +REG64_FLD( PERV_ROOT_CTRL8_TP_SS0_PLL_TEST_EN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_SS0_PLL_TEST_EN ); REG64_FLD( PERV_ROOT_CTRL8_3_SPARE_SS_PLL_CONTROL , 3 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_3_SPARE_SS_PLL_CONTROL ); -REG64_FLD( PERV_ROOT_CTRL8_TP_FILTPLL_PLL_RESET1_DC , 4 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_TP_FILTPLL_PLL_RESET1_DC ); -REG64_FLD( PERV_ROOT_CTRL8_TP_FILTPLL_PLL_BYPASS1_DC , 5 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_TP_FILTPLL_PLL_BYPASS1_DC ); -REG64_FLD( PERV_ROOT_CTRL8_TP_FILTPLL_CP_ALT_BYPASS_DC , 6 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_TP_FILTPLL_CP_ALT_BYPASS_DC ); -REG64_FLD( PERV_ROOT_CTRL8_TP_FILTPLL_IO_ALT_BYPASS_DC , 7 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_TP_FILTPLL_IO_ALT_BYPASS_DC ); -REG64_FLD( PERV_ROOT_CTRL8_8_SPARE_FILTER_PLL_CONTROL , 8 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_8_SPARE_FILTER_PLL_CONTROL ); -REG64_FLD( PERV_ROOT_CTRL8_9_SPARE_FILTER_PLL_CONTROL , 9 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_9_SPARE_FILTER_PLL_CONTROL ); -REG64_FLD( PERV_ROOT_CTRL8_TP_TANKPLL_TEST_PLL_BYPASS2_DC , 10 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_TP_TANKPLL_TEST_PLL_BYPASS2_DC ); -REG64_FLD( PERV_ROOT_CTRL8_SPARE_TANK_PLL_CONTROL , 11 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_SPARE_TANK_PLL_CONTROL ); -REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_TEST_ENABLE_DC , 12 , SH_UNT_PERV , SH_ACS_SCOM , - SH_FLD_TP_PLL_TEST_ENABLE_DC ); +REG64_FLD( PERV_ROOT_CTRL8_TP_FILT0_PLL_RESET , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT0_PLL_RESET ); +REG64_FLD( PERV_ROOT_CTRL8_TP_FILT0_PLL_BYPASS , 5 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT0_PLL_BYPASS ); +REG64_FLD( PERV_ROOT_CTRL8_TP_FILT0_PLL_TEST_EN , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT0_PLL_TEST_EN ); +REG64_FLD( PERV_ROOT_CTRL8_SPARE_FILT0_PLL , 7 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SPARE_FILT0_PLL ); +REG64_FLD( PERV_ROOT_CTRL8_TP_FILT1_PLL_RESET , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT1_PLL_RESET ); +REG64_FLD( PERV_ROOT_CTRL8_TP_FILT1_PLL_BYPASS , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT1_PLL_BYPASS ); +REG64_FLD( PERV_ROOT_CTRL8_TP_FILT1_PLL_TEST_EN , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT1_PLL_TEST_EN ); +REG64_FLD( PERV_ROOT_CTRL8_SPARE_FILT1_PLL , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SPARE_FILT1_PLL ); +REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_TEST_EN , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_TEST_EN ); REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_FORCE_OUT_EN_DC , 13 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_PLL_FORCE_OUT_EN_DC ); REG64_FLD( PERV_ROOT_CTRL8_14_SPARE_PLL , 14 , SH_UNT_PERV , SH_ACS_SCOM , @@ -4758,6 +6827,136 @@ REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL3_DC , 30 , SH_UN REG64_FLD( PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL4_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_TP_PLL_CLKIN_SEL4_DC ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_SS0_PLL_RESET , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_SS0_PLL_RESET ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_SS0_PLL_BYPASS , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_SS0_PLL_BYPASS ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_SS0_PLL_TEST_EN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_SS0_PLL_TEST_EN ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_3_SPARE_SS_PLL_CONTROL , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_3_SPARE_SS_PLL_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_FILT0_PLL_RESET , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT0_PLL_RESET ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_FILT0_PLL_BYPASS , 5 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT0_PLL_BYPASS ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_FILT0_PLL_TEST_EN , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT0_PLL_TEST_EN ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_SPARE_FILT0_PLL , 7 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SPARE_FILT0_PLL ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_FILT1_PLL_RESET , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT1_PLL_RESET ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_FILT1_PLL_BYPASS , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT1_PLL_BYPASS ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_FILT1_PLL_TEST_EN , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT1_PLL_TEST_EN ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_SPARE_FILT1_PLL , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SPARE_FILT1_PLL ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_PLL_TEST_EN , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_TEST_EN ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_PLL_FORCE_OUT_EN_DC , 13 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_FORCE_OUT_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_14_SPARE_PLL , 14 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_14_SPARE_PLL ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_15_SPARE_PLL , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_15_SPARE_PLL ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_CLK_ASYNC_RESET_DC , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CLK_ASYNC_RESET_DC ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_CLK_DIV_BYPASS_EN_DC , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CLK_DIV_BYPASS_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_CLK_PDLY_BYPASS1_EN_DC , 18 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CLK_PDLY_BYPASS1_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_CLK_PDLY_BYPASS2_EN_DC , 19 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CLK_PDLY_BYPASS2_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_20_SPARE_PLL_CONTROL , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_20_SPARE_PLL_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_21_SPARE_PLL_CONTROL , 21 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_21_SPARE_PLL_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_22_SPARE_PLL_CONTROL , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_22_SPARE_PLL_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_23_SPARE_PLL_CONTROL , 23 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_23_SPARE_PLL_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_FSI_CLKIN_SEL_DC , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FSI_CLKIN_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_25_SPARE_CLKIN_CONTROL , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_25_SPARE_CLKIN_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_26_SPARE_CLKIN_CONTROL , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_26_SPARE_CLKIN_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_27_SPARE_CLKIN_CONTROL , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_27_SPARE_CLKIN_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_PLL_CLKIN_SEL1_DC , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_CLKIN_SEL1_DC ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_PLL_CLKIN_SEL2_DC , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_CLKIN_SEL2_DC ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_PLL_CLKIN_SEL3_DC , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_CLKIN_SEL3_DC ); +REG64_FLD( PERV_ROOT_CTRL8_CLEAR_TP_PLL_CLKIN_SEL4_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_CLKIN_SEL4_DC ); + +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_SS0_PLL_RESET , 0 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_SS0_PLL_RESET ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_SS0_PLL_BYPASS , 1 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_SS0_PLL_BYPASS ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_SS0_PLL_TEST_EN , 2 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_SS0_PLL_TEST_EN ); +REG64_FLD( PERV_ROOT_CTRL8_SET_3_SPARE_SS_PLL_CONTROL , 3 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_3_SPARE_SS_PLL_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_RESET , 4 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT0_PLL_RESET ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_BYPASS , 5 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT0_PLL_BYPASS ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_TEST_EN , 6 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT0_PLL_TEST_EN ); +REG64_FLD( PERV_ROOT_CTRL8_SET_SPARE_FILT0_PLL , 7 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SPARE_FILT0_PLL ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_RESET , 8 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT1_PLL_RESET ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_BYPASS , 9 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT1_PLL_BYPASS ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_TEST_EN , 10 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FILT1_PLL_TEST_EN ); +REG64_FLD( PERV_ROOT_CTRL8_SET_SPARE_FILT1_PLL , 11 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SPARE_FILT1_PLL ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_PLL_TEST_EN , 12 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_TEST_EN ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_PLL_FORCE_OUT_EN_DC , 13 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_FORCE_OUT_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL8_SET_14_SPARE_PLL , 14 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_14_SPARE_PLL ); +REG64_FLD( PERV_ROOT_CTRL8_SET_15_SPARE_PLL , 15 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_15_SPARE_PLL ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_CLK_ASYNC_RESET_DC , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CLK_ASYNC_RESET_DC ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_CLK_DIV_BYPASS_EN_DC , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CLK_DIV_BYPASS_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_CLK_PDLY_BYPASS1_EN_DC , 18 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CLK_PDLY_BYPASS1_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_CLK_PDLY_BYPASS2_EN_DC , 19 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_CLK_PDLY_BYPASS2_EN_DC ); +REG64_FLD( PERV_ROOT_CTRL8_SET_20_SPARE_PLL_CONTROL , 20 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_20_SPARE_PLL_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_SET_21_SPARE_PLL_CONTROL , 21 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_21_SPARE_PLL_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_SET_22_SPARE_PLL_CONTROL , 22 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_22_SPARE_PLL_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_SET_23_SPARE_PLL_CONTROL , 23 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_23_SPARE_PLL_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_FSI_CLKIN_SEL_DC , 24 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_FSI_CLKIN_SEL_DC ); +REG64_FLD( PERV_ROOT_CTRL8_SET_25_SPARE_CLKIN_CONTROL , 25 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_25_SPARE_CLKIN_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_SET_26_SPARE_CLKIN_CONTROL , 26 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_26_SPARE_CLKIN_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_SET_27_SPARE_CLKIN_CONTROL , 27 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_27_SPARE_CLKIN_CONTROL ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL1_DC , 28 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_CLKIN_SEL1_DC ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL2_DC , 29 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_CLKIN_SEL2_DC ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL3_DC , 30 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_CLKIN_SEL3_DC ); +REG64_FLD( PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL4_DC , 31 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_TP_PLL_CLKIN_SEL4_DC ); + REG64_FLD( PERV_SBE_LCL_DBG_EN , 0 , SH_UNT_PERV , SH_ACS_PPE , SH_FLD_EN ); REG64_FLD( PERV_SBE_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_PERV , SH_ACS_PPE , @@ -4921,6 +7120,10 @@ REG64_FLD( PERV_SB_CS_INTERRUPT_S0 , 14 , SH_UN SH_FLD_INTERRUPT_S0 ); REG64_FLD( PERV_SB_CS_INTERRUPT_S1 , 15 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_INTERRUPT_S1 ); +REG64_FLD( PERV_SB_CS_BYPASSING_RESET_SEQUENCE_PIB_I2CM , 16 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_BYPASSING_RESET_SEQUENCE_PIB_I2CM ); +REG64_FLD( PERV_SB_CS_SELECT_SECONDARY_SEEPROM , 17 , SH_UNT_PERV , SH_ACS_SCOM , + SH_FLD_SELECT_SECONDARY_SEEPROM ); REG64_FLD( PERV_SB_CS_DEBUG_BOLT_ON_CONTROL_BITS , 25 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS ); REG64_FLD( PERV_SB_CS_DEBUG_BOLT_ON_CONTROL_BITS_LEN , 7 , SH_UNT_PERV , SH_ACS_SCOM , @@ -4977,26 +7180,6 @@ REG64_FLD( PERV_1_SCAN_REGION_TYPE_CMSK , 58 , SH_UN REG64_FLD( PERV_1_SCAN_REGION_TYPE_INEX , 59 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_INEX ); -REG64_FLD( PERV_FSI2PIB_SCRATCH0_SCRATCH_N , 0 , SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2 , - SH_FLD_SCRATCH_N ); -REG64_FLD( PERV_FSI2PIB_SCRATCH0_SCRATCH_N_LEN , 64 , SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2 , - SH_FLD_SCRATCH_N_LEN ); - -REG64_FLD( PERV_FSI2PIB_SCRATCH1_SCRATCH_N , 0 , SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2 , - SH_FLD_SCRATCH_N ); -REG64_FLD( PERV_FSI2PIB_SCRATCH1_SCRATCH_N_LEN , 64 , SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2 , - SH_FLD_SCRATCH_N_LEN ); - -REG64_FLD( PERV_FSI2PIB_SCRATCH2_SCRATCH_N , 0 , SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2 , - SH_FLD_SCRATCH_N ); -REG64_FLD( PERV_FSI2PIB_SCRATCH2_SCRATCH_N_LEN , 64 , SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2 , - SH_FLD_SCRATCH_N_LEN ); - -REG64_FLD( PERV_FSI2PIB_SCRATCH3_SCRATCH_N , 0 , SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2 , - SH_FLD_SCRATCH_N ); -REG64_FLD( PERV_FSI2PIB_SCRATCH3_SCRATCH_N_LEN , 64 , SH_UNT_PERV_FSI2PIB, SH_ACS_PPE2 , - SH_FLD_SCRATCH_N_LEN ); - REG64_FLD( PERV_SCRATCH_REGISTER_1_SR , 0 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_SR ); REG64_FLD( PERV_SCRATCH_REGISTER_1_SR_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , @@ -5037,6 +7220,11 @@ REG64_FLD( PERV_SCRATCH_REGISTER_8_SR , 0 , SH_UN REG64_FLD( PERV_SCRATCH_REGISTER_8_SR_LEN , 32 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_SR_LEN ); +REG64_FLD( PERV_1_SECURE_PIB_MASTER_ID_REG_MASTERS , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASTERS ); +REG64_FLD( PERV_1_SECURE_PIB_MASTER_ID_REG_MASTERS_LEN , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASTERS_LEN ); + REG32_FLD( PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2_REGISTER , 0 , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REGISTER ); REG32_FLD( PERV_FSISHIFT_SHIFT_CONTROL_REGISTER_2_REGISTER_LEN , 32 , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , @@ -5152,8 +7340,8 @@ REG32_FLD( PERV_FSI2PIB_STATUS_SELFBOOT_DONE , 8 , SH_UN SH_FLD_SELFBOOT_DONE ); REG32_FLD( PERV_FSI2PIB_STATUS_RESERVED_9 , 9 , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_RESERVED_9 ); -REG32_FLD( PERV_FSI2PIB_STATUS_RESERVED_10 , 10 , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , - SH_FLD_RESERVED_10 ); +REG32_FLD( PERV_FSI2PIB_STATUS_IDLE_INDICATION , 10 , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , + SH_FLD_IDLE_INDICATION ); REG32_FLD( PERV_FSI2PIB_STATUS_PIB_ABORT , 11 , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_PIB_ABORT ); REG32_FLD( PERV_FSI2PIB_STATUS_USE_OSC_OBSERVATION , 12 , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , @@ -5192,6 +7380,31 @@ REG32_FLD( PERV_FSISHIFT_STATUS_4 , 0 , SH_UN REG32_FLD( PERV_FSISHIFT_STATUS_4_LEN , 32 , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_4_LEN ); +REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_INVALID_CMD_0 , 0 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_INVALID_CMD_0 ); +REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_LBUS_PARITY_ERROR_0 , 1 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_LBUS_PARITY_ERROR_0 ); +REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_BE_OV_ERROR_0 , 2 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_BE_OV_ERROR_0 ); +REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_BE_ACC_ERROR_0 , 3 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_BE_ACC_ERROR_0 ); +REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_ARBITRATION_LOST_ERROR_0 , 4 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_ARBITRATION_LOST_ERROR_0 ); +REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_NACK_RECEIVED_ERROR_0 , 5 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_NACK_RECEIVED_ERROR_0 ); +REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_DATA_REQUEST_0 , 6 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_DATA_REQUEST_0 ); +REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_STOP_ERROR_0 , 8 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_STOP_ERROR_0 ); +REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_BUSY , 22 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_BUSY ); +REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_SELF_BUSY_0 , 23 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_SELF_BUSY_0 ); +REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_FIFO_ENTRY_COUNT_0 , 28 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_FIFO_ENTRY_COUNT_0 ); +REG32_FLD( PERV_FSII2C_STATUS_REGISTER_ENGINE_A_FIFO_ENTRY_COUNT_0_LEN , 4 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_FIFO_ENTRY_COUNT_0_LEN ); + REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_CMD_PARITY_ERROR , 1 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , SH_FLD_CMD_PARITY_ERROR ); REG64_FLD( PERV_PIB2OPB1_STAT_RDDAT_ERRES_WR_DATA_PARITY_ERROR , 2 , SH_UNT_PERV_PIB2OPB1, SH_ACS_SCOM_RO , @@ -5231,31 +7444,39 @@ REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_FSM_PARITY_ERROR , 5 , SH_UN REG64_FLD( PERV_PIB2OPB0_STAT_RDDAT_ERRES_OPB_PARITY_ERROR , 8 , SH_UNT_PERV_PIB2OPB0, SH_ACS_SCOM_RO , SH_FLD_OPB_PARITY_ERROR ); -REG64_FLD( PERV_1_SUM_MASK_REG_SMASK_IN , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_SMASK_IN ); -REG64_FLD( PERV_1_SUM_MASK_REG_SMASK_IN_LEN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_SMASK_IN_LEN ); +REG64_FLD( PERV_1_SUM_MASK_REG_SMASK_IN0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SMASK_IN0 ); +REG64_FLD( PERV_1_SUM_MASK_REG_SMASK_IN1 , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SMASK_IN1 ); +REG64_FLD( PERV_1_SUM_MASK_REG_SMASK_IN2 , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SMASK_IN2 ); +REG64_FLD( PERV_1_SUM_MASK_REG_SMASK_IN3 , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SMASK_IN3 ); +REG64_FLD( PERV_1_SUM_MASK_REG_SMASK_IN4 , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_SMASK_IN4 ); REG64_FLD( PERV_1_SYNC_CONFIG_PULSE_DELAY , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_PULSE_DELAY ); -REG64_FLD( PERV_1_SYNC_CONFIG_PULSE_DELAY_LEN , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_SYNC_CONFIG_PULSE_DELAY_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_PULSE_DELAY_LEN ); -REG64_FLD( PERV_1_SYNC_CONFIG_UNUSED3 , 3 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_UNUSED3 ); REG64_FLD( PERV_1_SYNC_CONFIG_LISTEN_TO_PULSE_DIS , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_LISTEN_TO_PULSE_DIS ); -REG64_FLD( PERV_1_SYNC_CONFIG_USE_FOR_SCAN , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , +REG64_FLD( PERV_1_SYNC_CONFIG_PULSE_INPUT_SEL , 5 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PULSE_INPUT_SEL ); +REG64_FLD( PERV_1_SYNC_CONFIG_USE_FOR_SCAN , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_USE_FOR_SCAN ); -REG64_FLD( PERV_1_SYNC_CONFIG_DISABLE_PCB_ITR , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_DISABLE_PCB_ITR ); REG64_FLD( PERV_1_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED , 7 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_CLEAR_CHIPLET_IS_ALIGNED ); REG64_FLD( PERV_1_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_UNIT_REGION_CLKCMD_ENABLE ); -REG64_FLD( PERV_1_SYNC_CONFIG_UNUSED919 , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_UNUSED919 ); -REG64_FLD( PERV_1_SYNC_CONFIG_UNUSED919_LEN , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , - SH_FLD_UNUSED919_LEN ); +REG64_FLD( PERV_1_SYNC_CONFIG_DISABLE_PCB_ITR , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_DISABLE_PCB_ITR ); +REG64_FLD( PERV_1_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_ENABLE_VITL_ALIGN_CHECK ); +REG64_FLD( PERV_1_SYNC_CONFIG_UNUSED1119 , 11 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNUSED1119 ); +REG64_FLD( PERV_1_SYNC_CONFIG_UNUSED1119_LEN , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_UNUSED1119_LEN ); REG64_FLD( PERV_1_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_DIS_CPM_BUBBLE_CORR ); @@ -6637,6 +8858,254 @@ REG64_FLD( PERV_TOD_VALUE_REG_WOF_COUNTER , 60 , SH_UN REG64_FLD( PERV_TOD_VALUE_REG_WOF_COUNTER_LEN , 4 , SH_UNT_PERV , SH_ACS_SCOM , SH_FLD_WOF_COUNTER_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_DATA ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_DATA_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_ADDRESS_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_LAST_BANK_VALID ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_WRITE_ON_RUN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_RUNNING ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM_RO , + SH_FLD_HOLD_ADDRESS_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_STORE_ON_TRIG_MODE_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_CMP_MSK_LT_B_TO_63 ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERNA ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERNA_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERNB ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERNB_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERNC ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERNC_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERND ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_PATTERND_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKA ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKA_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKB ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKB_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKC ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKC_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKD ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MASKD_LEN ); + +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_DISABLE_COMPRESSION ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_PERV_1 , + SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHA_MUXSEL_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHB_MUXSEL_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHC_MUXSEL_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCHD_MUXSEL_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG0_OR_MASK_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG0_AND_MASK_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG1_OR_MASK_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG1_AND_MASK_LEN ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG0_NOT_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_TRIG1_NOT_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE ); +REG64_FLD( PERV_1_TPCHIP_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_MATCH_NOT_MODE_LEN ); + REG32_FLD( PERV_FSI2PIB_TRUE_MASK_REG , 0 , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , SH_FLD_REG ); REG32_FLD( PERV_FSI2PIB_TRUE_MASK_REG_LEN , 32 , SH_UNT_PERV_FSI2PIB, SH_ACS_FSI_BYTE , @@ -6647,10 +9116,20 @@ REG32_FLD( PERV_FSISHIFT_TRUE_MASK_REG , 0 , SH_UN REG32_FLD( PERV_FSISHIFT_TRUE_MASK_REG_LEN , 32 , SH_UNT_PERV_FSISHIFT, SH_ACS_FSI_BYTE , SH_FLD_REG_LEN ); -REG32_FLD( PERV_FSII2C_WATER_MARK_REGISTER_WATERMARK_REG , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , - SH_FLD_WATERMARK_REG ); -REG32_FLD( PERV_FSII2C_WATER_MARK_REGISTER_WATERMARK_REG_LEN , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , - SH_FLD_WATERMARK_REG_LEN ); +REG32_FLD( PERV_FSII2C_WATER_MARK_REGISTER_A_WATERMARK_REG_0 , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_WATERMARK_REG_0 ); +REG32_FLD( PERV_FSII2C_WATER_MARK_REGISTER_A_WATERMARK_REG_0_LEN , 16 , SH_UNT_PERV_FSII2C, SH_ACS_SCOM , + SH_FLD_WATERMARK_REG_0_LEN ); + +REG64_FLD( PERV_1_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RING_LOCKING ); +REG64_FLD( PERV_1_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RESERVED_RING_LOCKING ); + +REG64_FLD( PERV_1_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RINGS ); +REG64_FLD( PERV_1_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_PERV_1 , SH_ACS_SCOM , + SH_FLD_RINGS_LEN ); REG64_FLD( PERV_1_XFIR_IN0 , 0 , SH_UNT_PERV_1 , SH_ACS_SCOM , SH_FLD_IN0 ); diff --git a/import/chips/p9/common/include/p9_scom_template_consts.H b/import/chips/p9/common/include/p9_scom_template_consts.H index 20185b0f..949582a9 100644 --- a/import/chips/p9/common/include/p9_scom_template_consts.H +++ b/import/chips/p9/common/include/p9_scom_template_consts.H @@ -277,47 +277,53 @@ const static uint64_t SH_UNT_PU_HTM1 = 244; const static uint64_t SH_UNT_PU_IOE = 245; const static uint64_t SH_UNT_PU_IOPPE = 246; const static uint64_t SH_UNT_PU_MCD1 = 247; -const static uint64_t SH_UNT_PU_NMMU = 248; -const static uint64_t SH_UNT_PU_NPU = 249; -const static uint64_t SH_UNT_PU_NPU0 = 250; -const static uint64_t SH_UNT_PU_NPU0_CTL = 251; -const static uint64_t SH_UNT_PU_NPU0_DAT = 252; -const static uint64_t SH_UNT_PU_NPU0_SM0 = 253; -const static uint64_t SH_UNT_PU_NPU0_SM1 = 254; -const static uint64_t SH_UNT_PU_NPU0_SM2 = 255; -const static uint64_t SH_UNT_PU_NPU0_SM3 = 256; -const static uint64_t SH_UNT_PU_NPU1 = 257; -const static uint64_t SH_UNT_PU_NPU1_CTL = 258; -const static uint64_t SH_UNT_PU_NPU1_DAT = 259; -const static uint64_t SH_UNT_PU_NPU1_SM0 = 260; -const static uint64_t SH_UNT_PU_NPU1_SM1 = 261; -const static uint64_t SH_UNT_PU_NPU1_SM2 = 262; -const static uint64_t SH_UNT_PU_NPU1_SM3 = 263; -const static uint64_t SH_UNT_PU_NPU2 = 264; -const static uint64_t SH_UNT_PU_NPU2_CTL = 265; -const static uint64_t SH_UNT_PU_NPU2_DAT = 266; -const static uint64_t SH_UNT_PU_NPU2_NTL0 = 267; -const static uint64_t SH_UNT_PU_NPU2_NTL1 = 268; -const static uint64_t SH_UNT_PU_NPU2_SM0 = 269; -const static uint64_t SH_UNT_PU_NPU2_SM1 = 270; -const static uint64_t SH_UNT_PU_NPU2_SM2 = 271; -const static uint64_t SH_UNT_PU_NPU2_SM3 = 272; -const static uint64_t SH_UNT_PU_NPU_CTL = 273; -const static uint64_t SH_UNT_PU_NPU_DAT = 274; -const static uint64_t SH_UNT_PU_NPU_NTL0 = 275; -const static uint64_t SH_UNT_PU_NPU_NTL1 = 276; -const static uint64_t SH_UNT_PU_NPU_SM0 = 277; -const static uint64_t SH_UNT_PU_NPU_SM1 = 278; -const static uint64_t SH_UNT_PU_NPU_SM2 = 279; -const static uint64_t SH_UNT_PU_OTPROM0 = 280; -const static uint64_t SH_UNT_PU_OTPROM1 = 281; -const static uint64_t SH_UNT_PU_PBAIB_STACK1 = 282; -const static uint64_t SH_UNT_PU_PBAIB_STACK2 = 283; -const static uint64_t SH_UNT_PU_PBAIB_STACK5 = 284; -const static uint64_t SH_UNT_XBUS_1 = 285; -const static uint64_t SH_UNT_XBUS_2 = 286; -const static uint64_t SH_UNT__SM0 = 287; -const static uint64_t SH_UNT__SM2 = 288; +const static uint64_t SH_UNT_PU_N0 = 248; +const static uint64_t SH_UNT_PU_N1 = 249; +const static uint64_t SH_UNT_PU_N2 = 250; +const static uint64_t SH_UNT_PU_N3 = 251; +const static uint64_t SH_UNT_PU_NMMU = 252; +const static uint64_t SH_UNT_PU_NPU = 253; +const static uint64_t SH_UNT_PU_NPU0 = 254; +const static uint64_t SH_UNT_PU_NPU0_CTL = 255; +const static uint64_t SH_UNT_PU_NPU0_DAT = 256; +const static uint64_t SH_UNT_PU_NPU0_SM0 = 257; +const static uint64_t SH_UNT_PU_NPU0_SM1 = 258; +const static uint64_t SH_UNT_PU_NPU0_SM2 = 259; +const static uint64_t SH_UNT_PU_NPU0_SM3 = 260; +const static uint64_t SH_UNT_PU_NPU1 = 261; +const static uint64_t SH_UNT_PU_NPU1_CTL = 262; +const static uint64_t SH_UNT_PU_NPU1_DAT = 263; +const static uint64_t SH_UNT_PU_NPU1_SM0 = 264; +const static uint64_t SH_UNT_PU_NPU1_SM1 = 265; +const static uint64_t SH_UNT_PU_NPU1_SM2 = 266; +const static uint64_t SH_UNT_PU_NPU1_SM3 = 267; +const static uint64_t SH_UNT_PU_NPU2 = 268; +const static uint64_t SH_UNT_PU_NPU2_CTL = 269; +const static uint64_t SH_UNT_PU_NPU2_DAT = 270; +const static uint64_t SH_UNT_PU_NPU2_NTL0 = 271; +const static uint64_t SH_UNT_PU_NPU2_NTL1 = 272; +const static uint64_t SH_UNT_PU_NPU2_SM0 = 273; +const static uint64_t SH_UNT_PU_NPU2_SM1 = 274; +const static uint64_t SH_UNT_PU_NPU2_SM2 = 275; +const static uint64_t SH_UNT_PU_NPU2_SM3 = 276; +const static uint64_t SH_UNT_PU_NPU_CTL = 277; +const static uint64_t SH_UNT_PU_NPU_DAT = 278; +const static uint64_t SH_UNT_PU_NPU_NTL0 = 279; +const static uint64_t SH_UNT_PU_NPU_NTL1 = 280; +const static uint64_t SH_UNT_PU_NPU_SM0 = 281; +const static uint64_t SH_UNT_PU_NPU_SM1 = 282; +const static uint64_t SH_UNT_PU_NPU_SM2 = 283; +const static uint64_t SH_UNT_PU_OTPROM0 = 284; +const static uint64_t SH_UNT_PU_OTPROM1 = 285; +const static uint64_t SH_UNT_PU_PBAIB_STACK1 = 286; +const static uint64_t SH_UNT_PU_PBAIB_STACK2 = 287; +const static uint64_t SH_UNT_PU_PBAIB_STACK5 = 288; +const static uint64_t SH_UNT_XBUS = 289; +const static uint64_t SH_UNT_XBUS_0 = 290; +const static uint64_t SH_UNT_XBUS_1 = 291; +const static uint64_t SH_UNT_XBUS_2 = 292; +const static uint64_t SH_UNT__SM0 = 293; +const static uint64_t SH_UNT__SM2 = 294; const static uint64_t SH_ACS_FSI = 0; @@ -360,23 +366,24 @@ const static uint64_t SH_ACS_SCOMFSI1_CLEAR = 36; const static uint64_t SH_ACS_SCOMFSI1_OR = 37; const static uint64_t SH_ACS_SCOMFSI1_RO = 38; const static uint64_t SH_ACS_SCOMFSI1_RW = 39; -const static uint64_t SH_ACS_SCOM_CLRPART = 40; -const static uint64_t SH_ACS_SCOM_NC = 41; -const static uint64_t SH_ACS_SCOM_RCLRPART = 42; -const static uint64_t SH_ACS_SCOM_RO = 43; -const static uint64_t SH_ACS_SCOM_RW = 44; -const static uint64_t SH_ACS_SCOM_W = 45; -const static uint64_t SH_ACS_SCOM_WAND = 46; -const static uint64_t SH_ACS_SCOM_WCLEAR = 47; -const static uint64_t SH_ACS_SCOM_WCLRPART = 48; -const static uint64_t SH_ACS_SCOM_WCLRREG = 49; -const static uint64_t SH_ACS_SCOM_WO = 50; -const static uint64_t SH_ACS_SCOM_WOR = 51; +const static uint64_t SH_ACS_SCOM_4P = 40; +const static uint64_t SH_ACS_SCOM_CLRPART = 41; +const static uint64_t SH_ACS_SCOM_NC = 42; +const static uint64_t SH_ACS_SCOM_RCLRPART = 43; +const static uint64_t SH_ACS_SCOM_RO = 44; +const static uint64_t SH_ACS_SCOM_RW = 45; +const static uint64_t SH_ACS_SCOM_W = 46; +const static uint64_t SH_ACS_SCOM_WAND = 47; +const static uint64_t SH_ACS_SCOM_WCLEAR = 48; +const static uint64_t SH_ACS_SCOM_WCLRPART = 49; +const static uint64_t SH_ACS_SCOM_WCLRREG = 50; +const static uint64_t SH_ACS_SCOM_WO = 51; +const static uint64_t SH_ACS_SCOM_WOR = 52; -const static uint64_t SH_FLD_0 = 0; // 472 -const static uint64_t SH_FLD_01 = 1; // 96 +const static uint64_t SH_FLD_0 = 0; // 482 +const static uint64_t SH_FLD_01 = 1; // 112 const static uint64_t SH_FLD_01_0_11 = 2; // 16 const static uint64_t SH_FLD_01_0_11_LEN = 3; // 16 const static uint64_t SH_FLD_01_12_15 = 4; // 16 @@ -387,15390 +394,17531 @@ const static uint64_t SH_FLD_01_ATESTSEL_0_4 = 8; // 8 const static uint64_t SH_FLD_01_ATESTSEL_0_4_LEN = 9; // 8 const static uint64_t SH_FLD_01_ATESTSEL_4 = 10; // 8 const static uint64_t SH_FLD_01_ATESTSEL_4_LEN = 11; // 8 -const static uint64_t SH_FLD_01_BB_LOCK0 = 12; // 16 -const static uint64_t SH_FLD_01_BB_LOCK1 = 13; // 16 -const static uint64_t SH_FLD_01_BIG_STEP_RIGHT = 14; // 16 -const static uint64_t SH_FLD_01_BIT_CENTERED = 15; // 16 -const static uint64_t SH_FLD_01_BIT_CENTERED_LEN = 16; // 16 -const static uint64_t SH_FLD_01_BLFIFO_DIS = 17; // 16 -const static uint64_t SH_FLD_01_BUMP = 18; // 16 -const static uint64_t SH_FLD_01_CALGATE_ON = 19; // 16 -const static uint64_t SH_FLD_01_CALIBRATE_BIT = 20; // 16 -const static uint64_t SH_FLD_01_CALIBRATE_BIT_LEN = 21; // 16 -const static uint64_t SH_FLD_01_CAL_ERROR = 22; // 32 -const static uint64_t SH_FLD_01_CAL_ERROR_FINE = 23; // 32 -const static uint64_t SH_FLD_01_CAL_GOOD = 24; // 32 -const static uint64_t SH_FLD_01_CHECKER_ENABLE = 25; // 16 -const static uint64_t SH_FLD_01_CHECKER_RESET = 26; // 16 -const static uint64_t SH_FLD_01_CLK16_SINGLE_ENDED = 27; // 128 -const static uint64_t SH_FLD_01_CLK18_SINGLE_ENDED = 28; // 128 -const static uint64_t SH_FLD_01_CLK20_SINGLE_ENDED = 29; // 128 -const static uint64_t SH_FLD_01_CLK22_SINGLE_ENDED = 30; // 128 -const static uint64_t SH_FLD_01_CLK_LEVEL = 31; // 16 -const static uint64_t SH_FLD_01_CLK_LEVEL_LEN = 32; // 16 -const static uint64_t SH_FLD_01_CNTL_POL = 33; // 16 -const static uint64_t SH_FLD_01_CNTL_SRC = 34; // 16 -const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N0 = 35; // 16 -const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N0_MASK = 36; // 16 -const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N1 = 37; // 16 -const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N1_MASK = 38; // 16 -const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N2 = 39; // 16 -const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N2_MASK = 40; // 16 -const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N3 = 41; // 16 -const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N3_MASK = 42; // 16 -const static uint64_t SH_FLD_01_CONTINUOUS_UPDATE = 43; // 32 -const static uint64_t SH_FLD_01_DD2_DQS_FIX_DIS = 44; // 16 -const static uint64_t SH_FLD_01_DD2_FIX_DIS = 45; // 16 -const static uint64_t SH_FLD_01_DD2_WTRFL_SYNC_DIS = 46; // 16 -const static uint64_t SH_FLD_01_DELAY1 = 47; // 16 -const static uint64_t SH_FLD_01_DELAY10 = 48; // 16 -const static uint64_t SH_FLD_01_DELAY10_LEN = 49; // 16 -const static uint64_t SH_FLD_01_DELAY11 = 50; // 16 -const static uint64_t SH_FLD_01_DELAY11_LEN = 51; // 16 -const static uint64_t SH_FLD_01_DELAY12 = 52; // 16 -const static uint64_t SH_FLD_01_DELAY12_LEN = 53; // 16 -const static uint64_t SH_FLD_01_DELAY13 = 54; // 16 -const static uint64_t SH_FLD_01_DELAY13_LEN = 55; // 16 -const static uint64_t SH_FLD_01_DELAY14 = 56; // 16 -const static uint64_t SH_FLD_01_DELAY14_LEN = 57; // 16 -const static uint64_t SH_FLD_01_DELAY15 = 58; // 16 -const static uint64_t SH_FLD_01_DELAY15_LEN = 59; // 16 -const static uint64_t SH_FLD_01_DELAY1_LEN = 60; // 16 -const static uint64_t SH_FLD_01_DELAY2 = 61; // 16 -const static uint64_t SH_FLD_01_DELAY2_LEN = 62; // 16 -const static uint64_t SH_FLD_01_DELAY3 = 63; // 16 -const static uint64_t SH_FLD_01_DELAY3_LEN = 64; // 16 -const static uint64_t SH_FLD_01_DELAY4 = 65; // 16 -const static uint64_t SH_FLD_01_DELAY4_LEN = 66; // 16 -const static uint64_t SH_FLD_01_DELAY5 = 67; // 16 -const static uint64_t SH_FLD_01_DELAY5_LEN = 68; // 16 -const static uint64_t SH_FLD_01_DELAY6 = 69; // 16 -const static uint64_t SH_FLD_01_DELAY6_LEN = 70; // 16 -const static uint64_t SH_FLD_01_DELAY7 = 71; // 16 -const static uint64_t SH_FLD_01_DELAY7_LEN = 72; // 16 -const static uint64_t SH_FLD_01_DELAY8 = 73; // 16 -const static uint64_t SH_FLD_01_DELAY8_LEN = 74; // 16 -const static uint64_t SH_FLD_01_DELAY9 = 75; // 16 -const static uint64_t SH_FLD_01_DELAY9_LEN = 76; // 16 -const static uint64_t SH_FLD_01_DELAYG = 77; // 1280 -const static uint64_t SH_FLD_01_DELAYG_LEN = 78; // 1280 -const static uint64_t SH_FLD_01_DELAY_PING_PONG_HALF = 79; // 16 -const static uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH = 80; // 16 -const static uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 81; // 16 -const static uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW = 82; // 16 -const static uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 83; // 16 -const static uint64_t SH_FLD_01_DFT_FORCE_OUTPUTS = 84; // 16 -const static uint64_t SH_FLD_01_DFT_PRBS7_GEN_EN = 85; // 16 -const static uint64_t SH_FLD_01_DIGITAL_EN = 86; // 16 -const static uint64_t SH_FLD_01_DIR_0_15 = 87; // 8 -const static uint64_t SH_FLD_01_DIR_0_15_LEN = 88; // 8 -const static uint64_t SH_FLD_01_DIR_15 = 89; // 8 -const static uint64_t SH_FLD_01_DIR_15_LEN = 90; // 8 -const static uint64_t SH_FLD_01_DISABLE_0_15 = 91; // 32 -const static uint64_t SH_FLD_01_DISABLE_0_15_LEN = 92; // 32 -const static uint64_t SH_FLD_01_DISABLE_15 = 93; // 32 -const static uint64_t SH_FLD_01_DISABLE_15_LEN = 94; // 32 -const static uint64_t SH_FLD_01_DISABLE_16_23 = 95; // 64 -const static uint64_t SH_FLD_01_DISABLE_16_23_LEN = 96; // 64 -const static uint64_t SH_FLD_01_DISABLE_PING_PONG = 97; // 16 -const static uint64_t SH_FLD_01_DISABLE_TERMINATION = 98; // 16 -const static uint64_t SH_FLD_01_DIS_CLK_GATE = 99; // 16 -const static uint64_t SH_FLD_01_DI_ADR0 = 100; // 8 -const static uint64_t SH_FLD_01_DI_ADR1 = 101; // 8 -const static uint64_t SH_FLD_01_DI_ADR10_ADR11 = 102; // 16 -const static uint64_t SH_FLD_01_DI_ADR12_ADR13 = 103; // 16 -const static uint64_t SH_FLD_01_DI_ADR14_ADR15 = 104; // 16 -const static uint64_t SH_FLD_01_DI_ADR2_ADR3 = 105; // 16 -const static uint64_t SH_FLD_01_DI_ADR4_ADR5 = 106; // 16 -const static uint64_t SH_FLD_01_DI_ADR6_ADR7 = 107; // 16 -const static uint64_t SH_FLD_01_DI_ADR8_ADR9 = 108; // 16 -const static uint64_t SH_FLD_01_DL_FORCE_ON = 109; // 16 -const static uint64_t SH_FLD_01_DONE = 110; // 32 -const static uint64_t SH_FLD_01_DQS = 111; // 16 -const static uint64_t SH_FLD_01_DQSCLK_SELECT0 = 112; // 64 -const static uint64_t SH_FLD_01_DQSCLK_SELECT0_LEN = 113; // 64 -const static uint64_t SH_FLD_01_DQSCLK_SELECT1 = 114; // 64 -const static uint64_t SH_FLD_01_DQSCLK_SELECT1_LEN = 115; // 64 -const static uint64_t SH_FLD_01_DQSCLK_SELECT2 = 116; // 64 -const static uint64_t SH_FLD_01_DQSCLK_SELECT2_LEN = 117; // 64 -const static uint64_t SH_FLD_01_DQSCLK_SELECT3 = 118; // 64 -const static uint64_t SH_FLD_01_DQSCLK_SELECT3_LEN = 119; // 64 -const static uint64_t SH_FLD_01_DQS_ALIGN_CNTR = 120; // 16 -const static uint64_t SH_FLD_01_DQS_ALIGN_CNTR_LEN = 121; // 16 -const static uint64_t SH_FLD_01_DQS_ALIGN_FIX_DIS = 122; // 16 -const static uint64_t SH_FLD_01_DQS_ALIGN_ITR_CNTR = 123; // 16 -const static uint64_t SH_FLD_01_DQS_ALIGN_ITR_CNTR_LEN = 124; // 16 -const static uint64_t SH_FLD_01_DQS_ALIGN_JITTER = 125; // 16 -const static uint64_t SH_FLD_01_DQS_ALIGN_QUAD = 126; // 16 -const static uint64_t SH_FLD_01_DQS_ALIGN_QUAD_LEN = 127; // 16 -const static uint64_t SH_FLD_01_DQS_ALIGN_SM = 128; // 16 -const static uint64_t SH_FLD_01_DQS_ALIGN_SM_LEN = 129; // 16 -const static uint64_t SH_FLD_01_DQS_LEN = 130; // 16 -const static uint64_t SH_FLD_01_DQS_PIPE_FIX_DIS = 131; // 16 -const static uint64_t SH_FLD_01_DQS_PIPE_FIX_DIS_LEN = 132; // 16 -const static uint64_t SH_FLD_01_DRIFT_ERROR = 133; // 16 -const static uint64_t SH_FLD_01_DRIFT_MASK = 134; // 16 -const static uint64_t SH_FLD_01_DRVREN_MODE = 135; // 16 -const static uint64_t SH_FLD_01_DYN_MCTERM_CNTL_EN = 136; // 16 -const static uint64_t SH_FLD_01_DYN_POWER_CNTL_EN = 137; // 16 -const static uint64_t SH_FLD_01_DYN_RX_GATE_CNTL_EN = 138; // 16 -const static uint64_t SH_FLD_01_ENABLE = 139; // 32 -const static uint64_t SH_FLD_01_ENABLE_0_15 = 140; // 8 -const static uint64_t SH_FLD_01_ENABLE_0_15_LEN = 141; // 8 -const static uint64_t SH_FLD_01_ENABLE_15 = 142; // 8 -const static uint64_t SH_FLD_01_ENABLE_15_LEN = 143; // 8 -const static uint64_t SH_FLD_01_ENABLE_16_23 = 144; // 16 -const static uint64_t SH_FLD_01_ENABLE_16_23_LEN = 145; // 16 -const static uint64_t SH_FLD_01_EN_DQS_OFFSET = 146; // 16 -const static uint64_t SH_FLD_01_EN_DRIVER_INVFB_DC = 147; // 32 -const static uint64_t SH_FLD_01_EN_N_WR = 148; // 16 -const static uint64_t SH_FLD_01_EN_N_WR_LEN = 149; // 16 -const static uint64_t SH_FLD_01_EN_P_WR = 150; // 32 -const static uint64_t SH_FLD_01_EN_P_WR_LEN = 151; // 32 -const static uint64_t SH_FLD_01_ERROR = 152; // 16 -const static uint64_t SH_FLD_01_ERROR_LEN = 153; // 16 -const static uint64_t SH_FLD_01_ERR_CLK22_MASK = 154; // 16 -const static uint64_t SH_FLD_01_EYE_CLIPPING = 155; // 16 -const static uint64_t SH_FLD_01_EYE_CLIPPING_MASK = 156; // 16 -const static uint64_t SH_FLD_01_FINE_STEPPING = 157; // 16 -const static uint64_t SH_FLD_01_FLUSH = 158; // 16 -const static uint64_t SH_FLD_01_FORCE_DQS_LANES_ON = 159; // 16 -const static uint64_t SH_FLD_01_FORCE_FIFO_CAPTURE = 160; // 16 -const static uint64_t SH_FLD_01_FRZSULV = 161; // 32 -const static uint64_t SH_FLD_01_FW_LEFT_SIDE = 162; // 16 -const static uint64_t SH_FLD_01_FW_LEFT_SIDE_LEN = 163; // 16 -const static uint64_t SH_FLD_01_FW_RIGHT_SIDE = 164; // 16 -const static uint64_t SH_FLD_01_FW_RIGHT_SIDE_LEN = 165; // 16 -const static uint64_t SH_FLD_01_HS_DLLMUX_SEL0_0_3 = 166; // 8 -const static uint64_t SH_FLD_01_HS_DLLMUX_SEL0_0_3_LEN = 167; // 8 -const static uint64_t SH_FLD_01_HS_DLLMUX_SEL0_3 = 168; // 8 -const static uint64_t SH_FLD_01_HS_DLLMUX_SEL0_3_LEN = 169; // 8 -const static uint64_t SH_FLD_01_HS_DLLMUX_SEL1_0_3 = 170; // 8 -const static uint64_t SH_FLD_01_HS_DLLMUX_SEL1_0_3_LEN = 171; // 8 -const static uint64_t SH_FLD_01_HS_DLLMUX_SEL1_3 = 172; // 8 -const static uint64_t SH_FLD_01_HS_DLLMUX_SEL1_3_LEN = 173; // 8 -const static uint64_t SH_FLD_01_HS_PROBE_A = 174; // 16 -const static uint64_t SH_FLD_01_HS_PROBE_A_LEN = 175; // 16 -const static uint64_t SH_FLD_01_HS_PROBE_B = 176; // 16 -const static uint64_t SH_FLD_01_HS_PROBE_B_LEN = 177; // 16 -const static uint64_t SH_FLD_01_HW_VALUE = 178; // 16 -const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N0 = 179; // 16 -const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N0_MASK = 180; // 16 -const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N1 = 181; // 16 -const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N1_MASK = 182; // 16 -const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N2 = 183; // 16 -const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N2_MASK = 184; // 16 -const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N3 = 185; // 16 -const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N3_MASK = 186; // 16 -const static uint64_t SH_FLD_01_INIT_IO = 187; // 16 -const static uint64_t SH_FLD_01_INIT_RXDLL_CAL_RESET = 188; // 32 -const static uint64_t SH_FLD_01_INIT_RXDLL_CAL_UPDATE = 189; // 32 -const static uint64_t SH_FLD_01_INTERP_SIG_SLEW = 190; // 16 -const static uint64_t SH_FLD_01_INTERP_SIG_SLEW_LEN = 191; // 16 -const static uint64_t SH_FLD_01_INVALID_NS_BIG_R = 192; // 16 -const static uint64_t SH_FLD_01_INVALID_NS_BIG_R_MASK = 193; // 16 -const static uint64_t SH_FLD_01_INVALID_NS_SMALL_L = 194; // 16 -const static uint64_t SH_FLD_01_INVALID_NS_SMALL_L_MASK = 195; // 16 -const static uint64_t SH_FLD_01_INVALID_NS_SMALL_R = 196; // 16 -const static uint64_t SH_FLD_01_INVALID_NS_SMALL_R_MASK = 197; // 16 -const static uint64_t SH_FLD_01_JUMP_BACK_RIGHT = 198; // 16 -const static uint64_t SH_FLD_01_LANE__0_11_PD = 199; // 16 -const static uint64_t SH_FLD_01_LANE__0_11_PD_LEN = 200; // 16 -const static uint64_t SH_FLD_01_LANE__12_15_PD = 201; // 16 -const static uint64_t SH_FLD_01_LANE__12_15_PD_LEN = 202; // 16 -const static uint64_t SH_FLD_01_LEADING_EDGE_FOUND_MASK = 203; // 16 -const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND = 204; // 16 -const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_0_15 = 205; // 8 -const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_0_15_LEN = 206; // 8 -const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_15 = 207; // 8 -const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_15_LEN = 208; // 8 -const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23 = 209; // 16 -const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23_LEN = 210; // 16 -const static uint64_t SH_FLD_01_LEN = 211; // 96 -const static uint64_t SH_FLD_01_LOOPBACK_DLY12 = 212; // 16 -const static uint64_t SH_FLD_01_LOOPBACK_FIX_EN = 213; // 16 -const static uint64_t SH_FLD_01_MATCH_STEP_RIGHT = 214; // 16 -const static uint64_t SH_FLD_01_MAX_DQS = 215; // 16 -const static uint64_t SH_FLD_01_MAX_DQS_ITER = 216; // 16 -const static uint64_t SH_FLD_01_MAX_DQS_LEN = 217; // 16 -const static uint64_t SH_FLD_01_MEMINTD00 = 218; // 16 -const static uint64_t SH_FLD_01_MEMINTD00_LEN = 219; // 16 -const static uint64_t SH_FLD_01_MEMINTD01 = 220; // 16 -const static uint64_t SH_FLD_01_MEMINTD01_LEN = 221; // 16 -const static uint64_t SH_FLD_01_MEMINTD02 = 222; // 16 -const static uint64_t SH_FLD_01_MEMINTD02_LEN = 223; // 16 -const static uint64_t SH_FLD_01_MEMINTD03 = 224; // 16 -const static uint64_t SH_FLD_01_MEMINTD03_LEN = 225; // 16 -const static uint64_t SH_FLD_01_MEMINTD04 = 226; // 16 -const static uint64_t SH_FLD_01_MEMINTD04_LEN = 227; // 16 -const static uint64_t SH_FLD_01_MEMINTD05 = 228; // 16 -const static uint64_t SH_FLD_01_MEMINTD05_LEN = 229; // 16 -const static uint64_t SH_FLD_01_MEMINTD06 = 230; // 16 -const static uint64_t SH_FLD_01_MEMINTD06_LEN = 231; // 16 -const static uint64_t SH_FLD_01_MEMINTD07 = 232; // 16 -const static uint64_t SH_FLD_01_MEMINTD07_LEN = 233; // 16 -const static uint64_t SH_FLD_01_MEMINTD08 = 234; // 16 -const static uint64_t SH_FLD_01_MEMINTD08_LEN = 235; // 16 -const static uint64_t SH_FLD_01_MEMINTD09 = 236; // 16 -const static uint64_t SH_FLD_01_MEMINTD09_LEN = 237; // 16 -const static uint64_t SH_FLD_01_MEMINTD10 = 238; // 16 -const static uint64_t SH_FLD_01_MEMINTD10_LEN = 239; // 16 -const static uint64_t SH_FLD_01_MEMINTD11 = 240; // 16 -const static uint64_t SH_FLD_01_MEMINTD11_LEN = 241; // 16 -const static uint64_t SH_FLD_01_MEMINTD12 = 242; // 16 -const static uint64_t SH_FLD_01_MEMINTD12_LEN = 243; // 16 -const static uint64_t SH_FLD_01_MEMINTD13 = 244; // 16 -const static uint64_t SH_FLD_01_MEMINTD13_LEN = 245; // 16 -const static uint64_t SH_FLD_01_MEMINTD14 = 246; // 16 -const static uint64_t SH_FLD_01_MEMINTD14_LEN = 247; // 16 -const static uint64_t SH_FLD_01_MEMINTD15 = 248; // 16 -const static uint64_t SH_FLD_01_MEMINTD15_LEN = 249; // 16 -const static uint64_t SH_FLD_01_MEMINTD16 = 250; // 16 -const static uint64_t SH_FLD_01_MEMINTD16_LEN = 251; // 16 -const static uint64_t SH_FLD_01_MEMINTD17 = 252; // 16 -const static uint64_t SH_FLD_01_MEMINTD17_LEN = 253; // 16 -const static uint64_t SH_FLD_01_MEMINTD18 = 254; // 16 -const static uint64_t SH_FLD_01_MEMINTD18_LEN = 255; // 16 -const static uint64_t SH_FLD_01_MEMINTD19 = 256; // 16 -const static uint64_t SH_FLD_01_MEMINTD19_LEN = 257; // 16 -const static uint64_t SH_FLD_01_MEMINTD20 = 258; // 16 -const static uint64_t SH_FLD_01_MEMINTD20_LEN = 259; // 16 -const static uint64_t SH_FLD_01_MEMINTD21 = 260; // 16 -const static uint64_t SH_FLD_01_MEMINTD21_LEN = 261; // 16 -const static uint64_t SH_FLD_01_MEMINTD22 = 262; // 16 -const static uint64_t SH_FLD_01_MEMINTD22_LEN = 263; // 16 -const static uint64_t SH_FLD_01_MEMINTD23 = 264; // 16 -const static uint64_t SH_FLD_01_MEMINTD23_LEN = 265; // 16 -const static uint64_t SH_FLD_01_MIN_EYE = 266; // 16 -const static uint64_t SH_FLD_01_MIN_EYE_MASK = 267; // 16 -const static uint64_t SH_FLD_01_MIN_RD_EYE_SIZE = 268; // 16 -const static uint64_t SH_FLD_01_MIN_RD_EYE_SIZE_LEN = 269; // 16 -const static uint64_t SH_FLD_01_MRS_CMD_N0 = 270; // 16 -const static uint64_t SH_FLD_01_MRS_CMD_N1 = 271; // 16 -const static uint64_t SH_FLD_01_MRS_CMD_N2 = 272; // 16 -const static uint64_t SH_FLD_01_MRS_CMD_N3 = 273; // 16 -const static uint64_t SH_FLD_01_N0 = 274; // 128 -const static uint64_t SH_FLD_01_N0_LEN = 275; // 128 -const static uint64_t SH_FLD_01_N1 = 276; // 128 -const static uint64_t SH_FLD_01_N1_LEN = 277; // 128 -const static uint64_t SH_FLD_01_N2 = 278; // 128 -const static uint64_t SH_FLD_01_N2_LEN = 279; // 128 -const static uint64_t SH_FLD_01_N3 = 280; // 128 -const static uint64_t SH_FLD_01_N3_LEN = 281; // 128 -const static uint64_t SH_FLD_01_NIB0 = 282; // 16 -const static uint64_t SH_FLD_01_NIB0TCFLIP_DC = 283; // 16 -const static uint64_t SH_FLD_01_NIB0_LEN = 284; // 16 -const static uint64_t SH_FLD_01_NIB1 = 285; // 16 -const static uint64_t SH_FLD_01_NIB1TCFLIP_DC = 286; // 16 -const static uint64_t SH_FLD_01_NIB1_LEN = 287; // 16 -const static uint64_t SH_FLD_01_NIB2 = 288; // 16 -const static uint64_t SH_FLD_01_NIB2TCFLIP_DC = 289; // 16 -const static uint64_t SH_FLD_01_NIB2_LEN = 290; // 16 -const static uint64_t SH_FLD_01_NIB3 = 291; // 16 -const static uint64_t SH_FLD_01_NIB3TCFLIP_DC = 292; // 16 -const static uint64_t SH_FLD_01_NIB3_LEN = 293; // 16 -const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_CAP = 294; // 16 -const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_CAP_LEN = 295; // 16 -const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_IND = 296; // 16 -const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_IND_LEN = 297; // 16 -const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_RES = 298; // 16 -const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_RES_LEN = 299; // 16 -const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_CAP = 300; // 16 -const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_CAP_LEN = 301; // 16 -const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_IND = 302; // 16 -const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_IND_LEN = 303; // 16 -const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_RES = 304; // 16 -const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_RES_LEN = 305; // 16 -const static uint64_t SH_FLD_01_NIB_2_DQSEL_CAP = 306; // 16 -const static uint64_t SH_FLD_01_NIB_2_DQSEL_CAP_LEN = 307; // 16 -const static uint64_t SH_FLD_01_NIB_2_DQSEL_IND = 308; // 16 -const static uint64_t SH_FLD_01_NIB_2_DQSEL_IND_LEN = 309; // 16 -const static uint64_t SH_FLD_01_NIB_2_DQSEL_RES = 310; // 16 -const static uint64_t SH_FLD_01_NIB_2_DQSEL_RES_LEN = 311; // 16 -const static uint64_t SH_FLD_01_NIB_3_DQSEL_CAP = 312; // 16 -const static uint64_t SH_FLD_01_NIB_3_DQSEL_CAP_LEN = 313; // 16 -const static uint64_t SH_FLD_01_NIB_3_DQSEL_IND = 314; // 16 -const static uint64_t SH_FLD_01_NIB_3_DQSEL_IND_LEN = 315; // 16 -const static uint64_t SH_FLD_01_NIB_3_DQSEL_RES = 316; // 16 -const static uint64_t SH_FLD_01_NIB_3_DQSEL_RES_LEN = 317; // 16 -const static uint64_t SH_FLD_01_NO_DQS = 318; // 16 -const static uint64_t SH_FLD_01_NO_DQS_MASK = 319; // 16 -const static uint64_t SH_FLD_01_NO_EYE_DETECTED = 320; // 16 -const static uint64_t SH_FLD_01_NO_EYE_DETECTED_MASK = 321; // 16 -const static uint64_t SH_FLD_01_NO_LOCK = 322; // 16 -const static uint64_t SH_FLD_01_NO_LOCK_MASK = 323; // 16 -const static uint64_t SH_FLD_01_OFFSET0 = 324; // 16 -const static uint64_t SH_FLD_01_OFFSET0_LEN = 325; // 16 -const static uint64_t SH_FLD_01_OFFSET1 = 326; // 16 -const static uint64_t SH_FLD_01_OFFSET1_LEN = 327; // 16 -const static uint64_t SH_FLD_01_OFFSET2 = 328; // 32 -const static uint64_t SH_FLD_01_OFFSET2_LEN = 329; // 32 -const static uint64_t SH_FLD_01_OFFSET3 = 330; // 32 -const static uint64_t SH_FLD_01_OFFSET3_LEN = 331; // 32 -const static uint64_t SH_FLD_01_OFFSET4 = 332; // 32 -const static uint64_t SH_FLD_01_OFFSET4_LEN = 333; // 32 -const static uint64_t SH_FLD_01_OFFSET5 = 334; // 32 -const static uint64_t SH_FLD_01_OFFSET5_LEN = 335; // 32 -const static uint64_t SH_FLD_01_OFFSET6 = 336; // 32 -const static uint64_t SH_FLD_01_OFFSET6_LEN = 337; // 32 -const static uint64_t SH_FLD_01_OFFSET7 = 338; // 32 -const static uint64_t SH_FLD_01_OFFSET7_LEN = 339; // 32 -const static uint64_t SH_FLD_01_OFFSET_ERR = 340; // 16 -const static uint64_t SH_FLD_01_OFFSET_ERR_MASK = 341; // 16 -const static uint64_t SH_FLD_01_OPERATE_MODE = 342; // 16 -const static uint64_t SH_FLD_01_OPERATE_MODE_LEN = 343; // 16 -const static uint64_t SH_FLD_01_PERCAL_PWR_DIS = 344; // 16 -const static uint64_t SH_FLD_01_PER_CAL_UPDATE_DISABLE = 345; // 16 -const static uint64_t SH_FLD_01_PHASE_ALIGN_RESET = 346; // 32 -const static uint64_t SH_FLD_01_PHASE_CNTL_EN = 347; // 32 -const static uint64_t SH_FLD_01_PHASE_DEFAULT_EN = 348; // 32 -const static uint64_t SH_FLD_01_POS_EDGE_ALIGN = 349; // 32 -const static uint64_t SH_FLD_01_QUAD0 = 350; // 16 -const static uint64_t SH_FLD_01_QUAD0_CLK16 = 351; // 128 -const static uint64_t SH_FLD_01_QUAD0_CLK18 = 352; // 128 -const static uint64_t SH_FLD_01_QUAD0_LEN = 353; // 16 -const static uint64_t SH_FLD_01_QUAD1 = 354; // 16 -const static uint64_t SH_FLD_01_QUAD1_CLK16 = 355; // 128 -const static uint64_t SH_FLD_01_QUAD1_CLK18 = 356; // 128 -const static uint64_t SH_FLD_01_QUAD1_LEN = 357; // 16 -const static uint64_t SH_FLD_01_QUAD2 = 358; // 16 -const static uint64_t SH_FLD_01_QUAD2_CLK16 = 359; // 128 -const static uint64_t SH_FLD_01_QUAD2_CLK18 = 360; // 64 -const static uint64_t SH_FLD_01_QUAD2_CLK20 = 361; // 128 -const static uint64_t SH_FLD_01_QUAD2_CLK22 = 362; // 128 -const static uint64_t SH_FLD_01_QUAD2_LEN = 363; // 16 -const static uint64_t SH_FLD_01_QUAD3 = 364; // 16 -const static uint64_t SH_FLD_01_QUAD3_CLK16 = 365; // 128 -const static uint64_t SH_FLD_01_QUAD3_CLK18 = 366; // 64 -const static uint64_t SH_FLD_01_QUAD3_CLK20 = 367; // 128 -const static uint64_t SH_FLD_01_QUAD3_CLK22 = 368; // 128 -const static uint64_t SH_FLD_01_QUAD3_LEN = 369; // 16 -const static uint64_t SH_FLD_01_RD = 370; // 272 -const static uint64_t SH_FLD_01_RDCLK_SELECT0 = 371; // 64 -const static uint64_t SH_FLD_01_RDCLK_SELECT0_LEN = 372; // 64 -const static uint64_t SH_FLD_01_RDCLK_SELECT1 = 373; // 64 -const static uint64_t SH_FLD_01_RDCLK_SELECT1_LEN = 374; // 64 -const static uint64_t SH_FLD_01_RDCLK_SELECT2 = 375; // 64 -const static uint64_t SH_FLD_01_RDCLK_SELECT2_LEN = 376; // 64 -const static uint64_t SH_FLD_01_RDCLK_SELECT3 = 377; // 64 -const static uint64_t SH_FLD_01_RDCLK_SELECT3_LEN = 378; // 64 -const static uint64_t SH_FLD_01_RD_DELAY0 = 379; // 112 -const static uint64_t SH_FLD_01_RD_DELAY0_LEN = 380; // 112 -const static uint64_t SH_FLD_01_RD_DELAY1 = 381; // 112 -const static uint64_t SH_FLD_01_RD_DELAY1_LEN = 382; // 112 -const static uint64_t SH_FLD_01_RD_DELAY2 = 383; // 112 -const static uint64_t SH_FLD_01_RD_DELAY2_LEN = 384; // 112 -const static uint64_t SH_FLD_01_RD_DELAY3 = 385; // 112 -const static uint64_t SH_FLD_01_RD_DELAY3_LEN = 386; // 112 -const static uint64_t SH_FLD_01_RD_DELAY4 = 387; // 112 -const static uint64_t SH_FLD_01_RD_DELAY4_LEN = 388; // 112 -const static uint64_t SH_FLD_01_RD_DELAY5 = 389; // 112 -const static uint64_t SH_FLD_01_RD_DELAY5_LEN = 390; // 112 -const static uint64_t SH_FLD_01_RD_DELAY6 = 391; // 112 -const static uint64_t SH_FLD_01_RD_DELAY6_LEN = 392; // 112 -const static uint64_t SH_FLD_01_RD_DELAY7 = 393; // 112 -const static uint64_t SH_FLD_01_RD_DELAY7_LEN = 394; // 112 -const static uint64_t SH_FLD_01_RD_LEN = 395; // 272 -const static uint64_t SH_FLD_01_RD_SIZE0 = 396; // 176 -const static uint64_t SH_FLD_01_RD_SIZE0_LEN = 397; // 176 -const static uint64_t SH_FLD_01_RD_SIZE1 = 398; // 176 -const static uint64_t SH_FLD_01_RD_SIZE1_LEN = 399; // 176 -const static uint64_t SH_FLD_01_RD_SIZE2 = 400; // 176 -const static uint64_t SH_FLD_01_RD_SIZE2_LEN = 401; // 176 -const static uint64_t SH_FLD_01_RD_SIZE3 = 402; // 176 -const static uint64_t SH_FLD_01_RD_SIZE3_LEN = 403; // 176 -const static uint64_t SH_FLD_01_RD_SIZE4 = 404; // 176 -const static uint64_t SH_FLD_01_RD_SIZE4_LEN = 405; // 176 -const static uint64_t SH_FLD_01_RD_SIZE5 = 406; // 176 -const static uint64_t SH_FLD_01_RD_SIZE5_LEN = 407; // 176 -const static uint64_t SH_FLD_01_RD_SIZE6 = 408; // 176 -const static uint64_t SH_FLD_01_RD_SIZE6_LEN = 409; // 176 -const static uint64_t SH_FLD_01_RD_SIZE7 = 410; // 176 -const static uint64_t SH_FLD_01_RD_SIZE7_LEN = 411; // 176 -const static uint64_t SH_FLD_01_READ_CENTERING_MODE = 412; // 16 -const static uint64_t SH_FLD_01_READ_CENTERING_MODE_LEN = 413; // 16 -const static uint64_t SH_FLD_01_REFERENCE1 = 414; // 16 -const static uint64_t SH_FLD_01_REFERENCE1_LEN = 415; // 16 -const static uint64_t SH_FLD_01_REFERENCE2 = 416; // 16 -const static uint64_t SH_FLD_01_REFERENCE2_LEN = 417; // 16 -const static uint64_t SH_FLD_01_REFERENCE3 = 418; // 16 -const static uint64_t SH_FLD_01_REFERENCE3_LEN = 419; // 16 -const static uint64_t SH_FLD_01_REGS_RXDLL_CAL_SKIP = 420; // 32 -const static uint64_t SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN = 421; // 32 -const static uint64_t SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 = 422; // 32 -const static uint64_t SH_FLD_01_REGS_RXDLL_COARSE_EN = 423; // 32 -const static uint64_t SH_FLD_01_REGS_RXDLL_COARSE_EN_LEN = 424; // 32 -const static uint64_t SH_FLD_01_REGS_RXDLL_DAC_COARSE = 425; // 32 -const static uint64_t SH_FLD_01_REGS_RXDLL_DAC_COARSE_LEN = 426; // 32 -const static uint64_t SH_FLD_01_REGS_RXDLL_VREG_LOWER = 427; // 32 -const static uint64_t SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN = 428; // 32 -const static uint64_t SH_FLD_01_REGS_RXDLL_VREG_UPPER = 429; // 32 -const static uint64_t SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN = 430; // 32 -const static uint64_t SH_FLD_01_RESERVED_56_63 = 431; // 16 -const static uint64_t SH_FLD_01_RESERVED_56_63_LEN = 432; // 16 -const static uint64_t SH_FLD_01_ROT0 = 433; // 16 -const static uint64_t SH_FLD_01_ROT0_LEN = 434; // 16 -const static uint64_t SH_FLD_01_ROT1 = 435; // 16 -const static uint64_t SH_FLD_01_ROT1_LEN = 436; // 16 -const static uint64_t SH_FLD_01_ROT_CLK_N0 = 437; // 128 -const static uint64_t SH_FLD_01_ROT_CLK_N0_LEN = 438; // 128 -const static uint64_t SH_FLD_01_ROT_CLK_N1 = 439; // 128 -const static uint64_t SH_FLD_01_ROT_CLK_N1_LEN = 440; // 128 -const static uint64_t SH_FLD_01_ROT_N0 = 441; // 128 -const static uint64_t SH_FLD_01_ROT_N0_LEN = 442; // 128 -const static uint64_t SH_FLD_01_ROT_N1 = 443; // 128 -const static uint64_t SH_FLD_01_ROT_N1_LEN = 444; // 128 -const static uint64_t SH_FLD_01_ROT_OVERRIDE = 445; // 32 -const static uint64_t SH_FLD_01_ROT_OVERRIDE_EN = 446; // 32 -const static uint64_t SH_FLD_01_ROT_OVERRIDE_LEN = 447; // 32 -const static uint64_t SH_FLD_01_RXREG_COMPCON_DC = 448; // 32 -const static uint64_t SH_FLD_01_RXREG_COMPCON_DC_LEN = 449; // 32 -const static uint64_t SH_FLD_01_RXREG_CON_DC = 450; // 32 -const static uint64_t SH_FLD_01_RXREG_DAC_PULLUP_DC = 451; // 32 -const static uint64_t SH_FLD_01_RXREG_DRVCON_DC = 452; // 32 -const static uint64_t SH_FLD_01_RXREG_DRVCON_DC_LEN = 453; // 32 -const static uint64_t SH_FLD_01_RXREG_FILTER_LENGTH_DC = 454; // 32 -const static uint64_t SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN = 455; // 32 -const static uint64_t SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC = 456; // 32 -const static uint64_t SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 457; // 32 -const static uint64_t SH_FLD_01_RXREG_REF_SEL_DC = 458; // 32 -const static uint64_t SH_FLD_01_RXREG_REF_SEL_DC_LEN = 459; // 32 -const static uint64_t SH_FLD_01_S0ACENSLICENDRV_DC = 460; // 16 -const static uint64_t SH_FLD_01_S0ACENSLICENDRV_DC_LEN = 461; // 16 -const static uint64_t SH_FLD_01_S0ACENSLICEPDRV_DC = 462; // 16 -const static uint64_t SH_FLD_01_S0ACENSLICEPDRV_DC_LEN = 463; // 16 -const static uint64_t SH_FLD_01_S0ACENSLICEPTERM_DC = 464; // 16 -const static uint64_t SH_FLD_01_S0ACENSLICEPTERM_DC_LEN = 465; // 16 -const static uint64_t SH_FLD_01_S0INSDLYTAP = 466; // 16 -const static uint64_t SH_FLD_01_S1ACENSLICENDRV_DC = 467; // 16 -const static uint64_t SH_FLD_01_S1ACENSLICENDRV_DC_LEN = 468; // 16 -const static uint64_t SH_FLD_01_S1ACENSLICEPDRV_DC = 469; // 16 -const static uint64_t SH_FLD_01_S1ACENSLICEPDRV_DC_LEN = 470; // 16 -const static uint64_t SH_FLD_01_S1ACENSLICEPTERM_DC = 471; // 16 -const static uint64_t SH_FLD_01_S1ACENSLICEPTERM_DC_LEN = 472; // 16 -const static uint64_t SH_FLD_01_S1INSDLYTAP = 473; // 16 -const static uint64_t SH_FLD_01_SEL0 = 474; // 32 -const static uint64_t SH_FLD_01_SEL0_LEN = 475; // 16 -const static uint64_t SH_FLD_01_SEL1 = 476; // 32 -const static uint64_t SH_FLD_01_SEL10 = 477; // 32 -const static uint64_t SH_FLD_01_SEL10_LEN = 478; // 32 -const static uint64_t SH_FLD_01_SEL11 = 479; // 32 -const static uint64_t SH_FLD_01_SEL11_LEN = 480; // 32 -const static uint64_t SH_FLD_01_SEL12 = 481; // 32 -const static uint64_t SH_FLD_01_SEL12_LEN = 482; // 32 -const static uint64_t SH_FLD_01_SEL13 = 483; // 32 -const static uint64_t SH_FLD_01_SEL13_LEN = 484; // 32 -const static uint64_t SH_FLD_01_SEL14 = 485; // 32 -const static uint64_t SH_FLD_01_SEL14_LEN = 486; // 32 -const static uint64_t SH_FLD_01_SEL15 = 487; // 32 -const static uint64_t SH_FLD_01_SEL15_LEN = 488; // 32 -const static uint64_t SH_FLD_01_SEL1_LEN = 489; // 32 -const static uint64_t SH_FLD_01_SEL2 = 490; // 32 -const static uint64_t SH_FLD_01_SEL2_LEN = 491; // 32 -const static uint64_t SH_FLD_01_SEL3 = 492; // 32 -const static uint64_t SH_FLD_01_SEL3_LEN = 493; // 32 -const static uint64_t SH_FLD_01_SEL4 = 494; // 32 -const static uint64_t SH_FLD_01_SEL4_LEN = 495; // 32 -const static uint64_t SH_FLD_01_SEL5 = 496; // 32 -const static uint64_t SH_FLD_01_SEL5_LEN = 497; // 32 -const static uint64_t SH_FLD_01_SEL6 = 498; // 32 -const static uint64_t SH_FLD_01_SEL6_LEN = 499; // 32 -const static uint64_t SH_FLD_01_SEL7 = 500; // 32 -const static uint64_t SH_FLD_01_SEL7_LEN = 501; // 32 -const static uint64_t SH_FLD_01_SEL8 = 502; // 32 -const static uint64_t SH_FLD_01_SEL8_LEN = 503; // 16 -const static uint64_t SH_FLD_01_SEL9 = 504; // 32 -const static uint64_t SH_FLD_01_SEL9_LEN = 505; // 32 -const static uint64_t SH_FLD_01_SMALL_STEP_LEFT = 506; // 16 -const static uint64_t SH_FLD_01_SMALL_STEP_RIGHT = 507; // 16 -const static uint64_t SH_FLD_01_SYNC = 508; // 16 -const static uint64_t SH_FLD_01_SYNC_LEN = 509; // 16 -const static uint64_t SH_FLD_01_SYSCLK_DQSCLK_OFFSET = 510; // 16 -const static uint64_t SH_FLD_01_SYSCLK_DQSCLK_OFFSET_LEN = 511; // 16 -const static uint64_t SH_FLD_01_SYSCLK_RDCLK_OFFSET = 512; // 16 -const static uint64_t SH_FLD_01_SYSCLK_RDCLK_OFFSET_LEN = 513; // 16 -const static uint64_t SH_FLD_01_TEST_4TO1_MODE = 514; // 16 -const static uint64_t SH_FLD_01_TEST_CHECK_EN = 515; // 16 -const static uint64_t SH_FLD_01_TEST_CLEAR_ERROR = 516; // 16 -const static uint64_t SH_FLD_01_TEST_DATA_EN = 517; // 16 -const static uint64_t SH_FLD_01_TEST_GEN_EN = 518; // 16 -const static uint64_t SH_FLD_01_TEST_LANE_PAIR_FAIL = 519; // 16 -const static uint64_t SH_FLD_01_TEST_LANE_PAIR_FAIL_LEN = 520; // 16 -const static uint64_t SH_FLD_01_TEST_MODE = 521; // 16 -const static uint64_t SH_FLD_01_TEST_MODE_LEN = 522; // 16 -const static uint64_t SH_FLD_01_TEST_RESET = 523; // 16 -const static uint64_t SH_FLD_01_TRAILING_EDGE_FOUND_MASK = 524; // 16 -const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND = 525; // 16 -const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15 = 526; // 8 -const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 527; // 8 -const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15 = 528; // 8 -const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15_LEN = 529; // 8 -const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23 = 530; // 16 -const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 531; // 16 -const static uint64_t SH_FLD_01_TRIG_PERIOD = 532; // 16 -const static uint64_t SH_FLD_01_TSYS = 533; // 16 -const static uint64_t SH_FLD_01_TSYS_LEN = 534; // 16 -const static uint64_t SH_FLD_01_TUNEATST = 535; // 16 -const static uint64_t SH_FLD_01_TUNEATST_0 = 536; // 8 -const static uint64_t SH_FLD_01_TUNEATST_1 = 537; // 8 -const static uint64_t SH_FLD_01_VALID_NS_BIG_L = 538; // 16 -const static uint64_t SH_FLD_01_VALID_NS_BIG_L_MASK = 539; // 16 -const static uint64_t SH_FLD_01_VALID_NS_BIG_R = 540; // 16 -const static uint64_t SH_FLD_01_VALID_NS_BIG_R_MASK = 541; // 16 -const static uint64_t SH_FLD_01_VALID_NS_JUMP_BACK = 542; // 16 -const static uint64_t SH_FLD_01_VALID_NS_JUMP_BACK_MASK = 543; // 16 -const static uint64_t SH_FLD_01_WL_ADVANCE_DISABLE = 544; // 16 -const static uint64_t SH_FLD_01_WL_ERR_CLK16 = 545; // 32 -const static uint64_t SH_FLD_01_WL_ERR_CLK16_MASK = 546; // 16 -const static uint64_t SH_FLD_01_WL_ERR_CLK18 = 547; // 32 -const static uint64_t SH_FLD_01_WL_ERR_CLK18_MASK = 548; // 16 -const static uint64_t SH_FLD_01_WL_ERR_CLK20 = 549; // 32 -const static uint64_t SH_FLD_01_WL_ERR_CLK20_MASK = 550; // 16 -const static uint64_t SH_FLD_01_WL_ERR_CLK22 = 551; // 32 -const static uint64_t SH_FLD_01_WRAPSEL = 552; // 16 -const static uint64_t SH_FLD_01_WTRFL_AVE_DIS = 553; // 16 -const static uint64_t SH_FLD_01_ZERO_DETECTED = 554; // 16 -const static uint64_t SH_FLD_0X00_DATA_PARITY = 555; // 4 -const static uint64_t SH_FLD_0X00_SPARE_30_31 = 556; // 1 -const static uint64_t SH_FLD_0X00_SPARE_30_31_LEN = 557; // 1 -const static uint64_t SH_FLD_0X01_DATA_PARITY = 558; // 4 -const static uint64_t SH_FLD_0X01_SPARE_03 = 559; // 1 -const static uint64_t SH_FLD_0X01_SPARE_28_31 = 560; // 1 -const static uint64_t SH_FLD_0X01_SPARE_28_31_LEN = 561; // 1 -const static uint64_t SH_FLD_0X02_DATA_PARITY = 562; // 4 -const static uint64_t SH_FLD_0X02_SPARE_03 = 563; // 1 -const static uint64_t SH_FLD_0X02_SPARE_28_31 = 564; // 1 -const static uint64_t SH_FLD_0X02_SPARE_28_31_LEN = 565; // 1 -const static uint64_t SH_FLD_0X03_DATA_PARITY = 566; // 4 -const static uint64_t SH_FLD_0X03_SPARE_03 = 567; // 1 -const static uint64_t SH_FLD_0X03_SPARE_28_31 = 568; // 1 -const static uint64_t SH_FLD_0X03_SPARE_28_31_LEN = 569; // 1 -const static uint64_t SH_FLD_0X04_DATA_PARITY = 570; // 4 -const static uint64_t SH_FLD_0X04_SPARE_03 = 571; // 1 -const static uint64_t SH_FLD_0X04_SPARE_28_31 = 572; // 1 -const static uint64_t SH_FLD_0X04_SPARE_28_31_LEN = 573; // 1 -const static uint64_t SH_FLD_0X05_DATA_PARITY = 574; // 4 -const static uint64_t SH_FLD_0X05_SPARE_01 = 575; // 1 -const static uint64_t SH_FLD_0X05_SPARE_05 = 576; // 1 -const static uint64_t SH_FLD_0X06_DATA_PARITY = 577; // 4 -const static uint64_t SH_FLD_0X06_SPARE_02_04 = 578; // 1 -const static uint64_t SH_FLD_0X06_SPARE_02_04_LEN = 579; // 1 -const static uint64_t SH_FLD_0X06_SPARE_16_21 = 580; // 1 -const static uint64_t SH_FLD_0X06_SPARE_16_21_LEN = 581; // 1 -const static uint64_t SH_FLD_0X07_DATA_PARITY = 582; // 4 -const static uint64_t SH_FLD_0X07_SPARE_19 = 583; // 1 -const static uint64_t SH_FLD_0X07_SPARE_20 = 584; // 1 -const static uint64_t SH_FLD_0X07_SPARE_22_31 = 585; // 1 -const static uint64_t SH_FLD_0X07_SPARE_22_31_LEN = 586; // 1 -const static uint64_t SH_FLD_0X08_DATA_PARITY = 587; // 4 -const static uint64_t SH_FLD_0X08_SPARE_03 = 588; // 1 -const static uint64_t SH_FLD_0X08_SPARE_30 = 589; // 1 -const static uint64_t SH_FLD_0X09_DATA_PARITY = 590; // 4 -const static uint64_t SH_FLD_0X0A_DATA_PARITY = 591; // 4 -const static uint64_t SH_FLD_0X0A_SPARE_13_15 = 592; // 1 -const static uint64_t SH_FLD_0X0A_SPARE_13_15_LEN = 593; // 1 -const static uint64_t SH_FLD_0X0B_DATA_PARITY = 594; // 4 -const static uint64_t SH_FLD_0X0B_SPARE_04_05 = 595; // 1 -const static uint64_t SH_FLD_0X0B_SPARE_04_05_LEN = 596; // 1 -const static uint64_t SH_FLD_0X0B_SPARE_17 = 597; // 1 -const static uint64_t SH_FLD_0X0B_SPARE_33_39 = 598; // 1 -const static uint64_t SH_FLD_0X0B_SPARE_33_39_LEN = 599; // 1 -const static uint64_t SH_FLD_0X0C_DATA_PARITY = 600; // 4 -const static uint64_t SH_FLD_0X0D_SPARE_60_62 = 601; // 1 -const static uint64_t SH_FLD_0X0D_SPARE_60_62_LEN = 602; // 1 -const static uint64_t SH_FLD_0X10_DATA_PARITY = 603; // 4 -const static uint64_t SH_FLD_0X10_SPARE_17_18 = 604; // 1 -const static uint64_t SH_FLD_0X10_SPARE_17_18_LEN = 605; // 1 -const static uint64_t SH_FLD_0X10_SPARE_19_23 = 606; // 1 -const static uint64_t SH_FLD_0X10_SPARE_19_23_LEN = 607; // 1 -const static uint64_t SH_FLD_0X10_SPARE_24_25 = 608; // 1 -const static uint64_t SH_FLD_0X10_SPARE_24_25_LEN = 609; // 1 -const static uint64_t SH_FLD_0X10_SPARE_27 = 610; // 1 -const static uint64_t SH_FLD_0X10_SPARE_29 = 611; // 1 -const static uint64_t SH_FLD_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY = 612; // 4 -const static uint64_t SH_FLD_0X17_0X18_0X21_0X22_DATA_PARITY = 613; // 4 -const static uint64_t SH_FLD_0X1D_0X1E_0X1F_DATA_PARITY = 614; // 4 -const static uint64_t SH_FLD_0X20_DATA_PARITY = 615; // 4 -const static uint64_t SH_FLD_0X22_SPARE_01 = 616; // 1 -const static uint64_t SH_FLD_0X22_SPARE_03_07 = 617; // 1 -const static uint64_t SH_FLD_0X22_SPARE_03_07_LEN = 618; // 1 -const static uint64_t SH_FLD_0X23_DATA_PARITY = 619; // 4 -const static uint64_t SH_FLD_0X23_SPARE_06_07 = 620; // 1 -const static uint64_t SH_FLD_0X23_SPARE_06_07_LEN = 621; // 1 -const static uint64_t SH_FLD_0X24_DATA_PARITY = 622; // 4 -const static uint64_t SH_FLD_0X24_SPARE_05_07 = 623; // 1 -const static uint64_t SH_FLD_0X24_SPARE_05_07_LEN = 624; // 1 -const static uint64_t SH_FLD_0X27_DATA_PARITY = 625; // 4 -const static uint64_t SH_FLD_0X27_SPARE_34 = 626; // 1 -const static uint64_t SH_FLD_0X27_SPARE_36 = 627; // 1 -const static uint64_t SH_FLD_0X29_DATA_PARITY = 628; // 4 -const static uint64_t SH_FLD_0X30_0X31_0X32_0X33_DATA_PARITY = 629; // 4 -const static uint64_t SH_FLD_0_2 = 630; // 16 -const static uint64_t SH_FLD_0_CANNED_0 = 631; // 2 -const static uint64_t SH_FLD_0_CANNED_0_LEN = 632; // 2 -const static uint64_t SH_FLD_0_CANNED_1 = 633; // 2 -const static uint64_t SH_FLD_0_CANNED_1_LEN = 634; // 2 -const static uint64_t SH_FLD_0_CPS = 635; // 2 -const static uint64_t SH_FLD_0_CPS_LEN = 636; // 2 -const static uint64_t SH_FLD_0_DATA = 637; // 1 -const static uint64_t SH_FLD_0_DATA_LEN = 638; // 1 -const static uint64_t SH_FLD_0_LEN = 639; // 54 -const static uint64_t SH_FLD_0_LOCAL_STEP_MODE_ENABLE = 640; // 1 -const static uint64_t SH_FLD_0_OSC_NOT_VALID = 641; // 1 -const static uint64_t SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT = 642; // 1 -const static uint64_t SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT_LEN = 643; // 1 -const static uint64_t SH_FLD_0_RESULT = 644; // 43 -const static uint64_t SH_FLD_0_RESULT_LEN = 645; // 43 -const static uint64_t SH_FLD_0_SELECT = 646; // 1 -const static uint64_t SH_FLD_0_SELECT_LEN = 647; // 1 -const static uint64_t SH_FLD_0_SPARE_SECTOR_BUFFER_CONTROL = 648; // 1 -const static uint64_t SH_FLD_0_STEP_ALIGN_DISABLE = 649; // 1 -const static uint64_t SH_FLD_0_STEP_ALIGN_THRESHOLD = 650; // 1 -const static uint64_t SH_FLD_0_STEP_ALIGN_THRESHOLD_LEN = 651; // 1 -const static uint64_t SH_FLD_0_STEP_CHECK_CONSTANT_CPS_ENABLE = 652; // 2 -const static uint64_t SH_FLD_0_STEP_CHECK_CPS_DEVIATION = 653; // 2 -const static uint64_t SH_FLD_0_STEP_CHECK_CPS_DEVIATION_LEN = 654; // 2 -const static uint64_t SH_FLD_0_STEP_CHECK_VALIDITY_COUNT = 655; // 2 -const static uint64_t SH_FLD_0_STEP_CHECK_VALIDITY_COUNT_LEN = 656; // 2 -const static uint64_t SH_FLD_0_STEP_STEER_ENABLE = 657; // 1 -const static uint64_t SH_FLD_1 = 658; // 515 -const static uint64_t SH_FLD_10 = 659; // 6 -const static uint64_t SH_FLD_10_RESERVED = 660; // 1 -const static uint64_t SH_FLD_10_SPARE_REFCLOCK = 661; // 1 -const static uint64_t SH_FLD_10_SPARE_SECTOR_BUFFER_CONTROL = 662; // 1 -const static uint64_t SH_FLD_11 = 663; // 6 -const static uint64_t SH_FLD_11_RESERVED = 664; // 1 -const static uint64_t SH_FLD_11_SPARE_REFCLOCK = 665; // 1 -const static uint64_t SH_FLD_11_SPARE_SECTOR_BUFFER_CONTROL = 666; // 1 -const static uint64_t SH_FLD_12 = 667; // 6 -const static uint64_t SH_FLD_12GB_ENABLE = 668; // 8 -const static uint64_t SH_FLD_12_RESERVED = 669; // 1 -const static uint64_t SH_FLD_12_SPARE_SECTOR_BUFFER_CONTROL = 670; // 1 -const static uint64_t SH_FLD_13 = 671; // 6 -const static uint64_t SH_FLD_13_RESERVED = 672; // 1 -const static uint64_t SH_FLD_13_SPARE_OPB_CONTROL = 673; // 1 -const static uint64_t SH_FLD_13_SPARE_PROBE = 674; // 1 -const static uint64_t SH_FLD_13_SPARE_SECTOR_BUFFER_CONTROL = 675; // 1 -const static uint64_t SH_FLD_14 = 676; // 6 -const static uint64_t SH_FLD_14_RESERVED = 677; // 1 -const static uint64_t SH_FLD_14_SPARE_OPB_CONTROL = 678; // 1 -const static uint64_t SH_FLD_14_SPARE_PLL = 679; // 1 -const static uint64_t SH_FLD_14_SPARE_PROBE = 680; // 1 -const static uint64_t SH_FLD_14_SPARE_SECTOR_BUFFER_CONTROL = 681; // 1 -const static uint64_t SH_FLD_15 = 682; // 6 -const static uint64_t SH_FLD_15_RESERVED = 683; // 1 -const static uint64_t SH_FLD_15_SPARE_OPB_CONTROL = 684; // 1 -const static uint64_t SH_FLD_15_SPARE_OSC = 685; // 1 -const static uint64_t SH_FLD_15_SPARE_PLL = 686; // 1 -const static uint64_t SH_FLD_15_SPARE_PROBE = 687; // 1 -const static uint64_t SH_FLD_15_SPARE_SECTOR_BUFFER_CONTROL = 688; // 1 -const static uint64_t SH_FLD_16 = 689; // 6 -const static uint64_t SH_FLD_16_FREE_USAGE = 690; // 1 -const static uint64_t SH_FLD_16_SPARE_OSC = 691; // 1 -const static uint64_t SH_FLD_16_SPARE_RESONANT_CLOCKING_CONTROL = 692; // 1 -const static uint64_t SH_FLD_17 = 693; // 6 -const static uint64_t SH_FLD_17_SPARE_OSC = 694; // 1 -const static uint64_t SH_FLD_17_SPARE_RESONANT_CLOCKING_CONTROL = 695; // 1 -const static uint64_t SH_FLD_18 = 696; // 6 -const static uint64_t SH_FLD_18_31_SPARE = 697; // 8 -const static uint64_t SH_FLD_18_31_SPARE_LEN = 698; // 8 -const static uint64_t SH_FLD_18_SPARE_MUX_CONTROL = 699; // 1 -const static uint64_t SH_FLD_18_SPARE_OSC = 700; // 1 -const static uint64_t SH_FLD_18_SPARE_RESONANT_CLOCKING_CONTROL = 701; // 1 -const static uint64_t SH_FLD_19 = 702; // 6 -const static uint64_t SH_FLD_19_SPARE_MUX_CONTROL = 703; // 1 -const static uint64_t SH_FLD_19_SPARE_OSC = 704; // 1 -const static uint64_t SH_FLD_19_SPARE_RESONANT_CLOCKING_CONTROL = 705; // 1 -const static uint64_t SH_FLD_1_3 = 706; // 16 -const static uint64_t SH_FLD_1_CANNED_0 = 707; // 2 -const static uint64_t SH_FLD_1_CANNED_0_LEN = 708; // 2 -const static uint64_t SH_FLD_1_CANNED_1 = 709; // 2 -const static uint64_t SH_FLD_1_CANNED_1_LEN = 710; // 2 -const static uint64_t SH_FLD_1_CPS = 711; // 2 -const static uint64_t SH_FLD_1_CPS_LEN = 712; // 2 -const static uint64_t SH_FLD_1_DATA = 713; // 1 -const static uint64_t SH_FLD_1_DATA_LEN = 714; // 1 -const static uint64_t SH_FLD_1_LEN = 715; // 97 -const static uint64_t SH_FLD_1_LOCAL_STEP_MODE_ENABLE = 716; // 1 -const static uint64_t SH_FLD_1_OSC_NOT_VALID = 717; // 1 -const static uint64_t SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT = 718; // 1 -const static uint64_t SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT_LEN = 719; // 1 -const static uint64_t SH_FLD_1_RESULT = 720; // 43 -const static uint64_t SH_FLD_1_RESULT_LEN = 721; // 43 -const static uint64_t SH_FLD_1_SELECT = 722; // 1 -const static uint64_t SH_FLD_1_SELECT_LEN = 723; // 1 -const static uint64_t SH_FLD_1_SPARE_SECTOR_BUFFER_CONTROL = 724; // 1 -const static uint64_t SH_FLD_1_STEP_ALIGN_DISABLE = 725; // 1 -const static uint64_t SH_FLD_1_STEP_ALIGN_THRESHOLD = 726; // 1 -const static uint64_t SH_FLD_1_STEP_ALIGN_THRESHOLD_LEN = 727; // 1 -const static uint64_t SH_FLD_1_STEP_CHECK_CONSTANT_CPS_ENABLE = 728; // 2 -const static uint64_t SH_FLD_1_STEP_CHECK_CPS_DEVIATION = 729; // 2 -const static uint64_t SH_FLD_1_STEP_CHECK_CPS_DEVIATION_LEN = 730; // 2 -const static uint64_t SH_FLD_1_STEP_CHECK_VALIDITY_COUNT = 731; // 2 -const static uint64_t SH_FLD_1_STEP_CHECK_VALIDITY_COUNT_LEN = 732; // 2 -const static uint64_t SH_FLD_1_STEP_STEER_ENABLE = 733; // 1 -const static uint64_t SH_FLD_2 = 734; // 464 -const static uint64_t SH_FLD_20 = 735; // 6 -const static uint64_t SH_FLD_20_FREE_USAGE = 736; // 1 -const static uint64_t SH_FLD_20_RESERVED = 737; // 1 -const static uint64_t SH_FLD_20_SPARE_OSC = 738; // 1 -const static uint64_t SH_FLD_20_SPARE_PLL_CONTROL = 739; // 1 -const static uint64_t SH_FLD_20_SPARE_RESONANT_CLOCKING_CONTROL = 740; // 1 -const static uint64_t SH_FLD_21 = 741; // 6 -const static uint64_t SH_FLD_21_FREE_USAGE = 742; // 1 -const static uint64_t SH_FLD_21_RESERVED = 743; // 1 -const static uint64_t SH_FLD_21_SPARE_OSC = 744; // 1 -const static uint64_t SH_FLD_21_SPARE_PLL_CONTROL = 745; // 1 -const static uint64_t SH_FLD_21_SPARE_RESONANT_CLOCKING_CONTROL = 746; // 1 -const static uint64_t SH_FLD_22 = 747; // 6 -const static uint64_t SH_FLD_22_FREE_USAGE = 748; // 1 -const static uint64_t SH_FLD_22_RESERVED = 749; // 2 -const static uint64_t SH_FLD_22_SPARE_OSC = 750; // 1 -const static uint64_t SH_FLD_22_SPARE_PLL_CONTROL = 751; // 1 -const static uint64_t SH_FLD_22_SPARE_RESONANT_CLOCKING_CONTROL = 752; // 1 -const static uint64_t SH_FLD_22_SPARE_TEST = 753; // 1 -const static uint64_t SH_FLD_23 = 754; // 102 -const static uint64_t SH_FLD_23_0_11 = 755; // 16 -const static uint64_t SH_FLD_23_0_11_LEN = 756; // 16 -const static uint64_t SH_FLD_23_12_15 = 757; // 16 -const static uint64_t SH_FLD_23_12_15_LEN = 758; // 16 -const static uint64_t SH_FLD_23_ADVANCE_PING_PONG = 759; // 16 -const static uint64_t SH_FLD_23_ADVANCE_PR_VALUE = 760; // 16 -const static uint64_t SH_FLD_23_ATESTSEL_0_4 = 761; // 16 -const static uint64_t SH_FLD_23_ATESTSEL_0_4_LEN = 762; // 16 -const static uint64_t SH_FLD_23_BB_LOCK0 = 763; // 16 -const static uint64_t SH_FLD_23_BB_LOCK1 = 764; // 16 -const static uint64_t SH_FLD_23_BIG_STEP_RIGHT = 765; // 16 -const static uint64_t SH_FLD_23_BIT_CENTERED = 766; // 16 -const static uint64_t SH_FLD_23_BIT_CENTERED_LEN = 767; // 16 -const static uint64_t SH_FLD_23_BLFIFO_DIS = 768; // 16 -const static uint64_t SH_FLD_23_BUMP = 769; // 16 -const static uint64_t SH_FLD_23_CALGATE_ON = 770; // 16 -const static uint64_t SH_FLD_23_CALIBRATE_BIT = 771; // 16 -const static uint64_t SH_FLD_23_CALIBRATE_BIT_LEN = 772; // 16 -const static uint64_t SH_FLD_23_CAL_ERROR = 773; // 32 -const static uint64_t SH_FLD_23_CAL_ERROR_FINE = 774; // 32 -const static uint64_t SH_FLD_23_CAL_GOOD = 775; // 32 -const static uint64_t SH_FLD_23_CHECKER_ENABLE = 776; // 16 -const static uint64_t SH_FLD_23_CHECKER_RESET = 777; // 16 -const static uint64_t SH_FLD_23_CLK16_SINGLE_ENDED = 778; // 128 -const static uint64_t SH_FLD_23_CLK18_SINGLE_ENDED = 779; // 128 -const static uint64_t SH_FLD_23_CLK20_SINGLE_ENDED = 780; // 128 -const static uint64_t SH_FLD_23_CLK22_SINGLE_ENDED = 781; // 128 -const static uint64_t SH_FLD_23_CLK_LEVEL = 782; // 16 -const static uint64_t SH_FLD_23_CLK_LEVEL_LEN = 783; // 16 -const static uint64_t SH_FLD_23_CNTL_POL = 784; // 16 -const static uint64_t SH_FLD_23_CNTL_SRC = 785; // 16 -const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N0 = 786; // 16 -const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N0_MASK = 787; // 16 -const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N1 = 788; // 16 -const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N1_MASK = 789; // 16 -const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N2 = 790; // 16 -const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N2_MASK = 791; // 16 -const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N3 = 792; // 16 -const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N3_MASK = 793; // 16 -const static uint64_t SH_FLD_23_CONTINUOUS_UPDATE = 794; // 32 -const static uint64_t SH_FLD_23_DD2_DQS_FIX_DIS = 795; // 16 -const static uint64_t SH_FLD_23_DD2_FIX_DIS = 796; // 16 -const static uint64_t SH_FLD_23_DD2_WTRFL_SYNC_DIS = 797; // 16 -const static uint64_t SH_FLD_23_DELAY1 = 798; // 16 -const static uint64_t SH_FLD_23_DELAY10 = 799; // 16 -const static uint64_t SH_FLD_23_DELAY10_LEN = 800; // 16 -const static uint64_t SH_FLD_23_DELAY11 = 801; // 16 -const static uint64_t SH_FLD_23_DELAY11_LEN = 802; // 16 -const static uint64_t SH_FLD_23_DELAY12 = 803; // 16 -const static uint64_t SH_FLD_23_DELAY12_LEN = 804; // 16 -const static uint64_t SH_FLD_23_DELAY13 = 805; // 16 -const static uint64_t SH_FLD_23_DELAY13_LEN = 806; // 16 -const static uint64_t SH_FLD_23_DELAY14 = 807; // 16 -const static uint64_t SH_FLD_23_DELAY14_LEN = 808; // 16 -const static uint64_t SH_FLD_23_DELAY15 = 809; // 16 -const static uint64_t SH_FLD_23_DELAY15_LEN = 810; // 16 -const static uint64_t SH_FLD_23_DELAY1_LEN = 811; // 16 -const static uint64_t SH_FLD_23_DELAY2 = 812; // 16 -const static uint64_t SH_FLD_23_DELAY2_LEN = 813; // 16 -const static uint64_t SH_FLD_23_DELAY3 = 814; // 16 -const static uint64_t SH_FLD_23_DELAY3_LEN = 815; // 16 -const static uint64_t SH_FLD_23_DELAY4 = 816; // 16 -const static uint64_t SH_FLD_23_DELAY4_LEN = 817; // 16 -const static uint64_t SH_FLD_23_DELAY5 = 818; // 16 -const static uint64_t SH_FLD_23_DELAY5_LEN = 819; // 16 -const static uint64_t SH_FLD_23_DELAY6 = 820; // 16 -const static uint64_t SH_FLD_23_DELAY6_LEN = 821; // 16 -const static uint64_t SH_FLD_23_DELAY7 = 822; // 16 -const static uint64_t SH_FLD_23_DELAY7_LEN = 823; // 16 -const static uint64_t SH_FLD_23_DELAY8 = 824; // 16 -const static uint64_t SH_FLD_23_DELAY8_LEN = 825; // 16 -const static uint64_t SH_FLD_23_DELAY9 = 826; // 16 -const static uint64_t SH_FLD_23_DELAY9_LEN = 827; // 16 -const static uint64_t SH_FLD_23_DELAYG = 828; // 1280 -const static uint64_t SH_FLD_23_DELAYG_LEN = 829; // 1280 -const static uint64_t SH_FLD_23_DELAY_PING_PONG_HALF = 830; // 16 -const static uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH = 831; // 16 -const static uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 832; // 16 -const static uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW = 833; // 16 -const static uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 834; // 16 -const static uint64_t SH_FLD_23_DFT_FORCE_OUTPUTS = 835; // 16 -const static uint64_t SH_FLD_23_DFT_PRBS7_GEN_EN = 836; // 16 -const static uint64_t SH_FLD_23_DIGITAL_EN = 837; // 16 -const static uint64_t SH_FLD_23_DIR_0_15 = 838; // 16 -const static uint64_t SH_FLD_23_DIR_0_15_LEN = 839; // 16 -const static uint64_t SH_FLD_23_DISABLE_0_15 = 840; // 64 -const static uint64_t SH_FLD_23_DISABLE_0_15_LEN = 841; // 64 -const static uint64_t SH_FLD_23_DISABLE_16_23 = 842; // 64 -const static uint64_t SH_FLD_23_DISABLE_16_23_LEN = 843; // 64 -const static uint64_t SH_FLD_23_DISABLE_PING_PONG = 844; // 16 -const static uint64_t SH_FLD_23_DISABLE_TERMINATION = 845; // 16 -const static uint64_t SH_FLD_23_DIS_CLK_GATE = 846; // 16 -const static uint64_t SH_FLD_23_DI_ADR0_ADR1 = 847; // 16 -const static uint64_t SH_FLD_23_DI_ADR10_ADR11 = 848; // 16 -const static uint64_t SH_FLD_23_DI_ADR12_ADR13 = 849; // 16 -const static uint64_t SH_FLD_23_DI_ADR14_ADR15 = 850; // 16 -const static uint64_t SH_FLD_23_DI_ADR2 = 851; // 8 -const static uint64_t SH_FLD_23_DI_ADR3 = 852; // 8 -const static uint64_t SH_FLD_23_DI_ADR4_ADR5 = 853; // 16 -const static uint64_t SH_FLD_23_DI_ADR6_ADR7 = 854; // 16 -const static uint64_t SH_FLD_23_DI_ADR8_ADR9 = 855; // 16 -const static uint64_t SH_FLD_23_DL_FORCE_ON = 856; // 16 -const static uint64_t SH_FLD_23_DONE = 857; // 32 -const static uint64_t SH_FLD_23_DQS = 858; // 16 -const static uint64_t SH_FLD_23_DQSCLK_SELECT0 = 859; // 64 -const static uint64_t SH_FLD_23_DQSCLK_SELECT0_LEN = 860; // 64 -const static uint64_t SH_FLD_23_DQSCLK_SELECT1 = 861; // 64 -const static uint64_t SH_FLD_23_DQSCLK_SELECT1_LEN = 862; // 64 -const static uint64_t SH_FLD_23_DQSCLK_SELECT2 = 863; // 64 -const static uint64_t SH_FLD_23_DQSCLK_SELECT2_LEN = 864; // 64 -const static uint64_t SH_FLD_23_DQSCLK_SELECT3 = 865; // 64 -const static uint64_t SH_FLD_23_DQSCLK_SELECT3_LEN = 866; // 64 -const static uint64_t SH_FLD_23_DQS_ALIGN_CNTR = 867; // 16 -const static uint64_t SH_FLD_23_DQS_ALIGN_CNTR_LEN = 868; // 16 -const static uint64_t SH_FLD_23_DQS_ALIGN_FIX_DIS = 869; // 16 -const static uint64_t SH_FLD_23_DQS_ALIGN_ITR_CNTR = 870; // 16 -const static uint64_t SH_FLD_23_DQS_ALIGN_ITR_CNTR_LEN = 871; // 16 -const static uint64_t SH_FLD_23_DQS_ALIGN_JITTER = 872; // 16 -const static uint64_t SH_FLD_23_DQS_ALIGN_QUAD = 873; // 16 -const static uint64_t SH_FLD_23_DQS_ALIGN_QUAD_LEN = 874; // 16 -const static uint64_t SH_FLD_23_DQS_ALIGN_SM = 875; // 16 -const static uint64_t SH_FLD_23_DQS_ALIGN_SM_LEN = 876; // 16 -const static uint64_t SH_FLD_23_DQS_LEN = 877; // 16 -const static uint64_t SH_FLD_23_DQS_PIPE_FIX_DIS = 878; // 16 -const static uint64_t SH_FLD_23_DQS_PIPE_FIX_DIS_LEN = 879; // 16 -const static uint64_t SH_FLD_23_DRIFT_ERROR = 880; // 16 -const static uint64_t SH_FLD_23_DRIFT_MASK = 881; // 16 -const static uint64_t SH_FLD_23_DRVREN_MODE = 882; // 16 -const static uint64_t SH_FLD_23_DYN_MCTERM_CNTL_EN = 883; // 16 -const static uint64_t SH_FLD_23_DYN_POWER_CNTL_EN = 884; // 16 -const static uint64_t SH_FLD_23_DYN_RX_GATE_CNTL_EN = 885; // 16 -const static uint64_t SH_FLD_23_ENABLE = 886; // 32 -const static uint64_t SH_FLD_23_ENABLE_0_15 = 887; // 16 -const static uint64_t SH_FLD_23_ENABLE_0_15_LEN = 888; // 16 -const static uint64_t SH_FLD_23_ENABLE_16_23 = 889; // 16 -const static uint64_t SH_FLD_23_ENABLE_16_23_LEN = 890; // 16 -const static uint64_t SH_FLD_23_EN_DQS_OFFSET = 891; // 16 -const static uint64_t SH_FLD_23_EN_DRIVER_INVFB_DC = 892; // 32 -const static uint64_t SH_FLD_23_EN_N_WR = 893; // 16 -const static uint64_t SH_FLD_23_EN_N_WR_LEN = 894; // 16 -const static uint64_t SH_FLD_23_EN_P_WR = 895; // 32 -const static uint64_t SH_FLD_23_EN_P_WR_LEN = 896; // 32 -const static uint64_t SH_FLD_23_ERROR = 897; // 16 -const static uint64_t SH_FLD_23_ERROR_LEN = 898; // 16 -const static uint64_t SH_FLD_23_ERR_CLK22_MASK = 899; // 16 -const static uint64_t SH_FLD_23_EYE_CLIPPING = 900; // 16 -const static uint64_t SH_FLD_23_EYE_CLIPPING_MASK = 901; // 16 -const static uint64_t SH_FLD_23_FINE_STEPPING = 902; // 16 -const static uint64_t SH_FLD_23_FLUSH = 903; // 16 -const static uint64_t SH_FLD_23_FORCE_DQS_LANES_ON = 904; // 16 -const static uint64_t SH_FLD_23_FORCE_FIFO_CAPTURE = 905; // 16 -const static uint64_t SH_FLD_23_FREE_USAGE = 906; // 1 -const static uint64_t SH_FLD_23_FRZSULV = 907; // 32 -const static uint64_t SH_FLD_23_FW_LEFT_SIDE = 908; // 16 -const static uint64_t SH_FLD_23_FW_LEFT_SIDE_LEN = 909; // 16 -const static uint64_t SH_FLD_23_FW_RIGHT_SIDE = 910; // 16 -const static uint64_t SH_FLD_23_FW_RIGHT_SIDE_LEN = 911; // 16 -const static uint64_t SH_FLD_23_HS_DLLMUX_SEL0_0 = 912; // 8 -const static uint64_t SH_FLD_23_HS_DLLMUX_SEL0_0_3 = 913; // 8 -const static uint64_t SH_FLD_23_HS_DLLMUX_SEL0_0_3_LEN = 914; // 8 -const static uint64_t SH_FLD_23_HS_DLLMUX_SEL0_0_LEN = 915; // 8 -const static uint64_t SH_FLD_23_HS_DLLMUX_SEL1_0 = 916; // 8 -const static uint64_t SH_FLD_23_HS_DLLMUX_SEL1_0_3 = 917; // 8 -const static uint64_t SH_FLD_23_HS_DLLMUX_SEL1_0_3_LEN = 918; // 8 -const static uint64_t SH_FLD_23_HS_DLLMUX_SEL1_0_LEN = 919; // 8 -const static uint64_t SH_FLD_23_HS_PROBE_A = 920; // 16 -const static uint64_t SH_FLD_23_HS_PROBE_A_LEN = 921; // 16 -const static uint64_t SH_FLD_23_HS_PROBE_B = 922; // 16 -const static uint64_t SH_FLD_23_HS_PROBE_B_LEN = 923; // 16 -const static uint64_t SH_FLD_23_HW_VALUE = 924; // 16 -const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N0 = 925; // 16 -const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N0_MASK = 926; // 16 -const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N1 = 927; // 16 -const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N1_MASK = 928; // 16 -const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N2 = 929; // 16 -const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N2_MASK = 930; // 16 -const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N3 = 931; // 16 -const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N3_MASK = 932; // 16 -const static uint64_t SH_FLD_23_INIT_IO = 933; // 16 -const static uint64_t SH_FLD_23_INIT_RXDLL_CAL_RESET = 934; // 32 -const static uint64_t SH_FLD_23_INIT_RXDLL_CAL_UPDATE = 935; // 32 -const static uint64_t SH_FLD_23_INTERP_SIG_SLEW = 936; // 16 -const static uint64_t SH_FLD_23_INTERP_SIG_SLEW_LEN = 937; // 16 -const static uint64_t SH_FLD_23_INVALID_NS_BIG_R = 938; // 16 -const static uint64_t SH_FLD_23_INVALID_NS_BIG_R_MASK = 939; // 16 -const static uint64_t SH_FLD_23_INVALID_NS_SMALL_L = 940; // 16 -const static uint64_t SH_FLD_23_INVALID_NS_SMALL_L_MASK = 941; // 16 -const static uint64_t SH_FLD_23_INVALID_NS_SMALL_R = 942; // 16 -const static uint64_t SH_FLD_23_INVALID_NS_SMALL_R_MASK = 943; // 16 -const static uint64_t SH_FLD_23_JUMP_BACK_RIGHT = 944; // 16 -const static uint64_t SH_FLD_23_LANE__0_11_PD = 945; // 16 -const static uint64_t SH_FLD_23_LANE__0_11_PD_LEN = 946; // 16 -const static uint64_t SH_FLD_23_LANE__12_15_PD = 947; // 16 -const static uint64_t SH_FLD_23_LANE__12_15_PD_LEN = 948; // 16 -const static uint64_t SH_FLD_23_LEADING_EDGE_FOUND_MASK = 949; // 16 -const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND = 950; // 16 -const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15 = 951; // 16 -const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15_LEN = 952; // 16 -const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23 = 953; // 16 -const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23_LEN = 954; // 16 -const static uint64_t SH_FLD_23_LEN = 955; // 96 -const static uint64_t SH_FLD_23_LOOPBACK_DLY12 = 956; // 16 -const static uint64_t SH_FLD_23_LOOPBACK_FIX_EN = 957; // 16 -const static uint64_t SH_FLD_23_MATCH_STEP_RIGHT = 958; // 16 -const static uint64_t SH_FLD_23_MAX_DQS = 959; // 16 -const static uint64_t SH_FLD_23_MAX_DQS_ITER = 960; // 16 -const static uint64_t SH_FLD_23_MAX_DQS_LEN = 961; // 16 -const static uint64_t SH_FLD_23_MEMINTD00 = 962; // 16 -const static uint64_t SH_FLD_23_MEMINTD00_LEN = 963; // 16 -const static uint64_t SH_FLD_23_MEMINTD01 = 964; // 16 -const static uint64_t SH_FLD_23_MEMINTD01_LEN = 965; // 16 -const static uint64_t SH_FLD_23_MEMINTD02 = 966; // 16 -const static uint64_t SH_FLD_23_MEMINTD02_LEN = 967; // 16 -const static uint64_t SH_FLD_23_MEMINTD03 = 968; // 16 -const static uint64_t SH_FLD_23_MEMINTD03_LEN = 969; // 16 -const static uint64_t SH_FLD_23_MEMINTD04 = 970; // 16 -const static uint64_t SH_FLD_23_MEMINTD04_LEN = 971; // 16 -const static uint64_t SH_FLD_23_MEMINTD05 = 972; // 16 -const static uint64_t SH_FLD_23_MEMINTD05_LEN = 973; // 16 -const static uint64_t SH_FLD_23_MEMINTD06 = 974; // 16 -const static uint64_t SH_FLD_23_MEMINTD06_LEN = 975; // 16 -const static uint64_t SH_FLD_23_MEMINTD07 = 976; // 16 -const static uint64_t SH_FLD_23_MEMINTD07_LEN = 977; // 16 -const static uint64_t SH_FLD_23_MEMINTD08 = 978; // 16 -const static uint64_t SH_FLD_23_MEMINTD08_LEN = 979; // 16 -const static uint64_t SH_FLD_23_MEMINTD09 = 980; // 16 -const static uint64_t SH_FLD_23_MEMINTD09_LEN = 981; // 16 -const static uint64_t SH_FLD_23_MEMINTD10 = 982; // 16 -const static uint64_t SH_FLD_23_MEMINTD10_LEN = 983; // 16 -const static uint64_t SH_FLD_23_MEMINTD11 = 984; // 16 -const static uint64_t SH_FLD_23_MEMINTD11_LEN = 985; // 16 -const static uint64_t SH_FLD_23_MEMINTD12 = 986; // 16 -const static uint64_t SH_FLD_23_MEMINTD12_LEN = 987; // 16 -const static uint64_t SH_FLD_23_MEMINTD13 = 988; // 16 -const static uint64_t SH_FLD_23_MEMINTD13_LEN = 989; // 16 -const static uint64_t SH_FLD_23_MEMINTD14 = 990; // 16 -const static uint64_t SH_FLD_23_MEMINTD14_LEN = 991; // 16 -const static uint64_t SH_FLD_23_MEMINTD15 = 992; // 16 -const static uint64_t SH_FLD_23_MEMINTD15_LEN = 993; // 16 -const static uint64_t SH_FLD_23_MEMINTD16 = 994; // 16 -const static uint64_t SH_FLD_23_MEMINTD16_LEN = 995; // 16 -const static uint64_t SH_FLD_23_MEMINTD17 = 996; // 16 -const static uint64_t SH_FLD_23_MEMINTD17_LEN = 997; // 16 -const static uint64_t SH_FLD_23_MEMINTD18 = 998; // 16 -const static uint64_t SH_FLD_23_MEMINTD18_LEN = 999; // 16 -const static uint64_t SH_FLD_23_MEMINTD19 = 1000; // 16 -const static uint64_t SH_FLD_23_MEMINTD19_LEN = 1001; // 16 -const static uint64_t SH_FLD_23_MEMINTD20 = 1002; // 16 -const static uint64_t SH_FLD_23_MEMINTD20_LEN = 1003; // 16 -const static uint64_t SH_FLD_23_MEMINTD21 = 1004; // 16 -const static uint64_t SH_FLD_23_MEMINTD21_LEN = 1005; // 16 -const static uint64_t SH_FLD_23_MEMINTD22 = 1006; // 16 -const static uint64_t SH_FLD_23_MEMINTD22_LEN = 1007; // 16 -const static uint64_t SH_FLD_23_MEMINTD23 = 1008; // 16 -const static uint64_t SH_FLD_23_MEMINTD23_LEN = 1009; // 16 -const static uint64_t SH_FLD_23_MIN_EYE = 1010; // 16 -const static uint64_t SH_FLD_23_MIN_EYE_MASK = 1011; // 16 -const static uint64_t SH_FLD_23_MIN_RD_EYE_SIZE = 1012; // 16 -const static uint64_t SH_FLD_23_MIN_RD_EYE_SIZE_LEN = 1013; // 16 -const static uint64_t SH_FLD_23_MRS_CMD_N0 = 1014; // 16 -const static uint64_t SH_FLD_23_MRS_CMD_N1 = 1015; // 16 -const static uint64_t SH_FLD_23_MRS_CMD_N2 = 1016; // 16 -const static uint64_t SH_FLD_23_MRS_CMD_N3 = 1017; // 16 -const static uint64_t SH_FLD_23_N0 = 1018; // 128 -const static uint64_t SH_FLD_23_N0_LEN = 1019; // 128 -const static uint64_t SH_FLD_23_N1 = 1020; // 128 -const static uint64_t SH_FLD_23_N1_LEN = 1021; // 128 -const static uint64_t SH_FLD_23_N2 = 1022; // 128 -const static uint64_t SH_FLD_23_N2_LEN = 1023; // 128 -const static uint64_t SH_FLD_23_N3 = 1024; // 128 -const static uint64_t SH_FLD_23_N3_LEN = 1025; // 128 -const static uint64_t SH_FLD_23_NIB0 = 1026; // 16 -const static uint64_t SH_FLD_23_NIB0TCFLIP_DC = 1027; // 16 -const static uint64_t SH_FLD_23_NIB0_LEN = 1028; // 16 -const static uint64_t SH_FLD_23_NIB1 = 1029; // 16 -const static uint64_t SH_FLD_23_NIB1TCFLIP_DC = 1030; // 16 -const static uint64_t SH_FLD_23_NIB1_LEN = 1031; // 16 -const static uint64_t SH_FLD_23_NIB2 = 1032; // 16 -const static uint64_t SH_FLD_23_NIB2TCFLIP_DC = 1033; // 16 -const static uint64_t SH_FLD_23_NIB2_LEN = 1034; // 16 -const static uint64_t SH_FLD_23_NIB3 = 1035; // 16 -const static uint64_t SH_FLD_23_NIB3TCFLIP_DC = 1036; // 16 -const static uint64_t SH_FLD_23_NIB3_LEN = 1037; // 16 -const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_CAP = 1038; // 16 -const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_CAP_LEN = 1039; // 16 -const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_IND = 1040; // 16 -const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_IND_LEN = 1041; // 16 -const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_RES = 1042; // 16 -const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_RES_LEN = 1043; // 16 -const static uint64_t SH_FLD_23_NIB_0_DQSEL_CAP = 1044; // 16 -const static uint64_t SH_FLD_23_NIB_0_DQSEL_CAP_LEN = 1045; // 16 -const static uint64_t SH_FLD_23_NIB_0_DQSEL_IND = 1046; // 16 -const static uint64_t SH_FLD_23_NIB_0_DQSEL_IND_LEN = 1047; // 16 -const static uint64_t SH_FLD_23_NIB_0_DQSEL_RES = 1048; // 16 -const static uint64_t SH_FLD_23_NIB_0_DQSEL_RES_LEN = 1049; // 16 -const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_CAP = 1050; // 16 -const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_CAP_LEN = 1051; // 16 -const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_IND = 1052; // 16 -const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_IND_LEN = 1053; // 16 -const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_RES = 1054; // 16 -const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_RES_LEN = 1055; // 16 -const static uint64_t SH_FLD_23_NIB_1_DQSEL_CAP = 1056; // 16 -const static uint64_t SH_FLD_23_NIB_1_DQSEL_CAP_LEN = 1057; // 16 -const static uint64_t SH_FLD_23_NIB_1_DQSEL_IND = 1058; // 16 -const static uint64_t SH_FLD_23_NIB_1_DQSEL_IND_LEN = 1059; // 16 -const static uint64_t SH_FLD_23_NIB_1_DQSEL_RES = 1060; // 16 -const static uint64_t SH_FLD_23_NIB_1_DQSEL_RES_LEN = 1061; // 16 -const static uint64_t SH_FLD_23_NO_DQS = 1062; // 16 -const static uint64_t SH_FLD_23_NO_DQS_MASK = 1063; // 16 -const static uint64_t SH_FLD_23_NO_EYE_DETECTED = 1064; // 16 -const static uint64_t SH_FLD_23_NO_EYE_DETECTED_MASK = 1065; // 16 -const static uint64_t SH_FLD_23_NO_LOCK = 1066; // 16 -const static uint64_t SH_FLD_23_NO_LOCK_MASK = 1067; // 16 -const static uint64_t SH_FLD_23_OFFSET0 = 1068; // 16 -const static uint64_t SH_FLD_23_OFFSET0_LEN = 1069; // 16 -const static uint64_t SH_FLD_23_OFFSET1 = 1070; // 16 -const static uint64_t SH_FLD_23_OFFSET1_LEN = 1071; // 16 -const static uint64_t SH_FLD_23_OFFSET2 = 1072; // 32 -const static uint64_t SH_FLD_23_OFFSET2_LEN = 1073; // 32 -const static uint64_t SH_FLD_23_OFFSET3 = 1074; // 32 -const static uint64_t SH_FLD_23_OFFSET3_LEN = 1075; // 32 -const static uint64_t SH_FLD_23_OFFSET4 = 1076; // 32 -const static uint64_t SH_FLD_23_OFFSET4_LEN = 1077; // 32 -const static uint64_t SH_FLD_23_OFFSET5 = 1078; // 32 -const static uint64_t SH_FLD_23_OFFSET5_LEN = 1079; // 32 -const static uint64_t SH_FLD_23_OFFSET6 = 1080; // 32 -const static uint64_t SH_FLD_23_OFFSET6_LEN = 1081; // 32 -const static uint64_t SH_FLD_23_OFFSET7 = 1082; // 32 -const static uint64_t SH_FLD_23_OFFSET7_LEN = 1083; // 32 -const static uint64_t SH_FLD_23_OFFSET_ERR = 1084; // 16 -const static uint64_t SH_FLD_23_OFFSET_ERR_MASK = 1085; // 16 -const static uint64_t SH_FLD_23_OPERATE_MODE = 1086; // 16 -const static uint64_t SH_FLD_23_OPERATE_MODE_LEN = 1087; // 16 -const static uint64_t SH_FLD_23_PERCAL_PWR_DIS = 1088; // 16 -const static uint64_t SH_FLD_23_PER_CAL_UPDATE_DISABLE = 1089; // 16 -const static uint64_t SH_FLD_23_PHASE_ALIGN_RESET = 1090; // 32 -const static uint64_t SH_FLD_23_PHASE_CNTL_EN = 1091; // 32 -const static uint64_t SH_FLD_23_PHASE_DEFAULT_EN = 1092; // 32 -const static uint64_t SH_FLD_23_POS_EDGE_ALIGN = 1093; // 32 -const static uint64_t SH_FLD_23_QUAD0 = 1094; // 16 -const static uint64_t SH_FLD_23_QUAD0_CLK16 = 1095; // 128 -const static uint64_t SH_FLD_23_QUAD0_CLK18 = 1096; // 128 -const static uint64_t SH_FLD_23_QUAD0_LEN = 1097; // 16 -const static uint64_t SH_FLD_23_QUAD1 = 1098; // 16 -const static uint64_t SH_FLD_23_QUAD1_CLK16 = 1099; // 128 -const static uint64_t SH_FLD_23_QUAD1_CLK18 = 1100; // 128 -const static uint64_t SH_FLD_23_QUAD1_LEN = 1101; // 16 -const static uint64_t SH_FLD_23_QUAD2 = 1102; // 16 -const static uint64_t SH_FLD_23_QUAD2_CLK16 = 1103; // 128 -const static uint64_t SH_FLD_23_QUAD2_CLK18 = 1104; // 64 -const static uint64_t SH_FLD_23_QUAD2_CLK20 = 1105; // 128 -const static uint64_t SH_FLD_23_QUAD2_CLK22 = 1106; // 128 -const static uint64_t SH_FLD_23_QUAD2_LEN = 1107; // 16 -const static uint64_t SH_FLD_23_QUAD3 = 1108; // 16 -const static uint64_t SH_FLD_23_QUAD3_CLK16 = 1109; // 128 -const static uint64_t SH_FLD_23_QUAD3_CLK18 = 1110; // 64 -const static uint64_t SH_FLD_23_QUAD3_CLK20 = 1111; // 128 -const static uint64_t SH_FLD_23_QUAD3_CLK22 = 1112; // 128 -const static uint64_t SH_FLD_23_QUAD3_LEN = 1113; // 16 -const static uint64_t SH_FLD_23_RD = 1114; // 272 -const static uint64_t SH_FLD_23_RDCLK_SELECT0 = 1115; // 64 -const static uint64_t SH_FLD_23_RDCLK_SELECT0_LEN = 1116; // 64 -const static uint64_t SH_FLD_23_RDCLK_SELECT1 = 1117; // 64 -const static uint64_t SH_FLD_23_RDCLK_SELECT1_LEN = 1118; // 64 -const static uint64_t SH_FLD_23_RDCLK_SELECT2 = 1119; // 64 -const static uint64_t SH_FLD_23_RDCLK_SELECT2_LEN = 1120; // 64 -const static uint64_t SH_FLD_23_RDCLK_SELECT3 = 1121; // 64 -const static uint64_t SH_FLD_23_RDCLK_SELECT3_LEN = 1122; // 64 -const static uint64_t SH_FLD_23_RD_DELAY0 = 1123; // 112 -const static uint64_t SH_FLD_23_RD_DELAY0_LEN = 1124; // 112 -const static uint64_t SH_FLD_23_RD_DELAY1 = 1125; // 112 -const static uint64_t SH_FLD_23_RD_DELAY1_LEN = 1126; // 112 -const static uint64_t SH_FLD_23_RD_DELAY2 = 1127; // 112 -const static uint64_t SH_FLD_23_RD_DELAY2_LEN = 1128; // 112 -const static uint64_t SH_FLD_23_RD_DELAY3 = 1129; // 112 -const static uint64_t SH_FLD_23_RD_DELAY3_LEN = 1130; // 112 -const static uint64_t SH_FLD_23_RD_DELAY4 = 1131; // 112 -const static uint64_t SH_FLD_23_RD_DELAY4_LEN = 1132; // 112 -const static uint64_t SH_FLD_23_RD_DELAY5 = 1133; // 112 -const static uint64_t SH_FLD_23_RD_DELAY5_LEN = 1134; // 112 -const static uint64_t SH_FLD_23_RD_DELAY6 = 1135; // 112 -const static uint64_t SH_FLD_23_RD_DELAY6_LEN = 1136; // 112 -const static uint64_t SH_FLD_23_RD_DELAY7 = 1137; // 112 -const static uint64_t SH_FLD_23_RD_DELAY7_LEN = 1138; // 112 -const static uint64_t SH_FLD_23_RD_LEN = 1139; // 272 -const static uint64_t SH_FLD_23_RD_SIZE0 = 1140; // 176 -const static uint64_t SH_FLD_23_RD_SIZE0_LEN = 1141; // 176 -const static uint64_t SH_FLD_23_RD_SIZE1 = 1142; // 176 -const static uint64_t SH_FLD_23_RD_SIZE1_LEN = 1143; // 176 -const static uint64_t SH_FLD_23_RD_SIZE2 = 1144; // 176 -const static uint64_t SH_FLD_23_RD_SIZE2_LEN = 1145; // 176 -const static uint64_t SH_FLD_23_RD_SIZE3 = 1146; // 176 -const static uint64_t SH_FLD_23_RD_SIZE3_LEN = 1147; // 176 -const static uint64_t SH_FLD_23_RD_SIZE4 = 1148; // 176 -const static uint64_t SH_FLD_23_RD_SIZE4_LEN = 1149; // 176 -const static uint64_t SH_FLD_23_RD_SIZE5 = 1150; // 176 -const static uint64_t SH_FLD_23_RD_SIZE5_LEN = 1151; // 176 -const static uint64_t SH_FLD_23_RD_SIZE6 = 1152; // 176 -const static uint64_t SH_FLD_23_RD_SIZE6_LEN = 1153; // 176 -const static uint64_t SH_FLD_23_RD_SIZE7 = 1154; // 176 -const static uint64_t SH_FLD_23_RD_SIZE7_LEN = 1155; // 176 -const static uint64_t SH_FLD_23_READ_CENTERING_MODE = 1156; // 16 -const static uint64_t SH_FLD_23_READ_CENTERING_MODE_LEN = 1157; // 16 -const static uint64_t SH_FLD_23_REFERENCE1 = 1158; // 16 -const static uint64_t SH_FLD_23_REFERENCE1_LEN = 1159; // 16 -const static uint64_t SH_FLD_23_REFERENCE2 = 1160; // 16 -const static uint64_t SH_FLD_23_REFERENCE2_LEN = 1161; // 16 -const static uint64_t SH_FLD_23_REFERENCE3 = 1162; // 16 -const static uint64_t SH_FLD_23_REFERENCE3_LEN = 1163; // 16 -const static uint64_t SH_FLD_23_REGS_RXDLL_CAL_SKIP = 1164; // 32 -const static uint64_t SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN = 1165; // 32 -const static uint64_t SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 = 1166; // 32 -const static uint64_t SH_FLD_23_REGS_RXDLL_COARSE_EN = 1167; // 32 -const static uint64_t SH_FLD_23_REGS_RXDLL_COARSE_EN_LEN = 1168; // 32 -const static uint64_t SH_FLD_23_REGS_RXDLL_DAC_COARSE = 1169; // 32 -const static uint64_t SH_FLD_23_REGS_RXDLL_DAC_COARSE_LEN = 1170; // 32 -const static uint64_t SH_FLD_23_REGS_RXDLL_VREG_LOWER = 1171; // 32 -const static uint64_t SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN = 1172; // 32 -const static uint64_t SH_FLD_23_REGS_RXDLL_VREG_UPPER = 1173; // 32 -const static uint64_t SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN = 1174; // 32 -const static uint64_t SH_FLD_23_RESERVED = 1175; // 2 -const static uint64_t SH_FLD_23_RESERVED_56_63 = 1176; // 16 -const static uint64_t SH_FLD_23_RESERVED_56_63_LEN = 1177; // 16 -const static uint64_t SH_FLD_23_ROT0 = 1178; // 16 -const static uint64_t SH_FLD_23_ROT0_LEN = 1179; // 16 -const static uint64_t SH_FLD_23_ROT1 = 1180; // 16 -const static uint64_t SH_FLD_23_ROT1_LEN = 1181; // 16 -const static uint64_t SH_FLD_23_ROT_CLK_N0 = 1182; // 128 -const static uint64_t SH_FLD_23_ROT_CLK_N0_LEN = 1183; // 128 -const static uint64_t SH_FLD_23_ROT_CLK_N1 = 1184; // 128 -const static uint64_t SH_FLD_23_ROT_CLK_N1_LEN = 1185; // 128 -const static uint64_t SH_FLD_23_ROT_N0 = 1186; // 128 -const static uint64_t SH_FLD_23_ROT_N0_LEN = 1187; // 128 -const static uint64_t SH_FLD_23_ROT_N1 = 1188; // 128 -const static uint64_t SH_FLD_23_ROT_N1_LEN = 1189; // 128 -const static uint64_t SH_FLD_23_ROT_OVERRIDE = 1190; // 32 -const static uint64_t SH_FLD_23_ROT_OVERRIDE_EN = 1191; // 32 -const static uint64_t SH_FLD_23_ROT_OVERRIDE_LEN = 1192; // 32 -const static uint64_t SH_FLD_23_RXREG_COMPCON_DC = 1193; // 32 -const static uint64_t SH_FLD_23_RXREG_COMPCON_DC_LEN = 1194; // 32 -const static uint64_t SH_FLD_23_RXREG_CON_DC = 1195; // 32 -const static uint64_t SH_FLD_23_RXREG_DAC_PULLUP_DC = 1196; // 32 -const static uint64_t SH_FLD_23_RXREG_DRVCON_DC = 1197; // 32 -const static uint64_t SH_FLD_23_RXREG_DRVCON_DC_LEN = 1198; // 32 -const static uint64_t SH_FLD_23_RXREG_FILTER_LENGTH_DC = 1199; // 32 -const static uint64_t SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN = 1200; // 32 -const static uint64_t SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC = 1201; // 32 -const static uint64_t SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 1202; // 32 -const static uint64_t SH_FLD_23_RXREG_REF_SEL_DC = 1203; // 32 -const static uint64_t SH_FLD_23_RXREG_REF_SEL_DC_LEN = 1204; // 32 -const static uint64_t SH_FLD_23_S0ACENSLICENDRV_DC = 1205; // 16 -const static uint64_t SH_FLD_23_S0ACENSLICENDRV_DC_LEN = 1206; // 16 -const static uint64_t SH_FLD_23_S0ACENSLICEPDRV_DC = 1207; // 16 -const static uint64_t SH_FLD_23_S0ACENSLICEPDRV_DC_LEN = 1208; // 16 -const static uint64_t SH_FLD_23_S0ACENSLICEPTERM_DC = 1209; // 16 -const static uint64_t SH_FLD_23_S0ACENSLICEPTERM_DC_LEN = 1210; // 16 -const static uint64_t SH_FLD_23_S0INSDLYTAP = 1211; // 16 -const static uint64_t SH_FLD_23_S1ACENSLICENDRV_DC = 1212; // 16 -const static uint64_t SH_FLD_23_S1ACENSLICENDRV_DC_LEN = 1213; // 16 -const static uint64_t SH_FLD_23_S1ACENSLICEPDRV_DC = 1214; // 16 -const static uint64_t SH_FLD_23_S1ACENSLICEPDRV_DC_LEN = 1215; // 16 -const static uint64_t SH_FLD_23_S1ACENSLICEPTERM_DC = 1216; // 16 -const static uint64_t SH_FLD_23_S1ACENSLICEPTERM_DC_LEN = 1217; // 16 -const static uint64_t SH_FLD_23_S1INSDLYTAP = 1218; // 16 -const static uint64_t SH_FLD_23_SEL0 = 1219; // 32 -const static uint64_t SH_FLD_23_SEL0_LEN = 1220; // 16 -const static uint64_t SH_FLD_23_SEL1 = 1221; // 32 -const static uint64_t SH_FLD_23_SEL10 = 1222; // 32 -const static uint64_t SH_FLD_23_SEL10_LEN = 1223; // 32 -const static uint64_t SH_FLD_23_SEL11 = 1224; // 32 -const static uint64_t SH_FLD_23_SEL11_LEN = 1225; // 32 -const static uint64_t SH_FLD_23_SEL12 = 1226; // 32 -const static uint64_t SH_FLD_23_SEL12_LEN = 1227; // 32 -const static uint64_t SH_FLD_23_SEL13 = 1228; // 32 -const static uint64_t SH_FLD_23_SEL13_LEN = 1229; // 32 -const static uint64_t SH_FLD_23_SEL14 = 1230; // 32 -const static uint64_t SH_FLD_23_SEL14_LEN = 1231; // 32 -const static uint64_t SH_FLD_23_SEL15 = 1232; // 32 -const static uint64_t SH_FLD_23_SEL15_LEN = 1233; // 32 -const static uint64_t SH_FLD_23_SEL1_LEN = 1234; // 32 -const static uint64_t SH_FLD_23_SEL2 = 1235; // 32 -const static uint64_t SH_FLD_23_SEL2_LEN = 1236; // 32 -const static uint64_t SH_FLD_23_SEL3 = 1237; // 32 -const static uint64_t SH_FLD_23_SEL3_LEN = 1238; // 32 -const static uint64_t SH_FLD_23_SEL4 = 1239; // 32 -const static uint64_t SH_FLD_23_SEL4_LEN = 1240; // 32 -const static uint64_t SH_FLD_23_SEL5 = 1241; // 32 -const static uint64_t SH_FLD_23_SEL5_LEN = 1242; // 32 -const static uint64_t SH_FLD_23_SEL6 = 1243; // 32 -const static uint64_t SH_FLD_23_SEL6_LEN = 1244; // 32 -const static uint64_t SH_FLD_23_SEL7 = 1245; // 32 -const static uint64_t SH_FLD_23_SEL7_LEN = 1246; // 32 -const static uint64_t SH_FLD_23_SEL8 = 1247; // 32 -const static uint64_t SH_FLD_23_SEL8_LEN = 1248; // 16 -const static uint64_t SH_FLD_23_SEL9 = 1249; // 32 -const static uint64_t SH_FLD_23_SEL9_LEN = 1250; // 32 -const static uint64_t SH_FLD_23_SMALL_STEP_LEFT = 1251; // 16 -const static uint64_t SH_FLD_23_SMALL_STEP_RIGHT = 1252; // 16 -const static uint64_t SH_FLD_23_SPARE_OSC = 1253; // 1 -const static uint64_t SH_FLD_23_SPARE_PLL_CONTROL = 1254; // 1 -const static uint64_t SH_FLD_23_SPARE_RESONANT_CLOCKING_CONTROL = 1255; // 1 -const static uint64_t SH_FLD_23_SPARE_TEST = 1256; // 1 -const static uint64_t SH_FLD_23_SYNC = 1257; // 16 -const static uint64_t SH_FLD_23_SYNC_LEN = 1258; // 16 -const static uint64_t SH_FLD_23_SYSCLK_DQSCLK_OFFSET = 1259; // 16 -const static uint64_t SH_FLD_23_SYSCLK_DQSCLK_OFFSET_LEN = 1260; // 16 -const static uint64_t SH_FLD_23_SYSCLK_RDCLK_OFFSET = 1261; // 16 -const static uint64_t SH_FLD_23_SYSCLK_RDCLK_OFFSET_LEN = 1262; // 16 -const static uint64_t SH_FLD_23_TEST_4TO1_MODE = 1263; // 16 -const static uint64_t SH_FLD_23_TEST_CHECK_EN = 1264; // 16 -const static uint64_t SH_FLD_23_TEST_CLEAR_ERROR = 1265; // 16 -const static uint64_t SH_FLD_23_TEST_DATA_EN = 1266; // 16 -const static uint64_t SH_FLD_23_TEST_GEN_EN = 1267; // 16 -const static uint64_t SH_FLD_23_TEST_LANE_PAIR_FAIL = 1268; // 16 -const static uint64_t SH_FLD_23_TEST_LANE_PAIR_FAIL_LEN = 1269; // 16 -const static uint64_t SH_FLD_23_TEST_MODE = 1270; // 16 -const static uint64_t SH_FLD_23_TEST_MODE_LEN = 1271; // 16 -const static uint64_t SH_FLD_23_TEST_RESET = 1272; // 16 -const static uint64_t SH_FLD_23_TRAILING_EDGE_FOUND_MASK = 1273; // 16 -const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND = 1274; // 16 -const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15 = 1275; // 16 -const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 1276; // 16 -const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23 = 1277; // 16 -const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 1278; // 16 -const static uint64_t SH_FLD_23_TRIG_PERIOD = 1279; // 16 -const static uint64_t SH_FLD_23_TSYS = 1280; // 16 -const static uint64_t SH_FLD_23_TSYS_LEN = 1281; // 16 -const static uint64_t SH_FLD_23_TUNEATST_0 = 1282; // 16 -const static uint64_t SH_FLD_23_TUNEATST_1 = 1283; // 16 -const static uint64_t SH_FLD_23_VALID_NS_BIG_L = 1284; // 16 -const static uint64_t SH_FLD_23_VALID_NS_BIG_L_MASK = 1285; // 16 -const static uint64_t SH_FLD_23_VALID_NS_BIG_R = 1286; // 16 -const static uint64_t SH_FLD_23_VALID_NS_BIG_R_MASK = 1287; // 16 -const static uint64_t SH_FLD_23_VALID_NS_JUMP_BACK = 1288; // 16 -const static uint64_t SH_FLD_23_VALID_NS_JUMP_BACK_MASK = 1289; // 16 -const static uint64_t SH_FLD_23_WL_ADVANCE_DISABLE = 1290; // 16 -const static uint64_t SH_FLD_23_WL_ERR_CLK16 = 1291; // 32 -const static uint64_t SH_FLD_23_WL_ERR_CLK16_MASK = 1292; // 16 -const static uint64_t SH_FLD_23_WL_ERR_CLK18 = 1293; // 32 -const static uint64_t SH_FLD_23_WL_ERR_CLK18_MASK = 1294; // 16 -const static uint64_t SH_FLD_23_WL_ERR_CLK20 = 1295; // 32 -const static uint64_t SH_FLD_23_WL_ERR_CLK20_MASK = 1296; // 16 -const static uint64_t SH_FLD_23_WL_ERR_CLK22 = 1297; // 32 -const static uint64_t SH_FLD_23_WRAPSEL = 1298; // 16 -const static uint64_t SH_FLD_23_WTRFL_AVE_DIS = 1299; // 16 -const static uint64_t SH_FLD_23_ZERO_DETECTED = 1300; // 16 -const static uint64_t SH_FLD_24 = 1301; // 6 -const static uint64_t SH_FLD_24CORE_EN = 1302; // 1 -const static uint64_t SH_FLD_24_FREE_USAGE = 1303; // 1 -const static uint64_t SH_FLD_24_RESERVED = 1304; // 2 -const static uint64_t SH_FLD_24_SPARE_CBS_CONTROL = 1305; // 1 -const static uint64_t SH_FLD_24_SPARE_OSC = 1306; // 1 -const static uint64_t SH_FLD_24_SPARE_RESONANT_CLOCKING_CONTROL = 1307; // 1 -const static uint64_t SH_FLD_25 = 1308; // 6 -const static uint64_t SH_FLD_25_FREE_USAGE = 1309; // 1 -const static uint64_t SH_FLD_25_SPARE_CBS_CONTROL = 1310; // 1 -const static uint64_t SH_FLD_25_SPARE_CLKIN_CONTROL = 1311; // 1 -const static uint64_t SH_FLD_25_SPARE_OSC = 1312; // 1 -const static uint64_t SH_FLD_25_SPARE_REFCLOCK_CONTROL = 1313; // 1 -const static uint64_t SH_FLD_25_SPARE_RESONANT_CLOCKING_CONTROL = 1314; // 1 -const static uint64_t SH_FLD_26 = 1315; // 6 -const static uint64_t SH_FLD_26_FREE_USAGE = 1316; // 1 -const static uint64_t SH_FLD_26_SPARE_CBS_CONTROL = 1317; // 1 -const static uint64_t SH_FLD_26_SPARE_CLKIN_CONTROL = 1318; // 1 -const static uint64_t SH_FLD_26_SPARE_OSC = 1319; // 1 -const static uint64_t SH_FLD_26_SPARE_REFCLOCK_CONTROL = 1320; // 1 -const static uint64_t SH_FLD_26_SPARE_RESONANT_CLOCKING_CONTROL = 1321; // 1 -const static uint64_t SH_FLD_27 = 1322; // 6 -const static uint64_t SH_FLD_27_FREE_USAGE = 1323; // 1 -const static uint64_t SH_FLD_27_SPARE_CBS_CONTROL = 1324; // 1 -const static uint64_t SH_FLD_27_SPARE_CLKIN_CONTROL = 1325; // 1 -const static uint64_t SH_FLD_27_SPARE_OSC = 1326; // 1 -const static uint64_t SH_FLD_27_SPARE_RESONANT_CLOCKING_CONTROL = 1327; // 1 -const static uint64_t SH_FLD_28 = 1328; // 6 -const static uint64_t SH_FLD_28_FREE_USAGE = 1329; // 1 -const static uint64_t SH_FLD_28_RESERVED_FOR_HTB = 1330; // 1 -const static uint64_t SH_FLD_28_SPARE_OSC = 1331; // 1 -const static uint64_t SH_FLD_28_SPARE_RESET = 1332; // 1 -const static uint64_t SH_FLD_28_SPARE_RESONANT_CLOCKING_CONTROL = 1333; // 1 -const static uint64_t SH_FLD_28_SPARE_TEST_CONTROL = 1334; // 1 -const static uint64_t SH_FLD_29 = 1335; // 6 -const static uint64_t SH_FLD_29_FREE_USAGE = 1336; // 1 -const static uint64_t SH_FLD_29_RESERVED_FOR_HTB = 1337; // 1 -const static uint64_t SH_FLD_29_SPARE_OSC = 1338; // 1 -const static uint64_t SH_FLD_29_SPARE_REFCLOCK_CONTROL = 1339; // 1 -const static uint64_t SH_FLD_29_SPARE_RESET = 1340; // 1 -const static uint64_t SH_FLD_29_SPARE_RESONANT_CLOCKING_CONTROL = 1341; // 1 -const static uint64_t SH_FLD_29_SPARE_TEST_CONTROL = 1342; // 1 -const static uint64_t SH_FLD_2_CANNED_0 = 1343; // 2 -const static uint64_t SH_FLD_2_CANNED_0_LEN = 1344; // 2 -const static uint64_t SH_FLD_2_CANNED_1 = 1345; // 2 -const static uint64_t SH_FLD_2_CANNED_1_LEN = 1346; // 2 -const static uint64_t SH_FLD_2_DATA = 1347; // 1 -const static uint64_t SH_FLD_2_DATA_LEN = 1348; // 1 -const static uint64_t SH_FLD_2_LEN = 1349; // 46 -const static uint64_t SH_FLD_2_RESERVED = 1350; // 1 -const static uint64_t SH_FLD_2_SPARE_SECTOR_BUFFER_CONTROL = 1351; // 1 -const static uint64_t SH_FLD_2_SPARE_SS_PLL_CONTROL = 1352; // 1 -const static uint64_t SH_FLD_3 = 1353; // 464 -const static uint64_t SH_FLD_30 = 1354; // 6 -const static uint64_t SH_FLD_30_FREE_USAGE = 1355; // 1 -const static uint64_t SH_FLD_30_RESERVED = 1356; // 1 -const static uint64_t SH_FLD_30_RESERVED_FOR_HTB = 1357; // 1 -const static uint64_t SH_FLD_30_SPARE_OSC = 1358; // 1 -const static uint64_t SH_FLD_30_SPARE_REFCLOCK_CONTROL = 1359; // 1 -const static uint64_t SH_FLD_30_SPARE_RESONANT_CLOCKING_CONTROL = 1360; // 1 -const static uint64_t SH_FLD_30_SPARE_TEST_CONTROL = 1361; // 1 -const static uint64_t SH_FLD_31 = 1362; // 6 -const static uint64_t SH_FLD_31_FREE_USAGE = 1363; // 1 -const static uint64_t SH_FLD_31_RESERVED_FOR_HTB = 1364; // 1 -const static uint64_t SH_FLD_31_SPARE_OSC = 1365; // 1 -const static uint64_t SH_FLD_31_SPARE_REFCLOCK_CONTROL = 1366; // 1 -const static uint64_t SH_FLD_31_SPARE_RESONANT_CLOCKING_CONTROL = 1367; // 1 -const static uint64_t SH_FLD_31_SPARE_TEST_CONTROL = 1368; // 1 -const static uint64_t SH_FLD_3_DATA = 1369; // 1 -const static uint64_t SH_FLD_3_DATA_LEN = 1370; // 1 -const static uint64_t SH_FLD_3_LEN = 1371; // 46 -const static uint64_t SH_FLD_3_RESERVED = 1372; // 1 -const static uint64_t SH_FLD_3_SPARE_SECTOR_BUFFER_CONTROL = 1373; // 1 -const static uint64_t SH_FLD_3_SPARE_SS_PLL_CONTROL = 1374; // 1 -const static uint64_t SH_FLD_4 = 1375; // 502 -const static uint64_t SH_FLD_4X4_MODE = 1376; // 2 -const static uint64_t SH_FLD_4_ADVANCE_PING_PONG = 1377; // 8 -const static uint64_t SH_FLD_4_ADVANCE_PR_VALUE = 1378; // 8 -const static uint64_t SH_FLD_4_ATESTSEL_0 = 1379; // 8 -const static uint64_t SH_FLD_4_ATESTSEL_0_LEN = 1380; // 8 -const static uint64_t SH_FLD_4_BB_LOCK0 = 1381; // 8 -const static uint64_t SH_FLD_4_BB_LOCK1 = 1382; // 8 -const static uint64_t SH_FLD_4_BIG_STEP_RIGHT = 1383; // 8 -const static uint64_t SH_FLD_4_BIT_CENTERED = 1384; // 8 -const static uint64_t SH_FLD_4_BIT_CENTERED_LEN = 1385; // 8 -const static uint64_t SH_FLD_4_BLFIFO_DIS = 1386; // 8 -const static uint64_t SH_FLD_4_BUMP = 1387; // 8 -const static uint64_t SH_FLD_4_CALGATE_ON = 1388; // 8 -const static uint64_t SH_FLD_4_CALIBRATE_BIT = 1389; // 8 -const static uint64_t SH_FLD_4_CALIBRATE_BIT_LEN = 1390; // 8 -const static uint64_t SH_FLD_4_CAL_ERROR = 1391; // 16 -const static uint64_t SH_FLD_4_CAL_ERROR_FINE = 1392; // 16 -const static uint64_t SH_FLD_4_CAL_GOOD = 1393; // 16 -const static uint64_t SH_FLD_4_CHECKER_ENABLE = 1394; // 8 -const static uint64_t SH_FLD_4_CHECKER_RESET = 1395; // 8 -const static uint64_t SH_FLD_4_CLK16_SINGLE_ENDED = 1396; // 64 -const static uint64_t SH_FLD_4_CLK18_SINGLE_ENDED = 1397; // 64 -const static uint64_t SH_FLD_4_CLK20_SINGLE_ENDED = 1398; // 64 -const static uint64_t SH_FLD_4_CLK22_SINGLE_ENDED = 1399; // 64 -const static uint64_t SH_FLD_4_CLK_LEVEL = 1400; // 8 -const static uint64_t SH_FLD_4_CLK_LEVEL_LEN = 1401; // 8 -const static uint64_t SH_FLD_4_CNTL_POL = 1402; // 8 -const static uint64_t SH_FLD_4_CNTL_SRC = 1403; // 8 -const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N0 = 1404; // 8 -const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N0_MASK = 1405; // 8 -const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N1 = 1406; // 8 -const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N1_MASK = 1407; // 8 -const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N2 = 1408; // 8 -const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N2_MASK = 1409; // 8 -const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N3 = 1410; // 8 -const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N3_MASK = 1411; // 8 -const static uint64_t SH_FLD_4_CONTINUOUS_UPDATE = 1412; // 16 -const static uint64_t SH_FLD_4_DD2_DQS_FIX_DIS = 1413; // 8 -const static uint64_t SH_FLD_4_DD2_FIX_DIS = 1414; // 8 -const static uint64_t SH_FLD_4_DD2_WTRFL_SYNC_DIS = 1415; // 8 -const static uint64_t SH_FLD_4_DELAYG = 1416; // 608 -const static uint64_t SH_FLD_4_DELAYG_LEN = 1417; // 608 -const static uint64_t SH_FLD_4_DELAY_PING_PONG_HALF = 1418; // 8 -const static uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH = 1419; // 8 -const static uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 1420; // 8 -const static uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW = 1421; // 8 -const static uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 1422; // 8 -const static uint64_t SH_FLD_4_DFT_FORCE_OUTPUTS = 1423; // 8 -const static uint64_t SH_FLD_4_DFT_PRBS7_GEN_EN = 1424; // 8 -const static uint64_t SH_FLD_4_DIGITAL_EN = 1425; // 8 -const static uint64_t SH_FLD_4_DIR_0_15 = 1426; // 8 -const static uint64_t SH_FLD_4_DIR_0_15_LEN = 1427; // 8 -const static uint64_t SH_FLD_4_DISABLE_0_15 = 1428; // 32 -const static uint64_t SH_FLD_4_DISABLE_0_15_LEN = 1429; // 32 -const static uint64_t SH_FLD_4_DISABLE_16_23 = 1430; // 32 -const static uint64_t SH_FLD_4_DISABLE_16_23_LEN = 1431; // 32 -const static uint64_t SH_FLD_4_DISABLE_PING_PONG = 1432; // 8 -const static uint64_t SH_FLD_4_DISABLE_TERMINATION = 1433; // 8 -const static uint64_t SH_FLD_4_DIS_CLK_GATE = 1434; // 8 -const static uint64_t SH_FLD_4_DL_FORCE_ON = 1435; // 8 -const static uint64_t SH_FLD_4_DONE = 1436; // 16 -const static uint64_t SH_FLD_4_DQS = 1437; // 8 -const static uint64_t SH_FLD_4_DQSCLK_SELECT0 = 1438; // 32 -const static uint64_t SH_FLD_4_DQSCLK_SELECT0_LEN = 1439; // 32 -const static uint64_t SH_FLD_4_DQSCLK_SELECT1 = 1440; // 32 -const static uint64_t SH_FLD_4_DQSCLK_SELECT1_LEN = 1441; // 32 -const static uint64_t SH_FLD_4_DQSCLK_SELECT2 = 1442; // 32 -const static uint64_t SH_FLD_4_DQSCLK_SELECT2_LEN = 1443; // 32 -const static uint64_t SH_FLD_4_DQSCLK_SELECT3 = 1444; // 32 -const static uint64_t SH_FLD_4_DQSCLK_SELECT3_LEN = 1445; // 32 -const static uint64_t SH_FLD_4_DQS_ALIGN_CNTR = 1446; // 8 -const static uint64_t SH_FLD_4_DQS_ALIGN_CNTR_LEN = 1447; // 8 -const static uint64_t SH_FLD_4_DQS_ALIGN_FIX_DIS = 1448; // 8 -const static uint64_t SH_FLD_4_DQS_ALIGN_ITR_CNTR = 1449; // 8 -const static uint64_t SH_FLD_4_DQS_ALIGN_ITR_CNTR_LEN = 1450; // 8 -const static uint64_t SH_FLD_4_DQS_ALIGN_JITTER = 1451; // 8 -const static uint64_t SH_FLD_4_DQS_ALIGN_QUAD = 1452; // 8 -const static uint64_t SH_FLD_4_DQS_ALIGN_QUAD_LEN = 1453; // 8 -const static uint64_t SH_FLD_4_DQS_ALIGN_SM = 1454; // 8 -const static uint64_t SH_FLD_4_DQS_ALIGN_SM_LEN = 1455; // 8 -const static uint64_t SH_FLD_4_DQS_LEN = 1456; // 8 -const static uint64_t SH_FLD_4_DQS_PIPE_FIX_DIS = 1457; // 8 -const static uint64_t SH_FLD_4_DQS_PIPE_FIX_DIS_LEN = 1458; // 8 -const static uint64_t SH_FLD_4_DRIFT_ERROR = 1459; // 8 -const static uint64_t SH_FLD_4_DRIFT_MASK = 1460; // 8 -const static uint64_t SH_FLD_4_DRVREN_MODE = 1461; // 8 -const static uint64_t SH_FLD_4_DYN_MCTERM_CNTL_EN = 1462; // 8 -const static uint64_t SH_FLD_4_DYN_POWER_CNTL_EN = 1463; // 8 -const static uint64_t SH_FLD_4_DYN_RX_GATE_CNTL_EN = 1464; // 8 -const static uint64_t SH_FLD_4_ENABLE = 1465; // 16 -const static uint64_t SH_FLD_4_ENABLE_0_15 = 1466; // 8 -const static uint64_t SH_FLD_4_ENABLE_0_15_LEN = 1467; // 8 -const static uint64_t SH_FLD_4_ENABLE_16_23 = 1468; // 8 -const static uint64_t SH_FLD_4_ENABLE_16_23_LEN = 1469; // 8 -const static uint64_t SH_FLD_4_EN_DQS_OFFSET = 1470; // 8 -const static uint64_t SH_FLD_4_EN_DRIVER_INVFB_DC = 1471; // 16 -const static uint64_t SH_FLD_4_EN_N_WR = 1472; // 8 -const static uint64_t SH_FLD_4_EN_N_WR_LEN = 1473; // 8 -const static uint64_t SH_FLD_4_EN_P_WR = 1474; // 16 -const static uint64_t SH_FLD_4_EN_P_WR_LEN = 1475; // 16 -const static uint64_t SH_FLD_4_ERROR = 1476; // 8 -const static uint64_t SH_FLD_4_ERROR_LEN = 1477; // 8 -const static uint64_t SH_FLD_4_ERR_CLK22_MASK = 1478; // 8 -const static uint64_t SH_FLD_4_EYE_CLIPPING = 1479; // 8 -const static uint64_t SH_FLD_4_EYE_CLIPPING_MASK = 1480; // 8 -const static uint64_t SH_FLD_4_FINE_STEPPING = 1481; // 8 -const static uint64_t SH_FLD_4_FLUSH = 1482; // 8 -const static uint64_t SH_FLD_4_FORCE_DQS_LANES_ON = 1483; // 8 -const static uint64_t SH_FLD_4_FORCE_FIFO_CAPTURE = 1484; // 8 -const static uint64_t SH_FLD_4_FRZSULV = 1485; // 16 -const static uint64_t SH_FLD_4_FW_LEFT_SIDE = 1486; // 8 -const static uint64_t SH_FLD_4_FW_LEFT_SIDE_LEN = 1487; // 8 -const static uint64_t SH_FLD_4_FW_RIGHT_SIDE = 1488; // 8 -const static uint64_t SH_FLD_4_FW_RIGHT_SIDE_LEN = 1489; // 8 -const static uint64_t SH_FLD_4_HS_DLLMUX_SEL0_0_3 = 1490; // 8 -const static uint64_t SH_FLD_4_HS_DLLMUX_SEL0_0_3_LEN = 1491; // 8 -const static uint64_t SH_FLD_4_HS_DLLMUX_SEL1_0_3 = 1492; // 8 -const static uint64_t SH_FLD_4_HS_DLLMUX_SEL1_0_3_LEN = 1493; // 8 -const static uint64_t SH_FLD_4_HS_PROBE_A = 1494; // 8 -const static uint64_t SH_FLD_4_HS_PROBE_A_LEN = 1495; // 8 -const static uint64_t SH_FLD_4_HS_PROBE_B = 1496; // 8 -const static uint64_t SH_FLD_4_HS_PROBE_B_LEN = 1497; // 8 -const static uint64_t SH_FLD_4_HW_VALUE = 1498; // 8 -const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N0 = 1499; // 8 -const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N0_MASK = 1500; // 8 -const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N1 = 1501; // 8 -const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N1_MASK = 1502; // 8 -const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N2 = 1503; // 8 -const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N2_MASK = 1504; // 8 -const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N3 = 1505; // 8 -const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N3_MASK = 1506; // 8 -const static uint64_t SH_FLD_4_INIT_IO = 1507; // 8 -const static uint64_t SH_FLD_4_INIT_RXDLL_CAL_RESET = 1508; // 16 -const static uint64_t SH_FLD_4_INIT_RXDLL_CAL_UPDATE = 1509; // 16 -const static uint64_t SH_FLD_4_INTERP_SIG_SLEW = 1510; // 8 -const static uint64_t SH_FLD_4_INTERP_SIG_SLEW_LEN = 1511; // 8 -const static uint64_t SH_FLD_4_INVALID_NS_BIG_R = 1512; // 8 -const static uint64_t SH_FLD_4_INVALID_NS_BIG_R_MASK = 1513; // 8 -const static uint64_t SH_FLD_4_INVALID_NS_SMALL_L = 1514; // 8 -const static uint64_t SH_FLD_4_INVALID_NS_SMALL_L_MASK = 1515; // 8 -const static uint64_t SH_FLD_4_INVALID_NS_SMALL_R = 1516; // 8 -const static uint64_t SH_FLD_4_INVALID_NS_SMALL_R_MASK = 1517; // 8 -const static uint64_t SH_FLD_4_JUMP_BACK_RIGHT = 1518; // 8 -const static uint64_t SH_FLD_4_LEADING_EDGE_FOUND_MASK = 1519; // 8 -const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND = 1520; // 8 -const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15 = 1521; // 8 -const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15_LEN = 1522; // 8 -const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23 = 1523; // 8 -const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23_LEN = 1524; // 8 -const static uint64_t SH_FLD_4_LEN = 1525; // 84 -const static uint64_t SH_FLD_4_LOOPBACK_DLY12 = 1526; // 8 -const static uint64_t SH_FLD_4_LOOPBACK_FIX_EN = 1527; // 8 -const static uint64_t SH_FLD_4_MATCH_STEP_RIGHT = 1528; // 8 -const static uint64_t SH_FLD_4_MAX_DQS = 1529; // 8 -const static uint64_t SH_FLD_4_MAX_DQS_ITER = 1530; // 8 -const static uint64_t SH_FLD_4_MAX_DQS_LEN = 1531; // 8 -const static uint64_t SH_FLD_4_MEMINTD00 = 1532; // 8 -const static uint64_t SH_FLD_4_MEMINTD00_LEN = 1533; // 8 -const static uint64_t SH_FLD_4_MEMINTD01 = 1534; // 8 -const static uint64_t SH_FLD_4_MEMINTD01_LEN = 1535; // 8 -const static uint64_t SH_FLD_4_MEMINTD02 = 1536; // 8 -const static uint64_t SH_FLD_4_MEMINTD02_LEN = 1537; // 8 -const static uint64_t SH_FLD_4_MEMINTD03 = 1538; // 8 -const static uint64_t SH_FLD_4_MEMINTD03_LEN = 1539; // 8 -const static uint64_t SH_FLD_4_MEMINTD04 = 1540; // 8 -const static uint64_t SH_FLD_4_MEMINTD04_LEN = 1541; // 8 -const static uint64_t SH_FLD_4_MEMINTD05 = 1542; // 8 -const static uint64_t SH_FLD_4_MEMINTD05_LEN = 1543; // 8 -const static uint64_t SH_FLD_4_MEMINTD06 = 1544; // 8 -const static uint64_t SH_FLD_4_MEMINTD06_LEN = 1545; // 8 -const static uint64_t SH_FLD_4_MEMINTD07 = 1546; // 8 -const static uint64_t SH_FLD_4_MEMINTD07_LEN = 1547; // 8 -const static uint64_t SH_FLD_4_MEMINTD08 = 1548; // 8 -const static uint64_t SH_FLD_4_MEMINTD08_LEN = 1549; // 8 -const static uint64_t SH_FLD_4_MEMINTD09 = 1550; // 8 -const static uint64_t SH_FLD_4_MEMINTD09_LEN = 1551; // 8 -const static uint64_t SH_FLD_4_MEMINTD10 = 1552; // 8 -const static uint64_t SH_FLD_4_MEMINTD10_LEN = 1553; // 8 -const static uint64_t SH_FLD_4_MEMINTD11 = 1554; // 8 -const static uint64_t SH_FLD_4_MEMINTD11_LEN = 1555; // 8 -const static uint64_t SH_FLD_4_MEMINTD12 = 1556; // 8 -const static uint64_t SH_FLD_4_MEMINTD12_LEN = 1557; // 8 -const static uint64_t SH_FLD_4_MEMINTD13 = 1558; // 8 -const static uint64_t SH_FLD_4_MEMINTD13_LEN = 1559; // 8 -const static uint64_t SH_FLD_4_MEMINTD14 = 1560; // 8 -const static uint64_t SH_FLD_4_MEMINTD14_LEN = 1561; // 8 -const static uint64_t SH_FLD_4_MEMINTD15 = 1562; // 8 -const static uint64_t SH_FLD_4_MEMINTD15_LEN = 1563; // 8 -const static uint64_t SH_FLD_4_MEMINTD16 = 1564; // 8 -const static uint64_t SH_FLD_4_MEMINTD16_LEN = 1565; // 8 -const static uint64_t SH_FLD_4_MEMINTD17 = 1566; // 8 -const static uint64_t SH_FLD_4_MEMINTD17_LEN = 1567; // 8 -const static uint64_t SH_FLD_4_MEMINTD18 = 1568; // 8 -const static uint64_t SH_FLD_4_MEMINTD18_LEN = 1569; // 8 -const static uint64_t SH_FLD_4_MEMINTD19 = 1570; // 8 -const static uint64_t SH_FLD_4_MEMINTD19_LEN = 1571; // 8 -const static uint64_t SH_FLD_4_MEMINTD20 = 1572; // 8 -const static uint64_t SH_FLD_4_MEMINTD20_LEN = 1573; // 8 -const static uint64_t SH_FLD_4_MEMINTD21 = 1574; // 8 -const static uint64_t SH_FLD_4_MEMINTD21_LEN = 1575; // 8 -const static uint64_t SH_FLD_4_MEMINTD22 = 1576; // 8 -const static uint64_t SH_FLD_4_MEMINTD22_LEN = 1577; // 8 -const static uint64_t SH_FLD_4_MEMINTD23 = 1578; // 8 -const static uint64_t SH_FLD_4_MEMINTD23_LEN = 1579; // 8 -const static uint64_t SH_FLD_4_MIN_EYE = 1580; // 8 -const static uint64_t SH_FLD_4_MIN_EYE_MASK = 1581; // 8 -const static uint64_t SH_FLD_4_MIN_RD_EYE_SIZE = 1582; // 8 -const static uint64_t SH_FLD_4_MIN_RD_EYE_SIZE_LEN = 1583; // 8 -const static uint64_t SH_FLD_4_MRS_CMD_N0 = 1584; // 8 -const static uint64_t SH_FLD_4_MRS_CMD_N1 = 1585; // 8 -const static uint64_t SH_FLD_4_MRS_CMD_N2 = 1586; // 8 -const static uint64_t SH_FLD_4_MRS_CMD_N3 = 1587; // 8 -const static uint64_t SH_FLD_4_N0 = 1588; // 64 -const static uint64_t SH_FLD_4_N0_LEN = 1589; // 64 -const static uint64_t SH_FLD_4_N1 = 1590; // 64 -const static uint64_t SH_FLD_4_N1_LEN = 1591; // 64 -const static uint64_t SH_FLD_4_N2 = 1592; // 64 -const static uint64_t SH_FLD_4_N2_LEN = 1593; // 64 -const static uint64_t SH_FLD_4_N3 = 1594; // 64 -const static uint64_t SH_FLD_4_N3_LEN = 1595; // 64 -const static uint64_t SH_FLD_4_NIB0 = 1596; // 8 -const static uint64_t SH_FLD_4_NIB0TCFLIP_DC = 1597; // 8 -const static uint64_t SH_FLD_4_NIB0_LEN = 1598; // 8 -const static uint64_t SH_FLD_4_NIB1 = 1599; // 8 -const static uint64_t SH_FLD_4_NIB1TCFLIP_DC = 1600; // 8 -const static uint64_t SH_FLD_4_NIB1_LEN = 1601; // 8 -const static uint64_t SH_FLD_4_NIB2 = 1602; // 8 -const static uint64_t SH_FLD_4_NIB2TCFLIP_DC = 1603; // 8 -const static uint64_t SH_FLD_4_NIB2_LEN = 1604; // 8 -const static uint64_t SH_FLD_4_NIB3 = 1605; // 8 -const static uint64_t SH_FLD_4_NIB3TCFLIP_DC = 1606; // 8 -const static uint64_t SH_FLD_4_NIB3_LEN = 1607; // 8 -const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_CAP = 1608; // 16 -const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_CAP_LEN = 1609; // 16 -const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_IND = 1610; // 16 -const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_IND_LEN = 1611; // 16 -const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_RES = 1612; // 16 -const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_RES_LEN = 1613; // 16 -const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_CAP = 1614; // 16 -const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_CAP_LEN = 1615; // 16 -const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_IND = 1616; // 16 -const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_IND_LEN = 1617; // 16 -const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_RES = 1618; // 16 -const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_RES_LEN = 1619; // 16 -const static uint64_t SH_FLD_4_NO_DQS = 1620; // 8 -const static uint64_t SH_FLD_4_NO_DQS_MASK = 1621; // 8 -const static uint64_t SH_FLD_4_NO_EYE_DETECTED = 1622; // 8 -const static uint64_t SH_FLD_4_NO_EYE_DETECTED_MASK = 1623; // 8 -const static uint64_t SH_FLD_4_NO_LOCK = 1624; // 8 -const static uint64_t SH_FLD_4_NO_LOCK_MASK = 1625; // 8 -const static uint64_t SH_FLD_4_OFFSET0 = 1626; // 8 -const static uint64_t SH_FLD_4_OFFSET0_LEN = 1627; // 8 -const static uint64_t SH_FLD_4_OFFSET1 = 1628; // 8 -const static uint64_t SH_FLD_4_OFFSET1_LEN = 1629; // 8 -const static uint64_t SH_FLD_4_OFFSET2 = 1630; // 16 -const static uint64_t SH_FLD_4_OFFSET2_LEN = 1631; // 16 -const static uint64_t SH_FLD_4_OFFSET3 = 1632; // 16 -const static uint64_t SH_FLD_4_OFFSET3_LEN = 1633; // 16 -const static uint64_t SH_FLD_4_OFFSET4 = 1634; // 16 -const static uint64_t SH_FLD_4_OFFSET4_LEN = 1635; // 16 -const static uint64_t SH_FLD_4_OFFSET5 = 1636; // 16 -const static uint64_t SH_FLD_4_OFFSET5_LEN = 1637; // 16 -const static uint64_t SH_FLD_4_OFFSET6 = 1638; // 16 -const static uint64_t SH_FLD_4_OFFSET6_LEN = 1639; // 16 -const static uint64_t SH_FLD_4_OFFSET7 = 1640; // 16 -const static uint64_t SH_FLD_4_OFFSET7_LEN = 1641; // 16 -const static uint64_t SH_FLD_4_OFFSET_ERR = 1642; // 8 -const static uint64_t SH_FLD_4_OFFSET_ERR_MASK = 1643; // 8 -const static uint64_t SH_FLD_4_OPERATE_MODE = 1644; // 8 -const static uint64_t SH_FLD_4_OPERATE_MODE_LEN = 1645; // 8 -const static uint64_t SH_FLD_4_PERCAL_PWR_DIS = 1646; // 8 -const static uint64_t SH_FLD_4_PER_CAL_UPDATE_DISABLE = 1647; // 8 -const static uint64_t SH_FLD_4_PHASE_ALIGN_RESET = 1648; // 16 -const static uint64_t SH_FLD_4_PHASE_CNTL_EN = 1649; // 16 -const static uint64_t SH_FLD_4_PHASE_DEFAULT_EN = 1650; // 16 -const static uint64_t SH_FLD_4_POS_EDGE_ALIGN = 1651; // 16 -const static uint64_t SH_FLD_4_QUAD0 = 1652; // 8 -const static uint64_t SH_FLD_4_QUAD0_CLK16 = 1653; // 64 -const static uint64_t SH_FLD_4_QUAD0_CLK18 = 1654; // 64 -const static uint64_t SH_FLD_4_QUAD0_LEN = 1655; // 8 -const static uint64_t SH_FLD_4_QUAD1 = 1656; // 8 -const static uint64_t SH_FLD_4_QUAD1_CLK16 = 1657; // 64 -const static uint64_t SH_FLD_4_QUAD1_CLK18 = 1658; // 64 -const static uint64_t SH_FLD_4_QUAD1_LEN = 1659; // 8 -const static uint64_t SH_FLD_4_QUAD2 = 1660; // 8 -const static uint64_t SH_FLD_4_QUAD2_CLK16 = 1661; // 64 -const static uint64_t SH_FLD_4_QUAD2_CLK18 = 1662; // 32 -const static uint64_t SH_FLD_4_QUAD2_CLK20 = 1663; // 64 -const static uint64_t SH_FLD_4_QUAD2_CLK22 = 1664; // 64 -const static uint64_t SH_FLD_4_QUAD2_LEN = 1665; // 8 -const static uint64_t SH_FLD_4_QUAD3 = 1666; // 8 -const static uint64_t SH_FLD_4_QUAD3_CLK16 = 1667; // 64 -const static uint64_t SH_FLD_4_QUAD3_CLK18 = 1668; // 32 -const static uint64_t SH_FLD_4_QUAD3_CLK20 = 1669; // 64 -const static uint64_t SH_FLD_4_QUAD3_CLK22 = 1670; // 64 -const static uint64_t SH_FLD_4_QUAD3_LEN = 1671; // 8 -const static uint64_t SH_FLD_4_RD = 1672; // 136 -const static uint64_t SH_FLD_4_RDCLK_SELECT0 = 1673; // 32 -const static uint64_t SH_FLD_4_RDCLK_SELECT0_LEN = 1674; // 32 -const static uint64_t SH_FLD_4_RDCLK_SELECT1 = 1675; // 32 -const static uint64_t SH_FLD_4_RDCLK_SELECT1_LEN = 1676; // 32 -const static uint64_t SH_FLD_4_RDCLK_SELECT2 = 1677; // 32 -const static uint64_t SH_FLD_4_RDCLK_SELECT2_LEN = 1678; // 32 -const static uint64_t SH_FLD_4_RDCLK_SELECT3 = 1679; // 32 -const static uint64_t SH_FLD_4_RDCLK_SELECT3_LEN = 1680; // 32 -const static uint64_t SH_FLD_4_RD_DELAY0 = 1681; // 56 -const static uint64_t SH_FLD_4_RD_DELAY0_LEN = 1682; // 56 -const static uint64_t SH_FLD_4_RD_DELAY1 = 1683; // 56 -const static uint64_t SH_FLD_4_RD_DELAY1_LEN = 1684; // 56 -const static uint64_t SH_FLD_4_RD_DELAY2 = 1685; // 56 -const static uint64_t SH_FLD_4_RD_DELAY2_LEN = 1686; // 56 -const static uint64_t SH_FLD_4_RD_DELAY3 = 1687; // 56 -const static uint64_t SH_FLD_4_RD_DELAY3_LEN = 1688; // 56 -const static uint64_t SH_FLD_4_RD_DELAY4 = 1689; // 56 -const static uint64_t SH_FLD_4_RD_DELAY4_LEN = 1690; // 56 -const static uint64_t SH_FLD_4_RD_DELAY5 = 1691; // 56 -const static uint64_t SH_FLD_4_RD_DELAY5_LEN = 1692; // 56 -const static uint64_t SH_FLD_4_RD_DELAY6 = 1693; // 56 -const static uint64_t SH_FLD_4_RD_DELAY6_LEN = 1694; // 56 -const static uint64_t SH_FLD_4_RD_DELAY7 = 1695; // 56 -const static uint64_t SH_FLD_4_RD_DELAY7_LEN = 1696; // 56 -const static uint64_t SH_FLD_4_RD_LEN = 1697; // 136 -const static uint64_t SH_FLD_4_RD_SIZE0 = 1698; // 88 -const static uint64_t SH_FLD_4_RD_SIZE0_LEN = 1699; // 88 -const static uint64_t SH_FLD_4_RD_SIZE1 = 1700; // 88 -const static uint64_t SH_FLD_4_RD_SIZE1_LEN = 1701; // 88 -const static uint64_t SH_FLD_4_RD_SIZE2 = 1702; // 88 -const static uint64_t SH_FLD_4_RD_SIZE2_LEN = 1703; // 88 -const static uint64_t SH_FLD_4_RD_SIZE3 = 1704; // 88 -const static uint64_t SH_FLD_4_RD_SIZE3_LEN = 1705; // 88 -const static uint64_t SH_FLD_4_RD_SIZE4 = 1706; // 88 -const static uint64_t SH_FLD_4_RD_SIZE4_LEN = 1707; // 88 -const static uint64_t SH_FLD_4_RD_SIZE5 = 1708; // 88 -const static uint64_t SH_FLD_4_RD_SIZE5_LEN = 1709; // 88 -const static uint64_t SH_FLD_4_RD_SIZE6 = 1710; // 88 -const static uint64_t SH_FLD_4_RD_SIZE6_LEN = 1711; // 88 -const static uint64_t SH_FLD_4_RD_SIZE7 = 1712; // 88 -const static uint64_t SH_FLD_4_RD_SIZE7_LEN = 1713; // 88 -const static uint64_t SH_FLD_4_READ_CENTERING_MODE = 1714; // 8 -const static uint64_t SH_FLD_4_READ_CENTERING_MODE_LEN = 1715; // 8 -const static uint64_t SH_FLD_4_REFERENCE1 = 1716; // 8 -const static uint64_t SH_FLD_4_REFERENCE1_LEN = 1717; // 8 -const static uint64_t SH_FLD_4_REFERENCE2 = 1718; // 8 -const static uint64_t SH_FLD_4_REFERENCE2_LEN = 1719; // 8 -const static uint64_t SH_FLD_4_REFERENCE3 = 1720; // 8 -const static uint64_t SH_FLD_4_REFERENCE3_LEN = 1721; // 8 -const static uint64_t SH_FLD_4_REGS_RXDLL_CAL_SKIP = 1722; // 16 -const static uint64_t SH_FLD_4_REGS_RXDLL_CAL_SKIP_LEN = 1723; // 16 -const static uint64_t SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY2 = 1724; // 16 -const static uint64_t SH_FLD_4_REGS_RXDLL_COARSE_EN = 1725; // 16 -const static uint64_t SH_FLD_4_REGS_RXDLL_COARSE_EN_LEN = 1726; // 16 -const static uint64_t SH_FLD_4_REGS_RXDLL_DAC_COARSE = 1727; // 16 -const static uint64_t SH_FLD_4_REGS_RXDLL_DAC_COARSE_LEN = 1728; // 16 -const static uint64_t SH_FLD_4_REGS_RXDLL_VREG_LOWER = 1729; // 16 -const static uint64_t SH_FLD_4_REGS_RXDLL_VREG_LOWER_LEN = 1730; // 16 -const static uint64_t SH_FLD_4_REGS_RXDLL_VREG_UPPER = 1731; // 16 -const static uint64_t SH_FLD_4_REGS_RXDLL_VREG_UPPER_LEN = 1732; // 16 -const static uint64_t SH_FLD_4_RESERVED = 1733; // 1 -const static uint64_t SH_FLD_4_RESERVED_56_63 = 1734; // 8 -const static uint64_t SH_FLD_4_RESERVED_56_63_LEN = 1735; // 8 -const static uint64_t SH_FLD_4_ROT0 = 1736; // 8 -const static uint64_t SH_FLD_4_ROT0_LEN = 1737; // 8 -const static uint64_t SH_FLD_4_ROT1 = 1738; // 8 -const static uint64_t SH_FLD_4_ROT1_LEN = 1739; // 8 -const static uint64_t SH_FLD_4_ROT_CLK_N0 = 1740; // 64 -const static uint64_t SH_FLD_4_ROT_CLK_N0_LEN = 1741; // 64 -const static uint64_t SH_FLD_4_ROT_CLK_N1 = 1742; // 64 -const static uint64_t SH_FLD_4_ROT_CLK_N1_LEN = 1743; // 64 -const static uint64_t SH_FLD_4_ROT_N0 = 1744; // 64 -const static uint64_t SH_FLD_4_ROT_N0_LEN = 1745; // 64 -const static uint64_t SH_FLD_4_ROT_N1 = 1746; // 64 -const static uint64_t SH_FLD_4_ROT_N1_LEN = 1747; // 64 -const static uint64_t SH_FLD_4_ROT_OVERRIDE = 1748; // 16 -const static uint64_t SH_FLD_4_ROT_OVERRIDE_EN = 1749; // 16 -const static uint64_t SH_FLD_4_ROT_OVERRIDE_LEN = 1750; // 16 -const static uint64_t SH_FLD_4_RXREG_COMPCON_DC = 1751; // 16 -const static uint64_t SH_FLD_4_RXREG_COMPCON_DC_LEN = 1752; // 16 -const static uint64_t SH_FLD_4_RXREG_CON_DC = 1753; // 16 -const static uint64_t SH_FLD_4_RXREG_DAC_PULLUP_DC = 1754; // 16 -const static uint64_t SH_FLD_4_RXREG_DRVCON_DC = 1755; // 16 -const static uint64_t SH_FLD_4_RXREG_DRVCON_DC_LEN = 1756; // 16 -const static uint64_t SH_FLD_4_RXREG_FILTER_LENGTH_DC = 1757; // 16 -const static uint64_t SH_FLD_4_RXREG_FILTER_LENGTH_DC_LEN = 1758; // 16 -const static uint64_t SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC = 1759; // 16 -const static uint64_t SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 1760; // 16 -const static uint64_t SH_FLD_4_RXREG_REF_SEL_DC = 1761; // 16 -const static uint64_t SH_FLD_4_RXREG_REF_SEL_DC_LEN = 1762; // 16 -const static uint64_t SH_FLD_4_S0ACENSLICENDRV_DC = 1763; // 8 -const static uint64_t SH_FLD_4_S0ACENSLICENDRV_DC_LEN = 1764; // 8 -const static uint64_t SH_FLD_4_S0ACENSLICEPDRV_DC = 1765; // 8 -const static uint64_t SH_FLD_4_S0ACENSLICEPDRV_DC_LEN = 1766; // 8 -const static uint64_t SH_FLD_4_S0ACENSLICEPTERM_DC = 1767; // 8 -const static uint64_t SH_FLD_4_S0ACENSLICEPTERM_DC_LEN = 1768; // 8 -const static uint64_t SH_FLD_4_S0INSDLYTAP = 1769; // 8 -const static uint64_t SH_FLD_4_S1ACENSLICENDRV_DC = 1770; // 8 -const static uint64_t SH_FLD_4_S1ACENSLICENDRV_DC_LEN = 1771; // 8 -const static uint64_t SH_FLD_4_S1ACENSLICEPDRV_DC = 1772; // 8 -const static uint64_t SH_FLD_4_S1ACENSLICEPDRV_DC_LEN = 1773; // 8 -const static uint64_t SH_FLD_4_S1ACENSLICEPTERM_DC = 1774; // 8 -const static uint64_t SH_FLD_4_S1ACENSLICEPTERM_DC_LEN = 1775; // 8 -const static uint64_t SH_FLD_4_S1INSDLYTAP = 1776; // 8 -const static uint64_t SH_FLD_4_SEND_ENABLE = 1777; // 1 -const static uint64_t SH_FLD_4_SEND_MODE = 1778; // 1 -const static uint64_t SH_FLD_4_SMALL_STEP_LEFT = 1779; // 8 -const static uint64_t SH_FLD_4_SMALL_STEP_RIGHT = 1780; // 8 -const static uint64_t SH_FLD_4_SPARE_SECTOR_BUFFER_CONTROL = 1781; // 1 -const static uint64_t SH_FLD_4_SYNC = 1782; // 8 -const static uint64_t SH_FLD_4_SYNC_LEN = 1783; // 8 -const static uint64_t SH_FLD_4_SYSCLK_DQSCLK_OFFSET = 1784; // 8 -const static uint64_t SH_FLD_4_SYSCLK_DQSCLK_OFFSET_LEN = 1785; // 8 -const static uint64_t SH_FLD_4_SYSCLK_RDCLK_OFFSET = 1786; // 8 -const static uint64_t SH_FLD_4_SYSCLK_RDCLK_OFFSET_LEN = 1787; // 8 -const static uint64_t SH_FLD_4_TRAILING_EDGE_FOUND_MASK = 1788; // 8 -const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND = 1789; // 8 -const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15 = 1790; // 8 -const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 1791; // 8 -const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23 = 1792; // 8 -const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 1793; // 8 -const static uint64_t SH_FLD_4_TRIG_PERIOD = 1794; // 8 -const static uint64_t SH_FLD_4_TSYS = 1795; // 8 -const static uint64_t SH_FLD_4_TSYS_LEN = 1796; // 8 -const static uint64_t SH_FLD_4_TUNEATST_0 = 1797; // 8 -const static uint64_t SH_FLD_4_TUNEATST_1 = 1798; // 8 -const static uint64_t SH_FLD_4_VALID_NS_BIG_L = 1799; // 8 -const static uint64_t SH_FLD_4_VALID_NS_BIG_L_MASK = 1800; // 8 -const static uint64_t SH_FLD_4_VALID_NS_BIG_R = 1801; // 8 -const static uint64_t SH_FLD_4_VALID_NS_BIG_R_MASK = 1802; // 8 -const static uint64_t SH_FLD_4_VALID_NS_JUMP_BACK = 1803; // 8 -const static uint64_t SH_FLD_4_VALID_NS_JUMP_BACK_MASK = 1804; // 8 -const static uint64_t SH_FLD_4_WL_ADVANCE_DISABLE = 1805; // 8 -const static uint64_t SH_FLD_4_WL_ERR_CLK16 = 1806; // 16 -const static uint64_t SH_FLD_4_WL_ERR_CLK16_MASK = 1807; // 8 -const static uint64_t SH_FLD_4_WL_ERR_CLK18 = 1808; // 16 -const static uint64_t SH_FLD_4_WL_ERR_CLK18_MASK = 1809; // 8 -const static uint64_t SH_FLD_4_WL_ERR_CLK20 = 1810; // 16 -const static uint64_t SH_FLD_4_WL_ERR_CLK20_MASK = 1811; // 8 -const static uint64_t SH_FLD_4_WL_ERR_CLK22 = 1812; // 16 -const static uint64_t SH_FLD_4_WRAPSEL = 1813; // 8 -const static uint64_t SH_FLD_4_WTRFL_AVE_DIS = 1814; // 8 -const static uint64_t SH_FLD_4_ZERO_DETECTED = 1815; // 8 -const static uint64_t SH_FLD_5 = 1816; // 455 -const static uint64_t SH_FLD_5_LEN = 1817; // 43 -const static uint64_t SH_FLD_5_RESERVED = 1818; // 1 -const static uint64_t SH_FLD_5_SPARE_SECTOR_BUFFER_CONTROL = 1819; // 1 -const static uint64_t SH_FLD_6 = 1820; // 455 -const static uint64_t SH_FLD_6_LEN = 1821; // 43 -const static uint64_t SH_FLD_6_RESERVED = 1822; // 1 -const static uint64_t SH_FLD_6_SPARE_SECTOR_BUFFER_CONTROL = 1823; // 1 -const static uint64_t SH_FLD_6_SPARE_TERM_DIS = 1824; // 1 -const static uint64_t SH_FLD_7 = 1825; // 412 -const static uint64_t SH_FLD_7_RESERVED = 1826; // 1 -const static uint64_t SH_FLD_7_SPARE_SECTOR_BUFFER_CONTROL = 1827; // 1 -const static uint64_t SH_FLD_7_SPARE_TERM_DIS = 1828; // 1 -const static uint64_t SH_FLD_8 = 1829; // 6 -const static uint64_t SH_FLD_842_FC_SELECT = 1830; // 1 -const static uint64_t SH_FLD_842_FC_SELECT_LEN = 1831; // 1 -const static uint64_t SH_FLD_842_LATENCY_CFG = 1832; // 1 -const static uint64_t SH_FLD_8_11_SPARE = 1833; // 8 -const static uint64_t SH_FLD_8_11_SPARE_LEN = 1834; // 8 -const static uint64_t SH_FLD_8_9 = 1835; // 6 -const static uint64_t SH_FLD_8_9_LEN = 1836; // 6 -const static uint64_t SH_FLD_8_RESERVED = 1837; // 2 -const static uint64_t SH_FLD_8_SPARE_FILTER_PLL_CONTROL = 1838; // 1 -const static uint64_t SH_FLD_8_SPARE_SECTOR_BUFFER_CONTROL = 1839; // 1 -const static uint64_t SH_FLD_9 = 1840; // 6 -const static uint64_t SH_FLD_9_RESERVED = 1841; // 1 -const static uint64_t SH_FLD_9_SPARE_FILTER_PLL_CONTROL = 1842; // 1 -const static uint64_t SH_FLD_9_SPARE_SECTOR_BUFFER_CONTROL = 1843; // 1 -const static uint64_t SH_FLD_ABIST = 1844; // 43 -const static uint64_t SH_FLD_ABORT = 1845; // 6 -const static uint64_t SH_FLD_ABORTED_CMD = 1846; // 1 -const static uint64_t SH_FLD_ABORT_CHECK_TIMEOUT_SEL = 1847; // 6 -const static uint64_t SH_FLD_ABORT_CHECK_TIMEOUT_SEL_LEN = 1848; // 6 -const static uint64_t SH_FLD_ABORT_ON_ERROR = 1849; // 8 -const static uint64_t SH_FLD_ABORT_ON_ERR_EN = 1850; // 8 -const static uint64_t SH_FLD_ACCR_OVERRIDE_EN = 1851; // 12 -const static uint64_t SH_FLD_ACCUM = 1852; // 6 -const static uint64_t SH_FLD_ACCUM_LEN = 1853; // 6 -const static uint64_t SH_FLD_ACK = 1854; // 1 -const static uint64_t SH_FLD_ACM_EN = 1855; // 1 -const static uint64_t SH_FLD_ACT = 1856; // 62 -const static uint64_t SH_FLD_ACTCYCLECNT = 1857; // 3 -const static uint64_t SH_FLD_ACTCYCLECNT_LEN = 1858; // 3 -const static uint64_t SH_FLD_ACTION0 = 1859; // 47 -const static uint64_t SH_FLD_ACTION0_LEN = 1860; // 47 -const static uint64_t SH_FLD_ACTION1 = 1861; // 47 -const static uint64_t SH_FLD_ACTION1_LEN = 1862; // 47 -const static uint64_t SH_FLD_ACTION_0 = 1863; // 4 -const static uint64_t SH_FLD_ACTION_0_LEN = 1864; // 4 -const static uint64_t SH_FLD_ACTION_1 = 1865; // 4 -const static uint64_t SH_FLD_ACTION_1_LEN = 1866; // 4 -const static uint64_t SH_FLD_ACTIVATE_COUNT = 1867; // 8 -const static uint64_t SH_FLD_ACTIVATE_COUNT_LEN = 1868; // 8 -const static uint64_t SH_FLD_ACTIVE_CHANNEL_CNT = 1869; // 1 -const static uint64_t SH_FLD_ACTIVE_CHANNEL_CNT_LEN = 1870; // 1 -const static uint64_t SH_FLD_ACTIVITY = 1871; // 129 -const static uint64_t SH_FLD_ACTIVITY_0 = 1872; // 1 -const static uint64_t SH_FLD_ACTIVITY_0_LEN = 1873; // 1 -const static uint64_t SH_FLD_ACTIVITY_1 = 1874; // 1 -const static uint64_t SH_FLD_ACTIVITY_1_LEN = 1875; // 1 -const static uint64_t SH_FLD_ACTIVITY_2 = 1876; // 1 -const static uint64_t SH_FLD_ACTIVITY_2_LEN = 1877; // 1 -const static uint64_t SH_FLD_ACTIVITY_3 = 1878; // 1 -const static uint64_t SH_FLD_ACTIVITY_3_LEN = 1879; // 1 -const static uint64_t SH_FLD_ACTIVITY_LEN = 1880; // 129 -const static uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE = 1881; // 24 -const static uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_EN = 1882; // 24 -const static uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_LEN = 1883; // 24 -const static uint64_t SH_FLD_ACTUAL_CLK_SB_SPARE = 1884; // 24 -const static uint64_t SH_FLD_ACTUAL_CLK_SB_STRENGTH = 1885; // 24 -const static uint64_t SH_FLD_ACTUAL_CLK_SB_STRENGTH_LEN = 1886; // 24 -const static uint64_t SH_FLD_ACTUAL_CLK_SW_RESCLK = 1887; // 24 -const static uint64_t SH_FLD_ACTUAL_CLK_SW_RESCLK_LEN = 1888; // 24 -const static uint64_t SH_FLD_ACTUAL_CLK_SW_SPARE = 1889; // 24 -const static uint64_t SH_FLD_ACTUAL_ERROR = 1890; // 3 -const static uint64_t SH_FLD_ACTUAL_ERROR_LEN = 1891; // 3 -const static uint64_t SH_FLD_ACT_CHECK_TIMEOUT_SEL = 1892; // 4 -const static uint64_t SH_FLD_ACT_CHECK_TIMEOUT_SEL_LEN = 1893; // 4 -const static uint64_t SH_FLD_ACT_DIS = 1894; // 43 -const static uint64_t SH_FLD_ACT_STOP_LEVEL = 1895; // 30 -const static uint64_t SH_FLD_ACT_STOP_LEVEL_FSP = 1896; // 30 -const static uint64_t SH_FLD_ACT_STOP_LEVEL_FSP_LEN = 1897; // 30 -const static uint64_t SH_FLD_ACT_STOP_LEVEL_HYP = 1898; // 30 -const static uint64_t SH_FLD_ACT_STOP_LEVEL_HYP_LEN = 1899; // 30 -const static uint64_t SH_FLD_ACT_STOP_LEVEL_LEN = 1900; // 30 -const static uint64_t SH_FLD_ACT_STOP_LEVEL_OCC = 1901; // 30 -const static uint64_t SH_FLD_ACT_STOP_LEVEL_OCC_LEN = 1902; // 30 -const static uint64_t SH_FLD_ACT_STOP_LEVEL_OTR = 1903; // 30 -const static uint64_t SH_FLD_ACT_STOP_LEVEL_OTR_LEN = 1904; // 30 -const static uint64_t SH_FLD_ADAPTEST_1BIT_ENABLE = 1905; // 1 -const static uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX = 1906; // 1 -const static uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX_LEN = 1907; // 1 -const static uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN = 1908; // 1 -const static uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN_LEN = 1909; // 1 -const static uint64_t SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH = 1910; // 1 -const static uint64_t SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH_LEN = 1911; // 1 -const static uint64_t SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH = 1912; // 1 -const static uint64_t SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH_LEN = 1913; // 1 -const static uint64_t SH_FLD_ADAPTEST_ENABLE = 1914; // 1 -const static uint64_t SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH = 1915; // 1 -const static uint64_t SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH_LEN = 1916; // 1 -const static uint64_t SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH = 1917; // 1 -const static uint64_t SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH_LEN = 1918; // 1 -const static uint64_t SH_FLD_ADAPTEST_SAMPLE_SIZE = 1919; // 1 -const static uint64_t SH_FLD_ADAPTEST_SAMPLE_SIZE_LEN = 1920; // 1 -const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0 = 1921; // 1 -const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0_LEN = 1922; // 1 -const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1 = 1923; // 1 -const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1_LEN = 1924; // 1 -const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0 = 1925; // 1 -const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0_LEN = 1926; // 1 -const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1 = 1927; // 1 -const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1_LEN = 1928; // 1 -const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_TH = 1929; // 1 -const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_TH_LEN = 1930; // 1 -const static uint64_t SH_FLD_ADAPTEST_WINDOW_SIZE = 1931; // 1 -const static uint64_t SH_FLD_ADAPTEST_WINDOW_SIZE_LEN = 1932; // 1 -const static uint64_t SH_FLD_ADCFSM_ONGOING = 1933; // 1 -const static uint64_t SH_FLD_ADDR = 1934; // 38 -const static uint64_t SH_FLD_ADDR0 = 1935; // 8 -const static uint64_t SH_FLD_ADDR0_LEN = 1936; // 8 -const static uint64_t SH_FLD_ADDR1 = 1937; // 8 -const static uint64_t SH_FLD_ADDR1_LEN = 1938; // 8 -const static uint64_t SH_FLD_ADDR2 = 1939; // 16 -const static uint64_t SH_FLD_ADDR2_LEN = 1940; // 16 -const static uint64_t SH_FLD_ADDR3 = 1941; // 16 -const static uint64_t SH_FLD_ADDR3_LEN = 1942; // 16 -const static uint64_t SH_FLD_ADDR4 = 1943; // 16 -const static uint64_t SH_FLD_ADDR4_LEN = 1944; // 16 -const static uint64_t SH_FLD_ADDRESS = 1945; // 131 -const static uint64_t SH_FLD_ADDRESS_8_63 = 1946; // 1 -const static uint64_t SH_FLD_ADDRESS_8_63_LEN = 1947; // 1 -const static uint64_t SH_FLD_ADDRESS_LEN = 1948; // 130 -const static uint64_t SH_FLD_ADDRESS_PARITY = 1949; // 43 -const static uint64_t SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT = 1950; // 2 -const static uint64_t SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT_LEN = 1951; // 2 -const static uint64_t SH_FLD_ADDR_21_37 = 1952; // 1 -const static uint64_t SH_FLD_ADDR_21_37_LEN = 1953; // 1 -const static uint64_t SH_FLD_ADDR_26_38 = 1954; // 1 -const static uint64_t SH_FLD_ADDR_26_38_LEN = 1955; // 1 -const static uint64_t SH_FLD_ADDR_8_37 = 1956; // 1 -const static uint64_t SH_FLD_ADDR_8_37_LEN = 1957; // 1 -const static uint64_t SH_FLD_ADDR_8_38 = 1958; // 1 -const static uint64_t SH_FLD_ADDR_8_38_LEN = 1959; // 1 -const static uint64_t SH_FLD_ADDR_8_48 = 1960; // 1 -const static uint64_t SH_FLD_ADDR_8_48_LEN = 1961; // 1 -const static uint64_t SH_FLD_ADDR_8_49 = 1962; // 2 -const static uint64_t SH_FLD_ADDR_8_49_LEN = 1963; // 2 -const static uint64_t SH_FLD_ADDR_BAR = 1964; // 1 -const static uint64_t SH_FLD_ADDR_BAR_MODE = 1965; // 2 -const static uint64_t SH_FLD_ADDR_BUFFER = 1966; // 43 -const static uint64_t SH_FLD_ADDR_ERROR = 1967; // 2 -const static uint64_t SH_FLD_ADDR_ERROR_PULSE = 1968; // 2 -const static uint64_t SH_FLD_ADDR_INVALID_FACES = 1969; // 1 -const static uint64_t SH_FLD_ADDR_INVALID_PIB = 1970; // 1 -const static uint64_t SH_FLD_ADDR_LEN = 1971; // 38 -const static uint64_t SH_FLD_ADDR_MIRROR_A11_A13 = 1972; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_A3_A4 = 1973; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_A5_A6 = 1974; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_A7_A8 = 1975; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_BA0_BA1 = 1976; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_BG0_BG1 = 1977; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP0_PRI = 1978; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP0_QUA = 1979; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP0_SEC = 1980; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP0_TER = 1981; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP1_PRI = 1982; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP1_QUA = 1983; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP1_SEC = 1984; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP1_TER = 1985; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP2_PRI = 1986; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP2_QUA = 1987; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP2_SEC = 1988; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP2_TER = 1989; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP3_PRI = 1990; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP3_QUA = 1991; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP3_SEC = 1992; // 8 -const static uint64_t SH_FLD_ADDR_MIRROR_RP3_TER = 1993; // 8 -const static uint64_t SH_FLD_ADDR_NVLD = 1994; // 1 -const static uint64_t SH_FLD_ADDR_PARITY_ERR = 1995; // 4 -const static uint64_t SH_FLD_ADDR_RESET_INTR_FACES = 1996; // 1 -const static uint64_t SH_FLD_ADDR_RESET_INTR_FACES_LEN = 1997; // 1 -const static uint64_t SH_FLD_ADDR_RESET_INTR_PIB = 1998; // 1 -const static uint64_t SH_FLD_ADDR_RESET_INTR_PIB_LEN = 1999; // 1 -const static uint64_t SH_FLD_ADDR_TAG = 2000; // 1 -const static uint64_t SH_FLD_ADDR_TAG_LEN = 2001; // 1 -const static uint64_t SH_FLD_ADR = 2002; // 4 -const static uint64_t SH_FLD_ADR0_ANALOG_WRAPON = 2003; // 8 -const static uint64_t SH_FLD_ADR0_ATESTSEL_0_2 = 2004; // 8 -const static uint64_t SH_FLD_ADR0_ATESTSEL_0_2_LEN = 2005; // 8 -const static uint64_t SH_FLD_ADR0_ATEST_SEL_0 = 2006; // 8 -const static uint64_t SH_FLD_ADR0_ATEST_SEL_0_LEN = 2007; // 8 -const static uint64_t SH_FLD_ADR0_BB_LOCK = 2008; // 8 -const static uint64_t SH_FLD_ADR0_CAL_ERROR = 2009; // 8 -const static uint64_t SH_FLD_ADR0_CAL_ERROR_FINE = 2010; // 8 -const static uint64_t SH_FLD_ADR0_CAL_GOOD = 2011; // 8 -const static uint64_t SH_FLD_ADR0_CONTINUOUS_UPDATE = 2012; // 8 -const static uint64_t SH_FLD_ADR0_EN = 2013; // 8 -const static uint64_t SH_FLD_ADR0_ENABLE = 2014; // 8 -const static uint64_t SH_FLD_ADR0_EN_DRIVER_INVFB_DC = 2015; // 8 -const static uint64_t SH_FLD_ADR0_FLUSH = 2016; // 8 -const static uint64_t SH_FLD_ADR0_FRZSULV = 2017; // 8 -const static uint64_t SH_FLD_ADR0_HS_DLLMUX_SEL_0_3 = 2018; // 8 -const static uint64_t SH_FLD_ADR0_HS_DLLMUX_SEL_0_3_LEN = 2019; // 8 -const static uint64_t SH_FLD_ADR0_HS_PROBE_A_SEL_0_3 = 2020; // 8 -const static uint64_t SH_FLD_ADR0_HS_PROBE_A_SEL_0_3_LEN = 2021; // 8 -const static uint64_t SH_FLD_ADR0_HS_PROBE_B_SEL_0_3 = 2022; // 8 -const static uint64_t SH_FLD_ADR0_HS_PROBE_B_SEL_0_3_LEN = 2023; // 8 -const static uint64_t SH_FLD_ADR0_INIT_IO = 2024; // 8 -const static uint64_t SH_FLD_ADR0_INIT_RXDLL_CAL_RESET = 2025; // 8 -const static uint64_t SH_FLD_ADR0_INIT_RXDLL_CAL_UPDATE = 2026; // 8 -const static uint64_t SH_FLD_ADR0_INTERP_SIG_SLEW_0_3 = 2027; // 8 -const static uint64_t SH_FLD_ADR0_INTERP_SIG_SLEW_0_3_LEN = 2028; // 8 -const static uint64_t SH_FLD_ADR0_OVERRIDE = 2029; // 8 -const static uint64_t SH_FLD_ADR0_OVERRIDE_EN = 2030; // 8 -const static uint64_t SH_FLD_ADR0_OVERRIDE_LEN = 2031; // 8 -const static uint64_t SH_FLD_ADR0_PHASE_ALIGN_RESET = 2032; // 8 -const static uint64_t SH_FLD_ADR0_PHASE_DEFAULT_EN = 2033; // 8 -const static uint64_t SH_FLD_ADR0_PHASE_EN = 2034; // 8 -const static uint64_t SH_FLD_ADR0_POS_EDGE_ALIGN = 2035; // 8 -const static uint64_t SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP = 2036; // 8 -const static uint64_t SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP_LEN = 2037; // 8 -const static uint64_t SH_FLD_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 = 2038; // 8 -const static uint64_t SH_FLD_ADR0_REGS_RXDLL_DAC = 2039; // 8 -const static uint64_t SH_FLD_ADR0_REGS_RXDLL_DAC_LEN = 2040; // 8 -const static uint64_t SH_FLD_ADR0_REGS_RXDLL_EN = 2041; // 8 -const static uint64_t SH_FLD_ADR0_REGS_RXDLL_EN_LEN = 2042; // 8 -const static uint64_t SH_FLD_ADR0_REGS_RXDLL_VREG = 2043; // 16 -const static uint64_t SH_FLD_ADR0_REGS_RXDLL_VREG_LEN = 2044; // 16 -const static uint64_t SH_FLD_ADR0_RESERVED_60_63 = 2045; // 8 -const static uint64_t SH_FLD_ADR0_RESERVED_60_63_LEN = 2046; // 8 -const static uint64_t SH_FLD_ADR0_ROT = 2047; // 8 -const static uint64_t SH_FLD_ADR0_ROT_LEN = 2048; // 8 -const static uint64_t SH_FLD_ADR0_ROT_OVERRIDE = 2049; // 8 -const static uint64_t SH_FLD_ADR0_ROT_OVERRIDE_EN = 2050; // 8 -const static uint64_t SH_FLD_ADR0_ROT_OVERRIDE_LEN = 2051; // 8 -const static uint64_t SH_FLD_ADR0_RXREG_COMPCON_DC = 2052; // 8 -const static uint64_t SH_FLD_ADR0_RXREG_COMPCON_DC_LEN = 2053; // 8 -const static uint64_t SH_FLD_ADR0_RXREG_CON_DC = 2054; // 8 -const static uint64_t SH_FLD_ADR0_RXREG_DAC_PULLUP_DC = 2055; // 8 -const static uint64_t SH_FLD_ADR0_RXREG_DRVCON_DC = 2056; // 8 -const static uint64_t SH_FLD_ADR0_RXREG_DRVCON_DC_LEN = 2057; // 8 -const static uint64_t SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC = 2058; // 8 -const static uint64_t SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC_LEN = 2059; // 8 -const static uint64_t SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC = 2060; // 8 -const static uint64_t SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2061; // 8 -const static uint64_t SH_FLD_ADR0_RXREG_REF_SEL_DC = 2062; // 8 -const static uint64_t SH_FLD_ADR0_RXREG_REF_SEL_DC_LEN = 2063; // 8 -const static uint64_t SH_FLD_ADR0_SLEW_DONE_STATUS = 2064; // 8 -const static uint64_t SH_FLD_ADR0_SLEW_DONE_STATUS_LEN = 2065; // 8 -const static uint64_t SH_FLD_ADR0_START = 2066; // 8 -const static uint64_t SH_FLD_ADR0_TARGET_PR_OFFSET = 2067; // 8 -const static uint64_t SH_FLD_ADR0_TARGET_PR_OFFSET_LEN = 2068; // 8 -const static uint64_t SH_FLD_ADR0_TSYS = 2069; // 8 -const static uint64_t SH_FLD_ADR0_TSYS_LEN = 2070; // 8 -const static uint64_t SH_FLD_ADR0_VALUE = 2071; // 16 -const static uint64_t SH_FLD_ADR0_VALUE_LEN = 2072; // 16 -const static uint64_t SH_FLD_ADR1_ANALOG_WRAPON = 2073; // 8 -const static uint64_t SH_FLD_ADR1_ATESTSEL_0_2 = 2074; // 8 -const static uint64_t SH_FLD_ADR1_ATESTSEL_0_2_LEN = 2075; // 8 -const static uint64_t SH_FLD_ADR1_ATEST_SEL_0 = 2076; // 8 -const static uint64_t SH_FLD_ADR1_ATEST_SEL_0_LEN = 2077; // 8 -const static uint64_t SH_FLD_ADR1_BB_LOCK = 2078; // 8 -const static uint64_t SH_FLD_ADR1_CAL_ERROR = 2079; // 8 -const static uint64_t SH_FLD_ADR1_CAL_ERROR_FINE = 2080; // 8 -const static uint64_t SH_FLD_ADR1_CAL_GOOD = 2081; // 8 -const static uint64_t SH_FLD_ADR1_CONTINUOUS_UPDATE = 2082; // 8 -const static uint64_t SH_FLD_ADR1_EN = 2083; // 8 -const static uint64_t SH_FLD_ADR1_ENABLE = 2084; // 8 -const static uint64_t SH_FLD_ADR1_EN_DRIVER_INVFB_DC = 2085; // 8 -const static uint64_t SH_FLD_ADR1_FLUSH = 2086; // 8 -const static uint64_t SH_FLD_ADR1_FRZSULV = 2087; // 8 -const static uint64_t SH_FLD_ADR1_HS_DLLMUX_SEL_0_3 = 2088; // 8 -const static uint64_t SH_FLD_ADR1_HS_DLLMUX_SEL_0_3_LEN = 2089; // 8 -const static uint64_t SH_FLD_ADR1_HS_PROBE_A_SEL_0_3 = 2090; // 8 -const static uint64_t SH_FLD_ADR1_HS_PROBE_A_SEL_0_3_LEN = 2091; // 8 -const static uint64_t SH_FLD_ADR1_HS_PROBE_B_SEL_0_3 = 2092; // 8 -const static uint64_t SH_FLD_ADR1_HS_PROBE_B_SEL_0_3_LEN = 2093; // 8 -const static uint64_t SH_FLD_ADR1_INIT_IO = 2094; // 8 -const static uint64_t SH_FLD_ADR1_INIT_RXDLL_CAL_RESET = 2095; // 8 -const static uint64_t SH_FLD_ADR1_INIT_RXDLL_CAL_UPDATE = 2096; // 8 -const static uint64_t SH_FLD_ADR1_INTERP_SIG_SLEW_0_3 = 2097; // 8 -const static uint64_t SH_FLD_ADR1_INTERP_SIG_SLEW_0_3_LEN = 2098; // 8 -const static uint64_t SH_FLD_ADR1_OVERRIDE = 2099; // 8 -const static uint64_t SH_FLD_ADR1_OVERRIDE_EN = 2100; // 8 -const static uint64_t SH_FLD_ADR1_OVERRIDE_LEN = 2101; // 8 -const static uint64_t SH_FLD_ADR1_PHASE_ALIGN_RESET = 2102; // 8 -const static uint64_t SH_FLD_ADR1_PHASE_DEFAULT_EN = 2103; // 8 -const static uint64_t SH_FLD_ADR1_PHASE_EN = 2104; // 8 -const static uint64_t SH_FLD_ADR1_POS_EDGE_ALIGN = 2105; // 8 -const static uint64_t SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP = 2106; // 8 -const static uint64_t SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP_LEN = 2107; // 8 -const static uint64_t SH_FLD_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 = 2108; // 8 -const static uint64_t SH_FLD_ADR1_REGS_RXDLL_DAC = 2109; // 8 -const static uint64_t SH_FLD_ADR1_REGS_RXDLL_DAC_LEN = 2110; // 8 -const static uint64_t SH_FLD_ADR1_REGS_RXDLL_EN = 2111; // 8 -const static uint64_t SH_FLD_ADR1_REGS_RXDLL_EN_LEN = 2112; // 8 -const static uint64_t SH_FLD_ADR1_REGS_RXDLL_VREG = 2113; // 16 -const static uint64_t SH_FLD_ADR1_REGS_RXDLL_VREG_LEN = 2114; // 16 -const static uint64_t SH_FLD_ADR1_RESERVED_60_63 = 2115; // 8 -const static uint64_t SH_FLD_ADR1_RESERVED_60_63_LEN = 2116; // 8 -const static uint64_t SH_FLD_ADR1_ROT = 2117; // 8 -const static uint64_t SH_FLD_ADR1_ROT_LEN = 2118; // 8 -const static uint64_t SH_FLD_ADR1_ROT_OVERRIDE = 2119; // 8 -const static uint64_t SH_FLD_ADR1_ROT_OVERRIDE_EN = 2120; // 8 -const static uint64_t SH_FLD_ADR1_ROT_OVERRIDE_LEN = 2121; // 8 -const static uint64_t SH_FLD_ADR1_RXREG_COMPCON_DC = 2122; // 8 -const static uint64_t SH_FLD_ADR1_RXREG_COMPCON_DC_LEN = 2123; // 8 -const static uint64_t SH_FLD_ADR1_RXREG_CON_DC = 2124; // 8 -const static uint64_t SH_FLD_ADR1_RXREG_DAC_PULLUP_DC = 2125; // 8 -const static uint64_t SH_FLD_ADR1_RXREG_DRVCON_DC = 2126; // 8 -const static uint64_t SH_FLD_ADR1_RXREG_DRVCON_DC_LEN = 2127; // 8 -const static uint64_t SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC = 2128; // 8 -const static uint64_t SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC_LEN = 2129; // 8 -const static uint64_t SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC = 2130; // 8 -const static uint64_t SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2131; // 8 -const static uint64_t SH_FLD_ADR1_RXREG_REF_SEL_DC = 2132; // 8 -const static uint64_t SH_FLD_ADR1_RXREG_REF_SEL_DC_LEN = 2133; // 8 -const static uint64_t SH_FLD_ADR1_SLEW_DONE_STATUS = 2134; // 8 -const static uint64_t SH_FLD_ADR1_SLEW_DONE_STATUS_LEN = 2135; // 8 -const static uint64_t SH_FLD_ADR1_START = 2136; // 8 -const static uint64_t SH_FLD_ADR1_TARGET_PR_OFFSET = 2137; // 8 -const static uint64_t SH_FLD_ADR1_TARGET_PR_OFFSET_LEN = 2138; // 8 -const static uint64_t SH_FLD_ADR1_TSYS = 2139; // 8 -const static uint64_t SH_FLD_ADR1_TSYS_LEN = 2140; // 8 -const static uint64_t SH_FLD_ADR1_VALUE = 2141; // 16 -const static uint64_t SH_FLD_ADR1_VALUE_LEN = 2142; // 16 -const static uint64_t SH_FLD_ADR_LEN = 2143; // 4 -const static uint64_t SH_FLD_ADR_SLAVE_SEL = 2144; // 8 -const static uint64_t SH_FLD_ADS_HANG = 2145; // 1 -const static uint64_t SH_FLD_ADU_MALF_ALERT = 2146; // 1 -const static uint64_t SH_FLD_ADVANCE_RD_VALID = 2147; // 8 -const static uint64_t SH_FLD_AESSHA_LATENCY_CFG = 2148; // 1 -const static uint64_t SH_FLD_AES_LATENCY_CFG = 2149; // 1 -const static uint64_t SH_FLD_AIB_FENCE = 2150; // 9 -const static uint64_t SH_FLD_AIB_FENCE_MASK = 2151; // 9 -const static uint64_t SH_FLD_AIB_PE = 2152; // 9 -const static uint64_t SH_FLD_AIB_PE_MASK = 2153; // 9 -const static uint64_t SH_FLD_ALIGN_ON_EVEN_CYCLES = 2154; // 8 -const static uint64_t SH_FLD_ALINK_NOTPHB_MODE = 2155; // 2 -const static uint64_t SH_FLD_ALLOW_CRYPTO = 2156; // 1 -const static uint64_t SH_FLD_ALLOW_RD_FIFO_AUTO_RESET = 2157; // 8 -const static uint64_t SH_FLD_ALLOW_REG_WAKEUP_C0 = 2158; // 12 -const static uint64_t SH_FLD_ALLOW_REG_WAKEUP_C1 = 2159; // 12 -const static uint64_t SH_FLD_ALTD_DATA_ITAG = 2160; // 1 -const static uint64_t SH_FLD_ALTD_DATA_TX = 2161; // 1 -const static uint64_t SH_FLD_ALTD_DATA_TX_LEN = 2162; // 1 -const static uint64_t SH_FLD_ALTD_DATA_TX_OVERWRITE = 2163; // 1 -const static uint64_t SH_FLD_ALT_SEGSZ_DIS = 2164; // 1 -const static uint64_t SH_FLD_ALU_FLIP_ENDIAN_BIG = 2165; // 3 -const static uint64_t SH_FLD_ALU_FLIP_ENDIAN_LITTLE = 2166; // 3 -const static uint64_t SH_FLD_ALU_SAFE_LATENCY = 2167; // 3 -const static uint64_t SH_FLD_ALWAYS_RTY = 2168; // 8 -const static uint64_t SH_FLD_AMAX_HIGH = 2169; // 6 -const static uint64_t SH_FLD_AMAX_HIGH_LEN = 2170; // 6 -const static uint64_t SH_FLD_AMAX_LOW = 2171; // 6 -const static uint64_t SH_FLD_AMAX_LOW_LEN = 2172; // 6 -const static uint64_t SH_FLD_AMIN_CFG = 2173; // 6 -const static uint64_t SH_FLD_AMIN_CFG_LEN = 2174; // 6 -const static uint64_t SH_FLD_AMIN_TIMEOUT = 2175; // 6 -const static uint64_t SH_FLD_AMIN_TIMEOUT_LEN = 2176; // 6 -const static uint64_t SH_FLD_AMO_DRAM_SIZE_128B = 2177; // 8 -const static uint64_t SH_FLD_AMO_LIMIT = 2178; // 8 -const static uint64_t SH_FLD_AMO_LIMIT_LEN = 2179; // 8 -const static uint64_t SH_FLD_AMP0_FILTER_MASK = 2180; // 6 -const static uint64_t SH_FLD_AMP0_FILTER_MASK_LEN = 2181; // 6 -const static uint64_t SH_FLD_AMP1_FILTER_MASK = 2182; // 6 -const static uint64_t SH_FLD_AMP1_FILTER_MASK_LEN = 2183; // 6 -const static uint64_t SH_FLD_AMP_CFG = 2184; // 6 -const static uint64_t SH_FLD_AMP_CFG_LEN = 2185; // 6 -const static uint64_t SH_FLD_AMP_GAIN_CNT_MAX = 2186; // 6 -const static uint64_t SH_FLD_AMP_GAIN_CNT_MAX_LEN = 2187; // 6 -const static uint64_t SH_FLD_AMP_INIT_CFG = 2188; // 6 -const static uint64_t SH_FLD_AMP_INIT_CFG_LEN = 2189; // 6 -const static uint64_t SH_FLD_AMP_INIT_TIMEOUT = 2190; // 6 -const static uint64_t SH_FLD_AMP_INIT_TIMEOUT_LEN = 2191; // 6 -const static uint64_t SH_FLD_AMP_RECAL_CFG = 2192; // 6 -const static uint64_t SH_FLD_AMP_RECAL_CFG_LEN = 2193; // 6 -const static uint64_t SH_FLD_AMP_RECAL_TIMEOUT = 2194; // 6 -const static uint64_t SH_FLD_AMP_RECAL_TIMEOUT_LEN = 2195; // 6 -const static uint64_t SH_FLD_AMP_START_VAL = 2196; // 6 -const static uint64_t SH_FLD_AMP_START_VAL_LEN = 2197; // 6 -const static uint64_t SH_FLD_AMP_TIMEOUT = 2198; // 6 -const static uint64_t SH_FLD_AMP_TIMEOUT_LEN = 2199; // 6 -const static uint64_t SH_FLD_AMP_VAL = 2200; // 120 -const static uint64_t SH_FLD_AMP_VAL_LEN = 2201; // 120 -const static uint64_t SH_FLD_ANALOGTUNE = 2202; // 20 -const static uint64_t SH_FLD_ANALOGTUNE_LEN = 2203; // 20 -const static uint64_t SH_FLD_ANALOG_INPUT_STAB1 = 2204; // 8 -const static uint64_t SH_FLD_ANALOG_OUTPUT_STAB = 2205; // 8 -const static uint64_t SH_FLD_ANY_ERROR = 2206; // 1 -const static uint64_t SH_FLD_ANY_REQ_ACTIVE = 2207; // 12 -const static uint64_t SH_FLD_AP = 2208; // 8 -const static uint64_t SH_FLD_AP110_AP010_DELTA_MAX = 2209; // 6 -const static uint64_t SH_FLD_AP110_AP010_DELTA_MAX_LEN = 2210; // 6 -const static uint64_t SH_FLD_APB = 2211; // 8 -const static uint64_t SH_FLD_APB_MASK = 2212; // 8 -const static uint64_t SH_FLD_APCARY = 2213; // 4 -const static uint64_t SH_FLD_APCARY_ADDRESS = 2214; // 2 -const static uint64_t SH_FLD_APCARY_ADDRESS_LEN = 2215; // 2 -const static uint64_t SH_FLD_APCARY_LEN = 2216; // 4 -const static uint64_t SH_FLD_APCCTL_ADR_BAR_MODE = 2217; // 2 -const static uint64_t SH_FLD_APCCTL_CFG_BKILL_INC = 2218; // 2 -const static uint64_t SH_FLD_APCCTL_DISABLE_G = 2219; // 2 -const static uint64_t SH_FLD_APCCTL_DISABLE_LN = 2220; // 2 -const static uint64_t SH_FLD_APCCTL_DISABLE_NN_RN = 2221; // 2 -const static uint64_t SH_FLD_APCCTL_DISABLE_PSL_CMDQUEUE = 2222; // 2 -const static uint64_t SH_FLD_APCCTL_DISABLE_VG_NOT_SYS = 2223; // 2 -const static uint64_t SH_FLD_APCCTL_ENABLE_MASTER_RETRY_BACKOFF = 2224; // 2 -const static uint64_t SH_FLD_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT = 2225; // 2 -const static uint64_t SH_FLD_APCCTL_ENB_CRESP_EXAM = 2226; // 2 -const static uint64_t SH_FLD_APCCTL_ENB_FRC_ADDR13 = 2227; // 2 -const static uint64_t SH_FLD_APCCTL_HANG_ARE = 2228; // 2 -const static uint64_t SH_FLD_APCCTL_HANG_DEAD = 2229; // 2 -const static uint64_t SH_FLD_APCCTL_MAX_RETRY = 2230; // 2 -const static uint64_t SH_FLD_APCCTL_MAX_RETRY_LEN = 2231; // 2 -const static uint64_t SH_FLD_APCCTL_MEM_SEL_MODE = 2232; // 2 -const static uint64_t SH_FLD_APCCTL_P9_MODE = 2233; // 2 -const static uint64_t SH_FLD_APCCTL_PHB_SEL = 2234; // 2 -const static uint64_t SH_FLD_APCCTL_PHB_SEL_LEN = 2235; // 2 -const static uint64_t SH_FLD_APCCTL_SKIP_G = 2236; // 2 -const static uint64_t SH_FLD_APCCTL_SYSADDR = 2237; // 2 -const static uint64_t SH_FLD_APCCTL_SYSADDR_LEN = 2238; // 2 -const static uint64_t SH_FLD_APC_ARRAY_CMD_CE_ERPT = 2239; // 4 -const static uint64_t SH_FLD_APC_ARRAY_CMD_UE_ERPT = 2240; // 4 -const static uint64_t SH_FLD_APX111_HIGH = 2241; // 6 -const static uint64_t SH_FLD_APX111_HIGH_LEN = 2242; // 6 -const static uint64_t SH_FLD_APX111_LOW = 2243; // 6 -const static uint64_t SH_FLD_APX111_LOW_LEN = 2244; // 6 -const static uint64_t SH_FLD_AP_LEN = 2245; // 8 -const static uint64_t SH_FLD_ARBITRATION_LOST_ERROR_0 = 2246; // 2 -const static uint64_t SH_FLD_ARBITRATION_LOST_ERROR_1 = 2247; // 2 -const static uint64_t SH_FLD_ARBITRATION_LOST_ERROR_2 = 2248; // 2 -const static uint64_t SH_FLD_ARBITRATION_LOST_ERROR_3 = 2249; // 2 -const static uint64_t SH_FLD_ARB_EN_SEND_ALL_WRITES = 2250; // 1 -const static uint64_t SH_FLD_ARB_STALL = 2251; // 1 -const static uint64_t SH_FLD_ARB_STOP = 2252; // 1 -const static uint64_t SH_FLD_ARRAY_ADDR = 2253; // 6 -const static uint64_t SH_FLD_ARRAY_ADDR_LEN = 2254; // 6 -const static uint64_t SH_FLD_ARRAY_POINTER_SELECT = 2255; // 6 -const static uint64_t SH_FLD_ARRAY_POINTER_SELECT_LEN = 2256; // 6 -const static uint64_t SH_FLD_ARRAY_SELECT = 2257; // 1 -const static uint64_t SH_FLD_ARRAY_SELECT_LEN = 2258; // 1 -const static uint64_t SH_FLD_ARRAY_WRITE_ASSIST_EN = 2259; // 43 -const static uint64_t SH_FLD_ARY_ECC_CE = 2260; // 9 -const static uint64_t SH_FLD_ARY_ECC_CE_MASK = 2261; // 9 -const static uint64_t SH_FLD_ARY_ECC_SUE = 2262; // 9 -const static uint64_t SH_FLD_ARY_ECC_SUE_MASK = 2263; // 9 -const static uint64_t SH_FLD_ARY_ECC_UE = 2264; // 9 -const static uint64_t SH_FLD_ARY_ECC_UE_MASK = 2265; // 9 -const static uint64_t SH_FLD_ASSN_DONE = 2266; // 1 -const static uint64_t SH_FLD_ASYNC_IF_ERROR = 2267; // 16 -const static uint64_t SH_FLD_ASYNC_INJ = 2268; // 16 -const static uint64_t SH_FLD_ASYNC_INJ_LEN = 2269; // 16 -const static uint64_t SH_FLD_ASYNC_MODE = 2270; // 6 -const static uint64_t SH_FLD_AS_INTERRUPT_ENABLE = 2271; // 2 -const static uint64_t SH_FLD_ATAG_0_15 = 2272; // 1 -const static uint64_t SH_FLD_ATAG_0_15_LEN = 2273; // 1 -const static uint64_t SH_FLD_ATOMIC_ALT_CE_INJ = 2274; // 2 -const static uint64_t SH_FLD_ATOMIC_ALT_CHIP_KILL_INJ = 2275; // 2 -const static uint64_t SH_FLD_ATOMIC_ALT_INJ_SYM_SEL = 2276; // 2 -const static uint64_t SH_FLD_ATOMIC_ALT_INJ_SYM_SEL_LEN = 2277; // 2 -const static uint64_t SH_FLD_ATOMIC_ALT_SUE_INJ = 2278; // 2 -const static uint64_t SH_FLD_ATOMIC_ALT_UE_INJ = 2279; // 2 -const static uint64_t SH_FLD_ATSTSEL = 2280; // 17 -const static uint64_t SH_FLD_ATSTSEL_LEN = 2281; // 17 -const static uint64_t SH_FLD_ATS_AT_EA_CE = 2282; // 1 -const static uint64_t SH_FLD_ATS_AT_EA_UE = 2283; // 1 -const static uint64_t SH_FLD_ATS_AT_RSPOUT_CE = 2284; // 1 -const static uint64_t SH_FLD_ATS_AT_RSPOUT_UE = 2285; // 1 -const static uint64_t SH_FLD_ATS_AT_TDRMEM_CE = 2286; // 1 -const static uint64_t SH_FLD_ATS_AT_TDRMEM_UE = 2287; // 1 -const static uint64_t SH_FLD_ATS_INVAL_IODA_TBL_SEL = 2288; // 1 -const static uint64_t SH_FLD_ATS_IODA_ADDR_PERR = 2289; // 1 -const static uint64_t SH_FLD_ATS_NPU_CTRL_PERR = 2290; // 1 -const static uint64_t SH_FLD_ATS_NPU_TOR_PERR = 2291; // 1 -const static uint64_t SH_FLD_ATS_RSPOUT_ADDR_ERR = 2292; // 1 -const static uint64_t SH_FLD_ATS_TCD_PERR = 2293; // 1 -const static uint64_t SH_FLD_ATS_TCE_CACHE_MULT_HIT_ERR = 2294; // 1 -const static uint64_t SH_FLD_ATS_TCE_PAGE_ACCESS_CA_ERR = 2295; // 1 -const static uint64_t SH_FLD_ATS_TCE_PAGE_ACCESS_TW_ERR = 2296; // 1 -const static uint64_t SH_FLD_ATS_TCE_REQ_TO_ERR = 2297; // 1 -const static uint64_t SH_FLD_ATS_TDR_PERR = 2298; // 1 -const static uint64_t SH_FLD_ATS_TVT_ADDR_RANGE_ERR = 2299; // 1 -const static uint64_t SH_FLD_ATS_TVT_ENTRY_INVALID = 2300; // 1 -const static uint64_t SH_FLD_ATS_TVT_PERR = 2301; // 1 -const static uint64_t SH_FLD_ATTENTION = 2302; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP = 2303; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP_LEN = 2304; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_EQD_DMA = 2305; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_EQD_DMA_LEN = 2306; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_IRQ = 2307; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_IRQ_LEN = 2308; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_IVC = 2309; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_IVC_LEN = 2310; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD = 2311; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD_LEN = 2312; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_REGS = 2313; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_REGS_LEN = 2314; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_SBC_DMA = 2315; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_SBC_DMA_LEN = 2316; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP = 2317; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP_LEN = 2318; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_TRIG_FWD = 2319; // 1 -const static uint64_t SH_FLD_ATX_PRIO_FOR_TRIG_FWD_LEN = 2320; // 1 -const static uint64_t SH_FLD_AT_EA_CE_ESR = 2321; // 1 -const static uint64_t SH_FLD_AT_EA_UE_ESR = 2322; // 1 -const static uint64_t SH_FLD_AT_TDRMEM_CE_ESR = 2323; // 1 -const static uint64_t SH_FLD_AT_TDRMEM_UE_ESR = 2324; // 1 -const static uint64_t SH_FLD_AUE = 2325; // 2 -const static uint64_t SH_FLD_AUE_LEN = 2326; // 2 -const static uint64_t SH_FLD_AUTOINC = 2327; // 12 -const static uint64_t SH_FLD_AUTO_INC = 2328; // 7 -const static uint64_t SH_FLD_AUTO_INCREMENT = 2329; // 3 -const static uint64_t SH_FLD_AUTO_INC_TRIG = 2330; // 6 -const static uint64_t SH_FLD_AUTO_INC_TRIG_LEN = 2331; // 6 -const static uint64_t SH_FLD_AUTO_POST_DECREMENT_FACES = 2332; // 1 -const static uint64_t SH_FLD_AUTO_POST_DECREMENT_PIB = 2333; // 1 -const static uint64_t SH_FLD_AUTO_PRE_INCREMENT_FACES = 2334; // 1 -const static uint64_t SH_FLD_AUTO_PRE_INCREMENT_PIB = 2335; // 1 -const static uint64_t SH_FLD_AUTO_RELOAD_N = 2336; // 2 -const static uint64_t SH_FLD_AUTO_STOP1_DISABLE = 2337; // 12 -const static uint64_t SH_FLD_AVA = 2338; // 8 -const static uint64_t SH_FLD_AVAIL_GROUPS = 2339; // 2 -const static uint64_t SH_FLD_AVAIL_GROUPS_LEN = 2340; // 2 -const static uint64_t SH_FLD_AVA_LEN = 2341; // 8 -const static uint64_t SH_FLD_AVG_CYCLE_SAMPLE = 2342; // 12 -const static uint64_t SH_FLD_AVG_CYCLE_SAMPLE_LEN = 2343; // 12 -const static uint64_t SH_FLD_AVG_FREQ_TSEL = 2344; // 12 -const static uint64_t SH_FLD_AVG_FREQ_TSEL_LEN = 2345; // 12 -const static uint64_t SH_FLD_AVS_SLAVE0 = 2346; // 1 -const static uint64_t SH_FLD_AVS_SLAVE1 = 2347; // 1 -const static uint64_t SH_FLD_AXFLOW_ERR = 2348; // 1 -const static uint64_t SH_FLD_AXFLOW_ERR_MASK = 2349; // 1 -const static uint64_t SH_FLD_AXPUSH_WRERR = 2350; // 1 -const static uint64_t SH_FLD_AXPUSH_WRERR_MASK = 2351; // 1 -const static uint64_t SH_FLD_AXRCV_DLO_ERR = 2352; // 1 -const static uint64_t SH_FLD_AXRCV_DLO_ERR_MASK = 2353; // 1 -const static uint64_t SH_FLD_AXRCV_DLO_TO = 2354; // 1 -const static uint64_t SH_FLD_AXRCV_DLO_TO_MASK = 2355; // 1 -const static uint64_t SH_FLD_AXRCV_RSVDATA_TO = 2356; // 1 -const static uint64_t SH_FLD_AXRCV_RSVDATA_TO_MASK = 2357; // 1 -const static uint64_t SH_FLD_AXSND_DHI_RTYTO = 2358; // 1 -const static uint64_t SH_FLD_AXSND_DHI_RTYTO_MASK = 2359; // 1 -const static uint64_t SH_FLD_AXSND_DLO_RTYTO = 2360; // 1 -const static uint64_t SH_FLD_AXSND_DLO_RTYTO_MASK = 2361; // 1 -const static uint64_t SH_FLD_AXSND_RSVERR = 2362; // 1 -const static uint64_t SH_FLD_AXSND_RSVERR_MASK = 2363; // 1 -const static uint64_t SH_FLD_AXSND_RSVTO = 2364; // 1 -const static uint64_t SH_FLD_AXSND_RSVTO_MASK = 2365; // 1 -const static uint64_t SH_FLD_A_AP = 2366; // 144 -const static uint64_t SH_FLD_A_AP_LEN = 2367; // 144 -const static uint64_t SH_FLD_A_BAD_DFE_CONV = 2368; // 144 -const static uint64_t SH_FLD_A_BANK_CONTROLS = 2369; // 120 -const static uint64_t SH_FLD_A_BANK_CONTROLS_LEN = 2370; // 120 -const static uint64_t SH_FLD_A_BIST_EN = 2371; // 6 -const static uint64_t SH_FLD_A_CONTROLS = 2372; // 120 -const static uint64_t SH_FLD_A_CONTROLS_LEN = 2373; // 120 -const static uint64_t SH_FLD_A_CTLE_COARSE = 2374; // 48 -const static uint64_t SH_FLD_A_CTLE_COARSE_LEN = 2375; // 48 -const static uint64_t SH_FLD_A_CTLE_GAIN = 2376; // 120 -const static uint64_t SH_FLD_A_CTLE_GAIN_LEN = 2377; // 120 -const static uint64_t SH_FLD_A_CTLE_PEAK = 2378; // 72 -const static uint64_t SH_FLD_A_CTLE_PEAK_LEN = 2379; // 72 -const static uint64_t SH_FLD_A_EVEN_INTEG_FINE_GAIN = 2380; // 120 -const static uint64_t SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN = 2381; // 120 -const static uint64_t SH_FLD_A_H10_VAL = 2382; // 72 -const static uint64_t SH_FLD_A_H10_VAL_LEN = 2383; // 72 -const static uint64_t SH_FLD_A_H11_VAL = 2384; // 72 -const static uint64_t SH_FLD_A_H11_VAL_LEN = 2385; // 72 -const static uint64_t SH_FLD_A_H12_VAL = 2386; // 72 -const static uint64_t SH_FLD_A_H12_VAL_LEN = 2387; // 72 -const static uint64_t SH_FLD_A_H1AP_AT_LIMIT = 2388; // 144 -const static uint64_t SH_FLD_A_H1ARATIO_VAL = 2389; // 72 -const static uint64_t SH_FLD_A_H1ARATIO_VAL_LEN = 2390; // 72 -const static uint64_t SH_FLD_A_H1CAL_EN = 2391; // 72 -const static uint64_t SH_FLD_A_H1CAL_VAL = 2392; // 72 -const static uint64_t SH_FLD_A_H1CAL_VAL_LEN = 2393; // 72 -const static uint64_t SH_FLD_A_H1E_VAL = 2394; // 120 -const static uint64_t SH_FLD_A_H1E_VAL_LEN = 2395; // 120 -const static uint64_t SH_FLD_A_H1O_VAL = 2396; // 120 -const static uint64_t SH_FLD_A_H1O_VAL_LEN = 2397; // 120 -const static uint64_t SH_FLD_A_H2E_VAL = 2398; // 72 -const static uint64_t SH_FLD_A_H2E_VAL_LEN = 2399; // 72 -const static uint64_t SH_FLD_A_H2O_VAL = 2400; // 72 -const static uint64_t SH_FLD_A_H2O_VAL_LEN = 2401; // 72 -const static uint64_t SH_FLD_A_H3E_VAL = 2402; // 72 -const static uint64_t SH_FLD_A_H3E_VAL_LEN = 2403; // 72 -const static uint64_t SH_FLD_A_H3O_VAL = 2404; // 72 -const static uint64_t SH_FLD_A_H3O_VAL_LEN = 2405; // 72 -const static uint64_t SH_FLD_A_H4E_VAL = 2406; // 72 -const static uint64_t SH_FLD_A_H4E_VAL_LEN = 2407; // 72 -const static uint64_t SH_FLD_A_H4O_VAL = 2408; // 72 -const static uint64_t SH_FLD_A_H4O_VAL_LEN = 2409; // 72 -const static uint64_t SH_FLD_A_H5E_VAL = 2410; // 72 -const static uint64_t SH_FLD_A_H5E_VAL_LEN = 2411; // 72 -const static uint64_t SH_FLD_A_H5O_VAL = 2412; // 72 -const static uint64_t SH_FLD_A_H5O_VAL_LEN = 2413; // 72 -const static uint64_t SH_FLD_A_H6_VAL = 2414; // 72 -const static uint64_t SH_FLD_A_H6_VAL_LEN = 2415; // 72 -const static uint64_t SH_FLD_A_H7_VAL = 2416; // 72 -const static uint64_t SH_FLD_A_H7_VAL_LEN = 2417; // 72 -const static uint64_t SH_FLD_A_H8_VAL = 2418; // 72 -const static uint64_t SH_FLD_A_H8_VAL_LEN = 2419; // 72 -const static uint64_t SH_FLD_A_H9_VAL = 2420; // 72 -const static uint64_t SH_FLD_A_H9_VAL_LEN = 2421; // 72 -const static uint64_t SH_FLD_A_INTEG_COARSE_GAIN = 2422; // 120 -const static uint64_t SH_FLD_A_INTEG_COARSE_GAIN_LEN = 2423; // 120 -const static uint64_t SH_FLD_A_ODD_INTEG_FINE_GAIN = 2424; // 120 -const static uint64_t SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN = 2425; // 120 -const static uint64_t SH_FLD_A_OFFSET_E0 = 2426; // 120 -const static uint64_t SH_FLD_A_OFFSET_E0_LEN = 2427; // 120 -const static uint64_t SH_FLD_A_OFFSET_E1 = 2428; // 120 -const static uint64_t SH_FLD_A_OFFSET_E1_LEN = 2429; // 120 -const static uint64_t SH_FLD_A_OFFSET_O0 = 2430; // 120 -const static uint64_t SH_FLD_A_OFFSET_O0_LEN = 2431; // 120 -const static uint64_t SH_FLD_A_OFFSET_O1 = 2432; // 120 -const static uint64_t SH_FLD_A_OFFSET_O1_LEN = 2433; // 120 -const static uint64_t SH_FLD_A_PATH_OFF_EVEN = 2434; // 144 -const static uint64_t SH_FLD_A_PATH_OFF_EVEN_LEN = 2435; // 144 -const static uint64_t SH_FLD_A_PATH_OFF_ODD = 2436; // 144 -const static uint64_t SH_FLD_A_PATH_OFF_ODD_LEN = 2437; // 144 -const static uint64_t SH_FLD_A_PR_DFE_CLKADJ = 2438; // 120 -const static uint64_t SH_FLD_A_PR_DFE_CLKADJ_LEN = 2439; // 120 -const static uint64_t SH_FLD_B = 2440; // 8 -const static uint64_t SH_FLD_B0_63 = 2441; // 2 -const static uint64_t SH_FLD_B0_63_LEN = 2442; // 2 -const static uint64_t SH_FLD_B64_87 = 2443; // 2 -const static uint64_t SH_FLD_B64_87_LEN = 2444; // 2 -const static uint64_t SH_FLD_BACKUP_SEEPROM_SELECT = 2445; // 1 -const static uint64_t SH_FLD_BAD_ARRAY_ADDRESS_FACES = 2446; // 1 -const static uint64_t SH_FLD_BAD_ARRAY_ADDR_FACES = 2447; // 1 -const static uint64_t SH_FLD_BAD_ARRAY_ADDR_PIB = 2448; // 1 -const static uint64_t SH_FLD_BAD_BLOCK_LOCK = 2449; // 96 -const static uint64_t SH_FLD_BAD_BUS_LANE_ERR_CNTR_DIS_CLR = 2450; // 4 -const static uint64_t SH_FLD_BAD_DESKEW = 2451; // 96 -const static uint64_t SH_FLD_BAD_EYE_OPT_BER = 2452; // 96 -const static uint64_t SH_FLD_BAD_EYE_OPT_DDC = 2453; // 96 -const static uint64_t SH_FLD_BAD_EYE_OPT_HEIGHT = 2454; // 96 -const static uint64_t SH_FLD_BAD_EYE_OPT_WIDTH = 2455; // 96 -const static uint64_t SH_FLD_BAD_LANE1_GCRMSG = 2456; // 4 -const static uint64_t SH_FLD_BAD_LANE1_GCRMSG_LEN = 2457; // 4 -const static uint64_t SH_FLD_BAD_LANE2_GCRMSG = 2458; // 4 -const static uint64_t SH_FLD_BAD_LANE2_GCRMSG_LEN = 2459; // 4 -const static uint64_t SH_FLD_BAD_LANE_CODE_GCRMSG = 2460; // 4 -const static uint64_t SH_FLD_BAD_LANE_CODE_GCRMSG_LEN = 2461; // 4 -const static uint64_t SH_FLD_BAD_SKEW = 2462; // 96 -const static uint64_t SH_FLD_BANDSEL = 2463; // 20 -const static uint64_t SH_FLD_BANDSEL_LEN = 2464; // 20 -const static uint64_t SH_FLD_BANK = 2465; // 24 -const static uint64_t SH_FLD_BANK0_BIT_MAP = 2466; // 8 -const static uint64_t SH_FLD_BANK0_BIT_MAP_LEN = 2467; // 8 -const static uint64_t SH_FLD_BANK1_BIT_MAP = 2468; // 8 -const static uint64_t SH_FLD_BANK1_BIT_MAP_LEN = 2469; // 8 -const static uint64_t SH_FLD_BANK2_BIT_MAP = 2470; // 8 -const static uint64_t SH_FLD_BANK2_BIT_MAP_LEN = 2471; // 8 -const static uint64_t SH_FLD_BANK_GROUP0_BIT_MAP = 2472; // 8 -const static uint64_t SH_FLD_BANK_GROUP0_BIT_MAP_LEN = 2473; // 8 -const static uint64_t SH_FLD_BANK_GROUP1_BIT_MAP = 2474; // 8 -const static uint64_t SH_FLD_BANK_GROUP1_BIT_MAP_LEN = 2475; // 8 -const static uint64_t SH_FLD_BANK_PDWN = 2476; // 48 -const static uint64_t SH_FLD_BANK_PDWN_LEN = 2477; // 48 -const static uint64_t SH_FLD_BANK_SEL_A = 2478; // 48 -const static uint64_t SH_FLD_BAR = 2479; // 6 -const static uint64_t SH_FLD_BAR1_EN = 2480; // 4 -const static uint64_t SH_FLD_BAR1_MS_GROUP_CHIP = 2481; // 2 -const static uint64_t SH_FLD_BAR1_MS_GROUP_CHIP_LEN = 2482; // 2 -const static uint64_t SH_FLD_BAR1_SIZE = 2483; // 2 -const static uint64_t SH_FLD_BAR1_SIZE_LEN = 2484; // 2 -const static uint64_t SH_FLD_BAR1_STARTING_ADDRESS = 2485; // 4 -const static uint64_t SH_FLD_BAR1_STARTING_ADDRESS_LEN = 2486; // 4 -const static uint64_t SH_FLD_BAR1_SYSTEM = 2487; // 2 -const static uint64_t SH_FLD_BAR1_SYSTEM_LEN = 2488; // 2 -const static uint64_t SH_FLD_BARSEL = 2489; // 12 -const static uint64_t SH_FLD_BAR_LEN = 2490; // 6 -const static uint64_t SH_FLD_BAR_PE = 2491; // 13 -const static uint64_t SH_FLD_BAR_PE_MASK = 2492; // 9 -const static uint64_t SH_FLD_BAR_PIB_ON_ERROR1 = 2493; // 1 -const static uint64_t SH_FLD_BAR_PIB_ON_ERROR2 = 2494; // 1 -const static uint64_t SH_FLD_BAR_PIB_ON_ERROR3 = 2495; // 1 -const static uint64_t SH_FLD_BAR_PIB_ON_ERROR4 = 2496; // 1 -const static uint64_t SH_FLD_BAR_PIB_ON_ERROR5 = 2497; // 1 -const static uint64_t SH_FLD_BAR_PIB_ON_ERROR6 = 2498; // 1 -const static uint64_t SH_FLD_BAR_PIB_ON_ERROR7 = 2499; // 1 -const static uint64_t SH_FLD_BASE = 2500; // 26 -const static uint64_t SH_FLD_BASE_ADDR = 2501; // 2 -const static uint64_t SH_FLD_BASE_ADDR_LEN = 2502; // 2 -const static uint64_t SH_FLD_BASE_IDLE_COUNT = 2503; // 8 -const static uint64_t SH_FLD_BASE_IDLE_COUNT_LEN = 2504; // 8 -const static uint64_t SH_FLD_BASE_LEN = 2505; // 26 -const static uint64_t SH_FLD_BASE_UPPER_BITS = 2506; // 1 -const static uint64_t SH_FLD_BASE_UPPER_BITS_LEN = 2507; // 1 -const static uint64_t SH_FLD_BBWR_MASK = 2508; // 3 -const static uint64_t SH_FLD_BBWR_MASK_LEN = 2509; // 3 -const static uint64_t SH_FLD_BCAST_DONE = 2510; // 1 -const static uint64_t SH_FLD_BCDE_CE = 2511; // 1 -const static uint64_t SH_FLD_BCDE_CE_MASK = 2512; // 1 -const static uint64_t SH_FLD_BCDE_OCITRANS = 2513; // 1 -const static uint64_t SH_FLD_BCDE_OCITRANS_LEN = 2514; // 1 -const static uint64_t SH_FLD_BCDE_OCI_DATERR = 2515; // 1 -const static uint64_t SH_FLD_BCDE_OCI_DATERR_MASK = 2516; // 1 -const static uint64_t SH_FLD_BCDE_PB_ACK_DEAD = 2517; // 1 -const static uint64_t SH_FLD_BCDE_PB_ACK_DEAD_MASK = 2518; // 1 -const static uint64_t SH_FLD_BCDE_PB_ADRERR = 2519; // 1 -const static uint64_t SH_FLD_BCDE_PB_ADRERR_MASK = 2520; // 1 -const static uint64_t SH_FLD_BCDE_RDDATATO_ERR = 2521; // 1 -const static uint64_t SH_FLD_BCDE_RDDATATO_ERR_MASK = 2522; // 1 -const static uint64_t SH_FLD_BCDE_SETUP_ERR = 2523; // 1 -const static uint64_t SH_FLD_BCDE_SETUP_ERR_MASK = 2524; // 1 -const static uint64_t SH_FLD_BCDE_SUE_ERR = 2525; // 1 -const static uint64_t SH_FLD_BCDE_SUE_ERR_MASK = 2526; // 1 -const static uint64_t SH_FLD_BCDE_UE_ERR = 2527; // 1 -const static uint64_t SH_FLD_BCDE_UE_ERR_MASK = 2528; // 1 -const static uint64_t SH_FLD_BCESCR_OVERRIDE_EN = 2529; // 12 -const static uint64_t SH_FLD_BCE_BUSY_HIGH = 2530; // 12 -const static uint64_t SH_FLD_BCE_BUSY_LOW = 2531; // 12 -const static uint64_t SH_FLD_BCE_ERROR = 2532; // 12 -const static uint64_t SH_FLD_BCE_TIMEOUT = 2533; // 24 -const static uint64_t SH_FLD_BCUE_OCITRANS = 2534; // 1 -const static uint64_t SH_FLD_BCUE_OCITRANS_LEN = 2535; // 1 -const static uint64_t SH_FLD_BCUE_OCI_DATERR = 2536; // 1 -const static uint64_t SH_FLD_BCUE_OCI_DATERR_MASK = 2537; // 1 -const static uint64_t SH_FLD_BCUE_PB_ACK_DEAD = 2538; // 1 -const static uint64_t SH_FLD_BCUE_PB_ACK_DEAD_MASK = 2539; // 1 -const static uint64_t SH_FLD_BCUE_PB_ADRERR = 2540; // 1 -const static uint64_t SH_FLD_BCUE_PB_ADRERR_MASK = 2541; // 1 -const static uint64_t SH_FLD_BCUE_SETUP_ERR = 2542; // 1 -const static uint64_t SH_FLD_BCUE_SETUP_ERR_MASK = 2543; // 1 -const static uint64_t SH_FLD_BDF = 2544; // 52 -const static uint64_t SH_FLD_BDF2PE_00 = 2545; // 1 -const static uint64_t SH_FLD_BDF2PE_01 = 2546; // 1 -const static uint64_t SH_FLD_BDF2PE_02 = 2547; // 1 -const static uint64_t SH_FLD_BDF2PE_10 = 2548; // 1 -const static uint64_t SH_FLD_BDF2PE_11 = 2549; // 1 -const static uint64_t SH_FLD_BDF2PE_12 = 2550; // 1 -const static uint64_t SH_FLD_BDF2PE_20 = 2551; // 1 -const static uint64_t SH_FLD_BDF2PE_21 = 2552; // 1 -const static uint64_t SH_FLD_BDF2PE_22 = 2553; // 1 -const static uint64_t SH_FLD_BDF2PE_30 = 2554; // 1 -const static uint64_t SH_FLD_BDF2PE_31 = 2555; // 1 -const static uint64_t SH_FLD_BDF2PE_32 = 2556; // 1 -const static uint64_t SH_FLD_BDF2PE_40 = 2557; // 1 -const static uint64_t SH_FLD_BDF2PE_41 = 2558; // 1 -const static uint64_t SH_FLD_BDF2PE_42 = 2559; // 1 -const static uint64_t SH_FLD_BDF2PE_50 = 2560; // 1 -const static uint64_t SH_FLD_BDF2PE_51 = 2561; // 1 -const static uint64_t SH_FLD_BDF2PE_52 = 2562; // 1 -const static uint64_t SH_FLD_BDF_LEN = 2563; // 52 -const static uint64_t SH_FLD_BEAT_NUM = 2564; // 1 -const static uint64_t SH_FLD_BEAT_NUM_ERR = 2565; // 1 -const static uint64_t SH_FLD_BEAT_REC = 2566; // 1 -const static uint64_t SH_FLD_BEAT_REC_ERR = 2567; // 1 -const static uint64_t SH_FLD_BENIGN_PTR_DATA = 2568; // 2 -const static uint64_t SH_FLD_BER_CFG = 2569; // 120 -const static uint64_t SH_FLD_BER_CFG_LEN = 2570; // 120 -const static uint64_t SH_FLD_BER_CLR_COUNT_ON_READ_EN = 2571; // 6 -const static uint64_t SH_FLD_BER_CLR_TIMER_ON_READ_EN = 2572; // 6 -const static uint64_t SH_FLD_BER_COUNT_FREEZE_EN = 2573; // 6 -const static uint64_t SH_FLD_BER_COUNT_SEL = 2574; // 6 -const static uint64_t SH_FLD_BER_COUNT_SEL_LEN = 2575; // 6 -const static uint64_t SH_FLD_BER_DPIPE_MUX_SEL = 2576; // 120 -const static uint64_t SH_FLD_BER_EN = 2577; // 6 -const static uint64_t SH_FLD_BER_TIMEOUT = 2578; // 6 -const static uint64_t SH_FLD_BER_TIMEOUT_LEN = 2579; // 6 -const static uint64_t SH_FLD_BER_TIMER_FREEZE_EN = 2580; // 6 -const static uint64_t SH_FLD_BER_TIMER_SEL = 2581; // 6 -const static uint64_t SH_FLD_BER_TIMER_SEL_LEN = 2582; // 6 -const static uint64_t SH_FLD_BE_ACC_ERROR_0 = 2583; // 2 -const static uint64_t SH_FLD_BE_ACC_ERROR_1 = 2584; // 2 -const static uint64_t SH_FLD_BE_ACC_ERROR_2 = 2585; // 2 -const static uint64_t SH_FLD_BE_ACC_ERROR_3 = 2586; // 2 -const static uint64_t SH_FLD_BE_OV_ERROR_0 = 2587; // 2 -const static uint64_t SH_FLD_BE_OV_ERROR_1 = 2588; // 2 -const static uint64_t SH_FLD_BE_OV_ERROR_2 = 2589; // 2 -const static uint64_t SH_FLD_BE_OV_ERROR_3 = 2590; // 2 -const static uint64_t SH_FLD_BGOFFSET = 2591; // 14 -const static uint64_t SH_FLD_BGOFFSET_LEN = 2592; // 14 -const static uint64_t SH_FLD_BG_SCAN_RATE = 2593; // 2 -const static uint64_t SH_FLD_BG_SCAN_RATE_LEN = 2594; // 2 -const static uint64_t SH_FLD_BHR_DIR_STATE = 2595; // 2 -const static uint64_t SH_FLD_BHR_DIR_STATE_LEN = 2596; // 2 -const static uint64_t SH_FLD_BIG_RSP = 2597; // 1 -const static uint64_t SH_FLD_BIG_STEP = 2598; // 8 -const static uint64_t SH_FLD_BIG_STEP_LEN = 2599; // 8 -const static uint64_t SH_FLD_BISTCLK_EN = 2600; // 6 -const static uint64_t SH_FLD_BISTCLK_EN_LEN = 2601; // 2 -const static uint64_t SH_FLD_BIST_BIT_FAIL_TH = 2602; // 1 -const static uint64_t SH_FLD_BIST_BIT_FAIL_TH_LEN = 2603; // 1 -const static uint64_t SH_FLD_BIST_BUS_DATA_MODE = 2604; // 6 -const static uint64_t SH_FLD_BIST_COMPLETE = 2605; // 1 -const static uint64_t SH_FLD_BIST_CUPLL_LOCK_CHECK_EN = 2606; // 6 -const static uint64_t SH_FLD_BIST_DONE = 2607; // 6 -const static uint64_t SH_FLD_BIST_EN = 2608; // 13 -const static uint64_t SH_FLD_BIST_ENABLE = 2609; // 1 -const static uint64_t SH_FLD_BIST_ERR = 2610; // 96 -const static uint64_t SH_FLD_BIST_ERROR = 2611; // 1 -const static uint64_t SH_FLD_BIST_ERROR_LEN = 2612; // 1 -const static uint64_t SH_FLD_BIST_ERR_A = 2613; // 48 -const static uint64_t SH_FLD_BIST_ERR_B = 2614; // 48 -const static uint64_t SH_FLD_BIST_ERR_E = 2615; // 48 -const static uint64_t SH_FLD_BIST_EXT_START_MODE = 2616; // 6 -const static uint64_t SH_FLD_BIST_EYE_A_WIDTH = 2617; // 6 -const static uint64_t SH_FLD_BIST_EYE_A_WIDTH_LEN = 2618; // 6 -const static uint64_t SH_FLD_BIST_EYE_B_WIDTH = 2619; // 6 -const static uint64_t SH_FLD_BIST_EYE_B_WIDTH_LEN = 2620; // 6 -const static uint64_t SH_FLD_BIST_INIT_DISABLE = 2621; // 6 -const static uint64_t SH_FLD_BIST_INIT_DISABLE_LEN = 2622; // 6 -const static uint64_t SH_FLD_BIST_INIT_DONE = 2623; // 6 -const static uint64_t SH_FLD_BIST_JITTER_PULSE_SEL = 2624; // 4 -const static uint64_t SH_FLD_BIST_JITTER_PULSE_SEL_LEN = 2625; // 4 -const static uint64_t SH_FLD_BIST_LL_ERR = 2626; // 6 -const static uint64_t SH_FLD_BIST_LL_TEST_EN = 2627; // 6 -const static uint64_t SH_FLD_BIST_MIN_EYE_WIDTH = 2628; // 6 -const static uint64_t SH_FLD_BIST_MIN_EYE_WIDTH_LEN = 2629; // 6 -const static uint64_t SH_FLD_BIST_NO_EDGE_DET = 2630; // 6 -const static uint64_t SH_FLD_BIST_PLL_LOCK_TIMEOUT = 2631; // 4 -const static uint64_t SH_FLD_BIST_PLL_LOCK_TIMEOUT_LEN = 2632; // 4 -const static uint64_t SH_FLD_BIST_PRBS_PROP_TIME = 2633; // 6 -const static uint64_t SH_FLD_BIST_PRBS_PROP_TIME_LEN = 2634; // 6 -const static uint64_t SH_FLD_BIST_PRBS_TEST_TIME = 2635; // 6 -const static uint64_t SH_FLD_BIST_PRBS_TEST_TIME_LEN = 2636; // 6 -const static uint64_t SH_FLD_BIST_STORE_EYES_BANK_SEL = 2637; // 6 -const static uint64_t SH_FLD_BIST_STORE_EYES_BANK_SEL_LEN = 2638; // 6 -const static uint64_t SH_FLD_BIST_STORE_EYES_LANE_SEL = 2639; // 6 -const static uint64_t SH_FLD_BIST_STORE_EYES_LANE_SEL_LEN = 2640; // 6 -const static uint64_t SH_FLD_BITS = 2641; // 27 -const static uint64_t SH_FLD_BITSEL = 2642; // 4 -const static uint64_t SH_FLD_BITSEL_LEN = 2643; // 4 -const static uint64_t SH_FLD_BITS_LEN = 2644; // 27 -const static uint64_t SH_FLD_BIT_RATE_DIVISOR = 2645; // 1 -const static uint64_t SH_FLD_BIT_RATE_DIVISOR_0 = 2646; // 3 -const static uint64_t SH_FLD_BIT_RATE_DIVISOR_0_LEN = 2647; // 3 -const static uint64_t SH_FLD_BIT_RATE_DIVISOR_1 = 2648; // 3 -const static uint64_t SH_FLD_BIT_RATE_DIVISOR_1_LEN = 2649; // 3 -const static uint64_t SH_FLD_BIT_RATE_DIVISOR_2 = 2650; // 3 -const static uint64_t SH_FLD_BIT_RATE_DIVISOR_2_LEN = 2651; // 3 -const static uint64_t SH_FLD_BIT_RATE_DIVISOR_3 = 2652; // 3 -const static uint64_t SH_FLD_BIT_RATE_DIVISOR_3_LEN = 2653; // 3 -const static uint64_t SH_FLD_BIT_RATE_DIVISOR_LEN = 2654; // 1 -const static uint64_t SH_FLD_BIT_RATE_DIVISOR_VALUE = 2655; // 1 -const static uint64_t SH_FLD_BIT_RATE_DIVISOR_VALUE_LEN = 2656; // 1 -const static uint64_t SH_FLD_BKINV_INTERLOCK_DIS = 2657; // 1 -const static uint64_t SH_FLD_BLKU_DONE = 2658; // 1 -const static uint64_t SH_FLD_BLOCKID = 2659; // 10 -const static uint64_t SH_FLD_BLOCKID_LEN = 2660; // 10 -const static uint64_t SH_FLD_BLOCKY0 = 2661; // 15 -const static uint64_t SH_FLD_BLOCKY1 = 2662; // 15 -const static uint64_t SH_FLD_BLOCK_FIR_ERR_INJ = 2663; // 24 -const static uint64_t SH_FLD_BLOCK_GROUP_EN = 2664; // 1 -const static uint64_t SH_FLD_BLOCK_MUX_PORT_SEL = 2665; // 2 -const static uint64_t SH_FLD_BLOCK_MUX_PORT_SEL_LEN = 2666; // 2 -const static uint64_t SH_FLD_BLOCK_SEL = 2667; // 2 -const static uint64_t SH_FLD_BLOCK_SEL_LEN = 2668; // 2 -const static uint64_t SH_FLD_BLOCK_TRACK_EN = 2669; // 1 -const static uint64_t SH_FLD_BLOCK_TRACK_RESET_DELAY = 2670; // 1 -const static uint64_t SH_FLD_BLOCK_TRACK_RESET_DELAY_LEN = 2671; // 1 -const static uint64_t SH_FLD_BNDY = 2672; // 43 -const static uint64_t SH_FLD_BOOT_VECTOR_WORD0 = 2673; // 1 -const static uint64_t SH_FLD_BOOT_VECTOR_WORD0_LEN = 2674; // 1 -const static uint64_t SH_FLD_BOOT_VECTOR_WORD1 = 2675; // 1 -const static uint64_t SH_FLD_BOOT_VECTOR_WORD1_LEN = 2676; // 1 -const static uint64_t SH_FLD_BOOT_VECTOR_WORD2 = 2677; // 1 -const static uint64_t SH_FLD_BOOT_VECTOR_WORD2_LEN = 2678; // 1 -const static uint64_t SH_FLD_BOOT_VECTOR_WORD3 = 2679; // 1 -const static uint64_t SH_FLD_BOOT_VECTOR_WORD3_LEN = 2680; // 1 -const static uint64_t SH_FLD_BRAZOS = 2681; // 1 -const static uint64_t SH_FLD_BRICK = 2682; // 16 -const static uint64_t SH_FLD_BRICK_DEBUG_MODE = 2683; // 6 -const static uint64_t SH_FLD_BRICK_ENABLE = 2684; // 6 -const static uint64_t SH_FLD_BRIDGE_ENABLE = 2685; // 1 -const static uint64_t SH_FLD_BRK0 = 2686; // 1 -const static uint64_t SH_FLD_BRK0_CLUSTER = 2687; // 1 -const static uint64_t SH_FLD_BRK0_CLUSTER_LEN = 2688; // 1 -const static uint64_t SH_FLD_BRK1 = 2689; // 1 -const static uint64_t SH_FLD_BRK1_CLUSTER = 2690; // 1 -const static uint64_t SH_FLD_BRK1_CLUSTER_LEN = 2691; // 1 -const static uint64_t SH_FLD_BRK2 = 2692; // 1 -const static uint64_t SH_FLD_BRK2_CLUSTER = 2693; // 1 -const static uint64_t SH_FLD_BRK2_CLUSTER_LEN = 2694; // 1 -const static uint64_t SH_FLD_BRK3 = 2695; // 1 -const static uint64_t SH_FLD_BRK3_CLUSTER = 2696; // 1 -const static uint64_t SH_FLD_BRK3_CLUSTER_LEN = 2697; // 1 -const static uint64_t SH_FLD_BRK4 = 2698; // 1 -const static uint64_t SH_FLD_BRK4_CLUSTER = 2699; // 1 -const static uint64_t SH_FLD_BRK4_CLUSTER_LEN = 2700; // 1 -const static uint64_t SH_FLD_BRK5 = 2701; // 1 -const static uint64_t SH_FLD_BRK5_CLUSTER = 2702; // 1 -const static uint64_t SH_FLD_BRK5_CLUSTER_LEN = 2703; // 1 -const static uint64_t SH_FLD_BROADCAST_SYNC_EN = 2704; // 2 -const static uint64_t SH_FLD_BROADCAST_SYNC_WAIT = 2705; // 2 -const static uint64_t SH_FLD_BROADCAST_SYNC_WAIT_LEN = 2706; // 2 -const static uint64_t SH_FLD_BUF0_REG_DATA0 = 2707; // 2 -const static uint64_t SH_FLD_BUF0_REG_DATA0_LEN = 2708; // 2 -const static uint64_t SH_FLD_BUF1_REG_DATA0 = 2709; // 1 -const static uint64_t SH_FLD_BUF1_REG_DATA0_LEN = 2710; // 1 -const static uint64_t SH_FLD_BUF1_REG_DATA1 = 2711; // 1 -const static uint64_t SH_FLD_BUF1_REG_DATA1_LEN = 2712; // 1 -const static uint64_t SH_FLD_BUFFER = 2713; // 12 -const static uint64_t SH_FLD_BUFFER_OVERRUN = 2714; // 8 -const static uint64_t SH_FLD_BUFFER_STATUS = 2715; // 6 -const static uint64_t SH_FLD_BUFFER_STATUS_LEN = 2716; // 6 -const static uint64_t SH_FLD_BUF_ALLOC_A = 2717; // 4 -const static uint64_t SH_FLD_BUF_ALLOC_B = 2718; // 4 -const static uint64_t SH_FLD_BUF_ALLOC_C = 2719; // 4 -const static uint64_t SH_FLD_BUF_ALLOC_W = 2720; // 4 -const static uint64_t SH_FLD_BUF_INVALIDATE_CTL = 2721; // 4 -const static uint64_t SH_FLD_BURST_WINDOW = 2722; // 8 -const static uint64_t SH_FLD_BURST_WINDOW_LEN = 2723; // 8 -const static uint64_t SH_FLD_BUSY = 2724; // 43 -const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD0 = 2725; // 8 -const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD0_LEN = 2726; // 8 -const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD1 = 2727; // 8 -const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD1_LEN = 2728; // 8 -const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD2 = 2729; // 8 -const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD2_LEN = 2730; // 8 -const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD3 = 2731; // 8 -const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD3_LEN = 2732; // 8 -const static uint64_t SH_FLD_BUSY_COUNTER_WINDOW_SELECT = 2733; // 8 -const static uint64_t SH_FLD_BUSY_COUNTER_WINDOW_SELECT_LEN = 2734; // 8 -const static uint64_t SH_FLD_BUSY_ENABLE = 2735; // 3 -const static uint64_t SH_FLD_BUSY_RESPONSE_CODE = 2736; // 1 -const static uint64_t SH_FLD_BUSY_RESPONSE_CODE_LEN = 2737; // 1 -const static uint64_t SH_FLD_BUSY_RESPONSE_CODE_NO_1 = 2738; // 1 -const static uint64_t SH_FLD_BUSY_RESPONSE_CODE_NO_1_LEN = 2739; // 1 -const static uint64_t SH_FLD_BUSY_STATUS = 2740; // 1 -const static uint64_t SH_FLD_BUSY_STATUS_LEN = 2741; // 1 -const static uint64_t SH_FLD_BUS_ADDR_NVLD_0 = 2742; // 1 -const static uint64_t SH_FLD_BUS_ADDR_NVLD_1 = 2743; // 1 -const static uint64_t SH_FLD_BUS_ADDR_NVLD_2 = 2744; // 1 -const static uint64_t SH_FLD_BUS_ADDR_NVLD_3 = 2745; // 1 -const static uint64_t SH_FLD_BUS_ADDR_P_ERR_0 = 2746; // 1 -const static uint64_t SH_FLD_BUS_ADDR_P_ERR_1 = 2747; // 1 -const static uint64_t SH_FLD_BUS_ADDR_P_ERR_2 = 2748; // 1 -const static uint64_t SH_FLD_BUS_ADDR_P_ERR_3 = 2749; // 1 -const static uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_0 = 2750; // 1 -const static uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_1 = 2751; // 1 -const static uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_2 = 2752; // 1 -const static uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_3 = 2753; // 1 -const static uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_0 = 2754; // 1 -const static uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_1 = 2755; // 1 -const static uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_2 = 2756; // 1 -const static uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_3 = 2757; // 1 -const static uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_0 = 2758; // 1 -const static uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_1 = 2759; // 1 -const static uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_2 = 2760; // 1 -const static uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_3 = 2761; // 1 -const static uint64_t SH_FLD_BUS_BUSY_0 = 2762; // 1 -const static uint64_t SH_FLD_BUS_BUSY_1 = 2763; // 1 -const static uint64_t SH_FLD_BUS_BUSY_2 = 2764; // 1 -const static uint64_t SH_FLD_BUS_BUSY_3 = 2765; // 1 -const static uint64_t SH_FLD_BUS_COMMAND_COMPLETE_0 = 2766; // 1 -const static uint64_t SH_FLD_BUS_COMMAND_COMPLETE_1 = 2767; // 1 -const static uint64_t SH_FLD_BUS_COMMAND_COMPLETE_2 = 2768; // 1 -const static uint64_t SH_FLD_BUS_COMMAND_COMPLETE_3 = 2769; // 1 -const static uint64_t SH_FLD_BUS_DATA_REQUEST_0 = 2770; // 1 -const static uint64_t SH_FLD_BUS_DATA_REQUEST_1 = 2771; // 1 -const static uint64_t SH_FLD_BUS_DATA_REQUEST_2 = 2772; // 1 -const static uint64_t SH_FLD_BUS_DATA_REQUEST_3 = 2773; // 1 -const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_0 = 2774; // 1 -const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_0_LEN = 2775; // 1 -const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_1 = 2776; // 1 -const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_1_LEN = 2777; // 1 -const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_2 = 2778; // 1 -const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_2_LEN = 2779; // 1 -const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_3 = 2780; // 1 -const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_3_LEN = 2781; // 1 -const static uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_0 = 2782; // 1 -const static uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_1 = 2783; // 1 -const static uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_2 = 2784; // 1 -const static uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_3 = 2785; // 1 -const static uint64_t SH_FLD_BUS_I2C_PORT_BUSY_0 = 2786; // 1 -const static uint64_t SH_FLD_BUS_I2C_PORT_BUSY_1 = 2787; // 1 -const static uint64_t SH_FLD_BUS_I2C_PORT_BUSY_2 = 2788; // 1 -const static uint64_t SH_FLD_BUS_I2C_PORT_BUSY_3 = 2789; // 1 -const static uint64_t SH_FLD_BUS_ID = 2790; // 12 -const static uint64_t SH_FLD_BUS_ID_LEN = 2791; // 12 -const static uint64_t SH_FLD_BUS_INVALID_COMMAND_0 = 2792; // 1 -const static uint64_t SH_FLD_BUS_INVALID_COMMAND_1 = 2793; // 1 -const static uint64_t SH_FLD_BUS_INVALID_COMMAND_2 = 2794; // 1 -const static uint64_t SH_FLD_BUS_INVALID_COMMAND_3 = 2795; // 1 -const static uint64_t SH_FLD_BUS_LB_PARITY_ERROR_0 = 2796; // 1 -const static uint64_t SH_FLD_BUS_LB_PARITY_ERROR_1 = 2797; // 1 -const static uint64_t SH_FLD_BUS_LB_PARITY_ERROR_2 = 2798; // 1 -const static uint64_t SH_FLD_BUS_LB_PARITY_ERROR_3 = 2799; // 1 -const static uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_0 = 2800; // 1 -const static uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_1 = 2801; // 1 -const static uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_2 = 2802; // 1 -const static uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_3 = 2803; // 1 -const static uint64_t SH_FLD_BUS_PARITY_ERROR_0 = 2804; // 1 -const static uint64_t SH_FLD_BUS_PARITY_ERROR_1 = 2805; // 1 -const static uint64_t SH_FLD_BUS_PARITY_ERROR_2 = 2806; // 1 -const static uint64_t SH_FLD_BUS_PARITY_ERROR_3 = 2807; // 1 -const static uint64_t SH_FLD_BUS_PAR_ERR_0 = 2808; // 1 -const static uint64_t SH_FLD_BUS_PAR_ERR_1 = 2809; // 1 -const static uint64_t SH_FLD_BUS_PAR_ERR_2 = 2810; // 1 -const static uint64_t SH_FLD_BUS_PAR_ERR_3 = 2811; // 1 -const static uint64_t SH_FLD_BUS_READ_NVLD_0 = 2812; // 1 -const static uint64_t SH_FLD_BUS_READ_NVLD_1 = 2813; // 1 -const static uint64_t SH_FLD_BUS_READ_NVLD_2 = 2814; // 1 -const static uint64_t SH_FLD_BUS_READ_NVLD_3 = 2815; // 1 -const static uint64_t SH_FLD_BUS_STOP_ERROR_0 = 2816; // 1 -const static uint64_t SH_FLD_BUS_STOP_ERROR_1 = 2817; // 1 -const static uint64_t SH_FLD_BUS_STOP_ERROR_2 = 2818; // 1 -const static uint64_t SH_FLD_BUS_STOP_ERROR_3 = 2819; // 1 -const static uint64_t SH_FLD_BUS_WIDTH = 2820; // 4 -const static uint64_t SH_FLD_BUS_WIDTH_LEN = 2821; // 4 -const static uint64_t SH_FLD_BUS_WRITE_NVLD_0 = 2822; // 1 -const static uint64_t SH_FLD_BUS_WRITE_NVLD_1 = 2823; // 1 -const static uint64_t SH_FLD_BUS_WRITE_NVLD_2 = 2824; // 1 -const static uint64_t SH_FLD_BUS_WRITE_NVLD_3 = 2825; // 1 -const static uint64_t SH_FLD_BYPASSCLKOUT = 2826; // 3 -const static uint64_t SH_FLD_BYPASSN = 2827; // 10 -const static uint64_t SH_FLD_BYTE0_SEL = 2828; // 8 -const static uint64_t SH_FLD_BYTE0_SEL_LEN = 2829; // 8 -const static uint64_t SH_FLD_BYTE1_SEL = 2830; // 8 -const static uint64_t SH_FLD_BYTE1_SEL_LEN = 2831; // 8 -const static uint64_t SH_FLD_BYTE2_SEL = 2832; // 8 -const static uint64_t SH_FLD_BYTE2_SEL_LEN = 2833; // 8 -const static uint64_t SH_FLD_BYTE3_SEL = 2834; // 8 -const static uint64_t SH_FLD_BYTE3_SEL_LEN = 2835; // 8 -const static uint64_t SH_FLD_B_BAD_DFE_CONV = 2836; // 144 -const static uint64_t SH_FLD_B_BANK_CONTROLS = 2837; // 48 -const static uint64_t SH_FLD_B_BANK_CONTROLS_LEN = 2838; // 48 -const static uint64_t SH_FLD_B_BIST_EN = 2839; // 2 -const static uint64_t SH_FLD_B_CONTROLS = 2840; // 48 -const static uint64_t SH_FLD_B_CONTROLS_LEN = 2841; // 48 -const static uint64_t SH_FLD_B_CTLE_COARSE = 2842; // 48 -const static uint64_t SH_FLD_B_CTLE_COARSE_LEN = 2843; // 48 -const static uint64_t SH_FLD_B_CTLE_GAIN = 2844; // 48 -const static uint64_t SH_FLD_B_CTLE_GAIN_LEN = 2845; // 48 -const static uint64_t SH_FLD_B_EVEN_INTEG_FINE_GAIN = 2846; // 48 -const static uint64_t SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN = 2847; // 48 -const static uint64_t SH_FLD_B_H1AP_AT_LIMIT = 2848; // 144 -const static uint64_t SH_FLD_B_H1E_VAL = 2849; // 48 -const static uint64_t SH_FLD_B_H1E_VAL_LEN = 2850; // 48 -const static uint64_t SH_FLD_B_H1O_VAL = 2851; // 48 -const static uint64_t SH_FLD_B_H1O_VAL_LEN = 2852; // 48 -const static uint64_t SH_FLD_B_INTEG_COARSE_GAIN = 2853; // 48 -const static uint64_t SH_FLD_B_INTEG_COARSE_GAIN_LEN = 2854; // 48 -const static uint64_t SH_FLD_B_ODD_INTEG_FINE_GAIN = 2855; // 48 -const static uint64_t SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN = 2856; // 48 -const static uint64_t SH_FLD_B_OFFSET_E0 = 2857; // 48 -const static uint64_t SH_FLD_B_OFFSET_E0_LEN = 2858; // 48 -const static uint64_t SH_FLD_B_OFFSET_E1 = 2859; // 48 -const static uint64_t SH_FLD_B_OFFSET_E1_LEN = 2860; // 48 -const static uint64_t SH_FLD_B_OFFSET_O0 = 2861; // 48 -const static uint64_t SH_FLD_B_OFFSET_O0_LEN = 2862; // 48 -const static uint64_t SH_FLD_B_OFFSET_O1 = 2863; // 48 -const static uint64_t SH_FLD_B_OFFSET_O1_LEN = 2864; // 48 -const static uint64_t SH_FLD_B_PATH_OFF_EVEN = 2865; // 48 -const static uint64_t SH_FLD_B_PATH_OFF_EVEN_LEN = 2866; // 48 -const static uint64_t SH_FLD_B_PATH_OFF_ODD = 2867; // 48 -const static uint64_t SH_FLD_B_PATH_OFF_ODD_LEN = 2868; // 48 -const static uint64_t SH_FLD_B_PR_DFE_CLKADJ = 2869; // 48 -const static uint64_t SH_FLD_B_PR_DFE_CLKADJ_LEN = 2870; // 48 -const static uint64_t SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE = 2871; // 12 -const static uint64_t SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE = 2872; // 12 -const static uint64_t SH_FLD_CACHE_CTRL_ARY_SELECT = 2873; // 3 -const static uint64_t SH_FLD_CACHE_CTRL_ARY_SELECT_LEN = 2874; // 3 -const static uint64_t SH_FLD_CACHE_INHIBITED_HIT_CACHEABLE_ERROR = 2875; // 12 -const static uint64_t SH_FLD_CACHE_RD_CE = 2876; // 12 -const static uint64_t SH_FLD_CACHE_RD_CE_AND_UE = 2877; // 12 -const static uint64_t SH_FLD_CACHE_RD_SUE = 2878; // 12 -const static uint64_t SH_FLD_CACHE_RD_UE = 2879; // 12 -const static uint64_t SH_FLD_CACHE_UE_SUE_DETECTED_ON_MODIFIED_LINE_BY_CO = 2880; // 12 -const static uint64_t SH_FLD_CACHE_UE_SUE_DETECTED_ON_NON_MODIFIED_LINE_BY_CO = 2881; // 12 -const static uint64_t SH_FLD_CAC_ALLOC_DIS = 2882; // 2 -const static uint64_t SH_FLD_CAL0_INVALID_ACCESS = 2883; // 8 -const static uint64_t SH_FLD_CAL0_PE = 2884; // 8 -const static uint64_t SH_FLD_CAL1_INVALID_ACCESS = 2885; // 8 -const static uint64_t SH_FLD_CAL1_PE = 2886; // 8 -const static uint64_t SH_FLD_CAL2_INVALID_ACCESS = 2887; // 8 -const static uint64_t SH_FLD_CAL2_PE = 2888; // 8 -const static uint64_t SH_FLD_CAL3_INVALID_ACCESS = 2889; // 8 -const static uint64_t SH_FLD_CAL3_PE = 2890; // 8 -const static uint64_t SH_FLD_CALRECAL = 2891; // 10 -const static uint64_t SH_FLD_CALREQ = 2892; // 10 -const static uint64_t SH_FLD_CAL_LANE_GCRMSG = 2893; // 4 -const static uint64_t SH_FLD_CAL_LANE_GCRMSG_LEN = 2894; // 4 -const static uint64_t SH_FLD_CAL_LANE_PHY_GCRMSG = 2895; // 6 -const static uint64_t SH_FLD_CAL_LANE_PHY_GCRMSG_LEN = 2896; // 6 -const static uint64_t SH_FLD_CAL_LANE_SEL = 2897; // 188 -const static uint64_t SH_FLD_CAL_LANE_VAL_GCRMSG = 2898; // 4 -const static uint64_t SH_FLD_CAL_SM_1HOT = 2899; // 8 -const static uint64_t SH_FLD_CAM256_MAX_CNT = 2900; // 6 -const static uint64_t SH_FLD_CAM256_MAX_CNT_LEN = 2901; // 6 -const static uint64_t SH_FLD_CAPP_ERROR = 2902; // 9 -const static uint64_t SH_FLD_CAPP_ERROR_MASK = 2903; // 9 -const static uint64_t SH_FLD_CAPSEL = 2904; // 4 -const static uint64_t SH_FLD_CASCADE = 2905; // 5 -const static uint64_t SH_FLD_CASCADE_LEN = 2906; // 5 -const static uint64_t SH_FLD_CC = 2907; // 10 -const static uint64_t SH_FLD_CCALBANDSEL = 2908; // 10 -const static uint64_t SH_FLD_CCALBANDSEL_LEN = 2909; // 10 -const static uint64_t SH_FLD_CCALCOMP = 2910; // 10 -const static uint64_t SH_FLD_CCALCVHOLD = 2911; // 10 -const static uint64_t SH_FLD_CCALERR = 2912; // 10 -const static uint64_t SH_FLD_CCALFMAX = 2913; // 10 -const static uint64_t SH_FLD_CCALFMIN = 2914; // 10 -const static uint64_t SH_FLD_CCALLOAD = 2915; // 10 -const static uint64_t SH_FLD_CCALMETH = 2916; // 10 -const static uint64_t SH_FLD_CCFG_GPTR = 2917; // 43 -const static uint64_t SH_FLD_CCS_ARRAY_CE_ERR_INJ = 2918; // 2 -const static uint64_t SH_FLD_CCS_ARRAY_CE_ERR_INJ_MODE = 2919; // 2 -const static uint64_t SH_FLD_CCS_ARRAY_UE_ERR_INJ = 2920; // 2 -const static uint64_t SH_FLD_CCS_ARRAY_UE_ERR_INJ_MODE = 2921; // 2 -const static uint64_t SH_FLD_CCS_CNTLQ_PE_HOLD_OUT = 2922; // 2 -const static uint64_t SH_FLD_CCS_FSM_INJ_MODE = 2923; // 2 -const static uint64_t SH_FLD_CCS_FSM_INJ_REG = 2924; // 2 -const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE0 = 2925; // 2 -const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE0_LEN = 2926; // 2 -const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE1 = 2927; // 2 -const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE1_LEN = 2928; // 2 -const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE2 = 2929; // 2 -const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE2_LEN = 2930; // 2 -const static uint64_t SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC = 2931; // 43 -const static uint64_t SH_FLD_CC_CTRL_OPCG_DONE_DC = 2932; // 43 -const static uint64_t SH_FLD_CC_MASK = 2933; // 8 -const static uint64_t SH_FLD_CD_ALL_DONE_GCRMSG = 2934; // 4 -const static uint64_t SH_FLD_CD_PREV_DONE_GCRMSG = 2935; // 4 -const static uint64_t SH_FLD_CE = 2936; // 43 -const static uint64_t SH_FLD_CE1_0_OUT = 2937; // 4 -const static uint64_t SH_FLD_CE1_1_OUT = 2938; // 4 -const static uint64_t SH_FLD_CE1_2_OUT = 2939; // 4 -const static uint64_t SH_FLD_CE1_3_OUT = 2940; // 4 -const static uint64_t SH_FLD_CE1_4_OUT = 2941; // 4 -const static uint64_t SH_FLD_CE1_5_OUT = 2942; // 4 -const static uint64_t SH_FLD_CE1_6_OUT = 2943; // 4 -const static uint64_t SH_FLD_CE1_7_OUT = 2944; // 4 -const static uint64_t SH_FLD_CE2_0_OUT = 2945; // 4 -const static uint64_t SH_FLD_CE2_1_OUT = 2946; // 4 -const static uint64_t SH_FLD_CE2_2_OUT = 2947; // 4 -const static uint64_t SH_FLD_CE2_3_OUT = 2948; // 4 -const static uint64_t SH_FLD_CE2_4_OUT = 2949; // 4 -const static uint64_t SH_FLD_CE2_5_OUT = 2950; // 4 -const static uint64_t SH_FLD_CE2_6_OUT = 2951; // 4 -const static uint64_t SH_FLD_CE2_7_OUT = 2952; // 4 -const static uint64_t SH_FLD_CEC_PSI_INTERRUPT = 2953; // 1 -const static uint64_t SH_FLD_CENTAURP_ENABLE_64B_READ_OPS = 2954; // 4 -const static uint64_t SH_FLD_CENTAURP_ENABLE_BYPASS_CMD = 2955; // 4 -const static uint64_t SH_FLD_CENTAURP_ENABLE_CENTAURP_CMD = 2956; // 4 -const static uint64_t SH_FLD_CENTAURP_ENABLE_CP_ME = 2957; // 4 -const static uint64_t SH_FLD_CENTAURP_ENABLE_CR_SIDEBAND = 2958; // 4 -const static uint64_t SH_FLD_CENTAURP_ENABLE_DTAG_CR = 2959; // 4 -const static uint64_t SH_FLD_CENTAURP_ENABLE_DYNAMIC_WRBUF_ALLOC = 2960; // 4 -const static uint64_t SH_FLD_CENTAURP_ENABLE_ECRESP = 2961; // 4 -const static uint64_t SH_FLD_CENTAURP_ENABLE_NEW_AMO = 2962; // 4 -const static uint64_t SH_FLD_CENTAURP_INBAND_IS_63 = 2963; // 4 -const static uint64_t SH_FLD_CENTAUR_MODE = 2964; // 4 -const static uint64_t SH_FLD_CENTAUR_SYNC_COMMAND_DETECTED = 2965; // 4 -const static uint64_t SH_FLD_CERR_AXFLOW_ERR = 2966; // 1 -const static uint64_t SH_FLD_CERR_AXFLOW_ERR_LEN = 2967; // 1 -const static uint64_t SH_FLD_CERR_AXPUSH_WRERR = 2968; // 1 -const static uint64_t SH_FLD_CERR_AXPUSH_WRERR_LEN = 2969; // 1 -const static uint64_t SH_FLD_CERR_BAR_PARITY_ERR = 2970; // 1 -const static uint64_t SH_FLD_CERR_BCDE_INTERNAL_ERR = 2971; // 1 -const static uint64_t SH_FLD_CERR_BCDE_INTERNAL_ERR_LEN = 2972; // 1 -const static uint64_t SH_FLD_CERR_BCDE_SETUP_ERR = 2973; // 1 -const static uint64_t SH_FLD_CERR_BCDE_SETUP_ERR_LEN = 2974; // 1 -const static uint64_t SH_FLD_CERR_BCUE_INTERNAL_ERR = 2975; // 1 -const static uint64_t SH_FLD_CERR_BCUE_INTERNAL_ERR_LEN = 2976; // 1 -const static uint64_t SH_FLD_CERR_BCUE_OCI_DATAERR = 2977; // 1 -const static uint64_t SH_FLD_CERR_BCUE_OCI_DATAERR_LEN = 2978; // 1 -const static uint64_t SH_FLD_CERR_BCUE_SETUP_ERR = 2979; // 1 -const static uint64_t SH_FLD_CERR_BCUE_SETUP_ERR_LEN = 2980; // 1 -const static uint64_t SH_FLD_CERR_PBDOUT_PARITY_ERR = 2981; // 1 -const static uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_RD = 2982; // 1 -const static uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_RD_LEN = 2983; // 1 -const static uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_WR = 2984; // 1 -const static uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_WR_LEN = 2985; // 1 -const static uint64_t SH_FLD_CERR_PB_BADCRESP = 2986; // 1 -const static uint64_t SH_FLD_CERR_PB_BADCRESP_LEN = 2987; // 1 -const static uint64_t SH_FLD_CERR_PB_OPERTO = 2988; // 1 -const static uint64_t SH_FLD_CERR_PB_OPERTO_LEN = 2989; // 1 -const static uint64_t SH_FLD_CERR_PB_PARITY_ERR = 2990; // 1 -const static uint64_t SH_FLD_CERR_PB_PARITY_ERR_LEN = 2991; // 1 -const static uint64_t SH_FLD_CERR_PB_RDADRERR_FW = 2992; // 1 -const static uint64_t SH_FLD_CERR_PB_RDADRERR_FW_LEN = 2993; // 1 -const static uint64_t SH_FLD_CERR_PB_RDDATATO_FW = 2994; // 1 -const static uint64_t SH_FLD_CERR_PB_RDDATATO_FW_LEN = 2995; // 1 -const static uint64_t SH_FLD_CERR_PB_UNEXPCRESP = 2996; // 1 -const static uint64_t SH_FLD_CERR_PB_UNEXPCRESP_LEN = 2997; // 1 -const static uint64_t SH_FLD_CERR_PB_UNEXPDATA = 2998; // 1 -const static uint64_t SH_FLD_CERR_PB_UNEXPDATA_LEN = 2999; // 1 -const static uint64_t SH_FLD_CERR_PB_WRADRERR_FW = 3000; // 1 -const static uint64_t SH_FLD_CERR_PB_WRADRERR_FW_LEN = 3001; // 1 -const static uint64_t SH_FLD_CERR_SCOMTB_ERR = 3002; // 1 -const static uint64_t SH_FLD_CERR_SLV_INTERNAL_ERR = 3003; // 1 -const static uint64_t SH_FLD_CERR_SLV_INTERNAL_ERR_LEN = 3004; // 1 -const static uint64_t SH_FLD_CERR_SPARE = 3005; // 1 -const static uint64_t SH_FLD_CERR_SPARE_LEN = 3006; // 1 -const static uint64_t SH_FLD_CFG = 3007; // 43 -const static uint64_t SH_FLD_CFG_2N_ADDR = 3008; // 8 -const static uint64_t SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY = 3009; // 8 -const static uint64_t SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY_LEN = 3010; // 8 -const static uint64_t SH_FLD_CFG_ADDRESS_COUNTER = 3011; // 2 -const static uint64_t SH_FLD_CFG_ADDRESS_COUNTER_LEN = 3012; // 2 -const static uint64_t SH_FLD_CFG_ADDR_COUNTER_MODE = 3013; // 2 -const static uint64_t SH_FLD_CFG_ADDR_COUNTER_MODE_LEN = 3014; // 2 -const static uint64_t SH_FLD_CFG_ALL_PERIODIC_LENGTH = 3015; // 8 -const static uint64_t SH_FLD_CFG_ALL_PERIODIC_LENGTH_LEN = 3016; // 8 -const static uint64_t SH_FLD_CFG_ALL_PERIODIC_TB = 3017; // 8 -const static uint64_t SH_FLD_CFG_ALL_PERIODIC_TB_LEN = 3018; // 8 -const static uint64_t SH_FLD_CFG_ALWAYS_WAIT_ACT_TIME = 3019; // 8 -const static uint64_t SH_FLD_CFG_AMAP_BANK0 = 3020; // 2 -const static uint64_t SH_FLD_CFG_AMAP_BANK0_LEN = 3021; // 2 -const static uint64_t SH_FLD_CFG_AMAP_BANK1 = 3022; // 2 -const static uint64_t SH_FLD_CFG_AMAP_BANK1_LEN = 3023; // 2 -const static uint64_t SH_FLD_CFG_AMAP_BANK2 = 3024; // 2 -const static uint64_t SH_FLD_CFG_AMAP_BANK2_LEN = 3025; // 2 -const static uint64_t SH_FLD_CFG_AMAP_BANK_GROUP0 = 3026; // 2 -const static uint64_t SH_FLD_CFG_AMAP_BANK_GROUP0_LEN = 3027; // 2 -const static uint64_t SH_FLD_CFG_AMAP_BANK_GROUP1 = 3028; // 2 -const static uint64_t SH_FLD_CFG_AMAP_BANK_GROUP1_LEN = 3029; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL2 = 3030; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL2_LEN = 3031; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL3 = 3032; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL3_LEN = 3033; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL4 = 3034; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL4_LEN = 3035; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL5 = 3036; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL5_LEN = 3037; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL6 = 3038; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL6_LEN = 3039; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL7 = 3040; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL7_LEN = 3041; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL8 = 3042; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL8_LEN = 3043; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL9 = 3044; // 2 -const static uint64_t SH_FLD_CFG_AMAP_COL9_LEN = 3045; // 2 -const static uint64_t SH_FLD_CFG_AMAP_DIMM_SELECT = 3046; // 2 -const static uint64_t SH_FLD_CFG_AMAP_DIMM_SELECT_LEN = 3047; // 2 -const static uint64_t SH_FLD_CFG_AMAP_MRANK0 = 3048; // 2 -const static uint64_t SH_FLD_CFG_AMAP_MRANK0_LEN = 3049; // 2 -const static uint64_t SH_FLD_CFG_AMAP_MRANK1 = 3050; // 2 -const static uint64_t SH_FLD_CFG_AMAP_MRANK1_LEN = 3051; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW0 = 3052; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW0_LEN = 3053; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW1 = 3054; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW10 = 3055; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW10_LEN = 3056; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW11 = 3057; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW11_LEN = 3058; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW12 = 3059; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW12_LEN = 3060; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW13 = 3061; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW13_LEN = 3062; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW14 = 3063; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW14_LEN = 3064; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW15 = 3065; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW15_LEN = 3066; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW16 = 3067; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW16_LEN = 3068; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW17 = 3069; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW17_LEN = 3070; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW1_LEN = 3071; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW2 = 3072; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW2_LEN = 3073; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW3 = 3074; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW3_LEN = 3075; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW4 = 3076; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW4_LEN = 3077; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW5 = 3078; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW5_LEN = 3079; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW6 = 3080; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW6_LEN = 3081; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW7 = 3082; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW7_LEN = 3083; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW8 = 3084; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW8_LEN = 3085; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW9 = 3086; // 2 -const static uint64_t SH_FLD_CFG_AMAP_ROW9_LEN = 3087; // 2 -const static uint64_t SH_FLD_CFG_AMAP_SRANK0 = 3088; // 2 -const static uint64_t SH_FLD_CFG_AMAP_SRANK0_LEN = 3089; // 2 -const static uint64_t SH_FLD_CFG_AMAP_SRANK1 = 3090; // 2 -const static uint64_t SH_FLD_CFG_AMAP_SRANK1_LEN = 3091; // 2 -const static uint64_t SH_FLD_CFG_AMAP_SRANK2 = 3092; // 2 -const static uint64_t SH_FLD_CFG_AMAP_SRANK2_LEN = 3093; // 2 -const static uint64_t SH_FLD_CFG_ARB_PRIO_PULL = 3094; // 1 -const static uint64_t SH_FLD_CFG_ARB_PRIO_PULL_LEN = 3095; // 1 -const static uint64_t SH_FLD_CFG_ARB_PRIO_PUSH = 3096; // 1 -const static uint64_t SH_FLD_CFG_ARB_PRIO_PUSH_LEN = 3097; // 1 -const static uint64_t SH_FLD_CFG_ARB_PRIO_QUERY = 3098; // 1 -const static uint64_t SH_FLD_CFG_ARB_PRIO_QUERY_LEN = 3099; // 1 -const static uint64_t SH_FLD_CFG_ARB_PRIO_RR = 3100; // 1 -const static uint64_t SH_FLD_CFG_ARB_PRIO_RR_LEN = 3101; // 1 -const static uint64_t SH_FLD_CFG_ARB_PULL_PRIO_HYP = 3102; // 1 -const static uint64_t SH_FLD_CFG_ARB_PULL_PRIO_HYP_LEN = 3103; // 1 -const static uint64_t SH_FLD_CFG_ARB_PUSH_PRIO_HYP = 3104; // 1 -const static uint64_t SH_FLD_CFG_ARB_PUSH_PRIO_HYP_LEN = 3105; // 1 -const static uint64_t SH_FLD_CFG_AUTOPC_THRESHOLD = 3106; // 8 -const static uint64_t SH_FLD_CFG_AUTOPC_THRESHOLD_LEN = 3107; // 8 -const static uint64_t SH_FLD_CFG_BANK_BUSY_FSM_DIS = 3108; // 8 -const static uint64_t SH_FLD_CFG_BANK_BUSY_FSM_DIS_LEN = 3109; // 8 -const static uint64_t SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS = 3110; // 8 -const static uint64_t SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN = 3111; // 8 -const static uint64_t SH_FLD_CFG_BC4_EN = 3112; // 2 -const static uint64_t SH_FLD_CFG_BW_SNAPSHOT = 3113; // 8 -const static uint64_t SH_FLD_CFG_BW_SNAPSHOT_LEN = 3114; // 8 -const static uint64_t SH_FLD_CFG_C0 = 3115; // 1 -const static uint64_t SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL = 3116; // 12 -const static uint64_t SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL_LEN = 3117; // 12 -const static uint64_t SH_FLD_CFG_C0_LEN = 3118; // 1 -const static uint64_t SH_FLD_CFG_C1 = 3119; // 1 -const static uint64_t SH_FLD_CFG_C10 = 3120; // 1 -const static uint64_t SH_FLD_CFG_C10_LEN = 3121; // 1 -const static uint64_t SH_FLD_CFG_C11 = 3122; // 1 -const static uint64_t SH_FLD_CFG_C11_LEN = 3123; // 1 -const static uint64_t SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL = 3124; // 12 -const static uint64_t SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL_LEN = 3125; // 12 -const static uint64_t SH_FLD_CFG_C1_LEN = 3126; // 1 -const static uint64_t SH_FLD_CFG_C2 = 3127; // 1 -const static uint64_t SH_FLD_CFG_C2_LEN = 3128; // 1 -const static uint64_t SH_FLD_CFG_C3 = 3129; // 1 -const static uint64_t SH_FLD_CFG_C3_LEN = 3130; // 1 -const static uint64_t SH_FLD_CFG_C4 = 3131; // 1 -const static uint64_t SH_FLD_CFG_C4_LEN = 3132; // 1 -const static uint64_t SH_FLD_CFG_C5 = 3133; // 1 -const static uint64_t SH_FLD_CFG_C5_LEN = 3134; // 1 -const static uint64_t SH_FLD_CFG_C6 = 3135; // 1 -const static uint64_t SH_FLD_CFG_C6_LEN = 3136; // 1 -const static uint64_t SH_FLD_CFG_C7 = 3137; // 1 -const static uint64_t SH_FLD_CFG_C7_LEN = 3138; // 1 -const static uint64_t SH_FLD_CFG_C8 = 3139; // 1 -const static uint64_t SH_FLD_CFG_C8_LEN = 3140; // 1 -const static uint64_t SH_FLD_CFG_C9 = 3141; // 1 -const static uint64_t SH_FLD_CFG_C9_LEN = 3142; // 1 -const static uint64_t SH_FLD_CFG_CAC_ERR_REPAIR_EN = 3143; // 12 -const static uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR0_ENABLE = 3144; // 8 -const static uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR1_ENABLE = 3145; // 8 -const static uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR2_ENABLE = 3146; // 8 -const static uint64_t SH_FLD_CFG_CAL_RANK_ENABLE = 3147; // 8 -const static uint64_t SH_FLD_CFG_CAL_RANK_ENABLE_LEN = 3148; // 8 -const static uint64_t SH_FLD_CFG_CAL_SINGLE_PORT_MODE = 3149; // 8 -const static uint64_t SH_FLD_CFG_CAL_SINGLE_PORT_MODE_LEN = 3150; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_DDR_DONE = 3151; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_ENABLE = 3152; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_TYPE = 3153; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_TYPE_LEN = 3154; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_DDR_DONE = 3155; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_ENABLE = 3156; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_TYPE = 3157; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_TYPE_LEN = 3158; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_DDR_DONE = 3159; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_ENABLE = 3160; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_TYPE = 3161; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_TYPE_LEN = 3162; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_ENABLE = 3163; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR = 3164; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_LEN = 3165; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB = 3166; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB_LEN = 3167; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_SINGLE_RANK = 3168; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_Z_SYNC = 3169; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR0_Z_SYNC_LEN = 3170; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_DDR_DONE = 3171; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_ENABLE = 3172; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_TYPE = 3173; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_TYPE_LEN = 3174; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_DDR_DONE = 3175; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_ENABLE = 3176; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_TYPE = 3177; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_TYPE_LEN = 3178; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_DDR_DONE = 3179; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_ENABLE = 3180; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_TYPE = 3181; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_TYPE_LEN = 3182; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_SINGLE_RANK = 3183; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_Z_SYNC = 3184; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR1_Z_SYNC_LEN = 3185; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_DDR_DONE = 3186; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_ENABLE = 3187; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_TYPE = 3188; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_TYPE_LEN = 3189; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_DDR_DONE = 3190; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_ENABLE = 3191; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_TYPE = 3192; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_TYPE_LEN = 3193; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_DDR_DONE = 3194; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_ENABLE = 3195; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_TYPE = 3196; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_TYPE_LEN = 3197; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_SINGLE_RANK = 3198; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_WAT_EVENT_ENABLE = 3199; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_Z_SYNC = 3200; // 8 -const static uint64_t SH_FLD_CFG_CAL_TMR2_Z_SYNC_LEN = 3201; // 8 -const static uint64_t SH_FLD_CFG_CCS_ADDR_MUX_SEL = 3202; // 8 -const static uint64_t SH_FLD_CFG_CCS_INST_RESET_ENABLE = 3203; // 8 -const static uint64_t SH_FLD_CFG_CKE_PUP_STATE = 3204; // 8 -const static uint64_t SH_FLD_CFG_CKE_PUP_STATE_LEN = 3205; // 8 -const static uint64_t SH_FLD_CFG_CMD_TIMEOUT_MODE = 3206; // 2 -const static uint64_t SH_FLD_CFG_CMD_TIMEOUT_MODE_LEN = 3207; // 2 -const static uint64_t SH_FLD_CFG_CO_SOFT_PURGE_ALL_LINES_EN = 3208; // 12 -const static uint64_t SH_FLD_CFG_CO_SOFT_PURGE_ME_SX_EN = 3209; // 12 -const static uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP = 3210; // 2 -const static uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP_LEN = 3211; // 2 -const static uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS = 3212; // 2 -const static uint64_t SH_FLD_CFG_CURRENT_PORT_DIMM_TRAP = 3213; // 2 -const static uint64_t SH_FLD_CFG_CURRENT_PORT_DIMM_TRAP_LEN = 3214; // 2 -const static uint64_t SH_FLD_CFG_DATA_ROT = 3215; // 2 -const static uint64_t SH_FLD_CFG_DATA_ROT_LEN = 3216; // 2 -const static uint64_t SH_FLD_CFG_DATA_ROT_SEED = 3217; // 4 -const static uint64_t SH_FLD_CFG_DATA_ROT_SEED_LEN = 3218; // 4 -const static uint64_t SH_FLD_CFG_DATA_SEED_MODE = 3219; // 2 -const static uint64_t SH_FLD_CFG_DATA_SEED_MODE_LEN = 3220; // 2 -const static uint64_t SH_FLD_CFG_DCACHE_CAPP_LPC_EN = 3221; // 12 -const static uint64_t SH_FLD_CFG_DCBZ_TRASHMODE_EN = 3222; // 12 -const static uint64_t SH_FLD_CFG_DDR4E_BLIND_STEER_MODE = 3223; // 2 -const static uint64_t SH_FLD_CFG_DDR4_PARITY_ON_CID_DIS = 3224; // 8 -const static uint64_t SH_FLD_CFG_DDR_DPHY_NCLK = 3225; // 8 -const static uint64_t SH_FLD_CFG_DDR_DPHY_NCLK_LEN = 3226; // 8 -const static uint64_t SH_FLD_CFG_DDR_DPHY_PCLK = 3227; // 8 -const static uint64_t SH_FLD_CFG_DDR_DPHY_PCLK_LEN = 3228; // 8 -const static uint64_t SH_FLD_CFG_DDR_RESETN = 3229; // 8 -const static uint64_t SH_FLD_CFG_DGEN_FIXED_MODE = 3230; // 2 -const static uint64_t SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK = 3231; // 43 -const static uint64_t SH_FLD_CFG_DISABLE_FAST_PATH = 3232; // 8 -const static uint64_t SH_FLD_CFG_DISABLE_FORCE_TO_ZERO = 3233; // 43 -const static uint64_t SH_FLD_CFG_DISABLE_HEARTBEAT = 3234; // 43 -const static uint64_t SH_FLD_CFG_DISABLE_MALF_PULSE_GEN = 3235; // 43 -const static uint64_t SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK = 3236; // 43 -const static uint64_t SH_FLD_CFG_DISABLE_RCD_RECOVERY = 3237; // 8 -const static uint64_t SH_FLD_CFG_DISABLE_RD_PG_MODE = 3238; // 8 -const static uint64_t SH_FLD_CFG_DISABLE_REFRESH_DURING_NOISE_WDW = 3239; // 8 -const static uint64_t SH_FLD_CFG_DISABLE_WR_PG_MODE = 3240; // 8 -const static uint64_t SH_FLD_CFG_DIS_CLK_IN_STR = 3241; // 8 -const static uint64_t SH_FLD_CFG_DIS_SMDR = 3242; // 8 -const static uint64_t SH_FLD_CFG_DONE_IACK_PRIO_HYP = 3243; // 1 -const static uint64_t SH_FLD_CFG_DONE_IACK_PRIO_HYP_LEN = 3244; // 1 -const static uint64_t SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL = 3245; // 1 -const static uint64_t SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL_LEN = 3246; // 1 -const static uint64_t SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL = 3247; // 1 -const static uint64_t SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL_LEN = 3248; // 1 -const static uint64_t SH_FLD_CFG_DONE_PRIO_IACK = 3249; // 1 -const static uint64_t SH_FLD_CFG_DONE_PRIO_IACK_LEN = 3250; // 1 -const static uint64_t SH_FLD_CFG_DONE_PULL_PRIO_HYP = 3251; // 1 -const static uint64_t SH_FLD_CFG_DONE_PULL_PRIO_HYP_LEN = 3252; // 1 -const static uint64_t SH_FLD_CFG_DQS_ALIGNMENT_LENGTH = 3253; // 8 -const static uint64_t SH_FLD_CFG_DQS_ALIGNMENT_LENGTH_LEN = 3254; // 8 -const static uint64_t SH_FLD_CFG_DQS_ALIGNMENT_TB = 3255; // 8 -const static uint64_t SH_FLD_CFG_DQS_ALIGNMENT_TB_LEN = 3256; // 8 -const static uint64_t SH_FLD_CFG_ECCCK_CE_UE_SUE_ERR_DET_DIS = 3257; // 12 -const static uint64_t SH_FLD_CFG_ECCCK_UE_SUE_DET_DIS = 3258; // 12 -const static uint64_t SH_FLD_CFG_EMER_MIN_MAX_DOMAIN = 3259; // 8 -const static uint64_t SH_FLD_CFG_EMER_MIN_MAX_DOMAIN_LEN = 3260; // 8 -const static uint64_t SH_FLD_CFG_ENABLE_RCD_RW_RETRY = 3261; // 8 -const static uint64_t SH_FLD_CFG_END_ADDR_0 = 3262; // 2 -const static uint64_t SH_FLD_CFG_END_ADDR_0_LEN = 3263; // 2 -const static uint64_t SH_FLD_CFG_END_ADDR_1 = 3264; // 2 -const static uint64_t SH_FLD_CFG_END_ADDR_1_LEN = 3265; // 2 -const static uint64_t SH_FLD_CFG_END_ADDR_2 = 3266; // 2 -const static uint64_t SH_FLD_CFG_END_ADDR_2_LEN = 3267; // 2 -const static uint64_t SH_FLD_CFG_END_ADDR_3 = 3268; // 2 -const static uint64_t SH_FLD_CFG_END_ADDR_3_LEN = 3269; // 2 -const static uint64_t SH_FLD_CFG_ENTER_STR_TIME = 3270; // 8 -const static uint64_t SH_FLD_CFG_ENTER_STR_TIME_LEN = 3271; // 8 -const static uint64_t SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR = 3272; // 8 -const static uint64_t SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN = 3273; // 8 -const static uint64_t SH_FLD_CFG_EN_RANDCMD_GAP = 3274; // 2 -const static uint64_t SH_FLD_CFG_EXTERNAL_ZQ_LENGTH = 3275; // 8 -const static uint64_t SH_FLD_CFG_EXTERNAL_ZQ_LENGTH_LEN = 3276; // 8 -const static uint64_t SH_FLD_CFG_EXTERNAL_ZQ_TB = 3277; // 8 -const static uint64_t SH_FLD_CFG_EXTERNAL_ZQ_TB_LEN = 3278; // 8 -const static uint64_t SH_FLD_CFG_FIXED_SEED = 3279; // 16 -const static uint64_t SH_FLD_CFG_FIXED_SEED1 = 3280; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED1_LEN = 3281; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED2 = 3282; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED2_LEN = 3283; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED3 = 3284; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED3_LEN = 3285; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED4 = 3286; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED4_LEN = 3287; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED5 = 3288; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED5_LEN = 3289; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED6 = 3290; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED6_LEN = 3291; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED7 = 3292; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED7_LEN = 3293; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED8 = 3294; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED8_LEN = 3295; // 2 -const static uint64_t SH_FLD_CFG_FIXED_SEED_LEN = 3296; // 16 -const static uint64_t SH_FLD_CFG_FIXED_WIDTH = 3297; // 2 -const static uint64_t SH_FLD_CFG_FIXED_WIDTH_LEN = 3298; // 2 -const static uint64_t SH_FLD_CFG_FORCE_MCLK_LOW_N = 3299; // 8 -const static uint64_t SH_FLD_CFG_FORCE_SPARE_PUP = 3300; // 8 -const static uint64_t SH_FLD_CFG_FREEZE_ON_PARITY_ERROR_DIS = 3301; // 8 -const static uint64_t SH_FLD_CFG_GP_BIT_3_ENABLE = 3302; // 8 -const static uint64_t SH_FLD_CFG_HASH_L3_ADDR_EN = 3303; // 12 -const static uint64_t SH_FLD_CFG_HW_TRIG_LINEDEL_LDDISP_CE_EN = 3304; // 12 -const static uint64_t SH_FLD_CFG_IGNORE_RCD_PARITY_ERR = 3305; // 8 -const static uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_ADDR5 = 3306; // 8 -const static uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_CONSTANT = 3307; // 8 -const static uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_WEN = 3308; // 8 -const static uint64_t SH_FLD_CFG_INJ_CANCEL_ACK_ERR = 3309; // 8 -const static uint64_t SH_FLD_CFG_INTERNAL_ZQ_LENGTH = 3310; // 8 -const static uint64_t SH_FLD_CFG_INTERNAL_ZQ_LENGTH_LEN = 3311; // 8 -const static uint64_t SH_FLD_CFG_INTERNAL_ZQ_TB = 3312; // 8 -const static uint64_t SH_FLD_CFG_INTERNAL_ZQ_TB_LEN = 3313; // 8 -const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR0 = 3314; // 8 -const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR0_LEN = 3315; // 8 -const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR1 = 3316; // 8 -const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR1_LEN = 3317; // 8 -const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR2 = 3318; // 8 -const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR2_LEN = 3319; // 8 -const static uint64_t SH_FLD_CFG_INVERT_DATA = 3320; // 2 -const static uint64_t SH_FLD_CFG_L3_DIS = 3321; // 12 -const static uint64_t SH_FLD_CFG_LDST_PRIO_RSP_LD = 3322; // 1 -const static uint64_t SH_FLD_CFG_LDST_PRIO_RSP_LD_LEN = 3323; // 1 -const static uint64_t SH_FLD_CFG_LDST_PRIO_SET_LD = 3324; // 1 -const static uint64_t SH_FLD_CFG_LDST_PRIO_SET_LD_LEN = 3325; // 1 -const static uint64_t SH_FLD_CFG_LFSR_MASK_A0 = 3326; // 2 -const static uint64_t SH_FLD_CFG_LFSR_MASK_A0_LEN = 3327; // 2 -const static uint64_t SH_FLD_CFG_LINEDEL_ON_CAC_UE_EN = 3328; // 12 -const static uint64_t SH_FLD_CFG_LOG_COUNTS_IN_TRACE = 3329; // 2 -const static uint64_t SH_FLD_CFG_LP_SUB_CNT = 3330; // 8 -const static uint64_t SH_FLD_CFG_LP_SUB_CNT_LEN = 3331; // 8 -const static uint64_t SH_FLD_CFG_LRU_DIRECT_MAP = 3332; // 12 -const static uint64_t SH_FLD_CFG_MAINT_ADDR_MODE_EN = 3333; // 2 -const static uint64_t SH_FLD_CFG_MAINT_BROADCAST_MODE_EN = 3334; // 2 -const static uint64_t SH_FLD_CFG_MAINT_DETECT_SRANK_BOUNDARIES = 3335; // 2 -const static uint64_t SH_FLD_CFG_MAINT_RCE_WITH_CE = 3336; // 2 -const static uint64_t SH_FLD_CFG_MAX = 3337; // 1 -const static uint64_t SH_FLD_CFG_MAX_LEN = 3338; // 1 -const static uint64_t SH_FLD_CFG_MAX_READS_IN_A_ROW = 3339; // 8 -const static uint64_t SH_FLD_CFG_MAX_READS_IN_A_ROW_LEN = 3340; // 8 -const static uint64_t SH_FLD_CFG_MAX_WRITES_IN_A_ROW = 3341; // 8 -const static uint64_t SH_FLD_CFG_MAX_WRITES_IN_A_ROW_LEN = 3342; // 8 -const static uint64_t SH_FLD_CFG_MCB_LEN64 = 3343; // 2 -const static uint64_t SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS = 3344; // 2 -const static uint64_t SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS_LEN = 3345; // 2 -const static uint64_t SH_FLD_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE = 3346; // 2 -const static uint64_t SH_FLD_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE = 3347; // 2 -const static uint64_t SH_FLD_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE = 3348; // 2 -const static uint64_t SH_FLD_CFG_MIN_CMD_GAP = 3349; // 2 -const static uint64_t SH_FLD_CFG_MIN_CMD_GAP_BLIND_STEER = 3350; // 2 -const static uint64_t SH_FLD_CFG_MIN_CMD_GAP_BLIND_STEER_LEN = 3351; // 2 -const static uint64_t SH_FLD_CFG_MIN_CMD_GAP_LEN = 3352; // 2 -const static uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT = 3353; // 8 -const static uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_ENABLE = 3354; // 8 -const static uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME = 3355; // 8 -const static uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN = 3356; // 8 -const static uint64_t SH_FLD_CFG_MIN_GAP_TIMEBASE = 3357; // 2 -const static uint64_t SH_FLD_CFG_MIN_GAP_TIMEBASE_BLIND_STEER = 3358; // 2 -const static uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS = 3359; // 8 -const static uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS_ENABLE = 3360; // 8 -const static uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS_LEN = 3361; // 8 -const static uint64_t SH_FLD_CFG_MISR_BLOCK = 3362; // 8 -const static uint64_t SH_FLD_CFG_MISR_BLOCK_LEN = 3363; // 8 -const static uint64_t SH_FLD_CFG_MISR_FEEDBACK_ENABLE = 3364; // 8 -const static uint64_t SH_FLD_CFG_MPR_READEYE_LENGTH = 3365; // 8 -const static uint64_t SH_FLD_CFG_MPR_READEYE_LENGTH_LEN = 3366; // 8 -const static uint64_t SH_FLD_CFG_MPR_READEYE_TB = 3367; // 8 -const static uint64_t SH_FLD_CFG_MPR_READEYE_TB_LEN = 3368; // 8 -const static uint64_t SH_FLD_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE = 3369; // 2 -const static uint64_t SH_FLD_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE = 3370; // 2 -const static uint64_t SH_FLD_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE = 3371; // 2 -const static uint64_t SH_FLD_CFG_NM_CAS_WEIGHT = 3372; // 8 -const static uint64_t SH_FLD_CFG_NM_CAS_WEIGHT_LEN = 3373; // 8 -const static uint64_t SH_FLD_CFG_NM_CHANGE_AFTER_SYNC = 3374; // 8 -const static uint64_t SH_FLD_CFG_NM_M = 3375; // 8 -const static uint64_t SH_FLD_CFG_NM_M_LEN = 3376; // 8 -const static uint64_t SH_FLD_CFG_NM_N_PER_PORT = 3377; // 8 -const static uint64_t SH_FLD_CFG_NM_N_PER_PORT_LEN = 3378; // 8 -const static uint64_t SH_FLD_CFG_NM_N_PER_SLOT = 3379; // 8 -const static uint64_t SH_FLD_CFG_NM_N_PER_SLOT_LEN = 3380; // 8 -const static uint64_t SH_FLD_CFG_NM_RAS_WEIGHT = 3381; // 8 -const static uint64_t SH_FLD_CFG_NM_RAS_WEIGHT_LEN = 3382; // 8 -const static uint64_t SH_FLD_CFG_NOISE_WAIT_TIME = 3383; // 8 -const static uint64_t SH_FLD_CFG_NOISE_WAIT_TIME_LEN = 3384; // 8 -const static uint64_t SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL = 3385; // 8 -const static uint64_t SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL_LEN = 3386; // 8 -const static uint64_t SH_FLD_CFG_OE_ALL_CKE_POWERED_DOWN = 3387; // 8 -const static uint64_t SH_FLD_CFG_OE_ALWAYS_ON = 3388; // 8 -const static uint64_t SH_FLD_CFG_OPT_RD_SIZE = 3389; // 8 -const static uint64_t SH_FLD_CFG_OPT_RD_SIZE_LEN = 3390; // 8 -const static uint64_t SH_FLD_CFG_PARITY_AFTER_CMD = 3391; // 10 -const static uint64_t SH_FLD_CFG_PARITY_DETECT_TIME = 3392; // 8 -const static uint64_t SH_FLD_CFG_PARITY_DETECT_TIME_LEN = 3393; // 8 -const static uint64_t SH_FLD_CFG_PARSE_PULL_RR_SEL = 3394; // 1 -const static uint64_t SH_FLD_CFG_PARSE_PULL_RR_SEL_LEN = 3395; // 1 -const static uint64_t SH_FLD_CFG_PARSE_PUSH_RR_SEL = 3396; // 1 -const static uint64_t SH_FLD_CFG_PARSE_PUSH_RR_SEL_LEN = 3397; // 1 -const static uint64_t SH_FLD_CFG_PARSE_QUERY_RR_SEL = 3398; // 1 -const static uint64_t SH_FLD_CFG_PARSE_QUERY_RR_SEL_LEN = 3399; // 1 -const static uint64_t SH_FLD_CFG_PAUSE_MCB_ERROR = 3400; // 2 -const static uint64_t SH_FLD_CFG_PAUSE_MCB_LOG_FULL = 3401; // 2 -const static uint64_t SH_FLD_CFG_PAUSE_ON_AUE = 3402; // 2 -const static uint64_t SH_FLD_CFG_PAUSE_ON_ERROR_MODE = 3403; // 2 -const static uint64_t SH_FLD_CFG_PAUSE_ON_ERROR_MODE_LEN = 3404; // 2 -const static uint64_t SH_FLD_CFG_PAUSE_ON_MCE = 3405; // 2 -const static uint64_t SH_FLD_CFG_PAUSE_ON_MPE = 3406; // 2 -const static uint64_t SH_FLD_CFG_PAUSE_ON_RCD = 3407; // 2 -const static uint64_t SH_FLD_CFG_PAUSE_ON_SCE = 3408; // 2 -const static uint64_t SH_FLD_CFG_PAUSE_ON_SUE = 3409; // 2 -const static uint64_t SH_FLD_CFG_PAUSE_ON_UE = 3410; // 2 -const static uint64_t SH_FLD_CFG_PCMD_PRIO_DONE = 3411; // 1 -const static uint64_t SH_FLD_CFG_PCMD_PRIO_DONE_LEN = 3412; // 1 -const static uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_RSP = 3413; // 1 -const static uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_RSP_LEN = 3414; // 1 -const static uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_SET = 3415; // 1 -const static uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_SET_LEN = 3416; // 1 -const static uint64_t SH_FLD_CFG_PCMD_PRIO_RR = 3417; // 1 -const static uint64_t SH_FLD_CFG_PCMD_PRIO_RR_LEN = 3418; // 1 -const static uint64_t SH_FLD_CFG_PDN_PUP = 3419; // 8 -const static uint64_t SH_FLD_CFG_PDN_PUP_LEN = 3420; // 8 -const static uint64_t SH_FLD_CFG_PERFMON_INFO_SRC_ED_SEL = 3421; // 12 -const static uint64_t SH_FLD_CFG_PER_BANK_REFRESH = 3422; // 8 -const static uint64_t SH_FLD_CFG_PM_DISABLE = 3423; // 43 -const static uint64_t SH_FLD_CFG_PM_MUX_DISABLE = 3424; // 43 -const static uint64_t SH_FLD_CFG_PRECHARGE_WAIT_TIME = 3425; // 8 -const static uint64_t SH_FLD_CFG_PRECHARGE_WAIT_TIME_LEN = 3426; // 8 -const static uint64_t SH_FLD_CFG_PRIO_LSI = 3427; // 1 -const static uint64_t SH_FLD_CFG_PRIO_LSI_LEN = 3428; // 1 -const static uint64_t SH_FLD_CFG_PRIO_MMIO = 3429; // 1 -const static uint64_t SH_FLD_CFG_PRIO_MMIO_LEN = 3430; // 1 -const static uint64_t SH_FLD_CFG_PRIO_PULL = 3431; // 1 -const static uint64_t SH_FLD_CFG_PRIO_PULL_LEN = 3432; // 1 -const static uint64_t SH_FLD_CFG_PRIO_PUSH_ARX = 3433; // 1 -const static uint64_t SH_FLD_CFG_PRIO_PUSH_ARX_LEN = 3434; // 1 -const static uint64_t SH_FLD_CFG_PRIO_PUSH_LCL = 3435; // 1 -const static uint64_t SH_FLD_CFG_PRIO_PUSH_LCL_LEN = 3436; // 1 -const static uint64_t SH_FLD_CFG_PRIO_RR = 3437; // 2 -const static uint64_t SH_FLD_CFG_PRIO_RR_LEN = 3438; // 2 -const static uint64_t SH_FLD_CFG_PRIO_RSVD = 3439; // 1 -const static uint64_t SH_FLD_CFG_PRIO_RSVD_LEN = 3440; // 1 -const static uint64_t SH_FLD_CFG_PRIO_VRQ_REQ = 3441; // 1 -const static uint64_t SH_FLD_CFG_PRIO_VRQ_REQ_LEN = 3442; // 1 -const static uint64_t SH_FLD_CFG_PRIO_VRQ_RSP = 3443; // 1 -const static uint64_t SH_FLD_CFG_PRIO_VRQ_RSP_LEN = 3444; // 1 -const static uint64_t SH_FLD_CFG_PULL_RSVD = 3445; // 1 -const static uint64_t SH_FLD_CFG_PULL_RSVD_LEN = 3446; // 1 -const static uint64_t SH_FLD_CFG_PUMP = 3447; // 1 -const static uint64_t SH_FLD_CFG_PUMP_MODE = 3448; // 1 -const static uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE = 3449; // 8 -const static uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME = 3450; // 8 -const static uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN = 3451; // 8 -const static uint64_t SH_FLD_CFG_PUP_ALL_WRITES_PENDING = 3452; // 8 -const static uint64_t SH_FLD_CFG_PUP_AVAIL = 3453; // 8 -const static uint64_t SH_FLD_CFG_PUP_AVAIL_LEN = 3454; // 8 -const static uint64_t SH_FLD_CFG_PUP_PDN = 3455; // 8 -const static uint64_t SH_FLD_CFG_PUP_PDN_LEN = 3456; // 8 -const static uint64_t SH_FLD_CFG_PUSH_ARX_RSVD = 3457; // 1 -const static uint64_t SH_FLD_CFG_PUSH_ARX_RSVD_LEN = 3458; // 1 -const static uint64_t SH_FLD_CFG_QUEUE_ECC_CORR_EN = 3459; // 1 -const static uint64_t SH_FLD_CFG_QUEUE_SIZE_PULL = 3460; // 1 -const static uint64_t SH_FLD_CFG_QUEUE_SIZE_PULL_LEN = 3461; // 1 -const static uint64_t SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL = 3462; // 1 -const static uint64_t SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL_LEN = 3463; // 1 -const static uint64_t SH_FLD_CFG_Q_BIT_TID_MASK = 3464; // 12 -const static uint64_t SH_FLD_CFG_Q_BIT_TID_MASK_LEN = 3465; // 12 -const static uint64_t SH_FLD_CFG_RANDCMD_WGT = 3466; // 2 -const static uint64_t SH_FLD_CFG_RANDCMD_WGT_LEN = 3467; // 2 -const static uint64_t SH_FLD_CFG_RANDGAP_WGT = 3468; // 2 -const static uint64_t SH_FLD_CFG_RANDGAP_WGT_LEN = 3469; // 2 -const static uint64_t SH_FLD_CFG_RANDOM_EN = 3470; // 12 -const static uint64_t SH_FLD_CFG_RANK0_RD_ODT = 3471; // 8 -const static uint64_t SH_FLD_CFG_RANK0_RD_ODT_LEN = 3472; // 8 -const static uint64_t SH_FLD_CFG_RANK0_WR_ODT = 3473; // 8 -const static uint64_t SH_FLD_CFG_RANK0_WR_ODT_LEN = 3474; // 8 -const static uint64_t SH_FLD_CFG_RANK1_RD_ODT = 3475; // 8 -const static uint64_t SH_FLD_CFG_RANK1_RD_ODT_LEN = 3476; // 8 -const static uint64_t SH_FLD_CFG_RANK1_WR_ODT = 3477; // 8 -const static uint64_t SH_FLD_CFG_RANK1_WR_ODT_LEN = 3478; // 8 -const static uint64_t SH_FLD_CFG_RANK2_RD_ODT = 3479; // 8 -const static uint64_t SH_FLD_CFG_RANK2_RD_ODT_LEN = 3480; // 8 -const static uint64_t SH_FLD_CFG_RANK2_WR_ODT = 3481; // 8 -const static uint64_t SH_FLD_CFG_RANK2_WR_ODT_LEN = 3482; // 8 -const static uint64_t SH_FLD_CFG_RANK3_RD_ODT = 3483; // 8 -const static uint64_t SH_FLD_CFG_RANK3_RD_ODT_LEN = 3484; // 8 -const static uint64_t SH_FLD_CFG_RANK3_WR_ODT = 3485; // 8 -const static uint64_t SH_FLD_CFG_RANK3_WR_ODT_LEN = 3486; // 8 -const static uint64_t SH_FLD_CFG_RANK4_RD_ODT = 3487; // 8 -const static uint64_t SH_FLD_CFG_RANK4_RD_ODT_LEN = 3488; // 8 -const static uint64_t SH_FLD_CFG_RANK4_WR_ODT = 3489; // 8 -const static uint64_t SH_FLD_CFG_RANK4_WR_ODT_LEN = 3490; // 8 -const static uint64_t SH_FLD_CFG_RANK5_RD_ODT = 3491; // 8 -const static uint64_t SH_FLD_CFG_RANK5_RD_ODT_LEN = 3492; // 8 -const static uint64_t SH_FLD_CFG_RANK5_WR_ODT = 3493; // 8 -const static uint64_t SH_FLD_CFG_RANK5_WR_ODT_LEN = 3494; // 8 -const static uint64_t SH_FLD_CFG_RANK6_RD_ODT = 3495; // 8 -const static uint64_t SH_FLD_CFG_RANK6_RD_ODT_LEN = 3496; // 8 -const static uint64_t SH_FLD_CFG_RANK6_WR_ODT = 3497; // 8 -const static uint64_t SH_FLD_CFG_RANK6_WR_ODT_LEN = 3498; // 8 -const static uint64_t SH_FLD_CFG_RANK7_RD_ODT = 3499; // 8 -const static uint64_t SH_FLD_CFG_RANK7_RD_ODT_LEN = 3500; // 8 -const static uint64_t SH_FLD_CFG_RANK7_WR_ODT = 3501; // 8 -const static uint64_t SH_FLD_CFG_RANK7_WR_ODT_LEN = 3502; // 8 -const static uint64_t SH_FLD_CFG_RCD_PROTECTION_TIME = 3503; // 8 -const static uint64_t SH_FLD_CFG_RCD_PROTECTION_TIME_LEN = 3504; // 8 -const static uint64_t SH_FLD_CFG_RC_FRC_DISP_EQ_NTM_INIG_SI_TO_RCR_EN = 3505; // 12 -const static uint64_t SH_FLD_CFG_RD2PRE = 3506; // 8 -const static uint64_t SH_FLD_CFG_RD2PRE_LEN = 3507; // 8 -const static uint64_t SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT = 3508; // 8 -const static uint64_t SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT_LEN = 3509; // 8 -const static uint64_t SH_FLD_CFG_RDCLK_SYSCLK_LENGTH = 3510; // 8 -const static uint64_t SH_FLD_CFG_RDCLK_SYSCLK_LENGTH_LEN = 3511; // 8 -const static uint64_t SH_FLD_CFG_RDCLK_SYSCLK_TB = 3512; // 8 -const static uint64_t SH_FLD_CFG_RDCLK_SYSCLK_TB_LEN = 3513; // 8 -const static uint64_t SH_FLD_CFG_RDTAG_DLY = 3514; // 8 -const static uint64_t SH_FLD_CFG_RDTAG_DLY_LEN = 3515; // 8 -const static uint64_t SH_FLD_CFG_RDTAG_MBX_CYCLE = 3516; // 8 -const static uint64_t SH_FLD_CFG_RD_IDLE_ALLOW_WR = 3517; // 8 -const static uint64_t SH_FLD_CFG_RD_IDLE_ALLOW_WR_LEN = 3518; // 8 -const static uint64_t SH_FLD_CFG_REFRESH_ENABLE = 3519; // 8 -const static uint64_t SH_FLD_CFG_REFRESH_HP_RANK_BLOCK_ENABLE = 3520; // 8 -const static uint64_t SH_FLD_CFG_REFRESH_INTERVAL = 3521; // 8 -const static uint64_t SH_FLD_CFG_REFRESH_INTERVAL_LEN = 3522; // 8 -const static uint64_t SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT = 3523; // 8 -const static uint64_t SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN = 3524; // 8 -const static uint64_t SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD = 3525; // 8 -const static uint64_t SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD_LEN = 3526; // 8 -const static uint64_t SH_FLD_CFG_REFRESH_RESET_INTERVAL = 3527; // 8 -const static uint64_t SH_FLD_CFG_REFRESH_RESET_INTERVAL_LEN = 3528; // 8 -const static uint64_t SH_FLD_CFG_REFR_CHECK_INTERVAL = 3529; // 8 -const static uint64_t SH_FLD_CFG_REFR_CHECK_INTERVAL_LEN = 3530; // 8 -const static uint64_t SH_FLD_CFG_REFR_TSV_STACK = 3531; // 8 -const static uint64_t SH_FLD_CFG_REFR_TSV_STACK_LEN = 3532; // 8 -const static uint64_t SH_FLD_CFG_REF_BLOCK_STOP_DLY = 3533; // 8 -const static uint64_t SH_FLD_CFG_REF_BLOCK_STOP_DLY_LEN = 3534; // 8 -const static uint64_t SH_FLD_CFG_RESET_CNTS_START_OF_RANK = 3535; // 2 -const static uint64_t SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT = 3536; // 8 -const static uint64_t SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT_LEN = 3537; // 8 -const static uint64_t SH_FLD_CFG_RODT_BC4_END_DLY = 3538; // 8 -const static uint64_t SH_FLD_CFG_RODT_BC4_END_DLY_LEN = 3539; // 8 -const static uint64_t SH_FLD_CFG_RODT_END_DLY = 3540; // 8 -const static uint64_t SH_FLD_CFG_RODT_END_DLY_LEN = 3541; // 8 -const static uint64_t SH_FLD_CFG_RODT_START_DLY = 3542; // 8 -const static uint64_t SH_FLD_CFG_RODT_START_DLY_LEN = 3543; // 8 -const static uint64_t SH_FLD_CFG_RQ_HANG_THRESHOLD = 3544; // 8 -const static uint64_t SH_FLD_CFG_RQ_HANG_THRESHOLD_LEN = 3545; // 8 -const static uint64_t SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING = 3546; // 8 -const static uint64_t SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING_LEN = 3547; // 8 -const static uint64_t SH_FLD_CFG_RRQ_DEPTH = 3548; // 8 -const static uint64_t SH_FLD_CFG_RRQ_DEPTH_LEN = 3549; // 8 -const static uint64_t SH_FLD_CFG_RRQ_FIFO_MODE = 3550; // 8 -const static uint64_t SH_FLD_CFG_RRQ_SINGLE_THREAD_MODE = 3551; // 8 -const static uint64_t SH_FLD_CFG_RRQ_SKIP_LIMIT = 3552; // 8 -const static uint64_t SH_FLD_CFG_RRQ_SKIP_LIMIT_LEN = 3553; // 8 -const static uint64_t SH_FLD_CFG_RSV0 = 3554; // 8 -const static uint64_t SH_FLD_CFG_RSV0_LEN = 3555; // 8 -const static uint64_t SH_FLD_CFG_RUNTIME_CTR = 3556; // 2 -const static uint64_t SH_FLD_CFG_RUNTIME_CTR_LEN = 3557; // 2 -const static uint64_t SH_FLD_CFG_RUNTIME_MCBALL = 3558; // 2 -const static uint64_t SH_FLD_CFG_RUNTIME_OVERHEAD = 3559; // 2 -const static uint64_t SH_FLD_CFG_RUNTIME_SUBTEST = 3560; // 2 -const static uint64_t SH_FLD_CFG_RUNTIME_SUBTEST_LEN = 3561; // 2 -const static uint64_t SH_FLD_CFG_SAFE_REFRESH_INTERVAL = 3562; // 8 -const static uint64_t SH_FLD_CFG_SAFE_REFRESH_INTERVAL_LEN = 3563; // 8 -const static uint64_t SH_FLD_CFG_SIM_FAST_NOISE_WINDOW = 3564; // 8 -const static uint64_t SH_FLD_CFG_SINGLE_MEM = 3565; // 12 -const static uint64_t SH_FLD_CFG_SINGLE_MEM_EN = 3566; // 12 -const static uint64_t SH_FLD_CFG_SINGLE_MEM_LEN = 3567; // 12 -const static uint64_t SH_FLD_CFG_SLOT0_S0_CID = 3568; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S0_CID_LEN = 3569; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S1_CID = 3570; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S1_CID_LEN = 3571; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S2_CID = 3572; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S2_CID_LEN = 3573; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S3_CID = 3574; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S3_CID_LEN = 3575; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S4_CID = 3576; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S4_CID_LEN = 3577; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S5_CID = 3578; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S5_CID_LEN = 3579; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S6_CID = 3580; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S6_CID_LEN = 3581; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S7_CID = 3582; // 8 -const static uint64_t SH_FLD_CFG_SLOT0_S7_CID_LEN = 3583; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S0_CID = 3584; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S0_CID_LEN = 3585; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S1_CID = 3586; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S1_CID_LEN = 3587; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S2_CID = 3588; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S2_CID_LEN = 3589; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S3_CID = 3590; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S3_CID_LEN = 3591; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S4_CID = 3592; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S4_CID_LEN = 3593; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S5_CID = 3594; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S5_CID_LEN = 3595; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S6_CID = 3596; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S6_CID_LEN = 3597; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S7_CID = 3598; // 8 -const static uint64_t SH_FLD_CFG_SLOT1_S7_CID_LEN = 3599; // 8 -const static uint64_t SH_FLD_CFG_STALL = 3600; // 1 -const static uint64_t SH_FLD_CFG_START_ADDR_0 = 3601; // 2 -const static uint64_t SH_FLD_CFG_START_ADDR_0_LEN = 3602; // 2 -const static uint64_t SH_FLD_CFG_START_ADDR_1 = 3603; // 2 -const static uint64_t SH_FLD_CFG_START_ADDR_1_LEN = 3604; // 2 -const static uint64_t SH_FLD_CFG_START_ADDR_2 = 3605; // 2 -const static uint64_t SH_FLD_CFG_START_ADDR_2_LEN = 3606; // 2 -const static uint64_t SH_FLD_CFG_START_ADDR_3 = 3607; // 2 -const static uint64_t SH_FLD_CFG_START_ADDR_3_LEN = 3608; // 2 -const static uint64_t SH_FLD_CFG_STATIC_IDLE_DLY = 3609; // 8 -const static uint64_t SH_FLD_CFG_STATIC_IDLE_DLY_LEN = 3610; // 8 -const static uint64_t SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP = 3611; // 43 -const static uint64_t SH_FLD_CFG_STQ_PF_EN = 3612; // 12 -const static uint64_t SH_FLD_CFG_STR_ENABLE = 3613; // 8 -const static uint64_t SH_FLD_CFG_STR_STATE = 3614; // 8 -const static uint64_t SH_FLD_CFG_SYMBOL_COUNTER_MODE = 3615; // 2 -const static uint64_t SH_FLD_CFG_SYMBOL_COUNTER_MODE_LEN = 3616; // 2 -const static uint64_t SH_FLD_CFG_SYSMAP_SM_NOT_LG_SEL = 3617; // 12 -const static uint64_t SH_FLD_CFG_TCKESR = 3618; // 8 -const static uint64_t SH_FLD_CFG_TCKESR_LEN = 3619; // 8 -const static uint64_t SH_FLD_CFG_TCKSRE = 3620; // 8 -const static uint64_t SH_FLD_CFG_TCKSRE_LEN = 3621; // 8 -const static uint64_t SH_FLD_CFG_TCKSRX = 3622; // 8 -const static uint64_t SH_FLD_CFG_TCKSRX_LEN = 3623; // 8 -const static uint64_t SH_FLD_CFG_TFAW = 3624; // 8 -const static uint64_t SH_FLD_CFG_TFAW_LEN = 3625; // 8 -const static uint64_t SH_FLD_CFG_THRESH_MAG_ICE = 3626; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_ICE_LEN = 3627; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_HARD = 3628; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_HARD_LEN = 3629; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_INT = 3630; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_INT_LEN = 3631; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_SOFT = 3632; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_SOFT_LEN = 3633; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_HARD = 3634; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_HARD_LEN = 3635; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_INT = 3636; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_INT_LEN = 3637; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_SOFT = 3638; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_SOFT_LEN = 3639; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_RCE = 3640; // 2 -const static uint64_t SH_FLD_CFG_THRESH_MAG_RCE_LEN = 3641; // 2 -const static uint64_t SH_FLD_CFG_TIME_BASE_TMR0 = 3642; // 8 -const static uint64_t SH_FLD_CFG_TIME_BASE_TMR0_LEN = 3643; // 8 -const static uint64_t SH_FLD_CFG_TIME_BASE_TMR1 = 3644; // 8 -const static uint64_t SH_FLD_CFG_TIME_BASE_TMR1_LEN = 3645; // 8 -const static uint64_t SH_FLD_CFG_TIME_BASE_TMR2 = 3646; // 8 -const static uint64_t SH_FLD_CFG_TIME_BASE_TMR2_LEN = 3647; // 8 -const static uint64_t SH_FLD_CFG_TRAS = 3648; // 8 -const static uint64_t SH_FLD_CFG_TRAS_LEN = 3649; // 8 -const static uint64_t SH_FLD_CFG_TRCD = 3650; // 8 -const static uint64_t SH_FLD_CFG_TRCD_LEN = 3651; // 8 -const static uint64_t SH_FLD_CFG_TRFC = 3652; // 8 -const static uint64_t SH_FLD_CFG_TRFC_COUNTER_DIS = 3653; // 8 -const static uint64_t SH_FLD_CFG_TRFC_COUNTER_DIS_LEN = 3654; // 8 -const static uint64_t SH_FLD_CFG_TRFC_LEN = 3655; // 8 -const static uint64_t SH_FLD_CFG_TRFC_STACK_GATE_ALL_REF = 3656; // 8 -const static uint64_t SH_FLD_CFG_TRP = 3657; // 8 -const static uint64_t SH_FLD_CFG_TRP_LEN = 3658; // 8 -const static uint64_t SH_FLD_CFG_TXSDLL = 3659; // 8 -const static uint64_t SH_FLD_CFG_TXSDLL_LEN = 3660; // 8 -const static uint64_t SH_FLD_CFG_VPC_PULL_LMIT = 3661; // 1 -const static uint64_t SH_FLD_CFG_VPC_PULL_LMIT_LEN = 3662; // 1 -const static uint64_t SH_FLD_CFG_VPC_PUSH_ARX_LMIT = 3663; // 1 -const static uint64_t SH_FLD_CFG_VPC_PUSH_ARX_LMIT_LEN = 3664; // 1 -const static uint64_t SH_FLD_CFG_VPC_PUSH_LCL_LMIT = 3665; // 1 -const static uint64_t SH_FLD_CFG_VPC_PUSH_LCL_LMIT_LEN = 3666; // 1 -const static uint64_t SH_FLD_CFG_VPC_PUSH_LCL_RSVD = 3667; // 1 -const static uint64_t SH_FLD_CFG_VPC_PUSH_LCL_RSVD_LEN = 3668; // 1 -const static uint64_t SH_FLD_CFG_WDF_SERIAL_SEQ_MODE = 3669; // 8 -const static uint64_t SH_FLD_CFG_WODT_BC4_END_DLY = 3670; // 8 -const static uint64_t SH_FLD_CFG_WODT_BC4_END_DLY_LEN = 3671; // 8 -const static uint64_t SH_FLD_CFG_WODT_END_DLY = 3672; // 8 -const static uint64_t SH_FLD_CFG_WODT_END_DLY_LEN = 3673; // 8 -const static uint64_t SH_FLD_CFG_WODT_START_DLY = 3674; // 8 -const static uint64_t SH_FLD_CFG_WODT_START_DLY_LEN = 3675; // 8 -const static uint64_t SH_FLD_CFG_WR2PRE = 3676; // 8 -const static uint64_t SH_FLD_CFG_WR2PRE_LEN = 3677; // 8 -const static uint64_t SH_FLD_CFG_WRDATA_DLY = 3678; // 8 -const static uint64_t SH_FLD_CFG_WRDATA_DLY_LEN = 3679; // 8 -const static uint64_t SH_FLD_CFG_WRDONE_DLY = 3680; // 8 -const static uint64_t SH_FLD_CFG_WRDONE_DLY_LEN = 3681; // 8 -const static uint64_t SH_FLD_CFG_WRITE_HW_MARK = 3682; // 8 -const static uint64_t SH_FLD_CFG_WRITE_HW_MARK_LEN = 3683; // 8 -const static uint64_t SH_FLD_CFG_WRITE_LW_MARK = 3684; // 8 -const static uint64_t SH_FLD_CFG_WRITE_LW_MARK_LEN = 3685; // 8 -const static uint64_t SH_FLD_CFG_WRITE_MODE_ECC_CHK_DIS = 3686; // 16 -const static uint64_t SH_FLD_CFG_WRITE_MODE_ECC_COR_DIS = 3687; // 16 -const static uint64_t SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING = 3688; // 8 -const static uint64_t SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN = 3689; // 8 -const static uint64_t SH_FLD_CFG_WRQ_DEPTH = 3690; // 8 -const static uint64_t SH_FLD_CFG_WRQ_DEPTH_LEN = 3691; // 8 -const static uint64_t SH_FLD_CFG_WRQ_ENABLE_NON_HP_WR = 3692; // 8 -const static uint64_t SH_FLD_CFG_WRQ_ENTRY0_HP_DLY = 3693; // 8 -const static uint64_t SH_FLD_CFG_WRQ_ENTRY0_HP_DLY_LEN = 3694; // 8 -const static uint64_t SH_FLD_CFG_WRQ_FIFO_MODE = 3695; // 8 -const static uint64_t SH_FLD_CFG_WRQ_FLUSH_WR_RANK = 3696; // 8 -const static uint64_t SH_FLD_CFG_WRQ_FRC_ST_RD_HIT_WR = 3697; // 8 -const static uint64_t SH_FLD_CFG_WRQ_SINGLE_THREAD_MODE = 3698; // 8 -const static uint64_t SH_FLD_CFG_WRQ_SKIP_LIMIT = 3699; // 8 -const static uint64_t SH_FLD_CFG_WRQ_SKIP_LIMIT_LEN = 3700; // 8 -const static uint64_t SH_FLD_CGC = 3701; // 24 -const static uint64_t SH_FLD_CGC_LEN = 3702; // 24 -const static uint64_t SH_FLD_CH0 = 3703; // 2 -const static uint64_t SH_FLD_CH0EFT_ACTION = 3704; // 1 -const static uint64_t SH_FLD_CH0EFT_ENA = 3705; // 1 -const static uint64_t SH_FLD_CH0EFT_SELECT = 3706; // 1 -const static uint64_t SH_FLD_CH0EFT_SELECT_LEN = 3707; // 1 -const static uint64_t SH_FLD_CH0EFT_TYPE = 3708; // 1 -const static uint64_t SH_FLD_CH0_842_ECC_CE = 3709; // 1 -const static uint64_t SH_FLD_CH0_842_ECC_UE = 3710; // 1 -const static uint64_t SH_FLD_CH0_CMD_CREDITS_0_5 = 3711; // 1 -const static uint64_t SH_FLD_CH0_CMD_CREDITS_0_5_LEN = 3712; // 1 -const static uint64_t SH_FLD_CH0_EFT = 3713; // 1 -const static uint64_t SH_FLD_CH0_INVALID_STATE = 3714; // 1 -const static uint64_t SH_FLD_CH0_LEN = 3715; // 2 -const static uint64_t SH_FLD_CH0_REF_DIV = 3716; // 1 -const static uint64_t SH_FLD_CH0_REF_DIV_LEN = 3717; // 1 -const static uint64_t SH_FLD_CH0_TIMER_ENBL = 3718; // 1 -const static uint64_t SH_FLD_CH1 = 3719; // 2 -const static uint64_t SH_FLD_CH1EFT_ACTION = 3720; // 1 -const static uint64_t SH_FLD_CH1EFT_ENA = 3721; // 1 -const static uint64_t SH_FLD_CH1EFT_SELECT = 3722; // 1 -const static uint64_t SH_FLD_CH1EFT_SELECT_LEN = 3723; // 1 -const static uint64_t SH_FLD_CH1EFT_TYPE = 3724; // 1 -const static uint64_t SH_FLD_CH1_842_ECC_CE = 3725; // 1 -const static uint64_t SH_FLD_CH1_842_ECC_UE = 3726; // 1 -const static uint64_t SH_FLD_CH1_CMD_CREDITS_0_5 = 3727; // 1 -const static uint64_t SH_FLD_CH1_CMD_CREDITS_0_5_LEN = 3728; // 1 -const static uint64_t SH_FLD_CH1_DAT_CREDITS_0_5 = 3729; // 1 -const static uint64_t SH_FLD_CH1_DAT_CREDITS_0_5_LEN = 3730; // 1 -const static uint64_t SH_FLD_CH1_EFT = 3731; // 1 -const static uint64_t SH_FLD_CH1_INVALID_STATE = 3732; // 1 -const static uint64_t SH_FLD_CH1_LEN = 3733; // 2 -const static uint64_t SH_FLD_CH1_REF_DIV = 3734; // 1 -const static uint64_t SH_FLD_CH1_REF_DIV_LEN = 3735; // 1 -const static uint64_t SH_FLD_CH1_TIMER_ENBL = 3736; // 1 -const static uint64_t SH_FLD_CH2 = 3737; // 2 -const static uint64_t SH_FLD_CH2_CMD_CREDITS_PC_0_5 = 3738; // 1 -const static uint64_t SH_FLD_CH2_CMD_CREDITS_PC_0_5_LEN = 3739; // 1 -const static uint64_t SH_FLD_CH2_CMD_CREDITS_VC_0_5 = 3740; // 1 -const static uint64_t SH_FLD_CH2_CMD_CREDITS_VC_0_5_LEN = 3741; // 1 -const static uint64_t SH_FLD_CH2_INVALID_STATE = 3742; // 1 -const static uint64_t SH_FLD_CH2_LEN = 3743; // 2 -const static uint64_t SH_FLD_CH2_REF_DIV = 3744; // 1 -const static uint64_t SH_FLD_CH2_REF_DIV_LEN = 3745; // 1 -const static uint64_t SH_FLD_CH2_SYM = 3746; // 1 -const static uint64_t SH_FLD_CH2_TIMER_ENBL = 3747; // 1 -const static uint64_t SH_FLD_CH3 = 3748; // 2 -const static uint64_t SH_FLD_CH3_INVALID_STATE = 3749; // 1 -const static uint64_t SH_FLD_CH3_LEN = 3750; // 2 -const static uint64_t SH_FLD_CH3_REF_DIV = 3751; // 1 -const static uint64_t SH_FLD_CH3_REF_DIV_LEN = 3752; // 1 -const static uint64_t SH_FLD_CH3_SYM = 3753; // 1 -const static uint64_t SH_FLD_CH3_TIMER_ENBL = 3754; // 1 -const static uint64_t SH_FLD_CH4GZIP_ACTION = 3755; // 1 -const static uint64_t SH_FLD_CH4GZIP_ENA = 3756; // 1 -const static uint64_t SH_FLD_CH4GZIP_SELECT = 3757; // 1 -const static uint64_t SH_FLD_CH4GZIP_SELECT_LEN = 3758; // 1 -const static uint64_t SH_FLD_CH4GZIP_TYPE = 3759; // 1 -const static uint64_t SH_FLD_CH4_AMF_ECC_CE = 3760; // 1 -const static uint64_t SH_FLD_CH4_AMF_ECC_UE = 3761; // 1 -const static uint64_t SH_FLD_CH4_GZIP = 3762; // 1 -const static uint64_t SH_FLD_CH4_INVALID_STATE = 3763; // 1 -const static uint64_t SH_FLD_CH4_REF_DIV = 3764; // 1 -const static uint64_t SH_FLD_CH4_REF_DIV_LEN = 3765; // 1 -const static uint64_t SH_FLD_CH4_TIMER_ENBL = 3766; // 1 -const static uint64_t SH_FLD_CH5_AMF_ECC_CE = 3767; // 1 -const static uint64_t SH_FLD_CH5_AMF_ECC_UE = 3768; // 1 -const static uint64_t SH_FLD_CH5_INVALID_STATE = 3769; // 1 -const static uint64_t SH_FLD_CH6_AMF_ECC_CE = 3770; // 1 -const static uint64_t SH_FLD_CH6_AMF_ECC_UE = 3771; // 1 -const static uint64_t SH_FLD_CH6_INVALID_STATE = 3772; // 1 -const static uint64_t SH_FLD_CH7_AMF_ECC_CE = 3773; // 1 -const static uint64_t SH_FLD_CH7_AMF_ECC_UE = 3774; // 1 -const static uint64_t SH_FLD_CH7_INVALID_STATE = 3775; // 1 -const static uint64_t SH_FLD_CHANGE_IN_PROGRESS = 3776; // 2 -const static uint64_t SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION = 3777; // 4 -const static uint64_t SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN = 3778; // 4 -const static uint64_t SH_FLD_CHANNEL_0_TIMEOUT_ERROR = 3779; // 4 -const static uint64_t SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION = 3780; // 4 -const static uint64_t SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION_LEN = 3781; // 4 -const static uint64_t SH_FLD_CHANNEL_1_TIMEOUT_ERROR = 3782; // 4 -const static uint64_t SH_FLD_CHANNEL_SELECT = 3783; // 4 -const static uint64_t SH_FLD_CHANNEL_SELECT_LEN = 3784; // 4 -const static uint64_t SH_FLD_CHECKSTOP = 3785; // 1 -const static uint64_t SH_FLD_CHECK_CMDS = 3786; // 2 -const static uint64_t SH_FLD_CHECK_CMDS_EN = 3787; // 2 -const static uint64_t SH_FLD_CHECK_CMDS_LEN = 3788; // 2 -const static uint64_t SH_FLD_CHECK_STOP_GPE0 = 3789; // 1 -const static uint64_t SH_FLD_CHECK_STOP_GPE1 = 3790; // 1 -const static uint64_t SH_FLD_CHECK_STOP_GPE2 = 3791; // 1 -const static uint64_t SH_FLD_CHECK_STOP_GPE3 = 3792; // 1 -const static uint64_t SH_FLD_CHECK_STOP_PPC405 = 3793; // 1 -const static uint64_t SH_FLD_CHIPID = 3794; // 1 -const static uint64_t SH_FLD_CHIPID_LEN = 3795; // 1 -const static uint64_t SH_FLD_CHIPID_OVERRIDE = 3796; // 1 -const static uint64_t SH_FLD_CHIPLET_ATOMIC_LOCK = 3797; // 43 -const static uint64_t SH_FLD_CHIPLET_ENABLE = 3798; // 43 -const static uint64_t SH_FLD_CHIPLET_ERRORS = 3799; // 43 -const static uint64_t SH_FLD_CHIPLET_ERRORS_LEN = 3800; // 43 -const static uint64_t SH_FLD_CHIPLET_GRID_SKITTER = 3801; // 43 -const static uint64_t SH_FLD_CHIPLET_INTERRUPT_FROM_HOST = 3802; // 1 -const static uint64_t SH_FLD_CHIPLET_IS_ALIGNED = 3803; // 43 -const static uint64_t SH_FLD_CHIPLET_OFFLINE = 3804; // 43 -const static uint64_t SH_FLD_CHIPMARK = 3805; // 72 -const static uint64_t SH_FLD_CHIPMARK_LEN = 3806; // 72 -const static uint64_t SH_FLD_CHIP_INTERFACEMODE = 3807; // 2 -const static uint64_t SH_FLD_CHIP_PERSONALISATION = 3808; // 2 -const static uint64_t SH_FLD_CHIP_RESET = 3809; // 1 -const static uint64_t SH_FLD_CHIP_STATUS = 3810; // 194 -const static uint64_t SH_FLD_CHIP_STATUS_LEN = 3811; // 194 -const static uint64_t SH_FLD_CHIP_TOD_STATUS = 3812; // 98 -const static uint64_t SH_FLD_CHIP_TOD_STATUS_LEN = 3813; // 98 -const static uint64_t SH_FLD_CHKSW_ALLOW1_RD = 3814; // 1 -const static uint64_t SH_FLD_CHKSW_ALLOW1_RDWR = 3815; // 1 -const static uint64_t SH_FLD_CHKSW_ALLOW1_WR = 3816; // 1 -const static uint64_t SH_FLD_CHKSW_I2C_BUSY = 3817; // 1 -const static uint64_t SH_FLD_CHKSW_I2C_BUSY_0 = 3818; // 1 -const static uint64_t SH_FLD_CHKSW_I2C_BUSY_1 = 3819; // 1 -const static uint64_t SH_FLD_CHKSW_I2C_BUSY_2 = 3820; // 1 -const static uint64_t SH_FLD_CHKSW_I2C_BUSY_3 = 3821; // 1 -const static uint64_t SH_FLD_CHKSW_OCI_PARCHK_DIS = 3822; // 1 -const static uint64_t SH_FLD_CHKSW_SO_SPARE = 3823; // 1 -const static uint64_t SH_FLD_CHKSW_SO_SPARE_LEN = 3824; // 1 -const static uint64_t SH_FLD_CHKSW_SPARE_6 = 3825; // 1 -const static uint64_t SH_FLD_CHKSW_TANK_RDDATA_PARCHK_DIS = 3826; // 1 -const static uint64_t SH_FLD_CHKSW_VAL_BE_ADDR_CHK_DIS = 3827; // 1 -const static uint64_t SH_FLD_CHKSW_WRFSM_DLY_DIS = 3828; // 1 -const static uint64_t SH_FLD_CHOP1G = 3829; // 1 -const static uint64_t SH_FLD_CHSW_DIS_DATA_HANG = 3830; // 1 -const static uint64_t SH_FLD_CHSW_DIS_ECC_CHECK = 3831; // 1 -const static uint64_t SH_FLD_CHSW_DIS_GROUP_SCOPE = 3832; // 1 -const static uint64_t SH_FLD_CHSW_DIS_OCIABUSPAR_CHECK = 3833; // 1 -const static uint64_t SH_FLD_CHSW_DIS_OCIBEPAR_CHECK = 3834; // 1 -const static uint64_t SH_FLD_CHSW_DIS_OCIDATAPAR_CHECK = 3835; // 1 -const static uint64_t SH_FLD_CHSW_DIS_OCIDATAPAR_GEN = 3836; // 1 -const static uint64_t SH_FLD_CHSW_DIS_OPER_HANG = 3837; // 1 -const static uint64_t SH_FLD_CHSW_DIS_PB_PARITY_CHK = 3838; // 1 -const static uint64_t SH_FLD_CHSW_DIS_RETRY_BACKOFF = 3839; // 1 -const static uint64_t SH_FLD_CHSW_DIS_RTAG_PARITY_CHK = 3840; // 1 -const static uint64_t SH_FLD_CHSW_DIS_WRITE_MATCH_REARB = 3841; // 1 -const static uint64_t SH_FLD_CHSW_EXIT_ON_INVALID_CRESP = 3842; // 1 -const static uint64_t SH_FLD_CHSW_HANG_ON_ADRERROR = 3843; // 1 -const static uint64_t SH_FLD_CHSW_HANG_ON_DERROR = 3844; // 1 -const static uint64_t SH_FLD_CHSW_SKIP_GROUP_SCOPE = 3845; // 1 -const static uint64_t SH_FLD_CHSW_USE_CL_DMA_INJ = 3846; // 1 -const static uint64_t SH_FLD_CHSW_USE_PR_DMA_INJ = 3847; // 1 -const static uint64_t SH_FLD_CHTM_PURGE_C0 = 3848; // 12 -const static uint64_t SH_FLD_CHTM_PURGE_C1 = 3849; // 12 -const static uint64_t SH_FLD_CHTM_PURGE_DONE_C0 = 3850; // 24 -const static uint64_t SH_FLD_CHTM_PURGE_DONE_C1 = 3851; // 24 -const static uint64_t SH_FLD_CIABR_EN = 3852; // 24 -const static uint64_t SH_FLD_CI_BUFF_AVAIL = 3853; // 2 -const static uint64_t SH_FLD_CI_LOAD = 3854; // 1 -const static uint64_t SH_FLD_CI_LOAD_LEN = 3855; // 1 -const static uint64_t SH_FLD_CI_MACHINE_HANG_ERR = 3856; // 12 -const static uint64_t SH_FLD_CI_READ = 3857; // 1 -const static uint64_t SH_FLD_CI_STORE = 3858; // 1 -const static uint64_t SH_FLD_CI_STORE_BUFFER_THRESHOLD = 3859; // 2 -const static uint64_t SH_FLD_CI_STORE_BUFFER_THRESHOLD_LEN = 3860; // 2 -const static uint64_t SH_FLD_CI_STORE_LEN = 3861; // 1 -const static uint64_t SH_FLD_CI_WRITE = 3862; // 1 -const static uint64_t SH_FLD_CKINSM_DIS = 3863; // 1 -const static uint64_t SH_FLD_CKINSM_DIS_LEN = 3864; // 1 -const static uint64_t SH_FLD_CKIN_PROT_ERR_CHK_DIS = 3865; // 1 -const static uint64_t SH_FLD_CKIN_TIMEOUT_CHK_DIS = 3866; // 1 -const static uint64_t SH_FLD_CLEAR = 3867; // 1 -const static uint64_t SH_FLD_CLEAR_CHIPLET_IS_ALIGNED = 3868; // 43 -const static uint64_t SH_FLD_CLKDIST_PDWN = 3869; // 12 -const static uint64_t SH_FLD_CLKDIST_PDWN_LEN = 3870; // 4 -const static uint64_t SH_FLD_CLKGLM_ASYNC_RESET = 3871; // 30 -const static uint64_t SH_FLD_CLKGLM_SEL = 3872; // 30 -const static uint64_t SH_FLD_CLK_ASYNC_RESET = 3873; // 43 -const static uint64_t SH_FLD_CLK_BIST_ACTIVITY_DET = 3874; // 4 -const static uint64_t SH_FLD_CLK_BIST_ERR = 3875; // 4 -const static uint64_t SH_FLD_CLK_DIV_BYPASS_EN = 3876; // 43 -const static uint64_t SH_FLD_CLK_DLY = 3877; // 1 -const static uint64_t SH_FLD_CLK_DLY_LEN = 3878; // 1 -const static uint64_t SH_FLD_CLK_HALF_WIDTH_MODE = 3879; // 4 -const static uint64_t SH_FLD_CLK_INVERT = 3880; // 6 -const static uint64_t SH_FLD_CLK_PDLY_BYPASS_EN = 3881; // 43 -const static uint64_t SH_FLD_CLK_PULSE_EN = 3882; // 43 -const static uint64_t SH_FLD_CLK_PULSE_MODE = 3883; // 43 -const static uint64_t SH_FLD_CLK_PULSE_MODE_LEN = 3884; // 43 -const static uint64_t SH_FLD_CLK_QUIESCE = 3885; // 4 -const static uint64_t SH_FLD_CLK_QUIESCE_LEN = 3886; // 4 -const static uint64_t SH_FLD_CLK_QUIESCE_N = 3887; // 1 -const static uint64_t SH_FLD_CLK_QUIESCE_N_LEN = 3888; // 1 -const static uint64_t SH_FLD_CLK_QUIESCE_P = 3889; // 1 -const static uint64_t SH_FLD_CLK_QUIESCE_P_LEN = 3890; // 1 -const static uint64_t SH_FLD_CLK_RATE = 3891; // 4 -const static uint64_t SH_FLD_CLK_RATE_LEN = 3892; // 4 -const static uint64_t SH_FLD_CLK_RATE_SEL = 3893; // 1 -const static uint64_t SH_FLD_CLK_RATE_SEL_LEN = 3894; // 1 -const static uint64_t SH_FLD_CLK_RUN_COUNT = 3895; // 4 -const static uint64_t SH_FLD_CLK_SB_PULSE_MODE = 3896; // 24 -const static uint64_t SH_FLD_CLK_SB_PULSE_MODE_EN = 3897; // 24 -const static uint64_t SH_FLD_CLK_SB_PULSE_MODE_LEN = 3898; // 24 -const static uint64_t SH_FLD_CLK_SB_SPARE = 3899; // 24 -const static uint64_t SH_FLD_CLK_SB_STRENGTH = 3900; // 24 -const static uint64_t SH_FLD_CLK_SB_STRENGTH_LEN = 3901; // 24 -const static uint64_t SH_FLD_CLK_SW_RESCLK = 3902; // 24 -const static uint64_t SH_FLD_CLK_SW_RESCLK_LEN = 3903; // 24 -const static uint64_t SH_FLD_CLK_SW_SPARE = 3904; // 24 -const static uint64_t SH_FLD_CLK_SYNC = 3905; // 24 -const static uint64_t SH_FLD_CLK_SYNC_DONE = 3906; // 24 -const static uint64_t SH_FLD_CLK_SYNC_ENABLE = 3907; // 24 -const static uint64_t SH_FLD_CLK_UNLOAD_CLK_DISABLE = 3908; // 4 -const static uint64_t SH_FLD_CLK_UNLOAD_SEL = 3909; // 4 -const static uint64_t SH_FLD_CLK_UNLOAD_SEL_LEN = 3910; // 4 -const static uint64_t SH_FLD_CLOCK_CMD = 3911; // 43 -const static uint64_t SH_FLD_CLOCK_CMD_LEN = 3912; // 43 -const static uint64_t SH_FLD_CLOCK_DIVIDER = 3913; // 1 -const static uint64_t SH_FLD_CLOCK_DIVIDER_LEN = 3914; // 1 -const static uint64_t SH_FLD_CLOCK_DIV_4 = 3915; // 3 -const static uint64_t SH_FLD_CLOCK_PERV = 3916; // 43 -const static uint64_t SH_FLD_CLOCK_PULSE_USE_EVEN = 3917; // 43 -const static uint64_t SH_FLD_CLOCK_RATE_SELECTION = 3918; // 3 -const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_0 = 3919; // 1 -const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_0_LEN = 3920; // 1 -const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_1 = 3921; // 2 -const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_1_LEN = 3922; // 2 -const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_LEN = 3923; // 3 -const static uint64_t SH_FLD_CLOCK_UNIT1 = 3924; // 43 -const static uint64_t SH_FLD_CLOCK_UNIT10 = 3925; // 43 -const static uint64_t SH_FLD_CLOCK_UNIT2 = 3926; // 43 -const static uint64_t SH_FLD_CLOCK_UNIT3 = 3927; // 43 -const static uint64_t SH_FLD_CLOCK_UNIT4 = 3928; // 43 -const static uint64_t SH_FLD_CLOCK_UNIT5 = 3929; // 43 -const static uint64_t SH_FLD_CLOCK_UNIT6 = 3930; // 43 -const static uint64_t SH_FLD_CLOCK_UNIT7 = 3931; // 43 -const static uint64_t SH_FLD_CLOCK_UNIT8 = 3932; // 43 -const static uint64_t SH_FLD_CLOCK_UNIT9 = 3933; // 43 -const static uint64_t SH_FLD_CLONE_CS_MODE = 3934; // 8 -const static uint64_t SH_FLD_CLR_PAR_ERRS = 3935; // 16 -const static uint64_t SH_FLD_CL_DATA = 3936; // 43 -const static uint64_t SH_FLD_CL_FINE_DISABLE = 3937; // 4 -const static uint64_t SH_FLD_CL_FINE_DISABLE_LEN = 3938; // 4 -const static uint64_t SH_FLD_CL_FSM = 3939; // 43 -const static uint64_t SH_FLD_CL_GLOBAL_DISABLE = 3940; // 4 -const static uint64_t SH_FLD_CL_GLOBAL_DISABLE_LEN = 3941; // 4 -const static uint64_t SH_FLD_CL_TIMEOUT_SEL = 3942; // 4 -const static uint64_t SH_FLD_CL_TIMEOUT_SEL_LEN = 3943; // 4 -const static uint64_t SH_FLD_CMD = 3944; // 43 -const static uint64_t SH_FLD_CMDREG_BROADCAST_FLAG = 3945; // 1 -const static uint64_t SH_FLD_CMDREG_SCAN_ADDRESS = 3946; // 1 -const static uint64_t SH_FLD_CMDREG_SCAN_ADDRESS_LEN = 3947; // 1 -const static uint64_t SH_FLD_CMDREG_SCAN_REGION = 3948; // 1 -const static uint64_t SH_FLD_CMDREG_SCAN_REGION_LEN = 3949; // 1 -const static uint64_t SH_FLD_CMDREG_SCAN_TYPE = 3950; // 1 -const static uint64_t SH_FLD_CMDREG_SCAN_TYPE_LEN = 3951; // 1 -const static uint64_t SH_FLD_CMDREG_WRITE_FLAG = 3952; // 1 -const static uint64_t SH_FLD_CMD_BUFFER_PAR_ERR = 3953; // 4 -const static uint64_t SH_FLD_CMD_COUNT_ERR = 3954; // 1 -const static uint64_t SH_FLD_CMD_IN_PROG = 3955; // 1 -const static uint64_t SH_FLD_CMD_LEN = 3956; // 43 -const static uint64_t SH_FLD_CMD_PARITY_ERROR = 3957; // 19 -const static uint64_t SH_FLD_CMD_REG = 3958; // 2 -const static uint64_t SH_FLD_CMD_REG_ADDR_1 = 3959; // 1 -const static uint64_t SH_FLD_CMD_REG_ADDR_1_LEN = 3960; // 1 -const static uint64_t SH_FLD_CMD_REG_ADDR_2 = 3961; // 1 -const static uint64_t SH_FLD_CMD_REG_ADDR_2_LEN = 3962; // 1 -const static uint64_t SH_FLD_CMD_REG_ADDR_3 = 3963; // 1 -const static uint64_t SH_FLD_CMD_REG_ADDR_3_LEN = 3964; // 1 -const static uint64_t SH_FLD_CMD_REG_ADDR_4 = 3965; // 1 -const static uint64_t SH_FLD_CMD_REG_ADDR_4_LEN = 3966; // 1 -const static uint64_t SH_FLD_CMD_REG_BIT_READCONT = 3967; // 1 -const static uint64_t SH_FLD_CMD_REG_BIT_RNW = 3968; // 1 -const static uint64_t SH_FLD_CMD_REG_BIT_WITHADDR = 3969; // 1 -const static uint64_t SH_FLD_CMD_REG_BIT_WITHSTART = 3970; // 1 -const static uint64_t SH_FLD_CMD_REG_BIT_WITHSTOP = 3971; // 1 -const static uint64_t SH_FLD_CMD_REG_LEN = 3972; // 2 -const static uint64_t SH_FLD_CMD_REG_LENGTH = 3973; // 1 -const static uint64_t SH_FLD_CMD_REG_LENGTH_LEN = 3974; // 1 -const static uint64_t SH_FLD_CMD_SCOPE = 3975; // 4 -const static uint64_t SH_FLD_CMD_SCOPE_LEN = 3976; // 4 -const static uint64_t SH_FLD_CMD_STATUS = 3977; // 1 -const static uint64_t SH_FLD_CMD_STATUS_LEN = 3978; // 1 -const static uint64_t SH_FLD_CMD_TO_CMD_COUNT = 3979; // 8 -const static uint64_t SH_FLD_CMD_TO_CMD_COUNT_LEN = 3980; // 8 -const static uint64_t SH_FLD_CME_ERR_NOTIFY_DIS = 3981; // 24 -const static uint64_t SH_FLD_CME_INTERPPM_ACLK_ENABLE = 3982; // 6 -const static uint64_t SH_FLD_CME_INTERPPM_ACLK_SEL = 3983; // 6 -const static uint64_t SH_FLD_CME_INTERPPM_DPLL_ENABLE = 3984; // 6 -const static uint64_t SH_FLD_CME_INTERPPM_DPLL_SEL = 3985; // 6 -const static uint64_t SH_FLD_CME_INTERPPM_IVRM_ENABLE = 3986; // 6 -const static uint64_t SH_FLD_CME_INTERPPM_IVRM_SEL = 3987; // 6 -const static uint64_t SH_FLD_CME_INTERPPM_VDM_ENABLE = 3988; // 6 -const static uint64_t SH_FLD_CME_INTERPPM_VDM_SEL = 3989; // 6 -const static uint64_t SH_FLD_CME_MESSAGE = 3990; // 24 -const static uint64_t SH_FLD_CME_MESSAGE_HI = 3991; // 24 -const static uint64_t SH_FLD_CME_MESSAGE_HI_LEN = 3992; // 24 -const static uint64_t SH_FLD_CME_MESSAGE_LEN = 3993; // 24 -const static uint64_t SH_FLD_CME_MESSAGE_NUMBER0 = 3994; // 24 -const static uint64_t SH_FLD_CME_MESSAGE_NUMBER0_LEN = 3995; // 24 -const static uint64_t SH_FLD_CME_MESSAGE_NUMBER_N = 3996; // 72 -const static uint64_t SH_FLD_CME_MESSAGE_NUMBER_N_LEN = 3997; // 72 -const static uint64_t SH_FLD_CME_REQUEST = 3998; // 96 -const static uint64_t SH_FLD_CME_SPECIAL_WKUP_DONE_DIS = 3999; // 24 -const static uint64_t SH_FLD_CMFSI_ACCESS_PROTCT = 4000; // 1 -const static uint64_t SH_FLD_CMLEN = 4001; // 10 -const static uint64_t SH_FLD_CMSK = 4002; // 43 -const static uint64_t SH_FLD_CM_CFG = 4003; // 6 -const static uint64_t SH_FLD_CM_CFG_LEN = 4004; // 6 -const static uint64_t SH_FLD_CM_CNTL = 4005; // 120 -const static uint64_t SH_FLD_CM_CNTL_LEN = 4006; // 120 -const static uint64_t SH_FLD_CM_OFFSET_VAL = 4007; // 6 -const static uint64_t SH_FLD_CM_OFFSET_VAL_LEN = 4008; // 6 -const static uint64_t SH_FLD_CM_TIMEOUT = 4009; // 6 -const static uint64_t SH_FLD_CM_TIMEOUT_LEN = 4010; // 6 -const static uint64_t SH_FLD_CND_HWD_DOES_DEM_IVE = 4011; // 1 -const static uint64_t SH_FLD_CND_HWD_DOES_DEM_IVE_LEN = 4012; // 1 -const static uint64_t SH_FLD_CNT0 = 4013; // 1 -const static uint64_t SH_FLD_CNT0_BIT_PAIR_SEL = 4014; // 1 -const static uint64_t SH_FLD_CNT0_BIT_PAIR_SELECT = 4015; // 1 -const static uint64_t SH_FLD_CNT0_BIT_PAIR_SELECT_LEN = 4016; // 1 -const static uint64_t SH_FLD_CNT0_BIT_PAIR_SEL_LEN = 4017; // 1 -const static uint64_t SH_FLD_CNT0_EN = 4018; // 1 -const static uint64_t SH_FLD_CNT0_ENABLE = 4019; // 1 -const static uint64_t SH_FLD_CNT0_EVENT_SEL = 4020; // 1 -const static uint64_t SH_FLD_CNT0_EVENT_SELECT = 4021; // 1 -const static uint64_t SH_FLD_CNT0_EVENT_SELECT_LEN = 4022; // 1 -const static uint64_t SH_FLD_CNT0_EVENT_SEL_LEN = 4023; // 1 -const static uint64_t SH_FLD_CNT0_LEN = 4024; // 1 -const static uint64_t SH_FLD_CNT0_MUX_SEL = 4025; // 2 -const static uint64_t SH_FLD_CNT0_MUX_SEL_LEN = 4026; // 2 -const static uint64_t SH_FLD_CNT0_PAIR_OP = 4027; // 2 -const static uint64_t SH_FLD_CNT0_PAIR_OP_LEN = 4028; // 2 -const static uint64_t SH_FLD_CNT0_POSEDGE_SEL = 4029; // 1 -const static uint64_t SH_FLD_CNT0_POS_EDGE_SELECT = 4030; // 1 -const static uint64_t SH_FLD_CNT1 = 4031; // 1 -const static uint64_t SH_FLD_CNT1_BIT_PAIR_SEL = 4032; // 1 -const static uint64_t SH_FLD_CNT1_BIT_PAIR_SELECT = 4033; // 1 -const static uint64_t SH_FLD_CNT1_BIT_PAIR_SELECT_LEN = 4034; // 1 -const static uint64_t SH_FLD_CNT1_BIT_PAIR_SEL_LEN = 4035; // 1 -const static uint64_t SH_FLD_CNT1_EN = 4036; // 1 -const static uint64_t SH_FLD_CNT1_ENABLE = 4037; // 1 -const static uint64_t SH_FLD_CNT1_EVENT_SEL = 4038; // 1 -const static uint64_t SH_FLD_CNT1_EVENT_SELECT = 4039; // 1 -const static uint64_t SH_FLD_CNT1_EVENT_SELECT_LEN = 4040; // 1 -const static uint64_t SH_FLD_CNT1_EVENT_SEL_LEN = 4041; // 1 -const static uint64_t SH_FLD_CNT1_LEN = 4042; // 1 -const static uint64_t SH_FLD_CNT1_MUX_SEL = 4043; // 2 -const static uint64_t SH_FLD_CNT1_MUX_SEL_LEN = 4044; // 2 -const static uint64_t SH_FLD_CNT1_PAIR_OP = 4045; // 2 -const static uint64_t SH_FLD_CNT1_PAIR_OP_LEN = 4046; // 2 -const static uint64_t SH_FLD_CNT1_POSEDGE_SEL = 4047; // 1 -const static uint64_t SH_FLD_CNT1_POS_EDGE_SELECT = 4048; // 1 -const static uint64_t SH_FLD_CNT2 = 4049; // 1 -const static uint64_t SH_FLD_CNT2_BIT_PAIR_SEL = 4050; // 1 -const static uint64_t SH_FLD_CNT2_BIT_PAIR_SELECT = 4051; // 1 -const static uint64_t SH_FLD_CNT2_BIT_PAIR_SELECT_LEN = 4052; // 1 -const static uint64_t SH_FLD_CNT2_BIT_PAIR_SEL_LEN = 4053; // 1 -const static uint64_t SH_FLD_CNT2_EN = 4054; // 1 -const static uint64_t SH_FLD_CNT2_ENABLE = 4055; // 1 -const static uint64_t SH_FLD_CNT2_EVENT_SEL = 4056; // 1 -const static uint64_t SH_FLD_CNT2_EVENT_SELECT = 4057; // 1 -const static uint64_t SH_FLD_CNT2_EVENT_SELECT_LEN = 4058; // 1 -const static uint64_t SH_FLD_CNT2_EVENT_SEL_LEN = 4059; // 1 -const static uint64_t SH_FLD_CNT2_LEN = 4060; // 1 -const static uint64_t SH_FLD_CNT2_MUX_SEL = 4061; // 2 -const static uint64_t SH_FLD_CNT2_MUX_SEL_LEN = 4062; // 2 -const static uint64_t SH_FLD_CNT2_PAIR_OP = 4063; // 2 -const static uint64_t SH_FLD_CNT2_PAIR_OP_LEN = 4064; // 2 -const static uint64_t SH_FLD_CNT2_POSEDGE_SEL = 4065; // 1 -const static uint64_t SH_FLD_CNT2_POS_EDGE_SELECT = 4066; // 1 -const static uint64_t SH_FLD_CNT3 = 4067; // 1 -const static uint64_t SH_FLD_CNT3_BIT_PAIR_SEL = 4068; // 1 -const static uint64_t SH_FLD_CNT3_BIT_PAIR_SELECT = 4069; // 1 -const static uint64_t SH_FLD_CNT3_BIT_PAIR_SELECT_LEN = 4070; // 1 -const static uint64_t SH_FLD_CNT3_BIT_PAIR_SEL_LEN = 4071; // 1 -const static uint64_t SH_FLD_CNT3_EN = 4072; // 1 -const static uint64_t SH_FLD_CNT3_ENABLE = 4073; // 1 -const static uint64_t SH_FLD_CNT3_EVENT_SEL = 4074; // 1 -const static uint64_t SH_FLD_CNT3_EVENT_SELECT = 4075; // 1 -const static uint64_t SH_FLD_CNT3_EVENT_SELECT_LEN = 4076; // 1 -const static uint64_t SH_FLD_CNT3_EVENT_SEL_LEN = 4077; // 1 -const static uint64_t SH_FLD_CNT3_LEN = 4078; // 1 -const static uint64_t SH_FLD_CNT3_MUX_SEL = 4079; // 2 -const static uint64_t SH_FLD_CNT3_MUX_SEL_LEN = 4080; // 2 -const static uint64_t SH_FLD_CNT3_PAIR_OP = 4081; // 2 -const static uint64_t SH_FLD_CNT3_PAIR_OP_LEN = 4082; // 2 -const static uint64_t SH_FLD_CNT3_POSEDGE_SEL = 4083; // 1 -const static uint64_t SH_FLD_CNT3_POS_EDGE_SELECT = 4084; // 1 -const static uint64_t SH_FLD_CNTL = 4085; // 8 -const static uint64_t SH_FLD_CNTLS_PREV_LDED_GCRMSG = 4086; // 4 -const static uint64_t SH_FLD_CNTL_LEN = 4087; // 8 -const static uint64_t SH_FLD_CNT_BROADCAST = 4088; // 1 -const static uint64_t SH_FLD_CNT_BROADCAST_LEN = 4089; // 1 -const static uint64_t SH_FLD_CNT_CI_STORE_REPLAY = 4090; // 1 -const static uint64_t SH_FLD_CNT_CI_STORE_REPLAY_LEN = 4091; // 1 -const static uint64_t SH_FLD_CNT_DEM_CACHE_HIT = 4092; // 1 -const static uint64_t SH_FLD_CNT_DEM_CACHE_HIT_LEN = 4093; // 1 -const static uint64_t SH_FLD_CNT_DMA_RD = 4094; // 6 -const static uint64_t SH_FLD_CNT_DMA_RD_LEN = 4095; // 6 -const static uint64_t SH_FLD_CNT_DMA_WR = 4096; // 6 -const static uint64_t SH_FLD_CNT_DMA_WR_LEN = 4097; // 6 -const static uint64_t SH_FLD_CNT_EOI_CACHE_HIT = 4098; // 1 -const static uint64_t SH_FLD_CNT_EOI_CACHE_HIT_LEN = 4099; // 1 -const static uint64_t SH_FLD_CNT_EOI_RESP_REPLAY = 4100; // 2 -const static uint64_t SH_FLD_CNT_EOI_RESP_REPLAY_LEN = 4101; // 2 -const static uint64_t SH_FLD_CNT_EQC_COMMAND = 4102; // 1 -const static uint64_t SH_FLD_CNT_EQC_COMMAND_LEN = 4103; // 1 -const static uint64_t SH_FLD_CNT_EQD_FETCH = 4104; // 1 -const static uint64_t SH_FLD_CNT_EQD_FETCH_LEN = 4105; // 1 -const static uint64_t SH_FLD_CNT_EQD_FETCH_REPLAY = 4106; // 1 -const static uint64_t SH_FLD_CNT_EQD_FETCH_REPLAY_LEN = 4107; // 1 -const static uint64_t SH_FLD_CNT_EQP = 4108; // 1 -const static uint64_t SH_FLD_CNT_EQP_LEN = 4109; // 1 -const static uint64_t SH_FLD_CNT_EQP_REPLAY = 4110; // 1 -const static uint64_t SH_FLD_CNT_EQP_REPLAY_LEN = 4111; // 1 -const static uint64_t SH_FLD_CNT_EQ_FWD = 4112; // 1 -const static uint64_t SH_FLD_CNT_EQ_FWD_LEN = 4113; // 1 -const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC = 4114; // 1 -const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC_LEN = 4115; // 1 -const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC = 4116; // 1 -const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC_LEN = 4117; // 1 -const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_HWD = 4118; // 1 -const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_HWD_LEN = 4119; // 1 -const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_IPI = 4120; // 1 -const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_IPI_LEN = 4121; // 1 -const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS = 4122; // 1 -const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS_LEN = 4123; // 1 -const static uint64_t SH_FLD_CNT_EQ_TRIG_CACHE_HIT = 4124; // 1 -const static uint64_t SH_FLD_CNT_EQ_TRIG_CACHE_HIT_LEN = 4125; // 1 -const static uint64_t SH_FLD_CNT_ESCALATE = 4126; // 1 -const static uint64_t SH_FLD_CNT_ESCALATE_LEN = 4127; // 1 -const static uint64_t SH_FLD_CNT_FIFO_FULL = 4128; // 6 -const static uint64_t SH_FLD_CNT_FIFO_FULL_LEN = 4129; // 6 -const static uint64_t SH_FLD_CNT_GROUP = 4130; // 1 -const static uint64_t SH_FLD_CNT_GROUP_LEN = 4131; // 1 -const static uint64_t SH_FLD_CNT_HWD_DOES_PRF_IVE = 4132; // 1 -const static uint64_t SH_FLD_CNT_HWD_DOES_PRF_IVE_LEN = 4133; // 1 -const static uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE = 4134; // 1 -const static uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_LEN = 4135; // 1 -const static uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC = 4136; // 1 -const static uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC_LEN = 4137; // 1 -const static uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE = 4138; // 1 -const static uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_LEN = 4139; // 1 -const static uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC = 4140; // 1 -const static uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC_LEN = 4141; // 1 -const static uint64_t SH_FLD_CNT_ISB_FETCH = 4142; // 1 -const static uint64_t SH_FLD_CNT_ISB_FETCH_LEN = 4143; // 1 -const static uint64_t SH_FLD_CNT_ISB_FETCH_REPLAY = 4144; // 1 -const static uint64_t SH_FLD_CNT_ISB_FETCH_REPLAY_LEN = 4145; // 1 -const static uint64_t SH_FLD_CNT_ISB_WRITE = 4146; // 1 -const static uint64_t SH_FLD_CNT_ISB_WRITE_LEN = 4147; // 1 -const static uint64_t SH_FLD_CNT_IVC_DEMAND = 4148; // 1 -const static uint64_t SH_FLD_CNT_IVC_DEMAND_LEN = 4149; // 1 -const static uint64_t SH_FLD_CNT_IVC_PRF = 4150; // 1 -const static uint64_t SH_FLD_CNT_IVC_PRF_LEN = 4151; // 1 -const static uint64_t SH_FLD_CNT_IVC_RESP_REPLAY = 4152; // 1 -const static uint64_t SH_FLD_CNT_IVC_RESP_REPLAY_LEN = 4153; // 1 -const static uint64_t SH_FLD_CNT_IVE_FETCH = 4154; // 1 -const static uint64_t SH_FLD_CNT_IVE_FETCH_LEN = 4155; // 1 -const static uint64_t SH_FLD_CNT_IVE_FETCH_REPLAY = 4156; // 1 -const static uint64_t SH_FLD_CNT_IVE_FETCH_REPLAY_LEN = 4157; // 1 -const static uint64_t SH_FLD_CNT_IVVC_RESP = 4158; // 1 -const static uint64_t SH_FLD_CNT_IVVC_RESP_LEN = 4159; // 1 -const static uint64_t SH_FLD_CNT_LOCAL_ESCALATE = 4160; // 1 -const static uint64_t SH_FLD_CNT_LOCAL_ESCALATE_LEN = 4161; // 1 -const static uint64_t SH_FLD_CNT_LOCAL_ESC_CACHE_HIT = 4162; // 1 -const static uint64_t SH_FLD_CNT_LOCAL_ESC_CACHE_HIT_LEN = 4163; // 1 -const static uint64_t SH_FLD_CNT_LOCAL_ESC_REPLAY = 4164; // 1 -const static uint64_t SH_FLD_CNT_LOCAL_ESC_REPLAY_LEN = 4165; // 1 -const static uint64_t SH_FLD_CNT_LOCAL_SBC_REPLAY = 4166; // 1 -const static uint64_t SH_FLD_CNT_LOCAL_SBC_REPLAY_LEN = 4167; // 1 -const static uint64_t SH_FLD_CNT_LOCAL_SBC_UPD = 4168; // 1 -const static uint64_t SH_FLD_CNT_LOCAL_SBC_UPD_LEN = 4169; // 1 -const static uint64_t SH_FLD_CNT_LOCAL_VPC_REPLAY = 4170; // 1 -const static uint64_t SH_FLD_CNT_LOCAL_VPC_REPLAY_LEN = 4171; // 1 -const static uint64_t SH_FLD_CNT_LOCAL_VPC_UPD = 4172; // 1 -const static uint64_t SH_FLD_CNT_LOCAL_VPC_UPD_LEN = 4173; // 1 -const static uint64_t SH_FLD_CNT_LS = 4174; // 1 -const static uint64_t SH_FLD_CNT_LS_LEN = 4175; // 1 -const static uint64_t SH_FLD_CNT_NEW_CMD_STALLED = 4176; // 1 -const static uint64_t SH_FLD_CNT_NEW_CMD_STALLED_LEN = 4177; // 1 -const static uint64_t SH_FLD_CNT_NON_SPEC_EOI = 4178; // 1 -const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_LEN = 4179; // 1 -const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED = 4180; // 1 -const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED_LEN = 4181; // 1 -const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_OWNED = 4182; // 1 -const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_OWNED_LEN = 4183; // 1 -const static uint64_t SH_FLD_CNT_OTHER_CACHE_HIT = 4184; // 1 -const static uint64_t SH_FLD_CNT_OTHER_CACHE_HIT_LEN = 4185; // 1 -const static uint64_t SH_FLD_CNT_PRF_CACHE_HIT = 4186; // 2 -const static uint64_t SH_FLD_CNT_PRF_CACHE_HIT_LEN = 4187; // 2 -const static uint64_t SH_FLD_CNT_R0 = 4188; // 3 -const static uint64_t SH_FLD_CNT_R0_LEN = 4189; // 3 -const static uint64_t SH_FLD_CNT_R10R = 4190; // 3 -const static uint64_t SH_FLD_CNT_R10R_LEN = 4191; // 3 -const static uint64_t SH_FLD_CNT_R10W = 4192; // 3 -const static uint64_t SH_FLD_CNT_R10W_LEN = 4193; // 3 -const static uint64_t SH_FLD_CNT_R1R = 4194; // 3 -const static uint64_t SH_FLD_CNT_R1R_LEN = 4195; // 3 -const static uint64_t SH_FLD_CNT_R1W = 4196; // 3 -const static uint64_t SH_FLD_CNT_R1W_LEN = 4197; // 3 -const static uint64_t SH_FLD_CNT_R2 = 4198; // 3 -const static uint64_t SH_FLD_CNT_R2_LEN = 4199; // 3 -const static uint64_t SH_FLD_CNT_R3 = 4200; // 3 -const static uint64_t SH_FLD_CNT_R3_LEN = 4201; // 3 -const static uint64_t SH_FLD_CNT_R4 = 4202; // 3 -const static uint64_t SH_FLD_CNT_R4_LEN = 4203; // 3 -const static uint64_t SH_FLD_CNT_R5R = 4204; // 3 -const static uint64_t SH_FLD_CNT_R5R_LEN = 4205; // 3 -const static uint64_t SH_FLD_CNT_R5W = 4206; // 3 -const static uint64_t SH_FLD_CNT_R5W_LEN = 4207; // 3 -const static uint64_t SH_FLD_CNT_R6 = 4208; // 3 -const static uint64_t SH_FLD_CNT_R6_LEN = 4209; // 3 -const static uint64_t SH_FLD_CNT_R7EQP = 4210; // 3 -const static uint64_t SH_FLD_CNT_R7EQP_LEN = 4211; // 3 -const static uint64_t SH_FLD_CNT_R7INT = 4212; // 3 -const static uint64_t SH_FLD_CNT_R7INT_LEN = 4213; // 3 -const static uint64_t SH_FLD_CNT_R7RSP = 4214; // 3 -const static uint64_t SH_FLD_CNT_R7RSP_LEN = 4215; // 3 -const static uint64_t SH_FLD_CNT_R8 = 4216; // 3 -const static uint64_t SH_FLD_CNT_R8_LEN = 4217; // 3 -const static uint64_t SH_FLD_CNT_R9 = 4218; // 3 -const static uint64_t SH_FLD_CNT_R9_LEN = 4219; // 3 -const static uint64_t SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY = 4220; // 1 -const static uint64_t SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY_LEN = 4221; // 1 -const static uint64_t SH_FLD_CNT_REMOTE_SBC_UPD = 4222; // 1 -const static uint64_t SH_FLD_CNT_REMOTE_SBC_UPD_LEN = 4223; // 1 -const static uint64_t SH_FLD_CNT_REMOTE_VPC_UPD = 4224; // 1 -const static uint64_t SH_FLD_CNT_REMOTE_VPC_UPD_LEN = 4225; // 1 -const static uint64_t SH_FLD_CNT_REPLAY = 4226; // 1 -const static uint64_t SH_FLD_CNT_REPLAY_LEN = 4227; // 1 -const static uint64_t SH_FLD_CNT_RETRY = 4228; // 2 -const static uint64_t SH_FLD_CNT_RETRY_LEN = 4229; // 2 -const static uint64_t SH_FLD_CNT_SBC_LOOKUP = 4230; // 1 -const static uint64_t SH_FLD_CNT_SBC_LOOKUP_LEN = 4231; // 1 -const static uint64_t SH_FLD_CNT_SBC_LOOKUP_REPLAY = 4232; // 1 -const static uint64_t SH_FLD_CNT_SBC_LOOKUP_REPLAY_LEN = 4233; // 1 -const static uint64_t SH_FLD_CNT_SPEC_EOI = 4234; // 1 -const static uint64_t SH_FLD_CNT_SPEC_EOI_CACHE_HIT = 4235; // 1 -const static uint64_t SH_FLD_CNT_SPEC_EOI_CACHE_HIT_LEN = 4236; // 1 -const static uint64_t SH_FLD_CNT_SPEC_EOI_LEN = 4237; // 1 -const static uint64_t SH_FLD_CNT_TOO_MANY_ENTRIES = 4238; // 2 -const static uint64_t SH_FLD_CNT_TOO_MANY_ENTRIES_LEN = 4239; // 2 -const static uint64_t SH_FLD_CNT_TRIG_DROPPED = 4240; // 6 -const static uint64_t SH_FLD_CNT_TRIG_DROPPED_LEN = 4241; // 6 -const static uint64_t SH_FLD_CNT_TRIG_FROM_AIB = 4242; // 6 -const static uint64_t SH_FLD_CNT_TRIG_FROM_AIB_LEN = 4243; // 6 -const static uint64_t SH_FLD_CNT_TRIG_FWD_TO_EQC = 4244; // 6 -const static uint64_t SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN = 4245; // 6 -const static uint64_t SH_FLD_CNT_USE_L2_DIVIDER_EN = 4246; // 12 -const static uint64_t SH_FLD_CNT_VICTIM_IS_1ST_USABLE = 4247; // 2 -const static uint64_t SH_FLD_CNT_VICTIM_IS_1ST_USABLE_LEN = 4248; // 2 -const static uint64_t SH_FLD_CNT_VICTIM_IS_FIRST_USABLE = 4249; // 1 -const static uint64_t SH_FLD_CNT_VICTIM_IS_FIRST_USABLE_LEN = 4250; // 1 -const static uint64_t SH_FLD_CNT_VICTIM_IS_LRU = 4251; // 3 -const static uint64_t SH_FLD_CNT_VICTIM_IS_LRU_LEN = 4252; // 3 -const static uint64_t SH_FLD_CNT_VP = 4253; // 1 -const static uint64_t SH_FLD_CNT_VP_LEN = 4254; // 1 -const static uint64_t SH_FLD_CNT_WAKEUP = 4255; // 1 -const static uint64_t SH_FLD_CNT_WAKEUP_LEN = 4256; // 1 -const static uint64_t SH_FLD_COARSE_CAL_STEP_SIZE = 4257; // 8 -const static uint64_t SH_FLD_COARSE_CAL_STEP_SIZE_LEN = 4258; // 8 -const static uint64_t SH_FLD_COARSE_DIR_ENABLE = 4259; // 2 -const static uint64_t SH_FLD_COARSE_DIR_SECTORS = 4260; // 2 -const static uint64_t SH_FLD_COARSE_RD = 4261; // 8 -const static uint64_t SH_FLD_COFSM_ADDR_ERR = 4262; // 12 -const static uint64_t SH_FLD_COL4_BIT_MAP = 4263; // 8 -const static uint64_t SH_FLD_COL4_BIT_MAP_LEN = 4264; // 8 -const static uint64_t SH_FLD_COL5_BIT_MAP = 4265; // 8 -const static uint64_t SH_FLD_COL5_BIT_MAP_LEN = 4266; // 8 -const static uint64_t SH_FLD_COL6_BIT_MAP = 4267; // 8 -const static uint64_t SH_FLD_COL6_BIT_MAP_LEN = 4268; // 8 -const static uint64_t SH_FLD_COL7_BIT_MAP = 4269; // 8 -const static uint64_t SH_FLD_COL7_BIT_MAP_LEN = 4270; // 8 -const static uint64_t SH_FLD_COL8_BIT_MAP = 4271; // 8 -const static uint64_t SH_FLD_COL8_BIT_MAP_LEN = 4272; // 8 -const static uint64_t SH_FLD_COL9_BIT_MAP = 4273; // 8 -const static uint64_t SH_FLD_COL9_BIT_MAP_LEN = 4274; // 8 -const static uint64_t SH_FLD_COLLISION_MODES = 4275; // 4 -const static uint64_t SH_FLD_COLLISION_MODES_LEN = 4276; // 4 -const static uint64_t SH_FLD_COLLISON = 4277; // 1 -const static uint64_t SH_FLD_COMMAND_ADDRESS_TIMEOUT = 4278; // 10 -const static uint64_t SH_FLD_COMMAND_COMPLETE = 4279; // 1 -const static uint64_t SH_FLD_COMMAND_LIST_TIMEOUT = 4280; // 4 -const static uint64_t SH_FLD_COMMAND_LIST_TIMEOUT_SPEC = 4281; // 4 -const static uint64_t SH_FLD_COMMAND_PATTERN_TO_COUNT = 4282; // 8 -const static uint64_t SH_FLD_COMMAND_PATTERN_TO_COUNT_LEN = 4283; // 8 -const static uint64_t SH_FLD_COMMON_FREEZE_MODE = 4284; // 2 -const static uint64_t SH_FLD_COMM_ACK = 4285; // 12 -const static uint64_t SH_FLD_COMM_NACK = 4286; // 12 -const static uint64_t SH_FLD_COMM_RECV = 4287; // 12 -const static uint64_t SH_FLD_COMM_RECVD = 4288; // 12 -const static uint64_t SH_FLD_COMM_RECV_LEN = 4289; // 12 -const static uint64_t SH_FLD_COMM_SEND = 4290; // 12 -const static uint64_t SH_FLD_COMM_SEND_ACK = 4291; // 12 -const static uint64_t SH_FLD_COMM_SEND_LEN = 4292; // 12 -const static uint64_t SH_FLD_COMM_SEND_NACK = 4293; // 12 -const static uint64_t SH_FLD_COMPLETE = 4294; // 8 -const static uint64_t SH_FLD_COMPLETE_LEN = 4295; // 8 -const static uint64_t SH_FLD_COMPRESSED_RSP_ENA = 4296; // 6 -const static uint64_t SH_FLD_COND_STARTUP_TEST_FAIL = 4297; // 1 -const static uint64_t SH_FLD_CONFIG = 4298; // 1 -const static uint64_t SH_FLD_CONFIG1_RESERVED0 = 4299; // 3 -const static uint64_t SH_FLD_CONFIG1_RESERVED1 = 4300; // 15 -const static uint64_t SH_FLD_CONFIG1_RESERVED1_LEN = 4301; // 3 -const static uint64_t SH_FLD_CONFIG1_RESERVED2 = 4302; // 15 -const static uint64_t SH_FLD_CONFIG1_RESERVED2_LEN = 4303; // 3 -const static uint64_t SH_FLD_CONFIG_ADDR = 4304; // 84 -const static uint64_t SH_FLD_CONFIG_ADDR_LEN = 4305; // 84 -const static uint64_t SH_FLD_CONFIG_ADR_BAR_MODE = 4306; // 15 -const static uint64_t SH_FLD_CONFIG_ARMWF_ADD = 4307; // 12 -const static uint64_t SH_FLD_CONFIG_ARMWF_AND = 4308; // 12 -const static uint64_t SH_FLD_CONFIG_ARMWF_CAS_E = 4309; // 12 -const static uint64_t SH_FLD_CONFIG_ARMWF_CAS_IMAX_S = 4310; // 12 -const static uint64_t SH_FLD_CONFIG_ARMWF_CAS_IMAX_U = 4311; // 12 -const static uint64_t SH_FLD_CONFIG_ARMWF_CAS_IMIN_S = 4312; // 12 -const static uint64_t SH_FLD_CONFIG_ARMWF_CAS_IMIN_U = 4313; // 12 -const static uint64_t SH_FLD_CONFIG_ARMWF_CAS_U = 4314; // 12 -const static uint64_t SH_FLD_CONFIG_ARMWF_OR = 4315; // 12 -const static uint64_t SH_FLD_CONFIG_ARMWF_XOR = 4316; // 12 -const static uint64_t SH_FLD_CONFIG_ARMW_ADD = 4317; // 12 -const static uint64_t SH_FLD_CONFIG_ARMW_AND = 4318; // 12 -const static uint64_t SH_FLD_CONFIG_ARMW_CAS_IMAX_S = 4319; // 12 -const static uint64_t SH_FLD_CONFIG_ARMW_CAS_IMAX_U = 4320; // 12 -const static uint64_t SH_FLD_CONFIG_ARMW_CAS_IMIN_S = 4321; // 12 -const static uint64_t SH_FLD_CONFIG_ARMW_CAS_IMIN_U = 4322; // 12 -const static uint64_t SH_FLD_CONFIG_ARMW_OR = 4323; // 12 -const static uint64_t SH_FLD_CONFIG_ARMW_XOR = 4324; // 12 -const static uint64_t SH_FLD_CONFIG_BRAZOS = 4325; // 1 -const static uint64_t SH_FLD_CONFIG_BRAZOS_MODE = 4326; // 15 -const static uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN = 4327; // 12 -const static uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_LEN = 4328; // 12 -const static uint64_t SH_FLD_CONFIG_CL_DMA_INJ = 4329; // 12 -const static uint64_t SH_FLD_CONFIG_CL_DMA_W = 4330; // 12 -const static uint64_t SH_FLD_CONFIG_CL_DMA_W_HP = 4331; // 12 -const static uint64_t SH_FLD_CONFIG_DCACHE_MODE = 4332; // 12 -const static uint64_t SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL = 4333; // 12 -const static uint64_t SH_FLD_CONFIG_DISABLE_G = 4334; // 12 -const static uint64_t SH_FLD_CONFIG_DISABLE_INJECT = 4335; // 12 -const static uint64_t SH_FLD_CONFIG_DISABLE_LN = 4336; // 12 -const static uint64_t SH_FLD_CONFIG_DISABLE_NN_RN = 4337; // 12 -const static uint64_t SH_FLD_CONFIG_DISABLE_VG_NOT_SYS = 4338; // 12 -const static uint64_t SH_FLD_CONFIG_DMA_PR_W = 4339; // 12 -const static uint64_t SH_FLD_CONFIG_ENABLE = 4340; // 84 -const static uint64_t SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC = 4341; // 12 -const static uint64_t SH_FLD_CONFIG_ENABLE_PBUS = 4342; // 12 -const static uint64_t SH_FLD_CONFIG_ENABLE_SNARF_CPM = 4343; // 12 -const static uint64_t SH_FLD_CONFIG_EVAPORATE_BY_LCO = 4344; // 12 -const static uint64_t SH_FLD_CONFIG_GEN_HEAD_DELAY = 4345; // 3 -const static uint64_t SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN = 4346; // 3 -const static uint64_t SH_FLD_CONFIG_GRANULE = 4347; // 24 -const static uint64_t SH_FLD_CONFIG_INC_PRI_MASK = 4348; // 12 -const static uint64_t SH_FLD_CONFIG_INC_PRI_MASK_LEN = 4349; // 12 -const static uint64_t SH_FLD_CONFIG_L2L3NCU = 4350; // 12 -const static uint64_t SH_FLD_CONFIG_LEN = 4351; // 1 -const static uint64_t SH_FLD_CONFIG_MACH_CORRENAB = 4352; // 12 -const static uint64_t SH_FLD_CONFIG_MACH_INJECT_ENABLE1 = 4353; // 12 -const static uint64_t SH_FLD_CONFIG_MACH_INJECT_ENABLE2 = 4354; // 12 -const static uint64_t SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR = 4355; // 12 -const static uint64_t SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG = 4356; // 12 -const static uint64_t SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR = 4357; // 12 -const static uint64_t SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE = 4358; // 12 -const static uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA = 4359; // 12 -const static uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ = 4360; // 12 -const static uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_WRP = 4361; // 12 -const static uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_B = 4362; // 12 -const static uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_C = 4363; // 12 -const static uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM = 4364; // 12 -const static uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 4365; // 12 -const static uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_A = 4366; // 12 -const static uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_B = 4367; // 12 -const static uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_C = 4368; // 12 -const static uint64_t SH_FLD_CONFIG_MEMTYPE = 4369; // 24 -const static uint64_t SH_FLD_CONFIG_MEMTYPE_LEN = 4370; // 24 -const static uint64_t SH_FLD_CONFIG_MODE = 4371; // 24 -const static uint64_t SH_FLD_CONFIG_MODE_LEN = 4372; // 24 -const static uint64_t SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ = 4373; // 3 -const static uint64_t SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ = 4374; // 3 -const static uint64_t SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP = 4375; // 3 -const static uint64_t SH_FLD_CONFIG_MRBGP_MAX_LEVEL = 4376; // 3 -const static uint64_t SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN = 4377; // 3 -const static uint64_t SH_FLD_CONFIG_MRBGP_THRESH1 = 4378; // 3 -const static uint64_t SH_FLD_CONFIG_MRBGP_THRESH1_LEN = 4379; // 3 -const static uint64_t SH_FLD_CONFIG_MRBGP_THRESH2 = 4380; // 3 -const static uint64_t SH_FLD_CONFIG_MRBGP_THRESH2_LEN = 4381; // 3 -const static uint64_t SH_FLD_CONFIG_MRBGP_TRACK_ALL = 4382; // 12 -const static uint64_t SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ = 4383; // 3 -const static uint64_t SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ = 4384; // 3 -const static uint64_t SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP = 4385; // 3 -const static uint64_t SH_FLD_CONFIG_MRBSP_MAX_LEVEL = 4386; // 3 -const static uint64_t SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN = 4387; // 3 -const static uint64_t SH_FLD_CONFIG_MRBSP_THRESH1 = 4388; // 3 -const static uint64_t SH_FLD_CONFIG_MRBSP_THRESH1_LEN = 4389; // 3 -const static uint64_t SH_FLD_CONFIG_MRBSP_THRESH2 = 4390; // 3 -const static uint64_t SH_FLD_CONFIG_MRBSP_THRESH2_LEN = 4391; // 3 -const static uint64_t SH_FLD_CONFIG_MRBSP_TRACK_ALL = 4392; // 12 -const static uint64_t SH_FLD_CONFIG_NPU = 4393; // 12 -const static uint64_t SH_FLD_CONFIG_NX = 4394; // 12 -const static uint64_t SH_FLD_CONFIG_PARITY = 4395; // 43 -const static uint64_t SH_FLD_CONFIG_PCIE = 4396; // 12 -const static uint64_t SH_FLD_CONFIG_PCIE_LEN = 4397; // 12 -const static uint64_t SH_FLD_CONFIG_PRB0 = 4398; // 24 -const static uint64_t SH_FLD_CONFIG_PRB0_LEN = 4399; // 24 -const static uint64_t SH_FLD_CONFIG_PRB1 = 4400; // 24 -const static uint64_t SH_FLD_CONFIG_PRB1_LEN = 4401; // 24 -const static uint64_t SH_FLD_CONFIG_PREALLOC2_PRB0 = 4402; // 12 -const static uint64_t SH_FLD_CONFIG_PREALLOC2_PRB1 = 4403; // 12 -const static uint64_t SH_FLD_CONFIG_PREALLOC2_REQ0 = 4404; // 12 -const static uint64_t SH_FLD_CONFIG_PREALLOC2_REQ1 = 4405; // 12 -const static uint64_t SH_FLD_CONFIG_PREALLOC2_XATS = 4406; // 12 -const static uint64_t SH_FLD_CONFIG_PR_DMA_INJ = 4407; // 12 -const static uint64_t SH_FLD_CONFIG_PWR0 = 4408; // 24 -const static uint64_t SH_FLD_CONFIG_PWR0_LEN = 4409; // 24 -const static uint64_t SH_FLD_CONFIG_PWR1 = 4410; // 24 -const static uint64_t SH_FLD_CONFIG_PWR1_LEN = 4411; // 24 -const static uint64_t SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK = 4412; // 12 -const static uint64_t SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 4413; // 12 -const static uint64_t SH_FLD_CONFIG_REQ0 = 4414; // 24 -const static uint64_t SH_FLD_CONFIG_REQ0_LEN = 4415; // 24 -const static uint64_t SH_FLD_CONFIG_REQ1 = 4416; // 24 -const static uint64_t SH_FLD_CONFIG_REQ1_LEN = 4417; // 24 -const static uint64_t SH_FLD_CONFIG_RESERVED4 = 4418; // 12 -const static uint64_t SH_FLD_CONFIG_RSI_CORRENAB = 4419; // 12 -const static uint64_t SH_FLD_CONFIG_RSI_INJECT_ENABLE1 = 4420; // 12 -const static uint64_t SH_FLD_CONFIG_RSI_INJECT_ENABLE2 = 4421; // 12 -const static uint64_t SH_FLD_CONFIG_RXO_CORRENAB = 4422; // 12 -const static uint64_t SH_FLD_CONFIG_RXO_INJECT_ENABLE1 = 4423; // 12 -const static uint64_t SH_FLD_CONFIG_RXO_INJECT_ENABLE2 = 4424; // 12 -const static uint64_t SH_FLD_CONFIG_SIZE = 4425; // 24 -const static uint64_t SH_FLD_CONFIG_SIZE_LEN = 4426; // 24 -const static uint64_t SH_FLD_CONFIG_SKIP_G = 4427; // 12 -const static uint64_t SH_FLD_CONFIG_SYNC_WAIT = 4428; // 1 -const static uint64_t SH_FLD_CONFIG_SYNC_WAIT_LEN = 4429; // 1 -const static uint64_t SH_FLD_CONFIG_VAS = 4430; // 12 -const static uint64_t SH_FLD_CONFIG_XATS = 4431; // 24 -const static uint64_t SH_FLD_CONFIG_XATS_LEN = 4432; // 24 -const static uint64_t SH_FLD_CONFIRMED = 4433; // 64 -const static uint64_t SH_FLD_CONFLICT = 4434; // 1 -const static uint64_t SH_FLD_CONG = 4435; // 1 -const static uint64_t SH_FLD_CONG_LEN = 4436; // 1 -const static uint64_t SH_FLD_CONSEQ_PASS = 4437; // 8 -const static uint64_t SH_FLD_CONSEQ_PASS_LEN = 4438; // 8 -const static uint64_t SH_FLD_CONSUMED_BUF_COUNT = 4439; // 1 -const static uint64_t SH_FLD_CONSUMED_BUF_COUNT_LEN = 4440; // 1 -const static uint64_t SH_FLD_CONTENT = 4441; // 3 -const static uint64_t SH_FLD_CONTENT_LEN = 4442; // 3 -const static uint64_t SH_FLD_CONTINUOUS = 4443; // 2 -const static uint64_t SH_FLD_CONTROL = 4444; // 15 -const static uint64_t SH_FLD_CONTROL_ERR = 4445; // 24 -const static uint64_t SH_FLD_CONTROL_LEN = 4446; // 15 -const static uint64_t SH_FLD_CONTROL_N = 4447; // 2 -const static uint64_t SH_FLD_CONVERGED_END_COUNT = 4448; // 6 -const static uint64_t SH_FLD_CONVERGED_END_COUNT_LEN = 4449; // 6 -const static uint64_t SH_FLD_COPY_CKE_TO_SPARE_CKE = 4450; // 2 -const static uint64_t SH_FLD_COPY_LENGTH = 4451; // 2 -const static uint64_t SH_FLD_COPY_LENGTH_LEN = 4452; // 2 -const static uint64_t SH_FLD_CORE0_REQ_ACTIVE = 4453; // 12 -const static uint64_t SH_FLD_CORE1_REQ_ACTIVE = 4454; // 12 -const static uint64_t SH_FLD_COREID = 4455; // 1 -const static uint64_t SH_FLD_COREID_LEN = 4456; // 1 -const static uint64_t SH_FLD_CORES_ENABLED = 4457; // 1 -const static uint64_t SH_FLD_CORES_ENABLED_LEN = 4458; // 1 -const static uint64_t SH_FLD_CORE_CHECKSTOP = 4459; // 12 -const static uint64_t SH_FLD_CORE_CLK_SB_PULSE_MODE = 4460; // 6 -const static uint64_t SH_FLD_CORE_CLK_SB_PULSE_MODE_EN = 4461; // 6 -const static uint64_t SH_FLD_CORE_CLK_SB_PULSE_MODE_LEN = 4462; // 6 -const static uint64_t SH_FLD_CORE_CLK_SB_SPARE = 4463; // 6 -const static uint64_t SH_FLD_CORE_CLK_SB_STRENGTH = 4464; // 6 -const static uint64_t SH_FLD_CORE_CLK_SB_STRENGTH_LEN = 4465; // 6 -const static uint64_t SH_FLD_CORE_CLK_SW_RESCLK = 4466; // 6 -const static uint64_t SH_FLD_CORE_CLK_SW_RESCLK_LEN = 4467; // 6 -const static uint64_t SH_FLD_CORE_CLK_SW_SPARE = 4468; // 6 -const static uint64_t SH_FLD_CORE_CONFIG = 4469; // 2 -const static uint64_t SH_FLD_CORE_CONFIG_LEN = 4470; // 2 -const static uint64_t SH_FLD_CORE_EXT_INTR = 4471; // 1 -const static uint64_t SH_FLD_CORE_OR_SNP_REQ_ACTIVE = 4472; // 12 -const static uint64_t SH_FLD_CORE_RESET = 4473; // 1 -const static uint64_t SH_FLD_CORE_STEP = 4474; // 1 -const static uint64_t SH_FLD_CORE_STEP_SYNC_TX_ENABLE = 4475; // 1 -const static uint64_t SH_FLD_CORE_STEP_SYNC_TX_SYNC_DISABLE = 4476; // 1 -const static uint64_t SH_FLD_CORE_STEP_SYNC_TX_TRIGGER = 4477; // 1 -const static uint64_t SH_FLD_CORR_DIS_BR = 4478; // 3 -const static uint64_t SH_FLD_CORR_DIS_IR = 4479; // 3 -const static uint64_t SH_FLD_CORR_DIS_OR = 4480; // 3 -const static uint64_t SH_FLD_CORR_DIS_PR = 4481; // 3 -const static uint64_t SH_FLD_CORR_DIS_PT = 4482; // 3 -const static uint64_t SH_FLD_CORR_ERR = 4483; // 1 -const static uint64_t SH_FLD_COUNT = 4484; // 44 -const static uint64_t SH_FLD_COUNTER = 4485; // 43 -const static uint64_t SH_FLD_COUNTER0 = 4486; // 16 -const static uint64_t SH_FLD_COUNTER0_LEN = 4487; // 16 -const static uint64_t SH_FLD_COUNTER1 = 4488; // 16 -const static uint64_t SH_FLD_COUNTER1_LEN = 4489; // 16 -const static uint64_t SH_FLD_COUNTER2 = 4490; // 16 -const static uint64_t SH_FLD_COUNTER2_LEN = 4491; // 16 -const static uint64_t SH_FLD_COUNTER3 = 4492; // 16 -const static uint64_t SH_FLD_COUNTER3_LEN = 4493; // 16 -const static uint64_t SH_FLD_COUNTERA_0 = 4494; // 2 -const static uint64_t SH_FLD_COUNTERA_0_LEN = 4495; // 2 -const static uint64_t SH_FLD_COUNTERA_1 = 4496; // 2 -const static uint64_t SH_FLD_COUNTERA_1_LEN = 4497; // 2 -const static uint64_t SH_FLD_COUNTERA_2 = 4498; // 2 -const static uint64_t SH_FLD_COUNTERA_2_LEN = 4499; // 2 -const static uint64_t SH_FLD_COUNTERA_3 = 4500; // 2 -const static uint64_t SH_FLD_COUNTERA_3_LEN = 4501; // 2 -const static uint64_t SH_FLD_COUNTERB_0 = 4502; // 2 -const static uint64_t SH_FLD_COUNTERB_0_LEN = 4503; // 2 -const static uint64_t SH_FLD_COUNTERB_1 = 4504; // 2 -const static uint64_t SH_FLD_COUNTERB_1_LEN = 4505; // 2 -const static uint64_t SH_FLD_COUNTERB_2 = 4506; // 2 -const static uint64_t SH_FLD_COUNTERB_2_LEN = 4507; // 2 -const static uint64_t SH_FLD_COUNTERB_3 = 4508; // 2 -const static uint64_t SH_FLD_COUNTERB_3_LEN = 4509; // 2 -const static uint64_t SH_FLD_COUNTER_LEN = 4510; // 43 -const static uint64_t SH_FLD_COUNTER_LOAD_FLAG = 4511; // 2 -const static uint64_t SH_FLD_COUNTER_LOAD_VALUE = 4512; // 2 -const static uint64_t SH_FLD_COUNTER_LOAD_VALUE_LEN = 4513; // 2 -const static uint64_t SH_FLD_COUNTER_VALUE = 4514; // 1 -const static uint64_t SH_FLD_COUNTER_VALUE_LEN = 4515; // 1 -const static uint64_t SH_FLD_COUNT_0_47 = 4516; // 7 -const static uint64_t SH_FLD_COUNT_0_47_LEN = 4517; // 7 -const static uint64_t SH_FLD_COUNT_47 = 4518; // 1 -const static uint64_t SH_FLD_COUNT_47_LEN = 4519; // 1 -const static uint64_t SH_FLD_COUNT_LEN = 4520; // 44 -const static uint64_t SH_FLD_COUNT_STATE_MASK = 4521; // 43 -const static uint64_t SH_FLD_COURSE_DIR_FLUSH_FAILED = 4522; // 2 -const static uint64_t SH_FLD_CO_MACHINE_HANG_ERR = 4523; // 12 -const static uint64_t SH_FLD_CO_PROT_ERR_CHK_DIS = 4524; // 1 -const static uint64_t SH_FLD_CO_TIMEOUT_CHK_DIS = 4525; // 1 -const static uint64_t SH_FLD_CO_UNSOLICITED_CRESP_ERR = 4526; // 12 -const static uint64_t SH_FLD_CO_UNSOLICITED_CRESP_ERR_LEN = 4527; // 12 -const static uint64_t SH_FLD_CP = 4528; // 2 -const static uint64_t SH_FLD_CPG = 4529; // 8 -const static uint64_t SH_FLD_CPHA = 4530; // 1 -const static uint64_t SH_FLD_CPISEL = 4531; // 20 -const static uint64_t SH_FLD_CPISEL_LEN = 4532; // 20 -const static uint64_t SH_FLD_CPI_TYPE = 4533; // 12 -const static uint64_t SH_FLD_CPI_TYPE_LEN = 4534; // 12 -const static uint64_t SH_FLD_CPLITE = 4535; // 2 -const static uint64_t SH_FLD_CPLITE_LEN = 4536; // 2 -const static uint64_t SH_FLD_CPLTMASK0 = 4537; // 43 -const static uint64_t SH_FLD_CPLTMASK0_LEN = 4538; // 43 -const static uint64_t SH_FLD_CPM_CAL_SET = 4539; // 43 -const static uint64_t SH_FLD_CPOL = 4540; // 1 -const static uint64_t SH_FLD_CPS = 4541; // 1 -const static uint64_t SH_FLD_CPS_LEN = 4542; // 1 -const static uint64_t SH_FLD_CP_LEN = 4543; // 2 -const static uint64_t SH_FLD_CP_RETRY_THRESH = 4544; // 4 -const static uint64_t SH_FLD_CP_RETRY_THRESH_LEN = 4545; // 4 -const static uint64_t SH_FLD_CQ_CERR_BITS = 4546; // 1 -const static uint64_t SH_FLD_CQ_CERR_BITS_LEN = 4547; // 1 -const static uint64_t SH_FLD_CQ_CERR_RESET = 4548; // 1 -const static uint64_t SH_FLD_CQ_DRAIN_THRESHOLD = 4549; // 1 -const static uint64_t SH_FLD_CQ_DRAIN_THRESHOLD_LEN = 4550; // 1 -const static uint64_t SH_FLD_CQ_ECC_CE_ERROR = 4551; // 2 -const static uint64_t SH_FLD_CQ_ECC_SUE_ERROR = 4552; // 2 -const static uint64_t SH_FLD_CQ_ECC_UE_ERROR = 4553; // 2 -const static uint64_t SH_FLD_CQ_FILL_THRESHOLD = 4554; // 1 -const static uint64_t SH_FLD_CQ_FILL_THRESHOLD_LEN = 4555; // 1 -const static uint64_t SH_FLD_CQ_LFSR_RESEED_EN = 4556; // 1 -const static uint64_t SH_FLD_CQ_LOGIC_HW_ERROR = 4557; // 2 -const static uint64_t SH_FLD_CQ_PB_LINK_ABORT = 4558; // 2 -const static uint64_t SH_FLD_CQ_PB_MASTER_FSM_HANG = 4559; // 2 -const static uint64_t SH_FLD_CQ_PB_OB_CE_ERROR = 4560; // 2 -const static uint64_t SH_FLD_CQ_PB_OB_UE_ERROR = 4561; // 2 -const static uint64_t SH_FLD_CQ_PB_PARITY_ERROR = 4562; // 2 -const static uint64_t SH_FLD_CQ_PB_RD_ADDR_ERROR = 4563; // 2 -const static uint64_t SH_FLD_CQ_PB_RD_LINK_ERROR = 4564; // 2 -const static uint64_t SH_FLD_CQ_PB_WR_ADDR_ERROR = 4565; // 2 -const static uint64_t SH_FLD_CQ_PB_WR_LINK_ERROR = 4566; // 2 -const static uint64_t SH_FLD_CQ_READ_RTY_RATIO = 4567; // 1 -const static uint64_t SH_FLD_CQ_READ_RTY_RATIO_LEN = 4568; // 1 -const static uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_HI = 4569; // 1 -const static uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_HI_LEN = 4570; // 1 -const static uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_LO = 4571; // 1 -const static uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_LO_LEN = 4572; // 1 -const static uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_01 = 4573; // 1 -const static uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_01_LEN = 4574; // 1 -const static uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_23 = 4575; // 1 -const static uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_23_LEN = 4576; // 1 -const static uint64_t SH_FLD_CR0_ATAG_PERR = 4577; // 1 -const static uint64_t SH_FLD_CR0_TTAG_PERR = 4578; // 1 -const static uint64_t SH_FLD_CR1_ATAG_PERR = 4579; // 1 -const static uint64_t SH_FLD_CR1_TTAG_PERR = 4580; // 1 -const static uint64_t SH_FLD_CR2_ATAG_PERR = 4581; // 1 -const static uint64_t SH_FLD_CR2_TTAG_PERR = 4582; // 1 -const static uint64_t SH_FLD_CR3_ATAG_PERR = 4583; // 1 -const static uint64_t SH_FLD_CR3_TTAG_PERR = 4584; // 1 -const static uint64_t SH_FLD_CRB_ECC_SUE = 4585; // 1 -const static uint64_t SH_FLD_CRB_ECC_UE = 4586; // 1 -const static uint64_t SH_FLD_CRB_READS_ENBL = 4587; // 1 -const static uint64_t SH_FLD_CRB_READS_HALTED = 4588; // 1 -const static uint64_t SH_FLD_CRC_MODE = 4589; // 2 -const static uint64_t SH_FLD_CRD_REQUEST = 4590; // 1 -const static uint64_t SH_FLD_CREDIT_CUR = 4591; // 36 -const static uint64_t SH_FLD_CREDIT_CUR_LEN = 4592; // 36 -const static uint64_t SH_FLD_CREDIT_MAX = 4593; // 36 -const static uint64_t SH_FLD_CREDIT_MAX_LEN = 4594; // 36 -const static uint64_t SH_FLD_CREDIT_RCV_CUR = 4595; // 12 -const static uint64_t SH_FLD_CREDIT_RCV_CUR_LEN = 4596; // 12 -const static uint64_t SH_FLD_CREDIT_RCV_UPD = 4597; // 12 -const static uint64_t SH_FLD_CREDIT_SEND = 4598; // 36 -const static uint64_t SH_FLD_CREDIT_SEND_LEN = 4599; // 36 -const static uint64_t SH_FLD_CREDIT_UPD = 4600; // 36 -const static uint64_t SH_FLD_CREDIT_UPDATE_PENDING = 4601; // 6 -const static uint64_t SH_FLD_CREQ_AE_ALWAYS = 4602; // 6 -const static uint64_t SH_FLD_CREQ_BE_128 = 4603; // 6 -const static uint64_t SH_FLD_CRESP_0_4 = 4604; // 1 -const static uint64_t SH_FLD_CRESP_0_4_LEN = 4605; // 1 -const static uint64_t SH_FLD_CRESP_ATAG_P_ERR = 4606; // 12 -const static uint64_t SH_FLD_CRESP_ATAG_P_ERR_LEN = 4607; // 12 -const static uint64_t SH_FLD_CRESP_HANG = 4608; // 1 -const static uint64_t SH_FLD_CRESP_TTAG_P_ERR = 4609; // 12 -const static uint64_t SH_FLD_CRESP_TTAG_P_ERR_LEN = 4610; // 12 -const static uint64_t SH_FLD_CRITICAL_INTERRUPT = 4611; // 1 -const static uint64_t SH_FLD_CR_ATAG_PAR = 4612; // 1 -const static uint64_t SH_FLD_CR_TTAG_PAR = 4613; // 1 -const static uint64_t SH_FLD_CS0_INIT_CAL_VALUE = 4614; // 8 -const static uint64_t SH_FLD_CS1_INIT_CAL_VALUE = 4615; // 8 -const static uint64_t SH_FLD_CS2_INIT_CAL_VALUE = 4616; // 8 -const static uint64_t SH_FLD_CS3_INIT_CAL_VALUE = 4617; // 8 -const static uint64_t SH_FLD_CS4_INIT_CAL_VALUE = 4618; // 8 -const static uint64_t SH_FLD_CS5_INIT_CAL_VALUE = 4619; // 8 -const static uint64_t SH_FLD_CS6_INIT_CAL_VALUE = 4620; // 8 -const static uint64_t SH_FLD_CS7_INIT_CAL_VALUE = 4621; // 8 -const static uint64_t SH_FLD_CSEL = 4622; // 10 -const static uint64_t SH_FLD_CSEL_LEN = 4623; // 10 -const static uint64_t SH_FLD_CS_CHIP_ID_2N_MODE = 4624; // 2 -const static uint64_t SH_FLD_CTLE_GAIN_MAX = 4625; // 6 -const static uint64_t SH_FLD_CTLE_GAIN_MAX_LEN = 4626; // 6 -const static uint64_t SH_FLD_CTLE_UPDATE_MODE = 4627; // 6 -const static uint64_t SH_FLD_CTLR_HP_THRESH = 4628; // 3 -const static uint64_t SH_FLD_CTLR_HP_THRESH_LEN = 4629; // 3 -const static uint64_t SH_FLD_CTLW_HP_THRESH = 4630; // 3 -const static uint64_t SH_FLD_CTLW_HP_THRESH_LEN = 4631; // 3 -const static uint64_t SH_FLD_CTL_ADDR_ERR_ESR = 4632; // 1 -const static uint64_t SH_FLD_CTL_ARRAY_CE = 4633; // 1 -const static uint64_t SH_FLD_CTL_ARRAY_UE = 4634; // 1 -const static uint64_t SH_FLD_CTL_FWD_PROGRESS_ERR = 4635; // 1 -const static uint64_t SH_FLD_CTL_LOGIC_ERR = 4636; // 1 -const static uint64_t SH_FLD_CTL_MMIO_ST_DATA_UE = 4637; // 1 -const static uint64_t SH_FLD_CTL_NVL_CFG_ERR = 4638; // 1 -const static uint64_t SH_FLD_CTL_NVL_FATAL_ERR = 4639; // 1 -const static uint64_t SH_FLD_CTL_PBUS_CONFIG_ERR = 4640; // 1 -const static uint64_t SH_FLD_CTL_PBUS_FATAL_ERR = 4641; // 1 -const static uint64_t SH_FLD_CTL_PBUS_PERR = 4642; // 1 -const static uint64_t SH_FLD_CTL_PBUS_RECOV_ERR = 4643; // 1 -const static uint64_t SH_FLD_CTL_PEST_DIS = 4644; // 1 -const static uint64_t SH_FLD_CTL_RING_ERR = 4645; // 1 -const static uint64_t SH_FLD_CTL_SM_0 = 4646; // 6 -const static uint64_t SH_FLD_CTL_SM_1 = 4647; // 6 -const static uint64_t SH_FLD_CTL_SM_2 = 4648; // 6 -const static uint64_t SH_FLD_CTL_SM_3 = 4649; // 6 -const static uint64_t SH_FLD_CTL_SM_4 = 4650; // 6 -const static uint64_t SH_FLD_CTL_SM_5 = 4651; // 6 -const static uint64_t SH_FLD_CTL_SM_6 = 4652; // 6 -const static uint64_t SH_FLD_CTL_SM_7 = 4653; // 6 -const static uint64_t SH_FLD_CTL_TICK = 4654; // 12 -const static uint64_t SH_FLD_CTL_TICK_LEN = 4655; // 12 -const static uint64_t SH_FLD_CTL_TRACE_EN = 4656; // 1 -const static uint64_t SH_FLD_CTL_TRACE_SEL = 4657; // 1 -const static uint64_t SH_FLD_CTRLR_PERR_ESR = 4658; // 1 -const static uint64_t SH_FLD_CTRL_BUSY = 4659; // 1 -const static uint64_t SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC = 4660; // 43 -const static uint64_t SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC = 4661; // 43 -const static uint64_t SH_FLD_CTRL_CC_DCTEST_DC = 4662; // 43 -const static uint64_t SH_FLD_CTRL_CC_FLUSHMODE_INH_DC = 4663; // 43 -const static uint64_t SH_FLD_CTRL_CC_FORCE_ALIGN_DC = 4664; // 43 -const static uint64_t SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC = 4665; // 43 -const static uint64_t SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC = 4666; // 43 -const static uint64_t SH_FLD_CTRL_CC_OTP_PRGMODE_DC = 4667; // 43 -const static uint64_t SH_FLD_CTRL_CC_PIN_LBIST_DC = 4668; // 43 -const static uint64_t SH_FLD_CTRL_CC_SCAN_PROTECT_DC = 4669; // 43 -const static uint64_t SH_FLD_CTRL_CC_SDIS_DC_N = 4670; // 43 -const static uint64_t SH_FLD_CTRL_CC_SSS_CALIBRATE_DC = 4671; // 43 -const static uint64_t SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC = 4672; // 43 -const static uint64_t SH_FLD_CTRL_MISC_CLKDIV_SEL_DC = 4673; // 43 -const static uint64_t SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN = 4674; // 43 -const static uint64_t SH_FLD_CTRL_MISC_PROBE0_SEL_DC = 4675; // 43 -const static uint64_t SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN = 4676; // 43 -const static uint64_t SH_FLD_CTRL_MISC_PROBE1_SEL_DC = 4677; // 43 -const static uint64_t SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN = 4678; // 43 -const static uint64_t SH_FLD_CTRL_MISC_PROBE2_SEL_DC = 4679; // 43 -const static uint64_t SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN = 4680; // 43 -const static uint64_t SH_FLD_CTRL_MISC_PROBE3_SEL_DC = 4681; // 43 -const static uint64_t SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN = 4682; // 43 -const static uint64_t SH_FLD_CTRL_PARITY = 4683; // 43 -const static uint64_t SH_FLD_CT_COMPARE_VECTOR = 4684; // 2 -const static uint64_t SH_FLD_CT_COMPARE_VECTOR_LEN = 4685; // 2 -const static uint64_t SH_FLD_CURRENT_OPCG_MODE = 4686; // 43 -const static uint64_t SH_FLD_CURRENT_OPCG_MODE_LEN = 4687; // 43 -const static uint64_t SH_FLD_CUR_RD_ADDR = 4688; // 6 -const static uint64_t SH_FLD_CUR_RD_ADDR_LEN = 4689; // 6 -const static uint64_t SH_FLD_CUSTOM_INIT_WRITE = 4690; // 8 -const static uint64_t SH_FLD_CUSTOM_RD = 4691; // 8 -const static uint64_t SH_FLD_CUSTOM_WR = 4692; // 8 -const static uint64_t SH_FLD_CW_MIRROR = 4693; // 8 -const static uint64_t SH_FLD_CW_TYPE = 4694; // 12 -const static uint64_t SH_FLD_CW_TYPE_LEN = 4695; // 12 -const static uint64_t SH_FLD_CYCLECNT = 4696; // 3 -const static uint64_t SH_FLD_CYCLECNT_LEN = 4697; // 3 -const static uint64_t SH_FLD_CYCLES = 4698; // 12 -const static uint64_t SH_FLD_CYCLES_LEN = 4699; // 12 -const static uint64_t SH_FLD_CYCLE_COUNT = 4700; // 24 -const static uint64_t SH_FLD_CYCLE_COUNT_LEN = 4701; // 24 -const static uint64_t SH_FLD_C_ERR_RPT_HOLD_DATA = 4702; // 2 -const static uint64_t SH_FLD_C_ERR_RPT_HOLD_DATA_LEN = 4703; // 2 -const static uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT = 4704; // 4 -const static uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT_LEN = 4705; // 4 -const static uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT = 4706; // 4 -const static uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT_LEN = 4707; // 4 -const static uint64_t SH_FLD_DACTEST_HLMT = 4708; // 6 -const static uint64_t SH_FLD_DACTEST_HLMT_LEN = 4709; // 6 -const static uint64_t SH_FLD_DACTEST_LLMT = 4710; // 6 -const static uint64_t SH_FLD_DACTEST_LLMT_LEN = 4711; // 6 -const static uint64_t SH_FLD_DACTEST_RESET = 4712; // 6 -const static uint64_t SH_FLD_DACTEST_START = 4713; // 6 -const static uint64_t SH_FLD_DAC_BO_CFG = 4714; // 6 -const static uint64_t SH_FLD_DAC_BO_CFG_LEN = 4715; // 6 -const static uint64_t SH_FLD_DAT0 = 4716; // 1 -const static uint64_t SH_FLD_DAT0_LEN = 4717; // 1 -const static uint64_t SH_FLD_DAT1 = 4718; // 1 -const static uint64_t SH_FLD_DAT1_LEN = 4719; // 1 -const static uint64_t SH_FLD_DATA = 4720; // 201 -const static uint64_t SH_FLD_DATA0 = 4721; // 6 -const static uint64_t SH_FLD_DATA0_LEN = 4722; // 6 -const static uint64_t SH_FLD_DATA1 = 4723; // 6 -const static uint64_t SH_FLD_DATA1_LEN = 4724; // 6 -const static uint64_t SH_FLD_DATA2 = 4725; // 6 -const static uint64_t SH_FLD_DATA2_LEN = 4726; // 6 -const static uint64_t SH_FLD_DATA_0_63 = 4727; // 2 -const static uint64_t SH_FLD_DATA_0_63_LEN = 4728; // 2 -const static uint64_t SH_FLD_DATA_64_79 = 4729; // 2 -const static uint64_t SH_FLD_DATA_64_79_LEN = 4730; // 2 -const static uint64_t SH_FLD_DATA_ARB_LFSR_CONFIG = 4731; // 1 -const static uint64_t SH_FLD_DATA_ARB_LFSR_CONFIG_LEN = 4732; // 1 -const static uint64_t SH_FLD_DATA_BUFFER = 4733; // 43 -const static uint64_t SH_FLD_DATA_COMPARE_BURST_SEL = 4734; // 2 -const static uint64_t SH_FLD_DATA_COMPARE_BURST_SEL_LEN = 4735; // 2 -const static uint64_t SH_FLD_DATA_DLY = 4736; // 1 -const static uint64_t SH_FLD_DATA_DLY_LEN = 4737; // 1 -const static uint64_t SH_FLD_DATA_HANG_DETECTED = 4738; // 2 -const static uint64_t SH_FLD_DATA_HANG_POLL_SCALE = 4739; // 2 -const static uint64_t SH_FLD_DATA_HANG_POLL_SCALE_LEN = 4740; // 2 -const static uint64_t SH_FLD_DATA_LEN = 4741; // 201 -const static uint64_t SH_FLD_DATA_MUX4_1MODE = 4742; // 8 -const static uint64_t SH_FLD_DATA_PARITY_ERR = 4743; // 4 -const static uint64_t SH_FLD_DATA_PIPE_CLR_ON_READ_MODE = 4744; // 6 -const static uint64_t SH_FLD_DATA_POISON_SUE_ENA = 4745; // 6 -const static uint64_t SH_FLD_DATA_POLL_PULSE_DIV = 4746; // 12 -const static uint64_t SH_FLD_DATA_POLL_PULSE_DIV_LEN = 4747; // 12 -const static uint64_t SH_FLD_DATA_REG0 = 4748; // 8 -const static uint64_t SH_FLD_DATA_REG0_LEN = 4749; // 8 -const static uint64_t SH_FLD_DATA_REG1 = 4750; // 8 -const static uint64_t SH_FLD_DATA_REG1_LEN = 4751; // 8 -const static uint64_t SH_FLD_DATA_REG_0_31 = 4752; // 1 -const static uint64_t SH_FLD_DATA_REG_0_31_LEN = 4753; // 1 -const static uint64_t SH_FLD_DATA_REQUEST_0 = 4754; // 2 -const static uint64_t SH_FLD_DATA_REQUEST_1 = 4755; // 2 -const static uint64_t SH_FLD_DATA_REQUEST_2 = 4756; // 2 -const static uint64_t SH_FLD_DATA_REQUEST_3 = 4757; // 2 -const static uint64_t SH_FLD_DATA_RTAG_P_ERR = 4758; // 12 -const static uint64_t SH_FLD_DATA_V_LT = 4759; // 43 -const static uint64_t SH_FLD_DAT_ARR_ECC_CORR_ENA = 4760; // 6 -const static uint64_t SH_FLD_DAT_ARR_ECC_SUE_ENA = 4761; // 6 -const static uint64_t SH_FLD_DAT_BUFFER_PAR_ERR = 4762; // 4 -const static uint64_t SH_FLD_DAT_CREG_PERR = 4763; // 1 -const static uint64_t SH_FLD_DAT_DATA_BE_CE = 4764; // 1 -const static uint64_t SH_FLD_DAT_DATA_BE_CE_OVERTHRESH = 4765; // 1 -const static uint64_t SH_FLD_DAT_DATA_BE_PERR = 4766; // 1 -const static uint64_t SH_FLD_DAT_DATA_BE_UE = 4767; // 1 -const static uint64_t SH_FLD_DAT_LOGIC_ERR = 4768; // 1 -const static uint64_t SH_FLD_DAT_RTAG_PERR = 4769; // 1 -const static uint64_t SH_FLD_DAT_STATE_PERR = 4770; // 1 -const static uint64_t SH_FLD_DBG_BUS_BIT = 4771; // 8 -const static uint64_t SH_FLD_DBG_CC_ERROR = 4772; // 1 -const static uint64_t SH_FLD_DBG_CHIPLET_IS_ALIGNED = 4773; // 1 -const static uint64_t SH_FLD_DBG_CMD = 4774; // 1 -const static uint64_t SH_FLD_DBG_CMD_LEN = 4775; // 1 -const static uint64_t SH_FLD_DBG_CURRENT_OPCG_MODE = 4776; // 1 -const static uint64_t SH_FLD_DBG_CURRENT_OPCG_MODE_LEN = 4777; // 1 -const static uint64_t SH_FLD_DBG_HALT = 4778; // 1 -const static uint64_t SH_FLD_DBG_LAST_OPCG_MODE = 4779; // 1 -const static uint64_t SH_FLD_DBG_LAST_OPCG_MODE_LEN = 4780; // 1 -const static uint64_t SH_FLD_DBG_OPCG_IP = 4781; // 1 -const static uint64_t SH_FLD_DBG_PARANOIA_TEST_ENABLE_CHANGE = 4782; // 1 -const static uint64_t SH_FLD_DBG_PARANOIA_VITL_CLKOFF_CHANGE = 4783; // 1 -const static uint64_t SH_FLD_DBG_PARITY_ERROR = 4784; // 1 -const static uint64_t SH_FLD_DBG_PCB_ERROR = 4785; // 1 -const static uint64_t SH_FLD_DBG_PCB_IDLE = 4786; // 1 -const static uint64_t SH_FLD_DBG_PCB_REQUEST_SINCE_RESET = 4787; // 1 -const static uint64_t SH_FLD_DBG_PROTOCOL_ERROR = 4788; // 1 -const static uint64_t SH_FLD_DBG_REQ = 4789; // 1 -const static uint64_t SH_FLD_DBG_RESET_EP = 4790; // 1 -const static uint64_t SH_FLD_DBG_SECURITY_DEBUG_MODE = 4791; // 1 -const static uint64_t SH_FLD_DBG_SEL_IN = 4792; // 8 -const static uint64_t SH_FLD_DBG_SEL_PWCTL_DEBUG = 4793; // 8 -const static uint64_t SH_FLD_DBG_SEL_PWSEQ0_DEBUG_0 = 4794; // 8 -const static uint64_t SH_FLD_DBG_SEL_PWSEQ0_DEBUG_1 = 4795; // 8 -const static uint64_t SH_FLD_DBG_SEL_PWSEQ1_DEBUG_0 = 4796; // 8 -const static uint64_t SH_FLD_DBG_SEL_PWSEQ1_DEBUG_1 = 4797; // 8 -const static uint64_t SH_FLD_DBG_SEL_PWSEQ2_DEBUG_0 = 4798; // 8 -const static uint64_t SH_FLD_DBG_SEL_PWSEQ2_DEBUG_1 = 4799; // 8 -const static uint64_t SH_FLD_DBG_SEL_PWSEQ3_DEBUG_0 = 4800; // 8 -const static uint64_t SH_FLD_DBG_SEL_PWSEQ3_DEBUG_1 = 4801; // 8 -const static uint64_t SH_FLD_DBG_SEL_PWSEQ4_DEBUG_0 = 4802; // 8 -const static uint64_t SH_FLD_DBG_SEL_PWSEQ4_DEBUG_1 = 4803; // 8 -const static uint64_t SH_FLD_DBG_SEL_PWSEQ5_DEBUG_0 = 4804; // 8 -const static uint64_t SH_FLD_DBG_SEL_PWSEQ5_DEBUG_1 = 4805; // 8 -const static uint64_t SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_0 = 4806; // 8 -const static uint64_t SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_1 = 4807; // 8 -const static uint64_t SH_FLD_DBG_SEL_WDF = 4808; // 8 -const static uint64_t SH_FLD_DBG_SEL_WDFMGR_DEBUG = 4809; // 8 -const static uint64_t SH_FLD_DBG_SEL_WDFRD_DEBUG_0 = 4810; // 8 -const static uint64_t SH_FLD_DBG_SEL_WDFRD_DEBUG_1 = 4811; // 8 -const static uint64_t SH_FLD_DBG_SEL_WDFWR_DEBUG_0 = 4812; // 8 -const static uint64_t SH_FLD_DBG_SEL_WDFWR_DEBUG_1 = 4813; // 8 -const static uint64_t SH_FLD_DBG_STATE = 4814; // 1 -const static uint64_t SH_FLD_DBG_STATE_LEN = 4815; // 1 -const static uint64_t SH_FLD_DBG_TEST_ENABLE = 4816; // 1 -const static uint64_t SH_FLD_DBG_TP_TPFSI_ACK = 4817; // 1 -const static uint64_t SH_FLD_DBG_UNCONDITIONAL_EVENT = 4818; // 1 -const static uint64_t SH_FLD_DBG_VITL_CLKOFF = 4819; // 1 -const static uint64_t SH_FLD_DCACHE_ERR = 4820; // 4 -const static uint64_t SH_FLD_DCACHE_TAG_ADDR = 4821; // 4 -const static uint64_t SH_FLD_DCACHE_TAG_ADDR_LEN = 4822; // 4 -const static uint64_t SH_FLD_DCLKSEL = 4823; // 6 -const static uint64_t SH_FLD_DCLKSEL_LEN = 4824; // 6 -const static uint64_t SH_FLD_DCOMP_ENABLE = 4825; // 1 -const static uint64_t SH_FLD_DCOMP_ENGINE_BUSY = 4826; // 1 -const static uint64_t SH_FLD_DCOMP_ERR = 4827; // 1 -const static uint64_t SH_FLD_DCO_DECR = 4828; // 6 -const static uint64_t SH_FLD_DCO_INCR = 4829; // 6 -const static uint64_t SH_FLD_DCO_OVERRIDE = 4830; // 6 -const static uint64_t SH_FLD_DCU_RNW = 4831; // 1 -const static uint64_t SH_FLD_DCU_TIMEOUT_ERROR = 4832; // 1 -const static uint64_t SH_FLD_DC_ENABLE_CM_COARSE_CAL = 4833; // 6 -const static uint64_t SH_FLD_DC_ENABLE_CM_FINE_CAL = 4834; // 6 -const static uint64_t SH_FLD_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 4835; // 6 -const static uint64_t SH_FLD_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 4836; // 6 -const static uint64_t SH_FLD_DC_ENABLE_DAC_H1_CAL = 4837; // 4 -const static uint64_t SH_FLD_DC_ENABLE_DAC_H1_TO_A_CAL = 4838; // 4 -const static uint64_t SH_FLD_DC_ENABLE_INTEG_LATCH_OFFSET_CAL = 4839; // 6 -const static uint64_t SH_FLD_DD2_FIX_DIS = 4840; // 8 -const static uint64_t SH_FLD_DDC_CFG = 4841; // 120 -const static uint64_t SH_FLD_DDC_CFG_LEN = 4842; // 120 -const static uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_SM = 4843; // 72 -const static uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN = 4844; // 72 -const static uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP = 4845; // 72 -const static uint64_t SH_FLD_DDR4_CMD_SIG_REDUCTION = 4846; // 8 -const static uint64_t SH_FLD_DDR4_IPW_LOOP_DIS = 4847; // 8 -const static uint64_t SH_FLD_DDR4_LATENCY_SW = 4848; // 8 -const static uint64_t SH_FLD_DDR4_MRS_CMD_DQ_EN = 4849; // 8 -const static uint64_t SH_FLD_DDR4_VLEVEL_BANK_GROUP = 4850; // 8 -const static uint64_t SH_FLD_DDR_ACTN = 4851; // 64 -const static uint64_t SH_FLD_DDR_ADDRESS = 4852; // 8 -const static uint64_t SH_FLD_DDR_ADDRESS_0 = 4853; // 2 -const static uint64_t SH_FLD_DDR_ADDRESS_0_13 = 4854; // 62 -const static uint64_t SH_FLD_DDR_ADDRESS_0_13_LEN = 4855; // 62 -const static uint64_t SH_FLD_DDR_ADDRESS_0_LEN = 4856; // 2 -const static uint64_t SH_FLD_DDR_ADDRESS_14 = 4857; // 62 -const static uint64_t SH_FLD_DDR_ADDRESS_15 = 4858; // 62 -const static uint64_t SH_FLD_DDR_ADDRESS_16 = 4859; // 62 -const static uint64_t SH_FLD_DDR_ADDRESS_17 = 4860; // 62 -const static uint64_t SH_FLD_DDR_BANK_0_1 = 4861; // 64 -const static uint64_t SH_FLD_DDR_BANK_0_1_LEN = 4862; // 64 -const static uint64_t SH_FLD_DDR_BANK_2 = 4863; // 64 -const static uint64_t SH_FLD_DDR_BANK_GROUP_0 = 4864; // 64 -const static uint64_t SH_FLD_DDR_BANK_GROUP_1 = 4865; // 64 -const static uint64_t SH_FLD_DDR_CALIBRATION_ENABLE = 4866; // 64 -const static uint64_t SH_FLD_DDR_CAL_RANK = 4867; // 64 -const static uint64_t SH_FLD_DDR_CAL_RANK_LEN = 4868; // 64 -const static uint64_t SH_FLD_DDR_CAL_RESET_TIMEOUT = 4869; // 16 -const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT = 4870; // 2 -const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_LEN = 4871; // 2 -const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT = 4872; // 2 -const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT_LEN = 4873; // 2 -const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_ERR = 4874; // 16 -const static uint64_t SH_FLD_DDR_CAL_TYPE = 4875; // 64 -const static uint64_t SH_FLD_DDR_CAL_TYPE_LEN = 4876; // 64 -const static uint64_t SH_FLD_DDR_CID_0_1 = 4877; // 64 -const static uint64_t SH_FLD_DDR_CID_0_1_LEN = 4878; // 64 -const static uint64_t SH_FLD_DDR_CID_2 = 4879; // 64 -const static uint64_t SH_FLD_DDR_CKE = 4880; // 64 -const static uint64_t SH_FLD_DDR_CKE_LEN = 4881; // 64 -const static uint64_t SH_FLD_DDR_CSN_0_1 = 4882; // 64 -const static uint64_t SH_FLD_DDR_CSN_0_1_LEN = 4883; // 64 -const static uint64_t SH_FLD_DDR_CSN_2_3 = 4884; // 64 -const static uint64_t SH_FLD_DDR_CSN_2_3_LEN = 4885; // 64 -const static uint64_t SH_FLD_DDR_IF_SM_1HOT = 4886; // 8 -const static uint64_t SH_FLD_DDR_INVALID_ACCESS = 4887; // 8 -const static uint64_t SH_FLD_DDR_MBA_EVENT_N = 4888; // 16 -const static uint64_t SH_FLD_DDR_ODT = 4889; // 64 -const static uint64_t SH_FLD_DDR_ODT_LEN = 4890; // 64 -const static uint64_t SH_FLD_DDR_PARITY = 4891; // 64 -const static uint64_t SH_FLD_DDR_PARITY_ENABLE = 4892; // 2 -const static uint64_t SH_FLD_DDR_RESETN = 4893; // 64 -const static uint64_t SH_FLD_DEAD = 4894; // 43 -const static uint64_t SH_FLD_DEBUG = 4895; // 2 -const static uint64_t SH_FLD_DEBUG0_CONFIG_P = 4896; // 1 -const static uint64_t SH_FLD_DEBUG1_CONFIG_P = 4897; // 1 -const static uint64_t SH_FLD_DEBUGGER = 4898; // 25 -const static uint64_t SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS = 4899; // 1 -const static uint64_t SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS_LEN = 4900; // 1 -const static uint64_t SH_FLD_DEBUG_BUS_SEL = 4901; // 8 -const static uint64_t SH_FLD_DEBUG_BUS_SEL_LEN = 4902; // 8 -const static uint64_t SH_FLD_DEBUG_LEN = 4903; // 2 -const static uint64_t SH_FLD_DEBUG_OCI_MODE = 4904; // 1 -const static uint64_t SH_FLD_DEBUG_OCI_MODE_LEN = 4905; // 1 -const static uint64_t SH_FLD_DEBUG_PB_NOT_OCI = 4906; // 1 -const static uint64_t SH_FLD_DEBUG_TRIGGER = 4907; // 24 -const static uint64_t SH_FLD_DECONFIGURED_INTR = 4908; // 24 -const static uint64_t SH_FLD_DECOUPLE_EDGE_A = 4909; // 48 -const static uint64_t SH_FLD_DECOUPLE_EDGE_B = 4910; // 48 -const static uint64_t SH_FLD_DEC_EXIT_ENABLE = 4911; // 96 -const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP = 4912; // 30 -const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP_LEN = 4913; // 30 -const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP = 4914; // 30 -const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP_LEN = 4915; // 30 -const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC = 4916; // 30 -const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC_LEN = 4917; // 30 -const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR = 4918; // 30 -const static uint64_t SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR_LEN = 4919; // 30 -const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP = 4920; // 30 -const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP_LEN = 4921; // 30 -const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP = 4922; // 30 -const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP_LEN = 4923; // 30 -const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC = 4924; // 30 -const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC_LEN = 4925; // 30 -const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR = 4926; // 30 -const static uint64_t SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR_LEN = 4927; // 30 -const static uint64_t SH_FLD_DEF_VALUES = 4928; // 8 -const static uint64_t SH_FLD_DEF_VALUES_LEN = 4929; // 8 -const static uint64_t SH_FLD_DEGLITCH_CLK_DLY = 4930; // 1 -const static uint64_t SH_FLD_DEGLITCH_CLK_DLY_LEN = 4931; // 1 -const static uint64_t SH_FLD_DEGLITCH_DATA_DLY = 4932; // 1 -const static uint64_t SH_FLD_DEGLITCH_DATA_DLY_LEN = 4933; // 1 -const static uint64_t SH_FLD_DELAY = 4934; // 1 -const static uint64_t SH_FLD_DELAY1_ID = 4935; // 12 -const static uint64_t SH_FLD_DELAY1_ID_LEN = 4936; // 12 -const static uint64_t SH_FLD_DELAY1_VALID = 4937; // 12 -const static uint64_t SH_FLD_DELAY2_ID = 4938; // 12 -const static uint64_t SH_FLD_DELAY2_ID_LEN = 4939; // 12 -const static uint64_t SH_FLD_DELAY2_VALID = 4940; // 12 -const static uint64_t SH_FLD_DELAY3_ID = 4941; // 12 -const static uint64_t SH_FLD_DELAY3_ID_LEN = 4942; // 12 -const static uint64_t SH_FLD_DELAY3_VALID = 4943; // 12 -const static uint64_t SH_FLD_DELAY4_ID = 4944; // 12 -const static uint64_t SH_FLD_DELAY4_ID_LEN = 4945; // 12 -const static uint64_t SH_FLD_DELAY4_VALID = 4946; // 12 -const static uint64_t SH_FLD_DELAY5_ID = 4947; // 12 -const static uint64_t SH_FLD_DELAY5_ID_LEN = 4948; // 12 -const static uint64_t SH_FLD_DELAY5_VALID = 4949; // 12 -const static uint64_t SH_FLD_DELAY6_ID = 4950; // 12 -const static uint64_t SH_FLD_DELAY6_ID_LEN = 4951; // 12 -const static uint64_t SH_FLD_DELAY6_VALID = 4952; // 12 -const static uint64_t SH_FLD_DELAY7_ID = 4953; // 12 -const static uint64_t SH_FLD_DELAY7_ID_LEN = 4954; // 12 -const static uint64_t SH_FLD_DELAY7_VALID = 4955; // 12 -const static uint64_t SH_FLD_DELAY8_ID = 4956; // 12 -const static uint64_t SH_FLD_DELAY8_ID_LEN = 4957; // 12 -const static uint64_t SH_FLD_DELAY8_VALID = 4958; // 12 -const static uint64_t SH_FLD_DELAYED_PAR = 4959; // 8 -const static uint64_t SH_FLD_DELAYG = 4960; // 32 -const static uint64_t SH_FLD_DELAYG_LEN = 4961; // 32 -const static uint64_t SH_FLD_DELAY_ADJUST_DISABLE = 4962; // 1 -const static uint64_t SH_FLD_DELAY_ADJUST_VALUE = 4963; // 1 -const static uint64_t SH_FLD_DELAY_ADJUST_VALUE_LEN = 4964; // 1 -const static uint64_t SH_FLD_DELAY_DISABLE = 4965; // 1 -const static uint64_t SH_FLD_DELAY_LCLKR = 4966; // 43 -const static uint64_t SH_FLD_DELAY_LEN = 4967; // 1 -const static uint64_t SH_FLD_DELAY_LINE_CTL_OVERRIDE = 4968; // 8 -const static uint64_t SH_FLD_DEQUEUED_EOT_FLAG = 4969; // 1 -const static uint64_t SH_FLD_DESKEW_DONE = 4970; // 4 -const static uint64_t SH_FLD_DESKEW_FAILED = 4971; // 4 -const static uint64_t SH_FLD_DESKEW_MAXSKEW_GRP = 4972; // 4 -const static uint64_t SH_FLD_DESKEW_MAXSKEW_GRP_LEN = 4973; // 4 -const static uint64_t SH_FLD_DESKEW_MAX_LIMIT = 4974; // 4 -const static uint64_t SH_FLD_DESKEW_MAX_LIMIT_LEN = 4975; // 4 -const static uint64_t SH_FLD_DESKEW_MINSKEW_GRP = 4976; // 4 -const static uint64_t SH_FLD_DESKEW_MINSKEW_GRP_LEN = 4977; // 4 -const static uint64_t SH_FLD_DESKEW_RATE = 4978; // 8 -const static uint64_t SH_FLD_DESKEW_SEQ_GCRMSG = 4979; // 4 -const static uint64_t SH_FLD_DESKEW_SEQ_GCRMSG_LEN = 4980; // 4 -const static uint64_t SH_FLD_DESKEW_SKMAX_GCRMSG = 4981; // 4 -const static uint64_t SH_FLD_DESKEW_SKMAX_GCRMSG_LEN = 4982; // 4 -const static uint64_t SH_FLD_DESKEW_SKMIN_GCRMSG = 4983; // 4 -const static uint64_t SH_FLD_DESKEW_SKMIN_GCRMSG_LEN = 4984; // 4 -const static uint64_t SH_FLD_DEST = 4985; // 1 -const static uint64_t SH_FLD_DEST0 = 4986; // 15 -const static uint64_t SH_FLD_DEST0_LEN = 4987; // 15 -const static uint64_t SH_FLD_DEST1 = 4988; // 15 -const static uint64_t SH_FLD_DEST1_LEN = 4989; // 15 -const static uint64_t SH_FLD_DEST_CHIPID = 4990; // 1 -const static uint64_t SH_FLD_DEST_CHIPID_LEN = 4991; // 1 -const static uint64_t SH_FLD_DEST_GROUPID = 4992; // 1 -const static uint64_t SH_FLD_DEST_GROUPID_LEN = 4993; // 1 -const static uint64_t SH_FLD_DEST_LEN = 4994; // 1 -const static uint64_t SH_FLD_DEVICE = 4995; // 1 -const static uint64_t SH_FLD_DEVICE_ADDRESS_0 = 4996; // 1 -const static uint64_t SH_FLD_DEVICE_ADDRESS_0_LEN = 4997; // 1 -const static uint64_t SH_FLD_DEVICE_ADDRESS_1 = 4998; // 1 -const static uint64_t SH_FLD_DEVICE_ADDRESS_1_LEN = 4999; // 1 -const static uint64_t SH_FLD_DEVICE_ADDRESS_2 = 5000; // 1 -const static uint64_t SH_FLD_DEVICE_ADDRESS_2_LEN = 5001; // 1 -const static uint64_t SH_FLD_DEVICE_ADDRESS_3 = 5002; // 1 -const static uint64_t SH_FLD_DEVICE_ADDRESS_3_LEN = 5003; // 1 -const static uint64_t SH_FLD_DEVICE_ID = 5004; // 4 -const static uint64_t SH_FLD_DEVICE_ID_LEN = 5005; // 4 -const static uint64_t SH_FLD_DFE12_EN = 5006; // 4 -const static uint64_t SH_FLD_DFEHISPD_EN = 5007; // 4 -const static uint64_t SH_FLD_DFE_CA_CFG = 5008; // 6 -const static uint64_t SH_FLD_DFE_CA_CFG_LEN = 5009; // 6 -const static uint64_t SH_FLD_DFE_CONVERGED_CNT_MAX = 5010; // 6 -const static uint64_t SH_FLD_DFE_CONVERGED_CNT_MAX_LEN = 5011; // 6 -const static uint64_t SH_FLD_DGD_AE_ALWAYS = 5012; // 6 -const static uint64_t SH_FLD_DGD_BE_128 = 5013; // 6 -const static uint64_t SH_FLD_DGEN_RNDD_DATA_MAPPING = 5014; // 2 -const static uint64_t SH_FLD_DGEN_RNDD_DATA_MAPPING_LEN = 5015; // 2 -const static uint64_t SH_FLD_DGEN_RNDD_SEED0 = 5016; // 2 -const static uint64_t SH_FLD_DGEN_RNDD_SEED0_LEN = 5017; // 2 -const static uint64_t SH_FLD_DGEN_RNDD_SEED1 = 5018; // 2 -const static uint64_t SH_FLD_DGEN_RNDD_SEED1_LEN = 5019; // 2 -const static uint64_t SH_FLD_DGEN_RNDD_SEED2 = 5020; // 2 -const static uint64_t SH_FLD_DGEN_RNDD_SEED2_LEN = 5021; // 2 -const static uint64_t SH_FLD_DI1_N = 5022; // 43 -const static uint64_t SH_FLD_DI2_N = 5023; // 43 -const static uint64_t SH_FLD_DIAG = 5024; // 1 -const static uint64_t SH_FLD_DIAG_0 = 5025; // 1 -const static uint64_t SH_FLD_DIAG_1 = 5026; // 1 -const static uint64_t SH_FLD_DIAG_2 = 5027; // 1 -const static uint64_t SH_FLD_DIAG_3 = 5028; // 1 -const static uint64_t SH_FLD_DIB01_ERR = 5029; // 2 -const static uint64_t SH_FLD_DIB01_SPARE = 5030; // 1 -const static uint64_t SH_FLD_DIB01_SPARE_LEN = 5031; // 1 -const static uint64_t SH_FLD_DIB23_ERR = 5032; // 2 -const static uint64_t SH_FLD_DIB45_ERR = 5033; // 2 -const static uint64_t SH_FLD_DIB67_ERR = 5034; // 1 -const static uint64_t SH_FLD_DIB67_SPARE = 5035; // 1 -const static uint64_t SH_FLD_DIB67_SPARE_LEN = 5036; // 1 -const static uint64_t SH_FLD_DIGITAL_EYE = 5037; // 8 -const static uint64_t SH_FLD_DIRECT_ATTACH_MODE = 5038; // 4 -const static uint64_t SH_FLD_DIRECT_BRIDGE_SOURCE = 5039; // 1 -const static uint64_t SH_FLD_DIR_CE_DETECTED = 5040; // 12 -const static uint64_t SH_FLD_DIR_SBCE_REPAIR_FAILED = 5041; // 12 -const static uint64_t SH_FLD_DIR_STUCK_BIT_CE = 5042; // 12 -const static uint64_t SH_FLD_DIR_UE_DETECTED = 5043; // 12 -const static uint64_t SH_FLD_DISABLE = 5044; // 1 -const static uint64_t SH_FLD_DISABLE_1 = 5045; // 1 -const static uint64_t SH_FLD_DISABLE_1_LEN = 5046; // 1 -const static uint64_t SH_FLD_DISABLE_2 = 5047; // 1 -const static uint64_t SH_FLD_DISABLE_2K_SPEC_FILTER = 5048; // 4 -const static uint64_t SH_FLD_DISABLE_2N_MODE = 5049; // 2 -const static uint64_t SH_FLD_DISABLE_2_LEN = 5050; // 1 -const static uint64_t SH_FLD_DISABLE_ALL_SPEC_OPS = 5051; // 4 -const static uint64_t SH_FLD_DISABLE_BANK_PDWN = 5052; // 2 -const static uint64_t SH_FLD_DISABLE_BYPASS_IN_READ_DATAFLOW = 5053; // 4 -const static uint64_t SH_FLD_DISABLE_CENTAUR_BAD_CRESP = 5054; // 4 -const static uint64_t SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH = 5055; // 4 -const static uint64_t SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH_LEN = 5056; // 4 -const static uint64_t SH_FLD_DISABLE_CHARB_BYPASS = 5057; // 4 -const static uint64_t SH_FLD_DISABLE_CHECKSTOP = 5058; // 1 -const static uint64_t SH_FLD_DISABLE_CI = 5059; // 4 -const static uint64_t SH_FLD_DISABLE_CI_LEN = 5060; // 4 -const static uint64_t SH_FLD_DISABLE_CL_AO_QUEUES = 5061; // 4 -const static uint64_t SH_FLD_DISABLE_COMMAND_BYPASS = 5062; // 4 -const static uint64_t SH_FLD_DISABLE_COMMAND_BYPASS_LEN = 5063; // 4 -const static uint64_t SH_FLD_DISABLE_CRC_ECC_BYPASS = 5064; // 4 -const static uint64_t SH_FLD_DISABLE_CRC_ECC_BYPASS_LEN = 5065; // 4 -const static uint64_t SH_FLD_DISABLE_CRC_ECC_FP_BYPASS = 5066; // 4 -const static uint64_t SH_FLD_DISABLE_DROPABLE = 5067; // 8 -const static uint64_t SH_FLD_DISABLE_ECC = 5068; // 1 -const static uint64_t SH_FLD_DISABLE_ECC_ARRAY_CHK = 5069; // 2 -const static uint64_t SH_FLD_DISABLE_ECC_ARRAY_CORRECTION = 5070; // 2 -const static uint64_t SH_FLD_DISABLE_ECC_CHK = 5071; // 1 -const static uint64_t SH_FLD_DISABLE_ECC_CORRECTION = 5072; // 1 -const static uint64_t SH_FLD_DISABLE_ECC_COR_GXC_PSI = 5073; // 1 -const static uint64_t SH_FLD_DISABLE_ECC_COR_RXRF_PSI = 5074; // 1 -const static uint64_t SH_FLD_DISABLE_ECC_COR_TXRF_PSI = 5075; // 1 -const static uint64_t SH_FLD_DISABLE_ERR_CMD = 5076; // 1 -const static uint64_t SH_FLD_DISABLE_EXTRA_FIFO_ACCESSES = 5077; // 1 -const static uint64_t SH_FLD_DISABLE_EXTRA_HASH_ACCESSES = 5078; // 1 -const static uint64_t SH_FLD_DISABLE_FAR_HISTORY = 5079; // 1 -const static uint64_t SH_FLD_DISABLE_FASTPATH = 5080; // 4 -const static uint64_t SH_FLD_DISABLE_FENCE_RESET = 5081; // 4 -const static uint64_t SH_FLD_DISABLE_FLOW_SCOPE = 5082; // 1 -const static uint64_t SH_FLD_DISABLE_FP_COMMAND_BYPASS = 5083; // 4 -const static uint64_t SH_FLD_DISABLE_FP_M_BIT = 5084; // 4 -const static uint64_t SH_FLD_DISABLE_G = 5085; // 1 -const static uint64_t SH_FLD_DISABLE_G_RD = 5086; // 1 -const static uint64_t SH_FLD_DISABLE_G_WR = 5087; // 1 -const static uint64_t SH_FLD_DISABLE_H1_CLEAR = 5088; // 6 -const static uint64_t SH_FLD_DISABLE_HIGH_PRIORITY = 5089; // 4 -const static uint64_t SH_FLD_DISABLE_HIGH_PRIORITY_LEN = 5090; // 4 -const static uint64_t SH_FLD_DISABLE_HIT_UNDER_BARRIER = 5091; // 1 -const static uint64_t SH_FLD_DISABLE_HTM_CMD = 5092; // 1 -const static uint64_t SH_FLD_DISABLE_INJECT = 5093; // 1 -const static uint64_t SH_FLD_DISABLE_LFSR = 5094; // 1 -const static uint64_t SH_FLD_DISABLE_LN = 5095; // 1 -const static uint64_t SH_FLD_DISABLE_LN_RD = 5096; // 1 -const static uint64_t SH_FLD_DISABLE_LN_WR = 5097; // 1 -const static uint64_t SH_FLD_DISABLE_LPC_CMDS = 5098; // 3 -const static uint64_t SH_FLD_DISABLE_MDI0 = 5099; // 4 -const static uint64_t SH_FLD_DISABLE_MDI0_LEN = 5100; // 4 -const static uint64_t SH_FLD_DISABLE_MEMCTL_CAL = 5101; // 8 -const static uint64_t SH_FLD_DISABLE_NEAR_HISTORY = 5102; // 1 -const static uint64_t SH_FLD_DISABLE_NN_RD = 5103; // 1 -const static uint64_t SH_FLD_DISABLE_NN_RN = 5104; // 1 -const static uint64_t SH_FLD_DISABLE_NN_WR = 5105; // 1 -const static uint64_t SH_FLD_DISABLE_PARITY_CHECKER = 5106; // 8 -const static uint64_t SH_FLD_DISABLE_PCB_ITR = 5107; // 43 -const static uint64_t SH_FLD_DISABLE_PERFMON_RESET_ON_START = 5108; // 4 -const static uint64_t SH_FLD_DISABLE_PMISC = 5109; // 3 -const static uint64_t SH_FLD_DISABLE_PMU_SNOOPING = 5110; // 1 -const static uint64_t SH_FLD_DISABLE_PTAG_IN_AIBTAG = 5111; // 1 -const static uint64_t SH_FLD_DISABLE_RCMD_CLKGATE = 5112; // 3 -const static uint64_t SH_FLD_DISABLE_RESET_2K_COUNT_IF_HINT_BIT_SET = 5113; // 4 -const static uint64_t SH_FLD_DISABLE_RETRY_LOST_CLAIM = 5114; // 4 -const static uint64_t SH_FLD_DISABLE_SHARD_PRESP_ABORT = 5115; // 4 -const static uint64_t SH_FLD_DISABLE_SPEC_DISABLE_HINT_BIT = 5116; // 4 -const static uint64_t SH_FLD_DISABLE_SPEC_OP = 5117; // 4 -const static uint64_t SH_FLD_DISABLE_SPEC_OP_LEN = 5118; // 4 -const static uint64_t SH_FLD_DISABLE_SPEC_SOURCE_SCOPE = 5119; // 4 -const static uint64_t SH_FLD_DISABLE_SPEC_SOURCE_SCOPE_LEN = 5120; // 4 -const static uint64_t SH_FLD_DISABLE_STICKINESS = 5121; // 43 -const static uint64_t SH_FLD_DISABLE_TIMEOUT_AND_RETRY = 5122; // 1 -const static uint64_t SH_FLD_DISABLE_TOD_CMD = 5123; // 1 -const static uint64_t SH_FLD_DISABLE_TRACE_CMD = 5124; // 1 -const static uint64_t SH_FLD_DISABLE_VG_NOT_SYS = 5125; // 1 -const static uint64_t SH_FLD_DISABLE_VG_RD = 5126; // 1 -const static uint64_t SH_FLD_DISABLE_VG_WR = 5127; // 1 -const static uint64_t SH_FLD_DISABLE_WRP = 5128; // 1 -const static uint64_t SH_FLD_DISABLE_XSCOM_CMD = 5129; // 1 -const static uint64_t SH_FLD_DISPATCH_SLOT_KILLED_CNT = 5130; // 1 -const static uint64_t SH_FLD_DISPATCH_SLOT_KILLED_CNT_LEN = 5131; // 1 -const static uint64_t SH_FLD_DISTRIBUTION_BROADCAST_MODE_ENABLE = 5132; // 1 -const static uint64_t SH_FLD_DISTR_STEP_SYNC_TX_DISABLE = 5133; // 1 -const static uint64_t SH_FLD_DISTR_STEP_SYNC_TX_SYNC_DISABLE = 5134; // 1 -const static uint64_t SH_FLD_DISTR_STEP_SYNC_TX_TRIGGER = 5135; // 1 -const static uint64_t SH_FLD_DIS_AIB_IN_ECC_CORRECTION = 5136; // 1 -const static uint64_t SH_FLD_DIS_ARX_ECC_CORRECTION = 5137; // 1 -const static uint64_t SH_FLD_DIS_AT_SRAM_ECC_CORRECTION = 5138; // 1 -const static uint64_t SH_FLD_DIS_BAR_SRAM_ECC_CORRECTION = 5139; // 1 -const static uint64_t SH_FLD_DIS_CHGRATE_COUNT = 5140; // 1 -const static uint64_t SH_FLD_DIS_CPM_BUBBLE_CORR = 5141; // 43 -const static uint64_t SH_FLD_DIS_CTRLBUF_ECC_CORRECTION = 5142; // 1 -const static uint64_t SH_FLD_DIS_DATA_ECC_CORRECTION = 5143; // 3 -const static uint64_t SH_FLD_DIS_DATA_ECC_CORRECTION_LEN = 5144; // 3 -const static uint64_t SH_FLD_DIS_DMA_W = 5145; // 1 -const static uint64_t SH_FLD_DIS_ECCCHK = 5146; // 1 -const static uint64_t SH_FLD_DIS_ECCCHK_CLO = 5147; // 1 -const static uint64_t SH_FLD_DIS_ECCCHK_IN = 5148; // 1 -const static uint64_t SH_FLD_DIS_ECCCHK_LDO = 5149; // 1 -const static uint64_t SH_FLD_DIS_ECCCHK_STO = 5150; // 1 -const static uint64_t SH_FLD_DIS_ECCCHK_WRO = 5151; // 1 -const static uint64_t SH_FLD_DIS_GLOB_SCOM = 5152; // 2 -const static uint64_t SH_FLD_DIS_IRQ_ECC_CORRECTION = 5153; // 1 -const static uint64_t SH_FLD_DIS_MASTER_RD_PIPE = 5154; // 1 -const static uint64_t SH_FLD_DIS_MASTER_WR_PIPE = 5155; // 1 -const static uint64_t SH_FLD_DIS_MSTID_MATCH_PREF_INV = 5156; // 1 -const static uint64_t SH_FLD_DIS_NCNP = 5157; // 1 -const static uint64_t SH_FLD_DIS_REARB = 5158; // 1 -const static uint64_t SH_FLD_DIS_RECOVERY = 5159; // 24 -const static uint64_t SH_FLD_DIS_REREQUEST_TO = 5160; // 1 -const static uint64_t SH_FLD_DIS_SLAVE_RDPIPE = 5161; // 1 -const static uint64_t SH_FLD_DIS_SLAVE_WRPIPE = 5162; // 1 -const static uint64_t SH_FLD_DIS_STATE_ECC_CORRECTION = 5163; // 3 -const static uint64_t SH_FLD_DIS_STATE_ECC_CORRECTION_LEN = 5164; // 1 -const static uint64_t SH_FLD_DIS_TAG_ECC_CORRECTION = 5165; // 3 -const static uint64_t SH_FLD_DIS_TAG_ECC_CORRECTION_LEN = 5166; // 3 -const static uint64_t SH_FLD_DIS_TAG_SRAM_ECC_CORRECTION = 5167; // 1 -const static uint64_t SH_FLD_DIS_TRACE = 5168; // 24 -const static uint64_t SH_FLD_DIS_TRACE_EXTRA = 5169; // 17 -const static uint64_t SH_FLD_DIS_TRACE_STALL = 5170; // 17 -const static uint64_t SH_FLD_DIS_WRITE_GATHER = 5171; // 4 -const static uint64_t SH_FLD_DIVIDER_MODE = 5172; // 12 -const static uint64_t SH_FLD_DIVIDER_MODE_LEN = 5173; // 12 -const static uint64_t SH_FLD_DIVSELB = 5174; // 10 -const static uint64_t SH_FLD_DIVSELB_LEN = 5175; // 10 -const static uint64_t SH_FLD_DIVSELFB = 5176; // 10 -const static uint64_t SH_FLD_DIVSELFB_LEN = 5177; // 10 -const static uint64_t SH_FLD_DIV_PARITY = 5178; // 43 -const static uint64_t SH_FLD_DLL = 5179; // 8 -const static uint64_t SH_FLD_DLL_CLOCK_GATE = 5180; // 8 -const static uint64_t SH_FLD_DMAP_MODE_EN = 5181; // 2 -const static uint64_t SH_FLD_DMA_CH0_IDLE = 5182; // 1 -const static uint64_t SH_FLD_DMA_CH1_IDLE = 5183; // 1 -const static uint64_t SH_FLD_DMA_CH2_IDLE = 5184; // 1 -const static uint64_t SH_FLD_DMA_CH3_IDLE = 5185; // 1 -const static uint64_t SH_FLD_DMA_CH4_IDLE = 5186; // 1 -const static uint64_t SH_FLD_DMA_CRBARRAY_ACTION = 5187; // 1 -const static uint64_t SH_FLD_DMA_CRBARRAY_ENA = 5188; // 1 -const static uint64_t SH_FLD_DMA_CRBARRAY_SELECT = 5189; // 1 -const static uint64_t SH_FLD_DMA_CRBARRAY_TYPE = 5190; // 1 -const static uint64_t SH_FLD_DMA_EGRARRAY_ACTION = 5191; // 1 -const static uint64_t SH_FLD_DMA_EGRARRAY_ENA = 5192; // 1 -const static uint64_t SH_FLD_DMA_EGRARRAY_SELECT = 5193; // 1 -const static uint64_t SH_FLD_DMA_EGRARRAY_SELECT_LEN = 5194; // 1 -const static uint64_t SH_FLD_DMA_EGRARRAY_TYPE = 5195; // 1 -const static uint64_t SH_FLD_DMA_INGARRAY_ACTION = 5196; // 1 -const static uint64_t SH_FLD_DMA_INGARRAY_ENA = 5197; // 1 -const static uint64_t SH_FLD_DMA_INGARRAY_SELECT = 5198; // 1 -const static uint64_t SH_FLD_DMA_INGARRAY_SELECT_LEN = 5199; // 1 -const static uint64_t SH_FLD_DMA_INGARRAY_TYPE = 5200; // 1 -const static uint64_t SH_FLD_DMA_INWR_ACTION = 5201; // 1 -const static uint64_t SH_FLD_DMA_INWR_ENA = 5202; // 1 -const static uint64_t SH_FLD_DMA_INWR_TYPE = 5203; // 1 -const static uint64_t SH_FLD_DMA_MUX_SELECT = 5204; // 1 -const static uint64_t SH_FLD_DMA_MUX_SELECT_LEN = 5205; // 1 -const static uint64_t SH_FLD_DMA_OUTWR_ACTION = 5206; // 1 -const static uint64_t SH_FLD_DMA_OUTWR_ENA = 5207; // 1 -const static uint64_t SH_FLD_DMA_OUTWR_TYPE = 5208; // 1 -const static uint64_t SH_FLD_DMA_PARTIAL_WRT_NOT_INJECT = 5209; // 1 -const static uint64_t SH_FLD_DMA_PART_WR_NOT_INJ = 5210; // 1 -const static uint64_t SH_FLD_DMA_RD_DISABLE_GROUP = 5211; // 1 -const static uint64_t SH_FLD_DMA_RD_DISABLE_LN = 5212; // 1 -const static uint64_t SH_FLD_DMA_RD_DISABLE_NN_RN = 5213; // 1 -const static uint64_t SH_FLD_DMA_RD_DISABLE_VG_NOT_SYS = 5214; // 1 -const static uint64_t SH_FLD_DMA_RD_VG_RESET_TIMER_MASK = 5215; // 1 -const static uint64_t SH_FLD_DMA_RD_VG_RESET_TIMER_MASK_LEN = 5216; // 1 -const static uint64_t SH_FLD_DMA_RD_VG_RST_TMASK = 5217; // 1 -const static uint64_t SH_FLD_DMA_RD_VG_RST_TMASK_LEN = 5218; // 1 -const static uint64_t SH_FLD_DMA_READ = 5219; // 3 -const static uint64_t SH_FLD_DMA_READ_LEN = 5220; // 3 -const static uint64_t SH_FLD_DMA_STOPPED_STATE = 5221; // 32 -const static uint64_t SH_FLD_DMA_STOPPED_STATE_LEN = 5222; // 16 -const static uint64_t SH_FLD_DMA_TIMER_ENBL = 5223; // 1 -const static uint64_t SH_FLD_DMA_TIMER_REF_DIV = 5224; // 1 -const static uint64_t SH_FLD_DMA_TIMER_REF_DIV_LEN = 5225; // 1 -const static uint64_t SH_FLD_DMA_WRITE = 5226; // 3 -const static uint64_t SH_FLD_DMA_WRITE_LEN = 5227; // 2 -const static uint64_t SH_FLD_DMA_WR_DISABLE_GROUP = 5228; // 1 -const static uint64_t SH_FLD_DMA_WR_DISABLE_LN = 5229; // 1 -const static uint64_t SH_FLD_DMA_WR_DISABLE_NN_RN = 5230; // 1 -const static uint64_t SH_FLD_DMA_WR_DISABLE_VG_NOT_SYS = 5231; // 1 -const static uint64_t SH_FLD_DMA_WR_NOT_INJ = 5232; // 1 -const static uint64_t SH_FLD_DMA_WR_NOT_INJECT = 5233; // 1 -const static uint64_t SH_FLD_DMA_WR_VG_RESET_TIMER_MASK = 5234; // 1 -const static uint64_t SH_FLD_DMA_WR_VG_RESET_TIMER_MASK_LEN = 5235; // 1 -const static uint64_t SH_FLD_DMA_WR_VG_RST_TMASK = 5236; // 1 -const static uint64_t SH_FLD_DMA_WR_VG_RST_TMASK_LEN = 5237; // 1 -const static uint64_t SH_FLD_DNFIFO_DEQUEUED_EOT_FLAG = 5238; // 1 -const static uint64_t SH_FLD_DNFIFO_FIFO_EMPTY = 5239; // 1 -const static uint64_t SH_FLD_DNFIFO_FIFO_ENTRY_COUNT = 5240; // 1 -const static uint64_t SH_FLD_DNFIFO_FIFO_ENTRY_COUNT_LEN = 5241; // 1 -const static uint64_t SH_FLD_DNFIFO_FIFO_EOT_FLAGS = 5242; // 1 -const static uint64_t SH_FLD_DNFIFO_FIFO_EOT_FLAGS_LEN = 5243; // 1 -const static uint64_t SH_FLD_DNFIFO_FIFO_FULL = 5244; // 1 -const static uint64_t SH_FLD_DNFIFO_FIFO_VALID_FLAGS = 5245; // 1 -const static uint64_t SH_FLD_DNFIFO_FIFO_VALID_FLAGS_LEN = 5246; // 1 -const static uint64_t SH_FLD_DNFIFO_REQ_RESET_FR_SBE = 5247; // 1 -const static uint64_t SH_FLD_DNFIFO_REQ_RESET_FR_SP = 5248; // 1 -const static uint64_t SH_FLD_DOB01_CE = 5249; // 4 -const static uint64_t SH_FLD_DOB01_ERR = 5250; // 2 -const static uint64_t SH_FLD_DOB01_SUE = 5251; // 4 -const static uint64_t SH_FLD_DOB01_UE = 5252; // 4 -const static uint64_t SH_FLD_DOB23_CE = 5253; // 4 -const static uint64_t SH_FLD_DOB23_ERR = 5254; // 2 -const static uint64_t SH_FLD_DOB23_SUE = 5255; // 4 -const static uint64_t SH_FLD_DOB23_UE = 5256; // 4 -const static uint64_t SH_FLD_DOB45_CE = 5257; // 4 -const static uint64_t SH_FLD_DOB45_ERR = 5258; // 2 -const static uint64_t SH_FLD_DOB45_SUE = 5259; // 4 -const static uint64_t SH_FLD_DOB45_UE = 5260; // 4 -const static uint64_t SH_FLD_DOB67_CE = 5261; // 2 -const static uint64_t SH_FLD_DOB67_ERR = 5262; // 1 -const static uint64_t SH_FLD_DOB67_SUE = 5263; // 2 -const static uint64_t SH_FLD_DOB67_UE = 5264; // 2 -const static uint64_t SH_FLD_DONE = 5265; // 23 -const static uint64_t SH_FLD_DOORBELL = 5266; // 2 -const static uint64_t SH_FLD_DOORBELL0_C0 = 5267; // 12 -const static uint64_t SH_FLD_DOORBELL0_C1 = 5268; // 12 -const static uint64_t SH_FLD_DOORBELL1_C0 = 5269; // 12 -const static uint64_t SH_FLD_DOORBELL1_C1 = 5270; // 12 -const static uint64_t SH_FLD_DOORBELL2_C0 = 5271; // 12 -const static uint64_t SH_FLD_DOORBELL2_C1 = 5272; // 12 -const static uint64_t SH_FLD_DOORBELL3_C0 = 5273; // 12 -const static uint64_t SH_FLD_DOORBELL3_C1 = 5274; // 12 -const static uint64_t SH_FLD_DOUBLE_EPSILON_LENGTH = 5275; // 4 -const static uint64_t SH_FLD_DO_DR = 5276; // 1 -const static uint64_t SH_FLD_DO_IR = 5277; // 1 -const static uint64_t SH_FLD_DO_TAP_RESET = 5278; // 1 -const static uint64_t SH_FLD_DP16_RX_PD = 5279; // 8 -const static uint64_t SH_FLD_DP16_RX_PD_LEN = 5280; // 8 -const static uint64_t SH_FLD_DPLL_DCO_EMPTY = 5281; // 6 -const static uint64_t SH_FLD_DPLL_DCO_FULL = 5282; // 6 -const static uint64_t SH_FLD_DPLL_DYN_FMIN = 5283; // 6 -const static uint64_t SH_FLD_DPLL_INT = 5284; // 6 -const static uint64_t SH_FLD_DP_ERROR = 5285; // 8 -const static uint64_t SH_FLD_DP_ERROR_FINE = 5286; // 8 -const static uint64_t SH_FLD_DP_GOOD = 5287; // 8 -const static uint64_t SH_FLD_DQS_ALIGN = 5288; // 8 -const static uint64_t SH_FLD_DQ_SEL_LANE = 5289; // 8 -const static uint64_t SH_FLD_DQ_SEL_LANE_LEN = 5290; // 8 -const static uint64_t SH_FLD_DQ_SEL_QUAD = 5291; // 8 -const static uint64_t SH_FLD_DQ_SEL_QUAD_LEN = 5292; // 8 -const static uint64_t SH_FLD_DRAM_ABIST_DONE_DC = 5293; // 43 -const static uint64_t SH_FLD_DROP_COUNTER_FULL = 5294; // 4 -const static uint64_t SH_FLD_DROP_MASK_0_5 = 5295; // 1 -const static uint64_t SH_FLD_DROP_MASK_0_5_LEN = 5296; // 1 -const static uint64_t SH_FLD_DROP_PRIORITY_MASK = 5297; // 12 -const static uint64_t SH_FLD_DROP_PRIORITY_MASK_LEN = 5298; // 12 -const static uint64_t SH_FLD_DROP_PRIORITY_MODE = 5299; // 2 -const static uint64_t SH_FLD_DROP_PRI_DMA = 5300; // 1 -const static uint64_t SH_FLD_DROP_PRI_HPC_READ = 5301; // 1 -const static uint64_t SH_FLD_DROP_PRI_INTRP = 5302; // 1 -const static uint64_t SH_FLD_DRTM_REQ = 5303; // 5 -const static uint64_t SH_FLD_DRV_CLK_PATTERN_GCRMSG = 5304; // 4 -const static uint64_t SH_FLD_DRV_CLK_PATTERN_GCRMSG_LEN = 5305; // 4 -const static uint64_t SH_FLD_DRV_DATA_PATTERN_GCRMSG = 5306; // 6 -const static uint64_t SH_FLD_DRV_DATA_PATTERN_GCRMSG_LEN = 5307; // 6 -const static uint64_t SH_FLD_DRV_PATTERN_EN = 5308; // 1 -const static uint64_t SH_FLD_DSC1_ABORT_1 = 5309; // 1 -const static uint64_t SH_FLD_DSC1_DATA_COUNT = 5310; // 1 -const static uint64_t SH_FLD_DSC1_DATA_COUNT_1B = 5311; // 1 -const static uint64_t SH_FLD_DSC1_DATA_COUNT_1B_LEN = 5312; // 1 -const static uint64_t SH_FLD_DSC1_DATA_COUNT_LEN = 5313; // 1 -const static uint64_t SH_FLD_DSC1_HEADER_COUNT = 5314; // 1 -const static uint64_t SH_FLD_DSC1_HEADER_COUNT_1B = 5315; // 1 -const static uint64_t SH_FLD_DSC1_HEADER_COUNT_1B_LEN = 5316; // 1 -const static uint64_t SH_FLD_DSC1_HEADER_COUNT_LEN = 5317; // 1 -const static uint64_t SH_FLD_DSC1_LBUS_SLAVE_1B_PENDING = 5318; // 1 -const static uint64_t SH_FLD_DSC1_PERMISSION_TO_SEND_1 = 5319; // 1 -const static uint64_t SH_FLD_DSC1_PIB_SLAVE_PENDING = 5320; // 1 -const static uint64_t SH_FLD_DSC1_UNUSED_24 = 5321; // 1 -const static uint64_t SH_FLD_DSC1_UNUSED_27 = 5322; // 1 -const static uint64_t SH_FLD_DSC1_XDN_1 = 5323; // 1 -const static uint64_t SH_FLD_DSC1_XUP_1 = 5324; // 1 -const static uint64_t SH_FLD_DSC2_ABORT_2 = 5325; // 1 -const static uint64_t SH_FLD_DSC2_DATA_COUNT = 5326; // 1 -const static uint64_t SH_FLD_DSC2_DATA_COUNT_2B = 5327; // 1 -const static uint64_t SH_FLD_DSC2_DATA_COUNT_2B_LEN = 5328; // 1 -const static uint64_t SH_FLD_DSC2_DATA_COUNT_LEN = 5329; // 1 -const static uint64_t SH_FLD_DSC2_HEADER_COUNT = 5330; // 1 -const static uint64_t SH_FLD_DSC2_HEADER_COUNT_2B = 5331; // 1 -const static uint64_t SH_FLD_DSC2_HEADER_COUNT_2B_LEN = 5332; // 1 -const static uint64_t SH_FLD_DSC2_HEADER_COUNT_LEN = 5333; // 1 -const static uint64_t SH_FLD_DSC2_LBUS_SLAVE_2B_PENDING = 5334; // 1 -const static uint64_t SH_FLD_DSC2_PERMISSION_TO_SEND_2 = 5335; // 1 -const static uint64_t SH_FLD_DSC2_PIB_SLAVE_PENDING = 5336; // 1 -const static uint64_t SH_FLD_DSC2_UNUSED_24 = 5337; // 1 -const static uint64_t SH_FLD_DSC2_UNUSED_27 = 5338; // 1 -const static uint64_t SH_FLD_DSC2_XDN_2 = 5339; // 1 -const static uint64_t SH_FLD_DSC2_XUP_2 = 5340; // 1 -const static uint64_t SH_FLD_DSM_PE = 5341; // 8 -const static uint64_t SH_FLD_DS_SKEW_TIMEOUT_SEL = 5342; // 4 -const static uint64_t SH_FLD_DS_SKEW_TIMEOUT_SEL_LEN = 5343; // 4 -const static uint64_t SH_FLD_DS_TIMEOUT_SEL = 5344; // 4 -const static uint64_t SH_FLD_DS_TIMEOUT_SEL_LEN = 5345; // 4 -const static uint64_t SH_FLD_DTS_ENABLE_L1 = 5346; // 43 -const static uint64_t SH_FLD_DTS_ENABLE_L1_LEN = 5347; // 43 -const static uint64_t SH_FLD_DTS_READ_SEL = 5348; // 43 -const static uint64_t SH_FLD_DTS_READ_SEL_LEN = 5349; // 43 -const static uint64_t SH_FLD_DTS_SAMPLE_ENA = 5350; // 43 -const static uint64_t SH_FLD_DTS_TRIGGER = 5351; // 43 -const static uint64_t SH_FLD_DTS_TRIGGER_SEL = 5352; // 43 -const static uint64_t SH_FLD_DW0_ERR_TYPE = 5353; // 16 -const static uint64_t SH_FLD_DW0_ERR_TYPE_LEN = 5354; // 16 -const static uint64_t SH_FLD_DW0_SYNDROME = 5355; // 16 -const static uint64_t SH_FLD_DW0_SYNDROME_LEN = 5356; // 16 -const static uint64_t SH_FLD_DW1_ERR_TYPE = 5357; // 16 -const static uint64_t SH_FLD_DW1_ERR_TYPE_LEN = 5358; // 16 -const static uint64_t SH_FLD_DW1_SYNDROME = 5359; // 16 -const static uint64_t SH_FLD_DW1_SYNDROME_LEN = 5360; // 16 -const static uint64_t SH_FLD_DW2_ERR_TYPE = 5361; // 16 -const static uint64_t SH_FLD_DW2_ERR_TYPE_LEN = 5362; // 16 -const static uint64_t SH_FLD_DW2_SYNDROME = 5363; // 16 -const static uint64_t SH_FLD_DW2_SYNDROME_LEN = 5364; // 16 -const static uint64_t SH_FLD_DW3_ERR_TYPE = 5365; // 16 -const static uint64_t SH_FLD_DW3_ERR_TYPE_LEN = 5366; // 16 -const static uint64_t SH_FLD_DW3_SYNDROME = 5367; // 16 -const static uint64_t SH_FLD_DW3_SYNDROME_LEN = 5368; // 16 -const static uint64_t SH_FLD_DW_TYPE = 5369; // 12 -const static uint64_t SH_FLD_DW_TYPE_LEN = 5370; // 12 -const static uint64_t SH_FLD_DYNAMIC_FILTER_ENABLE = 5371; // 6 -const static uint64_t SH_FLD_DYNAMIC_MAX_SPARES_EXCEEDED = 5372; // 8 -const static uint64_t SH_FLD_DYNAMIC_REPAIR_ERROR = 5373; // 8 -const static uint64_t SH_FLD_DYNAMIC_SPARE_DEPLOYED = 5374; // 8 -const static uint64_t SH_FLD_DYNAMIC_WINDOW_SELECT = 5375; // 8 -const static uint64_t SH_FLD_DYNAMIC_WINDOW_SELECT_LEN = 5376; // 8 -const static uint64_t SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL = 5377; // 8 -const static uint64_t SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN = 5378; // 8 -const static uint64_t SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL = 5379; // 4 -const static uint64_t SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL_LEN = 5380; // 4 -const static uint64_t SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL = 5381; // 8 -const static uint64_t SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN = 5382; // 8 -const static uint64_t SH_FLD_DYN_RECAL_SUSPEND = 5383; // 4 -const static uint64_t SH_FLD_DYN_RECAL_TSR_IGNORE_GCRMSG = 5384; // 4 -const static uint64_t SH_FLD_DYN_RPR_BAD_BUS_MAX = 5385; // 4 -const static uint64_t SH_FLD_DYN_RPR_BAD_BUS_MAX_LEN = 5386; // 4 -const static uint64_t SH_FLD_DYN_RPR_BAD_LANE_MAX = 5387; // 4 -const static uint64_t SH_FLD_DYN_RPR_BAD_LANE_MAX_LEN = 5388; // 4 -const static uint64_t SH_FLD_DYN_RPR_CLR_ERR_CNTR1 = 5389; // 4 -const static uint64_t SH_FLD_DYN_RPR_CLR_ERR_CNTR2 = 5390; // 4 -const static uint64_t SH_FLD_DYN_RPR_COMPLETE_GCRMSG = 5391; // 4 -const static uint64_t SH_FLD_DYN_RPR_DISABLE = 5392; // 4 -const static uint64_t SH_FLD_DYN_RPR_DISABLE2 = 5393; // 4 -const static uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT = 5394; // 4 -const static uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT_LEN = 5395; // 4 -const static uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH = 5396; // 4 -const static uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH_LEN = 5397; // 4 -const static uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_DURATION = 5398; // 4 -const static uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_DURATION_LEN = 5399; // 4 -const static uint64_t SH_FLD_DYN_RPR_ERR_CNTR2_DURATION = 5400; // 4 -const static uint64_t SH_FLD_DYN_RPR_ERR_CNTR2_DURATION_LEN = 5401; // 4 -const static uint64_t SH_FLD_DYN_RPR_IP_GCRMSG = 5402; // 4 -const static uint64_t SH_FLD_DYN_RPR_LANE2RPR_GCRMSG = 5403; // 4 -const static uint64_t SH_FLD_DYN_RPR_LANE2RPR_GCRMSG_LEN = 5404; // 4 -const static uint64_t SH_FLD_DYN_RPR_REQ_GCRMSG = 5405; // 4 -const static uint64_t SH_FLD_D_BIT_MAP = 5406; // 8 -const static uint64_t SH_FLD_D_BIT_MAP_LEN = 5407; // 8 -const static uint64_t SH_FLD_EARLY_REQ = 5408; // 8 -const static uint64_t SH_FLD_EARLY_REQ_ERR_MASK = 5409; // 8 -const static uint64_t SH_FLD_EARLY_REQ_SOURCE = 5410; // 8 -const static uint64_t SH_FLD_EARLY_REQ_SOURCE_LEN = 5411; // 8 -const static uint64_t SH_FLD_EBUS_ENABLE = 5412; // 1 -const static uint64_t SH_FLD_EBUS_ENABLE_LEN = 5413; // 1 -const static uint64_t SH_FLD_ECC = 5414; // 3 -const static uint64_t SH_FLD_ECCCHK_DISABLE_0 = 5415; // 1 -const static uint64_t SH_FLD_ECCCHK_DISABLE_1 = 5416; // 1 -const static uint64_t SH_FLD_ECCCHK_DISABLE_2 = 5417; // 1 -const static uint64_t SH_FLD_ECCCHK_DISABLE_3 = 5418; // 1 -const static uint64_t SH_FLD_ECCGEN = 5419; // 8 -const static uint64_t SH_FLD_ECC_CE = 5420; // 3 -const static uint64_t SH_FLD_ECC_CHK_DISABLE = 5421; // 1 -const static uint64_t SH_FLD_ECC_CLEAR = 5422; // 2 -const static uint64_t SH_FLD_ECC_CONFIG_ERROR_0 = 5423; // 1 -const static uint64_t SH_FLD_ECC_CONFIG_ERROR_1 = 5424; // 1 -const static uint64_t SH_FLD_ECC_CONFIG_ERROR_2 = 5425; // 1 -const static uint64_t SH_FLD_ECC_CONFIG_ERROR_3 = 5426; // 1 -const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_0 = 5427; // 1 -const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_1 = 5428; // 1 -const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_2 = 5429; // 1 -const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_3 = 5430; // 1 -const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_FACES = 5431; // 1 -const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_PIB = 5432; // 1 -const static uint64_t SH_FLD_ECC_CORRECTOR_INTERNAL_PARITY_ERROR = 5433; // 8 -const static uint64_t SH_FLD_ECC_CORRECT_DIS = 5434; // 15 -const static uint64_t SH_FLD_ECC_DETECT_DIS = 5435; // 15 -const static uint64_t SH_FLD_ECC_ENABLE = 5436; // 6 -const static uint64_t SH_FLD_ECC_ENABLE_0 = 5437; // 1 -const static uint64_t SH_FLD_ECC_ENABLE_1 = 5438; // 1 -const static uint64_t SH_FLD_ECC_ENABLE_2 = 5439; // 1 -const static uint64_t SH_FLD_ECC_ENABLE_3 = 5440; // 1 -const static uint64_t SH_FLD_ECC_ERROR_ADDR = 5441; // 2 -const static uint64_t SH_FLD_ECC_ERROR_ADDR_LEN = 5442; // 2 -const static uint64_t SH_FLD_ECC_ERROR_COUNT = 5443; // 2 -const static uint64_t SH_FLD_ECC_ERROR_COUNT_LEN = 5444; // 2 -const static uint64_t SH_FLD_ECC_ERR_INJ_ARRAY_SEL = 5445; // 3 -const static uint64_t SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN = 5446; // 3 -const static uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_ENA = 5447; // 1 -const static uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_FRQ = 5448; // 1 -const static uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_TYP = 5449; // 1 -const static uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED = 5450; // 1 -const static uint64_t SH_FLD_ECC_ERR_INJ_SELECTION = 5451; // 1 -const static uint64_t SH_FLD_ECC_ERR_INJ_SELECTION_LEN = 5452; // 1 -const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_ENA = 5453; // 1 -const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_FRQ = 5454; // 1 -const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_SEL = 5455; // 1 -const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_TYP = 5456; // 1 -const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_ENA = 5457; // 1 -const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_FRQ = 5458; // 1 -const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_SEL = 5459; // 1 -const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_SEL_LEN = 5460; // 1 -const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_TYP = 5461; // 1 -const static uint64_t SH_FLD_ECC_GENERATOR_INTERNAL_PARITY_ERROR = 5462; // 8 -const static uint64_t SH_FLD_ECC_INJECT_ERR = 5463; // 15 -const static uint64_t SH_FLD_ECC_INJECT_TYPE = 5464; // 15 -const static uint64_t SH_FLD_ECC_LEN = 5465; // 3 -const static uint64_t SH_FLD_ECC_MCBIST_OUT_OF_SYNC_HOLD_OUT = 5466; // 2 -const static uint64_t SH_FLD_ECC_SYNDROME = 5467; // 2 -const static uint64_t SH_FLD_ECC_SYNDROME_LEN = 5468; // 2 -const static uint64_t SH_FLD_ECC_S_BIT_ERROR = 5469; // 1 -const static uint64_t SH_FLD_ECC_UE = 5470; // 3 -const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_0 = 5471; // 1 -const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_1 = 5472; // 1 -const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_2 = 5473; // 1 -const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_3 = 5474; // 1 -const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_FACES = 5475; // 1 -const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_PIB = 5476; // 1 -const static uint64_t SH_FLD_ECC_UNCORRECTED_ERR_FACES = 5477; // 1 -const static uint64_t SH_FLD_ECC_UNCORRECTED_ERR_PIB = 5478; // 1 -const static uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE = 5479; // 8 -const static uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_LEN = 5480; // 8 -const static uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT = 5481; // 8 -const static uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT_LEN = 5482; // 8 -const static uint64_t SH_FLD_ECHO_DELAY_CYCLES = 5483; // 2 -const static uint64_t SH_FLD_ECHO_DELAY_CYCLES_LEN = 5484; // 2 -const static uint64_t SH_FLD_ECRESP_HASH_MODE = 5485; // 4 -const static uint64_t SH_FLD_EDR = 5486; // 21 -const static uint64_t SH_FLD_EDR_LEN = 5487; // 21 -const static uint64_t SH_FLD_EFTCOMP_MAX_INRD = 5488; // 1 -const static uint64_t SH_FLD_EFTCOMP_MAX_INRD_LEN = 5489; // 1 -const static uint64_t SH_FLD_EFTDECOMP_MAX_INRD = 5490; // 1 -const static uint64_t SH_FLD_EFTDECOMP_MAX_INRD_LEN = 5491; // 1 -const static uint64_t SH_FLD_EFT_COMP_PREFETCH_ENABLE = 5492; // 1 -const static uint64_t SH_FLD_EFT_DECOMP_PREFETCH_ENABLE = 5493; // 1 -const static uint64_t SH_FLD_EFT_MUX_SELECT = 5494; // 1 -const static uint64_t SH_FLD_EFT_MUX_SELECT_LEN = 5495; // 1 -const static uint64_t SH_FLD_EFT_SPBC_ENABLE = 5496; // 1 -const static uint64_t SH_FLD_EG_CERR_BITS = 5497; // 1 -const static uint64_t SH_FLD_EG_CERR_BITS_LEN = 5498; // 1 -const static uint64_t SH_FLD_EG_CERR_RESET = 5499; // 1 -const static uint64_t SH_FLD_EG_ECC_CE_ERROR = 5500; // 2 -const static uint64_t SH_FLD_EG_ECC_SUE_ERROR = 5501; // 2 -const static uint64_t SH_FLD_EG_ECC_UE_ERROR = 5502; // 2 -const static uint64_t SH_FLD_EG_LOGIC_HW_ERROR = 5503; // 2 -const static uint64_t SH_FLD_EG_TRACE_GROUP_SEL_HI = 5504; // 1 -const static uint64_t SH_FLD_EG_TRACE_GROUP_SEL_HI_LEN = 5505; // 1 -const static uint64_t SH_FLD_EG_TRACE_GROUP_SEL_LO = 5506; // 1 -const static uint64_t SH_FLD_EG_TRACE_GROUP_SEL_LO_LEN = 5507; // 1 -const static uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_01 = 5508; // 1 -const static uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_01_LEN = 5509; // 1 -const static uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_23 = 5510; // 1 -const static uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_23_LEN = 5511; // 1 -const static uint64_t SH_FLD_EMERGENCY_M = 5512; // 8 -const static uint64_t SH_FLD_EMERGENCY_M_LEN = 5513; // 8 -const static uint64_t SH_FLD_EMERGENCY_N = 5514; // 8 -const static uint64_t SH_FLD_EMERGENCY_N_LEN = 5515; // 8 -const static uint64_t SH_FLD_EMERGENCY_THROTTLE = 5516; // 16 -const static uint64_t SH_FLD_EMER_THROTTLE_IP = 5517; // 8 -const static uint64_t SH_FLD_EMER_THROTTLE_IP_CLR = 5518; // 8 -const static uint64_t SH_FLD_EN = 5519; // 41 -const static uint64_t SH_FLD_ENABLE = 5520; // 207 -const static uint64_t SH_FLD_ENABLE_0 = 5521; // 1 -const static uint64_t SH_FLD_ENABLE_0_7 = 5522; // 1 -const static uint64_t SH_FLD_ENABLE_0_7_LEN = 5523; // 1 -const static uint64_t SH_FLD_ENABLE_1 = 5524; // 1 -const static uint64_t SH_FLD_ENABLE_2 = 5525; // 1 -const static uint64_t SH_FLD_ENABLE_3 = 5526; // 1 -const static uint64_t SH_FLD_ENABLE_64_128B_READ = 5527; // 4 -const static uint64_t SH_FLD_ENABLE_AUX_PORT_UNUSED = 5528; // 2 -const static uint64_t SH_FLD_ENABLE_BER_TEST = 5529; // 4 -const static uint64_t SH_FLD_ENABLE_BUSY_COUNTERS = 5530; // 8 -const static uint64_t SH_FLD_ENABLE_CENTAUR_CHECKSTOP_COMMAND = 5531; // 4 -const static uint64_t SH_FLD_ENABLE_CENTAUR_PERFMON_START_COMMAND = 5532; // 4 -const static uint64_t SH_FLD_ENABLE_CENTAUR_PERFMON_STOP_COMMAND = 5533; // 4 -const static uint64_t SH_FLD_ENABLE_CENTAUR_SYNC = 5534; // 4 -const static uint64_t SH_FLD_ENABLE_CENTAUR_TRACESTOP_COMMAND = 5535; // 4 -const static uint64_t SH_FLD_ENABLE_CHANNEL_ARB_DISABLE_HP_OP_LFSR = 5536; // 4 -const static uint64_t SH_FLD_ENABLE_CHANNEL_ARB_FORCE_WR_HP_LFSR = 5537; // 4 -const static uint64_t SH_FLD_ENABLE_CLEAN = 5538; // 8 -const static uint64_t SH_FLD_ENABLE_CLR_ERR_CMD = 5539; // 1 -const static uint64_t SH_FLD_ENABLE_CM_COARSE_CAL = 5540; // 6 -const static uint64_t SH_FLD_ENABLE_CM_FINE_CAL = 5541; // 6 -const static uint64_t SH_FLD_ENABLE_CQ_PMU_COUNTING = 5542; // 1 -const static uint64_t SH_FLD_ENABLE_CQ_TRACE = 5543; // 1 -const static uint64_t SH_FLD_ENABLE_CRC_BYPASS_ALWAYS = 5544; // 4 -const static uint64_t SH_FLD_ENABLE_CRC_ECC_BPASS_NODAL_ONLY = 5545; // 4 -const static uint64_t SH_FLD_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 5546; // 6 -const static uint64_t SH_FLD_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 5547; // 6 -const static uint64_t SH_FLD_ENABLE_CTLE_COARSE_CAL = 5548; // 6 -const static uint64_t SH_FLD_ENABLE_CTLE_EDGE_OFFSET_CAL = 5549; // 2 -const static uint64_t SH_FLD_ENABLE_CTLE_EDGE_TRACK_ONLY = 5550; // 4 -const static uint64_t SH_FLD_ENABLE_DAC_H1_CAL = 5551; // 6 -const static uint64_t SH_FLD_ENABLE_DAC_H1_TO_A_CAL = 5552; // 4 -const static uint64_t SH_FLD_ENABLE_DDC = 5553; // 6 -const static uint64_t SH_FLD_ENABLE_DEBUG_BUS = 5554; // 1 -const static uint64_t SH_FLD_ENABLE_DFE_H1_CAL = 5555; // 6 -const static uint64_t SH_FLD_ENABLE_DFE_H2_H12_CAL = 5556; // 4 -const static uint64_t SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP = 5557; // 4 -const static uint64_t SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 5558; // 4 -const static uint64_t SH_FLD_ENABLE_DFE_VOLTAGE_MODE = 5559; // 4 -const static uint64_t SH_FLD_ENABLE_DISABLE_PREFETCH_FOR_MIRROR_READS = 5560; // 4 -const static uint64_t SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ = 5561; // 4 -const static uint64_t SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ = 5562; // 4 -const static uint64_t SH_FLD_ENABLE_DONE_SIGNALING = 5563; // 4 -const static uint64_t SH_FLD_ENABLE_DYNAMIC_PF_USAGE = 5564; // 8 -const static uint64_t SH_FLD_ENABLE_DYNAMIC_WR_USAGE = 5565; // 8 -const static uint64_t SH_FLD_ENABLE_EG_PMU_COUNTING = 5566; // 1 -const static uint64_t SH_FLD_ENABLE_EG_TRACE = 5567; // 1 -const static uint64_t SH_FLD_ENABLE_EMER_THROTTLE = 5568; // 4 -const static uint64_t SH_FLD_ENABLE_FINAL_L2U_ADJ = 5569; // 4 -const static uint64_t SH_FLD_ENABLE_FIR_HOST_ATTN = 5570; // 4 -const static uint64_t SH_FLD_ENABLE_FIR_SPEC_ATTN = 5571; // 4 -const static uint64_t SH_FLD_ENABLE_FSAFE_UPON_HEARTBEAT_LOSS = 5572; // 6 -const static uint64_t SH_FLD_ENABLE_GCR_OFL_BUFF = 5573; // 4 -const static uint64_t SH_FLD_ENABLE_GLB_PULSE = 5574; // 1 -const static uint64_t SH_FLD_ENABLE_GLOBAL_RUN = 5575; // 2 -const static uint64_t SH_FLD_ENABLE_H1AP_TWEAK = 5576; // 6 -const static uint64_t SH_FLD_ENABLE_HW_ERROR_RECOVERY = 5577; // 5 -const static uint64_t SH_FLD_ENABLE_INTEG_LATCH_OFFSET_CAL = 5578; // 6 -const static uint64_t SH_FLD_ENABLE_IN_PMU_COUNTING = 5579; // 1 -const static uint64_t SH_FLD_ENABLE_IN_TRACE = 5580; // 1 -const static uint64_t SH_FLD_ENABLE_IPOLL_AND_DMA = 5581; // 3 -const static uint64_t SH_FLD_ENABLE_LEN = 5582; // 3 -const static uint64_t SH_FLD_ENABLE_MEMORY_BACKING = 5583; // 6 -const static uint64_t SH_FLD_ENABLE_PARITY_CHECK = 5584; // 3 -const static uint64_t SH_FLD_ENABLE_PB_PERFMON_COMMAND = 5585; // 4 -const static uint64_t SH_FLD_ENABLE_PB_SWITCH_AB = 5586; // 1 -const static uint64_t SH_FLD_ENABLE_PB_SWITCH_CD = 5587; // 1 -const static uint64_t SH_FLD_ENABLE_PECE = 5588; // 24 -const static uint64_t SH_FLD_ENABLE_PF_DROP = 5589; // 4 -const static uint64_t SH_FLD_ENABLE_PF_DROP_CMDLIST = 5590; // 4 -const static uint64_t SH_FLD_ENABLE_PF_DROP_SRQ = 5591; // 4 -const static uint64_t SH_FLD_ENABLE_PREFETCH_PROMOTE = 5592; // 4 -const static uint64_t SH_FLD_ENABLE_READ_DATA_FROM_AMOC = 5593; // 8 -const static uint64_t SH_FLD_ENABLE_READ_DATA_FROM_AMOC_LEN = 5594; // 8 -const static uint64_t SH_FLD_ENABLE_READ_LFSR_DATA = 5595; // 4 -const static uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TOD = 5596; // 1 -const static uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER = 5597; // 1 -const static uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER_LEN = 5598; // 1 -const static uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_DISP = 5599; // 8 -const static uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_NSQ = 5600; // 8 -const static uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_SQ = 5601; // 8 -const static uint64_t SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS = 5602; // 3 -const static uint64_t SH_FLD_ENABLE_REMAP = 5603; // 1 -const static uint64_t SH_FLD_ENABLE_RESULT_CHECK = 5604; // 4 -const static uint64_t SH_FLD_ENABLE_RG_PMU_COUNTING = 5605; // 1 -const static uint64_t SH_FLD_ENABLE_RG_TRACE = 5606; // 1 -const static uint64_t SH_FLD_ENABLE_SCRD_FR_RXRF = 5607; // 1 -const static uint64_t SH_FLD_ENABLE_SCWR_TO_RXRF = 5608; // 1 -const static uint64_t SH_FLD_ENABLE_SCWR_TO_TXRF = 5609; // 1 -const static uint64_t SH_FLD_ENABLE_STREAMING_MODE = 5610; // 2 -const static uint64_t SH_FLD_ENABLE_TRC_GLB_TRIG0 = 5611; // 1 -const static uint64_t SH_FLD_ENABLE_TRC_GLB_TRIG1 = 5612; // 1 -const static uint64_t SH_FLD_ENABLE_TTYPE_DECODE = 5613; // 2 -const static uint64_t SH_FLD_ENABLE_VGA_AMAX_MODE = 5614; // 6 -const static uint64_t SH_FLD_ENABLE_VGA_CAL = 5615; // 6 -const static uint64_t SH_FLD_ENABLE_VGA_EDGE_OFFSET_CAL = 5616; // 2 -const static uint64_t SH_FLD_ENABLE_WC_PMU_COUNTING = 5617; // 1 -const static uint64_t SH_FLD_ENABLE_WC_TRACE = 5618; // 1 -const static uint64_t SH_FLD_ENABLE_ZCAL = 5619; // 8 -const static uint64_t SH_FLD_ENA_COARSE_RD = 5620; // 8 -const static uint64_t SH_FLD_ENA_CUSTOM_RD = 5621; // 8 -const static uint64_t SH_FLD_ENA_CUSTOM_WR = 5622; // 8 -const static uint64_t SH_FLD_ENA_DIGITAL_EYE = 5623; // 8 -const static uint64_t SH_FLD_ENA_DQS_ALIGN = 5624; // 16 -const static uint64_t SH_FLD_ENA_INITIAL_COARSE_WR = 5625; // 8 -const static uint64_t SH_FLD_ENA_INITIAL_PAT_WR = 5626; // 8 -const static uint64_t SH_FLD_ENA_RANK = 5627; // 8 -const static uint64_t SH_FLD_ENA_RANK_LEN = 5628; // 8 -const static uint64_t SH_FLD_ENA_RANK_PAIR = 5629; // 16 -const static uint64_t SH_FLD_ENA_RANK_PAIR_LEN = 5630; // 16 -const static uint64_t SH_FLD_ENA_RDCLK_ALIGN = 5631; // 16 -const static uint64_t SH_FLD_ENA_READ_CTR = 5632; // 16 -const static uint64_t SH_FLD_ENA_SYSCLK_ALIGN = 5633; // 8 -const static uint64_t SH_FLD_ENA_WRITE_CTR = 5634; // 8 -const static uint64_t SH_FLD_ENA_WR_LEVEL = 5635; // 8 -const static uint64_t SH_FLD_ENA_ZCAL = 5636; // 8 -const static uint64_t SH_FLD_END = 5637; // 64 -const static uint64_t SH_FLD_ENDABLE_PMU_CNT_RESET = 5638; // 1 -const static uint64_t SH_FLD_ENDPOINTS = 5639; // 1 -const static uint64_t SH_FLD_END_LANE_ID = 5640; // 8 -const static uint64_t SH_FLD_END_LANE_ID_LEN = 5641; // 8 -const static uint64_t SH_FLD_ENH_MODE_0 = 5642; // 1 -const static uint64_t SH_FLD_ENH_MODE_1 = 5643; // 1 -const static uint64_t SH_FLD_ENH_MODE_2 = 5644; // 1 -const static uint64_t SH_FLD_ENH_MODE_3 = 5645; // 1 -const static uint64_t SH_FLD_ENOP = 5646; // 43 -const static uint64_t SH_FLD_ENOP_FORCE_SG = 5647; // 43 -const static uint64_t SH_FLD_ENOP_LEN = 5648; // 43 -const static uint64_t SH_FLD_ENOP_WAIT = 5649; // 43 -const static uint64_t SH_FLD_ENOP_WAIT_LEN = 5650; // 43 -const static uint64_t SH_FLD_ENTRIES = 5651; // 1 -const static uint64_t SH_FLD_ENTRIES_LEN = 5652; // 1 -const static uint64_t SH_FLD_ENTRY = 5653; // 75 -const static uint64_t SH_FLD_ENTRY_LEN = 5654; // 75 -const static uint64_t SH_FLD_ENTRY_SEL_0_5 = 5655; // 1 -const static uint64_t SH_FLD_ENTRY_SEL_0_5_LEN = 5656; // 1 -const static uint64_t SH_FLD_EN_ATTN = 5657; // 24 -const static uint64_t SH_FLD_EN_CHARB_STALL = 5658; // 4 -const static uint64_t SH_FLD_EN_DBG = 5659; // 4 -const static uint64_t SH_FLD_EN_EVENT_COUNT = 5660; // 1 -const static uint64_t SH_FLD_EN_INSTRUC_TRACE = 5661; // 24 -const static uint64_t SH_FLD_EN_MARKER_ACK = 5662; // 1 -const static uint64_t SH_FLD_EN_OR_DIS_WRITE_PROTECTION = 5663; // 1 -const static uint64_t SH_FLD_EN_OR_DIS_WRITE_PROTECTION_LEN = 5664; // 1 -const static uint64_t SH_FLD_EN_POLL_BACKOFF = 5665; // 1 -const static uint64_t SH_FLD_EN_RANDOM_BACKOFF = 5666; // 1 -const static uint64_t SH_FLD_EN_RESET_DD2_FIX_DIS = 5667; // 8 -const static uint64_t SH_FLD_EN_RESET_WR_DELAY_WL = 5668; // 8 -const static uint64_t SH_FLD_EN_RISCTRACE = 5669; // 17 -const static uint64_t SH_FLD_EN_SECOND_WRBUF = 5670; // 1 -const static uint64_t SH_FLD_EN_SLV_FAIRNESS = 5671; // 1 -const static uint64_t SH_FLD_EN_SPEC_CILD = 5672; // 1 -const static uint64_t SH_FLD_EN_TRACE_FULL_IVA = 5673; // 17 -const static uint64_t SH_FLD_EN_WIDE_TRACE = 5674; // 16 -const static uint64_t SH_FLD_EN_WT4CR_EPS_ON_LCO = 5675; // 12 -const static uint64_t SH_FLD_EN_WT4CR_EXTENDED_MODE = 5676; // 12 -const static uint64_t SH_FLD_EPOCH_TEST_VECTOR = 5677; // 2 -const static uint64_t SH_FLD_EPOCH_TEST_VECTOR_LEN = 5678; // 2 -const static uint64_t SH_FLD_EPOCH_VALUE = 5679; // 2 -const static uint64_t SH_FLD_EPOCH_VALUE_LEN = 5680; // 2 -const static uint64_t SH_FLD_EPS_CNT_USE_DIVIDER_EN = 5681; // 12 -const static uint64_t SH_FLD_EPS_DIVIDER_MODE = 5682; // 12 -const static uint64_t SH_FLD_EPS_DIVIDER_MODE_LEN = 5683; // 12 -const static uint64_t SH_FLD_EPS_MODE_SEL = 5684; // 12 -const static uint64_t SH_FLD_EPS_STEP_MODE = 5685; // 12 -const static uint64_t SH_FLD_EPS_STEP_MODE_LEN = 5686; // 12 -const static uint64_t SH_FLD_EQC_CILOAD = 5687; // 1 -const static uint64_t SH_FLD_EQC_CILOAD_LEN = 5688; // 1 -const static uint64_t SH_FLD_EQC_CISTORE = 5689; // 1 -const static uint64_t SH_FLD_EQC_CISTORE_LEN = 5690; // 1 -const static uint64_t SH_FLD_EQC_DMA = 5691; // 1 -const static uint64_t SH_FLD_EQC_DMA_LEN = 5692; // 1 -const static uint64_t SH_FLD_EQC_EOI_EQP = 5693; // 1 -const static uint64_t SH_FLD_EQC_EOI_EQP_LEN = 5694; // 1 -const static uint64_t SH_FLD_EQD_DMA_READ = 5695; // 1 -const static uint64_t SH_FLD_EQD_DMA_READ_LEN = 5696; // 1 -const static uint64_t SH_FLD_EQD_DMA_WRITE = 5697; // 1 -const static uint64_t SH_FLD_EQD_DMA_WRITE_LEN = 5698; // 1 -const static uint64_t SH_FLD_EQ_POST = 5699; // 1 -const static uint64_t SH_FLD_EQ_POST_LEN = 5700; // 1 -const static uint64_t SH_FLD_ERAT_ARRAY_CE = 5701; // 1 -const static uint64_t SH_FLD_ERAT_ARRAY_PE = 5702; // 1 -const static uint64_t SH_FLD_ERAT_ARRAY_SUE = 5703; // 1 -const static uint64_t SH_FLD_ERAT_ARRAY_UE = 5704; // 1 -const static uint64_t SH_FLD_ERAT_CICO_HANG = 5705; // 1 -const static uint64_t SH_FLD_ERAT_CNTRL_ERR = 5706; // 1 -const static uint64_t SH_FLD_ERAT_LOCAL_CSTOP = 5707; // 1 -const static uint64_t SH_FLD_ERAT_MUX_SELECT = 5708; // 1 -const static uint64_t SH_FLD_ERAT_MUX_SELECT_LEN = 5709; // 1 -const static uint64_t SH_FLD_ERR = 5710; // 24 -const static uint64_t SH_FLD_ERR0 = 5711; // 16 -const static uint64_t SH_FLD_ERR0_LEN = 5712; // 16 -const static uint64_t SH_FLD_ERR501 = 5713; // 43 -const static uint64_t SH_FLD_ERROR = 5714; // 121 -const static uint64_t SH_FLD_ERRORS = 5715; // 43 -const static uint64_t SH_FLD_ERRORS_LEN = 5716; // 43 -const static uint64_t SH_FLD_ERROR_0 = 5717; // 1 -const static uint64_t SH_FLD_ERROR_1 = 5718; // 1 -const static uint64_t SH_FLD_ERROR_2 = 5719; // 1 -const static uint64_t SH_FLD_ERROR_3 = 5720; // 1 -const static uint64_t SH_FLD_ERROR_4 = 5721; // 1 -const static uint64_t SH_FLD_ERROR_5 = 5722; // 1 -const static uint64_t SH_FLD_ERROR_ADDR = 5723; // 4 -const static uint64_t SH_FLD_ERROR_ADDRESS = 5724; // 2 -const static uint64_t SH_FLD_ERROR_ADDRESS_LEN = 5725; // 2 -const static uint64_t SH_FLD_ERROR_ADDR_LEN = 5726; // 4 -const static uint64_t SH_FLD_ERROR_COARSE_RD = 5727; // 8 -const static uint64_t SH_FLD_ERROR_CONFIG = 5728; // 6 -const static uint64_t SH_FLD_ERROR_CONFIG_LEN = 5729; // 6 -const static uint64_t SH_FLD_ERROR_CUSTOM_RD = 5730; // 8 -const static uint64_t SH_FLD_ERROR_CUSTOM_WR = 5731; // 8 -const static uint64_t SH_FLD_ERROR_DIGITAL_EYE = 5732; // 8 -const static uint64_t SH_FLD_ERROR_DQS_ALIGN = 5733; // 8 -const static uint64_t SH_FLD_ERROR_FINE = 5734; // 8 -const static uint64_t SH_FLD_ERROR_INITIAL_COARSE_WR = 5735; // 8 -const static uint64_t SH_FLD_ERROR_INITIAL_PAT_WRITE = 5736; // 8 -const static uint64_t SH_FLD_ERROR_INJECT = 5737; // 1 -const static uint64_t SH_FLD_ERROR_INJECT_ENABLE = 5738; // 1 -const static uint64_t SH_FLD_ERROR_INJECT_LEN = 5739; // 1 -const static uint64_t SH_FLD_ERROR_LEN = 5740; // 15 -const static uint64_t SH_FLD_ERROR_MASK = 5741; // 43 -const static uint64_t SH_FLD_ERROR_MASK_LEN = 5742; // 43 -const static uint64_t SH_FLD_ERROR_RDCLK_ALIGN = 5743; // 8 -const static uint64_t SH_FLD_ERROR_READ_CTR = 5744; // 8 -const static uint64_t SH_FLD_ERROR_RECOVERY_COMPLETE = 5745; // 2 -const static uint64_t SH_FLD_ERROR_RECOVERY_INITIATED = 5746; // 2 -const static uint64_t SH_FLD_ERROR_STATE = 5747; // 4 -const static uint64_t SH_FLD_ERROR_WRITE_CTR = 5748; // 8 -const static uint64_t SH_FLD_ERROR_WR_LEVEL = 5749; // 8 -const static uint64_t SH_FLD_ERRS = 5750; // 260 -const static uint64_t SH_FLD_ERRS_INJ = 5751; // 4 -const static uint64_t SH_FLD_ERRS_INJ_LEN = 5752; // 4 -const static uint64_t SH_FLD_ERRS_LEN = 5753; // 144 -const static uint64_t SH_FLD_ERR_ADDR_BEYOND_RANGE = 5754; // 1 -const static uint64_t SH_FLD_ERR_ADDR_OVERLAP = 5755; // 1 -const static uint64_t SH_FLD_ERR_BRK0 = 5756; // 1 -const static uint64_t SH_FLD_ERR_BRK0_LEN = 5757; // 1 -const static uint64_t SH_FLD_ERR_BRK1 = 5758; // 1 -const static uint64_t SH_FLD_ERR_BRK1_LEN = 5759; // 1 -const static uint64_t SH_FLD_ERR_BRK2 = 5760; // 1 -const static uint64_t SH_FLD_ERR_BRK2_LEN = 5761; // 1 -const static uint64_t SH_FLD_ERR_BRK3 = 5762; // 1 -const static uint64_t SH_FLD_ERR_BRK3_LEN = 5763; // 1 -const static uint64_t SH_FLD_ERR_BRK4 = 5764; // 1 -const static uint64_t SH_FLD_ERR_BRK4_LEN = 5765; // 1 -const static uint64_t SH_FLD_ERR_BRK5 = 5766; // 1 -const static uint64_t SH_FLD_ERR_BRK5_LEN = 5767; // 1 -const static uint64_t SH_FLD_ERR_CMD_OVERRUN = 5768; // 1 -const static uint64_t SH_FLD_ERR_FSM_DP18 = 5769; // 8 -const static uint64_t SH_FLD_ERR_FSM_DP18_LEN = 5770; // 8 -const static uint64_t SH_FLD_ERR_INJ = 5771; // 252 -const static uint64_t SH_FLD_ERR_INJ_ACTION = 5772; // 2 -const static uint64_t SH_FLD_ERR_INJ_ARRAY_SEL = 5773; // 2 -const static uint64_t SH_FLD_ERR_INJ_ARRAY_SEL_LEN = 5774; // 2 -const static uint64_t SH_FLD_ERR_INJ_A_BER_SEL = 5775; // 6 -const static uint64_t SH_FLD_ERR_INJ_A_BER_SEL_LEN = 5776; // 6 -const static uint64_t SH_FLD_ERR_INJ_A_COARSE_SEL = 5777; // 6 -const static uint64_t SH_FLD_ERR_INJ_A_COARSE_SEL_LEN = 5778; // 6 -const static uint64_t SH_FLD_ERR_INJ_A_ENABLE = 5779; // 116 -const static uint64_t SH_FLD_ERR_INJ_A_FINE_SEL = 5780; // 6 -const static uint64_t SH_FLD_ERR_INJ_A_FINE_SEL_LEN = 5781; // 6 -const static uint64_t SH_FLD_ERR_INJ_B_BER_SEL = 5782; // 6 -const static uint64_t SH_FLD_ERR_INJ_B_BER_SEL_LEN = 5783; // 6 -const static uint64_t SH_FLD_ERR_INJ_B_COARSE_SEL = 5784; // 6 -const static uint64_t SH_FLD_ERR_INJ_B_COARSE_SEL_LEN = 5785; // 6 -const static uint64_t SH_FLD_ERR_INJ_B_ENABLE = 5786; // 116 -const static uint64_t SH_FLD_ERR_INJ_B_FINE_SEL = 5787; // 6 -const static uint64_t SH_FLD_ERR_INJ_B_FINE_SEL_LEN = 5788; // 6 -const static uint64_t SH_FLD_ERR_INJ_CLOCK_ENABLE = 5789; // 6 -const static uint64_t SH_FLD_ERR_INJ_ENABLE = 5790; // 8 -const static uint64_t SH_FLD_ERR_INJ_LEN = 5791; // 136 -const static uint64_t SH_FLD_ERR_INJ_SLS_ALL_CMD = 5792; // 4 -const static uint64_t SH_FLD_ERR_INJ_SLS_CMD = 5793; // 4 -const static uint64_t SH_FLD_ERR_INJ_SLS_CMD_LEN = 5794; // 4 -const static uint64_t SH_FLD_ERR_INJ_SLS_MODE = 5795; // 4 -const static uint64_t SH_FLD_ERR_INJ_SLS_RECAL = 5796; // 4 -const static uint64_t SH_FLD_ERR_INJ_STATUS = 5797; // 2 -const static uint64_t SH_FLD_ERR_INJ_TYPE = 5798; // 2 -const static uint64_t SH_FLD_ERR_REG_DP18 = 5799; // 8 -const static uint64_t SH_FLD_ERR_REG_DP18_LEN = 5800; // 8 -const static uint64_t SH_FLD_ERR_SET0 = 5801; // 8 -const static uint64_t SH_FLD_ERR_SET1 = 5802; // 8 -const static uint64_t SH_FLD_ERR_SET2 = 5803; // 8 -const static uint64_t SH_FLD_ERR_SET3 = 5804; // 8 -const static uint64_t SH_FLD_ERR_SET4 = 5805; // 8 -const static uint64_t SH_FLD_ERR_SET5 = 5806; // 8 -const static uint64_t SH_FLD_ESB_OR_LSI_INTERRUPTS = 5807; // 1 -const static uint64_t SH_FLD_ESC1_PRIORITY = 5808; // 1 -const static uint64_t SH_FLD_ESC1_PRIORITY_LEN = 5809; // 1 -const static uint64_t SH_FLD_ESC1_RSD = 5810; // 1 -const static uint64_t SH_FLD_ESC1_RSD_LEN = 5811; // 1 -const static uint64_t SH_FLD_ESC2_PRIORITY = 5812; // 1 -const static uint64_t SH_FLD_ESC2_PRIORITY_LEN = 5813; // 1 -const static uint64_t SH_FLD_ESC2_RSD = 5814; // 1 -const static uint64_t SH_FLD_ESC2_RSD_LEN = 5815; // 1 -const static uint64_t SH_FLD_ESCAPE_ADDRESS = 5816; // 1 -const static uint64_t SH_FLD_ESCAPE_ADDRESS_LEN = 5817; // 1 -const static uint64_t SH_FLD_EVENT = 5818; // 6 -const static uint64_t SH_FLD_EVENT0 = 5819; // 3 -const static uint64_t SH_FLD_EVENT0_LEN = 5820; // 3 -const static uint64_t SH_FLD_EVENT0_SEL = 5821; // 2 -const static uint64_t SH_FLD_EVENT1 = 5822; // 3 -const static uint64_t SH_FLD_EVENT1_LEN = 5823; // 3 -const static uint64_t SH_FLD_EVENT1_SEL = 5824; // 2 -const static uint64_t SH_FLD_EVENT1_SEL_LEN = 5825; // 2 -const static uint64_t SH_FLD_EVENT2 = 5826; // 3 -const static uint64_t SH_FLD_EVENT2HALT_DELAY = 5827; // 1 -const static uint64_t SH_FLD_EVENT2HALT_DELAY_LEN = 5828; // 1 -const static uint64_t SH_FLD_EVENT2HALT_EN = 5829; // 1 -const static uint64_t SH_FLD_EVENT2HALT_EN_LEN = 5830; // 1 -const static uint64_t SH_FLD_EVENT2HALT_GPE0 = 5831; // 1 -const static uint64_t SH_FLD_EVENT2HALT_GPE1 = 5832; // 1 -const static uint64_t SH_FLD_EVENT2HALT_GPE2 = 5833; // 1 -const static uint64_t SH_FLD_EVENT2HALT_GPE3 = 5834; // 1 -const static uint64_t SH_FLD_EVENT2HALT_HALT_STATE = 5835; // 1 -const static uint64_t SH_FLD_EVENT2HALT_MODE = 5836; // 1 -const static uint64_t SH_FLD_EVENT2HALT_MODE_LEN = 5837; // 1 -const static uint64_t SH_FLD_EVENT2HALT_OCC = 5838; // 1 -const static uint64_t SH_FLD_EVENT2_LEN = 5839; // 3 -const static uint64_t SH_FLD_EVENT2_SEL = 5840; // 2 -const static uint64_t SH_FLD_EVENT2_SEL_LEN = 5841; // 2 -const static uint64_t SH_FLD_EVENT3 = 5842; // 3 -const static uint64_t SH_FLD_EVENT3_LEN = 5843; // 3 -const static uint64_t SH_FLD_EVENT3_SEL = 5844; // 2 -const static uint64_t SH_FLD_EVENT3_SEL_LEN = 5845; // 2 -const static uint64_t SH_FLD_EVENTCNT = 5846; // 3 -const static uint64_t SH_FLD_EVENTCNT_LEN = 5847; // 3 -const static uint64_t SH_FLD_EVENT_BUS_EN = 5848; // 4 -const static uint64_t SH_FLD_EVENT_BUS_ENABLE = 5849; // 4 -const static uint64_t SH_FLD_EVENT_BUS_EN_LEN = 5850; // 4 -const static uint64_t SH_FLD_EVENT_BUS_SELECTS = 5851; // 8 -const static uint64_t SH_FLD_EVENT_BUS_SELECTS_LEN = 5852; // 8 -const static uint64_t SH_FLD_EVENT_LEN = 5853; // 6 -const static uint64_t SH_FLD_EVENT_MUX_SELECTS = 5854; // 24 -const static uint64_t SH_FLD_EVENT_MUX_SELECTS_LEN = 5855; // 24 -const static uint64_t SH_FLD_EXBIST_MODE = 5856; // 6 -const static uint64_t SH_FLD_EXIT_1 = 5857; // 64 -const static uint64_t SH_FLD_EXIT_CRITERION_A_N = 5858; // 96 -const static uint64_t SH_FLD_EXTADDR = 5859; // 6 -const static uint64_t SH_FLD_EXTADDR_LEN = 5860; // 6 -const static uint64_t SH_FLD_EXTERNAL_TRAP = 5861; // 1 -const static uint64_t SH_FLD_EXTERNAL_XSTOP = 5862; // 4 -const static uint64_t SH_FLD_EXTRA_CMD_SPACING_0_2 = 5863; // 1 -const static uint64_t SH_FLD_EXTRA_CMD_SPACING_0_2_LEN = 5864; // 1 -const static uint64_t SH_FLD_EXTRA_DAT_SPACING_0_3 = 5865; // 1 -const static uint64_t SH_FLD_EXTRA_DAT_SPACING_0_3_LEN = 5866; // 1 -const static uint64_t SH_FLD_EXT_EBB_EXIT_ENABLE = 5867; // 96 -const static uint64_t SH_FLD_EXT_EXIT_ENABLE = 5868; // 96 -const static uint64_t SH_FLD_EXT_INTERRUPT = 5869; // 1 -const static uint64_t SH_FLD_EXT_RESUME_EXIT_ENABLE = 5870; // 96 -const static uint64_t SH_FLD_EYE_OPT_DONE = 5871; // 4 -const static uint64_t SH_FLD_EYE_OPT_FAILED = 5872; // 4 -const static uint64_t SH_FLD_E_BIST_EN = 5873; // 2 -const static uint64_t SH_FLD_E_CONTROLS = 5874; // 48 -const static uint64_t SH_FLD_E_CONTROLS_LEN = 5875; // 48 -const static uint64_t SH_FLD_E_CTLE_COARSE = 5876; // 48 -const static uint64_t SH_FLD_E_CTLE_COARSE_LEN = 5877; // 48 -const static uint64_t SH_FLD_E_CTLE_GAIN = 5878; // 48 -const static uint64_t SH_FLD_E_CTLE_GAIN_LEN = 5879; // 48 -const static uint64_t SH_FLD_E_EVEN_INTEG_FINE_GAIN = 5880; // 48 -const static uint64_t SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN = 5881; // 48 -const static uint64_t SH_FLD_E_INTEG_COARSE_GAIN = 5882; // 48 -const static uint64_t SH_FLD_E_INTEG_COARSE_GAIN_LEN = 5883; // 48 -const static uint64_t SH_FLD_E_ODD_INTEG_FINE_GAIN = 5884; // 48 -const static uint64_t SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN = 5885; // 48 -const static uint64_t SH_FLD_E_OFFSET = 5886; // 48 -const static uint64_t SH_FLD_E_OFFSET_E = 5887; // 48 -const static uint64_t SH_FLD_E_OFFSET_E_LEN = 5888; // 48 -const static uint64_t SH_FLD_E_OFFSET_LEN = 5889; // 48 -const static uint64_t SH_FLD_E_TARG_MIN = 5890; // 1 -const static uint64_t SH_FLD_E_TARG_MIN_LEN = 5891; // 1 -const static uint64_t SH_FLD_FACTOR = 5892; // 24 -const static uint64_t SH_FLD_FACTOR_LEN = 5893; // 24 -const static uint64_t SH_FLD_FAIL = 5894; // 4 -const static uint64_t SH_FLD_FAILED_LINK_ON_INTERRUPT = 5895; // 1 -const static uint64_t SH_FLD_FAILING_OPB_MASTER_ACT = 5896; // 3 -const static uint64_t SH_FLD_FAILING_OPB_MASTER_ACT_LEN = 5897; // 3 -const static uint64_t SH_FLD_FAILING_OPB_MASTER_FRST = 5898; // 3 -const static uint64_t SH_FLD_FAILING_OPB_MASTER_FRST_LEN = 5899; // 3 -const static uint64_t SH_FLD_FAIL_REG = 5900; // 1 -const static uint64_t SH_FLD_FAIL_REG_LEN = 5901; // 1 -const static uint64_t SH_FLD_FAIL_TYPE = 5902; // 2 -const static uint64_t SH_FLD_FAIL_TYPE_LEN = 5903; // 2 -const static uint64_t SH_FLD_FARB_CAL_RECVFSM_1HOT = 5904; // 8 -const static uint64_t SH_FLD_FARB_PE = 5905; // 8 -const static uint64_t SH_FLD_FARR = 5906; // 43 -const static uint64_t SH_FLD_FASTPATH_LIMIT = 5907; // 8 -const static uint64_t SH_FLD_FASTPATH_LIMIT_LEN = 5908; // 8 -const static uint64_t SH_FLD_FAST_SIM_CNTR = 5909; // 8 -const static uint64_t SH_FLD_FBC = 5910; // 2 -const static uint64_t SH_FLD_FBC_ADDRESS = 5911; // 1 -const static uint64_t SH_FLD_FBC_ADDRESS_ERROR = 5912; // 1 -const static uint64_t SH_FLD_FBC_ADDRESS_LEN = 5913; // 1 -const static uint64_t SH_FLD_FBC_ADDR_DONE = 5914; // 1 -const static uint64_t SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT = 5915; // 1 -const static uint64_t SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN = 5916; // 1 -const static uint64_t SH_FLD_FBC_AUTOINC_ERROR = 5917; // 1 -const static uint64_t SH_FLD_FBC_AUTO_INC = 5918; // 1 -const static uint64_t SH_FLD_FBC_AXTYPE = 5919; // 1 -const static uint64_t SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT = 5920; // 1 -const static uint64_t SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT_LEN = 5921; // 1 -const static uint64_t SH_FLD_FBC_BUS0_STG1_SEL = 5922; // 1 -const static uint64_t SH_FLD_FBC_BUS0_STG2_SEL = 5923; // 1 -const static uint64_t SH_FLD_FBC_BUS1_STG1_SEL = 5924; // 1 -const static uint64_t SH_FLD_FBC_BUS1_STG2_SEL = 5925; // 1 -const static uint64_t SH_FLD_FBC_CLEAR_STATUS = 5926; // 1 -const static uint64_t SH_FLD_FBC_COMMAND_ERROR = 5927; // 1 -const static uint64_t SH_FLD_FBC_CRESP_VALUE = 5928; // 1 -const static uint64_t SH_FLD_FBC_CRESP_VALUE_LEN = 5929; // 1 -const static uint64_t SH_FLD_FBC_DATA_DONE = 5930; // 1 -const static uint64_t SH_FLD_FBC_DATA_ONLY = 5931; // 1 -const static uint64_t SH_FLD_FBC_DIN_ECC_CHK_DIS = 5932; // 1 -const static uint64_t SH_FLD_FBC_DISABLE = 5933; // 1 -const static uint64_t SH_FLD_FBC_DISABLE_LOCAL_SHORTCUT = 5934; // 1 -const static uint64_t SH_FLD_FBC_DROP_PRIORITY = 5935; // 1 -const static uint64_t SH_FLD_FBC_DROP_PRIORITY_MAX = 5936; // 1 -const static uint64_t SH_FLD_FBC_ECC_CE = 5937; // 1 -const static uint64_t SH_FLD_FBC_ECC_SUE = 5938; // 1 -const static uint64_t SH_FLD_FBC_ECC_UE = 5939; // 1 -const static uint64_t SH_FLD_FBC_LEN = 5940; // 2 -const static uint64_t SH_FLD_FBC_LFSR_DIS = 5941; // 1 -const static uint64_t SH_FLD_FBC_LOCKED = 5942; // 1 -const static uint64_t SH_FLD_FBC_LOCK_ID = 5943; // 1 -const static uint64_t SH_FLD_FBC_LOCK_ID_LEN = 5944; // 1 -const static uint64_t SH_FLD_FBC_OVERRUN_ERROR = 5945; // 1 -const static uint64_t SH_FLD_FBC_OVERWRITE_PBINIT = 5946; // 1 -const static uint64_t SH_FLD_FBC_PBINIT_MISSING = 5947; // 1 -const static uint64_t SH_FLD_FBC_PB_DATA_HANG_ERR = 5948; // 1 -const static uint64_t SH_FLD_FBC_PB_OP_HANG_ERR = 5949; // 1 -const static uint64_t SH_FLD_FBC_PB_UNEXPECT_CRESP_ERR = 5950; // 1 -const static uint64_t SH_FLD_FBC_PB_UNEXPECT_DATA_ERR = 5951; // 1 -const static uint64_t SH_FLD_FBC_PIB_DIRECT = 5952; // 1 -const static uint64_t SH_FLD_FBC_PIB_DIRECT_DONE = 5953; // 1 -const static uint64_t SH_FLD_FBC_PIB_ERROR = 5954; // 1 -const static uint64_t SH_FLD_FBC_PIB_ERROR_LEN = 5955; // 1 -const static uint64_t SH_FLD_FBC_RESET = 5956; // 1 -const static uint64_t SH_FLD_FBC_RESET_FSM = 5957; // 1 -const static uint64_t SH_FLD_FBC_RNW = 5958; // 1 -const static uint64_t SH_FLD_FBC_SCOPE = 5959; // 1 -const static uint64_t SH_FLD_FBC_SCOPE_LEN = 5960; // 1 -const static uint64_t SH_FLD_FBC_START_OP = 5961; // 1 -const static uint64_t SH_FLD_FBC_TSIZE = 5962; // 1 -const static uint64_t SH_FLD_FBC_TSIZE_LEN = 5963; // 1 -const static uint64_t SH_FLD_FBC_TTYPE = 5964; // 1 -const static uint64_t SH_FLD_FBC_TTYPE_LEN = 5965; // 1 -const static uint64_t SH_FLD_FBC_WAIT_CMD_ARBIT = 5966; // 1 -const static uint64_t SH_FLD_FBC_WAIT_PIB_DIRECT = 5967; // 1 -const static uint64_t SH_FLD_FBC_WAIT_RESP = 5968; // 1 -const static uint64_t SH_FLD_FBC_WITH_PBINIT_LOW_WAIT = 5969; // 1 -const static uint64_t SH_FLD_FBC_WITH_POST_INIT = 5970; // 1 -const static uint64_t SH_FLD_FBC_WITH_PRE_QUIESCE = 5971; // 1 -const static uint64_t SH_FLD_FBC_WITH_TM_QUIESCE = 5972; // 1 -const static uint64_t SH_FLD_FBC_XLAT_ECC_CHK_DIS = 5973; // 1 -const static uint64_t SH_FLD_FBC_XLAT_PROT_ERR_CHK_DIS = 5974; // 1 -const static uint64_t SH_FLD_FBC_XLAT_TIMEOUT_CHK_DIS = 5975; // 1 -const static uint64_t SH_FLD_FENCE = 5976; // 4 -const static uint64_t SH_FLD_FENCE1_DC = 5977; // 1 -const static uint64_t SH_FLD_FENCE2_DC = 5978; // 1 -const static uint64_t SH_FLD_FENCE3_DC = 5979; // 1 -const static uint64_t SH_FLD_FENCE4_DC = 5980; // 1 -const static uint64_t SH_FLD_FENCE5_DC = 5981; // 1 -const static uint64_t SH_FLD_FENCE6_DC = 5982; // 1 -const static uint64_t SH_FLD_FENCE_EISR = 5983; // 24 -const static uint64_t SH_FLD_FENCE_EN = 5984; // 43 -const static uint64_t SH_FLD_FENCE_GX_INTERFACE = 5985; // 1 -const static uint64_t SH_FLD_FENCE_IO_INTERFACE = 5986; // 1 -const static uint64_t SH_FLD_FENCE_TLBIE = 5987; // 12 -const static uint64_t SH_FLD_FFE_BOOST_EN = 5988; // 6 -const static uint64_t SH_FLD_FF_BYPASS = 5989; // 6 -const static uint64_t SH_FLD_FF_SLEWRATE = 5990; // 6 -const static uint64_t SH_FLD_FF_SLEWRATE_LEN = 5991; // 6 -const static uint64_t SH_FLD_FGAT = 5992; // 1 -const static uint64_t SH_FLD_FGAT_0 = 5993; // 1 -const static uint64_t SH_FLD_FGAT_1 = 5994; // 1 -const static uint64_t SH_FLD_FGAT_2 = 5995; // 1 -const static uint64_t SH_FLD_FGAT_3 = 5996; // 1 -const static uint64_t SH_FLD_FIFO_BITS_READ0_0 = 5997; // 2 -const static uint64_t SH_FLD_FIFO_BITS_READ0_0_LEN = 5998; // 2 -const static uint64_t SH_FLD_FIFO_BITS_READ0_1 = 5999; // 2 -const static uint64_t SH_FLD_FIFO_BITS_READ0_1_LEN = 6000; // 2 -const static uint64_t SH_FLD_FIFO_BITS_READ0_2 = 6001; // 2 -const static uint64_t SH_FLD_FIFO_BITS_READ0_2_LEN = 6002; // 2 -const static uint64_t SH_FLD_FIFO_BITS_READ0_3 = 6003; // 2 -const static uint64_t SH_FLD_FIFO_BITS_READ0_3_LEN = 6004; // 2 -const static uint64_t SH_FLD_FIFO_DLY_CFG = 6005; // 120 -const static uint64_t SH_FLD_FIFO_DLY_CFG_LEN = 6006; // 120 -const static uint64_t SH_FLD_FIFO_EMPTY = 6007; // 1 -const static uint64_t SH_FLD_FIFO_ENTRY_COUNT = 6008; // 1 -const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_0 = 6009; // 1 -const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_0_LEN = 6010; // 1 -const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_1 = 6011; // 1 -const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_1_LEN = 6012; // 1 -const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_2 = 6013; // 1 -const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_2_LEN = 6014; // 1 -const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_3 = 6015; // 1 -const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_3_LEN = 6016; // 1 -const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_LEN = 6017; // 1 -const static uint64_t SH_FLD_FIFO_EOT_FLAGS = 6018; // 1 -const static uint64_t SH_FLD_FIFO_EOT_FLAGS_LEN = 6019; // 1 -const static uint64_t SH_FLD_FIFO_FINAL_L2U_DLY = 6020; // 4 -const static uint64_t SH_FLD_FIFO_FINAL_L2U_DLY_LEN = 6021; // 4 -const static uint64_t SH_FLD_FIFO_FULL = 6022; // 7 -const static uint64_t SH_FLD_FIFO_HALF_DEPTH_MODE = 6023; // 72 -const static uint64_t SH_FLD_FIFO_HALF_WIDTH_MODE = 6024; // 140 -const static uint64_t SH_FLD_FIFO_INITIAL_L2U_DLY = 6025; // 4 -const static uint64_t SH_FLD_FIFO_INITIAL_L2U_DLY_LEN = 6026; // 4 -const static uint64_t SH_FLD_FIFO_L2U_DLY = 6027; // 188 -const static uint64_t SH_FLD_FIFO_L2U_DLY_LEN = 6028; // 188 -const static uint64_t SH_FLD_FIFO_VALID_FLAGS = 6029; // 1 -const static uint64_t SH_FLD_FIFO_VALID_FLAGS_LEN = 6030; // 1 -const static uint64_t SH_FLD_FILTDIVSEL = 6031; // 3 -const static uint64_t SH_FLD_FILTDIVSEL_LEN = 6032; // 3 -const static uint64_t SH_FLD_FILTER_MODE = 6033; // 6 -const static uint64_t SH_FLD_FILTER_MODE_LEN = 6034; // 6 -const static uint64_t SH_FLD_FINE_CAL_STEP_SIZE = 6035; // 8 -const static uint64_t SH_FLD_FINE_CAL_STEP_SIZE_LEN = 6036; // 8 -const static uint64_t SH_FLD_FIR = 6037; // 49 -const static uint64_t SH_FLD_FIR0_CR0_ATAG_PERR = 6038; // 12 -const static uint64_t SH_FLD_FIR0_CR0_TTAG_PERR = 6039; // 12 -const static uint64_t SH_FLD_FIR0_CR1_ATAG_PERR = 6040; // 12 -const static uint64_t SH_FLD_FIR0_CR1_TTAG_PERR = 6041; // 12 -const static uint64_t SH_FLD_FIR0_CR2_ATAG_PERR = 6042; // 12 -const static uint64_t SH_FLD_FIR0_CR2_TTAG_PERR = 6043; // 12 -const static uint64_t SH_FLD_FIR0_CR3_ATAG_PERR = 6044; // 12 -const static uint64_t SH_FLD_FIR0_CR3_TTAG_PERR = 6045; // 12 -const static uint64_t SH_FLD_FIR0_ILLEGAL_STORE_SIZE = 6046; // 12 -const static uint64_t SH_FLD_FIR0_IMA_FSM_TIMEOUT = 6047; // 12 -const static uint64_t SH_FLD_FIR0_LD_AMO_SEQ = 6048; // 12 -const static uint64_t SH_FLD_FIR0_OVERFLOW = 6049; // 12 -const static uint64_t SH_FLD_FIR0_PBARB_TRASHMODE = 6050; // 12 -const static uint64_t SH_FLD_FIR0_PPE_RD_FSM_TIMEOUT = 6051; // 12 -const static uint64_t SH_FLD_FIR0_PPE_WR_FSM_TIMEOUT = 6052; // 12 -const static uint64_t SH_FLD_FIR0_PURGE_ABORT_LVL_ERR1 = 6053; // 12 -const static uint64_t SH_FLD_FIR0_PURGE_ABORT_LVL_ERR2 = 6054; // 12 -const static uint64_t SH_FLD_FIR0_PURGE_DONE_LVL_ERR1 = 6055; // 12 -const static uint64_t SH_FLD_FIR0_PURGE_LVL_ERR1 = 6056; // 12 -const static uint64_t SH_FLD_FIR0_PURGE_LVL_ERR2 = 6057; // 12 -const static uint64_t SH_FLD_FIR0_SNP0_ADDR_PERR = 6058; // 12 -const static uint64_t SH_FLD_FIR0_SNP0_TTAG_PERR = 6059; // 12 -const static uint64_t SH_FLD_FIR0_SNP1_ADDR_PERR = 6060; // 12 -const static uint64_t SH_FLD_FIR0_SNP1_TTAG_PERR = 6061; // 12 -const static uint64_t SH_FLD_FIR0_TLB_DATA_PAR = 6062; // 12 -const static uint64_t SH_FLD_FIR11_LRU_MEM_INVALID_ABCD = 6063; // 12 -const static uint64_t SH_FLD_FIR11_LRU_MEM_INVALID_EFGH = 6064; // 12 -const static uint64_t SH_FLD_FIR14_B01_BOTH_ACTIVE = 6065; // 12 -const static uint64_t SH_FLD_FIR14_B0_SD_DIR_MULT_HIT = 6066; // 12 -const static uint64_t SH_FLD_FIR14_B1_SD_DIR_MULT_HIT = 6067; // 12 -const static uint64_t SH_FLD_FIR14_B2_SD_DIR_MULT_HIT = 6068; // 12 -const static uint64_t SH_FLD_FIR14_B3_SD_DIR_MULT_HIT = 6069; // 12 -const static uint64_t SH_FLD_FIR14_BAD_FP_MATE = 6070; // 12 -const static uint64_t SH_FLD_FIR14_COX_UNEXP_IDLE_PB_CRESP = 6071; // 12 -const static uint64_t SH_FLD_FIR14_CR0_ATAG_PERR = 6072; // 12 -const static uint64_t SH_FLD_FIR14_CR0_TTAG_PERR = 6073; // 12 -const static uint64_t SH_FLD_FIR14_CR1_ATAG_PERR = 6074; // 12 -const static uint64_t SH_FLD_FIR14_CR1_TTAG_PERR = 6075; // 12 -const static uint64_t SH_FLD_FIR14_CR2_ATAG_PERR = 6076; // 12 -const static uint64_t SH_FLD_FIR14_CR2_TTAG_PERR = 6077; // 12 -const static uint64_t SH_FLD_FIR14_CR3_ATAG_PERR = 6078; // 12 -const static uint64_t SH_FLD_FIR14_CR3_TTAG_PERR = 6079; // 12 -const static uint64_t SH_FLD_FIR14_DW_SET_REF_WITH_FLAG_IDLE = 6080; // 12 -const static uint64_t SH_FLD_FIR14_DW_SET_SI_BY_MACH = 6081; // 12 -const static uint64_t SH_FLD_FIR14_HANG_WAITING_FOR_FP_MATE = 6082; // 12 -const static uint64_t SH_FLD_FIR14_IFU_MULT_REQ = 6083; // 12 -const static uint64_t SH_FLD_FIR14_INVALID_SNP_CPS_STATU_RTN = 6084; // 12 -const static uint64_t SH_FLD_FIR14_KILL_REF_WITH_FLAG_IDLE = 6085; // 12 -const static uint64_t SH_FLD_FIR14_L3PF_MACH_DONE = 6086; // 12 -const static uint64_t SH_FLD_FIR14_L3PF_REQ = 6087; // 12 -const static uint64_t SH_FLD_FIR14_LSU_TAG_REUSE = 6088; // 12 -const static uint64_t SH_FLD_FIR14_NCCTL_RLD_BARRIER = 6089; // 12 -const static uint64_t SH_FLD_FIR14_NCCTL_SNP = 6090; // 12 -const static uint64_t SH_FLD_FIR14_NCCTL_SYNC = 6091; // 12 -const static uint64_t SH_FLD_FIR14_NCCTL_TLBIE_ACK = 6092; // 12 -const static uint64_t SH_FLD_FIR14_NCCTL_VSYNC = 6093; // 12 -const static uint64_t SH_FLD_FIR14_NCU_TID_DONE = 6094; // 12 -const static uint64_t SH_FLD_FIR14_PBARB_FSM_REQ_OVERFLOW = 6095; // 12 -const static uint64_t SH_FLD_FIR14_PBARB_TRASHMODE_PB_REQ = 6096; // 12 -const static uint64_t SH_FLD_FIR14_PD_DIR_MULT_HIT = 6097; // 12 -const static uint64_t SH_FLD_FIR14_PHANTOM_B01_REQ = 6098; // 12 -const static uint64_t SH_FLD_FIR14_RCMD0_ADDR_PERR = 6099; // 12 -const static uint64_t SH_FLD_FIR14_RCMD0_TTAG_PERR = 6100; // 12 -const static uint64_t SH_FLD_FIR14_RCMD1_ADDR_PERR = 6101; // 12 -const static uint64_t SH_FLD_FIR14_RCMD1_TTAG_PERR = 6102; // 12 -const static uint64_t SH_FLD_FIR14_RCMD2_ADDR_PERR = 6103; // 12 -const static uint64_t SH_FLD_FIR14_RCMD2_TTAG_PERR = 6104; // 12 -const static uint64_t SH_FLD_FIR14_RCMD3_ADDR_PERR = 6105; // 12 -const static uint64_t SH_FLD_FIR14_RCMD3_TTAG_PERR = 6106; // 12 -const static uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_CRESP = 6107; // 12 -const static uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_DWDONE = 6108; // 12 -const static uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_PBL3_DATA = 6109; // 12 -const static uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_PB_CRESP = 6110; // 12 -const static uint64_t SH_FLD_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK = 6111; // 12 -const static uint64_t SH_FLD_FIR14_RC_PBBUS_SFSTAT = 6112; // 12 -const static uint64_t SH_FLD_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK = 6113; // 12 -const static uint64_t SH_FLD_FIR14_RC_UNEXP_F2_DATA = 6114; // 12 -const static uint64_t SH_FLD_FIR14_RC_UNEXP_PURG_HIT = 6115; // 12 -const static uint64_t SH_FLD_FIR14_RVCTL = 6116; // 12 -const static uint64_t SH_FLD_FIR14_SRCTL0_BAD_HPC = 6117; // 12 -const static uint64_t SH_FLD_FIR14_SRCTL1_BAD_HPC = 6118; // 12 -const static uint64_t SH_FLD_FIR14_SRCTL2_BAD_HPC = 6119; // 12 -const static uint64_t SH_FLD_FIR14_SRCTL3_BAD_HPC = 6120; // 12 -const static uint64_t SH_FLD_FIR14_STQ_COMING = 6121; // 12 -const static uint64_t SH_FLD_FIR14_STQ_OVERFLOW = 6122; // 12 -const static uint64_t SH_FLD_FIR14_TMA_LARXA_VS_FRCMISS_SV = 6123; // 12 -const static uint64_t SH_FLD_FIR14_TMCTL_TIDX_TEND_LDST_SEQ = 6124; // 12 -const static uint64_t SH_FLD_FIR14_XLT_QUEUE_OVRFLW = 6125; // 12 -const static uint64_t SH_FLD_FIR14_XPF_MULT_REQ = 6126; // 12 -const static uint64_t SH_FLD_FIR19_LD_TGT_NODAL_DINC = 6127; // 12 -const static uint64_t SH_FLD_FIR19_ST_TGT_NODAL_DINC = 6128; // 12 -const static uint64_t SH_FLD_FIR1_MASTER_SEQ_ID_PAR = 6129; // 12 -const static uint64_t SH_FLD_FIR1_SNOOP_TLBIE_SEQ_PARITY = 6130; // 12 -const static uint64_t SH_FLD_FIR1_TLBIE_BAD_OP = 6131; // 12 -const static uint64_t SH_FLD_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC = 6132; // 12 -const static uint64_t SH_FLD_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC = 6133; // 12 -const static uint64_t SH_FLD_FIR9_PEC_PHASE3_TIMEOUT = 6134; // 12 -const static uint64_t SH_FLD_FIR9_PEC_PHASE4_RCCO_DISP_FAIL = 6135; // 12 -const static uint64_t SH_FLD_FIR9_PEC_PHASE4_SAME = 6136; // 12 -const static uint64_t SH_FLD_FIR9_PEC_PHASE5_TIMEOUT = 6137; // 12 -const static uint64_t SH_FLD_FIRST_ERROR = 6138; // 3 -const static uint64_t SH_FLD_FIRST_ERROR_CAPTURED = 6139; // 1 -const static uint64_t SH_FLD_FIRST_ERROR_DECODE = 6140; // 1 -const static uint64_t SH_FLD_FIRST_ERROR_DECODE_LEN = 6141; // 1 -const static uint64_t SH_FLD_FIRST_ERROR_INFO = 6142; // 1 -const static uint64_t SH_FLD_FIRST_ERROR_INFO_LEN = 6143; // 1 -const static uint64_t SH_FLD_FIRST_ERROR_LEN = 6144; // 3 -const static uint64_t SH_FLD_FIRST_ERROR_SPARE = 6145; // 1 -const static uint64_t SH_FLD_FIRST_ERROR_SPARE_LEN = 6146; // 1 -const static uint64_t SH_FLD_FIR_ACTION0 = 6147; // 13 -const static uint64_t SH_FLD_FIR_ACTION0_LEN = 6148; // 13 -const static uint64_t SH_FLD_FIR_ACTION1 = 6149; // 13 -const static uint64_t SH_FLD_FIR_ACTION1_LEN = 6150; // 13 -const static uint64_t SH_FLD_FIR_LEN = 6151; // 49 -const static uint64_t SH_FLD_FIR_MASK = 6152; // 16 -const static uint64_t SH_FLD_FIR_MASK_LEN = 6153; // 16 -const static uint64_t SH_FLD_FIR_PARITY_ERR = 6154; // 13 -const static uint64_t SH_FLD_FIR_PARITY_ERR2 = 6155; // 1 -const static uint64_t SH_FLD_FIR_PARITY_ERR2_MASK = 6156; // 1 -const static uint64_t SH_FLD_FIR_PARITY_ERR_DUP = 6157; // 12 -const static uint64_t SH_FLD_FIR_PARITY_ERR_MASK = 6158; // 1 -const static uint64_t SH_FLD_FIR_RESET = 6159; // 6 -const static uint64_t SH_FLD_FIR_TRIGGER = 6160; // 17 -const static uint64_t SH_FLD_FIT_SEL = 6161; // 17 -const static uint64_t SH_FLD_FIT_SEL_LEN = 6162; // 17 -const static uint64_t SH_FLD_FLAG = 6163; // 2 -const static uint64_t SH_FLD_FLUSH_ALIGN_OVR = 6164; // 43 -const static uint64_t SH_FLD_FLUSH_CP_IG_STATE_MAP = 6165; // 2 -const static uint64_t SH_FLD_FLUSH_CP_IG_STATE_MAP_LEN = 6166; // 2 -const static uint64_t SH_FLD_FLUSH_IC = 6167; // 24 -const static uint64_t SH_FLD_FLUSH_SCAN_N = 6168; // 43 -const static uint64_t SH_FLD_FLUSH_SUE_STATE_MAP = 6169; // 2 -const static uint64_t SH_FLD_FLUSH_SUE_STATE_MAP_LEN = 6170; // 2 -const static uint64_t SH_FLD_FMAX = 6171; // 6 -const static uint64_t SH_FLD_FMAX_LEN = 6172; // 6 -const static uint64_t SH_FLD_FMIN = 6173; // 6 -const static uint64_t SH_FLD_FMIN_LEN = 6174; // 6 -const static uint64_t SH_FLD_FMR00_TRAINED = 6175; // 4 -const static uint64_t SH_FLD_FMR01_TRAINED = 6176; // 4 -const static uint64_t SH_FLD_FMR02_TRAINED = 6177; // 4 -const static uint64_t SH_FLD_FMR03_TRAINED = 6178; // 4 -const static uint64_t SH_FLD_FMR04_TRAINED = 6179; // 4 -const static uint64_t SH_FLD_FMR05_TRAINED = 6180; // 4 -const static uint64_t SH_FLD_FMR06_TRAINED = 6181; // 2 -const static uint64_t SH_FLD_FMR07_TRAINED = 6182; // 2 -const static uint64_t SH_FLD_FORCE_BYPASS = 6183; // 1 -const static uint64_t SH_FLD_FORCE_CL_INJECT = 6184; // 1 -const static uint64_t SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR = 6185; // 4 -const static uint64_t SH_FLD_FORCE_ECC_CE = 6186; // 2 -const static uint64_t SH_FLD_FORCE_ECC_SEL = 6187; // 1 -const static uint64_t SH_FLD_FORCE_ECC_SEL_0_1 = 6188; // 1 -const static uint64_t SH_FLD_FORCE_ECC_SEL_0_1_LEN = 6189; // 1 -const static uint64_t SH_FLD_FORCE_ECC_UE = 6190; // 2 -const static uint64_t SH_FLD_FORCE_MAX_SCOPE_INTRP = 6191; // 1 -const static uint64_t SH_FLD_FORCE_MPR = 6192; // 8 -const static uint64_t SH_FLD_FORCE_NON_INBAND_CL_FULL = 6193; // 4 -const static uint64_t SH_FLD_FORCE_ON_CLK_GATE = 6194; // 8 -const static uint64_t SH_FLD_FORCE_PR_INJECT = 6195; // 1 -const static uint64_t SH_FLD_FORCE_RESERVED = 6196; // 8 -const static uint64_t SH_FLD_FORCE_RESET = 6197; // 1 -const static uint64_t SH_FLD_FORCE_SFSTAT_ACTIVE = 6198; // 4 -const static uint64_t SH_FLD_FORCE_SINGLE_BIT_ECC_ERR = 6199; // 4 -const static uint64_t SH_FLD_FORCE_THRES_ACT = 6200; // 43 -const static uint64_t SH_FLD_FORCE_VG_SYS_INTRP = 6201; // 1 -const static uint64_t SH_FLD_FOREIGN_LINK_HANG_ERROR = 6202; // 4 -const static uint64_t SH_FLD_FP0_CREDIT_PRIORITY_4_NOT_8 = 6203; // 2 -const static uint64_t SH_FLD_FP0_DISABLE_CMD_COMPRESSION = 6204; // 2 -const static uint64_t SH_FLD_FP0_DISABLE_GATHERING = 6205; // 2 -const static uint64_t SH_FLD_FP0_DISABLE_PRSP_COMPRESSION = 6206; // 2 -const static uint64_t SH_FLD_FP0_FMR_DISABLE = 6207; // 2 -const static uint64_t SH_FLD_FP0_FMR_SPARE = 6208; // 2 -const static uint64_t SH_FLD_FP0_FMR_SPARE_LEN = 6209; // 2 -const static uint64_t SH_FLD_FP0_LL_CREDIT_HI_LIMIT = 6210; // 2 -const static uint64_t SH_FLD_FP0_LL_CREDIT_HI_LIMIT_LEN = 6211; // 2 -const static uint64_t SH_FLD_FP0_LL_CREDIT_LO_LIMIT = 6212; // 2 -const static uint64_t SH_FLD_FP0_LL_CREDIT_LO_LIMIT_LEN = 6213; // 2 -const static uint64_t SH_FLD_FP0_PRS_DISABLE = 6214; // 2 -const static uint64_t SH_FLD_FP0_PRS_SPARE = 6215; // 2 -const static uint64_t SH_FLD_FP0_PRS_SPARE_LEN = 6216; // 2 -const static uint64_t SH_FLD_FP0_RUN_AFTER_FRAME_ERROR = 6217; // 2 -const static uint64_t SH_FLD_FP1_CREDIT_PRIORITY_4_NOT_8 = 6218; // 2 -const static uint64_t SH_FLD_FP1_DISABLE_CMD_COMPRESSION = 6219; // 2 -const static uint64_t SH_FLD_FP1_DISABLE_GATHERING = 6220; // 2 -const static uint64_t SH_FLD_FP1_DISABLE_PRSP_COMPRESSION = 6221; // 2 -const static uint64_t SH_FLD_FP1_FMR_DISABLE = 6222; // 2 -const static uint64_t SH_FLD_FP1_FMR_SPARE = 6223; // 2 -const static uint64_t SH_FLD_FP1_FMR_SPARE_LEN = 6224; // 2 -const static uint64_t SH_FLD_FP1_LL_CREDIT_HI_LIMIT = 6225; // 2 -const static uint64_t SH_FLD_FP1_LL_CREDIT_HI_LIMIT_LEN = 6226; // 2 -const static uint64_t SH_FLD_FP1_LL_CREDIT_LO_LIMIT = 6227; // 2 -const static uint64_t SH_FLD_FP1_LL_CREDIT_LO_LIMIT_LEN = 6228; // 2 -const static uint64_t SH_FLD_FP1_PRS_DISABLE = 6229; // 2 -const static uint64_t SH_FLD_FP1_PRS_SPARE = 6230; // 2 -const static uint64_t SH_FLD_FP1_PRS_SPARE_LEN = 6231; // 2 -const static uint64_t SH_FLD_FP1_RUN_AFTER_FRAME_ERROR = 6232; // 2 -const static uint64_t SH_FLD_FP2_CREDIT_PRIORITY_4_NOT_8 = 6233; // 2 -const static uint64_t SH_FLD_FP2_DISABLE_CMD_COMPRESSION = 6234; // 2 -const static uint64_t SH_FLD_FP2_DISABLE_GATHERING = 6235; // 2 -const static uint64_t SH_FLD_FP2_DISABLE_PRSP_COMPRESSION = 6236; // 2 -const static uint64_t SH_FLD_FP2_FMR_DISABLE = 6237; // 2 -const static uint64_t SH_FLD_FP2_FMR_SPARE = 6238; // 2 -const static uint64_t SH_FLD_FP2_FMR_SPARE_LEN = 6239; // 2 -const static uint64_t SH_FLD_FP2_LL_CREDIT_HI_LIMIT = 6240; // 2 -const static uint64_t SH_FLD_FP2_LL_CREDIT_HI_LIMIT_LEN = 6241; // 2 -const static uint64_t SH_FLD_FP2_LL_CREDIT_LO_LIMIT = 6242; // 2 -const static uint64_t SH_FLD_FP2_LL_CREDIT_LO_LIMIT_LEN = 6243; // 2 -const static uint64_t SH_FLD_FP2_PRS_DISABLE = 6244; // 2 -const static uint64_t SH_FLD_FP2_PRS_SPARE = 6245; // 2 -const static uint64_t SH_FLD_FP2_PRS_SPARE_LEN = 6246; // 2 -const static uint64_t SH_FLD_FP2_RUN_AFTER_FRAME_ERROR = 6247; // 2 -const static uint64_t SH_FLD_FP3_CREDIT_PRIORITY_4_NOT_8 = 6248; // 2 -const static uint64_t SH_FLD_FP3_DISABLE_CMD_COMPRESSION = 6249; // 2 -const static uint64_t SH_FLD_FP3_DISABLE_GATHERING = 6250; // 2 -const static uint64_t SH_FLD_FP3_DISABLE_PRSP_COMPRESSION = 6251; // 2 -const static uint64_t SH_FLD_FP3_FMR_DISABLE = 6252; // 2 -const static uint64_t SH_FLD_FP3_FMR_SPARE = 6253; // 2 -const static uint64_t SH_FLD_FP3_FMR_SPARE_LEN = 6254; // 2 -const static uint64_t SH_FLD_FP3_LL_CREDIT_HI_LIMIT = 6255; // 2 -const static uint64_t SH_FLD_FP3_LL_CREDIT_HI_LIMIT_LEN = 6256; // 2 -const static uint64_t SH_FLD_FP3_LL_CREDIT_LO_LIMIT = 6257; // 2 -const static uint64_t SH_FLD_FP3_LL_CREDIT_LO_LIMIT_LEN = 6258; // 2 -const static uint64_t SH_FLD_FP3_PRS_DISABLE = 6259; // 2 -const static uint64_t SH_FLD_FP3_PRS_SPARE = 6260; // 2 -const static uint64_t SH_FLD_FP3_PRS_SPARE_LEN = 6261; // 2 -const static uint64_t SH_FLD_FP3_RUN_AFTER_FRAME_ERROR = 6262; // 2 -const static uint64_t SH_FLD_FP4_CREDIT_PRIORITY_4_NOT_8 = 6263; // 2 -const static uint64_t SH_FLD_FP4_DISABLE_CMD_COMPRESSION = 6264; // 2 -const static uint64_t SH_FLD_FP4_DISABLE_GATHERING = 6265; // 2 -const static uint64_t SH_FLD_FP4_DISABLE_PRSP_COMPRESSION = 6266; // 2 -const static uint64_t SH_FLD_FP4_FMR_DISABLE = 6267; // 2 -const static uint64_t SH_FLD_FP4_FMR_SPARE = 6268; // 2 -const static uint64_t SH_FLD_FP4_FMR_SPARE_LEN = 6269; // 2 -const static uint64_t SH_FLD_FP4_LL_CREDIT_HI_LIMIT = 6270; // 2 -const static uint64_t SH_FLD_FP4_LL_CREDIT_HI_LIMIT_LEN = 6271; // 2 -const static uint64_t SH_FLD_FP4_LL_CREDIT_LO_LIMIT = 6272; // 2 -const static uint64_t SH_FLD_FP4_LL_CREDIT_LO_LIMIT_LEN = 6273; // 2 -const static uint64_t SH_FLD_FP4_PRS_DISABLE = 6274; // 2 -const static uint64_t SH_FLD_FP4_PRS_SPARE = 6275; // 2 -const static uint64_t SH_FLD_FP4_PRS_SPARE_LEN = 6276; // 2 -const static uint64_t SH_FLD_FP4_RUN_AFTER_FRAME_ERROR = 6277; // 2 -const static uint64_t SH_FLD_FP5_CREDIT_PRIORITY_4_NOT_8 = 6278; // 2 -const static uint64_t SH_FLD_FP5_DISABLE_CMD_COMPRESSION = 6279; // 2 -const static uint64_t SH_FLD_FP5_DISABLE_GATHERING = 6280; // 2 -const static uint64_t SH_FLD_FP5_DISABLE_PRSP_COMPRESSION = 6281; // 2 -const static uint64_t SH_FLD_FP5_FMR_DISABLE = 6282; // 2 -const static uint64_t SH_FLD_FP5_FMR_SPARE = 6283; // 2 -const static uint64_t SH_FLD_FP5_FMR_SPARE_LEN = 6284; // 2 -const static uint64_t SH_FLD_FP5_LL_CREDIT_HI_LIMIT = 6285; // 2 -const static uint64_t SH_FLD_FP5_LL_CREDIT_HI_LIMIT_LEN = 6286; // 2 -const static uint64_t SH_FLD_FP5_LL_CREDIT_LO_LIMIT = 6287; // 2 -const static uint64_t SH_FLD_FP5_LL_CREDIT_LO_LIMIT_LEN = 6288; // 2 -const static uint64_t SH_FLD_FP5_PRS_DISABLE = 6289; // 2 -const static uint64_t SH_FLD_FP5_PRS_SPARE = 6290; // 2 -const static uint64_t SH_FLD_FP5_PRS_SPARE_LEN = 6291; // 2 -const static uint64_t SH_FLD_FP5_RUN_AFTER_FRAME_ERROR = 6292; // 2 -const static uint64_t SH_FLD_FP6_CREDIT_PRIORITY_4_NOT_8 = 6293; // 1 -const static uint64_t SH_FLD_FP6_DISABLE_CMD_COMPRESSION = 6294; // 1 -const static uint64_t SH_FLD_FP6_DISABLE_GATHERING = 6295; // 1 -const static uint64_t SH_FLD_FP6_DISABLE_PRSP_COMPRESSION = 6296; // 1 -const static uint64_t SH_FLD_FP6_FMR_DISABLE = 6297; // 1 -const static uint64_t SH_FLD_FP6_FMR_SPARE = 6298; // 1 -const static uint64_t SH_FLD_FP6_FMR_SPARE_LEN = 6299; // 1 -const static uint64_t SH_FLD_FP6_LL_CREDIT_HI_LIMIT = 6300; // 1 -const static uint64_t SH_FLD_FP6_LL_CREDIT_HI_LIMIT_LEN = 6301; // 1 -const static uint64_t SH_FLD_FP6_LL_CREDIT_LO_LIMIT = 6302; // 1 -const static uint64_t SH_FLD_FP6_LL_CREDIT_LO_LIMIT_LEN = 6303; // 1 -const static uint64_t SH_FLD_FP6_PRS_DISABLE = 6304; // 1 -const static uint64_t SH_FLD_FP6_PRS_SPARE = 6305; // 1 -const static uint64_t SH_FLD_FP6_PRS_SPARE_LEN = 6306; // 1 -const static uint64_t SH_FLD_FP6_RUN_AFTER_FRAME_ERROR = 6307; // 1 -const static uint64_t SH_FLD_FP7_CREDIT_PRIORITY_4_NOT_8 = 6308; // 1 -const static uint64_t SH_FLD_FP7_DISABLE_CMD_COMPRESSION = 6309; // 1 -const static uint64_t SH_FLD_FP7_DISABLE_GATHERING = 6310; // 1 -const static uint64_t SH_FLD_FP7_DISABLE_PRSP_COMPRESSION = 6311; // 1 -const static uint64_t SH_FLD_FP7_FMR_DISABLE = 6312; // 1 -const static uint64_t SH_FLD_FP7_FMR_SPARE = 6313; // 1 -const static uint64_t SH_FLD_FP7_FMR_SPARE_LEN = 6314; // 1 -const static uint64_t SH_FLD_FP7_LL_CREDIT_HI_LIMIT = 6315; // 1 -const static uint64_t SH_FLD_FP7_LL_CREDIT_HI_LIMIT_LEN = 6316; // 1 -const static uint64_t SH_FLD_FP7_LL_CREDIT_LO_LIMIT = 6317; // 1 -const static uint64_t SH_FLD_FP7_LL_CREDIT_LO_LIMIT_LEN = 6318; // 1 -const static uint64_t SH_FLD_FP7_PRS_DISABLE = 6319; // 1 -const static uint64_t SH_FLD_FP7_PRS_SPARE = 6320; // 1 -const static uint64_t SH_FLD_FP7_PRS_SPARE_LEN = 6321; // 1 -const static uint64_t SH_FLD_FP7_RUN_AFTER_FRAME_ERROR = 6322; // 1 -const static uint64_t SH_FLD_FRAC1 = 6323; // 3 -const static uint64_t SH_FLD_FRAC1_LEN = 6324; // 3 -const static uint64_t SH_FLD_FRAC2 = 6325; // 3 -const static uint64_t SH_FLD_FRAC2_LEN = 6326; // 3 -const static uint64_t SH_FLD_FRAMER00_ATTN = 6327; // 4 -const static uint64_t SH_FLD_FRAMER01_ATTN = 6328; // 4 -const static uint64_t SH_FLD_FRAMER02_ATTN = 6329; // 4 -const static uint64_t SH_FLD_FRAMER03_ATTN = 6330; // 4 -const static uint64_t SH_FLD_FRAMER04_ATTN = 6331; // 4 -const static uint64_t SH_FLD_FRAMER05_ATTN = 6332; // 4 -const static uint64_t SH_FLD_FRAMER06_ATTN = 6333; // 2 -const static uint64_t SH_FLD_FRAMER07_ATTN = 6334; // 2 -const static uint64_t SH_FLD_FRAME_COUNT = 6335; // 8 -const static uint64_t SH_FLD_FRAME_COUNT_LEN = 6336; // 8 -const static uint64_t SH_FLD_FRAME_SIZE = 6337; // 1 -const static uint64_t SH_FLD_FRAME_SIZE_LEN = 6338; // 1 -const static uint64_t SH_FLD_FREEZE = 6339; // 3 -const static uint64_t SH_FLD_FREEZEMODE = 6340; // 3 -const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR1 = 6341; // 1 -const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR2 = 6342; // 1 -const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR3 = 6343; // 1 -const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR4 = 6344; // 1 -const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR5 = 6345; // 1 -const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR6 = 6346; // 1 -const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR7 = 6347; // 1 -const static uint64_t SH_FLD_FREEZE_ON_OVERFLOW = 6348; // 2 -const static uint64_t SH_FLD_FREE_USAGE_10E = 6349; // 19 -const static uint64_t SH_FLD_FREE_USAGE_11E = 6350; // 19 -const static uint64_t SH_FLD_FREE_USAGE_12D = 6351; // 31 -const static uint64_t SH_FLD_FREE_USAGE_12E = 6352; // 41 -const static uint64_t SH_FLD_FREE_USAGE_13D = 6353; // 32 -const static uint64_t SH_FLD_FREE_USAGE_13E = 6354; // 41 -const static uint64_t SH_FLD_FREE_USAGE_14D = 6355; // 34 -const static uint64_t SH_FLD_FREE_USAGE_14E = 6356; // 41 -const static uint64_t SH_FLD_FREE_USAGE_15D = 6357; // 34 -const static uint64_t SH_FLD_FREE_USAGE_15E = 6358; // 41 -const static uint64_t SH_FLD_FREE_USAGE_16D = 6359; // 38 -const static uint64_t SH_FLD_FREE_USAGE_16E = 6360; // 41 -const static uint64_t SH_FLD_FREE_USAGE_17D = 6361; // 38 -const static uint64_t SH_FLD_FREE_USAGE_17E = 6362; // 41 -const static uint64_t SH_FLD_FREE_USAGE_18D = 6363; // 40 -const static uint64_t SH_FLD_FREE_USAGE_18E = 6364; // 41 -const static uint64_t SH_FLD_FREE_USAGE_19D = 6365; // 41 -const static uint64_t SH_FLD_FREE_USAGE_19E = 6366; // 41 -const static uint64_t SH_FLD_FREE_USAGE_20D = 6367; // 41 -const static uint64_t SH_FLD_FREE_USAGE_20E = 6368; // 43 -const static uint64_t SH_FLD_FREE_USAGE_21D = 6369; // 41 -const static uint64_t SH_FLD_FREE_USAGE_21E = 6370; // 43 -const static uint64_t SH_FLD_FREE_USAGE_22D = 6371; // 41 -const static uint64_t SH_FLD_FREE_USAGE_22E = 6372; // 43 -const static uint64_t SH_FLD_FREE_USAGE_23D = 6373; // 41 -const static uint64_t SH_FLD_FREE_USAGE_23E = 6374; // 43 -const static uint64_t SH_FLD_FREE_USAGE_24D = 6375; // 41 -const static uint64_t SH_FLD_FREE_USAGE_25D = 6376; // 41 -const static uint64_t SH_FLD_FREE_USAGE_26D = 6377; // 42 -const static uint64_t SH_FLD_FREE_USAGE_27D = 6378; // 42 -const static uint64_t SH_FLD_FREE_USAGE_28D = 6379; // 40 -const static uint64_t SH_FLD_FREE_USAGE_29D = 6380; // 40 -const static uint64_t SH_FLD_FREE_USAGE_30D = 6381; // 40 -const static uint64_t SH_FLD_FREE_USAGE_31D = 6382; // 40 -const static uint64_t SH_FLD_FREE_USAGE_44C = 6383; // 43 -const static uint64_t SH_FLD_FREE_USAGE_45C = 6384; // 43 -const static uint64_t SH_FLD_FREE_USAGE_46C = 6385; // 43 -const static uint64_t SH_FLD_FREE_USAGE_47C = 6386; // 43 -const static uint64_t SH_FLD_FREE_USAGE_48A = 6387; // 43 -const static uint64_t SH_FLD_FREE_USAGE_49A = 6388; // 43 -const static uint64_t SH_FLD_FREE_USAGE_50A = 6389; // 43 -const static uint64_t SH_FLD_FREE_USAGE_51A = 6390; // 43 -const static uint64_t SH_FLD_FREE_USAGE_52A = 6391; // 43 -const static uint64_t SH_FLD_FREE_USAGE_53A = 6392; // 43 -const static uint64_t SH_FLD_FREE_USAGE_54A = 6393; // 43 -const static uint64_t SH_FLD_FREE_USAGE_55A = 6394; // 43 -const static uint64_t SH_FLD_FREE_USAGE_56A = 6395; // 43 -const static uint64_t SH_FLD_FREE_USAGE_57A = 6396; // 43 -const static uint64_t SH_FLD_FREE_USAGE_58A = 6397; // 43 -const static uint64_t SH_FLD_FREE_USAGE_59A = 6398; // 43 -const static uint64_t SH_FLD_FREE_USAGE_60A = 6399; // 43 -const static uint64_t SH_FLD_FREE_USAGE_61A = 6400; // 43 -const static uint64_t SH_FLD_FREE_USAGE_62A = 6401; // 43 -const static uint64_t SH_FLD_FREE_USAGE_63A = 6402; // 43 -const static uint64_t SH_FLD_FREE_USAGE_6A = 6403; // 43 -const static uint64_t SH_FLD_FREE_USAGE_7A = 6404; // 43 -const static uint64_t SH_FLD_FREE_USAGE_9A = 6405; // 43 -const static uint64_t SH_FLD_FREQIN_AVG = 6406; // 6 -const static uint64_t SH_FLD_FREQIN_AVG_LEN = 6407; // 6 -const static uint64_t SH_FLD_FREQIN_MAX = 6408; // 6 -const static uint64_t SH_FLD_FREQIN_MAX_LEN = 6409; // 6 -const static uint64_t SH_FLD_FREQIN_MIN = 6410; // 6 -const static uint64_t SH_FLD_FREQIN_MIN_LEN = 6411; // 6 -const static uint64_t SH_FLD_FREQOUT = 6412; // 6 -const static uint64_t SH_FLD_FREQOUT_AVG = 6413; // 6 -const static uint64_t SH_FLD_FREQOUT_AVG_LEN = 6414; // 6 -const static uint64_t SH_FLD_FREQOUT_LEN = 6415; // 6 -const static uint64_t SH_FLD_FREQOUT_MAX = 6416; // 6 -const static uint64_t SH_FLD_FREQOUT_MAX_LEN = 6417; // 6 -const static uint64_t SH_FLD_FREQOUT_MIN = 6418; // 6 -const static uint64_t SH_FLD_FREQOUT_MIN_LEN = 6419; // 6 -const static uint64_t SH_FLD_FREQUENCY_REFERENCE = 6420; // 24 -const static uint64_t SH_FLD_FREQUENCY_REFERENCE_LEN = 6421; // 24 -const static uint64_t SH_FLD_FREQ_CHANGE = 6422; // 6 -const static uint64_t SH_FLD_FREQ_LCL_SAMPLE_EN = 6423; // 12 -const static uint64_t SH_FLD_FREQ_MULT = 6424; // 6 -const static uint64_t SH_FLD_FREQ_MULT_LEN = 6425; // 6 -const static uint64_t SH_FLD_FREQ_SCALE_A_THRESHOLD = 6426; // 24 -const static uint64_t SH_FLD_FREQ_SCALE_A_THRESHOLD_LEN = 6427; // 24 -const static uint64_t SH_FLD_FREQ_SCALE_B_THRESHOLD = 6428; // 24 -const static uint64_t SH_FLD_FREQ_SCALE_B_THRESHOLD_LEN = 6429; // 24 -const static uint64_t SH_FLD_FSAFE = 6430; // 6 -const static uint64_t SH_FLD_FSAFE_ACTIVE = 6431; // 6 -const static uint64_t SH_FLD_FSAFE_LEN = 6432; // 6 -const static uint64_t SH_FLD_FSI_A_MST_0_ACTUAL_ERROR = 6433; // 1 -const static uint64_t SH_FLD_FSI_A_MST_0_ACTUAL_ERROR_LEN = 6434; // 1 -const static uint64_t SH_FLD_FSI_A_MST_0_PORT_0_ENABLE = 6435; // 1 -const static uint64_t SH_FLD_FSI_A_MST_0_PORT_1_ENABLE = 6436; // 1 -const static uint64_t SH_FLD_FSI_A_MST_0_PORT_2_ENABLE = 6437; // 1 -const static uint64_t SH_FLD_FSI_A_MST_0_PORT_3_ENABLE = 6438; // 1 -const static uint64_t SH_FLD_FSI_A_MST_0_PORT_4_ENABLE = 6439; // 1 -const static uint64_t SH_FLD_FSI_A_MST_0_PORT_5_ENABLE = 6440; // 1 -const static uint64_t SH_FLD_FSI_A_MST_0_PORT_6_ENABLE = 6441; // 1 -const static uint64_t SH_FLD_FSI_A_MST_0_PORT_7_ENABLE = 6442; // 1 -const static uint64_t SH_FLD_FSI_A_MST_1_ACTUAL_ERROR = 6443; // 1 -const static uint64_t SH_FLD_FSI_A_MST_1_ACTUAL_ERROR_LEN = 6444; // 1 -const static uint64_t SH_FLD_FSI_A_MST_1_PORT_0_ENABLE = 6445; // 1 -const static uint64_t SH_FLD_FSI_A_MST_1_PORT_1_ENABLE = 6446; // 1 -const static uint64_t SH_FLD_FSI_A_MST_1_PORT_2_ENABLE = 6447; // 1 -const static uint64_t SH_FLD_FSI_A_MST_1_PORT_3_ENABLE = 6448; // 1 -const static uint64_t SH_FLD_FSI_A_MST_1_PORT_4_ENABLE = 6449; // 1 -const static uint64_t SH_FLD_FSI_B_MST_0_ACTUAL_ERROR = 6450; // 1 -const static uint64_t SH_FLD_FSI_B_MST_0_ACTUAL_ERROR_LEN = 6451; // 1 -const static uint64_t SH_FLD_FSI_B_MST_0_PORT_0_ENABLE = 6452; // 1 -const static uint64_t SH_FLD_FSI_B_MST_0_PORT_1_ENABLE = 6453; // 1 -const static uint64_t SH_FLD_FSI_B_MST_0_PORT_2_ENABLE = 6454; // 1 -const static uint64_t SH_FLD_FSI_B_MST_0_PORT_3_ENABLE = 6455; // 1 -const static uint64_t SH_FLD_FSI_B_MST_0_PORT_4_ENABLE = 6456; // 1 -const static uint64_t SH_FLD_FSI_B_MST_0_PORT_5_ENABLE = 6457; // 1 -const static uint64_t SH_FLD_FSI_B_MST_0_PORT_6_ENABLE = 6458; // 1 -const static uint64_t SH_FLD_FSI_B_MST_0_PORT_7_ENABLE = 6459; // 1 -const static uint64_t SH_FLD_FSI_CC_VSB_CBS_CMD = 6460; // 1 -const static uint64_t SH_FLD_FSI_CC_VSB_CBS_CMD_LEN = 6461; // 1 -const static uint64_t SH_FLD_FSI_CC_VSB_CBS_REQ = 6462; // 1 -const static uint64_t SH_FLD_FSI_SCRATCH_PAD1 = 6463; // 1 -const static uint64_t SH_FLD_FSI_SCRATCH_PAD1_LEN = 6464; // 1 -const static uint64_t SH_FLD_FSI_SCRATCH_PAD2 = 6465; // 1 -const static uint64_t SH_FLD_FSI_SCRATCH_PAD2_LEN = 6466; // 1 -const static uint64_t SH_FLD_FSI_SCRATCH_PAD3 = 6467; // 1 -const static uint64_t SH_FLD_FSI_SCRATCH_PAD3_LEN = 6468; // 1 -const static uint64_t SH_FLD_FSMJ_EVENT = 6469; // 2 -const static uint64_t SH_FLD_FSMJ_EVENT_LEN = 6470; // 2 -const static uint64_t SH_FLD_FSMJ_EVENT_SEL = 6471; // 2 -const static uint64_t SH_FLD_FSMJ_EVENT_SEL_LEN = 6472; // 2 -const static uint64_t SH_FLD_FSMJ_FSM = 6473; // 2 -const static uint64_t SH_FLD_FSMJ_FSM_LEN = 6474; // 2 -const static uint64_t SH_FLD_FSMJ_FSM_SEL = 6475; // 2 -const static uint64_t SH_FLD_FSMJ_FSM_SEL_LEN = 6476; // 2 -const static uint64_t SH_FLD_FSM_DATA02 = 6477; // 1 -const static uint64_t SH_FLD_FSM_ERR = 6478; // 5 -const static uint64_t SH_FLD_FSM_ERROR = 6479; // 1 -const static uint64_t SH_FLD_FSM_PARITY_ERROR = 6480; // 3 -const static uint64_t SH_FLD_FSM_PERR = 6481; // 1 -const static uint64_t SH_FLD_FSM_PRESENT_STATE = 6482; // 1 -const static uint64_t SH_FLD_FSM_PRESENT_STATE_LEN = 6483; // 1 -const static uint64_t SH_FLD_FSM_SYNC_ENABLE = 6484; // 1 -const static uint64_t SH_FLD_FSM_TRIGGER = 6485; // 2 -const static uint64_t SH_FLD_FSP_ACCESS_TRUSTED_SPACE = 6486; // 4 -const static uint64_t SH_FLD_FSP_CMD_ENABLE = 6487; // 1 -const static uint64_t SH_FLD_FSP_ECC_ERR_CE = 6488; // 4 -const static uint64_t SH_FLD_FSP_ECC_ERR_UE = 6489; // 4 -const static uint64_t SH_FLD_FSP_ERR_RSP_ENABLE = 6490; // 1 -const static uint64_t SH_FLD_FSP_INBOUND_ACTIVE = 6491; // 1 -const static uint64_t SH_FLD_FSP_INTERRUPT = 6492; // 1 -const static uint64_t SH_FLD_FSP_INT_ENABLE = 6493; // 1 -const static uint64_t SH_FLD_FSP_INV_READ = 6494; // 1 -const static uint64_t SH_FLD_FSP_LINK_ACTIVE = 6495; // 1 -const static uint64_t SH_FLD_FSP_MMIO_ENABLE = 6496; // 1 -const static uint64_t SH_FLD_FSP_MMIO_MASK = 6497; // 1 -const static uint64_t SH_FLD_FSP_MMIO_MASK_LEN = 6498; // 1 -const static uint64_t SH_FLD_FSP_OUTBOUND_ACTIVE = 6499; // 1 -const static uint64_t SH_FLD_FSP_RESET = 6500; // 1 -const static uint64_t SH_FLD_FSP_SPECIAL_WKUP = 6501; // 30 -const static uint64_t SH_FLD_FSP_TCE_ENABLE = 6502; // 1 -const static uint64_t SH_FLD_FULL = 6503; // 1 -const static uint64_t SH_FLD_FULLMASK = 6504; // 1 -const static uint64_t SH_FLD_FULLMASK_LEN = 6505; // 1 -const static uint64_t SH_FLD_FULL_WRITEBACK_ENABLE = 6506; // 6 -const static uint64_t SH_FLD_FUNC = 6507; // 43 -const static uint64_t SH_FLD_FUNCTION = 6508; // 6 -const static uint64_t SH_FLD_FUNCTION_LEN = 6509; // 6 -const static uint64_t SH_FLD_FUNC_MODE_DONE = 6510; // 4 -const static uint64_t SH_FLD_FWD_PROG_RATE2 = 6511; // 12 -const static uint64_t SH_FLD_FWD_PROG_RATE2_LEN = 6512; // 12 -const static uint64_t SH_FLD_FW_RD_WR = 6513; // 8 -const static uint64_t SH_FLD_FW_RD_WR_LEN = 6514; // 8 -const static uint64_t SH_FLD_FW_WR_RD = 6515; // 8 -const static uint64_t SH_FLD_FW_WR_RD_LEN = 6516; // 8 -const static uint64_t SH_FLD_F_READ = 6517; // 43 -const static uint64_t SH_FLD_F_SKITTER_READ_MASK = 6518; // 43 -const static uint64_t SH_FLD_GAP_LENGTH_ADDER = 6519; // 8 -const static uint64_t SH_FLD_GAP_LENGTH_ADDER_LEN = 6520; // 8 -const static uint64_t SH_FLD_GCR_BUFFER_ENABLED_RO_SIGNAL = 6521; // 4 -const static uint64_t SH_FLD_GCR_HANG_DET_SEL = 6522; // 4 -const static uint64_t SH_FLD_GCR_HANG_DET_SEL_LEN = 6523; // 4 -const static uint64_t SH_FLD_GCR_HANG_ERROR_INJ = 6524; // 4 -const static uint64_t SH_FLD_GCR_HANG_ERROR_MASK = 6525; // 4 -const static uint64_t SH_FLD_GCR_TEST = 6526; // 4 -const static uint64_t SH_FLD_GENERATE_MPIPL_SEQUENCE = 6527; // 4 -const static uint64_t SH_FLD_GLOBAL_EP_RESET_DC = 6528; // 1 -const static uint64_t SH_FLD_GLOBAL_PHY_OFFSET = 6529; // 8 -const static uint64_t SH_FLD_GLOBAL_PHY_OFFSET_LEN = 6530; // 8 -const static uint64_t SH_FLD_GLOBAL_RUN_MODE = 6531; // 2 -const static uint64_t SH_FLD_GO = 6532; // 43 -const static uint64_t SH_FLD_GO2 = 6533; // 43 -const static uint64_t SH_FLD_GOOD = 6534; // 8 -const static uint64_t SH_FLD_GOTO_CMD = 6535; // 64 -const static uint64_t SH_FLD_GOTO_CMD_LEN = 6536; // 64 -const static uint64_t SH_FLD_GP = 6537; // 2 -const static uint64_t SH_FLD_GPE0_ERROR = 6538; // 1 -const static uint64_t SH_FLD_GPE1_ERROR = 6539; // 1 -const static uint64_t SH_FLD_GPE2_ERROR = 6540; // 1 -const static uint64_t SH_FLD_GPE3_ERROR = 6541; // 1 -const static uint64_t SH_FLD_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC = 6542; // 1 -const static uint64_t SH_FLD_GRANTED_PACKET = 6543; // 30 -const static uint64_t SH_FLD_GRANTED_PACKET_LEN = 6544; // 30 -const static uint64_t SH_FLD_GRANTED_SOURCE = 6545; // 30 -const static uint64_t SH_FLD_GRANTED_SOURCE_LEN = 6546; // 30 -const static uint64_t SH_FLD_GROUP = 6547; // 9 -const static uint64_t SH_FLD_GROUPING = 6548; // 8 -const static uint64_t SH_FLD_GROUPING_LEN = 6549; // 8 -const static uint64_t SH_FLD_GROUP_BASE_ADDRESS = 6550; // 8 -const static uint64_t SH_FLD_GROUP_BASE_ADDRESS_LEN = 6551; // 8 -const static uint64_t SH_FLD_GROUP_EPSILON = 6552; // 8 -const static uint64_t SH_FLD_GROUP_EPSILON_LEN = 6553; // 8 -const static uint64_t SH_FLD_GROUP_LEN = 6554; // 9 -const static uint64_t SH_FLD_GROUP_SELECT = 6555; // 1 -const static uint64_t SH_FLD_GROUP_SELECT_LEN = 6556; // 1 -const static uint64_t SH_FLD_GROUP_SEL_0_4 = 6557; // 1 -const static uint64_t SH_FLD_GROUP_SEL_0_4_LEN = 6558; // 1 -const static uint64_t SH_FLD_GROUP_SIZE = 6559; // 8 -const static uint64_t SH_FLD_GROUP_SIZE_LEN = 6560; // 8 -const static uint64_t SH_FLD_GRPSEL = 6561; // 2 -const static uint64_t SH_FLD_GRPSEL_LEN = 6562; // 2 -const static uint64_t SH_FLD_GRP_BASE = 6563; // 8 -const static uint64_t SH_FLD_GRP_BASE_LEN = 6564; // 8 -const static uint64_t SH_FLD_GRP_MBR_ID = 6565; // 8 -const static uint64_t SH_FLD_GRP_SIZE = 6566; // 8 -const static uint64_t SH_FLD_GRP_SIZE_LEN = 6567; // 8 -const static uint64_t SH_FLD_GX = 6568; // 2 -const static uint64_t SH_FLD_GXSTP0_XSTOP_IN = 6569; // 43 -const static uint64_t SH_FLD_GXSTP0_XSTOP_IN_LEN = 6570; // 43 -const static uint64_t SH_FLD_GXSTP1_XSTOP_IN = 6571; // 43 -const static uint64_t SH_FLD_GXSTP1_XSTOP_IN_LEN = 6572; // 43 -const static uint64_t SH_FLD_GXSTP2_XSTOP_IN = 6573; // 43 -const static uint64_t SH_FLD_GXSTP2_XSTOP_IN_LEN = 6574; // 43 -const static uint64_t SH_FLD_GXSTP_IN = 6575; // 43 -const static uint64_t SH_FLD_GXSTP_IN_LEN = 6576; // 43 -const static uint64_t SH_FLD_GX_ENABLE_OVERWRITE = 6577; // 1 -const static uint64_t SH_FLD_GX_LEN = 6578; // 2 -const static uint64_t SH_FLD_GZIPCOMP_MAX_INRD = 6579; // 1 -const static uint64_t SH_FLD_GZIPCOMP_MAX_INRD_LEN = 6580; // 1 -const static uint64_t SH_FLD_GZIPDECOMP_MAX_INRD = 6581; // 1 -const static uint64_t SH_FLD_GZIPDECOMP_MAX_INRD_LEN = 6582; // 1 -const static uint64_t SH_FLD_GZIP_COMP_PREFETCH_ENABLE = 6583; // 1 -const static uint64_t SH_FLD_GZIP_DECOMP_PREFETCH_ENABLE = 6584; // 1 -const static uint64_t SH_FLD_GZIP_FC_SELECT = 6585; // 1 -const static uint64_t SH_FLD_GZIP_FC_SELECT_LEN = 6586; // 1 -const static uint64_t SH_FLD_GZIP_LATENCY_CFG = 6587; // 1 -const static uint64_t SH_FLD_GZIP_MUX_SELECT = 6588; // 1 -const static uint64_t SH_FLD_GZIP_MUX_SELECT_LEN = 6589; // 1 -const static uint64_t SH_FLD_H1AP_CFG = 6590; // 6 -const static uint64_t SH_FLD_H1AP_CFG_LEN = 6591; // 6 -const static uint64_t SH_FLD_HALT_INPUT = 6592; // 13 -const static uint64_t SH_FLD_HALT_ON_TRIG = 6593; // 17 -const static uint64_t SH_FLD_HALT_ON_XSTOP = 6594; // 17 -const static uint64_t SH_FLD_HALT_ROTATION = 6595; // 8 -const static uint64_t SH_FLD_HANG_DATA_SCALE = 6596; // 5 -const static uint64_t SH_FLD_HANG_DATA_SCALE_LEN = 6597; // 5 -const static uint64_t SH_FLD_HANG_ON_ACK_DEAD = 6598; // 1 -const static uint64_t SH_FLD_HANG_ON_ADDR_ERROR = 6599; // 1 -const static uint64_t SH_FLD_HANG_PE_SCALE = 6600; // 3 -const static uint64_t SH_FLD_HANG_PE_SCALE_LEN = 6601; // 3 -const static uint64_t SH_FLD_HANG_PIB_RESET = 6602; // 1 -const static uint64_t SH_FLD_HANG_POLL_ENABLE = 6603; // 2 -const static uint64_t SH_FLD_HANG_POLL_PULSE_DIV = 6604; // 24 -const static uint64_t SH_FLD_HANG_POLL_PULSE_DIV_LEN = 6605; // 24 -const static uint64_t SH_FLD_HANG_POLL_SCALE = 6606; // 7 -const static uint64_t SH_FLD_HANG_POLL_SCALE_LEN = 6607; // 7 -const static uint64_t SH_FLD_HANG_RESET = 6608; // 1 -const static uint64_t SH_FLD_HANG_SHM_SCALE = 6609; // 2 -const static uint64_t SH_FLD_HANG_SHM_SCALE_LEN = 6610; // 2 -const static uint64_t SH_FLD_HANG_SM_ON_ARE = 6611; // 2 -const static uint64_t SH_FLD_HANG_SM_ON_LINK_FAIL = 6612; // 2 -const static uint64_t SH_FLD_HARD_CE_COUNT = 6613; // 2 -const static uint64_t SH_FLD_HARD_CE_COUNT_LEN = 6614; // 2 -const static uint64_t SH_FLD_HARD_CHIPID_IN_BLOCK_EN = 6615; // 1 -const static uint64_t SH_FLD_HARD_MCE_COUNT = 6616; // 2 -const static uint64_t SH_FLD_HARD_MCE_COUNT_LEN = 6617; // 2 -const static uint64_t SH_FLD_HARD_NCE_ETE_ATTN = 6618; // 10 -const static uint64_t SH_FLD_HASH_LPID_DIS = 6619; // 1 -const static uint64_t SH_FLD_HASH_PID_DIS = 6620; // 1 -const static uint64_t SH_FLD_HASH_SIZE_MASK = 6621; // 1 -const static uint64_t SH_FLD_HASH_SIZE_MASK_LEN = 6622; // 1 -const static uint64_t SH_FLD_HA_ILLEGAL_CONSUMER_ACCESS = 6623; // 4 -const static uint64_t SH_FLD_HA_ILLEGAL_PRODUCER_ACCESS = 6624; // 4 -const static uint64_t SH_FLD_HDICE = 6625; // 96 -const static uint64_t SH_FLD_HDR_ARR_ECC_CORR_ENA = 6626; // 6 -const static uint64_t SH_FLD_HDR_ARR_ECC_SUE_ENA = 6627; // 6 -const static uint64_t SH_FLD_HI = 6628; // 1 -const static uint64_t SH_FLD_HIGH = 6629; // 1 -const static uint64_t SH_FLD_HIGH_IDLE_COUNT = 6630; // 8 -const static uint64_t SH_FLD_HIGH_IDLE_COUNT_LEN = 6631; // 8 -const static uint64_t SH_FLD_HIGH_IDLE_THRESHOLD = 6632; // 8 -const static uint64_t SH_FLD_HIGH_IDLE_THRESHOLD_LEN = 6633; // 8 -const static uint64_t SH_FLD_HIGH_LEN = 6634; // 1 -const static uint64_t SH_FLD_HILE = 6635; // 24 -const static uint64_t SH_FLD_HIRES_FMAX = 6636; // 6 -const static uint64_t SH_FLD_HIRES_FMAX_LEN = 6637; // 6 -const static uint64_t SH_FLD_HIRES_FMIN = 6638; // 6 -const static uint64_t SH_FLD_HIRES_FMIN_LEN = 6639; // 6 -const static uint64_t SH_FLD_HIRES_FREQIN_AVG = 6640; // 6 -const static uint64_t SH_FLD_HIRES_FREQIN_AVG_LEN = 6641; // 6 -const static uint64_t SH_FLD_HIRES_FREQIN_MAX = 6642; // 6 -const static uint64_t SH_FLD_HIRES_FREQIN_MAX_LEN = 6643; // 6 -const static uint64_t SH_FLD_HIRES_FREQIN_MIN = 6644; // 6 -const static uint64_t SH_FLD_HIRES_FREQIN_MIN_LEN = 6645; // 6 -const static uint64_t SH_FLD_HIRES_FREQOUT = 6646; // 6 -const static uint64_t SH_FLD_HIRES_FREQOUT_AVG = 6647; // 6 -const static uint64_t SH_FLD_HIRES_FREQOUT_AVG_LEN = 6648; // 6 -const static uint64_t SH_FLD_HIRES_FREQOUT_LEN = 6649; // 6 -const static uint64_t SH_FLD_HIRES_FREQOUT_MAX = 6650; // 6 -const static uint64_t SH_FLD_HIRES_FREQOUT_MAX_LEN = 6651; // 6 -const static uint64_t SH_FLD_HIRES_FREQOUT_MIN = 6652; // 6 -const static uint64_t SH_FLD_HIRES_FREQOUT_MIN_LEN = 6653; // 6 -const static uint64_t SH_FLD_HIRES_MULT = 6654; // 6 -const static uint64_t SH_FLD_HIRES_MULT_LEN = 6655; // 6 -const static uint64_t SH_FLD_HIST = 6656; // 6 -const static uint64_t SH_FLD_HIST_ADDRESS = 6657; // 1 -const static uint64_t SH_FLD_HIST_ADDRESS_LEN = 6658; // 1 -const static uint64_t SH_FLD_HIST_DONE = 6659; // 1 -const static uint64_t SH_FLD_HIST_FREEZE_HISTORY = 6660; // 1 -const static uint64_t SH_FLD_HIST_LEN = 6661; // 6 -const static uint64_t SH_FLD_HIST_MANUAL_MODE_EN = 6662; // 1 -const static uint64_t SH_FLD_HIST_MASK = 6663; // 1 -const static uint64_t SH_FLD_HIST_MASK_LEN = 6664; // 1 -const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT = 6665; // 6 -const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LANE = 6666; // 6 -const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LANE_LEN = 6667; // 6 -const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LEN = 6668; // 6 -const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_MODE = 6669; // 6 -const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_MODE_LEN = 6670; // 6 -const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_VALID = 6671; // 6 -const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH = 6672; // 6 -const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LANE = 6673; // 6 -const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LANE_LEN = 6674; // 6 -const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LEN = 6675; // 6 -const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_MODE = 6676; // 6 -const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_MODE_LEN = 6677; // 6 -const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_VALID = 6678; // 6 -const static uint64_t SH_FLD_HIST_RESERVED = 6679; // 1 -const static uint64_t SH_FLD_HIST_RESERVED_LEN = 6680; // 1 -const static uint64_t SH_FLD_HIST_RESET_HISTORY = 6681; // 1 -const static uint64_t SH_FLD_HIST_START_NOT_STOP = 6682; // 1 -const static uint64_t SH_FLD_HIST_STOP_ON_ERROR_GT = 6683; // 1 -const static uint64_t SH_FLD_HIST_STOP_ON_ERROR_GT_LEN = 6684; // 1 -const static uint64_t SH_FLD_HIST_TRACE_TRAFFIC = 6685; // 1 -const static uint64_t SH_FLD_HMI_ACTIVE = 6686; // 1 -const static uint64_t SH_FLD_HMI_EXIT_ENABLE = 6687; // 96 -const static uint64_t SH_FLD_HMI_REQUEST_C0 = 6688; // 12 -const static uint64_t SH_FLD_HMI_REQUEST_C1 = 6689; // 12 -const static uint64_t SH_FLD_HOLD = 6690; // 2 -const static uint64_t SH_FLD_HOLD_0_51 = 6691; // 1 -const static uint64_t SH_FLD_HOLD_0_51_LEN = 6692; // 1 -const static uint64_t SH_FLD_HOLD_DBGTRIG_SEL = 6693; // 43 -const static uint64_t SH_FLD_HOLD_DBGTRIG_SEL_LEN = 6694; // 43 -const static uint64_t SH_FLD_HOLD_LEN = 6695; // 2 -const static uint64_t SH_FLD_HOLD_SAMPLE = 6696; // 43 -const static uint64_t SH_FLD_HOLD_SAMPLE_WITH_TRIGGER = 6697; // 43 -const static uint64_t SH_FLD_HOLE0_LOWER_ADDRESS = 6698; // 8 -const static uint64_t SH_FLD_HOLE0_LOWER_ADDRESS_LEN = 6699; // 8 -const static uint64_t SH_FLD_HOLE0_UPPER_ADDRESS = 6700; // 8 -const static uint64_t SH_FLD_HOLE0_UPPER_ADDRESS_LEN = 6701; // 8 -const static uint64_t SH_FLD_HOLE0_VALID = 6702; // 8 -const static uint64_t SH_FLD_HOLE1_LOWER_ADDRESS = 6703; // 8 -const static uint64_t SH_FLD_HOLE1_LOWER_ADDRESS_LEN = 6704; // 8 -const static uint64_t SH_FLD_HOLE1_UPPER_ADDRESS = 6705; // 8 -const static uint64_t SH_FLD_HOLE1_UPPER_ADDRESS_LEN = 6706; // 8 -const static uint64_t SH_FLD_HOLE1_VALID = 6707; // 8 -const static uint64_t SH_FLD_HRMOR = 6708; // 1 -const static uint64_t SH_FLD_HRMOR_LEN = 6709; // 1 -const static uint64_t SH_FLD_HSSCALERR = 6710; // 6 -const static uint64_t SH_FLD_HSSPLLAERR = 6711; // 6 -const static uint64_t SH_FLD_HSSPLLBERR = 6712; // 6 -const static uint64_t SH_FLD_HSSPLLCAL = 6713; // 3 -const static uint64_t SH_FLD_HSSPLLFASTCAL = 6714; // 6 -const static uint64_t SH_FLD_HSSRECAL = 6715; // 6 -const static uint64_t SH_FLD_HSSRESYNC = 6716; // 6 -const static uint64_t SH_FLD_HTB_EXTEST = 6717; // 43 -const static uint64_t SH_FLD_HTB_INTEST = 6718; // 43 -const static uint64_t SH_FLD_HTMCO_STATUS_ADDR_ERROR = 6719; // 26 -const static uint64_t SH_FLD_HTMCO_STATUS_BUF_WAIT = 6720; // 26 -const static uint64_t SH_FLD_HTMCO_STATUS_COMPLETE = 6721; // 26 -const static uint64_t SH_FLD_HTMCO_STATUS_CRESP_OV = 6722; // 26 -const static uint64_t SH_FLD_HTMCO_STATUS_ENABLE = 6723; // 26 -const static uint64_t SH_FLD_HTMCO_STATUS_FLUSH = 6724; // 26 -const static uint64_t SH_FLD_HTMCO_STATUS_INIT = 6725; // 26 -const static uint64_t SH_FLD_HTMCO_STATUS_PAUSED = 6726; // 26 -const static uint64_t SH_FLD_HTMCO_STATUS_PREREQ = 6727; // 26 -const static uint64_t SH_FLD_HTMCO_STATUS_PURGE_DONE = 6728; // 24 -const static uint64_t SH_FLD_HTMCO_STATUS_PURGE_IN_PROG = 6729; // 24 -const static uint64_t SH_FLD_HTMCO_STATUS_READY = 6730; // 26 -const static uint64_t SH_FLD_HTMCO_STATUS_REPAIR = 6731; // 26 -const static uint64_t SH_FLD_HTMCO_STATUS_SPARE = 6732; // 2 -const static uint64_t SH_FLD_HTMCO_STATUS_SPARE_LEN = 6733; // 2 -const static uint64_t SH_FLD_HTMCO_STATUS_STAMP = 6734; // 26 -const static uint64_t SH_FLD_HTMCO_STATUS_TRACING = 6735; // 26 -const static uint64_t SH_FLD_HTMSC = 6736; // 24 -const static uint64_t SH_FLD_HTMSC_ALLOC = 6737; // 26 -const static uint64_t SH_FLD_HTMSC_BASE = 6738; // 26 -const static uint64_t SH_FLD_HTMSC_BASE_LEN = 6739; // 26 -const static uint64_t SH_FLD_HTMSC_CAPTURE = 6740; // 26 -const static uint64_t SH_FLD_HTMSC_CAPTURE_LEN = 6741; // 26 -const static uint64_t SH_FLD_HTMSC_CHIP0_STOP = 6742; // 24 -const static uint64_t SH_FLD_HTMSC_CHIP1_STOP = 6743; // 24 -const static uint64_t SH_FLD_HTMSC_CONTENT_SEL = 6744; // 26 -const static uint64_t SH_FLD_HTMSC_CONTENT_SEL_LEN = 6745; // 26 -const static uint64_t SH_FLD_HTMSC_COUNT = 6746; // 24 -const static uint64_t SH_FLD_HTMSC_COUNT_LEN = 6747; // 24 -const static uint64_t SH_FLD_HTMSC_CRESPFILT_INVERT = 6748; // 2 -const static uint64_t SH_FLD_HTMSC_CRESP_MASK = 6749; // 2 -const static uint64_t SH_FLD_HTMSC_CRESP_MASK_LEN = 6750; // 2 -const static uint64_t SH_FLD_HTMSC_CRESP_PAT = 6751; // 2 -const static uint64_t SH_FLD_HTMSC_CRESP_PAT_LEN = 6752; // 2 -const static uint64_t SH_FLD_HTMSC_DBG0_STOP = 6753; // 26 -const static uint64_t SH_FLD_HTMSC_DBG1_STOP = 6754; // 26 -const static uint64_t SH_FLD_HTMSC_DD1EQUIV = 6755; // 24 -const static uint64_t SH_FLD_HTMSC_DIS_DRP_PRIORITY_INCR = 6756; // 2 -const static uint64_t SH_FLD_HTMSC_DIS_FORCE_GROUP_SCOPE = 6757; // 2 -const static uint64_t SH_FLD_HTMSC_DIS_GROUP = 6758; // 24 -const static uint64_t SH_FLD_HTMSC_DIS_OPER_HANG = 6759; // 2 -const static uint64_t SH_FLD_HTMSC_DIS_RETRY_BACKOFF = 6760; // 2 -const static uint64_t SH_FLD_HTMSC_DIS_STALL = 6761; // 24 -const static uint64_t SH_FLD_HTMSC_DIS_TSTAMP = 6762; // 26 -const static uint64_t SH_FLD_HTMSC_ENABLE = 6763; // 26 -const static uint64_t SH_FLD_HTMSC_ENABLE_SPLIT_CORE = 6764; // 24 -const static uint64_t SH_FLD_HTMSC_ERROR = 6765; // 24 -const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL0 = 6766; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL0_LEN = 6767; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL1 = 6768; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL1_LEN = 6769; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL2 = 6770; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL2_LEN = 6771; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL0 = 6772; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL0_LEN = 6773; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL1 = 6774; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL1_LEN = 6775; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL2 = 6776; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL2_LEN = 6777; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL3 = 6778; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL3_LEN = 6779; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL4 = 6780; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL4_LEN = 6781; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL5 = 6782; // 2 -const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL5_LEN = 6783; // 2 -const static uint64_t SH_FLD_HTMSC_FSM = 6784; // 24 -const static uint64_t SH_FLD_HTMSC_FSM_LEN = 6785; // 24 -const static uint64_t SH_FLD_HTMSC_INVERT = 6786; // 2 -const static uint64_t SH_FLD_HTMSC_LEN = 6787; // 24 -const static uint64_t SH_FLD_HTMSC_MARK = 6788; // 26 -const static uint64_t SH_FLD_HTMSC_MARKERS_ONLY = 6789; // 26 -const static uint64_t SH_FLD_HTMSC_MARK_LEN = 6790; // 26 -const static uint64_t SH_FLD_HTMSC_MARK_TYPE = 6791; // 26 -const static uint64_t SH_FLD_HTMSC_MARK_TYPE_LEN = 6792; // 26 -const static uint64_t SH_FLD_HTMSC_MARK_VALID = 6793; // 26 -const static uint64_t SH_FLD_HTMSC_MASK = 6794; // 4 -const static uint64_t SH_FLD_HTMSC_MASK_LEN = 6795; // 4 -const static uint64_t SH_FLD_HTMSC_MTSPR_MARK = 6796; // 24 -const static uint64_t SH_FLD_HTMSC_MTSPR_TRIG = 6797; // 24 -const static uint64_t SH_FLD_HTMSC_OPER_HANG_DIV_RATIO = 6798; // 2 -const static uint64_t SH_FLD_HTMSC_OPER_HANG_DIV_RATIO_LEN = 6799; // 2 -const static uint64_t SH_FLD_HTMSC_OTHER_DBG0_STOP = 6800; // 2 -const static uint64_t SH_FLD_HTMSC_PAT = 6801; // 4 -const static uint64_t SH_FLD_HTMSC_PAT_LEN = 6802; // 4 -const static uint64_t SH_FLD_HTMSC_PAUSE = 6803; // 26 -const static uint64_t SH_FLD_HTMSC_PDBAR_ERROR = 6804; // 24 -const static uint64_t SH_FLD_HTMSC_PRIORITY = 6805; // 26 -const static uint64_t SH_FLD_HTMSC_RESERVED = 6806; // 24 -const static uint64_t SH_FLD_HTMSC_RESERVED_LEN = 6807; // 24 -const static uint64_t SH_FLD_HTMSC_RESET = 6808; // 26 -const static uint64_t SH_FLD_HTMSC_RTY_DRP_COUNT = 6809; // 2 -const static uint64_t SH_FLD_HTMSC_RTY_DRP_COUNT_LEN = 6810; // 2 -const static uint64_t SH_FLD_HTMSC_RUN_STOP = 6811; // 26 -const static uint64_t SH_FLD_HTMSC_SCOPE = 6812; // 50 -const static uint64_t SH_FLD_HTMSC_SCOPE_LEN = 6813; // 50 -const static uint64_t SH_FLD_HTMSC_SINGLE_TSTAMP = 6814; // 26 -const static uint64_t SH_FLD_HTMSC_SIZE = 6815; // 26 -const static uint64_t SH_FLD_HTMSC_SIZE_LEN = 6816; // 26 -const static uint64_t SH_FLD_HTMSC_SIZE_SMALL = 6817; // 26 -const static uint64_t SH_FLD_HTMSC_SPARE = 6818; // 24 -const static uint64_t SH_FLD_HTMSC_SPARE0 = 6819; // 24 -const static uint64_t SH_FLD_HTMSC_SPARE1012 = 6820; // 2 -const static uint64_t SH_FLD_HTMSC_SPARE1012_LEN = 6821; // 2 -const static uint64_t SH_FLD_HTMSC_SPARE1112 = 6822; // 24 -const static uint64_t SH_FLD_HTMSC_SPARE1112_LEN = 6823; // 24 -const static uint64_t SH_FLD_HTMSC_SPARE1415 = 6824; // 26 -const static uint64_t SH_FLD_HTMSC_SPARE1415_LEN = 6825; // 26 -const static uint64_t SH_FLD_HTMSC_SPARE16 = 6826; // 2 -const static uint64_t SH_FLD_HTMSC_SPARE23 = 6827; // 2 -const static uint64_t SH_FLD_HTMSC_SPARE2TO4 = 6828; // 24 -const static uint64_t SH_FLD_HTMSC_SPARE2TO4_LEN = 6829; // 24 -const static uint64_t SH_FLD_HTMSC_SPARE3 = 6830; // 2 -const static uint64_t SH_FLD_HTMSC_SPARE4043 = 6831; // 2 -const static uint64_t SH_FLD_HTMSC_SPARE4043_LEN = 6832; // 2 -const static uint64_t SH_FLD_HTMSC_SPARE67 = 6833; // 2 -const static uint64_t SH_FLD_HTMSC_SPARE67_LEN = 6834; // 2 -const static uint64_t SH_FLD_HTMSC_SPARES = 6835; // 24 -const static uint64_t SH_FLD_HTMSC_SPARES_LEN = 6836; // 24 -const static uint64_t SH_FLD_HTMSC_SPARE_1TO2 = 6837; // 24 -const static uint64_t SH_FLD_HTMSC_SPARE_1TO2_LEN = 6838; // 24 -const static uint64_t SH_FLD_HTMSC_SPARE_LEN = 6839; // 24 -const static uint64_t SH_FLD_HTMSC_START = 6840; // 26 -const static uint64_t SH_FLD_HTMSC_STOP = 6841; // 26 -const static uint64_t SH_FLD_HTMSC_STOP_ALT = 6842; // 26 -const static uint64_t SH_FLD_HTMSC_SYNC_STAMP_FORCE = 6843; // 2 -const static uint64_t SH_FLD_HTMSC_SYNC_STAMP_FORCE_LEN = 6844; // 2 -const static uint64_t SH_FLD_HTMSC_TRACE_ACTIVE = 6845; // 24 -const static uint64_t SH_FLD_HTMSC_TRIG = 6846; // 26 -const static uint64_t SH_FLD_HTMSC_TRIG_LEN = 6847; // 26 -const static uint64_t SH_FLD_HTMSC_TSIZEFILT_MASK = 6848; // 2 -const static uint64_t SH_FLD_HTMSC_TSIZEFILT_MASK_LEN = 6849; // 2 -const static uint64_t SH_FLD_HTMSC_TSIZEFILT_PAT = 6850; // 2 -const static uint64_t SH_FLD_HTMSC_TSIZEFILT_PAT_LEN = 6851; // 2 -const static uint64_t SH_FLD_HTMSC_VGTARGET = 6852; // 26 -const static uint64_t SH_FLD_HTMSC_VGTARGET_LEN = 6853; // 26 -const static uint64_t SH_FLD_HTMSC_WRAP = 6854; // 26 -const static uint64_t SH_FLD_HTMSC_WRITETOIO = 6855; // 2 -const static uint64_t SH_FLD_HTMSC_XSTOP_STOP = 6856; // 26 -const static uint64_t SH_FLD_HTM_CMD_OVERRUN = 6857; // 1 -const static uint64_t SH_FLD_HTM_IMA_TIMEOUT = 6858; // 12 -const static uint64_t SH_FLD_HTM_MARKER_SLAVE_ADRS = 6859; // 1 -const static uint64_t SH_FLD_HTM_MARKER_SLAVE_ADRS_LEN = 6860; // 1 -const static uint64_t SH_FLD_HTM_QUEUE_LIMIT = 6861; // 12 -const static uint64_t SH_FLD_HTM_QUEUE_LIMIT_LEN = 6862; // 12 -const static uint64_t SH_FLD_HTM_SRC_SEL = 6863; // 1 -const static uint64_t SH_FLD_HTM_SRC_SEL_LEN = 6864; // 1 -const static uint64_t SH_FLD_HTM_STOP = 6865; // 1 -const static uint64_t SH_FLD_HTM_TRACE_MODE = 6866; // 1 -const static uint64_t SH_FLD_HUC = 6867; // 1 -const static uint64_t SH_FLD_HUC_LEN = 6868; // 1 -const static uint64_t SH_FLD_HUT = 6869; // 1 -const static uint64_t SH_FLD_HUT_LEN = 6870; // 1 -const static uint64_t SH_FLD_HWCTRL = 6871; // 2 -const static uint64_t SH_FLD_HWCTRL_CLOCK_DIVIDER = 6872; // 1 -const static uint64_t SH_FLD_HWCTRL_CLOCK_DIVIDER_LEN = 6873; // 1 -const static uint64_t SH_FLD_HWCTRL_CPHA = 6874; // 1 -const static uint64_t SH_FLD_HWCTRL_CPOL = 6875; // 1 -const static uint64_t SH_FLD_HWCTRL_DEVICE = 6876; // 1 -const static uint64_t SH_FLD_HWCTRL_FRAME_SIZE = 6877; // 1 -const static uint64_t SH_FLD_HWCTRL_FRAME_SIZE_LEN = 6878; // 1 -const static uint64_t SH_FLD_HWCTRL_FSM_ENABLE = 6879; // 1 -const static uint64_t SH_FLD_HWCTRL_FSM_ERR = 6880; // 1 -const static uint64_t SH_FLD_HWCTRL_INTER_FRAME_DELAY = 6881; // 1 -const static uint64_t SH_FLD_HWCTRL_INTER_FRAME_DELAY_LEN = 6882; // 1 -const static uint64_t SH_FLD_HWCTRL_INVALID_NUMBER_OF_FRAMES = 6883; // 1 -const static uint64_t SH_FLD_HWCTRL_IN_COUNT = 6884; // 1 -const static uint64_t SH_FLD_HWCTRL_IN_COUNT_LEN = 6885; // 1 -const static uint64_t SH_FLD_HWCTRL_IN_DELAY = 6886; // 1 -const static uint64_t SH_FLD_HWCTRL_IN_DELAY_LEN = 6887; // 1 -const static uint64_t SH_FLD_HWCTRL_LEN = 6888; // 2 -const static uint64_t SH_FLD_HWCTRL_NR_OF_FRAMES = 6889; // 1 -const static uint64_t SH_FLD_HWCTRL_NR_OF_FRAMES_LEN = 6890; // 1 -const static uint64_t SH_FLD_HWCTRL_ONGOING = 6891; // 1 -const static uint64_t SH_FLD_HWCTRL_OUT_COUNT = 6892; // 1 -const static uint64_t SH_FLD_HWCTRL_OUT_COUNT_LEN = 6893; // 1 -const static uint64_t SH_FLD_HWCTRL_RDATA0 = 6894; // 1 -const static uint64_t SH_FLD_HWCTRL_RDATA0_LEN = 6895; // 1 -const static uint64_t SH_FLD_HWCTRL_RDATA1 = 6896; // 1 -const static uint64_t SH_FLD_HWCTRL_RDATA1_LEN = 6897; // 1 -const static uint64_t SH_FLD_HWCTRL_RDATA2 = 6898; // 1 -const static uint64_t SH_FLD_HWCTRL_RDATA2_LEN = 6899; // 1 -const static uint64_t SH_FLD_HWCTRL_RDATA3 = 6900; // 1 -const static uint64_t SH_FLD_HWCTRL_RDATA3_LEN = 6901; // 1 -const static uint64_t SH_FLD_HWCTRL_START_SAMPLING = 6902; // 1 -const static uint64_t SH_FLD_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 6903; // 1 -const static uint64_t SH_FLD_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR = 6904; // 1 -const static uint64_t SH_FLD_HWD = 6905; // 1 -const static uint64_t SH_FLD_HWD_0 = 6906; // 1 -const static uint64_t SH_FLD_HWD_0_LEN = 6907; // 1 -const static uint64_t SH_FLD_HWD_10 = 6908; // 1 -const static uint64_t SH_FLD_HWD_10_LEN = 6909; // 1 -const static uint64_t SH_FLD_HWD_11 = 6910; // 1 -const static uint64_t SH_FLD_HWD_11_LEN = 6911; // 1 -const static uint64_t SH_FLD_HWD_12 = 6912; // 1 -const static uint64_t SH_FLD_HWD_12_LEN = 6913; // 1 -const static uint64_t SH_FLD_HWD_13 = 6914; // 1 -const static uint64_t SH_FLD_HWD_13_LEN = 6915; // 1 -const static uint64_t SH_FLD_HWD_14 = 6916; // 1 -const static uint64_t SH_FLD_HWD_14_LEN = 6917; // 1 -const static uint64_t SH_FLD_HWD_15 = 6918; // 1 -const static uint64_t SH_FLD_HWD_15_LEN = 6919; // 1 -const static uint64_t SH_FLD_HWD_2 = 6920; // 1 -const static uint64_t SH_FLD_HWD_2_LEN = 6921; // 1 -const static uint64_t SH_FLD_HWD_3 = 6922; // 1 -const static uint64_t SH_FLD_HWD_3_LEN = 6923; // 1 -const static uint64_t SH_FLD_HWD_4 = 6924; // 1 -const static uint64_t SH_FLD_HWD_4_LEN = 6925; // 1 -const static uint64_t SH_FLD_HWD_5 = 6926; // 1 -const static uint64_t SH_FLD_HWD_5_LEN = 6927; // 1 -const static uint64_t SH_FLD_HWD_6 = 6928; // 1 -const static uint64_t SH_FLD_HWD_6_LEN = 6929; // 1 -const static uint64_t SH_FLD_HWD_7 = 6930; // 1 -const static uint64_t SH_FLD_HWD_7_LEN = 6931; // 1 -const static uint64_t SH_FLD_HWD_8 = 6932; // 1 -const static uint64_t SH_FLD_HWD_8_LEN = 6933; // 1 -const static uint64_t SH_FLD_HWD_9 = 6934; // 1 -const static uint64_t SH_FLD_HWD_9_LEN = 6935; // 1 -const static uint64_t SH_FLD_HWD_LEN = 6936; // 1 -const static uint64_t SH_FLD_HWD_PRIORITY = 6937; // 1 -const static uint64_t SH_FLD_HWD_PRIORITY_LEN = 6938; // 1 -const static uint64_t SH_FLD_HWD_RSD = 6939; // 1 -const static uint64_t SH_FLD_HWD_RSD_LEN = 6940; // 1 -const static uint64_t SH_FLD_HW_CONTROL_ERROR = 6941; // 12 -const static uint64_t SH_FLD_HW_DIR_INTIATED_LINE_DELETE_OCCURRED = 6942; // 12 -const static uint64_t SH_FLD_HW_ERRORS = 6943; // 9 -const static uint64_t SH_FLD_HW_ERRORS_MASK = 6944; // 9 -const static uint64_t SH_FLD_HYPERVISOR = 6945; // 2 -const static uint64_t SH_FLD_HYP_RECOURCE_ERR = 6946; // 96 -const static uint64_t SH_FLD_HYP_SPECIAL_WKUP = 6947; // 30 -const static uint64_t SH_FLD_HYP_VIRT_EXIT_ENABLE = 6948; // 96 -const static uint64_t SH_FLD_I2CM_ECC_ERRORS = 6949; // 1 -const static uint64_t SH_FLD_I2CM_ECC_ERRORS_LEN = 6950; // 1 -const static uint64_t SH_FLD_I2CM_I2C_ERRORS = 6951; // 1 -const static uint64_t SH_FLD_I2CM_I2C_ERRORS_LEN = 6952; // 1 -const static uint64_t SH_FLD_I2CM_INTER = 6953; // 1 -const static uint64_t SH_FLD_I2CM_INTR_STATUS = 6954; // 1 -const static uint64_t SH_FLD_I2CM_INTR_STATUS_LEN = 6955; // 1 -const static uint64_t SH_FLD_I2CM_PIB_ERRORS = 6956; // 1 -const static uint64_t SH_FLD_I2CM_PIB_ERRORS_LEN = 6957; // 1 -const static uint64_t SH_FLD_I2C_BUS_HELD_MODE_ENABLE = 6958; // 1 -const static uint64_t SH_FLD_I2C_EXTENDER = 6959; // 1 -const static uint64_t SH_FLD_I2C_SPEED_MUX = 6960; // 1 -const static uint64_t SH_FLD_I2C_SPEED_MUX_LEN = 6961; // 1 -const static uint64_t SH_FLD_I2C_TIMEOUT = 6962; // 1 -const static uint64_t SH_FLD_I2C_TIMEOUT_LEN = 6963; // 1 -const static uint64_t SH_FLD_IBWR_MASK = 6964; // 3 -const static uint64_t SH_FLD_IBWR_MASK_LEN = 6965; // 3 -const static uint64_t SH_FLD_ICACHE_ERR = 6966; // 21 -const static uint64_t SH_FLD_ICACHE_TAG_ADDR = 6967; // 21 -const static uint64_t SH_FLD_ICACHE_TAG_ADDR_LEN = 6968; // 21 -const static uint64_t SH_FLD_ICACHE_VALID = 6969; // 21 -const static uint64_t SH_FLD_ICACHE_VALID_LEN = 6970; // 21 -const static uint64_t SH_FLD_ICE_COUNT = 6971; // 2 -const static uint64_t SH_FLD_ICE_COUNT_LEN = 6972; // 2 -const static uint64_t SH_FLD_ICE_ETE_ATTN = 6973; // 10 -const static uint64_t SH_FLD_ICS_INVALID_STATE = 6974; // 1 -const static uint64_t SH_FLD_ICU_RNW = 6975; // 1 -const static uint64_t SH_FLD_ICU_TIMEOUT_ERROR = 6976; // 1 -const static uint64_t SH_FLD_ID = 6977; // 131 -const static uint64_t SH_FLD_IDIAL = 6978; // 58 -const static uint64_t SH_FLD_IDIAL_AMO_ADDR = 6979; // 3 -const static uint64_t SH_FLD_IDIAL_ATS = 6980; // 1 -const static uint64_t SH_FLD_IDIAL_ATS_ESR_MSK = 6981; // 1 -const static uint64_t SH_FLD_IDIAL_ATS_ESR_MSK_LEN = 6982; // 1 -const static uint64_t SH_FLD_IDIAL_ATS_FER_MSK = 6983; // 1 -const static uint64_t SH_FLD_IDIAL_ATS_FER_MSK_LEN = 6984; // 1 -const static uint64_t SH_FLD_IDIAL_ATS_LEN = 6985; // 1 -const static uint64_t SH_FLD_IDIAL_BBRD = 6986; // 3 -const static uint64_t SH_FLD_IDIAL_BBRD_LEN = 6987; // 3 -const static uint64_t SH_FLD_IDIAL_BR_CE = 6988; // 3 -const static uint64_t SH_FLD_IDIAL_BR_CE_LEN = 6989; // 3 -const static uint64_t SH_FLD_IDIAL_BR_SUE = 6990; // 3 -const static uint64_t SH_FLD_IDIAL_BR_SUE_LEN = 6991; // 3 -const static uint64_t SH_FLD_IDIAL_BR_UE = 6992; // 3 -const static uint64_t SH_FLD_IDIAL_BR_UE_LEN = 6993; // 3 -const static uint64_t SH_FLD_IDIAL_CONFIG1 = 6994; // 3 -const static uint64_t SH_FLD_IDIAL_COUNT0 = 6995; // 3 -const static uint64_t SH_FLD_IDIAL_COUNT0_LEN = 6996; // 3 -const static uint64_t SH_FLD_IDIAL_COUNT1 = 6997; // 3 -const static uint64_t SH_FLD_IDIAL_COUNT1_LEN = 6998; // 3 -const static uint64_t SH_FLD_IDIAL_COUNT2 = 6999; // 3 -const static uint64_t SH_FLD_IDIAL_COUNT2_LEN = 7000; // 3 -const static uint64_t SH_FLD_IDIAL_COUNT3 = 7001; // 3 -const static uint64_t SH_FLD_IDIAL_COUNT3_LEN = 7002; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_0 = 7003; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_1 = 7004; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_2 = 7005; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_3 = 7006; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_4 = 7007; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_5 = 7008; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_6 = 7009; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_7 = 7010; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_0 = 7011; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_1 = 7012; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_2 = 7013; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_3 = 7014; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_4 = 7015; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_5 = 7016; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_6 = 7017; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_7 = 7018; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_0 = 7019; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_1 = 7020; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_2 = 7021; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_3 = 7022; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_0 = 7023; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_1 = 7024; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_2 = 7025; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_3 = 7026; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_4 = 7027; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_5 = 7028; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_6 = 7029; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_7 = 7030; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_0 = 7031; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_1 = 7032; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_2 = 7033; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_3 = 7034; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_4 = 7035; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_5 = 7036; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_6 = 7037; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_7 = 7038; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_0 = 7039; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_1 = 7040; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_10 = 7041; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_11 = 7042; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_12 = 7043; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_13 = 7044; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_14 = 7045; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_15 = 7046; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_2 = 7047; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_3 = 7048; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_4 = 7049; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_5 = 7050; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_6 = 7051; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_7 = 7052; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_8 = 7053; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_9 = 7054; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_0 = 7055; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_1 = 7056; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_10 = 7057; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_11 = 7058; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_12 = 7059; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_13 = 7060; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_14 = 7061; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_15 = 7062; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_16 = 7063; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_17 = 7064; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_18 = 7065; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_19 = 7066; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_2 = 7067; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_20 = 7068; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_21 = 7069; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_22 = 7070; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_23 = 7071; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_3 = 7072; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_4 = 7073; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_5 = 7074; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_6 = 7075; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_7 = 7076; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_8 = 7077; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_9 = 7078; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_0 = 7079; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_1 = 7080; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_2 = 7081; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_3 = 7082; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_4 = 7083; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_5 = 7084; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_6 = 7085; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_7 = 7086; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_0 = 7087; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_1 = 7088; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_2 = 7089; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_3 = 7090; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_4 = 7091; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_5 = 7092; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_6 = 7093; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_7 = 7094; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_0 = 7095; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_1 = 7096; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_2 = 7097; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_3 = 7098; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_4 = 7099; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_5 = 7100; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_6 = 7101; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_7 = 7102; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_0 = 7103; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_1 = 7104; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_2 = 7105; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_3 = 7106; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_4 = 7107; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_5 = 7108; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_6 = 7109; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_7 = 7110; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_0 = 7111; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_1 = 7112; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_2 = 7113; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_3 = 7114; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_0 = 7115; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_1 = 7116; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_2 = 7117; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_3 = 7118; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_0 = 7119; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_1 = 7120; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_2 = 7121; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_3 = 7122; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_0 = 7123; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_1 = 7124; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_2 = 7125; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_3 = 7126; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV4_0 = 7127; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV4_1 = 7128; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV4_2 = 7129; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV4_3 = 7130; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_0 = 7131; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_1 = 7132; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_2 = 7133; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_3 = 7134; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_4 = 7135; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_5 = 7136; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_6 = 7137; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_7 = 7138; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_0 = 7139; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_1 = 7140; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_2 = 7141; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_3 = 7142; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_4 = 7143; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_5 = 7144; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_6 = 7145; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_7 = 7146; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_0 = 7147; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_1 = 7148; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_2 = 7149; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_3 = 7150; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_0 = 7151; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_1 = 7152; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_2 = 7153; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_3 = 7154; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_4 = 7155; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_5 = 7156; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_6 = 7157; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_7 = 7158; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_0 = 7159; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_1 = 7160; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_2 = 7161; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_3 = 7162; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_4 = 7163; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_5 = 7164; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_6 = 7165; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_7 = 7166; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_0 = 7167; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_1 = 7168; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_10 = 7169; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_11 = 7170; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_12 = 7171; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_13 = 7172; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_14 = 7173; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_15 = 7174; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_2 = 7175; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_3 = 7176; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_4 = 7177; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_5 = 7178; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_6 = 7179; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_7 = 7180; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_8 = 7181; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_9 = 7182; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_0 = 7183; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_1 = 7184; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_10 = 7185; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_11 = 7186; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_12 = 7187; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_13 = 7188; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_14 = 7189; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_15 = 7190; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_16 = 7191; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_17 = 7192; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_18 = 7193; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_19 = 7194; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_2 = 7195; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_20 = 7196; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_21 = 7197; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_22 = 7198; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_23 = 7199; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_3 = 7200; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_4 = 7201; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_5 = 7202; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_6 = 7203; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_7 = 7204; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_8 = 7205; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_9 = 7206; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_0 = 7207; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_1 = 7208; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_2 = 7209; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_3 = 7210; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_4 = 7211; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_5 = 7212; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_6 = 7213; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_7 = 7214; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_0 = 7215; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_1 = 7216; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_2 = 7217; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_3 = 7218; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_4 = 7219; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_5 = 7220; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_6 = 7221; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_7 = 7222; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_0 = 7223; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_1 = 7224; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_2 = 7225; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_3 = 7226; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_4 = 7227; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_5 = 7228; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_6 = 7229; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_7 = 7230; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_0 = 7231; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_1 = 7232; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_2 = 7233; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_3 = 7234; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_4 = 7235; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_5 = 7236; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_6 = 7237; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_7 = 7238; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_0 = 7239; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_1 = 7240; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_2 = 7241; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_3 = 7242; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_0 = 7243; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_1 = 7244; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_2 = 7245; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_3 = 7246; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_0 = 7247; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_1 = 7248; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_2 = 7249; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_3 = 7250; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_0 = 7251; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_1 = 7252; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_2 = 7253; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_3 = 7254; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV4_0 = 7255; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV4_1 = 7256; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV4_2 = 7257; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV4_3 = 7258; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_0 = 7259; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_1 = 7260; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_2 = 7261; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_3 = 7262; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_4 = 7263; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_5 = 7264; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_6 = 7265; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_7 = 7266; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_0 = 7267; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_1 = 7268; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_2 = 7269; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_3 = 7270; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_4 = 7271; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_5 = 7272; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_6 = 7273; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_7 = 7274; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_0 = 7275; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_1 = 7276; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_2 = 7277; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_3 = 7278; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_0 = 7279; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_1 = 7280; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_2 = 7281; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_3 = 7282; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_4 = 7283; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_5 = 7284; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_6 = 7285; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_7 = 7286; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_0 = 7287; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_1 = 7288; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_2 = 7289; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_3 = 7290; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_4 = 7291; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_5 = 7292; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_6 = 7293; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_7 = 7294; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_0 = 7295; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_1 = 7296; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_10 = 7297; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_11 = 7298; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_12 = 7299; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_13 = 7300; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_14 = 7301; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_15 = 7302; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_2 = 7303; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_3 = 7304; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_4 = 7305; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_5 = 7306; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_6 = 7307; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_7 = 7308; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_8 = 7309; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_9 = 7310; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_0 = 7311; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_1 = 7312; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_10 = 7313; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_11 = 7314; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_12 = 7315; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_13 = 7316; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_14 = 7317; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_15 = 7318; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_16 = 7319; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_17 = 7320; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_18 = 7321; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_19 = 7322; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_2 = 7323; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_20 = 7324; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_21 = 7325; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_22 = 7326; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_23 = 7327; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_3 = 7328; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_4 = 7329; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_5 = 7330; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_6 = 7331; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_7 = 7332; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_8 = 7333; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_9 = 7334; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_0 = 7335; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_1 = 7336; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_2 = 7337; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_3 = 7338; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_4 = 7339; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_5 = 7340; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_6 = 7341; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_7 = 7342; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_0 = 7343; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_1 = 7344; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_2 = 7345; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_3 = 7346; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_4 = 7347; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_5 = 7348; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_6 = 7349; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_7 = 7350; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_0 = 7351; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_1 = 7352; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_2 = 7353; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_3 = 7354; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_4 = 7355; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_5 = 7356; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_6 = 7357; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_7 = 7358; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_0 = 7359; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_1 = 7360; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_2 = 7361; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_3 = 7362; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_4 = 7363; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_5 = 7364; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_6 = 7365; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_7 = 7366; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_REG_0 = 7367; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_REG_1 = 7368; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_REG_2 = 7369; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_REG_3 = 7370; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_0 = 7371; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_1 = 7372; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_2 = 7373; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_3 = 7374; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_0 = 7375; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_1 = 7376; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_2 = 7377; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_3 = 7378; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_0 = 7379; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_1 = 7380; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_2 = 7381; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_3 = 7382; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV4_0 = 7383; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV4_1 = 7384; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV4_2 = 7385; // 3 -const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV4_3 = 7386; // 3 -const static uint64_t SH_FLD_IDIAL_DEBUG0_CONFIG = 7387; // 3 -const static uint64_t SH_FLD_IDIAL_DEBUG1_CONFIG = 7388; // 3 -const static uint64_t SH_FLD_IDIAL_EA = 7389; // 2 -const static uint64_t SH_FLD_IDIAL_EA_LEN = 7390; // 2 -const static uint64_t SH_FLD_IDIAL_ECC_CONFIG = 7391; // 3 -const static uint64_t SH_FLD_IDIAL_ERRINJ = 7392; // 3 -const static uint64_t SH_FLD_IDIAL_IBRD = 7393; // 3 -const static uint64_t SH_FLD_IDIAL_IBRD_LEN = 7394; // 3 -const static uint64_t SH_FLD_IDIAL_IBUF_STATE = 7395; // 3 -const static uint64_t SH_FLD_IDIAL_IBUF_WRITE = 7396; // 3 -const static uint64_t SH_FLD_IDIAL_IR_CE = 7397; // 3 -const static uint64_t SH_FLD_IDIAL_IR_CE_LEN = 7398; // 3 -const static uint64_t SH_FLD_IDIAL_IR_SUE = 7399; // 3 -const static uint64_t SH_FLD_IDIAL_IR_SUE_LEN = 7400; // 3 -const static uint64_t SH_FLD_IDIAL_IR_UE = 7401; // 3 -const static uint64_t SH_FLD_IDIAL_IR_UE_LEN = 7402; // 3 -const static uint64_t SH_FLD_IDIAL_ISSYNC = 7403; // 1 -const static uint64_t SH_FLD_IDIAL_ISSYNC_LEN = 7404; // 1 -const static uint64_t SH_FLD_IDIAL_LEN = 7405; // 58 -const static uint64_t SH_FLD_IDIAL_MASK0 = 7406; // 1 -const static uint64_t SH_FLD_IDIAL_MASK0_LEN = 7407; // 1 -const static uint64_t SH_FLD_IDIAL_MISC_STATE = 7408; // 3 -const static uint64_t SH_FLD_IDIAL_MRG_STATE = 7409; // 3 -const static uint64_t SH_FLD_IDIAL_OBRD = 7410; // 3 -const static uint64_t SH_FLD_IDIAL_OBRD_LEN = 7411; // 3 -const static uint64_t SH_FLD_IDIAL_OBUF_STATE = 7412; // 3 -const static uint64_t SH_FLD_IDIAL_OR_CE = 7413; // 3 -const static uint64_t SH_FLD_IDIAL_OR_CE_LEN = 7414; // 3 -const static uint64_t SH_FLD_IDIAL_OR_SUE = 7415; // 3 -const static uint64_t SH_FLD_IDIAL_OR_SUE_LEN = 7416; // 3 -const static uint64_t SH_FLD_IDIAL_OR_UE = 7417; // 3 -const static uint64_t SH_FLD_IDIAL_OR_UE_LEN = 7418; // 3 -const static uint64_t SH_FLD_IDIAL_PAR = 7419; // 1 -const static uint64_t SH_FLD_IDIAL_PAR_LEN = 7420; // 1 -const static uint64_t SH_FLD_IDIAL_PBRX_RTAG = 7421; // 6 -const static uint64_t SH_FLD_IDIAL_PBTX_AMO = 7422; // 3 -const static uint64_t SH_FLD_IDIAL_PBTX_AMO_LEN = 7423; // 3 -const static uint64_t SH_FLD_IDIAL_PBTX_STATE = 7424; // 3 -const static uint64_t SH_FLD_IDIAL_PC = 7425; // 2 -const static uint64_t SH_FLD_IDIAL_PC_LEN = 7426; // 2 -const static uint64_t SH_FLD_IDIAL_PE = 7427; // 2 -const static uint64_t SH_FLD_IDIAL_PE_LEN = 7428; // 2 -const static uint64_t SH_FLD_IDIAL_PR_CE = 7429; // 3 -const static uint64_t SH_FLD_IDIAL_PR_CE_LEN = 7430; // 3 -const static uint64_t SH_FLD_IDIAL_PR_SUE = 7431; // 3 -const static uint64_t SH_FLD_IDIAL_PR_SUE_LEN = 7432; // 3 -const static uint64_t SH_FLD_IDIAL_PR_UE = 7433; // 3 -const static uint64_t SH_FLD_IDIAL_PR_UE_LEN = 7434; // 3 -const static uint64_t SH_FLD_IDIAL_PT_CE = 7435; // 3 -const static uint64_t SH_FLD_IDIAL_PT_CE_LEN = 7436; // 3 -const static uint64_t SH_FLD_IDIAL_PT_SUE = 7437; // 3 -const static uint64_t SH_FLD_IDIAL_PT_SUE_LEN = 7438; // 3 -const static uint64_t SH_FLD_IDIAL_PT_UE = 7439; // 3 -const static uint64_t SH_FLD_IDIAL_PT_UE_LEN = 7440; // 3 -const static uint64_t SH_FLD_IDIAL_RA = 7441; // 2 -const static uint64_t SH_FLD_IDIAL_RA_LEN = 7442; // 2 -const static uint64_t SH_FLD_IDIAL_REG0_RSVD0 = 7443; // 1 -const static uint64_t SH_FLD_IDIAL_REG0_RSVD0_LEN = 7444; // 1 -const static uint64_t SH_FLD_IDIAL_REG1_RSVD0 = 7445; // 1 -const static uint64_t SH_FLD_IDIAL_REG1_RSVD0_LEN = 7446; // 1 -const static uint64_t SH_FLD_IDIAL_RESERVED = 7447; // 3 -const static uint64_t SH_FLD_IDIAL_RNW = 7448; // 1 -const static uint64_t SH_FLD_IDIAL_RQIN_STATE = 7449; // 3 -const static uint64_t SH_FLD_IDIAL_RSVD0 = 7450; // 4 -const static uint64_t SH_FLD_IDIAL_RSVD0_LEN = 7451; // 4 -const static uint64_t SH_FLD_IDIAL_RSVD1 = 7452; // 2 -const static uint64_t SH_FLD_IDIAL_RSVD1_LEN = 7453; // 2 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_0 = 7454; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_1 = 7455; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_2 = 7456; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_3 = 7457; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_0 = 7458; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_1 = 7459; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_2 = 7460; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_3 = 7461; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_0 = 7462; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_1 = 7463; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_2 = 7464; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_3 = 7465; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_0 = 7466; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_1 = 7467; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_2 = 7468; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_3 = 7469; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_0 = 7470; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_1 = 7471; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_10 = 7472; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_11 = 7473; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_12 = 7474; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_13 = 7475; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_14 = 7476; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_15 = 7477; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_16 = 7478; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_17 = 7479; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_18 = 7480; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_19 = 7481; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_2 = 7482; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_20 = 7483; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_21 = 7484; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_22 = 7485; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_23 = 7486; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_24 = 7487; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_25 = 7488; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_26 = 7489; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_27 = 7490; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_28 = 7491; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_29 = 7492; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_3 = 7493; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_30 = 7494; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_31 = 7495; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_32 = 7496; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_33 = 7497; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_34 = 7498; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_35 = 7499; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_36 = 7500; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_37 = 7501; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_38 = 7502; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_39 = 7503; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_4 = 7504; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_40 = 7505; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_41 = 7506; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_42 = 7507; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_43 = 7508; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_44 = 7509; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_45 = 7510; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_46 = 7511; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_47 = 7512; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_48 = 7513; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_49 = 7514; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_5 = 7515; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_50 = 7516; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_51 = 7517; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_52 = 7518; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_53 = 7519; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_54 = 7520; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_55 = 7521; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_6 = 7522; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_7 = 7523; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_8 = 7524; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_9 = 7525; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_0 = 7526; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_1 = 7527; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_10 = 7528; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_11 = 7529; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_12 = 7530; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_13 = 7531; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_14 = 7532; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_15 = 7533; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_16 = 7534; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_17 = 7535; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_18 = 7536; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_19 = 7537; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_2 = 7538; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_20 = 7539; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_21 = 7540; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_22 = 7541; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_23 = 7542; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_3 = 7543; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_4 = 7544; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_5 = 7545; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_6 = 7546; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_7 = 7547; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_8 = 7548; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_9 = 7549; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_0 = 7550; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_1 = 7551; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_2 = 7552; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_3 = 7553; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_4 = 7554; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_5 = 7555; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_6 = 7556; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_7 = 7557; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_0 = 7558; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_1 = 7559; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_10 = 7560; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_11 = 7561; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_2 = 7562; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_3 = 7563; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_4 = 7564; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_5 = 7565; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_6 = 7566; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_7 = 7567; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_8 = 7568; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_9 = 7569; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_0 = 7570; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_1 = 7571; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_2 = 7572; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_3 = 7573; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_4 = 7574; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_5 = 7575; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_6 = 7576; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_7 = 7577; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_0 = 7578; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_1 = 7579; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_2 = 7580; // 12 -const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_3 = 7581; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_0 = 7582; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_1 = 7583; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_2 = 7584; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_3 = 7585; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_0 = 7586; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_1 = 7587; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_2 = 7588; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_3 = 7589; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_0 = 7590; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_1 = 7591; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_2 = 7592; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_3 = 7593; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_0 = 7594; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_1 = 7595; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_2 = 7596; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_3 = 7597; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_0 = 7598; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_1 = 7599; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_10 = 7600; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_11 = 7601; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_12 = 7602; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_13 = 7603; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_14 = 7604; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_15 = 7605; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_16 = 7606; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_17 = 7607; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_18 = 7608; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_19 = 7609; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_2 = 7610; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_20 = 7611; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_21 = 7612; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_22 = 7613; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_23 = 7614; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_24 = 7615; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_25 = 7616; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_26 = 7617; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_27 = 7618; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_28 = 7619; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_29 = 7620; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_3 = 7621; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_30 = 7622; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_31 = 7623; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_32 = 7624; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_33 = 7625; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_34 = 7626; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_35 = 7627; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_36 = 7628; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_37 = 7629; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_38 = 7630; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_39 = 7631; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_4 = 7632; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_40 = 7633; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_41 = 7634; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_42 = 7635; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_43 = 7636; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_44 = 7637; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_45 = 7638; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_46 = 7639; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_47 = 7640; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_48 = 7641; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_49 = 7642; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_5 = 7643; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_50 = 7644; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_51 = 7645; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_52 = 7646; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_53 = 7647; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_54 = 7648; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_55 = 7649; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_6 = 7650; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_7 = 7651; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_8 = 7652; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_9 = 7653; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_0 = 7654; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_1 = 7655; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_10 = 7656; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_11 = 7657; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_12 = 7658; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_13 = 7659; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_14 = 7660; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_15 = 7661; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_16 = 7662; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_17 = 7663; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_18 = 7664; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_19 = 7665; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_2 = 7666; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_20 = 7667; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_21 = 7668; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_22 = 7669; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_23 = 7670; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_3 = 7671; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_4 = 7672; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_5 = 7673; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_6 = 7674; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_7 = 7675; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_8 = 7676; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_9 = 7677; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_0 = 7678; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_1 = 7679; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_2 = 7680; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_3 = 7681; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_4 = 7682; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_5 = 7683; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_6 = 7684; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_7 = 7685; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_0 = 7686; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_1 = 7687; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_10 = 7688; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_11 = 7689; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_2 = 7690; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_3 = 7691; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_4 = 7692; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_5 = 7693; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_6 = 7694; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_7 = 7695; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_8 = 7696; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_9 = 7697; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_0 = 7698; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_1 = 7699; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_2 = 7700; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_3 = 7701; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_4 = 7702; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_5 = 7703; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_6 = 7704; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_7 = 7705; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_0 = 7706; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_1 = 7707; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_2 = 7708; // 12 -const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_3 = 7709; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_0 = 7710; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_1 = 7711; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_2 = 7712; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_3 = 7713; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_AUE_0 = 7714; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_AUE_1 = 7715; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_AUE_2 = 7716; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_AUE_3 = 7717; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_FWD_0 = 7718; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_FWD_1 = 7719; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_FWD_2 = 7720; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_FWD_3 = 7721; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NCF_0 = 7722; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NCF_1 = 7723; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NCF_2 = 7724; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NCF_3 = 7725; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_0 = 7726; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_1 = 7727; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_10 = 7728; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_11 = 7729; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_12 = 7730; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_13 = 7731; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_14 = 7732; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_15 = 7733; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_16 = 7734; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_17 = 7735; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_18 = 7736; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_19 = 7737; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_2 = 7738; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_20 = 7739; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_21 = 7740; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_22 = 7741; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_23 = 7742; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_24 = 7743; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_25 = 7744; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_26 = 7745; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_27 = 7746; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_28 = 7747; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_29 = 7748; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_3 = 7749; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_30 = 7750; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_31 = 7751; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_32 = 7752; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_33 = 7753; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_34 = 7754; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_35 = 7755; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_36 = 7756; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_37 = 7757; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_38 = 7758; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_39 = 7759; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_4 = 7760; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_40 = 7761; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_41 = 7762; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_42 = 7763; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_43 = 7764; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_44 = 7765; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_45 = 7766; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_46 = 7767; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_47 = 7768; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_48 = 7769; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_49 = 7770; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_5 = 7771; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_50 = 7772; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_51 = 7773; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_52 = 7774; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_53 = 7775; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_54 = 7776; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_55 = 7777; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_6 = 7778; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_7 = 7779; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_8 = 7780; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_9 = 7781; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_0 = 7782; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_1 = 7783; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_10 = 7784; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_11 = 7785; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_12 = 7786; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_13 = 7787; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_14 = 7788; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_15 = 7789; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_16 = 7790; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_17 = 7791; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_18 = 7792; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_19 = 7793; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_2 = 7794; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_20 = 7795; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_21 = 7796; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_22 = 7797; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_23 = 7798; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_3 = 7799; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_4 = 7800; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_5 = 7801; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_6 = 7802; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_7 = 7803; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_8 = 7804; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_9 = 7805; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_0 = 7806; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_1 = 7807; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_2 = 7808; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_3 = 7809; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_4 = 7810; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_5 = 7811; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_6 = 7812; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_7 = 7813; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_0 = 7814; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_1 = 7815; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_10 = 7816; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_11 = 7817; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_2 = 7818; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_3 = 7819; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_4 = 7820; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_5 = 7821; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_6 = 7822; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_7 = 7823; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_8 = 7824; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_9 = 7825; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_0 = 7826; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_1 = 7827; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_2 = 7828; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_3 = 7829; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_4 = 7830; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_5 = 7831; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_6 = 7832; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_7 = 7833; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBR_0 = 7834; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBR_1 = 7835; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBR_2 = 7836; // 12 -const static uint64_t SH_FLD_IDIAL_SM_MASK_PBR_3 = 7837; // 12 -const static uint64_t SH_FLD_IDIAL_TAG = 7838; // 1 -const static uint64_t SH_FLD_IDIAL_TAG_LEN = 7839; // 1 -const static uint64_t SH_FLD_IDIAL_VLD = 7840; // 1 -const static uint64_t SH_FLD_IDLE = 7841; // 2 -const static uint64_t SH_FLD_IDLES = 7842; // 64 -const static uint64_t SH_FLD_IDLES_LEN = 7843; // 64 -const static uint64_t SH_FLD_IDLE_PAT_ACTN = 7844; // 2 -const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_0_13 = 7845; // 2 -const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_0_13_LEN = 7846; // 2 -const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_14 = 7847; // 2 -const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_15 = 7848; // 2 -const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_16 = 7849; // 2 -const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_17 = 7850; // 2 -const static uint64_t SH_FLD_IDLE_PAT_BANK_0_1 = 7851; // 2 -const static uint64_t SH_FLD_IDLE_PAT_BANK_0_1_LEN = 7852; // 2 -const static uint64_t SH_FLD_IDLE_PAT_BANK_2 = 7853; // 2 -const static uint64_t SH_FLD_IDLE_PAT_BANK_GROUP_0 = 7854; // 2 -const static uint64_t SH_FLD_IDLE_PAT_BANK_GROUP_1 = 7855; // 2 -const static uint64_t SH_FLD_IDLE_PAT_PARITY = 7856; // 2 -const static uint64_t SH_FLD_ID_0 = 7857; // 1 -const static uint64_t SH_FLD_ID_0_LEN = 7858; // 1 -const static uint64_t SH_FLD_ID_1 = 7859; // 1 -const static uint64_t SH_FLD_ID_1_LEN = 7860; // 1 -const static uint64_t SH_FLD_ID_2 = 7861; // 1 -const static uint64_t SH_FLD_ID_2_LEN = 7862; // 1 -const static uint64_t SH_FLD_ID_3 = 7863; // 1 -const static uint64_t SH_FLD_ID_3_LEN = 7864; // 1 -const static uint64_t SH_FLD_ID_LEN = 7865; // 129 -const static uint64_t SH_FLD_IFC_REG_CERR0 = 7866; // 1 -const static uint64_t SH_FLD_IFC_REG_CERR1 = 7867; // 1 -const static uint64_t SH_FLD_IFC_REG_CERR2 = 7868; // 1 -const static uint64_t SH_FLD_IFC_REG_ERR0 = 7869; // 1 -const static uint64_t SH_FLD_IFC_REG_ERR1 = 7870; // 1 -const static uint64_t SH_FLD_IFC_REG_ERR2 = 7871; // 1 -const static uint64_t SH_FLD_IFC_REG_ERR3 = 7872; // 1 -const static uint64_t SH_FLD_IFC_REG_ERR4 = 7873; // 1 -const static uint64_t SH_FLD_IFC_REG_ERR5 = 7874; // 1 -const static uint64_t SH_FLD_IFC_REG_ERR6 = 7875; // 1 -const static uint64_t SH_FLD_IFC_REG_ERR7 = 7876; // 1 -const static uint64_t SH_FLD_IFC_REG_ERR8 = 7877; // 1 -const static uint64_t SH_FLD_IFREQ = 7878; // 1 -const static uint64_t SH_FLD_IGNORE_PECE = 7879; // 12 -const static uint64_t SH_FLD_ILLEGAL_CACHE_OP = 7880; // 1 -const static uint64_t SH_FLD_ILLEGAL_CACHE_OP_MASK = 7881; // 1 -const static uint64_t SH_FLD_ILLEGAL_LPC_BAR_ACCESS = 7882; // 4 -const static uint64_t SH_FLD_ILL_CRESP = 7883; // 1 -const static uint64_t SH_FLD_IMA_ACK_DEAD = 7884; // 12 -const static uint64_t SH_FLD_IMA_CRESP_ADDR_ERR = 7885; // 24 -const static uint64_t SH_FLD_IMA_FOREIGN0_ACK_DEAD = 7886; // 12 -const static uint64_t SH_FLD_IMA_FOREIGN1_ACK_DEAD = 7887; // 12 -const static uint64_t SH_FLD_IN = 7888; // 131 -const static uint64_t SH_FLD_IN0 = 7889; // 48 -const static uint64_t SH_FLD_IN1 = 7890; // 47 -const static uint64_t SH_FLD_IN10 = 7891; // 47 -const static uint64_t SH_FLD_IN11 = 7892; // 47 -const static uint64_t SH_FLD_IN12 = 7893; // 4 -const static uint64_t SH_FLD_IN12_LEN = 7894; // 1 -const static uint64_t SH_FLD_IN13 = 7895; // 3 -const static uint64_t SH_FLD_IN14 = 7896; // 4 -const static uint64_t SH_FLD_IN15 = 7897; // 4 -const static uint64_t SH_FLD_IN16 = 7898; // 4 -const static uint64_t SH_FLD_IN16_LEN = 7899; // 1 -const static uint64_t SH_FLD_IN17 = 7900; // 3 -const static uint64_t SH_FLD_IN18 = 7901; // 3 -const static uint64_t SH_FLD_IN19 = 7902; // 4 -const static uint64_t SH_FLD_IN2 = 7903; // 47 -const static uint64_t SH_FLD_IN20 = 7904; // 4 -const static uint64_t SH_FLD_IN21 = 7905; // 4 -const static uint64_t SH_FLD_IN21_LEN = 7906; // 3 -const static uint64_t SH_FLD_IN22 = 7907; // 1 -const static uint64_t SH_FLD_IN22_LEN = 7908; // 1 -const static uint64_t SH_FLD_IN24 = 7909; // 1 -const static uint64_t SH_FLD_IN25 = 7910; // 1 -const static uint64_t SH_FLD_IN26 = 7911; // 3 -const static uint64_t SH_FLD_IN27 = 7912; // 1 -const static uint64_t SH_FLD_IN28 = 7913; // 1 -const static uint64_t SH_FLD_IN29 = 7914; // 1 -const static uint64_t SH_FLD_IN29_LEN = 7915; // 1 -const static uint64_t SH_FLD_IN3 = 7916; // 47 -const static uint64_t SH_FLD_IN31 = 7917; // 1 -const static uint64_t SH_FLD_IN31_LEN = 7918; // 1 -const static uint64_t SH_FLD_IN33 = 7919; // 1 -const static uint64_t SH_FLD_IN33_LEN = 7920; // 1 -const static uint64_t SH_FLD_IN35 = 7921; // 1 -const static uint64_t SH_FLD_IN36 = 7922; // 1 -const static uint64_t SH_FLD_IN36_LEN = 7923; // 1 -const static uint64_t SH_FLD_IN4 = 7924; // 48 -const static uint64_t SH_FLD_IN40 = 7925; // 1 -const static uint64_t SH_FLD_IN5 = 7926; // 48 -const static uint64_t SH_FLD_IN6 = 7927; // 48 -const static uint64_t SH_FLD_IN7 = 7928; // 48 -const static uint64_t SH_FLD_IN8 = 7929; // 48 -const static uint64_t SH_FLD_IN9 = 7930; // 48 -const static uint64_t SH_FLD_INBAND_BAR_HIT_WITH_INCORRECT_TTYPE = 7931; // 4 -const static uint64_t SH_FLD_INBD_ARRAY_ECC_CE = 7932; // 2 -const static uint64_t SH_FLD_INBD_ARRAY_ECC_UE = 7933; // 2 -const static uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_CE = 7934; // 1 -const static uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_SUE = 7935; // 1 -const static uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_UE = 7936; // 1 -const static uint64_t SH_FLD_INCLUDE_TRAFFIC = 7937; // 1 -const static uint64_t SH_FLD_INCOMING_PB_PARITY_ERR = 7938; // 2 -const static uint64_t SH_FLD_INDEX = 7939; // 1 -const static uint64_t SH_FLD_INDEX_LEN = 7940; // 1 -const static uint64_t SH_FLD_INDIRECT_BRIDGE_0_SOURCE = 7941; // 1 -const static uint64_t SH_FLD_INDIRECT_BRIDGE_1_SOURCE = 7942; // 1 -const static uint64_t SH_FLD_INDIRECT_BRIDGE_2_SOURCE = 7943; // 1 -const static uint64_t SH_FLD_INDIRECT_BRIDGE_3_SOURCE = 7944; // 1 -const static uint64_t SH_FLD_INDIRECT_MODE = 7945; // 2 -const static uint64_t SH_FLD_INEX = 7946; // 43 -const static uint64_t SH_FLD_INFINITE_MODE = 7947; // 43 -const static uint64_t SH_FLD_INFO = 7948; // 43 -const static uint64_t SH_FLD_INFORMATION = 7949; // 8 -const static uint64_t SH_FLD_INFORMATION_LEN = 7950; // 8 -const static uint64_t SH_FLD_INFO_CAPTURED = 7951; // 4 -const static uint64_t SH_FLD_INH0_TICK = 7952; // 12 -const static uint64_t SH_FLD_INH0_TICK_LEN = 7953; // 12 -const static uint64_t SH_FLD_INH1_TICK = 7954; // 12 -const static uint64_t SH_FLD_INH1_TICK_LEN = 7955; // 12 -const static uint64_t SH_FLD_INIT = 7956; // 1 -const static uint64_t SH_FLD_INITIAL_COARSE_WR = 7957; // 8 -const static uint64_t SH_FLD_INITIAL_PAT_WRITE = 7958; // 8 -const static uint64_t SH_FLD_INIT_DONE_DL_MASK = 7959; // 2 -const static uint64_t SH_FLD_INIT_TMR_CFG = 7960; // 72 -const static uint64_t SH_FLD_INIT_TMR_CFG_LEN = 7961; // 72 -const static uint64_t SH_FLD_INJ = 7962; // 1 -const static uint64_t SH_FLD_INJECT_1HOT_SM_ERROR = 7963; // 8 -const static uint64_t SH_FLD_INJECT_CAL0_PAR_ERROR = 7964; // 8 -const static uint64_t SH_FLD_INJECT_ENABLE = 7965; // 1 -const static uint64_t SH_FLD_INJECT_ERR = 7966; // 12 -const static uint64_t SH_FLD_INJECT_FIR_ERR0 = 7967; // 8 -const static uint64_t SH_FLD_INJECT_FIR_ERR1 = 7968; // 8 -const static uint64_t SH_FLD_INJECT_FIR_ERR2 = 7969; // 8 -const static uint64_t SH_FLD_INJECT_FIR_ERR3 = 7970; // 8 -const static uint64_t SH_FLD_INJECT_FIR_ERR4 = 7971; // 8 -const static uint64_t SH_FLD_INJECT_MODE = 7972; // 2 -const static uint64_t SH_FLD_INJECT_MODE_LEN = 7973; // 2 -const static uint64_t SH_FLD_INJECT_TYPE = 7974; // 2 -const static uint64_t SH_FLD_INJECT_TYPE_LEN = 7975; // 2 -const static uint64_t SH_FLD_INJ_LEN = 7976; // 1 -const static uint64_t SH_FLD_INOP = 7977; // 43 -const static uint64_t SH_FLD_INOP_FORCE_SG = 7978; // 43 -const static uint64_t SH_FLD_INOP_LEN = 7979; // 43 -const static uint64_t SH_FLD_INOP_WAIT = 7980; // 43 -const static uint64_t SH_FLD_INOP_WAIT_LEN = 7981; // 43 -const static uint64_t SH_FLD_INPROG_WR_ERR = 7982; // 1 -const static uint64_t SH_FLD_INRD_DONE_ERR = 7983; // 1 -const static uint64_t SH_FLD_INSTANT_CACHE_VDM_DATA = 7984; // 12 -const static uint64_t SH_FLD_INSTANT_CACHE_VDM_DATA_LEN = 7985; // 12 -const static uint64_t SH_FLD_INSTANT_CORE0_VDM_DATA = 7986; // 12 -const static uint64_t SH_FLD_INSTANT_CORE0_VDM_DATA_LEN = 7987; // 12 -const static uint64_t SH_FLD_INSTANT_CORE1_VDM_DATA = 7988; // 12 -const static uint64_t SH_FLD_INSTANT_CORE1_VDM_DATA_LEN = 7989; // 12 -const static uint64_t SH_FLD_INSTANT_CORE2_VDM_DATA = 7990; // 12 -const static uint64_t SH_FLD_INSTANT_CORE2_VDM_DATA_LEN = 7991; // 12 -const static uint64_t SH_FLD_INSTANT_CORE3_VDM_DATA = 7992; // 12 -const static uint64_t SH_FLD_INSTANT_CORE3_VDM_DATA_LEN = 7993; // 12 -const static uint64_t SH_FLD_INSTANT_VDM_CONTROL_SUMMARY = 7994; // 12 -const static uint64_t SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN = 7995; // 12 -const static uint64_t SH_FLD_INSTR0_BUSYCNT_RUNNING = 7996; // 1 -const static uint64_t SH_FLD_INSTR0_CYCLECNT_RUNNING = 7997; // 1 -const static uint64_t SH_FLD_INSTR0_MODE = 7998; // 1 -const static uint64_t SH_FLD_INSTR0_MODE_LEN = 7999; // 1 -const static uint64_t SH_FLD_INSTR0_RESET = 8000; // 1 -const static uint64_t SH_FLD_INSTR0_START = 8001; // 1 -const static uint64_t SH_FLD_INSTR0_STOP = 8002; // 1 -const static uint64_t SH_FLD_INSTR0_STOPPED_ON_ERROR = 8003; // 1 -const static uint64_t SH_FLD_INSTR0_STOP_ON_ERROR_GT = 8004; // 1 -const static uint64_t SH_FLD_INSTR0_STOP_ON_ERROR_GT_LEN = 8005; // 1 -const static uint64_t SH_FLD_INSTR0_STOP_TIMER_EN = 8006; // 1 -const static uint64_t SH_FLD_INSTR1_BUSYCNT_RUNNING = 8007; // 1 -const static uint64_t SH_FLD_INSTR1_CYCLECNT_RUNNING = 8008; // 1 -const static uint64_t SH_FLD_INSTR1_MODE = 8009; // 1 -const static uint64_t SH_FLD_INSTR1_MODE_LEN = 8010; // 1 -const static uint64_t SH_FLD_INSTR1_RESET = 8011; // 1 -const static uint64_t SH_FLD_INSTR1_START = 8012; // 1 -const static uint64_t SH_FLD_INSTR1_STOP = 8013; // 1 -const static uint64_t SH_FLD_INSTR1_STOPPED_ON_ERROR = 8014; // 1 -const static uint64_t SH_FLD_INSTR1_STOP_ON_ERROR_GT = 8015; // 1 -const static uint64_t SH_FLD_INSTR1_STOP_ON_ERROR_GT_LEN = 8016; // 1 -const static uint64_t SH_FLD_INSTR1_STOP_TIMER_EN = 8017; // 1 -const static uint64_t SH_FLD_INSTR2_BUSYCNT_RUNNING = 8018; // 1 -const static uint64_t SH_FLD_INSTR2_CYCLECNT_RUNNING = 8019; // 1 -const static uint64_t SH_FLD_INSTR2_MODE = 8020; // 1 -const static uint64_t SH_FLD_INSTR2_MODE_LEN = 8021; // 1 -const static uint64_t SH_FLD_INSTR2_RESET = 8022; // 1 -const static uint64_t SH_FLD_INSTR2_START = 8023; // 1 -const static uint64_t SH_FLD_INSTR2_STOP = 8024; // 1 -const static uint64_t SH_FLD_INSTR2_STOPPED_ON_ERROR = 8025; // 1 -const static uint64_t SH_FLD_INSTR2_STOP_ON_ERROR_GT = 8026; // 1 -const static uint64_t SH_FLD_INSTR2_STOP_ON_ERROR_GT_LEN = 8027; // 1 -const static uint64_t SH_FLD_INSTR2_STOP_TIMER_EN = 8028; // 1 -const static uint64_t SH_FLD_INST_CYCLE_SAMPLE = 8029; // 12 -const static uint64_t SH_FLD_INST_CYCLE_SAMPLE_LEN = 8030; // 12 -const static uint64_t SH_FLD_INT = 8031; // 1 -const static uint64_t SH_FLD_INTERMITTENT_CE_COUNT = 8032; // 2 -const static uint64_t SH_FLD_INTERMITTENT_CE_COUNT_LEN = 8033; // 2 -const static uint64_t SH_FLD_INTERMITTENT_MCE_COUNT = 8034; // 2 -const static uint64_t SH_FLD_INTERMITTENT_MCE_COUNT_LEN = 8035; // 2 -const static uint64_t SH_FLD_INTERNAL_ERR = 8036; // 1 -const static uint64_t SH_FLD_INTERNAL_ERROR = 8037; // 4 -const static uint64_t SH_FLD_INTERNAL_ERR_MASK = 8038; // 1 -const static uint64_t SH_FLD_INTERNAL_FSM_ERROR = 8039; // 10 -const static uint64_t SH_FLD_INTERNAL_SCOM_ERROR = 8040; // 40 -const static uint64_t SH_FLD_INTERNAL_SCOM_ERROR_CLONE = 8041; // 16 -const static uint64_t SH_FLD_INTERNAL_SCOM_ERROR_COPY = 8042; // 24 -const static uint64_t SH_FLD_INTERNAL_STATE_VECTOR = 8043; // 1 -const static uint64_t SH_FLD_INTERNAL_STATE_VECTOR_LEN = 8044; // 1 -const static uint64_t SH_FLD_INTERRUPT0_ADDRESS_ERROR = 8045; // 4 -const static uint64_t SH_FLD_INTERRUPT1 = 8046; // 1 -const static uint64_t SH_FLD_INTERRUPT1_ADDRESS_ERROR = 8047; // 4 -const static uint64_t SH_FLD_INTERRUPT1_LEN = 8048; // 1 -const static uint64_t SH_FLD_INTERRUPT2 = 8049; // 2 -const static uint64_t SH_FLD_INTERRUPT2_ADDRESS_ERROR = 8050; // 4 -const static uint64_t SH_FLD_INTERRUPT2_LEN = 8051; // 2 -const static uint64_t SH_FLD_INTERRUPT3 = 8052; // 2 -const static uint64_t SH_FLD_INTERRUPT3_ADDRESS_ERROR = 8053; // 4 -const static uint64_t SH_FLD_INTERRUPT3_LEN = 8054; // 2 -const static uint64_t SH_FLD_INTERRUPT4 = 8055; // 2 -const static uint64_t SH_FLD_INTERRUPT4_ADDRESS_ERROR = 8056; // 4 -const static uint64_t SH_FLD_INTERRUPT4_LEN = 8057; // 2 -const static uint64_t SH_FLD_INTERRUPT5_ADDRESS_ERROR = 8058; // 4 -const static uint64_t SH_FLD_INTERRUPT_00 = 8059; // 1 -const static uint64_t SH_FLD_INTERRUPT_01 = 8060; // 1 -const static uint64_t SH_FLD_INTERRUPT_02 = 8061; // 1 -const static uint64_t SH_FLD_INTERRUPT_03 = 8062; // 1 -const static uint64_t SH_FLD_INTERRUPT_04 = 8063; // 1 -const static uint64_t SH_FLD_INTERRUPT_05 = 8064; // 1 -const static uint64_t SH_FLD_INTERRUPT_06 = 8065; // 1 -const static uint64_t SH_FLD_INTERRUPT_07 = 8066; // 1 -const static uint64_t SH_FLD_INTERRUPT_08 = 8067; // 1 -const static uint64_t SH_FLD_INTERRUPT_09 = 8068; // 1 -const static uint64_t SH_FLD_INTERRUPT_10 = 8069; // 1 -const static uint64_t SH_FLD_INTERRUPT_11 = 8070; // 1 -const static uint64_t SH_FLD_INTERRUPT_12 = 8071; // 1 -const static uint64_t SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE = 8072; // 4 -const static uint64_t SH_FLD_INTERRUPT_CONDITION_PENDING = 8073; // 1 -const static uint64_t SH_FLD_INTERRUPT_DISABLE = 8074; // 1 -const static uint64_t SH_FLD_INTERRUPT_DISABLE_LEN = 8075; // 1 -const static uint64_t SH_FLD_INTERRUPT_EDGE_POL_N = 8076; // 2 -const static uint64_t SH_FLD_INTERRUPT_EDGE_POL_N_LEN = 8077; // 2 -const static uint64_t SH_FLD_INTERRUPT_ENABLE = 8078; // 2 -const static uint64_t SH_FLD_INTERRUPT_ENABLED = 8079; // 1 -const static uint64_t SH_FLD_INTERRUPT_FROM_ERROR = 8080; // 4 -const static uint64_t SH_FLD_INTERRUPT_FROM_FSP = 8081; // 4 -const static uint64_t SH_FLD_INTERRUPT_INPUT = 8082; // 12 -const static uint64_t SH_FLD_INTERRUPT_INPUT_LEN = 8083; // 12 -const static uint64_t SH_FLD_INTERRUPT_MASK = 8084; // 12 -const static uint64_t SH_FLD_INTERRUPT_MASK_LEN = 8085; // 12 -const static uint64_t SH_FLD_INTERRUPT_MASK_N = 8086; // 2 -const static uint64_t SH_FLD_INTERRUPT_MASK_N_LEN = 8087; // 2 -const static uint64_t SH_FLD_INTERRUPT_POLARITY = 8088; // 12 -const static uint64_t SH_FLD_INTERRUPT_POLARITY_LEN = 8089; // 12 -const static uint64_t SH_FLD_INTERRUPT_ROUTE_A_N = 8090; // 6 -const static uint64_t SH_FLD_INTERRUPT_ROUTE_A_N_LEN = 8091; // 6 -const static uint64_t SH_FLD_INTERRUPT_S0 = 8092; // 1 -const static uint64_t SH_FLD_INTERRUPT_S1 = 8093; // 1 -const static uint64_t SH_FLD_INTERRUPT_SENT = 8094; // 1 -const static uint64_t SH_FLD_INTERRUPT_TYPE = 8095; // 12 -const static uint64_t SH_FLD_INTERRUPT_TYPE_LEN = 8096; // 12 -const static uint64_t SH_FLD_INTERRUPT_TYPE_N = 8097; // 2 -const static uint64_t SH_FLD_INTERRUPT_TYPE_N_LEN = 8098; // 2 -const static uint64_t SH_FLD_INTER_FRAME_DELAY = 8099; // 1 -const static uint64_t SH_FLD_INTER_FRAME_DELAY_LEN = 8100; // 1 -const static uint64_t SH_FLD_INTQ_FSM_PERR = 8101; // 1 -const static uint64_t SH_FLD_INTQ_OVERFLOW = 8102; // 1 -const static uint64_t SH_FLD_INTR0 = 8103; // 5 -const static uint64_t SH_FLD_INTR1 = 8104; // 5 -const static uint64_t SH_FLD_INTR_GRANTED = 8105; // 30 -const static uint64_t SH_FLD_INT_0 = 8106; // 2 -const static uint64_t SH_FLD_INT_0_LEN = 8107; // 2 -const static uint64_t SH_FLD_INT_1 = 8108; // 2 -const static uint64_t SH_FLD_INT_1_LEN = 8109; // 2 -const static uint64_t SH_FLD_INT_2 = 8110; // 2 -const static uint64_t SH_FLD_INT_2_LEN = 8111; // 2 -const static uint64_t SH_FLD_INT_3 = 8112; // 2 -const static uint64_t SH_FLD_INT_3_LEN = 8113; // 2 -const static uint64_t SH_FLD_INT_CNTR_REF = 8114; // 1 -const static uint64_t SH_FLD_INT_CNTR_REF_LEN = 8115; // 1 -const static uint64_t SH_FLD_INT_CURRENT_STATE = 8116; // 6 -const static uint64_t SH_FLD_INT_CURRENT_STATE_LEN = 8117; // 6 -const static uint64_t SH_FLD_INT_ENA = 8118; // 1 -const static uint64_t SH_FLD_INT_ENABLE_ENC = 8119; // 6 -const static uint64_t SH_FLD_INT_ENABLE_ENC_LEN = 8120; // 6 -const static uint64_t SH_FLD_INT_GOTO_STATE = 8121; // 6 -const static uint64_t SH_FLD_INT_GOTO_STATE_LEN = 8122; // 6 -const static uint64_t SH_FLD_INT_LEN = 8123; // 1 -const static uint64_t SH_FLD_INT_MODE = 8124; // 6 -const static uint64_t SH_FLD_INT_MODE_LEN = 8125; // 6 -const static uint64_t SH_FLD_INT_NCE_ETE_ATTN = 8126; // 10 -const static uint64_t SH_FLD_INT_NEXT_STATE = 8127; // 6 -const static uint64_t SH_FLD_INT_NEXT_STATE_LEN = 8128; // 6 -const static uint64_t SH_FLD_INT_RETURN_STATE = 8129; // 6 -const static uint64_t SH_FLD_INT_RETURN_STATE_LEN = 8130; // 6 -const static uint64_t SH_FLD_INT_RX_FSM = 8131; // 43 -const static uint64_t SH_FLD_INT_STATE_ERR = 8132; // 1 -const static uint64_t SH_FLD_INT_TX_FSM = 8133; // 43 -const static uint64_t SH_FLD_INT_TYPE = 8134; // 43 -const static uint64_t SH_FLD_INVALIDATE_ADDRESS = 8135; // 1 -const static uint64_t SH_FLD_INVALIDATE_ADDRESS_LEN = 8136; // 1 -const static uint64_t SH_FLD_INVALIDATE_ALL = 8137; // 1 -const static uint64_t SH_FLD_INVALIDATE_ONE = 8138; // 1 -const static uint64_t SH_FLD_INVALIDATE_PE_NUMBER = 8139; // 1 -const static uint64_t SH_FLD_INVALIDATE_PE_NUMBER_LEN = 8140; // 1 -const static uint64_t SH_FLD_INVALIDCRESP = 8141; // 9 -const static uint64_t SH_FLD_INVALIDCRESP_MASK = 8142; // 9 -const static uint64_t SH_FLD_INVALID_ADDRESS = 8143; // 12 -const static uint64_t SH_FLD_INVALID_ADDRESS_ALIGNMENT = 8144; // 4 -const static uint64_t SH_FLD_INVALID_ADDRESS_MASK = 8145; // 8 -const static uint64_t SH_FLD_INVALID_CMD_0 = 8146; // 2 -const static uint64_t SH_FLD_INVALID_CMD_1 = 8147; // 2 -const static uint64_t SH_FLD_INVALID_CMD_2 = 8148; // 2 -const static uint64_t SH_FLD_INVALID_CMD_3 = 8149; // 2 -const static uint64_t SH_FLD_INVALID_COMMAND = 8150; // 4 -const static uint64_t SH_FLD_INVALID_CRESP = 8151; // 4 -const static uint64_t SH_FLD_INVALID_CRESP_ERR = 8152; // 1 -const static uint64_t SH_FLD_INVALID_CRESP_ERROR = 8153; // 2 -const static uint64_t SH_FLD_INVALID_MAINT_ADDRESS = 8154; // 10 -const static uint64_t SH_FLD_INVALID_REQTYPE = 8155; // 16 -const static uint64_t SH_FLD_INVALID_REQTYPE_ERR_MASK = 8156; // 8 -const static uint64_t SH_FLD_INVALID_REQTYPE_LEN = 8157; // 8 -const static uint64_t SH_FLD_INVALID_REQ_SOURCE = 8158; // 8 -const static uint64_t SH_FLD_INVALID_REQ_SOURCE_LEN = 8159; // 8 -const static uint64_t SH_FLD_INVALID_STATE_RECOV = 8160; // 1 -const static uint64_t SH_FLD_INVALID_STATE_UNRECOV = 8161; // 1 -const static uint64_t SH_FLD_INVALID_TRANSFER_SIZE = 8162; // 4 -const static uint64_t SH_FLD_INVALID_TTYPE = 8163; // 4 -const static uint64_t SH_FLD_INVAL_IODA_TBL_SEL_ESR = 8164; // 1 -const static uint64_t SH_FLD_INVLD_CMD_ERR = 8165; // 1 -const static uint64_t SH_FLD_INVLD_PRGM_ERR = 8166; // 1 -const static uint64_t SH_FLD_INV_PROT_ERR_CHK_DIS = 8167; // 1 -const static uint64_t SH_FLD_INV_SINGLE_THREAD_EN = 8168; // 1 -const static uint64_t SH_FLD_INV_TIMEOUT_CHK_DIS = 8169; // 1 -const static uint64_t SH_FLD_IN_BAD_OP_ERR = 8170; // 2 -const static uint64_t SH_FLD_IN_CERR_BITS = 8171; // 1 -const static uint64_t SH_FLD_IN_CERR_BITS_LEN = 8172; // 1 -const static uint64_t SH_FLD_IN_CERR_RESET = 8173; // 1 -const static uint64_t SH_FLD_IN_COUNT1 = 8174; // 1 -const static uint64_t SH_FLD_IN_COUNT1_LEN = 8175; // 1 -const static uint64_t SH_FLD_IN_COUNT2 = 8176; // 1 -const static uint64_t SH_FLD_IN_COUNT2_LEN = 8177; // 1 -const static uint64_t SH_FLD_IN_DELAY1 = 8178; // 1 -const static uint64_t SH_FLD_IN_DELAY1_LEN = 8179; // 1 -const static uint64_t SH_FLD_IN_DELAY2 = 8180; // 1 -const static uint64_t SH_FLD_IN_DELAY2_LEN = 8181; // 1 -const static uint64_t SH_FLD_IN_ECC_CE_ERROR = 8182; // 2 -const static uint64_t SH_FLD_IN_ECC_SUE_ERROR = 8183; // 2 -const static uint64_t SH_FLD_IN_ECC_UE_ERROR = 8184; // 2 -const static uint64_t SH_FLD_IN_LEN = 8185; // 131 -const static uint64_t SH_FLD_IN_LOGIC_HW_ERROR = 8186; // 2 -const static uint64_t SH_FLD_IN_MASTER_MODE = 8187; // 43 -const static uint64_t SH_FLD_IN_PARITY_ERROR = 8188; // 2 -const static uint64_t SH_FLD_IN_PROG = 8189; // 1 -const static uint64_t SH_FLD_IN_PROG_LEN = 8190; // 1 -const static uint64_t SH_FLD_IN_SEQ_ERR = 8191; // 2 -const static uint64_t SH_FLD_IN_SEQ_PERR = 8192; // 2 -const static uint64_t SH_FLD_IN_SLAVE_MODE = 8193; // 43 -const static uint64_t SH_FLD_IN_SNP_ADDR_PERR = 8194; // 2 -const static uint64_t SH_FLD_IN_SNP_TTAG_PERR = 8195; // 2 -const static uint64_t SH_FLD_IN_SW_CAST_ERROR = 8196; // 2 -const static uint64_t SH_FLD_IN_TIMEOUT = 8197; // 2 -const static uint64_t SH_FLD_IN_TRACE_GROUP_SEL_HI = 8198; // 1 -const static uint64_t SH_FLD_IN_TRACE_GROUP_SEL_HI_LEN = 8199; // 1 -const static uint64_t SH_FLD_IN_TRACE_GROUP_SEL_LO = 8200; // 1 -const static uint64_t SH_FLD_IN_TRACE_GROUP_SEL_LO_LEN = 8201; // 1 -const static uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_01 = 8202; // 1 -const static uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_01_LEN = 8203; // 1 -const static uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_23 = 8204; // 1 -const static uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_23_LEN = 8205; // 1 -const static uint64_t SH_FLD_IODA_ADDR_PERR_ESR = 8206; // 1 -const static uint64_t SH_FLD_IOE01_IS_LOGICAL_PAIR = 8207; // 1 -const static uint64_t SH_FLD_IOE23_IS_LOGICAL_PAIR = 8208; // 1 -const static uint64_t SH_FLD_IOE45_IS_LOGICAL_PAIR = 8209; // 1 -const static uint64_t SH_FLD_IOO01_IS_LOGICAL_PAIR = 8210; // 1 -const static uint64_t SH_FLD_IOO23_IS_LOGICAL_PAIR = 8211; // 1 -const static uint64_t SH_FLD_IOO45_IS_LOGICAL_PAIR = 8212; // 1 -const static uint64_t SH_FLD_IOO67_IS_LOGICAL_PAIR = 8213; // 1 -const static uint64_t SH_FLD_IORESET = 8214; // 96 -const static uint64_t SH_FLD_IORESET_HARD_BUS0 = 8215; // 4 -const static uint64_t SH_FLD_IORESET_HARD_BUS0_LEN = 8216; // 4 -const static uint64_t SH_FLD_IOVALID = 8217; // 1 -const static uint64_t SH_FLD_IOVALID_10D = 8218; // 35 -const static uint64_t SH_FLD_IOVALID_11D = 8219; // 35 -const static uint64_t SH_FLD_IOVALID_4D = 8220; // 31 -const static uint64_t SH_FLD_IOVALID_5D = 8221; // 32 -const static uint64_t SH_FLD_IOVALID_6D = 8222; // 35 -const static uint64_t SH_FLD_IOVALID_7D = 8223; // 35 -const static uint64_t SH_FLD_IOVALID_8D = 8224; // 35 -const static uint64_t SH_FLD_IOVALID_9D = 8225; // 35 -const static uint64_t SH_FLD_IP = 8226; // 4 -const static uint64_t SH_FLD_IPI = 8227; // 1 -const static uint64_t SH_FLD_IPI0_HI_PRIORITY = 8228; // 1 -const static uint64_t SH_FLD_IPI0_LO_PRIORITY = 8229; // 1 -const static uint64_t SH_FLD_IPI1_HI_PRIORITY = 8230; // 1 -const static uint64_t SH_FLD_IPI1_LO_PRIORITY = 8231; // 1 -const static uint64_t SH_FLD_IPI2_HI_PRIORITY = 8232; // 1 -const static uint64_t SH_FLD_IPI2_LO_PRIORITY = 8233; // 1 -const static uint64_t SH_FLD_IPI3_HI_PRIORITY = 8234; // 1 -const static uint64_t SH_FLD_IPI3_LO_PRIORITY = 8235; // 1 -const static uint64_t SH_FLD_IPI4_HI_PRIORITY = 8236; // 1 -const static uint64_t SH_FLD_IPI4_LO_PRIORITY = 8237; // 1 -const static uint64_t SH_FLD_IPI_LEN = 8238; // 1 -const static uint64_t SH_FLD_IPI_PRIORITY = 8239; // 1 -const static uint64_t SH_FLD_IPI_PRIORITY_LEN = 8240; // 1 -const static uint64_t SH_FLD_IPI_RSD = 8241; // 1 -const static uint64_t SH_FLD_IPI_RSD_LEN = 8242; // 1 -const static uint64_t SH_FLD_IPOLL_0 = 8243; // 1 -const static uint64_t SH_FLD_IPOLL_1 = 8244; // 1 -const static uint64_t SH_FLD_IPOLL_2 = 8245; // 1 -const static uint64_t SH_FLD_IPOLL_3 = 8246; // 1 -const static uint64_t SH_FLD_IPOLL_4 = 8247; // 1 -const static uint64_t SH_FLD_IPOLL_5 = 8248; // 1 -const static uint64_t SH_FLD_IPW_SIDEAB_SEL = 8249; // 8 -const static uint64_t SH_FLD_IPW_WR_WR = 8250; // 8 -const static uint64_t SH_FLD_IPW_WR_WR_LEN = 8251; // 8 -const static uint64_t SH_FLD_IQHISPD_EN = 8252; // 4 -const static uint64_t SH_FLD_IR = 8253; // 21 -const static uint64_t SH_FLD_IREF_BYPASS = 8254; // 2 -const static uint64_t SH_FLD_IREF_PDWN_B = 8255; // 2 -const static uint64_t SH_FLD_IREF_RES_DAC = 8256; // 2 -const static uint64_t SH_FLD_IREF_RES_DAC_LEN = 8257; // 2 -const static uint64_t SH_FLD_IRQ = 8258; // 1 -const static uint64_t SH_FLD_IRQ_LEN = 8259; // 1 -const static uint64_t SH_FLD_IRQ_TRACE_ENABLE = 8260; // 1 -const static uint64_t SH_FLD_IR_DR_EQ0_ERR = 8261; // 1 -const static uint64_t SH_FLD_IR_LEN = 8262; // 21 -const static uint64_t SH_FLD_IS = 8263; // 8 -const static uint64_t SH_FLD_IS_ACTIVE_MASTER = 8264; // 1 -const static uint64_t SH_FLD_IS_BACKUP_MASTER = 8265; // 1 -const static uint64_t SH_FLD_IS_LEN = 8266; // 8 -const static uint64_t SH_FLD_IS_PRIMARY = 8267; // 1 -const static uint64_t SH_FLD_IS_RUNNING = 8268; // 2 -const static uint64_t SH_FLD_IS_SECONDARY = 8269; // 1 -const static uint64_t SH_FLD_IS_SLAVE = 8270; // 1 -const static uint64_t SH_FLD_IS_SPECIAL = 8271; // 1 -const static uint64_t SH_FLD_ITUNE = 8272; // 4 -const static uint64_t SH_FLD_ITUNE_LEN = 8273; // 4 -const static uint64_t SH_FLD_IVC = 8274; // 1 -const static uint64_t SH_FLD_IVC_INTF_DISABLE = 8275; // 6 -const static uint64_t SH_FLD_IVC_LEN = 8276; // 1 -const static uint64_t SH_FLD_IVPR = 8277; // 5 -const static uint64_t SH_FLD_IVPR_LEN = 8278; // 5 -const static uint64_t SH_FLD_IVRM_BYPASS_B = 8279; // 30 -const static uint64_t SH_FLD_IVRM_IVID = 8280; // 30 -const static uint64_t SH_FLD_IVRM_IVID_LEN = 8281; // 30 -const static uint64_t SH_FLD_IVRM_LOCAL_CONTROL = 8282; // 24 -const static uint64_t SH_FLD_IVRM_PFET_STRENGTH_CACHE = 8283; // 30 -const static uint64_t SH_FLD_IVRM_PFET_STRENGTH_CACHE_LEN = 8284; // 30 -const static uint64_t SH_FLD_IVRM_PFET_STRENGTH_CORE = 8285; // 30 -const static uint64_t SH_FLD_IVRM_PFET_STRENGTH_CORE_LEN = 8286; // 30 -const static uint64_t SH_FLD_IVRM_POWERON = 8287; // 30 -const static uint64_t SH_FLD_IVRM_PVREF_ERROR = 8288; // 1 -const static uint64_t SH_FLD_IVRM_UREG_TEST_EN = 8289; // 24 -const static uint64_t SH_FLD_IVRM_UREG_TEST_ID = 8290; // 24 -const static uint64_t SH_FLD_IVRM_UREG_TEST_ID_LEN = 8291; // 24 -const static uint64_t SH_FLD_IVRM_VID_DONE = 8292; // 30 -const static uint64_t SH_FLD_IVRM_VID_VALID = 8293; // 30 -const static uint64_t SH_FLD_IVRM_VREG_SLOW_DC = 8294; // 30 -const static uint64_t SH_FLD_I_DELAY_ADJUST_RATIO = 8295; // 1 -const static uint64_t SH_FLD_I_DELAY_ADJUST_RATIO_LEN = 8296; // 1 -const static uint64_t SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT = 8297; // 1 -const static uint64_t SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT_LEN = 8298; // 1 -const static uint64_t SH_FLD_I_PATH_DELAY_ADJUST = 8299; // 1 -const static uint64_t SH_FLD_I_PATH_DELAY_STEP_CHECK_PARITY = 8300; // 4 -const static uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD = 8301; // 1 -const static uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE = 8302; // 1 -const static uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE_LEN = 8303; // 1 -const static uint64_t SH_FLD_I_PATH_DELAY_VALUE = 8304; // 2 -const static uint64_t SH_FLD_I_PATH_DELAY_VALUE_LEN = 8305; // 2 -const static uint64_t SH_FLD_I_PATH_FSM_STATE_PARITY = 8306; // 4 -const static uint64_t SH_FLD_I_PATH_STATE = 8307; // 1 -const static uint64_t SH_FLD_I_PATH_STATE_LEN = 8308; // 1 -const static uint64_t SH_FLD_I_PATH_STEP_CHECK = 8309; // 4 -const static uint64_t SH_FLD_I_PATH_STEP_CHECK_CPS_DEVIATION_X_DISABLE = 8310; // 1 -const static uint64_t SH_FLD_I_PATH_STEP_CHECK_VALID = 8311; // 1 -const static uint64_t SH_FLD_I_PATH_SYNC_CHECK = 8312; // 4 -const static uint64_t SH_FLD_I_PATH_SYNC_CHECK_DISABLE = 8313; // 1 -const static uint64_t SH_FLD_I_PATH_TIME_OVERFLOW = 8314; // 3 -const static uint64_t SH_FLD_I_PATH_TIME_OVERFLOW_CORE_INTERRUPT = 8315; // 1 -const static uint64_t SH_FLD_I_PATH_TIME_PARITY = 8316; // 4 -const static uint64_t SH_FLD_JITTER_EPSILON = 8317; // 8 -const static uint64_t SH_FLD_JITTER_EPSILON_LEN = 8318; // 8 -const static uint64_t SH_FLD_JTAG_INPROG = 8319; // 1 -const static uint64_t SH_FLD_JTAG_INSTR = 8320; // 1 -const static uint64_t SH_FLD_JTAG_INSTR_LEN = 8321; // 1 -const static uint64_t SH_FLD_JTAG_SRC_SEL = 8322; // 1 -const static uint64_t SH_FLD_JTAG_TDI = 8323; // 1 -const static uint64_t SH_FLD_JTAG_TDI_LEN = 8324; // 1 -const static uint64_t SH_FLD_JTAG_TDO = 8325; // 1 -const static uint64_t SH_FLD_JTAG_TDO_LEN = 8326; // 1 -const static uint64_t SH_FLD_JTAG_TRST_B = 8327; // 1 -const static uint64_t SH_FLD_KEEP_EDRAM_ENABLED_ON = 8328; // 129 -const static uint64_t SH_FLD_KEEP_MS_MODE = 8329; // 43 -const static uint64_t SH_FLD_L = 8330; // 8 -const static uint64_t SH_FLD_L2 = 8331; // 12 -const static uint64_t SH_FLD_L2_CORE_INTF_QUIESCE_C0 = 8332; // 12 -const static uint64_t SH_FLD_L2_CORE_INTF_QUIESCE_C1 = 8333; // 12 -const static uint64_t SH_FLD_L2_EX0_CLKGLM_ASYNC_RESET = 8334; // 6 -const static uint64_t SH_FLD_L2_EX0_CLKGLM_SEL = 8335; // 6 -const static uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE = 8336; // 6 -const static uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_EN = 8337; // 6 -const static uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_LEN = 8338; // 6 -const static uint64_t SH_FLD_L2_EX0_CLK_SB_SPARE0 = 8339; // 6 -const static uint64_t SH_FLD_L2_EX0_CLK_SB_STRENGTH = 8340; // 6 -const static uint64_t SH_FLD_L2_EX0_CLK_SB_STRENGTH_LEN = 8341; // 6 -const static uint64_t SH_FLD_L2_EX0_CLK_SW_RESCLK = 8342; // 6 -const static uint64_t SH_FLD_L2_EX0_CLK_SW_RESCLK_LEN = 8343; // 6 -const static uint64_t SH_FLD_L2_EX0_CLK_SW_SPARE1 = 8344; // 6 -const static uint64_t SH_FLD_L2_EX0_CLK_SYNC = 8345; // 6 -const static uint64_t SH_FLD_L2_EX0_CLK_SYNC_DONE = 8346; // 6 -const static uint64_t SH_FLD_L2_EX0_CLK_SYNC_ENABLE = 8347; // 6 -const static uint64_t SH_FLD_L2_EX1_CLKGLM_ASYNC_RESET = 8348; // 6 -const static uint64_t SH_FLD_L2_EX1_CLKGLM_SEL = 8349; // 6 -const static uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE = 8350; // 6 -const static uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_EN = 8351; // 6 -const static uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_LEN = 8352; // 6 -const static uint64_t SH_FLD_L2_EX1_CLK_SB_SPARE0 = 8353; // 6 -const static uint64_t SH_FLD_L2_EX1_CLK_SB_STRENGTH = 8354; // 6 -const static uint64_t SH_FLD_L2_EX1_CLK_SB_STRENGTH_LEN = 8355; // 6 -const static uint64_t SH_FLD_L2_EX1_CLK_SW_RESCLK = 8356; // 6 -const static uint64_t SH_FLD_L2_EX1_CLK_SW_RESCLK_LEN = 8357; // 6 -const static uint64_t SH_FLD_L2_EX1_CLK_SW_SPARE1 = 8358; // 6 -const static uint64_t SH_FLD_L2_EX1_CLK_SYNC = 8359; // 6 -const static uint64_t SH_FLD_L2_EX1_CLK_SYNC_DONE = 8360; // 6 -const static uint64_t SH_FLD_L2_EX1_CLK_SYNC_ENABLE = 8361; // 6 -const static uint64_t SH_FLD_L2_LEN = 8362; // 12 -const static uint64_t SH_FLD_L2_PURGE = 8363; // 12 -const static uint64_t SH_FLD_L2_PURGE_ABORT = 8364; // 12 -const static uint64_t SH_FLD_L2_PURGE_DONE = 8365; // 24 -const static uint64_t SH_FLD_L2_STEP_MODE = 8366; // 12 -const static uint64_t SH_FLD_L2_STEP_MODE_LEN = 8367; // 12 -const static uint64_t SH_FLD_L2_STOPPED = 8368; // 1 -const static uint64_t SH_FLD_L2_STOPPED_LEN = 8369; // 1 -const static uint64_t SH_FLD_L3 = 8370; // 36 -const static uint64_t SH_FLD_L3CERRS_CFG_DCACHE_CAPP = 8371; // 12 -const static uint64_t SH_FLD_L3CERRS_LCO_RETRY_THROTL_DIS = 8372; // 12 -const static uint64_t SH_FLD_L3CICTL_CI_OVERRUN_CK_ERR = 8373; // 12 -const static uint64_t SH_FLD_L3CORTR_NO_LCO_TGTS_ERR = 8374; // 12 -const static uint64_t SH_FLD_L3L2CTL_PF_OVERRUN_CK_ERR = 8375; // 12 -const static uint64_t SH_FLD_L3L2CTL_RD_OVERRUN_CK_ERR = 8376; // 12 -const static uint64_t SH_FLD_L3PBEXCA0_OVERFLOW_ERR = 8377; // 12 -const static uint64_t SH_FLD_L3PBEXCA0_UNDERFLOW_ERR = 8378; // 12 -const static uint64_t SH_FLD_L3PBEXCA1_OVERFLOW_ERR = 8379; // 12 -const static uint64_t SH_FLD_L3PBEXCA1_UNDERFLOW_ERR = 8380; // 12 -const static uint64_t SH_FLD_L3SDRTL0_CACHE_INHIBIT_ERR = 8381; // 12 -const static uint64_t SH_FLD_L3SDRTL0_CHECKSTOP_ERR = 8382; // 12 -const static uint64_t SH_FLD_L3SDRTL1_CACHE_INHIBIT_ERR = 8383; // 12 -const static uint64_t SH_FLD_L3SDRTL1_CHECKSTOP_ERR = 8384; // 12 -const static uint64_t SH_FLD_L3XMEMA0_CRW_DIR_HIT_ERR = 8385; // 12 -const static uint64_t SH_FLD_L3XMEMA0_DW_DIR_HIT_ERR = 8386; // 12 -const static uint64_t SH_FLD_L3XMEMA1_CRW_DIR_HIT_ERR = 8387; // 12 -const static uint64_t SH_FLD_L3XMEMA1_DW_DIR_HIT_ERR = 8388; // 12 -const static uint64_t SH_FLD_L3_1ST_BEAT_SYNDROME = 8389; // 12 -const static uint64_t SH_FLD_L3_1ST_BEAT_SYNDROME_LEN = 8390; // 12 -const static uint64_t SH_FLD_L3_1ST_BEAT_UE = 8391; // 12 -const static uint64_t SH_FLD_L3_2ND_BEAT_SYNDROME = 8392; // 12 -const static uint64_t SH_FLD_L3_2ND_BEAT_SYNDROME_LEN = 8393; // 12 -const static uint64_t SH_FLD_L3_2ND_BEAT_UE = 8394; // 12 -const static uint64_t SH_FLD_L3_ABORT = 8395; // 12 -const static uint64_t SH_FLD_L3_ADDR_HANG_DETECTED = 8396; // 12 -const static uint64_t SH_FLD_L3_ADDR_HASH_EN_CFG = 8397; // 12 -const static uint64_t SH_FLD_L3_ALL_MEMBERS_DELETED_ERROR = 8398; // 12 -const static uint64_t SH_FLD_L3_BANK = 8399; // 12 -const static uint64_t SH_FLD_L3_BANK_LEN = 8400; // 12 -const static uint64_t SH_FLD_L3_BUSY_ERR = 8401; // 36 -const static uint64_t SH_FLD_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ = 8402; // 12 -const static uint64_t SH_FLD_L3_CAC_RD_SUE_DET = 8403; // 12 -const static uint64_t SH_FLD_L3_CAC_RD_UE_DET = 8404; // 12 -const static uint64_t SH_FLD_L3_CAC_TYPE = 8405; // 12 -const static uint64_t SH_FLD_L3_CAC_TYPE_LEN = 8406; // 12 -const static uint64_t SH_FLD_L3_CAC_WR_DATA_CE_FROM_L2 = 8407; // 12 -const static uint64_t SH_FLD_L3_CAC_WR_DATA_CE_FROM_PB = 8408; // 12 -const static uint64_t SH_FLD_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC = 8409; // 12 -const static uint64_t SH_FLD_L3_CAC_WR_DATA_SUE_FROM_PB = 8410; // 12 -const static uint64_t SH_FLD_L3_CAC_WR_DATA_UE_FROM_L2 = 8411; // 12 -const static uint64_t SH_FLD_L3_CAC_WR_DATA_UE_FROM_PB = 8412; // 12 -const static uint64_t SH_FLD_L3_CFG = 8413; // 24 -const static uint64_t SH_FLD_L3_CFG_LEN = 8414; // 12 -const static uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE = 8415; // 6 -const static uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE_EN = 8416; // 6 -const static uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE_LEN = 8417; // 6 -const static uint64_t SH_FLD_L3_CLK_SB_SPARE0 = 8418; // 6 -const static uint64_t SH_FLD_L3_CLK_SB_STRENGTH = 8419; // 6 -const static uint64_t SH_FLD_L3_CLK_SB_STRENGTH_LEN = 8420; // 6 -const static uint64_t SH_FLD_L3_COLUMN_MD_CFG = 8421; // 12 -const static uint64_t SH_FLD_L3_COLUMN_MD_CFG_LEN = 8422; // 12 -const static uint64_t SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG = 8423; // 12 -const static uint64_t SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG_LEN = 8424; // 12 -const static uint64_t SH_FLD_L3_CO_SN_CRESP_ACK_DEAD_CACR4 = 8425; // 12 -const static uint64_t SH_FLD_L3_CO_SN_CRESP_ADDR_ERR = 8426; // 12 -const static uint64_t SH_FLD_L3_CP_UTIL_EN_DC = 8427; // 12 -const static uint64_t SH_FLD_L3_CP_UTIL_EXT_SEL = 8428; // 12 -const static uint64_t SH_FLD_L3_CP_UTIL_EXT_SEL_LEN = 8429; // 12 -const static uint64_t SH_FLD_L3_CP_UTIL_SEL_DC = 8430; // 12 -const static uint64_t SH_FLD_L3_CP_UTIL_SEL_DC_LEN = 8431; // 12 -const static uint64_t SH_FLD_L3_DATA_POLL_PULSE_DIV = 8432; // 12 -const static uint64_t SH_FLD_L3_DATA_POLL_PULSE_DIV_LEN = 8433; // 12 -const static uint64_t SH_FLD_L3_DIR_ADDR = 8434; // 24 -const static uint64_t SH_FLD_L3_DIR_ADDR_LEN = 8435; // 24 -const static uint64_t SH_FLD_L3_DIR_RD_CE_DET = 8436; // 12 -const static uint64_t SH_FLD_L3_DIR_RD_PHANTOM_ERROR = 8437; // 12 -const static uint64_t SH_FLD_L3_DIR_RD_UE_DET = 8438; // 12 -const static uint64_t SH_FLD_L3_DIR_TYPE = 8439; // 12 -const static uint64_t SH_FLD_L3_DISABLED_CFG = 8440; // 12 -const static uint64_t SH_FLD_L3_DMAP_CI_EN_CFG = 8441; // 12 -const static uint64_t SH_FLD_L3_DRAM_ERROR = 8442; // 12 -const static uint64_t SH_FLD_L3_DRAM_POS_WORDLINE_FAIL = 8443; // 12 -const static uint64_t SH_FLD_L3_DW = 8444; // 12 -const static uint64_t SH_FLD_L3_DW_LEN = 8445; // 12 -const static uint64_t SH_FLD_L3_DYN_LCO_BLK_DIS_CFG = 8446; // 12 -const static uint64_t SH_FLD_L3_EDRAM_ENABLE = 8447; // 43 -const static uint64_t SH_FLD_L3_EX0_ENABLE = 8448; // 6 -const static uint64_t SH_FLD_L3_EX0_VPP_ENABLE = 8449; // 6 -const static uint64_t SH_FLD_L3_EX0_VROW_VBLH_ENABLE = 8450; // 6 -const static uint64_t SH_FLD_L3_EX0_VWL_ENABLE = 8451; // 6 -const static uint64_t SH_FLD_L3_EX1_ENABLE = 8452; // 6 -const static uint64_t SH_FLD_L3_EX1_VPP_ENABLE = 8453; // 6 -const static uint64_t SH_FLD_L3_EX1_VROW_VBLH_ENABLE = 8454; // 6 -const static uint64_t SH_FLD_L3_EX1_VWL_ENABLE = 8455; // 6 -const static uint64_t SH_FLD_L3_HANG_POLL_PULSE_DIV = 8456; // 12 -const static uint64_t SH_FLD_L3_HANG_POLL_PULSE_DIV_LEN = 8457; // 12 -const static uint64_t SH_FLD_L3_HW_CONTROL_ERR = 8458; // 12 -const static uint64_t SH_FLD_L3_IS_ECO_CFG = 8459; // 12 -const static uint64_t SH_FLD_L3_LCO_ADDR_TGT_ENABLE = 8460; // 12 -const static uint64_t SH_FLD_L3_LCO_ENABLE_CFG = 8461; // 12 -const static uint64_t SH_FLD_L3_LCO_RTY_LIMIT_DISABLE = 8462; // 12 -const static uint64_t SH_FLD_L3_LCO_TARGET_GROUP = 8463; // 12 -const static uint64_t SH_FLD_L3_LCO_TARGET_ID = 8464; // 12 -const static uint64_t SH_FLD_L3_LCO_TARGET_ID_LEN = 8465; // 12 -const static uint64_t SH_FLD_L3_LCO_TARGET_VICTIMS = 8466; // 12 -const static uint64_t SH_FLD_L3_LCO_TARGET_VICTIMS_LEN = 8467; // 12 -const static uint64_t SH_FLD_L3_LEN = 8468; // 36 -const static uint64_t SH_FLD_L3_LINE_DEL_CE_DONE = 8469; // 12 -const static uint64_t SH_FLD_L3_LINE_DEL_ON_ALL_CE = 8470; // 24 -const static uint64_t SH_FLD_L3_LINE_DEL_ON_NEXT_CE = 8471; // 24 -const static uint64_t SH_FLD_L3_LRU_ERROR = 8472; // 12 -const static uint64_t SH_FLD_L3_LRU_INVAL_CNT = 8473; // 12 -const static uint64_t SH_FLD_L3_MACH_HANG_DETECTED = 8474; // 12 -const static uint64_t SH_FLD_L3_MEMBER = 8475; // 24 -const static uint64_t SH_FLD_L3_MEMBER_LEN = 8476; // 24 -const static uint64_t SH_FLD_L3_NO_ALLOCATE_ACTIVE = 8477; // 12 -const static uint64_t SH_FLD_L3_NO_ALLOCATE_EN = 8478; // 12 -const static uint64_t SH_FLD_L3_PF_CRESP_ACK_DEAD_CACR4 = 8479; // 12 -const static uint64_t SH_FLD_L3_PF_CRESP_ADDR_ERR = 8480; // 12 -const static uint64_t SH_FLD_L3_PPE_RD_CE_DET = 8481; // 12 -const static uint64_t SH_FLD_L3_PPE_RD_SUE_DET = 8482; // 12 -const static uint64_t SH_FLD_L3_PPE_RD_UE_DET = 8483; // 12 -const static uint64_t SH_FLD_L3_RA = 8484; // 12 -const static uint64_t SH_FLD_L3_RA_LEN = 8485; // 12 -const static uint64_t SH_FLD_L3_RDSN_LINEDEL_UE_EN = 8486; // 12 -const static uint64_t SH_FLD_L3_REFRESH_TIMER_ERROR = 8487; // 12 -const static uint64_t SH_FLD_L3_REQ = 8488; // 36 -const static uint64_t SH_FLD_L3_SCOM_FENCE_LVL = 8489; // 12 -const static uint64_t SH_FLD_L3_SCOM_INIT = 8490; // 12 -const static uint64_t SH_FLD_L3_SCOM_QUIESCE_CACHE = 8491; // 12 -const static uint64_t SH_FLD_L3_SCOM_QUIESCE_CACHE_LFSR = 8492; // 12 -const static uint64_t SH_FLD_L3_SCOM_QUIESCE_REFRESH = 8493; // 12 -const static uint64_t SH_FLD_L3_SINGLE_CAC = 8494; // 12 -const static uint64_t SH_FLD_L3_SINGLE_DIR = 8495; // 12 -const static uint64_t SH_FLD_L3_SINGLE_LRU = 8496; // 12 -const static uint64_t SH_FLD_L3_SNOOP_SW_ERR_DETECTED = 8497; // 12 -const static uint64_t SH_FLD_L3_SOLID_CAC = 8498; // 12 -const static uint64_t SH_FLD_L3_SOLID_DIR = 8499; // 12 -const static uint64_t SH_FLD_L3_SOLID_LRU = 8500; // 12 -const static uint64_t SH_FLD_L3_SPARE3 = 8501; // 12 -const static uint64_t SH_FLD_L3_SPARE5 = 8502; // 12 -const static uint64_t SH_FLD_L3_SPARE7 = 8503; // 12 -const static uint64_t SH_FLD_L3_STOPPED = 8504; // 1 -const static uint64_t SH_FLD_L3_STOPPED_LEN = 8505; // 1 -const static uint64_t SH_FLD_L3_SYSMAP_SM_NOT_LG_SEL = 8506; // 12 -const static uint64_t SH_FLD_L3_TIMER_DIVIDE_MAJOR = 8507; // 12 -const static uint64_t SH_FLD_L3_TIMER_DIVIDE_MAJOR_LEN = 8508; // 12 -const static uint64_t SH_FLD_L3_TIMER_DIVIDE_MINOR = 8509; // 12 -const static uint64_t SH_FLD_L3_TIMER_DIVIDE_MINOR_LEN = 8510; // 12 -const static uint64_t SH_FLD_L3_TTYPE = 8511; // 24 -const static uint64_t SH_FLD_L3_TTYPE_LEN = 8512; // 24 -const static uint64_t SH_FLD_L3_UTIL_MON_BITS = 8513; // 12 -const static uint64_t SH_FLD_L3_UTIL_MON_BITS_LEN = 8514; // 12 -const static uint64_t SH_FLD_L3_VAL = 8515; // 12 -const static uint64_t SH_FLD_LANE0_DISABLED = 8516; // 4 -const static uint64_t SH_FLD_LANE_ANA_PDWN = 8517; // 120 -const static uint64_t SH_FLD_LANE_BAD_VEC_0_15 = 8518; // 4 -const static uint64_t SH_FLD_LANE_BAD_VEC_0_15_LEN = 8519; // 4 -const static uint64_t SH_FLD_LANE_BAD_VEC_16_23 = 8520; // 4 -const static uint64_t SH_FLD_LANE_BAD_VEC_16_23_LEN = 8521; // 4 -const static uint64_t SH_FLD_LANE_BIST_ACTVITY_DET = 8522; // 116 -const static uint64_t SH_FLD_LANE_BIST_ERR = 8523; // 116 -const static uint64_t SH_FLD_LANE_DIG_PDWN = 8524; // 120 -const static uint64_t SH_FLD_LANE_DISABLED = 8525; // 48 -const static uint64_t SH_FLD_LANE_DISABLED_VEC_0_15 = 8526; // 4 -const static uint64_t SH_FLD_LANE_DISABLED_VEC_0_15_LEN = 8527; // 4 -const static uint64_t SH_FLD_LANE_DISABLED_VEC_16_23 = 8528; // 4 -const static uint64_t SH_FLD_LANE_DISABLED_VEC_16_23_LEN = 8529; // 4 -const static uint64_t SH_FLD_LANE_INVALID = 8530; // 72 -const static uint64_t SH_FLD_LANE_INVERT = 8531; // 190 -const static uint64_t SH_FLD_LANE_PDWN = 8532; // 116 -const static uint64_t SH_FLD_LANE_QUIESCE = 8533; // 117 -const static uint64_t SH_FLD_LANE_QUIESCE_LEN = 8534; // 117 -const static uint64_t SH_FLD_LANE_SCRAMBLE_DISABLE = 8535; // 140 -const static uint64_t SH_FLD_LAST_OPCG_MODE = 8536; // 43 -const static uint64_t SH_FLD_LAST_OPCG_MODE_LEN = 8537; // 43 -const static uint64_t SH_FLD_LATE_LAUNCH_PRIMARY = 8538; // 1 -const static uint64_t SH_FLD_LATE_LAUNCH_SECONDARY = 8539; // 1 -const static uint64_t SH_FLD_LAT_THRESHA = 8540; // 8 -const static uint64_t SH_FLD_LAT_THRESHA_LEN = 8541; // 8 -const static uint64_t SH_FLD_LAT_THRESHB = 8542; // 8 -const static uint64_t SH_FLD_LAT_THRESHB_LEN = 8543; // 8 -const static uint64_t SH_FLD_LAT_THRESHC = 8544; // 8 -const static uint64_t SH_FLD_LAT_THRESHC_LEN = 8545; // 8 -const static uint64_t SH_FLD_LBIST = 8546; // 43 -const static uint64_t SH_FLD_LBIST_SKITTER_CTL = 8547; // 43 -const static uint64_t SH_FLD_LBS_IDX0_SEL = 8548; // 1 -const static uint64_t SH_FLD_LBUS_CLOCK_DIVIDER = 8549; // 2 -const static uint64_t SH_FLD_LBUS_CLOCK_DIVIDER_LEN = 8550; // 2 -const static uint64_t SH_FLD_LBUS_PARITY_ERR1_0 = 8551; // 12 -const static uint64_t SH_FLD_LBUS_PARITY_ERR1_1 = 8552; // 12 -const static uint64_t SH_FLD_LBUS_PARITY_ERR1_2 = 8553; // 12 -const static uint64_t SH_FLD_LBUS_PARITY_ERR1_3 = 8554; // 12 -const static uint64_t SH_FLD_LBUS_PARITY_ERROR_0 = 8555; // 2 -const static uint64_t SH_FLD_LBUS_PARITY_ERROR_1 = 8556; // 2 -const static uint64_t SH_FLD_LBUS_PARITY_ERROR_2 = 8557; // 2 -const static uint64_t SH_FLD_LBUS_PARITY_ERROR_3 = 8558; // 2 -const static uint64_t SH_FLD_LCK_STATUS_PARITY_ERROR = 8559; // 3 -const static uint64_t SH_FLD_LD = 8560; // 96 -const static uint64_t SH_FLD_LDQ_EQD_MAX_0_4 = 8561; // 1 -const static uint64_t SH_FLD_LDQ_EQD_MAX_0_4_LEN = 8562; // 1 -const static uint64_t SH_FLD_LDQ_EQD_MIN_0_4 = 8563; // 1 -const static uint64_t SH_FLD_LDQ_EQD_MIN_0_4_LEN = 8564; // 1 -const static uint64_t SH_FLD_LDQ_FSM_PERR = 8565; // 1 -const static uint64_t SH_FLD_LDQ_IVE_MAX_0_4 = 8566; // 1 -const static uint64_t SH_FLD_LDQ_IVE_MAX_0_4_LEN = 8567; // 1 -const static uint64_t SH_FLD_LDQ_IVE_MIN_0_4 = 8568; // 1 -const static uint64_t SH_FLD_LDQ_IVE_MIN_0_4_LEN = 8569; // 1 -const static uint64_t SH_FLD_LDQ_REG_MAX_0_4 = 8570; // 1 -const static uint64_t SH_FLD_LDQ_REG_MAX_0_4_LEN = 8571; // 1 -const static uint64_t SH_FLD_LDQ_REG_MIN_0_4 = 8572; // 1 -const static uint64_t SH_FLD_LDQ_REG_MIN_0_4_LEN = 8573; // 1 -const static uint64_t SH_FLD_LDQ_REG_ORDER_ALL = 8574; // 1 -const static uint64_t SH_FLD_LDQ_THR_MAX_0_4 = 8575; // 1 -const static uint64_t SH_FLD_LDQ_THR_MAX_0_4_LEN = 8576; // 1 -const static uint64_t SH_FLD_LDQ_THR_MIN_0_4 = 8577; // 1 -const static uint64_t SH_FLD_LDQ_THR_MIN_0_4_LEN = 8578; // 1 -const static uint64_t SH_FLD_LDQ_VPC_MAX_0_4 = 8579; // 1 -const static uint64_t SH_FLD_LDQ_VPC_MAX_0_4_LEN = 8580; // 1 -const static uint64_t SH_FLD_LDQ_VPC_MIN_0_4 = 8581; // 1 -const static uint64_t SH_FLD_LDQ_VPC_MIN_0_4_LEN = 8582; // 1 -const static uint64_t SH_FLD_LD_ACK_DEAD = 8583; // 12 -const static uint64_t SH_FLD_LD_ADDR_ERR = 8584; // 24 -const static uint64_t SH_FLD_LD_CLASS_CMD_ADDR_ERR = 8585; // 4 -const static uint64_t SH_FLD_LD_CLASS_CMD_FOREIGN_LINK_FAIL = 8586; // 4 -const static uint64_t SH_FLD_LD_FOREIGN0_ACK_DEAD = 8587; // 12 -const static uint64_t SH_FLD_LD_FOREIGN1_ACK_DEAD = 8588; // 12 -const static uint64_t SH_FLD_LD_UNLD_DLY = 8589; // 1 -const static uint64_t SH_FLD_LD_UNLD_DLY_LEN = 8590; // 1 -const static uint64_t SH_FLD_LENGTH_IN_BYTES_0 = 8591; // 1 -const static uint64_t SH_FLD_LENGTH_IN_BYTES_0_LEN = 8592; // 1 -const static uint64_t SH_FLD_LENGTH_IN_BYTES_1 = 8593; // 1 -const static uint64_t SH_FLD_LENGTH_IN_BYTES_1_LEN = 8594; // 1 -const static uint64_t SH_FLD_LENGTH_IN_BYTES_2 = 8595; // 1 -const static uint64_t SH_FLD_LENGTH_IN_BYTES_2_LEN = 8596; // 1 -const static uint64_t SH_FLD_LENGTH_IN_BYTES_3 = 8597; // 1 -const static uint64_t SH_FLD_LENGTH_IN_BYTES_3_LEN = 8598; // 1 -const static uint64_t SH_FLD_LEVEL_TRANSITION_RATE_A_N = 8599; // 96 -const static uint64_t SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN = 8600; // 96 -const static uint64_t SH_FLD_LFIR_IN = 8601; // 43 -const static uint64_t SH_FLD_LFIR_IN_LEN = 8602; // 43 -const static uint64_t SH_FLD_LFIR_RECOV_ERR = 8603; // 1 -const static uint64_t SH_FLD_LFREQ = 8604; // 1 -const static uint64_t SH_FLD_LFREQ0 = 8605; // 15 -const static uint64_t SH_FLD_LFREQ0_LEN = 8606; // 15 -const static uint64_t SH_FLD_LFREQ1 = 8607; // 15 -const static uint64_t SH_FLD_LFREQ1_LEN = 8608; // 15 -const static uint64_t SH_FLD_LFREQ_LEN = 8609; // 1 -const static uint64_t SH_FLD_LFSR_ARB_MODE = 8610; // 3 -const static uint64_t SH_FLD_LFSR_DIS = 8611; // 1 -const static uint64_t SH_FLD_LFSR_FAIRNESS_MASK = 8612; // 1 -const static uint64_t SH_FLD_LFSR_FAIRNESS_MASK_LEN = 8613; // 1 -const static uint64_t SH_FLD_LIMIT = 8614; // 2 -const static uint64_t SH_FLD_LIMIT_LEN = 8615; // 2 -const static uint64_t SH_FLD_LIM_PS = 8616; // 1 -const static uint64_t SH_FLD_LINEAR_WINDOW_BAR = 8617; // 4 -const static uint64_t SH_FLD_LINEAR_WINDOW_BAR_LEN = 8618; // 4 -const static uint64_t SH_FLD_LINEAR_WINDOW_BASE = 8619; // 4 -const static uint64_t SH_FLD_LINEAR_WINDOW_BASE_LEN = 8620; // 4 -const static uint64_t SH_FLD_LINEAR_WINDOW_ENABLE = 8621; // 4 -const static uint64_t SH_FLD_LINEAR_WINDOW_MASK = 8622; // 4 -const static uint64_t SH_FLD_LINEAR_WINDOW_MASK_LEN = 8623; // 4 -const static uint64_t SH_FLD_LINEAR_WINDOW_REGION = 8624; // 4 -const static uint64_t SH_FLD_LINEAR_WINDOW_REGION_LEN = 8625; // 4 -const static uint64_t SH_FLD_LINEAR_WINDOW_SCRESP = 8626; // 4 -const static uint64_t SH_FLD_LINEAR_WINDOW_SCRESP_LEN = 8627; // 4 -const static uint64_t SH_FLD_LINK00_HI = 8628; // 2 -const static uint64_t SH_FLD_LINK00_HI_LEN = 8629; // 2 -const static uint64_t SH_FLD_LINK00_LO = 8630; // 2 -const static uint64_t SH_FLD_LINK00_LO_LEN = 8631; // 2 -const static uint64_t SH_FLD_LINK01_CAPP_MODE = 8632; // 1 -const static uint64_t SH_FLD_LINK01_DIB_VC_LIMIT = 8633; // 2 -const static uint64_t SH_FLD_LINK01_DIB_VC_LIMIT_LEN = 8634; // 2 -const static uint64_t SH_FLD_LINK01_HI = 8635; // 2 -const static uint64_t SH_FLD_LINK01_HI_LEN = 8636; // 2 -const static uint64_t SH_FLD_LINK01_HRB_INIT_STATE = 8637; // 1 -const static uint64_t SH_FLD_LINK01_LO = 8638; // 2 -const static uint64_t SH_FLD_LINK01_LO_LEN = 8639; // 2 -const static uint64_t SH_FLD_LINK02_HI = 8640; // 2 -const static uint64_t SH_FLD_LINK02_HI_LEN = 8641; // 2 -const static uint64_t SH_FLD_LINK02_LO = 8642; // 2 -const static uint64_t SH_FLD_LINK02_LO_LEN = 8643; // 2 -const static uint64_t SH_FLD_LINK03_HI = 8644; // 2 -const static uint64_t SH_FLD_LINK03_HI_LEN = 8645; // 2 -const static uint64_t SH_FLD_LINK03_LO = 8646; // 2 -const static uint64_t SH_FLD_LINK03_LO_LEN = 8647; // 2 -const static uint64_t SH_FLD_LINK04_HI = 8648; // 2 -const static uint64_t SH_FLD_LINK04_HI_LEN = 8649; // 2 -const static uint64_t SH_FLD_LINK04_LO = 8650; // 2 -const static uint64_t SH_FLD_LINK04_LO_LEN = 8651; // 2 -const static uint64_t SH_FLD_LINK05_HI = 8652; // 2 -const static uint64_t SH_FLD_LINK05_HI_LEN = 8653; // 2 -const static uint64_t SH_FLD_LINK05_LO = 8654; // 2 -const static uint64_t SH_FLD_LINK05_LO_LEN = 8655; // 2 -const static uint64_t SH_FLD_LINK06_HI = 8656; // 1 -const static uint64_t SH_FLD_LINK06_HI_LEN = 8657; // 1 -const static uint64_t SH_FLD_LINK06_LO = 8658; // 1 -const static uint64_t SH_FLD_LINK06_LO_LEN = 8659; // 1 -const static uint64_t SH_FLD_LINK07_HI = 8660; // 1 -const static uint64_t SH_FLD_LINK07_HI_LEN = 8661; // 1 -const static uint64_t SH_FLD_LINK07_LO = 8662; // 1 -const static uint64_t SH_FLD_LINK07_LO_LEN = 8663; // 1 -const static uint64_t SH_FLD_LINK0_DOB_LIMIT = 8664; // 1 -const static uint64_t SH_FLD_LINK0_DOB_LIMIT_LEN = 8665; // 1 -const static uint64_t SH_FLD_LINK0_DOB_VC0_LIMIT = 8666; // 2 -const static uint64_t SH_FLD_LINK0_DOB_VC0_LIMIT_LEN = 8667; // 2 -const static uint64_t SH_FLD_LINK0_DOB_VC1_LIMIT = 8668; // 2 -const static uint64_t SH_FLD_LINK0_DOB_VC1_LIMIT_LEN = 8669; // 2 -const static uint64_t SH_FLD_LINK0_SPARE = 8670; // 1 -const static uint64_t SH_FLD_LINK0_SPARE_LEN = 8671; // 1 -const static uint64_t SH_FLD_LINK1_DOB_LIMIT = 8672; // 1 -const static uint64_t SH_FLD_LINK1_DOB_LIMIT_LEN = 8673; // 1 -const static uint64_t SH_FLD_LINK1_DOB_VC0_LIMIT = 8674; // 2 -const static uint64_t SH_FLD_LINK1_DOB_VC0_LIMIT_LEN = 8675; // 2 -const static uint64_t SH_FLD_LINK1_DOB_VC1_LIMIT = 8676; // 2 -const static uint64_t SH_FLD_LINK1_DOB_VC1_LIMIT_LEN = 8677; // 2 -const static uint64_t SH_FLD_LINK1_SPARE = 8678; // 1 -const static uint64_t SH_FLD_LINK1_SPARE_LEN = 8679; // 1 -const static uint64_t SH_FLD_LINK23_DIB_VC_LIMIT = 8680; // 2 -const static uint64_t SH_FLD_LINK23_DIB_VC_LIMIT_LEN = 8681; // 2 -const static uint64_t SH_FLD_LINK2_DOB_LIMIT = 8682; // 2 -const static uint64_t SH_FLD_LINK2_DOB_LIMIT_LEN = 8683; // 2 -const static uint64_t SH_FLD_LINK2_DOB_VC0_LIMIT = 8684; // 2 -const static uint64_t SH_FLD_LINK2_DOB_VC0_LIMIT_LEN = 8685; // 2 -const static uint64_t SH_FLD_LINK2_DOB_VC1_LIMIT = 8686; // 2 -const static uint64_t SH_FLD_LINK2_DOB_VC1_LIMIT_LEN = 8687; // 2 -const static uint64_t SH_FLD_LINK3_DOB_LIMIT = 8688; // 2 -const static uint64_t SH_FLD_LINK3_DOB_LIMIT_LEN = 8689; // 2 -const static uint64_t SH_FLD_LINK3_DOB_VC0_LIMIT = 8690; // 2 -const static uint64_t SH_FLD_LINK3_DOB_VC0_LIMIT_LEN = 8691; // 2 -const static uint64_t SH_FLD_LINK3_DOB_VC1_LIMIT = 8692; // 2 -const static uint64_t SH_FLD_LINK3_DOB_VC1_LIMIT_LEN = 8693; // 2 -const static uint64_t SH_FLD_LINK45_DIB_VC_LIMIT = 8694; // 2 -const static uint64_t SH_FLD_LINK45_DIB_VC_LIMIT_LEN = 8695; // 2 -const static uint64_t SH_FLD_LINK4_DOB_LIMIT = 8696; // 2 -const static uint64_t SH_FLD_LINK4_DOB_LIMIT_LEN = 8697; // 2 -const static uint64_t SH_FLD_LINK4_DOB_VC0_LIMIT = 8698; // 2 -const static uint64_t SH_FLD_LINK4_DOB_VC0_LIMIT_LEN = 8699; // 2 -const static uint64_t SH_FLD_LINK4_DOB_VC1_LIMIT = 8700; // 2 -const static uint64_t SH_FLD_LINK4_DOB_VC1_LIMIT_LEN = 8701; // 2 -const static uint64_t SH_FLD_LINK5_DOB_LIMIT = 8702; // 2 -const static uint64_t SH_FLD_LINK5_DOB_LIMIT_LEN = 8703; // 2 -const static uint64_t SH_FLD_LINK5_DOB_VC0_LIMIT = 8704; // 2 -const static uint64_t SH_FLD_LINK5_DOB_VC0_LIMIT_LEN = 8705; // 2 -const static uint64_t SH_FLD_LINK5_DOB_VC1_LIMIT = 8706; // 2 -const static uint64_t SH_FLD_LINK5_DOB_VC1_LIMIT_LEN = 8707; // 2 -const static uint64_t SH_FLD_LINK67_CAPP_MODE = 8708; // 1 -const static uint64_t SH_FLD_LINK67_DIB_VC_LIMIT = 8709; // 1 -const static uint64_t SH_FLD_LINK67_DIB_VC_LIMIT_LEN = 8710; // 1 -const static uint64_t SH_FLD_LINK67_HRB_INIT_STATE = 8711; // 1 -const static uint64_t SH_FLD_LINK6_DOB_VC0_LIMIT = 8712; // 1 -const static uint64_t SH_FLD_LINK6_DOB_VC0_LIMIT_LEN = 8713; // 1 -const static uint64_t SH_FLD_LINK6_DOB_VC1_LIMIT = 8714; // 1 -const static uint64_t SH_FLD_LINK6_DOB_VC1_LIMIT_LEN = 8715; // 1 -const static uint64_t SH_FLD_LINK6_SPARE = 8716; // 1 -const static uint64_t SH_FLD_LINK6_SPARE_LEN = 8717; // 1 -const static uint64_t SH_FLD_LINK7_DOB_VC0_LIMIT = 8718; // 1 -const static uint64_t SH_FLD_LINK7_DOB_VC0_LIMIT_LEN = 8719; // 1 -const static uint64_t SH_FLD_LINK7_DOB_VC1_LIMIT = 8720; // 1 -const static uint64_t SH_FLD_LINK7_DOB_VC1_LIMIT_LEN = 8721; // 1 -const static uint64_t SH_FLD_LINK7_SPARE = 8722; // 1 -const static uint64_t SH_FLD_LINK7_SPARE_LEN = 8723; // 1 -const static uint64_t SH_FLD_LINKS01_TOD_ENABLE = 8724; // 1 -const static uint64_t SH_FLD_LINKS23_TOD_ENABLE = 8725; // 1 -const static uint64_t SH_FLD_LINKS45_TOD_ENABLE = 8726; // 1 -const static uint64_t SH_FLD_LINKS67_TOD_ENABLE = 8727; // 1 -const static uint64_t SH_FLD_LINK_AVP_MODE = 8728; // 2 -const static uint64_t SH_FLD_LINUX_TRIG_MODE = 8729; // 1 -const static uint64_t SH_FLD_LISTEN_TO_PULSE_DIS = 8730; // 43 -const static uint64_t SH_FLD_LO = 8731; // 1 -const static uint64_t SH_FLD_LOCALITY_4_ACCESS = 8732; // 1 -const static uint64_t SH_FLD_LOCAL_HIGH_PRIORITY = 8733; // 4 -const static uint64_t SH_FLD_LOCAL_HIGH_PRIORITY_LEN = 8734; // 4 -const static uint64_t SH_FLD_LOCAL_LOW_PRIORITY = 8735; // 4 -const static uint64_t SH_FLD_LOCAL_LOW_PRIORITY_LEN = 8736; // 4 -const static uint64_t SH_FLD_LOCAL_NODE_EPSILON = 8737; // 8 -const static uint64_t SH_FLD_LOCAL_NODE_EPSILON_LEN = 8738; // 8 -const static uint64_t SH_FLD_LOCAL_QUIESCE_ACHIEVED = 8739; // 1 -const static uint64_t SH_FLD_LOCK = 8740; // 16 -const static uint64_t SH_FLD_LOCKED_FSM_STATE = 8741; // 1 -const static uint64_t SH_FLD_LOCKED_FSM_STATE_LEN = 8742; // 1 -const static uint64_t SH_FLD_LOCKED_PIBM_ADDR = 8743; // 1 -const static uint64_t SH_FLD_LOCKED_PIBM_ADDR_LEN = 8744; // 1 -const static uint64_t SH_FLD_LOCKED_SEEPROM_ADDRESS = 8745; // 1 -const static uint64_t SH_FLD_LOCKED_SEEPROM_ADDRESS_LEN = 8746; // 1 -const static uint64_t SH_FLD_LOCK_PCB_ON_ERR = 8747; // 12 -const static uint64_t SH_FLD_LOCK_SEL = 8748; // 6 -const static uint64_t SH_FLD_LOFF_AMP_EN = 8749; // 6 -const static uint64_t SH_FLD_LOG = 8750; // 1 -const static uint64_t SH_FLD_LOG_LEN = 8751; // 1 -const static uint64_t SH_FLD_LOOP_BREAK_MODE = 8752; // 64 -const static uint64_t SH_FLD_LOOP_BREAK_MODE_LEN = 8753; // 64 -const static uint64_t SH_FLD_LOOP_COUNT = 8754; // 43 -const static uint64_t SH_FLD_LOOP_COUNT_LEN = 8755; // 43 -const static uint64_t SH_FLD_LOW = 8756; // 1 -const static uint64_t SH_FLD_LOW_IDLE_COUNT = 8757; // 8 -const static uint64_t SH_FLD_LOW_IDLE_COUNT_LEN = 8758; // 8 -const static uint64_t SH_FLD_LOW_IDLE_THRESHOLD = 8759; // 8 -const static uint64_t SH_FLD_LOW_IDLE_THRESHOLD_LEN = 8760; // 8 -const static uint64_t SH_FLD_LOW_LATENCY = 8761; // 8 -const static uint64_t SH_FLD_LOW_LEN = 8762; // 1 -const static uint64_t SH_FLD_LOW_ORDER_STEP_VALUE = 8763; // 1 -const static uint64_t SH_FLD_LOW_ORDER_STEP_VALUE_LEN = 8764; // 1 -const static uint64_t SH_FLD_LP = 8765; // 8 -const static uint64_t SH_FLD_LPARID = 8766; // 24 -const static uint64_t SH_FLD_LPARID_LEN = 8767; // 24 -const static uint64_t SH_FLD_LPARSHORT = 8768; // 272 -const static uint64_t SH_FLD_LPARSHORT_LEN = 8769; // 272 -const static uint64_t SH_FLD_LPCR_BOT = 8770; // 16 -const static uint64_t SH_FLD_LPCR_ISL = 8771; // 16 -const static uint64_t SH_FLD_LPCR_PS = 8772; // 16 -const static uint64_t SH_FLD_LPCR_PS_LEN = 8773; // 16 -const static uint64_t SH_FLD_LPCR_SC = 8774; // 16 -const static uint64_t SH_FLD_LPCR_TC = 8775; // 16 -const static uint64_t SH_FLD_LPC_MODE = 8776; // 2 -const static uint64_t SH_FLD_LPC_MODE_LEN = 8777; // 2 -const static uint64_t SH_FLD_LPID = 8778; // 9 -const static uint64_t SH_FLD_LPID_LEN = 8779; // 9 -const static uint64_t SH_FLD_LPID_MASK = 8780; // 1 -const static uint64_t SH_FLD_LPID_MASK_LEN = 8781; // 1 -const static uint64_t SH_FLD_LP_CNT_THRESH = 8782; // 6 -const static uint64_t SH_FLD_LP_CNT_THRESH_LEN = 8783; // 6 -const static uint64_t SH_FLD_LP_LEN = 8784; // 8 -const static uint64_t SH_FLD_LP_MAX_CRED_THRESH = 8785; // 6 -const static uint64_t SH_FLD_LP_MAX_CRED_THRESH_LEN = 8786; // 6 -const static uint64_t SH_FLD_LP_MIN_CRED_THRESH = 8787; // 6 -const static uint64_t SH_FLD_LP_MIN_CRED_THRESH_LEN = 8788; // 6 -const static uint64_t SH_FLD_LP_MODE_ENABLE = 8789; // 6 -const static uint64_t SH_FLD_LP_ONLY_MODE = 8790; // 6 -const static uint64_t SH_FLD_LP_TIMER_TICK_CONFIG = 8791; // 6 -const static uint64_t SH_FLD_LP_TIMER_TICK_CONFIG_LEN = 8792; // 6 -const static uint64_t SH_FLD_LRDIMM = 8793; // 2 -const static uint64_t SH_FLD_LRDIMM_CONTEXT = 8794; // 8 -const static uint64_t SH_FLD_LRDIMM_LEN = 8795; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD1 = 8796; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD10 = 8797; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD10_LEN = 8798; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD11 = 8799; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD11_LEN = 8800; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD12 = 8801; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD12_LEN = 8802; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD13 = 8803; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD13_LEN = 8804; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD14 = 8805; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD14_LEN = 8806; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD15 = 8807; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD15_LEN = 8808; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD1_LEN = 8809; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD2 = 8810; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD2_LEN = 8811; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD3 = 8812; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD3_LEN = 8813; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD4 = 8814; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD4_LEN = 8815; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD5 = 8816; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD5_LEN = 8817; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD6 = 8818; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD6_LEN = 8819; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD7 = 8820; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD7_LEN = 8821; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD8 = 8822; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD8_LEN = 8823; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD9 = 8824; // 2 -const static uint64_t SH_FLD_LRDIMM_WORD9_LEN = 8825; // 2 -const static uint64_t SH_FLD_LRU_ALL_MEMBERS_IN_CGC_ARE_LINE_DELETED = 8826; // 12 -const static uint64_t SH_FLD_LRU_READ_ERROR_DETECTED = 8827; // 12 -const static uint64_t SH_FLD_LTE_EN = 8828; // 4 -const static uint64_t SH_FLD_LUC = 8829; // 1 -const static uint64_t SH_FLD_LUC_LEN = 8830; // 1 -const static uint64_t SH_FLD_LUT = 8831; // 1 -const static uint64_t SH_FLD_LUT_LEN = 8832; // 1 -const static uint64_t SH_FLD_LVDIR_EN = 8833; // 12 -const static uint64_t SH_FLD_LVDIR_PERR = 8834; // 12 -const static uint64_t SH_FLD_LVLTRANS_FENCE = 8835; // 43 -const static uint64_t SH_FLD_M = 8836; // 1 -const static uint64_t SH_FLD_M0_BIT_MAP = 8837; // 8 -const static uint64_t SH_FLD_M0_BIT_MAP_LEN = 8838; // 8 -const static uint64_t SH_FLD_M0_PRIORITY = 8839; // 1 -const static uint64_t SH_FLD_M0_PRIORITY_LEN = 8840; // 1 -const static uint64_t SH_FLD_M0_PRIORITY_SEL = 8841; // 1 -const static uint64_t SH_FLD_M1HC0A = 8842; // 1 -const static uint64_t SH_FLD_M1HC0A_LEN = 8843; // 1 -const static uint64_t SH_FLD_M1HC0B = 8844; // 1 -const static uint64_t SH_FLD_M1HC0B_LEN = 8845; // 1 -const static uint64_t SH_FLD_M1HC1A = 8846; // 1 -const static uint64_t SH_FLD_M1HC1A_LEN = 8847; // 1 -const static uint64_t SH_FLD_M1HC1B = 8848; // 1 -const static uint64_t SH_FLD_M1HC1B_LEN = 8849; // 1 -const static uint64_t SH_FLD_M1HC2A = 8850; // 1 -const static uint64_t SH_FLD_M1HC2A_LEN = 8851; // 1 -const static uint64_t SH_FLD_M1HC2B = 8852; // 1 -const static uint64_t SH_FLD_M1HC2B_LEN = 8853; // 1 -const static uint64_t SH_FLD_M1SASIM1_ENABLE_PIB_ERROR = 8854; // 1 -const static uint64_t SH_FLD_M1SASIM1_ENABLE_PIB_PENDING = 8855; // 1 -const static uint64_t SH_FLD_M1SASIM1_ENABLE_XUP = 8856; // 1 -const static uint64_t SH_FLD_M1_BIT_MAP = 8857; // 8 -const static uint64_t SH_FLD_M1_BIT_MAP_LEN = 8858; // 8 -const static uint64_t SH_FLD_M1_PRIORITY = 8859; // 1 -const static uint64_t SH_FLD_M1_PRIORITY_LEN = 8860; // 1 -const static uint64_t SH_FLD_M1_PRIORITY_SEL = 8861; // 1 -const static uint64_t SH_FLD_M2HC0A = 8862; // 1 -const static uint64_t SH_FLD_M2HC0A_LEN = 8863; // 1 -const static uint64_t SH_FLD_M2HC0B = 8864; // 1 -const static uint64_t SH_FLD_M2HC0B_LEN = 8865; // 1 -const static uint64_t SH_FLD_M2HC1A = 8866; // 1 -const static uint64_t SH_FLD_M2HC1A_LEN = 8867; // 1 -const static uint64_t SH_FLD_M2HC1B = 8868; // 1 -const static uint64_t SH_FLD_M2HC1B_LEN = 8869; // 1 -const static uint64_t SH_FLD_M2HC2A = 8870; // 1 -const static uint64_t SH_FLD_M2HC2A_LEN = 8871; // 1 -const static uint64_t SH_FLD_M2HC2B = 8872; // 1 -const static uint64_t SH_FLD_M2HC2B_LEN = 8873; // 1 -const static uint64_t SH_FLD_M2_PRIORITY = 8874; // 1 -const static uint64_t SH_FLD_M2_PRIORITY_LEN = 8875; // 1 -const static uint64_t SH_FLD_M2_PRIORITY_SEL = 8876; // 1 -const static uint64_t SH_FLD_M3_PRIORITY = 8877; // 1 -const static uint64_t SH_FLD_M3_PRIORITY_LEN = 8878; // 1 -const static uint64_t SH_FLD_M3_PRIORITY_SEL = 8879; // 1 -const static uint64_t SH_FLD_M4_PRIORITY = 8880; // 1 -const static uint64_t SH_FLD_M4_PRIORITY_LEN = 8881; // 1 -const static uint64_t SH_FLD_M5_PRIORITY = 8882; // 1 -const static uint64_t SH_FLD_M5_PRIORITY_LEN = 8883; // 1 -const static uint64_t SH_FLD_M5_PRIORITY_SEL = 8884; // 1 -const static uint64_t SH_FLD_M6_PRIORITY = 8885; // 1 -const static uint64_t SH_FLD_M6_PRIORITY_LEN = 8886; // 1 -const static uint64_t SH_FLD_M7_PRIORITY = 8887; // 1 -const static uint64_t SH_FLD_M7_PRIORITY_LEN = 8888; // 1 -const static uint64_t SH_FLD_M7_PRIORITY_SEL = 8889; // 1 -const static uint64_t SH_FLD_MAGIC_COOKIE = 8890; // 1 -const static uint64_t SH_FLD_MAGIC_COOKIE_LEN = 8891; // 1 -const static uint64_t SH_FLD_MAINLINE_AUE = 8892; // 8 -const static uint64_t SH_FLD_MAINLINE_IAUE = 8893; // 8 -const static uint64_t SH_FLD_MAINLINE_IMPE = 8894; // 8 -const static uint64_t SH_FLD_MAINLINE_IRCD = 8895; // 8 -const static uint64_t SH_FLD_MAINLINE_IUE = 8896; // 8 -const static uint64_t SH_FLD_MAINLINE_MCE = 8897; // 8 -const static uint64_t SH_FLD_MAINLINE_MPE_RANK_0_TO_7 = 8898; // 8 -const static uint64_t SH_FLD_MAINLINE_MPE_RANK_0_TO_7_LEN = 8899; // 8 -const static uint64_t SH_FLD_MAINLINE_NCE = 8900; // 8 -const static uint64_t SH_FLD_MAINLINE_RCD = 8901; // 8 -const static uint64_t SH_FLD_MAINLINE_SCE = 8902; // 8 -const static uint64_t SH_FLD_MAINLINE_SUE = 8903; // 8 -const static uint64_t SH_FLD_MAINLINE_TCE = 8904; // 8 -const static uint64_t SH_FLD_MAINLINE_UE = 8905; // 8 -const static uint64_t SH_FLD_MAINTENANCE_AUE = 8906; // 8 -const static uint64_t SH_FLD_MAINTENANCE_IAUE = 8907; // 8 -const static uint64_t SH_FLD_MAINTENANCE_IMPE = 8908; // 8 -const static uint64_t SH_FLD_MAINTENANCE_IRCD = 8909; // 8 -const static uint64_t SH_FLD_MAINTENANCE_IUE = 8910; // 8 -const static uint64_t SH_FLD_MAINTENANCE_MCE = 8911; // 8 -const static uint64_t SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7 = 8912; // 8 -const static uint64_t SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7_LEN = 8913; // 8 -const static uint64_t SH_FLD_MAINTENANCE_NCE = 8914; // 8 -const static uint64_t SH_FLD_MAINTENANCE_RCD = 8915; // 8 -const static uint64_t SH_FLD_MAINTENANCE_SCE = 8916; // 8 -const static uint64_t SH_FLD_MAINTENANCE_SUE = 8917; // 8 -const static uint64_t SH_FLD_MAINTENANCE_TCE = 8918; // 8 -const static uint64_t SH_FLD_MAINTENANCE_UE = 8919; // 8 -const static uint64_t SH_FLD_MAINT_CCS_PE_HOLD_OUT = 8920; // 2 -const static uint64_t SH_FLD_MAIN_SLICE_EN_ENC = 8921; // 1 -const static uint64_t SH_FLD_MAIN_SLICE_EN_ENC_LEN = 8922; // 1 -const static uint64_t SH_FLD_MALFUNCTION_ALERT = 8923; // 96 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP0 = 8924; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP0_LEN = 8925; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP1 = 8926; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP10 = 8927; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP10_LEN = 8928; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP11 = 8929; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP11_LEN = 8930; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP12 = 8931; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP12_LEN = 8932; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP13 = 8933; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP13_LEN = 8934; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP14 = 8935; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP14_LEN = 8936; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP15 = 8937; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP15_LEN = 8938; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP1_LEN = 8939; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP2 = 8940; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP2_LEN = 8941; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP3 = 8942; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP3_LEN = 8943; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP4 = 8944; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP4_LEN = 8945; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP5 = 8946; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP5_LEN = 8947; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP6 = 8948; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP6_LEN = 8949; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP7 = 8950; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP7_LEN = 8951; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP8 = 8952; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP8_LEN = 8953; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP9 = 8954; // 1 -const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP9_LEN = 8955; // 1 -const static uint64_t SH_FLD_MANUAL_CLR_PB_STOP = 8956; // 1 -const static uint64_t SH_FLD_MANUAL_PB_SWITCH_ABCD = 8957; // 1 -const static uint64_t SH_FLD_MANUAL_SET_PB_STOP = 8958; // 1 -const static uint64_t SH_FLD_MAP_REG_CERR0 = 8959; // 1 -const static uint64_t SH_FLD_MAP_REG_CERR1 = 8960; // 1 -const static uint64_t SH_FLD_MAP_REG_ERR0 = 8961; // 1 -const static uint64_t SH_FLD_MAP_REG_ERR1 = 8962; // 1 -const static uint64_t SH_FLD_MARGINPD_SEL = 8963; // 6 -const static uint64_t SH_FLD_MARGINPD_SEL_LEN = 8964; // 6 -const static uint64_t SH_FLD_MARGINPU_SEL = 8965; // 6 -const static uint64_t SH_FLD_MARGINPU_SEL_LEN = 8966; // 6 -const static uint64_t SH_FLD_MARK = 8967; // 64 -const static uint64_t SH_FLD_MARK_LEN = 8968; // 64 -const static uint64_t SH_FLD_MASK = 8969; // 13 -const static uint64_t SH_FLD_MASK_AGV_DISABLE_MODE = 8970; // 2 -const static uint64_t SH_FLD_MASK_B = 8971; // 129 -const static uint64_t SH_FLD_MASK_LEN = 8972; // 5 -const static uint64_t SH_FLD_MASK_PURGE_INTERFACE = 8973; // 12 -const static uint64_t SH_FLD_MASK_TOGGLE_ENABLE = 8974; // 1 -const static uint64_t SH_FLD_MASTER = 8975; // 8 -const static uint64_t SH_FLD_MASTERID = 8976; // 6 -const static uint64_t SH_FLD_MASTERID_LEN = 8977; // 6 -const static uint64_t SH_FLD_MASTER_ARRAY_CE = 8978; // 4 -const static uint64_t SH_FLD_MASTER_ARRAY_UE = 8979; // 4 -const static uint64_t SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV = 8980; // 12 -const static uint64_t SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV_LEN = 8981; // 12 -const static uint64_t SH_FLD_MASTER_ERROR_CODE = 8982; // 1 -const static uint64_t SH_FLD_MASTER_ERROR_CODE_LEN = 8983; // 1 -const static uint64_t SH_FLD_MASTER_IDLE = 8984; // 1 -const static uint64_t SH_FLD_MASTER_MODE = 8985; // 47 -const static uint64_t SH_FLD_MASTER_RECOVERABLE_ERROR = 8986; // 4 -const static uint64_t SH_FLD_MASTER_RESPONSE_BIT = 8987; // 1 -const static uint64_t SH_FLD_MASTER_SYS_XSTOP_ERROR = 8988; // 4 -const static uint64_t SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV = 8989; // 12 -const static uint64_t SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN = 8990; // 12 -const static uint64_t SH_FLD_MAXCYCLECNT = 8991; // 3 -const static uint64_t SH_FLD_MAXCYCLECNT_LEN = 8992; // 3 -const static uint64_t SH_FLD_MAX_ALL_POLL_BCST_0_4 = 8993; // 1 -const static uint64_t SH_FLD_MAX_ALL_POLL_BCST_0_4_LEN = 8994; // 1 -const static uint64_t SH_FLD_MAX_BAD_LANES = 8995; // 4 -const static uint64_t SH_FLD_MAX_BAD_LANES_LEN = 8996; // 4 -const static uint64_t SH_FLD_MAX_BER_CHECK_COUNT = 8997; // 4 -const static uint64_t SH_FLD_MAX_BER_CHECK_COUNT_LEN = 8998; // 4 -const static uint64_t SH_FLD_MAX_CRD_TO_CQ = 8999; // 6 -const static uint64_t SH_FLD_MAX_CRD_TO_CQ_LEN = 9000; // 6 -const static uint64_t SH_FLD_MAX_CRD_TO_PC = 9001; // 6 -const static uint64_t SH_FLD_MAX_CRD_TO_PC_LEN = 9002; // 6 -const static uint64_t SH_FLD_MAX_CYCLE_SAMPLE = 9003; // 12 -const static uint64_t SH_FLD_MAX_CYCLE_SAMPLE_LEN = 9004; // 12 -const static uint64_t SH_FLD_MAX_ENTRIES_IN_MODIFIED = 9005; // 2 -const static uint64_t SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN = 9006; // 2 -const static uint64_t SH_FLD_MAX_GRP_POLL_BCST_0_4 = 9007; // 1 -const static uint64_t SH_FLD_MAX_GRP_POLL_BCST_0_4_LEN = 9008; // 1 -const static uint64_t SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS = 9009; // 2 -const static uint64_t SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS_LEN = 9010; // 2 -const static uint64_t SH_FLD_MAX_OUTSTANDING = 9011; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_CI_LOAD = 9012; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_CI_LOAD_LEN = 9013; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_CI_STORE = 9014; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_CI_STORE_LEN = 9015; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_EOI = 9016; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_EOI_LEN = 9017; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_EQD_FETCH = 9018; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_EQD_FETCH_LEN = 9019; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_EQD_WRITE = 9020; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_EQD_WRITE_LEN = 9021; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_EQP = 9022; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_EQP_LEN = 9023; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_ISB_FETCH = 9024; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_ISB_FETCH_LEN = 9025; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_ISB_WRITE = 9026; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_ISB_WRITE_LEN = 9027; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_IVE_FETCH = 9028; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_IVE_FETCH_LEN = 9029; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_LEN = 9030; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP = 9031; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP_LEN = 9032; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_SOFT_EOI = 9033; // 1 -const static uint64_t SH_FLD_MAX_OUTSTANDING_SOFT_EOI_LEN = 9034; // 1 -const static uint64_t SH_FLD_MAX_PROMOTE_LEVEL_A_N = 9035; // 96 -const static uint64_t SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN = 9036; // 96 -const static uint64_t SH_FLD_MAX_PTAG_IN_USE = 9037; // 3 -const static uint64_t SH_FLD_MAX_PTAG_IN_USE_LEN = 9038; // 3 -const static uint64_t SH_FLD_MAX_UNLOCK_IN_FIFO = 9039; // 3 -const static uint64_t SH_FLD_MAX_UNLOCK_IN_FIFO_LEN = 9040; // 3 -const static uint64_t SH_FLD_MB00_SPATTN = 9041; // 4 -const static uint64_t SH_FLD_MB01_SPATTN = 9042; // 4 -const static uint64_t SH_FLD_MB10_SPATTN = 9043; // 4 -const static uint64_t SH_FLD_MB11_SPATTN = 9044; // 4 -const static uint64_t SH_FLD_MB20_SPATTN = 9045; // 4 -const static uint64_t SH_FLD_MB21_SPATTN = 9046; // 4 -const static uint64_t SH_FLD_MB30_SPATTN = 9047; // 4 -const static uint64_t SH_FLD_MB31_SPATTN = 9048; // 4 -const static uint64_t SH_FLD_MB40_SPATTN = 9049; // 4 -const static uint64_t SH_FLD_MB41_SPATTN = 9050; // 4 -const static uint64_t SH_FLD_MB50_SPATTN = 9051; // 4 -const static uint64_t SH_FLD_MB51_SPATTN = 9052; // 4 -const static uint64_t SH_FLD_MB60_SPATTN = 9053; // 2 -const static uint64_t SH_FLD_MB61_SPATTN = 9054; // 2 -const static uint64_t SH_FLD_MB70_SPATTN = 9055; // 2 -const static uint64_t SH_FLD_MB71_SPATTN = 9056; // 2 -const static uint64_t SH_FLD_MBASE = 9057; // 12 -const static uint64_t SH_FLD_MBASE_LEN = 9058; // 12 -const static uint64_t SH_FLD_MBA_NONRECOVERABLE_ERROR = 9059; // 16 -const static uint64_t SH_FLD_MBA_RECOVERABLE_ERROR = 9060; // 16 -const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_CAW2_CE_UE_ERR_DETECT_EN = 9061; // 8 -const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_EN = 9062; // 8 -const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_X8 = 9063; // 8 -const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_CHK_DISABLE = 9064; // 8 -const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_COR_DISABLE = 9065; // 8 -const static uint64_t SH_FLD_MBA_WRD_MODE_RESERVED_4 = 9066; // 8 -const static uint64_t SH_FLD_MBOX0 = 9067; // 1 -const static uint64_t SH_FLD_MBOX0_LEN = 9068; // 1 -const static uint64_t SH_FLD_MBOX1 = 9069; // 1 -const static uint64_t SH_FLD_MBOX1_LEN = 9070; // 1 -const static uint64_t SH_FLD_MBOX2 = 9071; // 1 -const static uint64_t SH_FLD_MBOX2_LEN = 9072; // 1 -const static uint64_t SH_FLD_MBOX3 = 9073; // 1 -const static uint64_t SH_FLD_MBOX3_LEN = 9074; // 1 -const static uint64_t SH_FLD_MBOX4 = 9075; // 1 -const static uint64_t SH_FLD_MBOX4_LEN = 9076; // 1 -const static uint64_t SH_FLD_MBOX5 = 9077; // 1 -const static uint64_t SH_FLD_MBOX5_LEN = 9078; // 1 -const static uint64_t SH_FLD_MBOX6 = 9079; // 1 -const static uint64_t SH_FLD_MBOX6_LEN = 9080; // 1 -const static uint64_t SH_FLD_MBOX7 = 9081; // 1 -const static uint64_t SH_FLD_MBOX7_LEN = 9082; // 1 -const static uint64_t SH_FLD_MBR_DIS = 9083; // 2 -const static uint64_t SH_FLD_MBR_DIS_LEN = 9084; // 2 -const static uint64_t SH_FLD_MBSECCQ_DATA_GENERATOR_META_ENABLE = 9085; // 8 -const static uint64_t SH_FLD_MBSECCQ_DATA_GENERATOR_OVERRIDE = 9086; // 8 -const static uint64_t SH_FLD_MBSECCQ_DATA_INVERSION = 9087; // 8 -const static uint64_t SH_FLD_MBSECCQ_DATA_INVERSION_LEN = 9088; // 8 -const static uint64_t SH_FLD_MBSECCQ_DELAY_NONBYPASS = 9089; // 8 -const static uint64_t SH_FLD_MBSECCQ_DELAY_VALID_1X = 9090; // 8 -const static uint64_t SH_FLD_MBSECCQ_DISABLE_MARK_STORE_WRITE = 9091; // 8 -const static uint64_t SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT = 9092; // 8 -const static uint64_t SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT = 9093; // 8 -const static uint64_t SH_FLD_MBSECCQ_DISABLE_UE_RETRY = 9094; // 8 -const static uint64_t SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY = 9095; // 8 -const static uint64_t SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY_LEN = 9096; // 8 -const static uint64_t SH_FLD_MBSECCQ_ENABLE_HOST_ATTENTION = 9097; // 8 -const static uint64_t SH_FLD_MBSECCQ_ENABLE_SPECIAL_ATTENTION = 9098; // 8 -const static uint64_t SH_FLD_MBSECCQ_EXIT_OVERRIDE = 9099; // 8 -const static uint64_t SH_FLD_MBSECCQ_EXIT_OVERRIDE_LEN = 9100; // 8 -const static uint64_t SH_FLD_MBSECCQ_INT_RESET_KEEPER = 9101; // 8 -const static uint64_t SH_FLD_MBSECCQ_ITAG_METADATA_ENABLE = 9102; // 8 -const static uint64_t SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY = 9103; // 8 -const static uint64_t SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY_LEN = 9104; // 8 -const static uint64_t SH_FLD_MBSECCQ_READ_POINTER_DELAY = 9105; // 8 -const static uint64_t SH_FLD_MBSECCQ_READ_POINTER_DELAY_LEN = 9106; // 8 -const static uint64_t SH_FLD_MBSECCQ_RESERVED_10 = 9107; // 8 -const static uint64_t SH_FLD_MBSECCQ_RESERVED_12_16 = 9108; // 8 -const static uint64_t SH_FLD_MBSECCQ_RESERVED_12_16_LEN = 9109; // 8 -const static uint64_t SH_FLD_MBSECCQ_RESERVED_2 = 9110; // 8 -const static uint64_t SH_FLD_MBSECCQ_RESERVED_22_25 = 9111; // 8 -const static uint64_t SH_FLD_MBSECCQ_RESERVED_22_25_LEN = 9112; // 8 -const static uint64_t SH_FLD_MBSECCQ_RESERVED_3 = 9113; // 8 -const static uint64_t SH_FLD_MBSECCQ_RESERVED_4 = 9114; // 8 -const static uint64_t SH_FLD_MBSECCQ_RESERVED_40_47 = 9115; // 8 -const static uint64_t SH_FLD_MBSECCQ_RESERVED_40_47_LEN = 9116; // 8 -const static uint64_t SH_FLD_MBSECCQ_RESERVED_51 = 9117; // 8 -const static uint64_t SH_FLD_MBSECCQ_RESERVED_7_8 = 9118; // 8 -const static uint64_t SH_FLD_MBSECCQ_RESERVED_7_8_LEN = 9119; // 8 -const static uint64_t SH_FLD_MBSECCQ_USE_ADDRESS_HASH = 9120; // 8 -const static uint64_t SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY = 9121; // 8 -const static uint64_t SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY_LEN = 9122; // 8 -const static uint64_t SH_FLD_MB_BAD_ADDR = 9123; // 2 -const static uint64_t SH_FLD_MB_BAD_WRITE = 9124; // 2 -const static uint64_t SH_FLD_MB_CORRUPT = 9125; // 2 -const static uint64_t SH_FLD_MB_LINK_DOWN = 9126; // 2 -const static uint64_t SH_FLD_MB_LINK_ID = 9127; // 2 -const static uint64_t SH_FLD_MB_LINK_ID_LEN = 9128; // 2 -const static uint64_t SH_FLD_MB_RESET = 9129; // 2 -const static uint64_t SH_FLD_MB_SENT = 9130; // 2 -const static uint64_t SH_FLD_MB_SPARE = 9131; // 2 -const static uint64_t SH_FLD_MB_SPARE_LEN = 9132; // 2 -const static uint64_t SH_FLD_MB_VALID = 9133; // 2 -const static uint64_t SH_FLD_MB_WR_NOT_RD = 9134; // 2 -const static uint64_t SH_FLD_MCA_DBG_SEL_IN = 9135; // 8 -const static uint64_t SH_FLD_MCA_DBG_SEL_WRT = 9136; // 8 -const static uint64_t SH_FLD_MCBAGEN_PE_HOLD_OUT = 9137; // 2 -const static uint64_t SH_FLD_MCBCNTL_PE_HOLD_OUT = 9138; // 2 -const static uint64_t SH_FLD_MCBCNTL_PORT_SEL = 9139; // 2 -const static uint64_t SH_FLD_MCBCNTL_PORT_SEL_LEN = 9140; // 2 -const static uint64_t SH_FLD_MCBDGEN_PE_HOLD_OUT = 9141; // 2 -const static uint64_t SH_FLD_MCBERR_SCOM_PE_HOLD_OUT = 9142; // 2 -const static uint64_t SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC = 9143; // 10 -const static uint64_t SH_FLD_MCBIST_CCS_SUBTEST_DONE = 9144; // 10 -const static uint64_t SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR = 9145; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST = 9146; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST = 9147; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_REF_WAIT_TIME = 9148; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_REF_WAIT_TIME_LEN = 9149; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_RAND_MODE = 9150; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_REV_MODE = 9151; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL = 9152; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL_LEN = 9153; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_1ST_CMD = 9154; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_2ND_CMD = 9155; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_3RD_CMD = 9156; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST00_DATA_MODE = 9157; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST00_DATA_MODE_LEN = 9158; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST00_DONE = 9159; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ECC_MODE = 9160; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST00_OP_TYPE = 9161; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST00_OP_TYPE_LEN = 9162; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_RAND_MODE = 9163; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_REV_MODE = 9164; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL = 9165; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL_LEN = 9166; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_1ST_CMD = 9167; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_2ND_CMD = 9168; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_3RD_CMD = 9169; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST01_DATA_MODE = 9170; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST01_DATA_MODE_LEN = 9171; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST01_DONE = 9172; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ECC_MODE = 9173; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST01_OP_TYPE = 9174; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST01_OP_TYPE_LEN = 9175; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_RAND_MODE = 9176; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_REV_MODE = 9177; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL = 9178; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL_LEN = 9179; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_1ST_CMD = 9180; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_2ND_CMD = 9181; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_3RD_CMD = 9182; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST02_DATA_MODE = 9183; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST02_DATA_MODE_LEN = 9184; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST02_DONE = 9185; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ECC_MODE = 9186; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST02_OP_TYPE = 9187; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST02_OP_TYPE_LEN = 9188; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_RAND_MODE = 9189; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_REV_MODE = 9190; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL = 9191; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL_LEN = 9192; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_1ST_CMD = 9193; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_2ND_CMD = 9194; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_3RD_CMD = 9195; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST03_DATA_MODE = 9196; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST03_DATA_MODE_LEN = 9197; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST03_DONE = 9198; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ECC_MODE = 9199; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST03_OP_TYPE = 9200; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST03_OP_TYPE_LEN = 9201; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_RAND_MODE = 9202; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_REV_MODE = 9203; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL = 9204; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL_LEN = 9205; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_1ST_CMD = 9206; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_2ND_CMD = 9207; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_3RD_CMD = 9208; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST04_DATA_MODE = 9209; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST04_DATA_MODE_LEN = 9210; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST04_DONE = 9211; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ECC_MODE = 9212; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST04_OP_TYPE = 9213; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST04_OP_TYPE_LEN = 9214; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_RAND_MODE = 9215; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_REV_MODE = 9216; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL = 9217; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL_LEN = 9218; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_1ST_CMD = 9219; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_2ND_CMD = 9220; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_3RD_CMD = 9221; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST05_DATA_MODE = 9222; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST05_DATA_MODE_LEN = 9223; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST05_DONE = 9224; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ECC_MODE = 9225; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST05_OP_TYPE = 9226; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST05_OP_TYPE_LEN = 9227; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_RAND_MODE = 9228; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_REV_MODE = 9229; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL = 9230; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL_LEN = 9231; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_1ST_CMD = 9232; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_2ND_CMD = 9233; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_3RD_CMD = 9234; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST06_DATA_MODE = 9235; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST06_DATA_MODE_LEN = 9236; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST06_DONE = 9237; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ECC_MODE = 9238; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST06_OP_TYPE = 9239; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST06_OP_TYPE_LEN = 9240; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_RAND_MODE = 9241; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_REV_MODE = 9242; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL = 9243; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL_LEN = 9244; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_1ST_CMD = 9245; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_2ND_CMD = 9246; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_3RD_CMD = 9247; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST07_DATA_MODE = 9248; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST07_DATA_MODE_LEN = 9249; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST07_DONE = 9250; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ECC_MODE = 9251; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST07_OP_TYPE = 9252; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST07_OP_TYPE_LEN = 9253; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_RAND_MODE = 9254; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_REV_MODE = 9255; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL = 9256; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL_LEN = 9257; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_1ST_CMD = 9258; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_2ND_CMD = 9259; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_3RD_CMD = 9260; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST08_DATA_MODE = 9261; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST08_DATA_MODE_LEN = 9262; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST08_DONE = 9263; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ECC_MODE = 9264; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST08_OP_TYPE = 9265; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST08_OP_TYPE_LEN = 9266; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_RAND_MODE = 9267; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_REV_MODE = 9268; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL = 9269; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL_LEN = 9270; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_1ST_CMD = 9271; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_2ND_CMD = 9272; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_3RD_CMD = 9273; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST09_DATA_MODE = 9274; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST09_DATA_MODE_LEN = 9275; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST09_DONE = 9276; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ECC_MODE = 9277; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST09_OP_TYPE = 9278; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST09_OP_TYPE_LEN = 9279; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_RAND_MODE = 9280; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_REV_MODE = 9281; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL = 9282; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL_LEN = 9283; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_1ST_CMD = 9284; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_2ND_CMD = 9285; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_3RD_CMD = 9286; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST10_DATA_MODE = 9287; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST10_DATA_MODE_LEN = 9288; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST10_DONE = 9289; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ECC_MODE = 9290; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST10_OP_TYPE = 9291; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST10_OP_TYPE_LEN = 9292; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_RAND_MODE = 9293; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_REV_MODE = 9294; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL = 9295; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL_LEN = 9296; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_1ST_CMD = 9297; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_2ND_CMD = 9298; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_3RD_CMD = 9299; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST11_DATA_MODE = 9300; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST11_DATA_MODE_LEN = 9301; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST11_DONE = 9302; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ECC_MODE = 9303; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST11_OP_TYPE = 9304; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST11_OP_TYPE_LEN = 9305; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_RAND_MODE = 9306; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_REV_MODE = 9307; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL = 9308; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL_LEN = 9309; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_1ST_CMD = 9310; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_2ND_CMD = 9311; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_3RD_CMD = 9312; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST12_DATA_MODE = 9313; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST12_DATA_MODE_LEN = 9314; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST12_DONE = 9315; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ECC_MODE = 9316; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST12_OP_TYPE = 9317; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST12_OP_TYPE_LEN = 9318; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_RAND_MODE = 9319; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_REV_MODE = 9320; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL = 9321; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL_LEN = 9322; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_1ST_CMD = 9323; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_2ND_CMD = 9324; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_3RD_CMD = 9325; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST13_DATA_MODE = 9326; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST13_DATA_MODE_LEN = 9327; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST13_DONE = 9328; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ECC_MODE = 9329; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST13_OP_TYPE = 9330; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST13_OP_TYPE_LEN = 9331; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_RAND_MODE = 9332; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_REV_MODE = 9333; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL = 9334; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL_LEN = 9335; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_1ST_CMD = 9336; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_2ND_CMD = 9337; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_3RD_CMD = 9338; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST14_DATA_MODE = 9339; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST14_DATA_MODE_LEN = 9340; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST14_DONE = 9341; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ECC_MODE = 9342; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST14_OP_TYPE = 9343; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST14_OP_TYPE_LEN = 9344; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_RAND_MODE = 9345; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_REV_MODE = 9346; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL = 9347; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL_LEN = 9348; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_1ST_CMD = 9349; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_2ND_CMD = 9350; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_3RD_CMD = 9351; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST15_DATA_MODE = 9352; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST15_DATA_MODE_LEN = 9353; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST15_DONE = 9354; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ECC_MODE = 9355; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST15_OP_TYPE = 9356; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST15_OP_TYPE_LEN = 9357; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_RAND_MODE = 9358; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_REV_MODE = 9359; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL = 9360; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL_LEN = 9361; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_1ST_CMD = 9362; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_2ND_CMD = 9363; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_3RD_CMD = 9364; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST16_DATA_MODE = 9365; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST16_DATA_MODE_LEN = 9366; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST16_DONE = 9367; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ECC_MODE = 9368; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST16_OP_TYPE = 9369; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST16_OP_TYPE_LEN = 9370; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_RAND_MODE = 9371; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_REV_MODE = 9372; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL = 9373; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL_LEN = 9374; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_1ST_CMD = 9375; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_2ND_CMD = 9376; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_3RD_CMD = 9377; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST17_DATA_MODE = 9378; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST17_DATA_MODE_LEN = 9379; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST17_DONE = 9380; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ECC_MODE = 9381; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST17_OP_TYPE = 9382; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST17_OP_TYPE_LEN = 9383; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_RAND_MODE = 9384; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_REV_MODE = 9385; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL = 9386; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL_LEN = 9387; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_1ST_CMD = 9388; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_2ND_CMD = 9389; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_3RD_CMD = 9390; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST18_DATA_MODE = 9391; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST18_DATA_MODE_LEN = 9392; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST18_DONE = 9393; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ECC_MODE = 9394; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST18_OP_TYPE = 9395; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST18_OP_TYPE_LEN = 9396; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_RAND_MODE = 9397; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_REV_MODE = 9398; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL = 9399; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL_LEN = 9400; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_1ST_CMD = 9401; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_2ND_CMD = 9402; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_3RD_CMD = 9403; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST19_DATA_MODE = 9404; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST19_DATA_MODE_LEN = 9405; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST19_DONE = 9406; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ECC_MODE = 9407; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST19_OP_TYPE = 9408; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST19_OP_TYPE_LEN = 9409; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_RAND_MODE = 9410; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_REV_MODE = 9411; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL = 9412; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL_LEN = 9413; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_1ST_CMD = 9414; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_2ND_CMD = 9415; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_3RD_CMD = 9416; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST20_DATA_MODE = 9417; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST20_DATA_MODE_LEN = 9418; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST20_DONE = 9419; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ECC_MODE = 9420; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST20_OP_TYPE = 9421; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST20_OP_TYPE_LEN = 9422; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_RAND_MODE = 9423; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_REV_MODE = 9424; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL = 9425; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL_LEN = 9426; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_1ST_CMD = 9427; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_2ND_CMD = 9428; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_3RD_CMD = 9429; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST21_DATA_MODE = 9430; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST21_DATA_MODE_LEN = 9431; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST21_DONE = 9432; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ECC_MODE = 9433; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST21_OP_TYPE = 9434; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST21_OP_TYPE_LEN = 9435; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_RAND_MODE = 9436; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_REV_MODE = 9437; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL = 9438; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL_LEN = 9439; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_1ST_CMD = 9440; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_2ND_CMD = 9441; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_3RD_CMD = 9442; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST22_DATA_MODE = 9443; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST22_DATA_MODE_LEN = 9444; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST22_DONE = 9445; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ECC_MODE = 9446; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST22_OP_TYPE = 9447; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST22_OP_TYPE_LEN = 9448; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_RAND_MODE = 9449; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_REV_MODE = 9450; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL = 9451; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL_LEN = 9452; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_1ST_CMD = 9453; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_2ND_CMD = 9454; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_3RD_CMD = 9455; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST23_DATA_MODE = 9456; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST23_DATA_MODE_LEN = 9457; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST23_DONE = 9458; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ECC_MODE = 9459; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST23_OP_TYPE = 9460; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST23_OP_TYPE_LEN = 9461; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_RAND_MODE = 9462; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_REV_MODE = 9463; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL = 9464; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL_LEN = 9465; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_1ST_CMD = 9466; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_2ND_CMD = 9467; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_3RD_CMD = 9468; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST24_DATA_MODE = 9469; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST24_DATA_MODE_LEN = 9470; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST24_DONE = 9471; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ECC_MODE = 9472; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST24_OP_TYPE = 9473; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST24_OP_TYPE_LEN = 9474; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_RAND_MODE = 9475; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_REV_MODE = 9476; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL = 9477; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL_LEN = 9478; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_1ST_CMD = 9479; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_2ND_CMD = 9480; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_3RD_CMD = 9481; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST25_DATA_MODE = 9482; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST25_DATA_MODE_LEN = 9483; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST25_DONE = 9484; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ECC_MODE = 9485; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST25_OP_TYPE = 9486; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST25_OP_TYPE_LEN = 9487; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_RAND_MODE = 9488; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_REV_MODE = 9489; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL = 9490; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL_LEN = 9491; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_1ST_CMD = 9492; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_2ND_CMD = 9493; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_3RD_CMD = 9494; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST26_DATA_MODE = 9495; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST26_DATA_MODE_LEN = 9496; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST26_DONE = 9497; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ECC_MODE = 9498; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST26_OP_TYPE = 9499; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST26_OP_TYPE_LEN = 9500; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_RAND_MODE = 9501; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_REV_MODE = 9502; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL = 9503; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL_LEN = 9504; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_1ST_CMD = 9505; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_2ND_CMD = 9506; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_3RD_CMD = 9507; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST27_DATA_MODE = 9508; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST27_DATA_MODE_LEN = 9509; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST27_DONE = 9510; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ECC_MODE = 9511; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST27_OP_TYPE = 9512; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST27_OP_TYPE_LEN = 9513; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_RAND_MODE = 9514; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_REV_MODE = 9515; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL = 9516; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL_LEN = 9517; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_1ST_CMD = 9518; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_2ND_CMD = 9519; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_3RD_CMD = 9520; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST28_DATA_MODE = 9521; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST28_DATA_MODE_LEN = 9522; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST28_DONE = 9523; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ECC_MODE = 9524; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST28_OP_TYPE = 9525; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST28_OP_TYPE_LEN = 9526; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_RAND_MODE = 9527; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_REV_MODE = 9528; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL = 9529; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL_LEN = 9530; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_1ST_CMD = 9531; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_2ND_CMD = 9532; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_3RD_CMD = 9533; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST29_DATA_MODE = 9534; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST29_DATA_MODE_LEN = 9535; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST29_DONE = 9536; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ECC_MODE = 9537; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST29_OP_TYPE = 9538; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST29_OP_TYPE_LEN = 9539; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_RAND_MODE = 9540; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_REV_MODE = 9541; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL = 9542; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL_LEN = 9543; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_1ST_CMD = 9544; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_2ND_CMD = 9545; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_3RD_CMD = 9546; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST30_DATA_MODE = 9547; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST30_DATA_MODE_LEN = 9548; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST30_DONE = 9549; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ECC_MODE = 9550; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST30_OP_TYPE = 9551; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST30_OP_TYPE_LEN = 9552; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_RAND_MODE = 9553; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_REV_MODE = 9554; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL = 9555; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL_LEN = 9556; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_1ST_CMD = 9557; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_2ND_CMD = 9558; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_3RD_CMD = 9559; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST31_DATA_MODE = 9560; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST31_DATA_MODE_LEN = 9561; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST31_DONE = 9562; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ECC_MODE = 9563; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST31_OP_TYPE = 9564; // 2 -const static uint64_t SH_FLD_MCBIST_CFG_TEST31_OP_TYPE_LEN = 9565; // 2 -const static uint64_t SH_FLD_MCBIST_DATA_ERROR = 9566; // 10 -const static uint64_t SH_FLD_MCBIST_FSM_INJ_MODE = 9567; // 2 -const static uint64_t SH_FLD_MCBIST_FSM_INJ_REG = 9568; // 2 -const static uint64_t SH_FLD_MCBIST_HALF_COMPARE_MASK = 9569; // 8 -const static uint64_t SH_FLD_MCBIST_HALF_COMPARE_MASK_LEN = 9570; // 8 -const static uint64_t SH_FLD_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR = 9571; // 2 -const static uint64_t SH_FLD_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR_LEN = 9572; // 2 -const static uint64_t SH_FLD_MCBIST_MASK_COVERAGE_SELECTOR = 9573; // 8 -const static uint64_t SH_FLD_MCBIST_PROGRAM_COMPLETE = 9574; // 10 -const static uint64_t SH_FLD_MCBIST_SUBTEST_IP = 9575; // 2 -const static uint64_t SH_FLD_MCBIST_SUBTEST_NUM_INDICATOR = 9576; // 2 -const static uint64_t SH_FLD_MCBIST_SUBTEST_NUM_INDICATOR_LEN = 9577; // 2 -const static uint64_t SH_FLD_MCBIST_TRAP_CE_ENABLE = 9578; // 8 -const static uint64_t SH_FLD_MCBIST_TRAP_MPE_ENABLE = 9579; // 8 -const static uint64_t SH_FLD_MCBIST_TRAP_NONSTOP = 9580; // 8 -const static uint64_t SH_FLD_MCBIST_TRAP_UE_ENABLE = 9581; // 8 -const static uint64_t SH_FLD_MCB_CNTLQ_PE_HOLD_OUT = 9582; // 2 -const static uint64_t SH_FLD_MCB_FIR_CCS_ERR_HOLD_OUT = 9583; // 2 -const static uint64_t SH_FLD_MCB_FIR_MCBFSM_ERR_HOLD_OUT = 9584; // 2 -const static uint64_t SH_FLD_MCD_CHICKEN_SWITCH = 9585; // 2 -const static uint64_t SH_FLD_MCEBUSEN0_EVENT_BUS_SELECTS = 9586; // 4 -const static uint64_t SH_FLD_MCEBUSEN0_EVENT_BUS_SELECTS_LEN = 9587; // 4 -const static uint64_t SH_FLD_MCE_SYMBOL0_COUNT = 9588; // 2 -const static uint64_t SH_FLD_MCE_SYMBOL0_COUNT_LEN = 9589; // 2 -const static uint64_t SH_FLD_MCE_SYMBOL1_COUNT = 9590; // 2 -const static uint64_t SH_FLD_MCE_SYMBOL1_COUNT_LEN = 9591; // 2 -const static uint64_t SH_FLD_MCE_SYMBOL2_COUNT = 9592; // 2 -const static uint64_t SH_FLD_MCE_SYMBOL2_COUNT_LEN = 9593; // 2 -const static uint64_t SH_FLD_MCE_SYMBOL3_COUNT = 9594; // 2 -const static uint64_t SH_FLD_MCE_SYMBOL3_COUNT_LEN = 9595; // 2 -const static uint64_t SH_FLD_MCMODE0_64B_WR_IS_PWRT = 9596; // 4 -const static uint64_t SH_FLD_MCPERF1_DISABLE_FASTPATH_QOS = 9597; // 4 -const static uint64_t SH_FLD_MCS_RESET_KEEPER = 9598; // 4 -const static uint64_t SH_FLD_MCS_WAT = 9599; // 4 -const static uint64_t SH_FLD_MC_CHANNELS_PER_GROUP = 9600; // 4 -const static uint64_t SH_FLD_MC_CHANNELS_PER_GROUP_LEN = 9601; // 4 -const static uint64_t SH_FLD_MC_FP_MATE_CMD_ERR0 = 9602; // 12 -const static uint64_t SH_FLD_MC_FP_MATE_CMD_ERR1 = 9603; // 12 -const static uint64_t SH_FLD_MC_INTERNAL_NONRECOVERABLE_ERROR = 9604; // 4 -const static uint64_t SH_FLD_MC_INTERNAL_RECOVERABLE_ERROR = 9605; // 4 -const static uint64_t SH_FLD_MC_TC_0_FIR_HOST_ATTN = 9606; // 2 -const static uint64_t SH_FLD_MC_TC_1_FIR_HOST_ATTN = 9607; // 2 -const static uint64_t SH_FLD_MC_TC_2_FIR_HOST_ATTN = 9608; // 2 -const static uint64_t SH_FLD_MC_TC_3_FIR_HOST_ATTN = 9609; // 2 -const static uint64_t SH_FLD_MC_TC_4_FIR_HOST_ATTN = 9610; // 2 -const static uint64_t SH_FLD_MC_TC_5_FIR_HOST_ATTN = 9611; // 2 -const static uint64_t SH_FLD_MC_TC_6_FIR_HOST_ATTN = 9612; // 2 -const static uint64_t SH_FLD_MC_TC_7_FIR_HOST_ATTN = 9613; // 2 -const static uint64_t SH_FLD_MD5_LATENCY_CFG = 9614; // 1 -const static uint64_t SH_FLD_MDI_0 = 9615; // 8 -const static uint64_t SH_FLD_MDI_1 = 9616; // 8 -const static uint64_t SH_FLD_MED_IDLE_COUNT = 9617; // 8 -const static uint64_t SH_FLD_MED_IDLE_COUNT_LEN = 9618; // 8 -const static uint64_t SH_FLD_MED_IDLE_THRESHOLD = 9619; // 8 -const static uint64_t SH_FLD_MED_IDLE_THRESHOLD_LEN = 9620; // 8 -const static uint64_t SH_FLD_MEM = 9621; // 26 -const static uint64_t SH_FLD_MEMCTL_CIC_FAST = 9622; // 8 -const static uint64_t SH_FLD_MEMCTL_CTRN_IGNORE = 9623; // 8 -const static uint64_t SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP = 9624; // 4 -const static uint64_t SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN = 9625; // 4 -const static uint64_t SH_FLD_MEMORY_TYPE = 9626; // 8 -const static uint64_t SH_FLD_MEMORY_TYPE_LEN = 9627; // 8 -const static uint64_t SH_FLD_MEM_ADDR = 9628; // 21 -const static uint64_t SH_FLD_MEM_ADDR_LEN = 9629; // 21 -const static uint64_t SH_FLD_MEM_BUSY = 9630; // 21 -const static uint64_t SH_FLD_MEM_BYTE_ENABLE = 9631; // 21 -const static uint64_t SH_FLD_MEM_BYTE_ENABLE_LEN = 9632; // 21 -const static uint64_t SH_FLD_MEM_DATAOP_PENDING = 9633; // 21 -const static uint64_t SH_FLD_MEM_ERROR = 9634; // 21 -const static uint64_t SH_FLD_MEM_ERROR_LEN = 9635; // 21 -const static uint64_t SH_FLD_MEM_HIGH_PRIORITY = 9636; // 4 -const static uint64_t SH_FLD_MEM_HIGH_PRIORITY_LEN = 9637; // 4 -const static uint64_t SH_FLD_MEM_IFETCH_PENDING = 9638; // 21 -const static uint64_t SH_FLD_MEM_IMPRECISE_ERROR_PENDING = 9639; // 21 -const static uint64_t SH_FLD_MEM_LEN = 9640; // 26 -const static uint64_t SH_FLD_MEM_LINE_MODE = 9641; // 21 -const static uint64_t SH_FLD_MEM_LOW_PRIORITY = 9642; // 4 -const static uint64_t SH_FLD_MEM_LOW_PRIORITY_LEN = 9643; // 4 -const static uint64_t SH_FLD_MEM_R_NW = 9644; // 21 -const static uint64_t SH_FLD_MEM_SIZE = 9645; // 6 -const static uint64_t SH_FLD_MEM_SIZE_LEN = 9646; // 6 -const static uint64_t SH_FLD_MERGE_CAPACITY_LIMIT = 9647; // 8 -const static uint64_t SH_FLD_MERGE_CAPACITY_LIMIT_LEN = 9648; // 8 -const static uint64_t SH_FLD_MGR_CREDIT = 9649; // 3 -const static uint64_t SH_FLD_MGR_CREDIT_LEN = 9650; // 3 -const static uint64_t SH_FLD_MIB_GPIO = 9651; // 13 -const static uint64_t SH_FLD_MIB_GPIO_LEN = 9652; // 13 -const static uint64_t SH_FLD_MID_CARE_MASK = 9653; // 4 -const static uint64_t SH_FLD_MID_CARE_MASK_LEN = 9654; // 4 -const static uint64_t SH_FLD_MID_MATCH_VALUE = 9655; // 4 -const static uint64_t SH_FLD_MID_MATCH_VALUE_LEN = 9656; // 4 -const static uint64_t SH_FLD_MINCYCLECNT = 9657; // 3 -const static uint64_t SH_FLD_MINCYCLECNT_LEN = 9658; // 3 -const static uint64_t SH_FLD_MINIKERF = 9659; // 2 -const static uint64_t SH_FLD_MINIKERF_LEN = 9660; // 2 -const static uint64_t SH_FLD_MIN_CYCLE_SAMPLE = 9661; // 12 -const static uint64_t SH_FLD_MIN_CYCLE_SAMPLE_LEN = 9662; // 12 -const static uint64_t SH_FLD_MIN_EYE_HEIGHT = 9663; // 6 -const static uint64_t SH_FLD_MIN_EYE_HEIGHT_LEN = 9664; // 6 -const static uint64_t SH_FLD_MIN_EYE_WIDTH = 9665; // 6 -const static uint64_t SH_FLD_MIN_EYE_WIDTH_LEN = 9666; // 6 -const static uint64_t SH_FLD_MIRROR_ACTION_OCCURRED = 9667; // 4 -const static uint64_t SH_FLD_MISC = 9668; // 10 -const static uint64_t SH_FLD_MISC_CFG = 9669; // 6 -const static uint64_t SH_FLD_MISC_CFG_LEN = 9670; // 6 -const static uint64_t SH_FLD_MISC_CTL_4VS64 = 9671; // 1 -const static uint64_t SH_FLD_MISC_CTL_ACCEPT_PASTE = 9672; // 1 -const static uint64_t SH_FLD_MISC_CTL_CAM_LOCATION = 9673; // 1 -const static uint64_t SH_FLD_MISC_CTL_CAM_LOCATION_LEN = 9674; // 1 -const static uint64_t SH_FLD_MISC_CTL_CQ_IS_IDLE = 9675; // 1 -const static uint64_t SH_FLD_MISC_CTL_EG_IS_IDLE = 9676; // 1 -const static uint64_t SH_FLD_MISC_CTL_ENABLE_WRMON = 9677; // 1 -const static uint64_t SH_FLD_MISC_CTL_INVALIDATE_CAM_ALL = 9678; // 1 -const static uint64_t SH_FLD_MISC_CTL_INVALIDATE_CAM_LOC = 9679; // 1 -const static uint64_t SH_FLD_MISC_CTL_IN_IS_IDLE = 9680; // 1 -const static uint64_t SH_FLD_MISC_CTL_RG_IS_IDLE = 9681; // 1 -const static uint64_t SH_FLD_MISC_CTL_WC_IS_IDLE = 9682; // 1 -const static uint64_t SH_FLD_MISC_CTRL_PERR = 9683; // 1 -const static uint64_t SH_FLD_MISC_DA_ADDR_PERR = 9684; // 1 -const static uint64_t SH_FLD_MISC_INT_RA_PERR = 9685; // 1 -const static uint64_t SH_FLD_MISC_LEN = 9686; // 10 -const static uint64_t SH_FLD_MISC_NMMU_ERR = 9687; // 1 -const static uint64_t SH_FLD_MISC_RESYNC_OSC_FROM = 9688; // 1 -const static uint64_t SH_FLD_MISC_RING_ERR = 9689; // 1 -const static uint64_t SH_FLD_MISC_SCOMSAT00_ERR = 9690; // 1 -const static uint64_t SH_FLD_MISC_SCOMSAT01_ERR = 9691; // 1 -const static uint64_t SH_FLD_MISR_A_VAL = 9692; // 43 -const static uint64_t SH_FLD_MISR_A_VAL_LEN = 9693; // 43 -const static uint64_t SH_FLD_MISR_B_VAL = 9694; // 43 -const static uint64_t SH_FLD_MISR_B_VAL_LEN = 9695; // 43 -const static uint64_t SH_FLD_MISR_INIT_WAIT = 9696; // 43 -const static uint64_t SH_FLD_MISR_INIT_WAIT_LEN = 9697; // 43 -const static uint64_t SH_FLD_MISR_MODE = 9698; // 43 -const static uint64_t SH_FLD_MLC_ACCESS_ERR_ESR = 9699; // 1 -const static uint64_t SH_FLD_MMIOSD = 9700; // 1 -const static uint64_t SH_FLD_MMIO_BAR_PE = 9701; // 1 -const static uint64_t SH_FLD_MMIO_CTL_ACTYPE = 9702; // 1 -const static uint64_t SH_FLD_MMIO_CTL_COMP = 9703; // 1 -const static uint64_t SH_FLD_MMIO_CTL_INIT = 9704; // 1 -const static uint64_t SH_FLD_MMIO_CTL_OFFSET = 9705; // 1 -const static uint64_t SH_FLD_MMIO_CTL_OFFSET_LEN = 9706; // 1 -const static uint64_t SH_FLD_MMIO_CTL_OPTYPE = 9707; // 1 -const static uint64_t SH_FLD_MMIO_CTL_UNUSED = 9708; // 1 -const static uint64_t SH_FLD_MMIO_CTL_UNUSED_LEN = 9709; // 1 -const static uint64_t SH_FLD_MMIO_CTL_WINID = 9710; // 1 -const static uint64_t SH_FLD_MMIO_CTL_WINID_LEN = 9711; // 1 -const static uint64_t SH_FLD_MMIO_HYP_RD_ADDR_ERR = 9712; // 2 -const static uint64_t SH_FLD_MMIO_HYP_WR_ADDR_ERR = 9713; // 2 -const static uint64_t SH_FLD_MMIO_NON8B_HYP_ERR = 9714; // 2 -const static uint64_t SH_FLD_MMIO_NON8B_OS_ERR = 9715; // 2 -const static uint64_t SH_FLD_MMIO_OS_RD_ADDR_ERR = 9716; // 2 -const static uint64_t SH_FLD_MMIO_OS_WR_ADDR_ERR = 9717; // 2 -const static uint64_t SH_FLD_MMR = 9718; // 1 -const static uint64_t SH_FLD_MMR_LEN = 9719; // 1 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_00 = 9720; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_00_LEN = 9721; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_01 = 9722; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_01_LEN = 9723; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_02 = 9724; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_02_LEN = 9725; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_03 = 9726; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_03_LEN = 9727; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_04 = 9728; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_04_LEN = 9729; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_05 = 9730; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_05_LEN = 9731; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_06 = 9732; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_06_LEN = 9733; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_07 = 9734; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_07_LEN = 9735; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_08 = 9736; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_08_LEN = 9737; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_09 = 9738; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_09_LEN = 9739; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_10 = 9740; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_10_LEN = 9741; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_11 = 9742; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_11_LEN = 9743; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_12 = 9744; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_12_LEN = 9745; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_13 = 9746; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_13_LEN = 9747; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_14 = 9748; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_14_LEN = 9749; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_15 = 9750; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_15_LEN = 9751; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_16 = 9752; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_16_LEN = 9753; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_17 = 9754; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_17_LEN = 9755; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_18 = 9756; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_18_LEN = 9757; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_19 = 9758; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_19_LEN = 9759; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_20 = 9760; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_20_LEN = 9761; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_21 = 9762; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_21_LEN = 9763; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_22 = 9764; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_22_LEN = 9765; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_23 = 9766; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_23_LEN = 9767; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_24 = 9768; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_24_LEN = 9769; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_25 = 9770; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_25_LEN = 9771; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_26 = 9772; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_26_LEN = 9773; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_27 = 9774; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_27_LEN = 9775; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_28 = 9776; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_28_LEN = 9777; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_29 = 9778; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_29_LEN = 9779; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_30 = 9780; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_30_LEN = 9781; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_31 = 9782; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_31_LEN = 9783; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_32 = 9784; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_32_LEN = 9785; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_33 = 9786; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_33_LEN = 9787; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_34 = 9788; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_34_LEN = 9789; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_35 = 9790; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_35_LEN = 9791; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_36 = 9792; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_36_LEN = 9793; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_37 = 9794; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_37_LEN = 9795; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_38 = 9796; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_38_LEN = 9797; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_39 = 9798; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_39_LEN = 9799; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_40 = 9800; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_40_LEN = 9801; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_41 = 9802; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_41_LEN = 9803; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_42 = 9804; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_42_LEN = 9805; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_43 = 9806; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_43_LEN = 9807; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_44 = 9808; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_44_LEN = 9809; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_45 = 9810; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_45_LEN = 9811; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_46 = 9812; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_46_LEN = 9813; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_47 = 9814; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_47_LEN = 9815; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_48 = 9816; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_48_LEN = 9817; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_49 = 9818; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_49_LEN = 9819; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_50 = 9820; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_50_LEN = 9821; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_51 = 9822; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_51_LEN = 9823; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_52 = 9824; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_52_LEN = 9825; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_53 = 9826; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_53_LEN = 9827; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_54 = 9828; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_54_LEN = 9829; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_55 = 9830; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_55_LEN = 9831; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_56 = 9832; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_56_LEN = 9833; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_57 = 9834; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_57_LEN = 9835; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_58 = 9836; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_58_LEN = 9837; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_59 = 9838; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_59_LEN = 9839; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_60 = 9840; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_60_LEN = 9841; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_61 = 9842; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_61_LEN = 9843; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_62 = 9844; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_62_LEN = 9845; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_63 = 9846; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_63_LEN = 9847; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_64 = 9848; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_64_LEN = 9849; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_65 = 9850; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_65_LEN = 9851; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_66 = 9852; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_66_LEN = 9853; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_67 = 9854; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_67_LEN = 9855; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_68 = 9856; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_68_LEN = 9857; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_69 = 9858; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_69_LEN = 9859; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_70 = 9860; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_70_LEN = 9861; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_71 = 9862; // 2 -const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_71_LEN = 9863; // 2 -const static uint64_t SH_FLD_MODE = 9864; // 150 -const static uint64_t SH_FLD_MODE_128K_VP = 9865; // 1 -const static uint64_t SH_FLD_MODE_LEN = 9866; // 148 -const static uint64_t SH_FLD_MODE_REGISTER_0_VALUE = 9867; // 64 -const static uint64_t SH_FLD_MODE_REGISTER_0_VALUE_LEN = 9868; // 64 -const static uint64_t SH_FLD_MODE_REGISTER_1_VALUE = 9869; // 64 -const static uint64_t SH_FLD_MODE_REGISTER_1_VALUE_LEN = 9870; // 64 -const static uint64_t SH_FLD_MODE_REGISTER_2_VALUE = 9871; // 64 -const static uint64_t SH_FLD_MODE_REGISTER_2_VALUE_LEN = 9872; // 64 -const static uint64_t SH_FLD_MODE_REGISTER_3_VALUE = 9873; // 64 -const static uint64_t SH_FLD_MODE_REGISTER_3_VALUE_LEN = 9874; // 64 -const static uint64_t SH_FLD_MODE_SEL = 9875; // 12 -const static uint64_t SH_FLD_MON = 9876; // 12 -const static uint64_t SH_FLD_MON_LEN = 9877; // 12 -const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS = 9878; // 1 -const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS_ENABLE = 9879; // 1 -const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS_LEN = 9880; // 1 -const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ID = 9881; // 1 -const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ID_LEN = 9882; // 1 -const static uint64_t SH_FLD_MOVE_TO_TB_ON_2X_SYNC_ENABLE = 9883; // 1 -const static uint64_t SH_FLD_MPR_PATTERN_BIT = 9884; // 8 -const static uint64_t SH_FLD_MPSS_DIS = 9885; // 1 -const static uint64_t SH_FLD_MPW1 = 9886; // 43 -const static uint64_t SH_FLD_MPW2 = 9887; // 43 -const static uint64_t SH_FLD_MPW3 = 9888; // 43 -const static uint64_t SH_FLD_MRG_BBRD_NBUF = 9889; // 3 -const static uint64_t SH_FLD_MRG_BBRD_NBUF_LEN = 9890; // 3 -const static uint64_t SH_FLD_MRG_CR_DIS = 9891; // 3 -const static uint64_t SH_FLD_MRG_CTLW_CR_DIS = 9892; // 3 -const static uint64_t SH_FLD_MRG_IBRD_NBUF = 9893; // 3 -const static uint64_t SH_FLD_MRG_IBRD_NBUF_LEN = 9894; // 3 -const static uint64_t SH_FLD_MRG_IBWR_NBUF = 9895; // 3 -const static uint64_t SH_FLD_MRG_IBWR_NBUF_LEN = 9896; // 3 -const static uint64_t SH_FLD_MRG_OBRD_NBUF = 9897; // 3 -const static uint64_t SH_FLD_MRG_OBRD_NBUF_LEN = 9898; // 3 -const static uint64_t SH_FLD_MRG_PBTX_NBUF = 9899; // 3 -const static uint64_t SH_FLD_MRG_PBTX_NBUF_LEN = 9900; // 3 -const static uint64_t SH_FLD_MRG_RDBF_NBUF = 9901; // 3 -const static uint64_t SH_FLD_MRG_RDBF_NBUF_LEN = 9902; // 3 -const static uint64_t SH_FLD_MRS_CMD_DQ_OFF = 9903; // 8 -const static uint64_t SH_FLD_MRS_CMD_DQ_OFF_LEN = 9904; // 8 -const static uint64_t SH_FLD_MRS_CMD_DQ_ON = 9905; // 8 -const static uint64_t SH_FLD_MRS_CMD_DQ_ON_LEN = 9906; // 8 -const static uint64_t SH_FLD_MR_MASK_EN = 9907; // 8 -const static uint64_t SH_FLD_MR_MASK_EN_LEN = 9908; // 8 -const static uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1 = 9909; // 1 -const static uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1_LEN = 9910; // 1 -const static uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2 = 9911; // 1 -const static uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2_LEN = 9912; // 1 -const static uint64_t SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_1 = 9913; // 1 -const static uint64_t SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_2 = 9914; // 1 -const static uint64_t SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_1 = 9915; // 1 -const static uint64_t SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_2 = 9916; // 1 -const static uint64_t SH_FLD_MSADES_READ_EMPTY_PIB_1 = 9917; // 1 -const static uint64_t SH_FLD_MSADES_READ_EMPTY_PIB_2 = 9918; // 1 -const static uint64_t SH_FLD_MSADES_UNUSED_15_12 = 9919; // 1 -const static uint64_t SH_FLD_MSADES_UNUSED_15_12_LEN = 9920; // 1 -const static uint64_t SH_FLD_MSADES_UNUSED_31_28 = 9921; // 1 -const static uint64_t SH_FLD_MSADES_UNUSED_31_28_LEN = 9922; // 1 -const static uint64_t SH_FLD_MSADES_WRITE_FULL_PIB_1 = 9923; // 1 -const static uint64_t SH_FLD_MSADES_WRITE_FULL_PIB_2 = 9924; // 1 -const static uint64_t SH_FLD_MSADI_PIB_ERROR_1 = 9925; // 1 -const static uint64_t SH_FLD_MSADI_PIB_ERROR_2 = 9926; // 1 -const static uint64_t SH_FLD_MSADI_PIB_PENDING_1 = 9927; // 1 -const static uint64_t SH_FLD_MSADI_PIB_PENDING_2 = 9928; // 1 -const static uint64_t SH_FLD_MSADI_UNUSED_31_11 = 9929; // 4 -const static uint64_t SH_FLD_MSADI_UNUSED_31_11_LEN = 9930; // 4 -const static uint64_t SH_FLD_MSADI_UNUSED_7_3 = 9931; // 1 -const static uint64_t SH_FLD_MSADI_UNUSED_7_3_LEN = 9932; // 1 -const static uint64_t SH_FLD_MSADI_XUP_1 = 9933; // 1 -const static uint64_t SH_FLD_MSADI_XUP_2 = 9934; // 1 -const static uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1 = 9935; // 1 -const static uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1_LEN = 9936; // 1 -const static uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2 = 9937; // 1 -const static uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2_LEN = 9938; // 1 -const static uint64_t SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_1 = 9939; // 1 -const static uint64_t SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_2 = 9940; // 1 -const static uint64_t SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_1 = 9941; // 1 -const static uint64_t SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_2 = 9942; // 1 -const static uint64_t SH_FLD_MSBDES_READ_EMPTY_PIB_A_1 = 9943; // 1 -const static uint64_t SH_FLD_MSBDES_READ_EMPTY_PIB_A_2 = 9944; // 1 -const static uint64_t SH_FLD_MSBDES_UNUSED_17_12 = 9945; // 1 -const static uint64_t SH_FLD_MSBDES_UNUSED_17_12_LEN = 9946; // 1 -const static uint64_t SH_FLD_MSBDES_UNUSED_1_0 = 9947; // 2 -const static uint64_t SH_FLD_MSBDES_UNUSED_1_0_LEN = 9948; // 2 -const static uint64_t SH_FLD_MSBDES_UNUSED_31_28 = 9949; // 1 -const static uint64_t SH_FLD_MSBDES_UNUSED_31_28_LEN = 9950; // 1 -const static uint64_t SH_FLD_MSBDES_WRITE_FULL_PIB_A_1 = 9951; // 1 -const static uint64_t SH_FLD_MSBDES_WRITE_FULL_PIB_A_2 = 9952; // 1 -const static uint64_t SH_FLD_MSBDIM1_ENABLE_ABORT = 9953; // 1 -const static uint64_t SH_FLD_MSBDIM1_ENABLE_ABORT_2 = 9954; // 1 -const static uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR = 9955; // 1 -const static uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR_2 = 9956; // 1 -const static uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING = 9957; // 1 -const static uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING_2 = 9958; // 1 -const static uint64_t SH_FLD_MSBDIM1_ENABLE_XDN = 9959; // 1 -const static uint64_t SH_FLD_MSBDIM1_ENABLE_XDN_2 = 9960; // 1 -const static uint64_t SH_FLD_MSBDI_LBUS_ERROR_1 = 9961; // 1 -const static uint64_t SH_FLD_MSBDI_LBUS_ERROR_2 = 9962; // 1 -const static uint64_t SH_FLD_MSBDI_LBUS_PENDING_1 = 9963; // 1 -const static uint64_t SH_FLD_MSBDI_LBUS_PENDING_2 = 9964; // 1 -const static uint64_t SH_FLD_MSBDI_XDN_1 = 9965; // 1 -const static uint64_t SH_FLD_MSBDI_XDN_2 = 9966; // 1 -const static uint64_t SH_FLD_MSBSWAP = 9967; // 4 -const static uint64_t SH_FLD_MSC_BUS0_STG1_SEL = 9968; // 1 -const static uint64_t SH_FLD_MSC_BUS0_STG2_SEL = 9969; // 1 -const static uint64_t SH_FLD_MSC_BUS1_STG1_SEL = 9970; // 1 -const static uint64_t SH_FLD_MSC_BUS1_STG2_SEL = 9971; // 1 -const static uint64_t SH_FLD_MSG_ADDR_ERR = 9972; // 12 -const static uint64_t SH_FLD_MSK = 9973; // 5 -const static uint64_t SH_FLD_MSK_LEN = 9974; // 5 -const static uint64_t SH_FLD_MSM_CURR_STATE_0 = 9975; // 1 -const static uint64_t SH_FLD_MSM_CURR_STATE_0_LEN = 9976; // 1 -const static uint64_t SH_FLD_MSM_CURR_STATE_1 = 9977; // 1 -const static uint64_t SH_FLD_MSM_CURR_STATE_1_LEN = 9978; // 1 -const static uint64_t SH_FLD_MSM_CURR_STATE_2 = 9979; // 1 -const static uint64_t SH_FLD_MSM_CURR_STATE_2_LEN = 9980; // 1 -const static uint64_t SH_FLD_MSM_CURR_STATE_3 = 9981; // 1 -const static uint64_t SH_FLD_MSM_CURR_STATE_3_LEN = 9982; // 1 -const static uint64_t SH_FLD_MSR_DR = 9983; // 256 -const static uint64_t SH_FLD_MSR_HV = 9984; // 256 -const static uint64_t SH_FLD_MSR_PR = 9985; // 256 -const static uint64_t SH_FLD_MSR_SF = 9986; // 256 -const static uint64_t SH_FLD_MSR_TA = 9987; // 256 -const static uint64_t SH_FLD_MSR_US = 9988; // 256 -const static uint64_t SH_FLD_MSR_UV = 9989; // 256 -const static uint64_t SH_FLD_MST_DIS_ABUSPAREN = 9990; // 1 -const static uint64_t SH_FLD_MST_DIS_BEPAREN = 9991; // 1 -const static uint64_t SH_FLD_MST_DIS_RDDBUSPAR = 9992; // 1 -const static uint64_t SH_FLD_MST_DIS_WRDBUSPAREN = 9993; // 1 -const static uint64_t SH_FLD_MST_SPARE = 9994; // 1 -const static uint64_t SH_FLD_MS_GROUP_CHIP = 9995; // 2 -const static uint64_t SH_FLD_MS_GROUP_CHIP_LEN = 9996; // 2 -const static uint64_t SH_FLD_MULTICAST1 = 9997; // 43 -const static uint64_t SH_FLD_MULTICAST1_LEN = 9998; // 43 -const static uint64_t SH_FLD_MULTICAST2 = 9999; // 43 -const static uint64_t SH_FLD_MULTICAST2_LEN = 10000; // 43 -const static uint64_t SH_FLD_MULTICAST3 = 10001; // 43 -const static uint64_t SH_FLD_MULTICAST3_LEN = 10002; // 43 -const static uint64_t SH_FLD_MULTICAST4 = 10003; // 43 -const static uint64_t SH_FLD_MULTICAST4_LEN = 10004; // 43 -const static uint64_t SH_FLD_MULTICAST_COMPARE_REGISTER = 10005; // 2 -const static uint64_t SH_FLD_MULTICAST_COMPARE_REGISTER_LEN = 10006; // 2 -const static uint64_t SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER = 10007; // 1 -const static uint64_t SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER_LEN = 10008; // 1 -const static uint64_t SH_FLD_MULTIPLE_BAR = 10009; // 4 -const static uint64_t SH_FLD_MULTIPLE_DIR_ERRORS_DETECTED = 10010; // 12 -const static uint64_t SH_FLD_MULTIPLE_REQ = 10011; // 8 -const static uint64_t SH_FLD_MULTIPLE_REQ_SOURCE = 10012; // 8 -const static uint64_t SH_FLD_MULTIPLE_REQ_SOURCE_LEN = 10013; // 8 -const static uint64_t SH_FLD_MULT_REQ_ERR_MASK = 10014; // 8 -const static uint64_t SH_FLD_MUOP_ERROR_1 = 10015; // 4 -const static uint64_t SH_FLD_MUOP_ERROR_2 = 10016; // 4 -const static uint64_t SH_FLD_MUOP_ERROR_3 = 10017; // 4 -const static uint64_t SH_FLD_MUXEN = 10018; // 4 -const static uint64_t SH_FLD_MUXSEL = 10019; // 4 -const static uint64_t SH_FLD_MUXSEL_LEN = 10020; // 4 -const static uint64_t SH_FLD_M_0_STEP_ALIGN_FSM_STATE = 10021; // 1 -const static uint64_t SH_FLD_M_0_STEP_ALIGN_FSM_STATE_LEN = 10022; // 1 -const static uint64_t SH_FLD_M_1_STEP_ALIGN_FSM_STATE = 10023; // 1 -const static uint64_t SH_FLD_M_1_STEP_ALIGN_FSM_STATE_LEN = 10024; // 1 -const static uint64_t SH_FLD_M_CPS_ENABLE = 10025; // 1 -const static uint64_t SH_FLD_M_PATH_0_OSC_NOT_VALID = 10026; // 1 -const static uint64_t SH_FLD_M_PATH_0_PARITY = 10027; // 4 -const static uint64_t SH_FLD_M_PATH_0_STEP_ALIGN_THRESHOLD_ENABLE = 10028; // 1 -const static uint64_t SH_FLD_M_PATH_0_STEP_ALIGN_VALID_SWITCH = 10029; // 1 -const static uint64_t SH_FLD_M_PATH_0_STEP_CHECK = 10030; // 4 -const static uint64_t SH_FLD_M_PATH_0_STEP_CHECK_VALID = 10031; // 1 -const static uint64_t SH_FLD_M_PATH_0_STEP_CREATE_THRESHOLD_ENABLE = 10032; // 1 -const static uint64_t SH_FLD_M_PATH_0_SYNC_CREATE_COUNTER_ENABLE = 10033; // 1 -const static uint64_t SH_FLD_M_PATH_1_OSC_NOT_VALID = 10034; // 1 -const static uint64_t SH_FLD_M_PATH_1_PARITY = 10035; // 4 -const static uint64_t SH_FLD_M_PATH_1_STEP_ALIGN_THRESHOLD_ENABLE = 10036; // 1 -const static uint64_t SH_FLD_M_PATH_1_STEP_ALIGN_VALID_SWITCH = 10037; // 1 -const static uint64_t SH_FLD_M_PATH_1_STEP_CHECK = 10038; // 4 -const static uint64_t SH_FLD_M_PATH_1_STEP_CHECK_VALID = 10039; // 1 -const static uint64_t SH_FLD_M_PATH_1_STEP_CREATE_THRESHOLD_ENABLE = 10040; // 1 -const static uint64_t SH_FLD_M_PATH_1_SYNC_CREATE_COUNTER_ENABLE = 10041; // 1 -const static uint64_t SH_FLD_M_PATH_CLOCK_OFF_ENABLE = 10042; // 1 -const static uint64_t SH_FLD_M_PATH_SELECT = 10043; // 1 -const static uint64_t SH_FLD_M_PATH_SWITCH_TRIGGER = 10044; // 1 -const static uint64_t SH_FLD_NACK_RECEIVED_ERROR_0 = 10045; // 2 -const static uint64_t SH_FLD_NACK_RECEIVED_ERROR_1 = 10046; // 2 -const static uint64_t SH_FLD_NACK_RECEIVED_ERROR_2 = 10047; // 2 -const static uint64_t SH_FLD_NACK_RECEIVED_ERROR_3 = 10048; // 2 -const static uint64_t SH_FLD_NB_CLEAN_SLOT = 10049; // 6 -const static uint64_t SH_FLD_NB_CLEAN_SLOT_LEN = 10050; // 6 -const static uint64_t SH_FLD_NB_WRITE_SLOT = 10051; // 6 -const static uint64_t SH_FLD_NB_WRITE_SLOT_LEN = 10052; // 6 -const static uint64_t SH_FLD_NCU_POWERBUS_DATA_TIMEOUT = 10053; // 12 -const static uint64_t SH_FLD_NCU_PURGE = 10054; // 12 -const static uint64_t SH_FLD_NCU_PURGE_ABORT = 10055; // 12 -const static uint64_t SH_FLD_NCU_PURGE_DONE = 10056; // 24 -const static uint64_t SH_FLD_NCU_TLBIE_QUIESCE = 10057; // 12 -const static uint64_t SH_FLD_NDLMUX_BRK0TO2 = 10058; // 1 -const static uint64_t SH_FLD_NDLMUX_BRK0TO2_LEN = 10059; // 1 -const static uint64_t SH_FLD_NDL_BRK0_NOSTALL = 10060; // 1 -const static uint64_t SH_FLD_NDL_BRK0_STALL = 10061; // 1 -const static uint64_t SH_FLD_NDL_BRK1_NOSTALL = 10062; // 1 -const static uint64_t SH_FLD_NDL_BRK1_STALL = 10063; // 1 -const static uint64_t SH_FLD_NDL_BRK2_NOSTALL = 10064; // 1 -const static uint64_t SH_FLD_NDL_BRK2_STALL = 10065; // 1 -const static uint64_t SH_FLD_NDL_BRK3_NOSTALL = 10066; // 1 -const static uint64_t SH_FLD_NDL_BRK3_STALL = 10067; // 1 -const static uint64_t SH_FLD_NDL_BRK4_NOSTALL = 10068; // 1 -const static uint64_t SH_FLD_NDL_BRK4_STALL = 10069; // 1 -const static uint64_t SH_FLD_NDL_BRK5_NOSTALL = 10070; // 1 -const static uint64_t SH_FLD_NDL_BRK5_STALL = 10071; // 1 -const static uint64_t SH_FLD_NDL_PRI_PARITY_ENA = 10072; // 6 -const static uint64_t SH_FLD_NDL_RX_PARITY_ENA = 10073; // 6 -const static uint64_t SH_FLD_NDL_TX_PARITY_ENA = 10074; // 6 -const static uint64_t SH_FLD_NEAR_NODAL_EPSILON = 10075; // 8 -const static uint64_t SH_FLD_NEAR_NODAL_EPSILON_LEN = 10076; // 8 -const static uint64_t SH_FLD_NEST_DBG_SEL_IN = 10077; // 8 -const static uint64_t SH_FLD_NEST_DBG_SEL_WRT = 10078; // 8 -const static uint64_t SH_FLD_NEXT_RANK = 10079; // 8 -const static uint64_t SH_FLD_NEXT_RANK_LEN = 10080; // 8 -const static uint64_t SH_FLD_NEXT_RANK_PAIR = 10081; // 8 -const static uint64_t SH_FLD_NEXT_RANK_PAIR_LEN = 10082; // 8 -const static uint64_t SH_FLD_NFIRACTION0 = 10083; // 9 -const static uint64_t SH_FLD_NFIRACTION0_LEN = 10084; // 9 -const static uint64_t SH_FLD_NFIRACTION1 = 10085; // 9 -const static uint64_t SH_FLD_NFIRACTION1_LEN = 10086; // 9 -const static uint64_t SH_FLD_NMMU_LOCAL_XSTOP = 10087; // 1 -const static uint64_t SH_FLD_NONBAR_PE = 10088; // 9 -const static uint64_t SH_FLD_NONBAR_PE_MASK = 10089; // 9 -const static uint64_t SH_FLD_NONRD_ARE_ERRORS = 10090; // 9 -const static uint64_t SH_FLD_NONRD_ARE_ERRORS_MASK = 10091; // 9 -const static uint64_t SH_FLD_NONSLS_CNTR_TAP_PTS = 10092; // 4 -const static uint64_t SH_FLD_NONSLS_CNTR_TAP_PTS_LEN = 10093; // 4 -const static uint64_t SH_FLD_NONZERO_CSB_CC = 10094; // 1 -const static uint64_t SH_FLD_NOTIFY_FAILED_ERR = 10095; // 2 -const static uint64_t SH_FLD_NOT_USED_0 = 10096; // 1 -const static uint64_t SH_FLD_NOT_USED_0_LEN = 10097; // 1 -const static uint64_t SH_FLD_NOT_USED_1 = 10098; // 1 -const static uint64_t SH_FLD_NOT_USED_1_LEN = 10099; // 1 -const static uint64_t SH_FLD_NOT_USED_2 = 10100; // 1 -const static uint64_t SH_FLD_NOT_USED_2_LEN = 10101; // 1 -const static uint64_t SH_FLD_NOT_USED_3 = 10102; // 1 -const static uint64_t SH_FLD_NOT_USED_3_LEN = 10103; // 1 -const static uint64_t SH_FLD_NO_WAIT_ON_CLK_CMD = 10104; // 43 -const static uint64_t SH_FLD_NR_OF_FRAMES = 10105; // 1 -const static uint64_t SH_FLD_NSEG_MAIN_EN = 10106; // 6 -const static uint64_t SH_FLD_NSEG_MAIN_EN_LEN = 10107; // 6 -const static uint64_t SH_FLD_NSEG_MARGINPD_EN = 10108; // 6 -const static uint64_t SH_FLD_NSEG_MARGINPD_EN_LEN = 10109; // 6 -const static uint64_t SH_FLD_NSEG_MARGINPU_EN = 10110; // 6 -const static uint64_t SH_FLD_NSEG_MARGINPU_EN_LEN = 10111; // 6 -const static uint64_t SH_FLD_NSEG_POST_EN = 10112; // 2 -const static uint64_t SH_FLD_NSEG_POST_EN_LEN = 10113; // 2 -const static uint64_t SH_FLD_NSEG_POST_SEL = 10114; // 2 -const static uint64_t SH_FLD_NSEG_POST_SEL_LEN = 10115; // 2 -const static uint64_t SH_FLD_NSEG_PRE_EN = 10116; // 6 -const static uint64_t SH_FLD_NSEG_PRE_EN_LEN = 10117; // 6 -const static uint64_t SH_FLD_NSEG_PRE_SEL = 10118; // 6 -const static uint64_t SH_FLD_NSEG_PRE_SEL_LEN = 10119; // 6 -const static uint64_t SH_FLD_NSL_FILL_COUNT = 10120; // 43 -const static uint64_t SH_FLD_NSL_FILL_COUNT_LEN = 10121; // 43 -const static uint64_t SH_FLD_NTLR_PAUSE_THRESH = 10122; // 3 -const static uint64_t SH_FLD_NTLR_PAUSE_THRESH_LEN = 10123; // 3 -const static uint64_t SH_FLD_NTLW_PAUSE_THRESH = 10124; // 3 -const static uint64_t SH_FLD_NTLW_PAUSE_THRESH_LEN = 10125; // 3 -const static uint64_t SH_FLD_NTL_0 = 10126; // 36 -const static uint64_t SH_FLD_NTL_1 = 10127; // 36 -const static uint64_t SH_FLD_NTL_10 = 10128; // 36 -const static uint64_t SH_FLD_NTL_11 = 10129; // 36 -const static uint64_t SH_FLD_NTL_12 = 10130; // 36 -const static uint64_t SH_FLD_NTL_13 = 10131; // 36 -const static uint64_t SH_FLD_NTL_14 = 10132; // 36 -const static uint64_t SH_FLD_NTL_15 = 10133; // 36 -const static uint64_t SH_FLD_NTL_16 = 10134; // 36 -const static uint64_t SH_FLD_NTL_17 = 10135; // 36 -const static uint64_t SH_FLD_NTL_18 = 10136; // 36 -const static uint64_t SH_FLD_NTL_19 = 10137; // 36 -const static uint64_t SH_FLD_NTL_2 = 10138; // 36 -const static uint64_t SH_FLD_NTL_20 = 10139; // 36 -const static uint64_t SH_FLD_NTL_21 = 10140; // 36 -const static uint64_t SH_FLD_NTL_22 = 10141; // 36 -const static uint64_t SH_FLD_NTL_23 = 10142; // 36 -const static uint64_t SH_FLD_NTL_24 = 10143; // 36 -const static uint64_t SH_FLD_NTL_25 = 10144; // 36 -const static uint64_t SH_FLD_NTL_26 = 10145; // 36 -const static uint64_t SH_FLD_NTL_27 = 10146; // 36 -const static uint64_t SH_FLD_NTL_28 = 10147; // 36 -const static uint64_t SH_FLD_NTL_29 = 10148; // 36 -const static uint64_t SH_FLD_NTL_3 = 10149; // 36 -const static uint64_t SH_FLD_NTL_30 = 10150; // 36 -const static uint64_t SH_FLD_NTL_31 = 10151; // 36 -const static uint64_t SH_FLD_NTL_32 = 10152; // 36 -const static uint64_t SH_FLD_NTL_33 = 10153; // 36 -const static uint64_t SH_FLD_NTL_34 = 10154; // 36 -const static uint64_t SH_FLD_NTL_35 = 10155; // 36 -const static uint64_t SH_FLD_NTL_36 = 10156; // 36 -const static uint64_t SH_FLD_NTL_37 = 10157; // 36 -const static uint64_t SH_FLD_NTL_38 = 10158; // 36 -const static uint64_t SH_FLD_NTL_39 = 10159; // 36 -const static uint64_t SH_FLD_NTL_4 = 10160; // 36 -const static uint64_t SH_FLD_NTL_40 = 10161; // 36 -const static uint64_t SH_FLD_NTL_41 = 10162; // 36 -const static uint64_t SH_FLD_NTL_42 = 10163; // 36 -const static uint64_t SH_FLD_NTL_43 = 10164; // 36 -const static uint64_t SH_FLD_NTL_44 = 10165; // 36 -const static uint64_t SH_FLD_NTL_45 = 10166; // 36 -const static uint64_t SH_FLD_NTL_46 = 10167; // 36 -const static uint64_t SH_FLD_NTL_47 = 10168; // 36 -const static uint64_t SH_FLD_NTL_48 = 10169; // 36 -const static uint64_t SH_FLD_NTL_49 = 10170; // 36 -const static uint64_t SH_FLD_NTL_5 = 10171; // 36 -const static uint64_t SH_FLD_NTL_50 = 10172; // 36 -const static uint64_t SH_FLD_NTL_51 = 10173; // 36 -const static uint64_t SH_FLD_NTL_52 = 10174; // 36 -const static uint64_t SH_FLD_NTL_53 = 10175; // 36 -const static uint64_t SH_FLD_NTL_54 = 10176; // 36 -const static uint64_t SH_FLD_NTL_55 = 10177; // 36 -const static uint64_t SH_FLD_NTL_56 = 10178; // 36 -const static uint64_t SH_FLD_NTL_57 = 10179; // 36 -const static uint64_t SH_FLD_NTL_58 = 10180; // 36 -const static uint64_t SH_FLD_NTL_59 = 10181; // 36 -const static uint64_t SH_FLD_NTL_6 = 10182; // 36 -const static uint64_t SH_FLD_NTL_60 = 10183; // 36 -const static uint64_t SH_FLD_NTL_61 = 10184; // 36 -const static uint64_t SH_FLD_NTL_62 = 10185; // 36 -const static uint64_t SH_FLD_NTL_63 = 10186; // 36 -const static uint64_t SH_FLD_NTL_7 = 10187; // 36 -const static uint64_t SH_FLD_NTL_8 = 10188; // 36 -const static uint64_t SH_FLD_NTL_9 = 10189; // 36 -const static uint64_t SH_FLD_NTL_ARRAY_CE = 10190; // 1 -const static uint64_t SH_FLD_NTL_ARRAY_DATA_UE = 10191; // 1 -const static uint64_t SH_FLD_NTL_ARRAY_HDR_UE = 10192; // 1 -const static uint64_t SH_FLD_NTL_LOGIC_ERR = 10193; // 1 -const static uint64_t SH_FLD_NTL_NVL_CONFIG_ERR = 10194; // 1 -const static uint64_t SH_FLD_NTL_NVL_CRC_ERR = 10195; // 1 -const static uint64_t SH_FLD_NTL_NVL_DATA_PERR = 10196; // 1 -const static uint64_t SH_FLD_NTL_NVL_FLIT_PERR = 10197; // 1 -const static uint64_t SH_FLD_NTL_NVL_PKT_MALFOR = 10198; // 1 -const static uint64_t SH_FLD_NTL_NVL_PKT_UNSUPPORTED = 10199; // 1 -const static uint64_t SH_FLD_NTL_PRI_ERR = 10200; // 1 -const static uint64_t SH_FLD_NTTM_MODE = 10201; // 2 -const static uint64_t SH_FLD_NTTM_RW_DATA_DLY = 10202; // 2 -const static uint64_t SH_FLD_NTTM_RW_DATA_DLY_LEN = 10203; // 2 -const static uint64_t SH_FLD_NULL_MSR_LP = 10204; // 46 -const static uint64_t SH_FLD_NULL_MSR_SIBRC = 10205; // 46 -const static uint64_t SH_FLD_NULL_MSR_SIBRC_LEN = 10206; // 46 -const static uint64_t SH_FLD_NULL_MSR_WE = 10207; // 46 -const static uint64_t SH_FLD_NUM_BLOCKS = 10208; // 12 -const static uint64_t SH_FLD_NUM_BLOCKS_LEN = 10209; // 12 -const static uint64_t SH_FLD_NUM_CL_ACTIVE = 10210; // 8 -const static uint64_t SH_FLD_NUM_CL_ACTIVE_LEN = 10211; // 8 -const static uint64_t SH_FLD_NUM_HA_RSVD = 10212; // 8 -const static uint64_t SH_FLD_NUM_HA_RSVD_LEN = 10213; // 8 -const static uint64_t SH_FLD_NUM_HA_RSVD_SEL = 10214; // 8 -const static uint64_t SH_FLD_NUM_HA_RSVD_SEL_LEN = 10215; // 8 -const static uint64_t SH_FLD_NUM_HPC_RD_RSVD = 10216; // 8 -const static uint64_t SH_FLD_NUM_HPC_RD_RSVD_LEN = 10217; // 8 -const static uint64_t SH_FLD_NUM_HTM_RSVD = 10218; // 8 -const static uint64_t SH_FLD_NUM_HTM_RSVD_LEN = 10219; // 8 -const static uint64_t SH_FLD_NUM_HTM_RSVD_SEL = 10220; // 8 -const static uint64_t SH_FLD_NUM_HTM_RSVD_SEL_LEN = 10221; // 8 -const static uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD = 10222; // 8 -const static uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_LEN = 10223; // 8 -const static uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_SEL = 10224; // 8 -const static uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_SEL_LEN = 10225; // 8 -const static uint64_t SH_FLD_NUM_VALID_SAMPLES = 10226; // 8 -const static uint64_t SH_FLD_NUM_VALID_SAMPLES_LEN = 10227; // 8 -const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_ACTION = 10228; // 1 -const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_ENABLE = 10229; // 1 -const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_SELECT = 10230; // 1 -const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_SELECT_LEN = 10231; // 1 -const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_TYPE = 10232; // 1 -const static uint64_t SH_FLD_NXCQ_INJECT_MODE = 10233; // 2 -const static uint64_t SH_FLD_NXCQ_INJECT_MODE_LEN = 10234; // 2 -const static uint64_t SH_FLD_NXCQ_INJECT_TYPE = 10235; // 2 -const static uint64_t SH_FLD_NXCQ_INJECT_TYPE_LEN = 10236; // 2 -const static uint64_t SH_FLD_NXCQ_PBCQ_ARRAY = 10237; // 2 -const static uint64_t SH_FLD_NXCQ_PBCQ_ARRAY_LEN = 10238; // 2 -const static uint64_t SH_FLD_NXCQ_PBCQ_INJECT_ENABLE = 10239; // 2 -const static uint64_t SH_FLD_NXCQ_RNG_INJECT_ACTION = 10240; // 1 -const static uint64_t SH_FLD_NXCQ_RNG_INJECT_ENABLE = 10241; // 1 -const static uint64_t SH_FLD_NXCQ_TRACE_CNTL = 10242; // 2 -const static uint64_t SH_FLD_NXCQ_TRACE_CNTL_LEN = 10243; // 2 -const static uint64_t SH_FLD_NXWR_CFG = 10244; // 1 -const static uint64_t SH_FLD_NXWR_CFG_LEN = 10245; // 1 -const static uint64_t SH_FLD_NXWR_DISABLE_CP = 10246; // 1 -const static uint64_t SH_FLD_NX_FREEZE_MODES = 10247; // 1 -const static uint64_t SH_FLD_NX_FREEZE_MODES_LEN = 10248; // 1 -const static uint64_t SH_FLD_NX_LOCAL_XSTOP = 10249; // 2 -const static uint64_t SH_FLD_O = 10250; // 1 -const static uint64_t SH_FLD_O2SCMD_A_N_RESERVED_0 = 10251; // 4 -const static uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_1 = 10252; // 4 -const static uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 = 10253; // 4 -const static uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN = 10254; // 4 -const static uint64_t SH_FLD_O2SST_A_N_RESERVED_1_4 = 10255; // 4 -const static uint64_t SH_FLD_O2SST_A_N_RESERVED_1_4_LEN = 10256; // 4 -const static uint64_t SH_FLD_O2SST_A_N_RESERVED_6 = 10257; // 4 -const static uint64_t SH_FLD_O2S_BRIDGE_ENABLE_A_N = 10258; // 4 -const static uint64_t SH_FLD_O2S_CLEAR_STICKY_BITS_A_N = 10259; // 4 -const static uint64_t SH_FLD_O2S_CLOCK_DIVIDER_A_N = 10260; // 4 -const static uint64_t SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN = 10261; // 4 -const static uint64_t SH_FLD_O2S_CPHA_A_N = 10262; // 4 -const static uint64_t SH_FLD_O2S_CPOL_A_N = 10263; // 4 -const static uint64_t SH_FLD_O2S_FRAME_SIZE_A_N = 10264; // 4 -const static uint64_t SH_FLD_O2S_FRAME_SIZE_A_N_LEN = 10265; // 4 -const static uint64_t SH_FLD_O2S_FSM_ERR_A_N = 10266; // 4 -const static uint64_t SH_FLD_O2S_INTER_FRAME_DELAY_A_N = 10267; // 4 -const static uint64_t SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN = 10268; // 4 -const static uint64_t SH_FLD_O2S_IN_COUNT1_A_N = 10269; // 4 -const static uint64_t SH_FLD_O2S_IN_COUNT1_A_N_LEN = 10270; // 4 -const static uint64_t SH_FLD_O2S_IN_COUNT2_A_N = 10271; // 4 -const static uint64_t SH_FLD_O2S_IN_COUNT2_A_N_LEN = 10272; // 4 -const static uint64_t SH_FLD_O2S_IN_DELAY1_A_N = 10273; // 4 -const static uint64_t SH_FLD_O2S_IN_DELAY1_A_N_LEN = 10274; // 4 -const static uint64_t SH_FLD_O2S_IN_DELAY2_A_N = 10275; // 4 -const static uint64_t SH_FLD_O2S_IN_DELAY2_A_N_LEN = 10276; // 4 -const static uint64_t SH_FLD_O2S_NR_OF_FRAMES_A_N = 10277; // 4 -const static uint64_t SH_FLD_O2S_ONGOING_A_N = 10278; // 4 -const static uint64_t SH_FLD_O2S_OUT_COUNT1_A_N = 10279; // 4 -const static uint64_t SH_FLD_O2S_OUT_COUNT1_A_N_LEN = 10280; // 4 -const static uint64_t SH_FLD_O2S_OUT_COUNT2_A_N = 10281; // 4 -const static uint64_t SH_FLD_O2S_OUT_COUNT2_A_N_LEN = 10282; // 4 -const static uint64_t SH_FLD_O2S_RDATA_A_N = 10283; // 4 -const static uint64_t SH_FLD_O2S_RDATA_A_N_LEN = 10284; // 4 -const static uint64_t SH_FLD_O2S_WDATA_A_N = 10285; // 4 -const static uint64_t SH_FLD_O2S_WDATA_A_N_LEN = 10286; // 4 -const static uint64_t SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N = 10287; // 4 -const static uint64_t SH_FLD_OBWR_MASK = 10288; // 3 -const static uint64_t SH_FLD_OBWR_MASK_LEN = 10289; // 3 -const static uint64_t SH_FLD_OCC_ACTION_SET = 10290; // 1 -const static uint64_t SH_FLD_OCC_ACTION_SET_LEN = 10291; // 1 -const static uint64_t SH_FLD_OCC_ERROR = 10292; // 1 -const static uint64_t SH_FLD_OCC_FLAGS = 10293; // 1 -const static uint64_t SH_FLD_OCC_FLAGS_LEN = 10294; // 1 -const static uint64_t SH_FLD_OCC_HEARTBEAT_COUNT = 10295; // 7 -const static uint64_t SH_FLD_OCC_HEARTBEAT_COUNT_LEN = 10296; // 7 -const static uint64_t SH_FLD_OCC_HEARTBEAT_EN = 10297; // 1 -const static uint64_t SH_FLD_OCC_HEARTBEAT_ENABLE = 10298; // 6 -const static uint64_t SH_FLD_OCC_HEARTBEAT_LOSS = 10299; // 6 -const static uint64_t SH_FLD_OCC_HEARTBEAT_LOST = 10300; // 12 -const static uint64_t SH_FLD_OCC_MALF_ALERT = 10301; // 1 -const static uint64_t SH_FLD_OCC_SCRATCH_N = 10302; // 3 -const static uint64_t SH_FLD_OCC_SCRATCH_N_LEN = 10303; // 3 -const static uint64_t SH_FLD_OCC_SPCL_TIMEOUT_ADDR = 10304; // 1 -const static uint64_t SH_FLD_OCC_SPCL_TIMEOUT_ADDR_LEN = 10305; // 1 -const static uint64_t SH_FLD_OCC_SPECIAL_WKUP = 10306; // 30 -const static uint64_t SH_FLD_OCC_STRM0_PULL = 10307; // 1 -const static uint64_t SH_FLD_OCC_STRM0_PUSH = 10308; // 1 -const static uint64_t SH_FLD_OCC_STRM1_PULL = 10309; // 1 -const static uint64_t SH_FLD_OCC_STRM1_PUSH = 10310; // 1 -const static uint64_t SH_FLD_OCC_STRM2_PULL = 10311; // 1 -const static uint64_t SH_FLD_OCC_STRM2_PUSH = 10312; // 1 -const static uint64_t SH_FLD_OCC_STRM3_PULL = 10313; // 1 -const static uint64_t SH_FLD_OCC_STRM3_PUSH = 10314; // 1 -const static uint64_t SH_FLD_OCC_TIMER0 = 10315; // 1 -const static uint64_t SH_FLD_OCC_TIMER1 = 10316; // 1 -const static uint64_t SH_FLD_OCC_TRACE_MUX_SEL = 10317; // 1 -const static uint64_t SH_FLD_OCC_TRACE_MUX_SEL_LEN = 10318; // 1 -const static uint64_t SH_FLD_OCICFG_RESERVED_20 = 10319; // 1 -const static uint64_t SH_FLD_OCICFG_RESERVED_23 = 10320; // 1 -const static uint64_t SH_FLD_OCISLV_FAIRNESS_MASK = 10321; // 1 -const static uint64_t SH_FLD_OCISLV_FAIRNESS_MASK_LEN = 10322; // 1 -const static uint64_t SH_FLD_OCISLV_REREQ_HANG_DIV = 10323; // 1 -const static uint64_t SH_FLD_OCISLV_REREQ_HANG_DIV_LEN = 10324; // 1 -const static uint64_t SH_FLD_OCI_APAR_ERR = 10325; // 1 -const static uint64_t SH_FLD_OCI_APAR_ERR_MASK = 10326; // 1 -const static uint64_t SH_FLD_OCI_ARB_RESET = 10327; // 1 -const static uint64_t SH_FLD_OCI_BAD_REG_ADDR = 10328; // 1 -const static uint64_t SH_FLD_OCI_BAD_REG_ADDR_MASK = 10329; // 1 -const static uint64_t SH_FLD_OCI_ERR_INJ_CE_UE = 10330; // 1 -const static uint64_t SH_FLD_OCI_ERR_INJ_DCU = 10331; // 1 -const static uint64_t SH_FLD_OCI_ERR_INJ_ICU = 10332; // 1 -const static uint64_t SH_FLD_OCI_ERR_INJ_SINGL_CONT = 10333; // 1 -const static uint64_t SH_FLD_OCI_HI_BUS_MODE = 10334; // 1 -const static uint64_t SH_FLD_OCI_M0_FLCK = 10335; // 1 -const static uint64_t SH_FLD_OCI_M0_OEAR_LOCK = 10336; // 1 -const static uint64_t SH_FLD_OCI_M0_RW_STATUS = 10337; // 1 -const static uint64_t SH_FLD_OCI_M0_TIMEOUT_ERROR = 10338; // 1 -const static uint64_t SH_FLD_OCI_M1_FLCK = 10339; // 1 -const static uint64_t SH_FLD_OCI_M1_OEAR_LOCK = 10340; // 1 -const static uint64_t SH_FLD_OCI_M1_RW_STATUS = 10341; // 1 -const static uint64_t SH_FLD_OCI_M1_TIMEOUT_ERROR = 10342; // 1 -const static uint64_t SH_FLD_OCI_M2_FLCK = 10343; // 1 -const static uint64_t SH_FLD_OCI_M2_OEAR_LOCK = 10344; // 1 -const static uint64_t SH_FLD_OCI_M2_RW_STATUS = 10345; // 1 -const static uint64_t SH_FLD_OCI_M2_TIMEOUT_ERROR = 10346; // 1 -const static uint64_t SH_FLD_OCI_M3_FLCK = 10347; // 1 -const static uint64_t SH_FLD_OCI_M3_OEAR_LOCK = 10348; // 1 -const static uint64_t SH_FLD_OCI_M3_RW_STATUS = 10349; // 1 -const static uint64_t SH_FLD_OCI_M3_TIMEOUT_ERROR = 10350; // 1 -const static uint64_t SH_FLD_OCI_M4_FLCK = 10351; // 1 -const static uint64_t SH_FLD_OCI_M4_OEAR_LOCK = 10352; // 1 -const static uint64_t SH_FLD_OCI_M4_RW_STATUS = 10353; // 1 -const static uint64_t SH_FLD_OCI_M4_TIMEOUT_ERROR = 10354; // 1 -const static uint64_t SH_FLD_OCI_M5_FLCK = 10355; // 1 -const static uint64_t SH_FLD_OCI_M5_OEAR_LOCK = 10356; // 1 -const static uint64_t SH_FLD_OCI_M5_RW_STATUS = 10357; // 1 -const static uint64_t SH_FLD_OCI_M5_TIMEOUT_ERROR = 10358; // 1 -const static uint64_t SH_FLD_OCI_M6_FLCK = 10359; // 1 -const static uint64_t SH_FLD_OCI_M6_OEAR_LOCK = 10360; // 1 -const static uint64_t SH_FLD_OCI_M6_RW_STATUS = 10361; // 1 -const static uint64_t SH_FLD_OCI_M6_TIMEOUT_ERROR = 10362; // 1 -const static uint64_t SH_FLD_OCI_M7_FLCK = 10363; // 1 -const static uint64_t SH_FLD_OCI_M7_OEAR_LOCK = 10364; // 1 -const static uint64_t SH_FLD_OCI_M7_RW_STATUS = 10365; // 1 -const static uint64_t SH_FLD_OCI_M7_TIMEOUT_ERROR = 10366; // 1 -const static uint64_t SH_FLD_OCI_MARKER_SPACE = 10367; // 1 -const static uint64_t SH_FLD_OCI_MARKER_SPACE_LEN = 10368; // 1 -const static uint64_t SH_FLD_OCI_PRIORITY_MODE = 10369; // 1 -const static uint64_t SH_FLD_OCI_PRIORITY_ORDER = 10370; // 1 -const static uint64_t SH_FLD_OCI_PRIORITY_ORDER_LEN = 10371; // 1 -const static uint64_t SH_FLD_OCI_READ_DATA_PARITY = 10372; // 4 -const static uint64_t SH_FLD_OCI_READ_PIPELINE_CONTROL = 10373; // 1 -const static uint64_t SH_FLD_OCI_READ_PIPELINE_CONTROL_LEN = 10374; // 1 -const static uint64_t SH_FLD_OCI_REGION = 10375; // 4 -const static uint64_t SH_FLD_OCI_REGION_LEN = 10376; // 4 -const static uint64_t SH_FLD_OCI_SLAVE_ERROR = 10377; // 4 -const static uint64_t SH_FLD_OCI_SLAVE_INIT = 10378; // 1 -const static uint64_t SH_FLD_OCI_SLAVE_INIT_MASK = 10379; // 1 -const static uint64_t SH_FLD_OCI_TIMEOUT = 10380; // 4 -const static uint64_t SH_FLD_OCI_TIMEOUT_ADDR = 10381; // 1 -const static uint64_t SH_FLD_OCI_TIMEOUT_ADDR_LEN = 10382; // 1 -const static uint64_t SH_FLD_OCI_TRACE_MUX_SEL = 10383; // 1 -const static uint64_t SH_FLD_OCI_TRACE_MUX_SEL_LEN = 10384; // 1 -const static uint64_t SH_FLD_OCI_WRITE_PIPELINE_CONTROL = 10385; // 1 -const static uint64_t SH_FLD_OCI_WRPAR_ERR = 10386; // 1 -const static uint64_t SH_FLD_OCI_WRPAR_ERR_MASK = 10387; // 1 -const static uint64_t SH_FLD_OCR_DBG_HALT = 10388; // 1 -const static uint64_t SH_FLD_OFFSET = 10389; // 10 -const static uint64_t SH_FLD_OFFSET_LEN = 10390; // 10 -const static uint64_t SH_FLD_OFF_INIT_CFG = 10391; // 6 -const static uint64_t SH_FLD_OFF_INIT_CFG_LEN = 10392; // 6 -const static uint64_t SH_FLD_OFF_INIT_TIMEOUT = 10393; // 6 -const static uint64_t SH_FLD_OFF_INIT_TIMEOUT_LEN = 10394; // 6 -const static uint64_t SH_FLD_OFF_RECAL_CFG = 10395; // 6 -const static uint64_t SH_FLD_OFF_RECAL_CFG_LEN = 10396; // 6 -const static uint64_t SH_FLD_OFF_RECAL_TIMEOUT = 10397; // 6 -const static uint64_t SH_FLD_OFF_RECAL_TIMEOUT_LEN = 10398; // 6 -const static uint64_t SH_FLD_OJCFG_DBG_HALT = 10399; // 1 -const static uint64_t SH_FLD_OJCFG_JTAG_SRC_SEL = 10400; // 1 -const static uint64_t SH_FLD_OJCFG_JTAG_TRST_B = 10401; // 1 -const static uint64_t SH_FLD_OJCFG_RUN_TCK = 10402; // 1 -const static uint64_t SH_FLD_OJCFG_TCK_WIDTH = 10403; // 1 -const static uint64_t SH_FLD_OJCFG_TCK_WIDTH_LEN = 10404; // 1 -const static uint64_t SH_FLD_OJIC_DO_DR = 10405; // 1 -const static uint64_t SH_FLD_OJIC_DO_IR = 10406; // 1 -const static uint64_t SH_FLD_OJIC_DO_TAP_RESET = 10407; // 1 -const static uint64_t SH_FLD_OJIC_JTAG_INSTR = 10408; // 1 -const static uint64_t SH_FLD_OJIC_JTAG_INSTR_LEN = 10409; // 1 -const static uint64_t SH_FLD_OJIC_WR_VALID = 10410; // 1 -const static uint64_t SH_FLD_OJSTAT_FSM_ERROR = 10411; // 1 -const static uint64_t SH_FLD_OJSTAT_INPROG_WR_ERR = 10412; // 1 -const static uint64_t SH_FLD_OJSTAT_IR_DR_EQ0_ERR = 10413; // 1 -const static uint64_t SH_FLD_OJSTAT_JTAG_INPROG = 10414; // 1 -const static uint64_t SH_FLD_OJSTAT_RUN_TCK_EQ0_ERR = 10415; // 1 -const static uint64_t SH_FLD_OJSTAT_SRC_SEL_EQ1_ERR = 10416; // 1 -const static uint64_t SH_FLD_OJSTAT_TRST_B_EQ0_ERR = 10417; // 1 -const static uint64_t SH_FLD_ONESHOT0 = 10418; // 15 -const static uint64_t SH_FLD_ONESHOT1 = 10419; // 15 -const static uint64_t SH_FLD_ONE_PPC = 10420; // 24 -const static uint64_t SH_FLD_ONGOING = 10421; // 1 -const static uint64_t SH_FLD_ONL = 10422; // 96 -const static uint64_t SH_FLD_OOB_MUX = 10423; // 1 -const static uint64_t SH_FLD_OPB_ERROR = 10424; // 4 -const static uint64_t SH_FLD_OPB_MASTER_HANG_TIMEOUT = 10425; // 4 -const static uint64_t SH_FLD_OPB_PARITY_ERROR = 10426; // 3 -const static uint64_t SH_FLD_OPB_TIMEOUT = 10427; // 4 -const static uint64_t SH_FLD_OPCG_IP = 10428; // 43 -const static uint64_t SH_FLD_OPCODE = 10429; // 1 -const static uint64_t SH_FLD_OPCODE_LEN = 10430; // 1 -const static uint64_t SH_FLD_OPER = 10431; // 1 -const static uint64_t SH_FLD_OPER_LEN = 10432; // 1 -const static uint64_t SH_FLD_OPTION_PIB_RESET = 10433; // 1 -const static uint64_t SH_FLD_OSCILLATOR = 10434; // 1 -const static uint64_t SH_FLD_OSCILLATOR_LEN = 10435; // 1 -const static uint64_t SH_FLD_OSCSWITCH_CNTL0_DC = 10436; // 1 -const static uint64_t SH_FLD_OSCSWITCH_CNTL0_DC_LEN = 10437; // 1 -const static uint64_t SH_FLD_OSCSWITCH_CNTL1_DC = 10438; // 1 -const static uint64_t SH_FLD_OSCSWITCH_CNTL1_DC_LEN = 10439; // 1 -const static uint64_t SH_FLD_OSCSWITCH_INTERRUPT = 10440; // 4 -const static uint64_t SH_FLD_OS_STATUS_DISABLE_A_N = 10441; // 96 -const static uint64_t SH_FLD_OTHER_SCOM_SAT = 10442; // 1 -const static uint64_t SH_FLD_OTP = 10443; // 1 -const static uint64_t SH_FLD_OTP_LEN = 10444; // 1 -const static uint64_t SH_FLD_OTR_SPECIAL_WKUP = 10445; // 30 -const static uint64_t SH_FLD_OUT = 10446; // 1 -const static uint64_t SH_FLD_OUTER_LOOP_CNT = 10447; // 8 -const static uint64_t SH_FLD_OUTER_LOOP_CNT_LEN = 10448; // 8 -const static uint64_t SH_FLD_OUTWR_INRD_ECC_CE = 10449; // 1 -const static uint64_t SH_FLD_OUTWR_INRD_ECC_SUE = 10450; // 1 -const static uint64_t SH_FLD_OUTWR_INRD_ECC_UE = 10451; // 1 -const static uint64_t SH_FLD_OUT_COUNT1 = 10452; // 1 -const static uint64_t SH_FLD_OUT_COUNT1_LEN = 10453; // 1 -const static uint64_t SH_FLD_OUT_COUNT2 = 10454; // 1 -const static uint64_t SH_FLD_OUT_COUNT2_LEN = 10455; // 1 -const static uint64_t SH_FLD_OUT_LEN = 10456; // 1 -const static uint64_t SH_FLD_OVERFLOW_ERR = 10457; // 43 -const static uint64_t SH_FLD_OVERFLOW_MASK = 10458; // 43 -const static uint64_t SH_FLD_OVERRIDE = 10459; // 8 -const static uint64_t SH_FLD_OVERRIDE_EN = 10460; // 24 -const static uint64_t SH_FLD_OVERRIDE_PBINIT_ERR_CMD = 10461; // 1 -const static uint64_t SH_FLD_OVERRIDE_PBINIT_HTM_CMD = 10462; // 1 -const static uint64_t SH_FLD_OVERRIDE_PBINIT_TOD_CMD = 10463; // 1 -const static uint64_t SH_FLD_OVERRIDE_PBINIT_TRACE_CMD = 10464; // 1 -const static uint64_t SH_FLD_OVERRIDE_PBINIT_XSCOM_CMD = 10465; // 1 -const static uint64_t SH_FLD_OVERRUN = 10466; // 8 -const static uint64_t SH_FLD_OVER_OR_UNDERRUN_ERR = 10467; // 1 -const static uint64_t SH_FLD_OVR_PM = 10468; // 1 -const static uint64_t SH_FLD_OWN_ID_THIS_SLAVE = 10469; // 2 -const static uint64_t SH_FLD_OWN_ID_THIS_SLAVE_LEN = 10470; // 2 -const static uint64_t SH_FLD_P0_IS_IDLE = 10471; // 3 -const static uint64_t SH_FLD_P1_IS_IDLE = 10472; // 3 -const static uint64_t SH_FLD_PACE = 10473; // 2 -const static uint64_t SH_FLD_PACE_LEN = 10474; // 2 -const static uint64_t SH_FLD_PACE_RATE = 10475; // 1 -const static uint64_t SH_FLD_PACE_RATE_LEN = 10476; // 1 -const static uint64_t SH_FLD_PACING_ALLOW = 10477; // 1 -const static uint64_t SH_FLD_PACING_ALLOW_0 = 10478; // 1 -const static uint64_t SH_FLD_PACING_ALLOW_1 = 10479; // 1 -const static uint64_t SH_FLD_PACING_ALLOW_2 = 10480; // 1 -const static uint64_t SH_FLD_PACING_ALLOW_3 = 10481; // 1 -const static uint64_t SH_FLD_PAGE_OFFSET_CFG = 10482; // 1 -const static uint64_t SH_FLD_PAGE_OFFSET_CFG_LEN = 10483; // 1 -const static uint64_t SH_FLD_PAGE_SIZE_64K = 10484; // 1 -const static uint64_t SH_FLD_PAGE_SIZE_64K_IC = 10485; // 1 -const static uint64_t SH_FLD_PAGE_SIZE_64K_PC = 10486; // 1 -const static uint64_t SH_FLD_PAGE_SIZE_64K_TM = 10487; // 1 -const static uint64_t SH_FLD_PAGE_SIZE_64K_VC = 10488; // 1 -const static uint64_t SH_FLD_PAIR0_QUA = 10489; // 8 -const static uint64_t SH_FLD_PAIR0_QUA_LEN = 10490; // 8 -const static uint64_t SH_FLD_PAIR0_QUA_V = 10491; // 8 -const static uint64_t SH_FLD_PAIR0_TER = 10492; // 8 -const static uint64_t SH_FLD_PAIR0_TER_LEN = 10493; // 8 -const static uint64_t SH_FLD_PAIR0_TER_V = 10494; // 8 -const static uint64_t SH_FLD_PAIR1_PRI = 10495; // 8 -const static uint64_t SH_FLD_PAIR1_PRI_LEN = 10496; // 8 -const static uint64_t SH_FLD_PAIR1_PRI_V = 10497; // 8 -const static uint64_t SH_FLD_PAIR1_QUA = 10498; // 8 -const static uint64_t SH_FLD_PAIR1_QUA_LEN = 10499; // 8 -const static uint64_t SH_FLD_PAIR1_QUA_V = 10500; // 8 -const static uint64_t SH_FLD_PAIR1_SEC = 10501; // 8 -const static uint64_t SH_FLD_PAIR1_SEC_LEN = 10502; // 8 -const static uint64_t SH_FLD_PAIR1_SEC_V = 10503; // 8 -const static uint64_t SH_FLD_PAIR1_TER = 10504; // 8 -const static uint64_t SH_FLD_PAIR1_TER_LEN = 10505; // 8 -const static uint64_t SH_FLD_PAIR1_TER_V = 10506; // 8 -const static uint64_t SH_FLD_PAIR2_PRI = 10507; // 8 -const static uint64_t SH_FLD_PAIR2_PRI_LEN = 10508; // 8 -const static uint64_t SH_FLD_PAIR2_PRI_V = 10509; // 8 -const static uint64_t SH_FLD_PAIR2_QUA = 10510; // 8 -const static uint64_t SH_FLD_PAIR2_QUA_LEN = 10511; // 8 -const static uint64_t SH_FLD_PAIR2_QUA_V = 10512; // 8 -const static uint64_t SH_FLD_PAIR2_SEC = 10513; // 8 -const static uint64_t SH_FLD_PAIR2_SEC_LEN = 10514; // 8 -const static uint64_t SH_FLD_PAIR2_SEC_V = 10515; // 8 -const static uint64_t SH_FLD_PAIR2_TER = 10516; // 8 -const static uint64_t SH_FLD_PAIR2_TER_LEN = 10517; // 8 -const static uint64_t SH_FLD_PAIR2_TER_V = 10518; // 8 -const static uint64_t SH_FLD_PAIR3_PRI = 10519; // 8 -const static uint64_t SH_FLD_PAIR3_PRI_LEN = 10520; // 8 -const static uint64_t SH_FLD_PAIR3_PRI_V = 10521; // 8 -const static uint64_t SH_FLD_PAIR3_SEC = 10522; // 8 -const static uint64_t SH_FLD_PAIR3_SEC_LEN = 10523; // 8 -const static uint64_t SH_FLD_PAIR3_SEC_V = 10524; // 8 -const static uint64_t SH_FLD_PARANOIA_TEST_ENABLE_CHANGE = 10525; // 43 -const static uint64_t SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE = 10526; // 43 -const static uint64_t SH_FLD_PARITY = 10527; // 45 -const static uint64_t SH_FLD_PARITY_CHECK = 10528; // 1 -const static uint64_t SH_FLD_PARITY_ERR = 10529; // 4 -const static uint64_t SH_FLD_PARITY_ERR2 = 10530; // 3 -const static uint64_t SH_FLD_PARITY_ERROR = 10531; // 51 -const static uint64_t SH_FLD_PARITY_ERROR_SUE_ENA = 10532; // 6 -const static uint64_t SH_FLD_PARSER00_ATTN = 10533; // 4 -const static uint64_t SH_FLD_PARSER01_ATTN = 10534; // 4 -const static uint64_t SH_FLD_PARSER02_ATTN = 10535; // 4 -const static uint64_t SH_FLD_PARSER03_ATTN = 10536; // 4 -const static uint64_t SH_FLD_PARSER04_ATTN = 10537; // 4 -const static uint64_t SH_FLD_PARSER05_ATTN = 10538; // 4 -const static uint64_t SH_FLD_PARSER06_ATTN = 10539; // 2 -const static uint64_t SH_FLD_PARSER07_ATTN = 10540; // 2 -const static uint64_t SH_FLD_PART_0 = 10541; // 2 -const static uint64_t SH_FLD_PART_0_LEN = 10542; // 2 -const static uint64_t SH_FLD_PART_1 = 10543; // 2 -const static uint64_t SH_FLD_PART_10 = 10544; // 2 -const static uint64_t SH_FLD_PART_10_LEN = 10545; // 2 -const static uint64_t SH_FLD_PART_11 = 10546; // 2 -const static uint64_t SH_FLD_PART_11_LEN = 10547; // 2 -const static uint64_t SH_FLD_PART_12 = 10548; // 2 -const static uint64_t SH_FLD_PART_12_LEN = 10549; // 2 -const static uint64_t SH_FLD_PART_13 = 10550; // 2 -const static uint64_t SH_FLD_PART_13_LEN = 10551; // 2 -const static uint64_t SH_FLD_PART_14 = 10552; // 2 -const static uint64_t SH_FLD_PART_14_LEN = 10553; // 2 -const static uint64_t SH_FLD_PART_15 = 10554; // 2 -const static uint64_t SH_FLD_PART_15_LEN = 10555; // 2 -const static uint64_t SH_FLD_PART_16 = 10556; // 2 -const static uint64_t SH_FLD_PART_16_LEN = 10557; // 2 -const static uint64_t SH_FLD_PART_17 = 10558; // 2 -const static uint64_t SH_FLD_PART_17_LEN = 10559; // 2 -const static uint64_t SH_FLD_PART_18 = 10560; // 2 -const static uint64_t SH_FLD_PART_18_LEN = 10561; // 2 -const static uint64_t SH_FLD_PART_19 = 10562; // 2 -const static uint64_t SH_FLD_PART_19_LEN = 10563; // 2 -const static uint64_t SH_FLD_PART_1_LEN = 10564; // 2 -const static uint64_t SH_FLD_PART_2 = 10565; // 2 -const static uint64_t SH_FLD_PART_20 = 10566; // 2 -const static uint64_t SH_FLD_PART_20_LEN = 10567; // 2 -const static uint64_t SH_FLD_PART_21 = 10568; // 2 -const static uint64_t SH_FLD_PART_21_LEN = 10569; // 2 -const static uint64_t SH_FLD_PART_22 = 10570; // 2 -const static uint64_t SH_FLD_PART_22_LEN = 10571; // 2 -const static uint64_t SH_FLD_PART_23 = 10572; // 2 -const static uint64_t SH_FLD_PART_23_LEN = 10573; // 2 -const static uint64_t SH_FLD_PART_24 = 10574; // 2 -const static uint64_t SH_FLD_PART_24_LEN = 10575; // 2 -const static uint64_t SH_FLD_PART_25 = 10576; // 2 -const static uint64_t SH_FLD_PART_25_LEN = 10577; // 2 -const static uint64_t SH_FLD_PART_26 = 10578; // 2 -const static uint64_t SH_FLD_PART_26_LEN = 10579; // 2 -const static uint64_t SH_FLD_PART_27 = 10580; // 2 -const static uint64_t SH_FLD_PART_27_LEN = 10581; // 2 -const static uint64_t SH_FLD_PART_28 = 10582; // 2 -const static uint64_t SH_FLD_PART_28_LEN = 10583; // 2 -const static uint64_t SH_FLD_PART_29 = 10584; // 2 -const static uint64_t SH_FLD_PART_29_LEN = 10585; // 2 -const static uint64_t SH_FLD_PART_2_LEN = 10586; // 2 -const static uint64_t SH_FLD_PART_3 = 10587; // 2 -const static uint64_t SH_FLD_PART_30 = 10588; // 2 -const static uint64_t SH_FLD_PART_30_LEN = 10589; // 2 -const static uint64_t SH_FLD_PART_31 = 10590; // 2 -const static uint64_t SH_FLD_PART_31_LEN = 10591; // 2 -const static uint64_t SH_FLD_PART_32 = 10592; // 2 -const static uint64_t SH_FLD_PART_32_LEN = 10593; // 2 -const static uint64_t SH_FLD_PART_33 = 10594; // 2 -const static uint64_t SH_FLD_PART_33_LEN = 10595; // 2 -const static uint64_t SH_FLD_PART_34 = 10596; // 2 -const static uint64_t SH_FLD_PART_34_LEN = 10597; // 2 -const static uint64_t SH_FLD_PART_35 = 10598; // 2 -const static uint64_t SH_FLD_PART_35_LEN = 10599; // 2 -const static uint64_t SH_FLD_PART_36 = 10600; // 2 -const static uint64_t SH_FLD_PART_36_LEN = 10601; // 2 -const static uint64_t SH_FLD_PART_37 = 10602; // 2 -const static uint64_t SH_FLD_PART_37_LEN = 10603; // 2 -const static uint64_t SH_FLD_PART_38 = 10604; // 2 -const static uint64_t SH_FLD_PART_38_LEN = 10605; // 2 -const static uint64_t SH_FLD_PART_39 = 10606; // 2 -const static uint64_t SH_FLD_PART_39_LEN = 10607; // 2 -const static uint64_t SH_FLD_PART_3_LEN = 10608; // 2 -const static uint64_t SH_FLD_PART_4 = 10609; // 2 -const static uint64_t SH_FLD_PART_40 = 10610; // 2 -const static uint64_t SH_FLD_PART_40_LEN = 10611; // 2 -const static uint64_t SH_FLD_PART_41 = 10612; // 2 -const static uint64_t SH_FLD_PART_41_LEN = 10613; // 2 -const static uint64_t SH_FLD_PART_42 = 10614; // 2 -const static uint64_t SH_FLD_PART_42_LEN = 10615; // 2 -const static uint64_t SH_FLD_PART_43 = 10616; // 2 -const static uint64_t SH_FLD_PART_43_LEN = 10617; // 2 -const static uint64_t SH_FLD_PART_44 = 10618; // 2 -const static uint64_t SH_FLD_PART_44_LEN = 10619; // 2 -const static uint64_t SH_FLD_PART_45 = 10620; // 2 -const static uint64_t SH_FLD_PART_45_LEN = 10621; // 2 -const static uint64_t SH_FLD_PART_46 = 10622; // 2 -const static uint64_t SH_FLD_PART_46_LEN = 10623; // 2 -const static uint64_t SH_FLD_PART_47 = 10624; // 2 -const static uint64_t SH_FLD_PART_47_LEN = 10625; // 2 -const static uint64_t SH_FLD_PART_48 = 10626; // 2 -const static uint64_t SH_FLD_PART_48_LEN = 10627; // 2 -const static uint64_t SH_FLD_PART_49 = 10628; // 2 -const static uint64_t SH_FLD_PART_49_LEN = 10629; // 2 -const static uint64_t SH_FLD_PART_4_LEN = 10630; // 2 -const static uint64_t SH_FLD_PART_5 = 10631; // 2 -const static uint64_t SH_FLD_PART_50 = 10632; // 2 -const static uint64_t SH_FLD_PART_50_LEN = 10633; // 2 -const static uint64_t SH_FLD_PART_51 = 10634; // 2 -const static uint64_t SH_FLD_PART_51_LEN = 10635; // 2 -const static uint64_t SH_FLD_PART_52 = 10636; // 2 -const static uint64_t SH_FLD_PART_52_LEN = 10637; // 2 -const static uint64_t SH_FLD_PART_53 = 10638; // 2 -const static uint64_t SH_FLD_PART_53_LEN = 10639; // 2 -const static uint64_t SH_FLD_PART_54 = 10640; // 2 -const static uint64_t SH_FLD_PART_54_LEN = 10641; // 2 -const static uint64_t SH_FLD_PART_55 = 10642; // 2 -const static uint64_t SH_FLD_PART_55_LEN = 10643; // 2 -const static uint64_t SH_FLD_PART_56 = 10644; // 2 -const static uint64_t SH_FLD_PART_56_LEN = 10645; // 2 -const static uint64_t SH_FLD_PART_57 = 10646; // 2 -const static uint64_t SH_FLD_PART_57_LEN = 10647; // 2 -const static uint64_t SH_FLD_PART_58 = 10648; // 2 -const static uint64_t SH_FLD_PART_58_LEN = 10649; // 2 -const static uint64_t SH_FLD_PART_59 = 10650; // 2 -const static uint64_t SH_FLD_PART_59_LEN = 10651; // 2 -const static uint64_t SH_FLD_PART_5_LEN = 10652; // 2 -const static uint64_t SH_FLD_PART_6 = 10653; // 2 -const static uint64_t SH_FLD_PART_60 = 10654; // 2 -const static uint64_t SH_FLD_PART_60_LEN = 10655; // 2 -const static uint64_t SH_FLD_PART_61 = 10656; // 2 -const static uint64_t SH_FLD_PART_61_LEN = 10657; // 2 -const static uint64_t SH_FLD_PART_62 = 10658; // 2 -const static uint64_t SH_FLD_PART_62_LEN = 10659; // 2 -const static uint64_t SH_FLD_PART_63 = 10660; // 2 -const static uint64_t SH_FLD_PART_63_LEN = 10661; // 2 -const static uint64_t SH_FLD_PART_6_LEN = 10662; // 2 -const static uint64_t SH_FLD_PART_7 = 10663; // 2 -const static uint64_t SH_FLD_PART_7_LEN = 10664; // 2 -const static uint64_t SH_FLD_PART_8 = 10665; // 2 -const static uint64_t SH_FLD_PART_8_LEN = 10666; // 2 -const static uint64_t SH_FLD_PART_9 = 10667; // 2 -const static uint64_t SH_FLD_PART_9_LEN = 10668; // 2 -const static uint64_t SH_FLD_PAR_17_MASK = 10669; // 8 -const static uint64_t SH_FLD_PAR_INVERT = 10670; // 8 -const static uint64_t SH_FLD_PASS_CQ_INT_PMU_DATA_HI = 10671; // 1 -const static uint64_t SH_FLD_PASS_CQ_INT_PMU_DATA_LO = 10672; // 1 -const static uint64_t SH_FLD_PASS_CQ_INT_TRACE_DATA_HI = 10673; // 1 -const static uint64_t SH_FLD_PASS_CQ_INT_TRACE_DATA_LO = 10674; // 1 -const static uint64_t SH_FLD_PASS_CQ_INT_TRACE_TRIG_01 = 10675; // 1 -const static uint64_t SH_FLD_PASS_CQ_INT_TRACE_TRIG_23 = 10676; // 1 -const static uint64_t SH_FLD_PASS_WC_INT_PMU_DATA_HI = 10677; // 1 -const static uint64_t SH_FLD_PASS_WC_INT_PMU_DATA_LO = 10678; // 1 -const static uint64_t SH_FLD_PASS_WC_INT_TRACE_DATA_HI = 10679; // 1 -const static uint64_t SH_FLD_PASS_WC_INT_TRACE_DATA_LO = 10680; // 1 -const static uint64_t SH_FLD_PASS_WC_INT_TRACE_TRIG_01 = 10681; // 1 -const static uint64_t SH_FLD_PASS_WC_INT_TRACE_TRIG_23 = 10682; // 1 -const static uint64_t SH_FLD_PASTE_ADDR_ALIGN = 10683; // 1 -const static uint64_t SH_FLD_PASTE_REJECT = 10684; // 1 -const static uint64_t SH_FLD_PATTERN_CHECK_EN = 10685; // 1 -const static uint64_t SH_FLD_PATTERN_SEL = 10686; // 2 -const static uint64_t SH_FLD_PATTERN_SEL_LEN = 10687; // 2 -const static uint64_t SH_FLD_PAYLOAD = 10688; // 1 -const static uint64_t SH_FLD_PAYLOAD_LEN = 10689; // 1 -const static uint64_t SH_FLD_PBASE = 10690; // 4 -const static uint64_t SH_FLD_PBASE_LEN = 10691; // 4 -const static uint64_t SH_FLD_PBAX_EN = 10692; // 1 -const static uint64_t SH_FLD_PBAX_OCC_PUSH0 = 10693; // 1 -const static uint64_t SH_FLD_PBAX_OCC_PUSH1 = 10694; // 1 -const static uint64_t SH_FLD_PBAX_OCC_SEND_ATTN = 10695; // 1 -const static uint64_t SH_FLD_PBA_BCDE_ATTN = 10696; // 1 -const static uint64_t SH_FLD_PBA_BCUE_ATTN = 10697; // 1 -const static uint64_t SH_FLD_PBA_ERROR = 10698; // 1 -const static uint64_t SH_FLD_PBA_REGION = 10699; // 1 -const static uint64_t SH_FLD_PBA_REGION_LEN = 10700; // 1 -const static uint64_t SH_FLD_PBCFG_0_EPSILON = 10701; // 1 -const static uint64_t SH_FLD_PBCFG_0_EPSILON_LEN = 10702; // 1 -const static uint64_t SH_FLD_PBCFG_0_HANG_NX_MAX_CNT = 10703; // 1 -const static uint64_t SH_FLD_PBCFG_0_HANG_NX_MAX_CNT_LEN = 10704; // 1 -const static uint64_t SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT = 10705; // 1 -const static uint64_t SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT_LEN = 10706; // 1 -const static uint64_t SH_FLD_PBCFG_0_UNUSED1 = 10707; // 1 -const static uint64_t SH_FLD_PBCFG_0_UNUSED1_LEN = 10708; // 1 -const static uint64_t SH_FLD_PBCFG_0_UNUSED2 = 10709; // 1 -const static uint64_t SH_FLD_PBCFG_0_UNUSED2_LEN = 10710; // 1 -const static uint64_t SH_FLD_PBCFG_0_UNUSED3 = 10711; // 1 -const static uint64_t SH_FLD_PBCFG_0_UNUSED3_LEN = 10712; // 1 -const static uint64_t SH_FLD_PBCFG_1_UNUSED1 = 10713; // 1 -const static uint64_t SH_FLD_PBCFG_1_UNUSED1_LEN = 10714; // 1 -const static uint64_t SH_FLD_PBCFG_1_UNUSED2 = 10715; // 1 -const static uint64_t SH_FLD_PBCFG_1_UNUSED2_LEN = 10716; // 1 -const static uint64_t SH_FLD_PBCQ_CNTRL_LOGIC_ERR = 10717; // 1 -const static uint64_t SH_FLD_PBDATA_HANG = 10718; // 1 -const static uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR0 = 10719; // 12 -const static uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR1 = 10720; // 12 -const static uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR2 = 10721; // 12 -const static uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR0 = 10722; // 12 -const static uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR1 = 10723; // 12 -const static uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR2 = 10724; // 12 -const static uint64_t SH_FLD_PBI_IDLE = 10725; // 1 -const static uint64_t SH_FLD_PBI_INTERNAL_HANG = 10726; // 1 -const static uint64_t SH_FLD_PBI_MUX_SELECT = 10727; // 1 -const static uint64_t SH_FLD_PBI_MUX_SELECT_LEN = 10728; // 1 -const static uint64_t SH_FLD_PBI_PE = 10729; // 2 -const static uint64_t SH_FLD_PBI_WRITE_IDLE = 10730; // 2 -const static uint64_t SH_FLD_PBREQ_BCE_MAX_PRIORITY = 10731; // 1 -const static uint64_t SH_FLD_PBREQ_DATA_HANG_DIV = 10732; // 1 -const static uint64_t SH_FLD_PBREQ_DATA_HANG_DIV_LEN = 10733; // 1 -const static uint64_t SH_FLD_PBREQ_DROP_PRIORITY_MASK = 10734; // 1 -const static uint64_t SH_FLD_PBREQ_DROP_PRIORITY_MASK_LEN = 10735; // 1 -const static uint64_t SH_FLD_PBREQ_EVENT_MUX = 10736; // 1 -const static uint64_t SH_FLD_PBREQ_EVENT_MUX_LEN = 10737; // 1 -const static uint64_t SH_FLD_PBREQ_EXIT_HANG_DIV = 10738; // 1 -const static uint64_t SH_FLD_PBREQ_EXIT_HANG_DIV_LEN = 10739; // 1 -const static uint64_t SH_FLD_PBREQ_EXIT_ON_HANG = 10740; // 1 -const static uint64_t SH_FLD_PBREQ_EXIT_ON_HANG_PBAX = 10741; // 1 -const static uint64_t SH_FLD_PBREQ_OPER_HANG_DIV = 10742; // 1 -const static uint64_t SH_FLD_PBREQ_OPER_HANG_DIV_LEN = 10743; // 1 -const static uint64_t SH_FLD_PBREQ_SLVFW_MAX_PRIORITY = 10744; // 1 -const static uint64_t SH_FLD_PBRX_MASK = 10745; // 3 -const static uint64_t SH_FLD_PBRX_MASK_LEN = 10746; // 3 -const static uint64_t SH_FLD_PBTX_AMO_IGNORE_XUE = 10747; // 3 -const static uint64_t SH_FLD_PBTX_DELAY_BDONE = 10748; // 3 -const static uint64_t SH_FLD_PBTX_FLIP_IMIN_BIG = 10749; // 3 -const static uint64_t SH_FLD_PBTX_FLIP_IMIN_LITTLE = 10750; // 3 -const static uint64_t SH_FLD_PBTX_REDUCE_RTAG = 10751; // 3 -const static uint64_t SH_FLD_PBUNSUPPORTEDCMD = 10752; // 9 -const static uint64_t SH_FLD_PBUNSUPPORTEDCMD_MASK = 10753; // 9 -const static uint64_t SH_FLD_PBUNSUPPORTEDSIZE = 10754; // 9 -const static uint64_t SH_FLD_PBUNSUPPORTEDSIZE_MASK = 10755; // 9 -const static uint64_t SH_FLD_PBUS_CMD_HANG = 10756; // 2 -const static uint64_t SH_FLD_PBUS_ECC_CE = 10757; // 2 -const static uint64_t SH_FLD_PBUS_ECC_SUE = 10758; // 2 -const static uint64_t SH_FLD_PBUS_ECC_UE = 10759; // 2 -const static uint64_t SH_FLD_PBUS_LINK_ABORT = 10760; // 2 -const static uint64_t SH_FLD_PBUS_LOAD_LINK_ERR = 10761; // 2 -const static uint64_t SH_FLD_PBUS_MISC_HW = 10762; // 2 -const static uint64_t SH_FLD_PBUS_READ_ARE = 10763; // 2 -const static uint64_t SH_FLD_PBUS_STORE_LINK_ERR = 10764; // 2 -const static uint64_t SH_FLD_PBUS_WRITE_ARE = 10765; // 2 -const static uint64_t SH_FLD_PBUS_XLAT_ECC_SUE = 10766; // 1 -const static uint64_t SH_FLD_PBUS_XLAT_ECC_UE = 10767; // 1 -const static uint64_t SH_FLD_PB_ACKDEAD_FW_RD = 10768; // 1 -const static uint64_t SH_FLD_PB_ACKDEAD_FW_RD_MASK = 10769; // 1 -const static uint64_t SH_FLD_PB_ACKDEAD_FW_WR = 10770; // 1 -const static uint64_t SH_FLD_PB_ACKDEAD_FW_WR_MASK = 10771; // 1 -const static uint64_t SH_FLD_PB_BADCRESP = 10772; // 1 -const static uint64_t SH_FLD_PB_BADCRESP_MASK = 10773; // 1 -const static uint64_t SH_FLD_PB_CE_FW = 10774; // 1 -const static uint64_t SH_FLD_PB_CE_FW_MASK = 10775; // 1 -const static uint64_t SH_FLD_PB_CMD_ERR = 10776; // 12 -const static uint64_t SH_FLD_PB_DATA_ERR = 10777; // 12 -const static uint64_t SH_FLD_PB_DATA_HANG_ERRORS = 10778; // 9 -const static uint64_t SH_FLD_PB_DATA_HANG_ERRORS_MASK = 10779; // 9 -const static uint64_t SH_FLD_PB_DATA_TIME_OUT = 10780; // 4 -const static uint64_t SH_FLD_PB_ECC_CE = 10781; // 1 -const static uint64_t SH_FLD_PB_ECC_ERR_CE = 10782; // 4 -const static uint64_t SH_FLD_PB_ECC_ERR_SUE = 10783; // 4 -const static uint64_t SH_FLD_PB_ECC_ERR_UE = 10784; // 4 -const static uint64_t SH_FLD_PB_ECC_SUE = 10785; // 1 -const static uint64_t SH_FLD_PB_ECC_UE = 10786; // 1 -const static uint64_t SH_FLD_PB_HANG_ERRORS = 10787; // 9 -const static uint64_t SH_FLD_PB_HANG_ERRORS_MASK = 10788; // 9 -const static uint64_t SH_FLD_PB_INTERFACE_PE = 10789; // 9 -const static uint64_t SH_FLD_PB_INTERFACE_PE_MASK = 10790; // 9 -const static uint64_t SH_FLD_PB_NOCI_EVENT_SEL = 10791; // 1 -const static uint64_t SH_FLD_PB_OFFSET = 10792; // 2 -const static uint64_t SH_FLD_PB_OFFSET_LEN = 10793; // 2 -const static uint64_t SH_FLD_PB_OPERTO = 10794; // 1 -const static uint64_t SH_FLD_PB_OPERTO_MASK = 10795; // 1 -const static uint64_t SH_FLD_PB_OP_HANG_ERR = 10796; // 1 -const static uint64_t SH_FLD_PB_PARITY_ERR = 10797; // 1 -const static uint64_t SH_FLD_PB_PARITY_ERROR = 10798; // 4 -const static uint64_t SH_FLD_PB_PARITY_ERR_MASK = 10799; // 1 -const static uint64_t SH_FLD_PB_PURGE_DONE_LVL = 10800; // 6 -const static uint64_t SH_FLD_PB_PURGE_PLS = 10801; // 6 -const static uint64_t SH_FLD_PB_RDADRERR_FW = 10802; // 1 -const static uint64_t SH_FLD_PB_RDADRERR_FW_MASK = 10803; // 1 -const static uint64_t SH_FLD_PB_RDDATATO_FW = 10804; // 1 -const static uint64_t SH_FLD_PB_RDDATATO_FW_MASK = 10805; // 1 -const static uint64_t SH_FLD_PB_STOP = 10806; // 1 -const static uint64_t SH_FLD_PB_SUE_FW = 10807; // 1 -const static uint64_t SH_FLD_PB_SUE_FW_MASK = 10808; // 1 -const static uint64_t SH_FLD_PB_TO_PEC_CE = 10809; // 9 -const static uint64_t SH_FLD_PB_TO_PEC_CE_MASK = 10810; // 9 -const static uint64_t SH_FLD_PB_TO_PEC_SUE = 10811; // 9 -const static uint64_t SH_FLD_PB_TO_PEC_SUE_MASK = 10812; // 9 -const static uint64_t SH_FLD_PB_TO_PEC_UE = 10813; // 9 -const static uint64_t SH_FLD_PB_TO_PEC_UE_MASK = 10814; // 9 -const static uint64_t SH_FLD_PB_UE_FW = 10815; // 1 -const static uint64_t SH_FLD_PB_UE_FW_MASK = 10816; // 1 -const static uint64_t SH_FLD_PB_UNEXPCRESP = 10817; // 1 -const static uint64_t SH_FLD_PB_UNEXPCRESP_MASK = 10818; // 1 -const static uint64_t SH_FLD_PB_UNEXPDATA = 10819; // 1 -const static uint64_t SH_FLD_PB_UNEXPDATA_MASK = 10820; // 1 -const static uint64_t SH_FLD_PB_WRADRERR_FW = 10821; // 1 -const static uint64_t SH_FLD_PB_WRADRERR_FW_MASK = 10822; // 1 -const static uint64_t SH_FLD_PB_XLAT_DATA_SUE = 10823; // 1 -const static uint64_t SH_FLD_PB_XLAT_DATA_UE = 10824; // 1 -const static uint64_t SH_FLD_PCB = 10825; // 3 -const static uint64_t SH_FLD_PCBMUX_GRANT_C0 = 10826; // 12 -const static uint64_t SH_FLD_PCBMUX_GRANT_C1 = 10827; // 12 -const static uint64_t SH_FLD_PCBMUX_REQ_C0 = 10828; // 12 -const static uint64_t SH_FLD_PCBMUX_REQ_C1 = 10829; // 12 -const static uint64_t SH_FLD_PCBQ_N_INFO = 10830; // 24 -const static uint64_t SH_FLD_PCBQ_N_INFO_LEN = 10831; // 24 -const static uint64_t SH_FLD_PCB_EP_RESET = 10832; // 43 -const static uint64_t SH_FLD_PCB_ERROR = 10833; // 43 -const static uint64_t SH_FLD_PCB_FSM = 10834; // 43 -const static uint64_t SH_FLD_PCB_IDLE = 10835; // 43 -const static uint64_t SH_FLD_PCB_INTERFACE = 10836; // 43 -const static uint64_t SH_FLD_PCB_INTERRUPT_PROTOCOL = 10837; // 30 -const static uint64_t SH_FLD_PCB_INTR_TYPE_A_CORE_N = 10838; // 144 -const static uint64_t SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN = 10839; // 144 -const static uint64_t SH_FLD_PCB_INTR_TYPE_A_QUAD_N = 10840; // 12 -const static uint64_t SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN = 10841; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_0 = 10842; // 8 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_1 = 10843; // 8 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_10 = 10844; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_11 = 10845; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_12 = 10846; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_13 = 10847; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_14 = 10848; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_15 = 10849; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_16 = 10850; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_17 = 10851; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_18 = 10852; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_19 = 10853; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_2 = 10854; // 8 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_20 = 10855; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_21 = 10856; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_22 = 10857; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_23 = 10858; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_3 = 10859; // 8 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_4 = 10860; // 8 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_5 = 10861; // 8 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_6 = 10862; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_7 = 10863; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_8 = 10864; // 6 -const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_9 = 10865; // 6 -const static uint64_t SH_FLD_PCB_LEN = 10866; // 2 -const static uint64_t SH_FLD_PCB_MASK = 10867; // 43 -const static uint64_t SH_FLD_PCB_REQUEST_SINCE_RESET = 10868; // 43 -const static uint64_t SH_FLD_PCB_RESET_DC = 10869; // 1 -const static uint64_t SH_FLD_PCB_TMP = 10870; // 1 -const static uint64_t SH_FLD_PCB_TMP_LEN = 10871; // 1 -const static uint64_t SH_FLD_PCC_CORE_INTF_QUIESCE_C0 = 10872; // 12 -const static uint64_t SH_FLD_PCC_CORE_INTF_QUIESCE_C1 = 10873; // 12 -const static uint64_t SH_FLD_PCI_CLOCK_ERROR = 10874; // 9 -const static uint64_t SH_FLD_PCI_CLOCK_ERROR_MASK = 10875; // 9 -const static uint64_t SH_FLD_PCI_HANG_ERROR = 10876; // 9 -const static uint64_t SH_FLD_PCI_HANG_ERROR_MASK = 10877; // 9 -const static uint64_t SH_FLD_PCLKDIFSEL = 10878; // 10 -const static uint64_t SH_FLD_PCLKOUTEN = 10879; // 3 -const static uint64_t SH_FLD_PCLKSEL = 10880; // 14 -const static uint64_t SH_FLD_PCLKSEL_LEN = 10881; // 14 -const static uint64_t SH_FLD_PC_BLOCK_INTERRUPTS_C0 = 10882; // 12 -const static uint64_t SH_FLD_PC_BLOCK_INTERRUPTS_C1 = 10883; // 12 -const static uint64_t SH_FLD_PC_CAL_PCFSM_1HOT = 10884; // 8 -const static uint64_t SH_FLD_PC_CAL_REFFSM_1HOT = 10885; // 8 -const static uint64_t SH_FLD_PC_ENTRY_ACK_C0 = 10886; // 12 -const static uint64_t SH_FLD_PC_ENTRY_ACK_C1 = 10887; // 12 -const static uint64_t SH_FLD_PC_ERR_STATUS0 = 10888; // 8 -const static uint64_t SH_FLD_PC_ERR_STATUS0_LEN = 10889; // 8 -const static uint64_t SH_FLD_PC_FUSED_CORE_MODE = 10890; // 24 -const static uint64_t SH_FLD_PC_INIT_CAL_ERR = 10891; // 8 -const static uint64_t SH_FLD_PC_INIT_CAL_ERR_LEN = 10892; // 8 -const static uint64_t SH_FLD_PC_INSTR_RUNNING_C0 = 10893; // 12 -const static uint64_t SH_FLD_PC_INSTR_RUNNING_C1 = 10894; // 12 -const static uint64_t SH_FLD_PC_INTR_PENDING_C0 = 10895; // 24 -const static uint64_t SH_FLD_PC_INTR_PENDING_C1 = 10896; // 24 -const static uint64_t SH_FLD_PC_NON_HV_RUNNING_C0 = 10897; // 12 -const static uint64_t SH_FLD_PC_NON_HV_RUNNING_C0_LEN = 10898; // 12 -const static uint64_t SH_FLD_PC_NON_HV_RUNNING_C1 = 10899; // 12 -const static uint64_t SH_FLD_PC_NON_HV_RUNNING_C1_LEN = 10900; // 12 -const static uint64_t SH_FLD_PC_PE = 10901; // 8 -const static uint64_t SH_FLD_PC_PM_STATE_ACTIVE_C0 = 10902; // 24 -const static uint64_t SH_FLD_PC_PM_STATE_ACTIVE_C1 = 10903; // 24 -const static uint64_t SH_FLD_PC_PRIORITY_LIMIT_0_3 = 10904; // 1 -const static uint64_t SH_FLD_PC_PRIORITY_LIMIT_0_3_LEN = 10905; // 1 -const static uint64_t SH_FLD_PC_SLICE_EN_ENC = 10906; // 1 -const static uint64_t SH_FLD_PC_SLICE_EN_ENC_LEN = 10907; // 1 -const static uint64_t SH_FLD_PC_TC_AVP_OUT = 10908; // 24 -const static uint64_t SH_FLD_PC_TC_VALID_NOT_HV_MODE = 10909; // 24 -const static uint64_t SH_FLD_PC_TEST = 10910; // 1 -const static uint64_t SH_FLD_PC_UNMASKED_ATTN_C0 = 10911; // 12 -const static uint64_t SH_FLD_PC_UNMASKED_ATTN_C1 = 10912; // 12 -const static uint64_t SH_FLD_PC_WAKEUP_C0 = 10913; // 12 -const static uint64_t SH_FLD_PC_WAKEUP_C1 = 10914; // 12 -const static uint64_t SH_FLD_PDWN = 10915; // 2 -const static uint64_t SH_FLD_PDWNPLL = 10916; // 6 -const static uint64_t SH_FLD_PDWNT = 10917; // 3 -const static uint64_t SH_FLD_PDWN_LITE = 10918; // 140 -const static uint64_t SH_FLD_PDWN_LITE_DISABLE = 10919; // 8 -const static uint64_t SH_FLD_PE = 10920; // 39 -const static uint64_t SH_FLD_PEAK_INIT_CFG = 10921; // 6 -const static uint64_t SH_FLD_PEAK_INIT_CFG_LEN = 10922; // 6 -const static uint64_t SH_FLD_PEAK_INIT_TIMEOUT = 10923; // 6 -const static uint64_t SH_FLD_PEAK_INIT_TIMEOUT_LEN = 10924; // 6 -const static uint64_t SH_FLD_PEAK_RECAL_CFG = 10925; // 6 -const static uint64_t SH_FLD_PEAK_RECAL_CFG_LEN = 10926; // 6 -const static uint64_t SH_FLD_PEAK_RECAL_TIMEOUT = 10927; // 6 -const static uint64_t SH_FLD_PEAK_RECAL_TIMEOUT_LEN = 10928; // 6 -const static uint64_t SH_FLD_PEAK_TUNE = 10929; // 4 -const static uint64_t SH_FLD_PECE_C_N_T0 = 10930; // 24 -const static uint64_t SH_FLD_PECE_C_N_T0_LEN = 10931; // 24 -const static uint64_t SH_FLD_PECE_C_N_T1 = 10932; // 24 -const static uint64_t SH_FLD_PECE_C_N_T1_LEN = 10933; // 24 -const static uint64_t SH_FLD_PECE_C_N_T2 = 10934; // 24 -const static uint64_t SH_FLD_PECE_C_N_T2_LEN = 10935; // 24 -const static uint64_t SH_FLD_PECE_C_N_T3 = 10936; // 24 -const static uint64_t SH_FLD_PECE_C_N_T3_LEN = 10937; // 24 -const static uint64_t SH_FLD_PECE_DECR = 10938; // 96 -const static uint64_t SH_FLD_PECE_DHDES = 10939; // 96 -const static uint64_t SH_FLD_PECE_DPDES = 10940; // 96 -const static uint64_t SH_FLD_PECE_HMAINT = 10941; // 96 -const static uint64_t SH_FLD_PECE_HYPV = 10942; // 96 -const static uint64_t SH_FLD_PECE_INTR_DISABLED = 10943; // 24 -const static uint64_t SH_FLD_PECE_OS_EXT = 10944; // 96 -const static uint64_t SH_FLD_PEC_SCOM_ERR = 10945; // 9 -const static uint64_t SH_FLD_PEC_SCOM_ERR_MASK = 10946; // 9 -const static uint64_t SH_FLD_PEEK_DATA1_0 = 10947; // 12 -const static uint64_t SH_FLD_PEEK_DATA1_0_LEN = 10948; // 12 -const static uint64_t SH_FLD_PEEK_DATA1_1 = 10949; // 12 -const static uint64_t SH_FLD_PEEK_DATA1_1_LEN = 10950; // 12 -const static uint64_t SH_FLD_PEEK_DATA1_2 = 10951; // 12 -const static uint64_t SH_FLD_PEEK_DATA1_2_LEN = 10952; // 12 -const static uint64_t SH_FLD_PEEK_DATA1_3 = 10953; // 12 -const static uint64_t SH_FLD_PEEK_DATA1_3_LEN = 10954; // 12 -const static uint64_t SH_FLD_PEND = 10955; // 8 -const static uint64_t SH_FLD_PENDING_SOURCE = 10956; // 30 -const static uint64_t SH_FLD_PENDING_SOURCE_LEN = 10957; // 30 -const static uint64_t SH_FLD_PERFORM_RDCLK_ALIGN = 10958; // 8 -const static uint64_t SH_FLD_PERIODIC = 10959; // 56 -const static uint64_t SH_FLD_PERIODIC_CAL_REQ_EN = 10960; // 8 -const static uint64_t SH_FLD_PERIODIC_LEN = 10961; // 56 -const static uint64_t SH_FLD_PERSIST = 10962; // 8 -const static uint64_t SH_FLD_PERSIST_LEN = 10963; // 8 -const static uint64_t SH_FLD_PERV = 10964; // 215 -const static uint64_t SH_FLD_PERVASIVE_CAPT = 10965; // 6 -const static uint64_t SH_FLD_PER_ABORT = 10966; // 8 -const static uint64_t SH_FLD_PER_DUTY_CYCLE_SW = 10967; // 8 -const static uint64_t SH_FLD_PER_REPEAT_COUNT = 10968; // 8 -const static uint64_t SH_FLD_PER_REPEAT_COUNT_LEN = 10969; // 8 -const static uint64_t SH_FLD_PE_ADR_BAR_MODE = 10970; // 3 -const static uint64_t SH_FLD_PE_BLOCK_CQPB_PB_INIT = 10971; // 3 -const static uint64_t SH_FLD_PE_CAPP = 10972; // 3 -const static uint64_t SH_FLD_PE_CAPP_256 = 10973; // 3 -const static uint64_t SH_FLD_PE_CAPP_DMA = 10974; // 3 -const static uint64_t SH_FLD_PE_CAPP_EN = 10975; // 3 -const static uint64_t SH_FLD_PE_CAPP_LEN = 10976; // 3 -const static uint64_t SH_FLD_PE_CAPP_P8_MODE = 10977; // 3 -const static uint64_t SH_FLD_PE_CHANNEL_STREAMING_EN = 10978; // 3 -const static uint64_t SH_FLD_PE_CQ_ECC_INJECT_ENABLE = 10979; // 3 -const static uint64_t SH_FLD_PE_CQ_PAR_INJECT_ENABLE = 10980; // 3 -const static uint64_t SH_FLD_PE_CQ_REGISTER_ARRAY = 10981; // 3 -const static uint64_t SH_FLD_PE_CQ_REGISTER_ARRAY_LEN = 10982; // 3 -const static uint64_t SH_FLD_PE_CQ_SRAM_ARRAY = 10983; // 3 -const static uint64_t SH_FLD_PE_CQ_SRAM_ARRAY_LEN = 10984; // 3 -const static uint64_t SH_FLD_PE_DISABLE_CQ_TCE_ARBITRATION = 10985; // 3 -const static uint64_t SH_FLD_PE_DISABLE_INJ_ON_RESEND = 10986; // 3 -const static uint64_t SH_FLD_PE_DISABLE_INTWR_SCOPE_GROUP = 10987; // 3 -const static uint64_t SH_FLD_PE_DISABLE_INTWR_SCOPE_NODE = 10988; // 3 -const static uint64_t SH_FLD_PE_DISABLE_INTWR_VG = 10989; // 3 -const static uint64_t SH_FLD_PE_DISABLE_MC_PREFETCH = 10990; // 3 -const static uint64_t SH_FLD_PE_DISABLE_OOO_MODE = 10991; // 3 -const static uint64_t SH_FLD_PE_DISABLE_PCI_CLK_CHECK = 10992; // 3 -const static uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_GROUP = 10993; // 3 -const static uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_NODAL = 10994; // 3 -const static uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_RNNN = 10995; // 3 -const static uint64_t SH_FLD_PE_DISABLE_RD_VG = 10996; // 3 -const static uint64_t SH_FLD_PE_DISABLE_TCE_ARBITRATION = 10997; // 3 -const static uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_GROUP = 10998; // 3 -const static uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_NODAL = 10999; // 3 -const static uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_RNNN = 11000; // 3 -const static uint64_t SH_FLD_PE_DISABLE_TCE_VG = 11001; // 3 -const static uint64_t SH_FLD_PE_DISABLE_WR_SCOPE_GROUP = 11002; // 3 -const static uint64_t SH_FLD_PE_DISABLE_WR_VG = 11003; // 3 -const static uint64_t SH_FLD_PE_DROPPACECOUNT = 11004; // 3 -const static uint64_t SH_FLD_PE_DROPPACECOUNT_LEN = 11005; // 3 -const static uint64_t SH_FLD_PE_DROPPACEINC = 11006; // 3 -const static uint64_t SH_FLD_PE_DROPPACEINC_LEN = 11007; // 3 -const static uint64_t SH_FLD_PE_DROPPRIORITYMASK = 11008; // 3 -const static uint64_t SH_FLD_PE_DROPPRIORITYMASK_LEN = 11009; // 3 -const static uint64_t SH_FLD_PE_ECC_INJECT_TYPE = 11010; // 3 -const static uint64_t SH_FLD_PE_ECC_INJECT_TYPE_LEN = 11011; // 3 -const static uint64_t SH_FLD_PE_EINJ_STACK = 11012; // 3 -const static uint64_t SH_FLD_PE_EINJ_STACK_LEN = 11013; // 3 -const static uint64_t SH_FLD_PE_ENABLENESTTRACE = 11014; // 3 -const static uint64_t SH_FLD_PE_ENABLE_CTAG_DROP_PRIORITY = 11015; // 3 -const static uint64_t SH_FLD_PE_ENABLE_DMAR_IOPACING = 11016; // 3 -const static uint64_t SH_FLD_PE_ENABLE_DMAW_IOPACING = 11017; // 3 -const static uint64_t SH_FLD_PE_ENABLE_ENH_FLOW = 11018; // 3 -const static uint64_t SH_FLD_PE_ENABLE_IO_CMD_PACING = 11019; // 3 -const static uint64_t SH_FLD_PE_ENABLE_NEW_FLOW_CACHE_INJECT = 11020; // 3 -const static uint64_t SH_FLD_PE_ENABLE_RD_SKIP_GROUP = 11021; // 3 -const static uint64_t SH_FLD_PE_ENABLE_TCE_SKIP_GROUP = 11022; // 3 -const static uint64_t SH_FLD_PE_ENHANCED_PEER2PEER_MODDE = 11023; // 9 -const static uint64_t SH_FLD_PE_ETU_RESET = 11024; // 9 -const static uint64_t SH_FLD_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW = 11025; // 3 -const static uint64_t SH_FLD_PE_HANG_SM_ON_ARE = 11026; // 3 -const static uint64_t SH_FLD_PE_IGNORE_SFSTAT = 11027; // 3 -const static uint64_t SH_FLD_PE_INBOUND_ACTIVE = 11028; // 9 -const static uint64_t SH_FLD_PE_ISMB_ERROR_INJECT = 11029; // 3 -const static uint64_t SH_FLD_PE_ISMB_ERROR_INJECT_LEN = 11030; // 3 -const static uint64_t SH_FLD_PE_LEN = 11031; // 39 -const static uint64_t SH_FLD_PE_LSI_BAR = 11032; // 9 -const static uint64_t SH_FLD_PE_LSI_BAR_EN = 11033; // 9 -const static uint64_t SH_FLD_PE_LSI_BAR_LEN = 11034; // 9 -const static uint64_t SH_FLD_PE_MASK0 = 11035; // 1 -const static uint64_t SH_FLD_PE_MASK1 = 11036; // 1 -const static uint64_t SH_FLD_PE_MATCH0 = 11037; // 1 -const static uint64_t SH_FLD_PE_MATCH0_LEN = 11038; // 1 -const static uint64_t SH_FLD_PE_MATCH1 = 11039; // 1 -const static uint64_t SH_FLD_PE_MATCH1_LEN = 11040; // 1 -const static uint64_t SH_FLD_PE_MMIO_BAR0 = 11041; // 9 -const static uint64_t SH_FLD_PE_MMIO_BAR0_EN = 11042; // 9 -const static uint64_t SH_FLD_PE_MMIO_BAR0_LEN = 11043; // 9 -const static uint64_t SH_FLD_PE_MMIO_BAR1 = 11044; // 9 -const static uint64_t SH_FLD_PE_MMIO_BAR1_EN = 11045; // 9 -const static uint64_t SH_FLD_PE_MMIO_BAR1_LEN = 11046; // 9 -const static uint64_t SH_FLD_PE_MMIO_MASK0 = 11047; // 9 -const static uint64_t SH_FLD_PE_MMIO_MASK0_LEN = 11048; // 9 -const static uint64_t SH_FLD_PE_MMIO_MASK1 = 11049; // 9 -const static uint64_t SH_FLD_PE_MMIO_MASK1_LEN = 11050; // 9 -const static uint64_t SH_FLD_PE_MSI_BAR = 11051; // 9 -const static uint64_t SH_FLD_PE_MSI_BAR_EN = 11052; // 9 -const static uint64_t SH_FLD_PE_MSI_BAR_LEN = 11053; // 9 -const static uint64_t SH_FLD_PE_NESTTRACESEL = 11054; // 3 -const static uint64_t SH_FLD_PE_NESTTRACESEL_LEN = 11055; // 3 -const static uint64_t SH_FLD_PE_OSMB_DATASTART_MODE = 11056; // 3 -const static uint64_t SH_FLD_PE_OSMB_DATASTART_MODE_LEN = 11057; // 3 -const static uint64_t SH_FLD_PE_OSMB_EARLYEMPTY_MODE = 11058; // 3 -const static uint64_t SH_FLD_PE_OSMB_EARLYEMPTY_MODE_LEN = 11059; // 3 -const static uint64_t SH_FLD_PE_OSMB_EARLY_START = 11060; // 3 -const static uint64_t SH_FLD_PE_OSMB_EARLY_START_LEN = 11061; // 3 -const static uint64_t SH_FLD_PE_OSMB_HOL_BLK_CNT = 11062; // 3 -const static uint64_t SH_FLD_PE_OSMB_HOL_BLK_CNT_LEN = 11063; // 3 -const static uint64_t SH_FLD_PE_OUTBOUND_ACTIVE = 11064; // 9 -const static uint64_t SH_FLD_PE_PCIE_CLK_TRACE_EN = 11065; // 3 -const static uint64_t SH_FLD_PE_PCI_CLK_TRACE_SEL = 11066; // 3 -const static uint64_t SH_FLD_PE_PCI_CLK_TRACE_SEL_LEN = 11067; // 3 -const static uint64_t SH_FLD_PE_PEER2PEER_MODDE = 11068; // 9 -const static uint64_t SH_FLD_PE_PERFMON_EN = 11069; // 3 -const static uint64_t SH_FLD_PE_PERFMON_EN_LEN = 11070; // 3 -const static uint64_t SH_FLD_PE_PERFMON_READ_TYPE = 11071; // 3 -const static uint64_t SH_FLD_PE_PERFMON_READ_TYPE_LEN = 11072; // 3 -const static uint64_t SH_FLD_PE_PHB_BAR = 11073; // 9 -const static uint64_t SH_FLD_PE_PHB_BAR_EN = 11074; // 9 -const static uint64_t SH_FLD_PE_PHB_BAR_LEN = 11075; // 9 -const static uint64_t SH_FLD_PE_PMON_MUX_BYTE0 = 11076; // 3 -const static uint64_t SH_FLD_PE_PMON_MUX_BYTE0_LEN = 11077; // 3 -const static uint64_t SH_FLD_PE_PMON_MUX_BYTE1 = 11078; // 3 -const static uint64_t SH_FLD_PE_PMON_MUX_BYTE1_LEN = 11079; // 3 -const static uint64_t SH_FLD_PE_PMON_MUX_BYTE2 = 11080; // 3 -const static uint64_t SH_FLD_PE_PMON_MUX_BYTE2_LEN = 11081; // 3 -const static uint64_t SH_FLD_PE_PMON_MUX_BYTE3 = 11082; // 3 -const static uint64_t SH_FLD_PE_PMON_MUX_BYTE3_LEN = 11083; // 3 -const static uint64_t SH_FLD_PE_QFIFO_HOLD_MODE = 11084; // 3 -const static uint64_t SH_FLD_PE_QFIFO_HOLD_MODE_LEN = 11085; // 3 -const static uint64_t SH_FLD_PE_RD_TIMEOUT_MASK = 11086; // 3 -const static uint64_t SH_FLD_PE_RD_TIMEOUT_MASK_LEN = 11087; // 3 -const static uint64_t SH_FLD_PE_RD_WRITE_ORDERING = 11088; // 3 -const static uint64_t SH_FLD_PE_RD_WRITE_ORDERING_LEN = 11089; // 3 -const static uint64_t SH_FLD_PE_RTYDROPDIVIDER = 11090; // 3 -const static uint64_t SH_FLD_PE_RTYDROPDIVIDER_LEN = 11091; // 3 -const static uint64_t SH_FLD_PE_SELECT_ETU_TRACE = 11092; // 3 -const static uint64_t SH_FLD_PE_STQ_ALLOCATION = 11093; // 3 -const static uint64_t SH_FLD_PE_TX_RESP_HWM = 11094; // 3 -const static uint64_t SH_FLD_PE_TX_RESP_HWM_LEN = 11095; // 3 -const static uint64_t SH_FLD_PE_TX_RESP_LWM = 11096; // 3 -const static uint64_t SH_FLD_PE_TX_RESP_LWM_LEN = 11097; // 3 -const static uint64_t SH_FLD_PE_WR_CACHE_INJECT_MODE = 11098; // 3 -const static uint64_t SH_FLD_PE_WR_CACHE_INJECT_MODE_LEN = 11099; // 3 -const static uint64_t SH_FLD_PE_WR_STRICT_ORDER_MODE = 11100; // 3 -const static uint64_t SH_FLD_PE_WR_TIMEOUT_MASK = 11101; // 3 -const static uint64_t SH_FLD_PE_WR_TIMEOUT_MASK_LEN = 11102; // 3 -const static uint64_t SH_FLD_PFD360SEL = 11103; // 4 -const static uint64_t SH_FLD_PFET_SEQ_PROGRAM = 11104; // 30 -const static uint64_t SH_FLD_PFREQ0 = 11105; // 15 -const static uint64_t SH_FLD_PFREQ0_LEN = 11106; // 15 -const static uint64_t SH_FLD_PFREQ1 = 11107; // 15 -const static uint64_t SH_FLD_PFREQ1_LEN = 11108; // 15 -const static uint64_t SH_FLD_PF_DROP_CNT_THRESH = 11109; // 4 -const static uint64_t SH_FLD_PF_DROP_CNT_THRESH_LEN = 11110; // 4 -const static uint64_t SH_FLD_PF_DROP_VALUE0 = 11111; // 8 -const static uint64_t SH_FLD_PF_DROP_VALUE0_LEN = 11112; // 8 -const static uint64_t SH_FLD_PF_DROP_VALUE1 = 11113; // 8 -const static uint64_t SH_FLD_PF_DROP_VALUE1_LEN = 11114; // 8 -const static uint64_t SH_FLD_PF_DROP_VALUE2 = 11115; // 8 -const static uint64_t SH_FLD_PF_DROP_VALUE2_LEN = 11116; // 8 -const static uint64_t SH_FLD_PF_DROP_VALUE3 = 11117; // 8 -const static uint64_t SH_FLD_PF_DROP_VALUE3_LEN = 11118; // 8 -const static uint64_t SH_FLD_PF_MACHINE_HANG_ERR = 11119; // 12 -const static uint64_t SH_FLD_PF_MACHINE_W4DT_HANG_ERR = 11120; // 12 -const static uint64_t SH_FLD_PF_PROMOTE_ERR_INJ = 11121; // 8 -const static uint64_t SH_FLD_PF_UNSOLICITED_CRESP_ERR = 11122; // 12 -const static uint64_t SH_FLD_PF_UNSOLICITED_CRESP_ERR_LEN = 11123; // 12 -const static uint64_t SH_FLD_PF_UNSOLICITED_DATA_ERR = 11124; // 12 -const static uint64_t SH_FLD_PGMIGR1_BAR = 11125; // 1 -const static uint64_t SH_FLD_PGMIGR1_BAR_LEN = 11126; // 1 -const static uint64_t SH_FLD_PGMIGR1_PGSZ = 11127; // 1 -const static uint64_t SH_FLD_PGMIGR1_PGSZ_LEN = 11128; // 1 -const static uint64_t SH_FLD_PGMIGR1_VAL = 11129; // 1 -const static uint64_t SH_FLD_PGMIGR2_BAR = 11130; // 1 -const static uint64_t SH_FLD_PGMIGR2_BAR_LEN = 11131; // 1 -const static uint64_t SH_FLD_PGMIGR2_PGSZ = 11132; // 1 -const static uint64_t SH_FLD_PGMIGR2_PGSZ_LEN = 11133; // 1 -const static uint64_t SH_FLD_PGMIGR2_VAL = 11134; // 1 -const static uint64_t SH_FLD_PGMIGR3_BAR = 11135; // 1 -const static uint64_t SH_FLD_PGMIGR3_BAR_LEN = 11136; // 1 -const static uint64_t SH_FLD_PGMIGR3_PGSZ = 11137; // 1 -const static uint64_t SH_FLD_PGMIGR3_PGSZ_LEN = 11138; // 1 -const static uint64_t SH_FLD_PGMIGR3_VAL = 11139; // 1 -const static uint64_t SH_FLD_PGMIGR4_BAR = 11140; // 1 -const static uint64_t SH_FLD_PGMIGR4_BAR_LEN = 11141; // 1 -const static uint64_t SH_FLD_PGMIGR4_PGSZ = 11142; // 1 -const static uint64_t SH_FLD_PGMIGR4_PGSZ_LEN = 11143; // 1 -const static uint64_t SH_FLD_PGMIGR4_VAL = 11144; // 1 -const static uint64_t SH_FLD_PGMIGR5_BAR = 11145; // 1 -const static uint64_t SH_FLD_PGMIGR5_BAR_LEN = 11146; // 1 -const static uint64_t SH_FLD_PGMIGR5_PGSZ = 11147; // 1 -const static uint64_t SH_FLD_PGMIGR5_PGSZ_LEN = 11148; // 1 -const static uint64_t SH_FLD_PGMIGR5_VAL = 11149; // 1 -const static uint64_t SH_FLD_PGMIGR6_BAR = 11150; // 1 -const static uint64_t SH_FLD_PGMIGR6_BAR_LEN = 11151; // 1 -const static uint64_t SH_FLD_PGMIGR6_PGSZ = 11152; // 1 -const static uint64_t SH_FLD_PGMIGR6_PGSZ_LEN = 11153; // 1 -const static uint64_t SH_FLD_PGMIGR6_VAL = 11154; // 1 -const static uint64_t SH_FLD_PGMIGR7_BAR = 11155; // 1 -const static uint64_t SH_FLD_PGMIGR7_BAR_LEN = 11156; // 1 -const static uint64_t SH_FLD_PGMIGR7_PGSZ = 11157; // 1 -const static uint64_t SH_FLD_PGMIGR7_PGSZ_LEN = 11158; // 1 -const static uint64_t SH_FLD_PGMIGR7_VAL = 11159; // 1 -const static uint64_t SH_FLD_PGOOD_TIMEOUT_SEL = 11160; // 4 -const static uint64_t SH_FLD_PGOOD_TIMEOUT_SEL_LEN = 11161; // 4 -const static uint64_t SH_FLD_PG_MIG_DISABLED_ERR = 11162; // 2 -const static uint64_t SH_FLD_PG_MIG_SIZE_MISMATCH_ERR = 11163; // 2 -const static uint64_t SH_FLD_PHASEFB = 11164; // 4 -const static uint64_t SH_FLD_PHASEFB_LEN = 11165; // 4 -const static uint64_t SH_FLD_PHBCSR_SPARE = 11166; // 1 -const static uint64_t SH_FLD_PHB_FILTER_CNTL = 11167; // 2 -const static uint64_t SH_FLD_PHB_FILTER_CNTL_LEN = 11168; // 2 -const static uint64_t SH_FLD_PHB_LINK_DOWN = 11169; // 4 -const static uint64_t SH_FLD_PHYP_SCOPE = 11170; // 1 -const static uint64_t SH_FLD_PIB2PCB_DC = 11171; // 1 -const static uint64_t SH_FLD_PIBI2CM_PIB_SLAVE_ID = 11172; // 1 -const static uint64_t SH_FLD_PIBI2CM_PIB_SLAVE_ID_LEN = 11173; // 1 -const static uint64_t SH_FLD_PIB_0 = 11174; // 2 -const static uint64_t SH_FLD_PIB_0_LEN = 11175; // 2 -const static uint64_t SH_FLD_PIB_1 = 11176; // 2 -const static uint64_t SH_FLD_PIB_1_LEN = 11177; // 2 -const static uint64_t SH_FLD_PIB_2 = 11178; // 2 -const static uint64_t SH_FLD_PIB_2_LEN = 11179; // 2 -const static uint64_t SH_FLD_PIB_3 = 11180; // 2 -const static uint64_t SH_FLD_PIB_3_LEN = 11181; // 2 -const static uint64_t SH_FLD_PIB_ABORT = 11182; // 2 -const static uint64_t SH_FLD_PIB_ADDR = 11183; // 22 -const static uint64_t SH_FLD_PIB_ADDR_LEN = 11184; // 22 -const static uint64_t SH_FLD_PIB_ADDR_P = 11185; // 1 -const static uint64_t SH_FLD_PIB_ADDR_P_ERR = 11186; // 1 -const static uint64_t SH_FLD_PIB_BUSY = 11187; // 21 -const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_0 = 11188; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_0_LEN = 11189; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_1 = 11190; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_1_LEN = 11191; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_2 = 11192; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_2_LEN = 11193; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_3 = 11194; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_3_LEN = 11195; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_0 = 11196; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_1 = 11197; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_2 = 11198; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_3 = 11199; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_0 = 11200; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_1 = 11201; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_2 = 11202; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_3 = 11203; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_0 = 11204; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_1 = 11205; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_2 = 11206; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_3 = 11207; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_0 = 11208; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_1 = 11209; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_2 = 11210; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_3 = 11211; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_0 = 11212; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_1 = 11213; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_2 = 11214; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_3 = 11215; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_0 = 11216; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_0_LEN = 11217; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_1 = 11218; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_1_LEN = 11219; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_2 = 11220; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_2_LEN = 11221; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_3 = 11222; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_3_LEN = 11223; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_0 = 11224; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_0_LEN = 11225; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_1 = 11226; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_1_LEN = 11227; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_2 = 11228; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_2_LEN = 11229; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_3 = 11230; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_3_LEN = 11231; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_0 = 11232; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_0_LEN = 11233; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_1 = 11234; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_1_LEN = 11235; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_2 = 11236; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_2_LEN = 11237; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_3 = 11238; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_3_LEN = 11239; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_0 = 11240; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_0_LEN = 11241; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_1 = 11242; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_1_LEN = 11243; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_2 = 11244; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_2_LEN = 11245; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_3 = 11246; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_3_LEN = 11247; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_0 = 11248; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_0_LEN = 11249; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_1 = 11250; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_1_LEN = 11251; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_2 = 11252; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_2_LEN = 11253; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_3 = 11254; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_3_LEN = 11255; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0 = 11256; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0_LEN = 11257; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1 = 11258; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1_LEN = 11259; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2 = 11260; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2_LEN = 11261; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3 = 11262; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3_LEN = 11263; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_0 = 11264; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_0_LEN = 11265; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_1 = 11266; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_1_LEN = 11267; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_2 = 11268; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_2_LEN = 11269; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_3 = 11270; // 1 -const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_3_LEN = 11271; // 1 -const static uint64_t SH_FLD_PIB_COMPONENT_BUSY = 11272; // 1 -const static uint64_t SH_FLD_PIB_DATA0TO7_0 = 11273; // 1 -const static uint64_t SH_FLD_PIB_DATA0TO7_0_LEN = 11274; // 1 -const static uint64_t SH_FLD_PIB_DATA0TO7_1 = 11275; // 1 -const static uint64_t SH_FLD_PIB_DATA0TO7_1_LEN = 11276; // 1 -const static uint64_t SH_FLD_PIB_DATA0TO7_2 = 11277; // 1 -const static uint64_t SH_FLD_PIB_DATA0TO7_2_LEN = 11278; // 1 -const static uint64_t SH_FLD_PIB_DATA0TO7_3 = 11279; // 1 -const static uint64_t SH_FLD_PIB_DATA0TO7_3_LEN = 11280; // 1 -const static uint64_t SH_FLD_PIB_DATAOP_PENDING = 11281; // 21 -const static uint64_t SH_FLD_PIB_DATA_P = 11282; // 1 -const static uint64_t SH_FLD_PIB_DATA_P_ERR = 11283; // 1 -const static uint64_t SH_FLD_PIB_ERROR_CODE = 11284; // 1 -const static uint64_t SH_FLD_PIB_ERROR_CODE_LEN = 11285; // 1 -const static uint64_t SH_FLD_PIB_FSM_STATE = 11286; // 1 -const static uint64_t SH_FLD_PIB_FSM_STATE_LEN = 11287; // 1 -const static uint64_t SH_FLD_PIB_HANG = 11288; // 1 -const static uint64_t SH_FLD_PIB_IFETCH_PENDING = 11289; // 21 -const static uint64_t SH_FLD_PIB_IMPRECISE_ERROR_PENDING = 11290; // 21 -const static uint64_t SH_FLD_PIB_MASTER_REQUEST = 11291; // 4 -const static uint64_t SH_FLD_PIB_MASTER_RSP_INFO = 11292; // 4 -const static uint64_t SH_FLD_PIB_MASTER_RSP_INFO_LEN = 11293; // 4 -const static uint64_t SH_FLD_PIB_RESET = 11294; // 1 -const static uint64_t SH_FLD_PIB_RESET_DURING_PIB_ACCESS = 11295; // 4 -const static uint64_t SH_FLD_PIB_RESPONSE_INFO = 11296; // 1 -const static uint64_t SH_FLD_PIB_RESPONSE_INFO_LEN = 11297; // 1 -const static uint64_t SH_FLD_PIB_RSP_INFO = 11298; // 21 -const static uint64_t SH_FLD_PIB_RSP_INFO_LEN = 11299; // 21 -const static uint64_t SH_FLD_PIB_R_NW = 11300; // 21 -const static uint64_t SH_FLD_PIB_SLAVE_ADDR_INVALID = 11301; // 4 -const static uint64_t SH_FLD_PIB_SLAVE_ADDR_PARITY = 11302; // 4 -const static uint64_t SH_FLD_PIB_SLAVE_DATA_PARITY = 11303; // 4 -const static uint64_t SH_FLD_PIB_SLAVE_READ_INVALID = 11304; // 4 -const static uint64_t SH_FLD_PIB_SLAVE_WRITE_INVALID = 11305; // 4 -const static uint64_t SH_FLD_PID = 11306; // 273 -const static uint64_t SH_FLD_PID_LEN = 11307; // 273 -const static uint64_t SH_FLD_PID_MASK = 11308; // 1 -const static uint64_t SH_FLD_PID_MASK_LEN = 11309; // 1 -const static uint64_t SH_FLD_PIPELINE_ENABLE = 11310; // 1 -const static uint64_t SH_FLD_PIPE_COUNTER = 11311; // 1 -const static uint64_t SH_FLD_PIPE_COUNTER_LEN = 11312; // 1 -const static uint64_t SH_FLD_PIPE_MARGIN = 11313; // 48 -const static uint64_t SH_FLD_PIPE_SEL = 11314; // 120 -const static uint64_t SH_FLD_PIPE_SEL_LEN = 11315; // 48 -const static uint64_t SH_FLD_PLBARB_LOCKERR = 11316; // 1 -const static uint64_t SH_FLD_PLLCVHOLD = 11317; // 6 -const static uint64_t SH_FLD_PLLFMAX = 11318; // 6 -const static uint64_t SH_FLD_PLLFMIN = 11319; // 6 -const static uint64_t SH_FLD_PLLLOCK = 11320; // 4 -const static uint64_t SH_FLD_PLLLOCK_0_FILTER_PLL_NEST = 11321; // 1 -const static uint64_t SH_FLD_PLLLOCK_1_FILTER_PLL_MC = 11322; // 1 -const static uint64_t SH_FLD_PLLLOCK_2_XBUS = 11323; // 1 -const static uint64_t SH_FLD_PLLLOCK_3_NEST = 11324; // 1 -const static uint64_t SH_FLD_PLLREFSEL = 11325; // 3 -const static uint64_t SH_FLD_PLLREFSEL_LEN = 11326; // 3 -const static uint64_t SH_FLD_PLLRESET = 11327; // 6 -const static uint64_t SH_FLD_PLL_BYPASS = 11328; // 43 -const static uint64_t SH_FLD_PLL_CLKIN_SEL = 11329; // 43 -const static uint64_t SH_FLD_PLL_DESTOUT = 11330; // 43 -const static uint64_t SH_FLD_PLL_LOCK_TIMEOUT_SEL = 11331; // 4 -const static uint64_t SH_FLD_PLL_LOCK_TIMEOUT_SEL_LEN = 11332; // 4 -const static uint64_t SH_FLD_PLL_REFCLKSEL_SCOM_EN = 11333; // 4 -const static uint64_t SH_FLD_PLL_RESET = 11334; // 43 -const static uint64_t SH_FLD_PLL_TEST_EN = 11335; // 43 -const static uint64_t SH_FLD_PLL_UNLOCK = 11336; // 43 -const static uint64_t SH_FLD_PLL_UNLOCK_LEN = 11337; // 43 -const static uint64_t SH_FLD_PL_ERR = 11338; // 6 -const static uint64_t SH_FLD_PL_FIR_ERR = 11339; // 6 -const static uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_EN = 11340; // 12 -const static uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_NUM = 11341; // 12 -const static uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_NUM_LEN = 11342; // 12 -const static uint64_t SH_FLD_PM03_SMT_ROTATION_DIS = 11343; // 12 -const static uint64_t SH_FLD_PM07_TID_ROTATE_PLSS_RATE = 11344; // 12 -const static uint64_t SH_FLD_PM07_TID_ROTATE_PLSS_RATE_LEN = 11345; // 12 -const static uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_EN = 11346; // 12 -const static uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_NUM = 11347; // 12 -const static uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_NUM_LEN = 11348; // 12 -const static uint64_t SH_FLD_PM47_SMT_ROTATION_DIS = 11349; // 12 -const static uint64_t SH_FLD_PMCM_THRESHOLD = 11350; // 24 -const static uint64_t SH_FLD_PMCM_THRESHOLD_LEN = 11351; // 24 -const static uint64_t SH_FLD_PMCR_OVERRIDE_EN = 11352; // 12 -const static uint64_t SH_FLD_PMCR_UPDATE_C0 = 11353; // 12 -const static uint64_t SH_FLD_PMCR_UPDATE_C1 = 11354; // 12 -const static uint64_t SH_FLD_PMC_O2S_0A_ONGOING = 11355; // 1 -const static uint64_t SH_FLD_PMC_O2S_0B_ONGOING = 11356; // 1 -const static uint64_t SH_FLD_PMC_O2S_1A_ONGOING = 11357; // 1 -const static uint64_t SH_FLD_PMC_O2S_1B_ONGOING = 11358; // 1 -const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE0_PENDING = 11359; // 1 -const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE1_PENDING = 11360; // 1 -const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE2_PENDING = 11361; // 1 -const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE3_PENDING = 11362; // 1 -const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE4_PENDING = 11363; // 1 -const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE5_PENDING = 11364; // 1 -const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE6_PENDING = 11365; // 1 -const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE7_PENDING = 11366; // 1 -const static uint64_t SH_FLD_PMISC_CRESP_ADDR_ERR = 11367; // 24 -const static uint64_t SH_FLD_PMISC_MODE = 11368; // 3 -const static uint64_t SH_FLD_PMON_GROUP_SELECT = 11369; // 2 -const static uint64_t SH_FLD_PMON_GROUP_SELECT_LEN = 11370; // 2 -const static uint64_t SH_FLD_PMON_MUX_BYTE0 = 11371; // 1 -const static uint64_t SH_FLD_PMON_MUX_BYTE0_LEN = 11372; // 1 -const static uint64_t SH_FLD_PMON_MUX_BYTE1 = 11373; // 1 -const static uint64_t SH_FLD_PMON_MUX_BYTE1_LEN = 11374; // 1 -const static uint64_t SH_FLD_PMON_MUX_BYTE2 = 11375; // 1 -const static uint64_t SH_FLD_PMON_MUX_BYTE2_LEN = 11376; // 1 -const static uint64_t SH_FLD_PMON_MUX_BYTE3 = 11377; // 1 -const static uint64_t SH_FLD_PMON_MUX_BYTE3_LEN = 11378; // 1 -const static uint64_t SH_FLD_PMSR_OVERRIDE_EN = 11379; // 12 -const static uint64_t SH_FLD_PMU0145_EVENT0_MODE = 11380; // 2 -const static uint64_t SH_FLD_PMU0145_EVENT0_MODE_LEN = 11381; // 2 -const static uint64_t SH_FLD_PMU0145_EVENT1_MODE = 11382; // 2 -const static uint64_t SH_FLD_PMU0145_EVENT1_MODE_LEN = 11383; // 2 -const static uint64_t SH_FLD_PMU0145_EVENT2_MODE = 11384; // 2 -const static uint64_t SH_FLD_PMU0145_EVENT2_MODE_LEN = 11385; // 2 -const static uint64_t SH_FLD_PMU0145_EVENT3_MODE = 11386; // 2 -const static uint64_t SH_FLD_PMU0145_EVENT3_MODE_LEN = 11387; // 2 -const static uint64_t SH_FLD_PMU01_LINK_SELECT = 11388; // 2 -const static uint64_t SH_FLD_PMU0_ENABLE = 11389; // 2 -const static uint64_t SH_FLD_PMU0_SIZE = 11390; // 2 -const static uint64_t SH_FLD_PMU0_SIZE_LEN = 11391; // 2 -const static uint64_t SH_FLD_PMU1_ENABLE = 11392; // 2 -const static uint64_t SH_FLD_PMU1_SIZE = 11393; // 2 -const static uint64_t SH_FLD_PMU1_SIZE_LEN = 11394; // 2 -const static uint64_t SH_FLD_PMU2367_EVENT0_MODE = 11395; // 2 -const static uint64_t SH_FLD_PMU2367_EVENT0_MODE_LEN = 11396; // 2 -const static uint64_t SH_FLD_PMU2367_EVENT1_MODE = 11397; // 2 -const static uint64_t SH_FLD_PMU2367_EVENT1_MODE_LEN = 11398; // 2 -const static uint64_t SH_FLD_PMU2367_EVENT2_MODE = 11399; // 2 -const static uint64_t SH_FLD_PMU2367_EVENT2_MODE_LEN = 11400; // 2 -const static uint64_t SH_FLD_PMU2367_EVENT3_MODE = 11401; // 2 -const static uint64_t SH_FLD_PMU2367_EVENT3_MODE_LEN = 11402; // 2 -const static uint64_t SH_FLD_PMU23_LINK_SELECT = 11403; // 2 -const static uint64_t SH_FLD_PMU2_ENABLE = 11404; // 2 -const static uint64_t SH_FLD_PMU2_SIZE = 11405; // 2 -const static uint64_t SH_FLD_PMU2_SIZE_LEN = 11406; // 2 -const static uint64_t SH_FLD_PMU3_ENABLE = 11407; // 2 -const static uint64_t SH_FLD_PMU3_SIZE = 11408; // 2 -const static uint64_t SH_FLD_PMU3_SIZE_LEN = 11409; // 2 -const static uint64_t SH_FLD_PMU45_LINK_SELECT = 11410; // 2 -const static uint64_t SH_FLD_PMU4_ENABLE = 11411; // 2 -const static uint64_t SH_FLD_PMU5_ENABLE = 11412; // 2 -const static uint64_t SH_FLD_PMU67_LINK_SELECT = 11413; // 2 -const static uint64_t SH_FLD_PMU6_ENABLE = 11414; // 2 -const static uint64_t SH_FLD_PMU7_ENABLE = 11415; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT = 11416; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT_LEN = 11417; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER0_ENABLE = 11418; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER0_EVENT_SELECT = 11419; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER0_EVENT_SELECT_LEN = 11420; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER0_POSEDGE_SELECT = 11421; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT = 11422; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT_LEN = 11423; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER1_ENABLE = 11424; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER1_EVENT_SELECT = 11425; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER1_EVENT_SELECT_LEN = 11426; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER1_POSEDGE_SELECT = 11427; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT = 11428; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT_LEN = 11429; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER2_ENABLE = 11430; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER2_EVENT_SELECT = 11431; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER2_EVENT_SELECT_LEN = 11432; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER2_POSEDGE_SELECT = 11433; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT = 11434; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT_LEN = 11435; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER3_ENABLE = 11436; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER3_EVENT_SELECT = 11437; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER3_EVENT_SELECT_LEN = 11438; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER3_POSEDGE_SELECT = 11439; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER_FREEZE_MODE = 11440; // 2 -const static uint64_t SH_FLD_PMUA_COUNTER_RESET_MODE = 11441; // 2 -const static uint64_t SH_FLD_PMUA_PORT_SELECT = 11442; // 2 -const static uint64_t SH_FLD_PMUA_PORT_SELECT_LEN = 11443; // 2 -const static uint64_t SH_FLD_PMUA_PRESCALER_SELECT = 11444; // 2 -const static uint64_t SH_FLD_PMUA_PRESCALER_SELECT_LEN = 11445; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT = 11446; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT_LEN = 11447; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER0_ENABLE = 11448; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER0_EVENT_SELECT = 11449; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER0_EVENT_SELECT_LEN = 11450; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER0_POSEDGE_SELECT = 11451; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT = 11452; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT_LEN = 11453; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER1_ENABLE = 11454; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER1_EVENT_SELECT = 11455; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER1_EVENT_SELECT_LEN = 11456; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER1_POSEDGE_SELECT = 11457; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT = 11458; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT_LEN = 11459; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER2_ENABLE = 11460; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER2_EVENT_SELECT = 11461; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER2_EVENT_SELECT_LEN = 11462; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER2_POSEDGE_SELECT = 11463; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT = 11464; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT_LEN = 11465; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER3_ENABLE = 11466; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER3_EVENT_SELECT = 11467; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER3_EVENT_SELECT_LEN = 11468; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER3_POSEDGE_SELECT = 11469; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER_FREEZE_MODE = 11470; // 2 -const static uint64_t SH_FLD_PMUB_COUNTER_RESET_MODE = 11471; // 2 -const static uint64_t SH_FLD_PMUB_PORT_SELECT = 11472; // 2 -const static uint64_t SH_FLD_PMUB_PORT_SELECT_LEN = 11473; // 2 -const static uint64_t SH_FLD_PMUB_PRESCALER_SELECT = 11474; // 2 -const static uint64_t SH_FLD_PMUB_PRESCALER_SELECT_LEN = 11475; // 2 -const static uint64_t SH_FLD_PMULET_FREEZE_MODE = 11476; // 2 -const static uint64_t SH_FLD_PMULET_RESET_MODE = 11477; // 2 -const static uint64_t SH_FLD_PMU_BUS_ENABLE = 11478; // 2 -const static uint64_t SH_FLD_PMU_BUS_ENABLE_LEN = 11479; // 2 -const static uint64_t SH_FLD_PMU_ENABLE = 11480; // 2 -const static uint64_t SH_FLD_PMU_SELECT_HIGH = 11481; // 2 -const static uint64_t SH_FLD_PMU_SELECT_HIGH_LEN = 11482; // 2 -const static uint64_t SH_FLD_PMU_SELECT_LOW = 11483; // 2 -const static uint64_t SH_FLD_PMU_SELECT_LOW_LEN = 11484; // 2 -const static uint64_t SH_FLD_PM_ERROR = 11485; // 6 -const static uint64_t SH_FLD_PM_STATE_ACTIVE_C0 = 11486; // 12 -const static uint64_t SH_FLD_PM_STATE_ACTIVE_C1 = 11487; // 12 -const static uint64_t SH_FLD_PM_STATE_ALL_HV_C0 = 11488; // 12 -const static uint64_t SH_FLD_PM_STATE_ALL_HV_C1 = 11489; // 12 -const static uint64_t SH_FLD_PM_STATE_C0 = 11490; // 12 -const static uint64_t SH_FLD_PM_STATE_C0_LEN = 11491; // 12 -const static uint64_t SH_FLD_PM_STATE_C1 = 11492; // 12 -const static uint64_t SH_FLD_PM_STATE_C1_LEN = 11493; // 12 -const static uint64_t SH_FLD_POCKET_RATE1 = 11494; // 12 -const static uint64_t SH_FLD_POCKET_RATE1_LEN = 11495; // 12 -const static uint64_t SH_FLD_POCKET_RATE2 = 11496; // 12 -const static uint64_t SH_FLD_POCKET_RATE2_LEN = 11497; // 12 -const static uint64_t SH_FLD_POCKET_RATE3 = 11498; // 12 -const static uint64_t SH_FLD_POCKET_RATE3_LEN = 11499; // 12 -const static uint64_t SH_FLD_POD0 = 11500; // 50 -const static uint64_t SH_FLD_POD0_LEN = 11501; // 50 -const static uint64_t SH_FLD_POD1 = 11502; // 50 -const static uint64_t SH_FLD_POD10 = 11503; // 50 -const static uint64_t SH_FLD_POD10_LEN = 11504; // 50 -const static uint64_t SH_FLD_POD1_LEN = 11505; // 50 -const static uint64_t SH_FLD_POD2 = 11506; // 50 -const static uint64_t SH_FLD_POD2_LEN = 11507; // 50 -const static uint64_t SH_FLD_POD3 = 11508; // 50 -const static uint64_t SH_FLD_POD3_LEN = 11509; // 50 -const static uint64_t SH_FLD_POD4 = 11510; // 50 -const static uint64_t SH_FLD_POD4_LEN = 11511; // 50 -const static uint64_t SH_FLD_POD5 = 11512; // 50 -const static uint64_t SH_FLD_POD5_LEN = 11513; // 50 -const static uint64_t SH_FLD_POD6 = 11514; // 50 -const static uint64_t SH_FLD_POD6_LEN = 11515; // 50 -const static uint64_t SH_FLD_POD7 = 11516; // 50 -const static uint64_t SH_FLD_POD7_LEN = 11517; // 50 -const static uint64_t SH_FLD_POD8 = 11518; // 50 -const static uint64_t SH_FLD_POD8_LEN = 11519; // 50 -const static uint64_t SH_FLD_POD9 = 11520; // 50 -const static uint64_t SH_FLD_POD9_LEN = 11521; // 50 -const static uint64_t SH_FLD_POINTER = 11522; // 2 -const static uint64_t SH_FLD_POINTER_LEN = 11523; // 2 -const static uint64_t SH_FLD_POLLING_TIMEOUT_SEL = 11524; // 6 -const static uint64_t SH_FLD_POLLING_TIMEOUT_SEL_LEN = 11525; // 6 -const static uint64_t SH_FLD_POLL_BCST_RTY_MON = 11526; // 1 -const static uint64_t SH_FLD_POLL_DONE = 11527; // 1 -const static uint64_t SH_FLD_POOL = 11528; // 1 -const static uint64_t SH_FLD_POOL_LEN = 11529; // 1 -const static uint64_t SH_FLD_PORT0_ERROR_CODE = 11530; // 3 -const static uint64_t SH_FLD_PORT0_ERROR_CODE_0 = 11531; // 1 -const static uint64_t SH_FLD_PORT0_ERROR_CODE_0_LEN = 11532; // 1 -const static uint64_t SH_FLD_PORT0_ERROR_CODE_1 = 11533; // 2 -const static uint64_t SH_FLD_PORT0_ERROR_CODE_1_LEN = 11534; // 2 -const static uint64_t SH_FLD_PORT0_ERROR_CODE_2 = 11535; // 3 -const static uint64_t SH_FLD_PORT0_ERROR_CODE_2_LEN = 11536; // 3 -const static uint64_t SH_FLD_PORT0_ERROR_CODE_LEN = 11537; // 3 -const static uint64_t SH_FLD_PORT1_ERROR_CODE = 11538; // 3 -const static uint64_t SH_FLD_PORT1_ERROR_CODE_0 = 11539; // 1 -const static uint64_t SH_FLD_PORT1_ERROR_CODE_0_LEN = 11540; // 1 -const static uint64_t SH_FLD_PORT1_ERROR_CODE_1 = 11541; // 2 -const static uint64_t SH_FLD_PORT1_ERROR_CODE_1_LEN = 11542; // 2 -const static uint64_t SH_FLD_PORT1_ERROR_CODE_2 = 11543; // 3 -const static uint64_t SH_FLD_PORT1_ERROR_CODE_2_LEN = 11544; // 3 -const static uint64_t SH_FLD_PORT1_ERROR_CODE_LEN = 11545; // 3 -const static uint64_t SH_FLD_PORT2_ERROR_CODE = 11546; // 3 -const static uint64_t SH_FLD_PORT2_ERROR_CODE_0 = 11547; // 1 -const static uint64_t SH_FLD_PORT2_ERROR_CODE_0_LEN = 11548; // 1 -const static uint64_t SH_FLD_PORT2_ERROR_CODE_1 = 11549; // 2 -const static uint64_t SH_FLD_PORT2_ERROR_CODE_1_LEN = 11550; // 2 -const static uint64_t SH_FLD_PORT2_ERROR_CODE_2 = 11551; // 3 -const static uint64_t SH_FLD_PORT2_ERROR_CODE_2_LEN = 11552; // 3 -const static uint64_t SH_FLD_PORT2_ERROR_CODE_LEN = 11553; // 3 -const static uint64_t SH_FLD_PORT3_ERROR_CODE = 11554; // 3 -const static uint64_t SH_FLD_PORT3_ERROR_CODE_0 = 11555; // 1 -const static uint64_t SH_FLD_PORT3_ERROR_CODE_0_LEN = 11556; // 1 -const static uint64_t SH_FLD_PORT3_ERROR_CODE_1 = 11557; // 2 -const static uint64_t SH_FLD_PORT3_ERROR_CODE_1_LEN = 11558; // 2 -const static uint64_t SH_FLD_PORT3_ERROR_CODE_2 = 11559; // 3 -const static uint64_t SH_FLD_PORT3_ERROR_CODE_2_LEN = 11560; // 3 -const static uint64_t SH_FLD_PORT3_ERROR_CODE_LEN = 11561; // 3 -const static uint64_t SH_FLD_PORT4_ERROR_CODE = 11562; // 3 -const static uint64_t SH_FLD_PORT4_ERROR_CODE_0 = 11563; // 1 -const static uint64_t SH_FLD_PORT4_ERROR_CODE_0_LEN = 11564; // 1 -const static uint64_t SH_FLD_PORT4_ERROR_CODE_1 = 11565; // 2 -const static uint64_t SH_FLD_PORT4_ERROR_CODE_1_LEN = 11566; // 2 -const static uint64_t SH_FLD_PORT4_ERROR_CODE_2 = 11567; // 3 -const static uint64_t SH_FLD_PORT4_ERROR_CODE_2_LEN = 11568; // 3 -const static uint64_t SH_FLD_PORT4_ERROR_CODE_LEN = 11569; // 3 -const static uint64_t SH_FLD_PORT5_ERROR_CODE = 11570; // 3 -const static uint64_t SH_FLD_PORT5_ERROR_CODE_0 = 11571; // 1 -const static uint64_t SH_FLD_PORT5_ERROR_CODE_0_LEN = 11572; // 1 -const static uint64_t SH_FLD_PORT5_ERROR_CODE_1 = 11573; // 2 -const static uint64_t SH_FLD_PORT5_ERROR_CODE_1_LEN = 11574; // 2 -const static uint64_t SH_FLD_PORT5_ERROR_CODE_2 = 11575; // 3 -const static uint64_t SH_FLD_PORT5_ERROR_CODE_2_LEN = 11576; // 3 -const static uint64_t SH_FLD_PORT5_ERROR_CODE_LEN = 11577; // 3 -const static uint64_t SH_FLD_PORT6_ERROR_CODE = 11578; // 3 -const static uint64_t SH_FLD_PORT6_ERROR_CODE_0 = 11579; // 1 -const static uint64_t SH_FLD_PORT6_ERROR_CODE_0_LEN = 11580; // 1 -const static uint64_t SH_FLD_PORT6_ERROR_CODE_1 = 11581; // 2 -const static uint64_t SH_FLD_PORT6_ERROR_CODE_1_LEN = 11582; // 2 -const static uint64_t SH_FLD_PORT6_ERROR_CODE_2 = 11583; // 3 -const static uint64_t SH_FLD_PORT6_ERROR_CODE_2_LEN = 11584; // 3 -const static uint64_t SH_FLD_PORT6_ERROR_CODE_LEN = 11585; // 3 -const static uint64_t SH_FLD_PORT7_ERROR_CODE = 11586; // 3 -const static uint64_t SH_FLD_PORT7_ERROR_CODE_0 = 11587; // 1 -const static uint64_t SH_FLD_PORT7_ERROR_CODE_0_LEN = 11588; // 1 -const static uint64_t SH_FLD_PORT7_ERROR_CODE_1 = 11589; // 2 -const static uint64_t SH_FLD_PORT7_ERROR_CODE_1_LEN = 11590; // 2 -const static uint64_t SH_FLD_PORT7_ERROR_CODE_2 = 11591; // 3 -const static uint64_t SH_FLD_PORT7_ERROR_CODE_2_LEN = 11592; // 3 -const static uint64_t SH_FLD_PORT7_ERROR_CODE_LEN = 11593; // 3 -const static uint64_t SH_FLD_PORT_0_ENABLE = 11594; // 1 -const static uint64_t SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP = 11595; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN = 11596; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP = 11597; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN = 11598; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ON_RCE = 11599; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP = 11600; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN = 11601; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD = 11602; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN = 11603; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_IS_TCE = 11604; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD = 11605; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 11606; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ON_RCE = 11607; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP = 11608; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN = 11609; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD = 11610; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN = 11611; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD = 11612; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 11613; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP = 11614; // 2 -const static uint64_t SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN = 11615; // 2 -const static uint64_t SH_FLD_PORT_1_ENABLE = 11616; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP = 11617; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP_LEN = 11618; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP = 11619; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP_LEN = 11620; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ON_RCE = 11621; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP = 11622; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP_LEN = 11623; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD = 11624; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN = 11625; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_IS_TCE = 11626; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD = 11627; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 11628; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ON_RCE = 11629; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP = 11630; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP_LEN = 11631; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD = 11632; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN = 11633; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD = 11634; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 11635; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP = 11636; // 2 -const static uint64_t SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP_LEN = 11637; // 2 -const static uint64_t SH_FLD_PORT_2_ENABLE = 11638; // 3 -const static uint64_t SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP = 11639; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP_LEN = 11640; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP = 11641; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP_LEN = 11642; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ON_RCE = 11643; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP = 11644; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP_LEN = 11645; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD = 11646; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD_LEN = 11647; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_IS_TCE = 11648; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD = 11649; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 11650; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ON_RCE = 11651; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP = 11652; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP_LEN = 11653; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD = 11654; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD_LEN = 11655; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD = 11656; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 11657; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP = 11658; // 2 -const static uint64_t SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP_LEN = 11659; // 2 -const static uint64_t SH_FLD_PORT_3_ENABLE = 11660; // 3 -const static uint64_t SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP = 11661; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP_LEN = 11662; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP = 11663; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP_LEN = 11664; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ON_RCE = 11665; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP = 11666; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP_LEN = 11667; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD = 11668; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD_LEN = 11669; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_IS_TCE = 11670; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD = 11671; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 11672; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ON_RCE = 11673; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP = 11674; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP_LEN = 11675; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD = 11676; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD_LEN = 11677; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD = 11678; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 11679; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP = 11680; // 2 -const static uint64_t SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP_LEN = 11681; // 2 -const static uint64_t SH_FLD_PORT_4_ENABLE = 11682; // 3 -const static uint64_t SH_FLD_PORT_5_ENABLE = 11683; // 3 -const static uint64_t SH_FLD_PORT_6_ENABLE = 11684; // 3 -const static uint64_t SH_FLD_PORT_7_ENABLE = 11685; // 3 -const static uint64_t SH_FLD_PORT_ENABLE = 11686; // 3 -const static uint64_t SH_FLD_PORT_ERROR_RESET = 11687; // 1 -const static uint64_t SH_FLD_PORT_ERROR_RESET_1 = 11688; // 2 -const static uint64_t SH_FLD_PORT_ERROR_RESET_2 = 11689; // 3 -const static uint64_t SH_FLD_PORT_ERROR_RESET_3 = 11690; // 3 -const static uint64_t SH_FLD_PORT_ERROR_RESET_4 = 11691; // 3 -const static uint64_t SH_FLD_PORT_ERROR_RESET_5 = 11692; // 3 -const static uint64_t SH_FLD_PORT_ERROR_RESET_6 = 11693; // 3 -const static uint64_t SH_FLD_PORT_ERROR_RESET_7 = 11694; // 3 -const static uint64_t SH_FLD_PORT_GENERAL_RESET = 11695; // 1 -const static uint64_t SH_FLD_PORT_GENERAL_RESET_1 = 11696; // 2 -const static uint64_t SH_FLD_PORT_GENERAL_RESET_2 = 11697; // 3 -const static uint64_t SH_FLD_PORT_GENERAL_RESET_3 = 11698; // 3 -const static uint64_t SH_FLD_PORT_GENERAL_RESET_4 = 11699; // 3 -const static uint64_t SH_FLD_PORT_GENERAL_RESET_5 = 11700; // 3 -const static uint64_t SH_FLD_PORT_GENERAL_RESET_6 = 11701; // 3 -const static uint64_t SH_FLD_PORT_GENERAL_RESET_7 = 11702; // 3 -const static uint64_t SH_FLD_PORT_NUMBER = 11703; // 1 -const static uint64_t SH_FLD_PORT_NUMBER_0 = 11704; // 1 -const static uint64_t SH_FLD_PORT_NUMBER_0_LEN = 11705; // 1 -const static uint64_t SH_FLD_PORT_NUMBER_1 = 11706; // 1 -const static uint64_t SH_FLD_PORT_NUMBER_1_LEN = 11707; // 1 -const static uint64_t SH_FLD_PORT_NUMBER_2 = 11708; // 1 -const static uint64_t SH_FLD_PORT_NUMBER_2_LEN = 11709; // 1 -const static uint64_t SH_FLD_PORT_NUMBER_3 = 11710; // 1 -const static uint64_t SH_FLD_PORT_NUMBER_3_LEN = 11711; // 1 -const static uint64_t SH_FLD_PORT_NUMBER_LEN = 11712; // 1 -const static uint64_t SH_FLD_PORT_SEL = 11713; // 1 -const static uint64_t SH_FLD_PORT_SEL_LEN = 11714; // 1 -const static uint64_t SH_FLD_POWDN_DLY = 11715; // 30 -const static uint64_t SH_FLD_POWDN_DLY_LEN = 11716; // 30 -const static uint64_t SH_FLD_POWERBUS_DATA_HANG_ERROR = 11717; // 4 -const static uint64_t SH_FLD_POWERBUS_HANG_ERROR = 11718; // 4 -const static uint64_t SH_FLD_POWERBUS_INTERFACE_PE = 11719; // 4 -const static uint64_t SH_FLD_POWERBUS_MISC_ERROR = 11720; // 4 -const static uint64_t SH_FLD_POWERBUS_PROTOCOL_ERROR = 11721; // 4 -const static uint64_t SH_FLD_POWER_MANAGEMENT_INTERRUPT = 11722; // 1 -const static uint64_t SH_FLD_POWER_SAVING_LIMIT_A_N = 11723; // 96 -const static uint64_t SH_FLD_POWER_SAVING_LIMIT_A_N_LEN = 11724; // 96 -const static uint64_t SH_FLD_POWER_UP_CNTR_REF = 11725; // 1 -const static uint64_t SH_FLD_POWER_UP_CNTR_REF_LEN = 11726; // 1 -const static uint64_t SH_FLD_POWUP_DLY = 11727; // 30 -const static uint64_t SH_FLD_POWUP_DLY_LEN = 11728; // 30 -const static uint64_t SH_FLD_PPC405_HALT = 11729; // 1 -const static uint64_t SH_FLD_PPE_BREAKPOINT_ERROR = 11730; // 12 -const static uint64_t SH_FLD_PPE_DEBUG_TRIGGER = 11731; // 12 -const static uint64_t SH_FLD_PPE_EXTERNAL_ERROR = 11732; // 12 -const static uint64_t SH_FLD_PPE_HALTED = 11733; // 12 -const static uint64_t SH_FLD_PPE_INTERNAL_ERROR = 11734; // 12 -const static uint64_t SH_FLD_PPE_PROGRESS_ERROR = 11735; // 12 -const static uint64_t SH_FLD_PPE_RD_ACK_DEAD = 11736; // 12 -const static uint64_t SH_FLD_PPE_RD_CRESP_ADDR_ERR = 11737; // 24 -const static uint64_t SH_FLD_PPE_RD_FOREIGN0_ACK_DEAD = 11738; // 12 -const static uint64_t SH_FLD_PPE_RD_FOREIGN1_ACK_DEAD = 11739; // 12 -const static uint64_t SH_FLD_PPE_WATCHDOG = 11740; // 12 -const static uint64_t SH_FLD_PPE_WR_ACK_DEAD = 11741; // 12 -const static uint64_t SH_FLD_PPE_WR_CRESP_ADDR_ERR = 11742; // 24 -const static uint64_t SH_FLD_PPE_WR_FOREIGN0_ACK_DEAD = 11743; // 12 -const static uint64_t SH_FLD_PPE_WR_FOREIGN1_ACK_DEAD = 11744; // 12 -const static uint64_t SH_FLD_PPE_XIRAMEDR_EDR = 11745; // 4 -const static uint64_t SH_FLD_PPE_XIRAMEDR_EDR_LEN = 11746; // 4 -const static uint64_t SH_FLD_PPE_XIRAMGA_IR = 11747; // 4 -const static uint64_t SH_FLD_PPE_XIRAMGA_IR_LEN = 11748; // 4 -const static uint64_t SH_FLD_PPE_XIRAMRA_SPRG0 = 11749; // 4 -const static uint64_t SH_FLD_PPE_XIRAMRA_SPRG0_LEN = 11750; // 4 -const static uint64_t SH_FLD_PPE_XIXCR_XCR = 11751; // 4 -const static uint64_t SH_FLD_PPE_XIXCR_XCR_LEN = 11752; // 4 -const static uint64_t SH_FLD_PPM_SPARE_OUT_C0 = 11753; // 12 -const static uint64_t SH_FLD_PPM_SPARE_OUT_C1 = 11754; // 12 -const static uint64_t SH_FLD_PPM_WRITE_DISABLE = 11755; // 24 -const static uint64_t SH_FLD_PPM_WRITE_OVERRIDE = 11756; // 24 -const static uint64_t SH_FLD_PQ_STATE = 11757; // 1 -const static uint64_t SH_FLD_PQ_STATE_LEN = 11758; // 1 -const static uint64_t SH_FLD_PRBS_CHECK_SYNC = 11759; // 72 -const static uint64_t SH_FLD_PRBS_SCRAMBLE_MODE = 11760; // 144 -const static uint64_t SH_FLD_PRBS_SCRAMBLE_MODE_LEN = 11761; // 144 -const static uint64_t SH_FLD_PRBS_SEED_DDC = 11762; // 72 -const static uint64_t SH_FLD_PRBS_SEED_MODE = 11763; // 76 -const static uint64_t SH_FLD_PRBS_SEED_VALUE_0_15 = 11764; // 140 -const static uint64_t SH_FLD_PRBS_SEED_VALUE_0_15_LEN = 11765; // 140 -const static uint64_t SH_FLD_PRBS_SEED_VALUE_16_22 = 11766; // 140 -const static uint64_t SH_FLD_PRBS_SEED_VALUE_16_22_LEN = 11767; // 140 -const static uint64_t SH_FLD_PRBS_SLS_EXPECT = 11768; // 4 -const static uint64_t SH_FLD_PRBS_SLS_EXPECT_LEN = 11769; // 4 -const static uint64_t SH_FLD_PRBS_SYNC_MODE = 11770; // 72 -const static uint64_t SH_FLD_PRBS_TEST_DATA = 11771; // 120 -const static uint64_t SH_FLD_PRBS_TEST_DATA_LEN = 11772; // 120 -const static uint64_t SH_FLD_PRECISE_DIR_FLUSH_FAILED = 11773; // 2 -const static uint64_t SH_FLD_PRECISE_DIR_SIZE = 11774; // 2 -const static uint64_t SH_FLD_PRECISE_DIR_SIZE_LEN = 11775; // 2 -const static uint64_t SH_FLD_PRECLUDE = 11776; // 1 -const static uint64_t SH_FLD_PREFETCH = 11777; // 6 -const static uint64_t SH_FLD_PREFETCH_CHANNEL_CNT = 11778; // 1 -const static uint64_t SH_FLD_PREFETCH_CHANNEL_CNT_LEN = 11779; // 1 -const static uint64_t SH_FLD_PREFETCH_DISABLE = 11780; // 6 -const static uint64_t SH_FLD_PREFETCH_DISTANCE = 11781; // 6 -const static uint64_t SH_FLD_PREFETCH_DISTANCE_LEN = 11782; // 6 -const static uint64_t SH_FLD_PREFETCH_LIMIT = 11783; // 8 -const static uint64_t SH_FLD_PREFETCH_LIMIT_LEN = 11784; // 8 -const static uint64_t SH_FLD_PREF_DEPTH = 11785; // 1 -const static uint64_t SH_FLD_PREF_DEPTH_LEN = 11786; // 1 -const static uint64_t SH_FLD_PREF_THRSH0 = 11787; // 1 -const static uint64_t SH_FLD_PREF_THRSH0_LEN = 11788; // 1 -const static uint64_t SH_FLD_PREF_THRSH1 = 11789; // 1 -const static uint64_t SH_FLD_PREF_THRSH1_LEN = 11790; // 1 -const static uint64_t SH_FLD_PREF_THRSH2 = 11791; // 1 -const static uint64_t SH_FLD_PREF_THRSH2_LEN = 11792; // 1 -const static uint64_t SH_FLD_PREF_THRSH3 = 11793; // 1 -const static uint64_t SH_FLD_PREF_THRSH3_LEN = 11794; // 1 -const static uint64_t SH_FLD_PREF_TIMEOUT = 11795; // 1 -const static uint64_t SH_FLD_PREF_TIMEOUT_LEN = 11796; // 1 -const static uint64_t SH_FLD_PRESCALAR_SEL0 = 11797; // 2 -const static uint64_t SH_FLD_PRESCALAR_SEL0_LEN = 11798; // 2 -const static uint64_t SH_FLD_PRESCALAR_SEL1 = 11799; // 2 -const static uint64_t SH_FLD_PRESCALAR_SEL1_LEN = 11800; // 2 -const static uint64_t SH_FLD_PRESCALAR_SEL2 = 11801; // 2 -const static uint64_t SH_FLD_PRESCALAR_SEL2_LEN = 11802; // 2 -const static uint64_t SH_FLD_PRESCALAR_SEL3 = 11803; // 2 -const static uint64_t SH_FLD_PRESCALAR_SEL3_LEN = 11804; // 2 -const static uint64_t SH_FLD_PRESCALER_SEL = 11805; // 1 -const static uint64_t SH_FLD_PRESCALER_SELECT = 11806; // 1 -const static uint64_t SH_FLD_PRESCALER_SELECT_LEN = 11807; // 1 -const static uint64_t SH_FLD_PRESCALER_SEL_LEN = 11808; // 1 -const static uint64_t SH_FLD_PRESCALE_C0 = 11809; // 3 -const static uint64_t SH_FLD_PRESCALE_C0_LEN = 11810; // 3 -const static uint64_t SH_FLD_PRESCALE_C1 = 11811; // 3 -const static uint64_t SH_FLD_PRESCALE_C1_LEN = 11812; // 3 -const static uint64_t SH_FLD_PRESCALE_C2 = 11813; // 3 -const static uint64_t SH_FLD_PRESCALE_C2_LEN = 11814; // 3 -const static uint64_t SH_FLD_PRESCALE_C3 = 11815; // 3 -const static uint64_t SH_FLD_PRESCALE_C3_LEN = 11816; // 3 -const static uint64_t SH_FLD_PRESP_RTY_OTHER = 11817; // 2 -const static uint64_t SH_FLD_PREVENT_SBE_START = 11818; // 1 -const static uint64_t SH_FLD_PRGM_ADDR = 11819; // 1 -const static uint64_t SH_FLD_PRGM_ADDR_LEN = 11820; // 1 -const static uint64_t SH_FLD_PRGSM_BUSY = 11821; // 24 -const static uint64_t SH_FLD_PRGSM_BUSY_ON_THIS = 11822; // 24 -const static uint64_t SH_FLD_PRG_BIT_LOCATION = 11823; // 1 -const static uint64_t SH_FLD_PRG_BIT_LOCATION_LEN = 11824; // 1 -const static uint64_t SH_FLD_PRI = 11825; // 8 -const static uint64_t SH_FLD_PRIORITY = 11826; // 18 -const static uint64_t SH_FLD_PRIORITY_ENABLE = 11827; // 6 -const static uint64_t SH_FLD_PRIORITY_LEN = 11828; // 6 -const static uint64_t SH_FLD_PRIORITY_LIMIT_0_3 = 11829; // 1 -const static uint64_t SH_FLD_PRIORITY_LIMIT_0_3_LEN = 11830; // 1 -const static uint64_t SH_FLD_PRIORITY_LPID = 11831; // 6 -const static uint64_t SH_FLD_PRIORITY_LPID_LEN = 11832; // 6 -const static uint64_t SH_FLD_PRIORITY_PID = 11833; // 6 -const static uint64_t SH_FLD_PRIORITY_PID_LEN = 11834; // 6 -const static uint64_t SH_FLD_PRIORITY_PRIMAX = 11835; // 3 -const static uint64_t SH_FLD_PRIORITY_PRIMAX_LEN = 11836; // 3 -const static uint64_t SH_FLD_PRIORITY_QUEUED = 11837; // 6 -const static uint64_t SH_FLD_PRIORITY_QUEUED_LEN = 11838; // 6 -const static uint64_t SH_FLD_PRIORITY_READ_OFFSET = 11839; // 6 -const static uint64_t SH_FLD_PRIORITY_READ_OFFSET_LEN = 11840; // 6 -const static uint64_t SH_FLD_PRIORITY_SIZE = 11841; // 6 -const static uint64_t SH_FLD_PRIORITY_SIZE_LEN = 11842; // 6 -const static uint64_t SH_FLD_PRIORITY_TID = 11843; // 6 -const static uint64_t SH_FLD_PRIORITY_TID_LEN = 11844; // 6 -const static uint64_t SH_FLD_PRI_I_PATH_STEP_CHECK_ENABLE = 11845; // 1 -const static uint64_t SH_FLD_PRI_LEN = 11846; // 8 -const static uint64_t SH_FLD_PRI_M_PATH_0_STEP_CHECK_ENABLE = 11847; // 1 -const static uint64_t SH_FLD_PRI_M_PATH_1_STEP_CHECK_ENABLE = 11848; // 1 -const static uint64_t SH_FLD_PRI_M_PATH_SELECT = 11849; // 2 -const static uint64_t SH_FLD_PRI_M_S_DRAWER_SELECT = 11850; // 2 -const static uint64_t SH_FLD_PRI_M_S_SELECT = 11851; // 2 -const static uint64_t SH_FLD_PRI_SEC_SELECT = 11852; // 1 -const static uint64_t SH_FLD_PRI_SEC_SELECT_LEN = 11853; // 1 -const static uint64_t SH_FLD_PRI_SELECT = 11854; // 1 -const static uint64_t SH_FLD_PRI_S_PATH_0_STEP_CHECK_ENABLE = 11855; // 1 -const static uint64_t SH_FLD_PRI_S_PATH_1_STEP_CHECK_ENABLE = 11856; // 1 -const static uint64_t SH_FLD_PRI_S_PATH_SELECT = 11857; // 1 -const static uint64_t SH_FLD_PRI_V = 11858; // 8 -const static uint64_t SH_FLD_PROBE_0_TOGGLE_ENABLE = 11859; // 1 -const static uint64_t SH_FLD_PROBE_1_TOGGLE_ENABLE = 11860; // 1 -const static uint64_t SH_FLD_PROBE_2_TOGGLE_ENABLE = 11861; // 1 -const static uint64_t SH_FLD_PROBE_3_TOGGLE_ENABLE = 11862; // 1 -const static uint64_t SH_FLD_PROC_RCVY_AGAIN = 11863; // 96 -const static uint64_t SH_FLD_PROC_RCVY_DONE = 11864; // 96 -const static uint64_t SH_FLD_PROGRAM_ENABLE = 11865; // 1 -const static uint64_t SH_FLD_PROG_REQ_DELAY = 11866; // 1 -const static uint64_t SH_FLD_PROG_REQ_DELAY_LEN = 11867; // 1 -const static uint64_t SH_FLD_PROTECTION_CHECK = 11868; // 1 -const static uint64_t SH_FLD_PROTOCOL = 11869; // 8 -const static uint64_t SH_FLD_PROTOCOL_ERROR = 11870; // 43 -const static uint64_t SH_FLD_PROTOCOL_LEN = 11871; // 8 -const static uint64_t SH_FLD_PROT_EX_SPARE0 = 11872; // 1 -const static uint64_t SH_FLD_PROT_EX_SPARE1 = 11873; // 1 -const static uint64_t SH_FLD_PROT_TP_SPARE0 = 11874; // 1 -const static uint64_t SH_FLD_PROT_TP_SPARE1 = 11875; // 1 -const static uint64_t SH_FLD_PROT_TP_SPARE2 = 11876; // 1 -const static uint64_t SH_FLD_PRPG_A_VAL = 11877; // 43 -const static uint64_t SH_FLD_PRPG_A_VAL_LEN = 11878; // 43 -const static uint64_t SH_FLD_PRPG_B_VAL = 11879; // 43 -const static uint64_t SH_FLD_PRPG_B_VAL_LEN = 11880; // 43 -const static uint64_t SH_FLD_PRPG_MODE = 11881; // 43 -const static uint64_t SH_FLD_PRPG_VALUE = 11882; // 43 -const static uint64_t SH_FLD_PRPG_VALUE_LEN = 11883; // 43 -const static uint64_t SH_FLD_PRPG_WEIGHTING = 11884; // 43 -const static uint64_t SH_FLD_PRPG_WEIGHTING_LEN = 11885; // 43 -const static uint64_t SH_FLD_PRS = 11886; // 8 -const static uint64_t SH_FLD_PRV_BUS0_STG2_SEL = 11887; // 1 -const static uint64_t SH_FLD_PRV_BUS1_STG2_SEL = 11888; // 1 -const static uint64_t SH_FLD_PR_BUMP_SL_1UI = 11889; // 120 -const static uint64_t SH_FLD_PR_BUMP_SR_1UI = 11890; // 120 -const static uint64_t SH_FLD_PR_BUMP_TO_CENTER = 11891; // 72 -const static uint64_t SH_FLD_PR_BUMP_TO_EDGE_A = 11892; // 120 -const static uint64_t SH_FLD_PR_BUMP_TO_EDGE_B = 11893; // 48 -const static uint64_t SH_FLD_PR_DATA_A_OFFSET = 11894; // 120 -const static uint64_t SH_FLD_PR_DATA_A_OFFSET_LEN = 11895; // 120 -const static uint64_t SH_FLD_PR_DATA_B_OFFSET = 11896; // 120 -const static uint64_t SH_FLD_PR_DATA_B_OFFSET_LEN = 11897; // 120 -const static uint64_t SH_FLD_PR_DDC_A = 11898; // 120 -const static uint64_t SH_FLD_PR_DDC_B = 11899; // 48 -const static uint64_t SH_FLD_PR_EDGE_TRACK_CNTL = 11900; // 120 -const static uint64_t SH_FLD_PR_EDGE_TRACK_CNTL_LEN = 11901; // 120 -const static uint64_t SH_FLD_PR_FW_INERTIA_AMT = 11902; // 48 -const static uint64_t SH_FLD_PR_FW_INERTIA_AMT_LEN = 11903; // 48 -const static uint64_t SH_FLD_PR_FW_OFF = 11904; // 48 -const static uint64_t SH_FLD_PR_HALFRATE_MODE = 11905; // 120 -const static uint64_t SH_FLD_PR_INVALID_LOCK_BUMP_SIZE = 11906; // 120 -const static uint64_t SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN = 11907; // 120 -const static uint64_t SH_FLD_PR_INVALID_LOCK_FILTER_EN = 11908; // 120 -const static uint64_t SH_FLD_PR_IQ_RES_SEL = 11909; // 120 -const static uint64_t SH_FLD_PR_IQ_RES_SEL_LEN = 11910; // 120 -const static uint64_t SH_FLD_PR_LOCK_DONE = 11911; // 120 -const static uint64_t SH_FLD_PR_PHASE_STEP = 11912; // 120 -const static uint64_t SH_FLD_PR_PHASE_STEP_LEN = 11913; // 120 -const static uint64_t SH_FLD_PR_RESET = 11914; // 48 -const static uint64_t SH_FLD_PR_TRACE_DDC_SM = 11915; // 120 -const static uint64_t SH_FLD_PR_TRACE_DDC_SM_LEN = 11916; // 120 -const static uint64_t SH_FLD_PR_TRACE_DDC_STOP = 11917; // 120 -const static uint64_t SH_FLD_PR_TRACE_WOBBLE_SM = 11918; // 120 -const static uint64_t SH_FLD_PR_TRACE_WOBBLE_SM_LEN = 11919; // 120 -const static uint64_t SH_FLD_PR_TRACE_WOBBLE_STOP = 11920; // 120 -const static uint64_t SH_FLD_PR_USE_DFE_CLOCK_A = 11921; // 120 -const static uint64_t SH_FLD_PR_USE_DFE_CLOCK_B = 11922; // 48 -const static uint64_t SH_FLD_PR_WOBBLE_A = 11923; // 120 -const static uint64_t SH_FLD_PR_WOBBLE_B = 11924; // 48 -const static uint64_t SH_FLD_PR_WOBBLE_EDGE = 11925; // 48 -const static uint64_t SH_FLD_PSAVE_ANA_REQ_DIS = 11926; // 48 -const static uint64_t SH_FLD_PSAVE_DIG_REQ_DIS = 11927; // 48 -const static uint64_t SH_FLD_PSAVE_REQ_DIS = 11928; // 48 -const static uint64_t SH_FLD_PSCR_OVERRIDE_EN = 11929; // 12 -const static uint64_t SH_FLD_PSEG_MAIN_EN = 11930; // 6 -const static uint64_t SH_FLD_PSEG_MAIN_EN_LEN = 11931; // 6 -const static uint64_t SH_FLD_PSEG_MARGINPD_EN = 11932; // 6 -const static uint64_t SH_FLD_PSEG_MARGINPD_EN_LEN = 11933; // 6 -const static uint64_t SH_FLD_PSEG_MARGINPU_EN = 11934; // 6 -const static uint64_t SH_FLD_PSEG_MARGINPU_EN_LEN = 11935; // 6 -const static uint64_t SH_FLD_PSEG_POST_EN = 11936; // 2 -const static uint64_t SH_FLD_PSEG_POST_EN_LEN = 11937; // 2 -const static uint64_t SH_FLD_PSEG_POST_SEL = 11938; // 2 -const static uint64_t SH_FLD_PSEG_POST_SEL_LEN = 11939; // 2 -const static uint64_t SH_FLD_PSEG_PRE_EN = 11940; // 6 -const static uint64_t SH_FLD_PSEG_PRE_EN_LEN = 11941; // 6 -const static uint64_t SH_FLD_PSEG_PRE_SEL = 11942; // 6 -const static uint64_t SH_FLD_PSEG_PRE_SEL_LEN = 11943; // 6 -const static uint64_t SH_FLD_PSIFSP_ACK_TIMEOUT = 11944; // 1 -const static uint64_t SH_FLD_PSIFSP_DMAR_OUTSTANDING = 11945; // 1 -const static uint64_t SH_FLD_PSIFSP_DMA_ADDR_ERR = 11946; // 1 -const static uint64_t SH_FLD_PSIFSP_DMA_ERR = 11947; // 1 -const static uint64_t SH_FLD_PSIFSP_INT_BUSY = 11948; // 1 -const static uint64_t SH_FLD_PSIFSP_INV_OP = 11949; // 1 -const static uint64_t SH_FLD_PSIFSP_LOAD_OUTSTANDING = 11950; // 1 -const static uint64_t SH_FLD_PSIFSP_MMIO_ADDR_ERR = 11951; // 1 -const static uint64_t SH_FLD_PSIFSP_MMIO_LENGTH_ERR = 11952; // 1 -const static uint64_t SH_FLD_PSIFSP_MMIO_LOAD_TIMEOUT = 11953; // 1 -const static uint64_t SH_FLD_PSIFSP_MMIO_TYPE_ERR = 11954; // 1 -const static uint64_t SH_FLD_PSIFSP_PAGE_FAULT = 11955; // 1 -const static uint64_t SH_FLD_PSIFSP_PERR = 11956; // 1 -const static uint64_t SH_FLD_PSIFSP_TCE_EXTENT_ERR = 11957; // 1 -const static uint64_t SH_FLD_PSIHB2FSP_INJ_CONST = 11958; // 1 -const static uint64_t SH_FLD_PSIHB2FSP_INJ_ERR_BITS = 11959; // 1 -const static uint64_t SH_FLD_PSIHB2FSP_INJ_ERR_BITS_LEN = 11960; // 1 -const static uint64_t SH_FLD_PSIHB2FSP_INJ_ONCE = 11961; // 1 -const static uint64_t SH_FLD_PSIHB2PB_INJ_CONST = 11962; // 1 -const static uint64_t SH_FLD_PSIHB2PB_INJ_ERR_BITS = 11963; // 1 -const static uint64_t SH_FLD_PSIHB2PB_INJ_ERR_BITS_LEN = 11964; // 1 -const static uint64_t SH_FLD_PSIHB2PB_INJ_ONCE = 11965; // 1 -const static uint64_t SH_FLD_PSIHBC_RESET = 11966; // 1 -const static uint64_t SH_FLD_PSIRFACC_C_RXDATA_RDY_ERR = 11967; // 1 -const static uint64_t SH_FLD_PSIRFACC_RADDR_PCK = 11968; // 1 -const static uint64_t SH_FLD_PSIRFACC_RCTRL_PCK = 11969; // 1 -const static uint64_t SH_FLD_PSIRFACC_RDL_FSM_PCK = 11970; // 1 -const static uint64_t SH_FLD_PSIRFACC_RFSM_PCK = 11971; // 1 -const static uint64_t SH_FLD_PSIRFACC_RLINK_STATE_LT_02 = 11972; // 1 -const static uint64_t SH_FLD_PSIRFACC_RXSC_PCK = 11973; // 1 -const static uint64_t SH_FLD_PSIRFACC_TADDR_PCK = 11974; // 1 -const static uint64_t SH_FLD_PSIRFACC_TCTRL_PCK = 11975; // 1 -const static uint64_t SH_FLD_PSIRFACC_TDL_CMD_CTRL_PCK = 11976; // 1 -const static uint64_t SH_FLD_PSIRFACC_TDL_FSM_PCK = 11977; // 1 -const static uint64_t SH_FLD_PSIRFACC_TDL_RETRY_ERR = 11978; // 1 -const static uint64_t SH_FLD_PSIRFACC_TDL_RSP_CTRL_PCK = 11979; // 1 -const static uint64_t SH_FLD_PSIRFACC_TFSM_PCK = 11980; // 1 -const static uint64_t SH_FLD_PSIRFACC_TXSC_PCK = 11981; // 1 -const static uint64_t SH_FLD_PSIRXBFF_DATAO_PCK = 11982; // 1 -const static uint64_t SH_FLD_PSIRXBFF_DATA_PCK = 11983; // 1 -const static uint64_t SH_FLD_PSIRXBFF_RFC_PCK = 11984; // 1 -const static uint64_t SH_FLD_PSIRXEI_SHIFT_PCK = 11985; // 1 -const static uint64_t SH_FLD_PSIRXEI_TRANSMIT_PCK = 11986; // 1 -const static uint64_t SH_FLD_PSIRXINS_DATA_PCK = 11987; // 1 -const static uint64_t SH_FLD_PSIRXINS_OVERRUN = 11988; // 1 -const static uint64_t SH_FLD_PSIRXINS_RFGSHIFT_PCK = 11989; // 1 -const static uint64_t SH_FLD_PSIRXINS_RZRTMP_PCK = 11990; // 1 -const static uint64_t SH_FLD_PSIRXLC_CE_RF = 11991; // 1 -const static uint64_t SH_FLD_PSIRXLC_DATA_BUFF_PCK = 11992; // 1 -const static uint64_t SH_FLD_PSIRXLC_DATA_GXST1_PCK_2N = 11993; // 1 -const static uint64_t SH_FLD_PSIRXLC_DATA_PCK = 11994; // 1 -const static uint64_t SH_FLD_PSIRXLC_FSM_PCK = 11995; // 1 -const static uint64_t SH_FLD_PSIRXLC_RADDR_PCK = 11996; // 1 -const static uint64_t SH_FLD_PSIRXLC_RCTRL_PCK = 11997; // 1 -const static uint64_t SH_FLD_PSIRXLC_UE_RF = 11998; // 1 -const static uint64_t SH_FLD_PSITXBFF_DATA_PCK = 11999; // 1 -const static uint64_t SH_FLD_PSITXBFF_TDO_PCK = 12000; // 1 -const static uint64_t SH_FLD_PSITXBFF_TFC_PCK = 12001; // 1 -const static uint64_t SH_FLD_PSITXEI_SHIFT_PCK = 12002; // 1 -const static uint64_t SH_FLD_PSITXEI_TRANSMIT_PCK = 12003; // 1 -const static uint64_t SH_FLD_PSITXINS_DATA_PCK = 12004; // 1 -const static uint64_t SH_FLD_PSITXINS_PARITY = 12005; // 1 -const static uint64_t SH_FLD_PSITXINS_TZRTMP_PCK = 12006; // 1 -const static uint64_t SH_FLD_PSITXINS_UNDERRUN = 12007; // 1 -const static uint64_t SH_FLD_PSITXLC_CE_GX_2N = 12008; // 1 -const static uint64_t SH_FLD_PSITXLC_CE_RF = 12009; // 1 -const static uint64_t SH_FLD_PSITXLC_DATA_BUFF_PCK = 12010; // 1 -const static uint64_t SH_FLD_PSITXLC_DATA_GXST2_PCK_2N = 12011; // 1 -const static uint64_t SH_FLD_PSITXLC_DATA_GXST3_PCK_2N = 12012; // 1 -const static uint64_t SH_FLD_PSITXLC_FSM_PCK = 12013; // 1 -const static uint64_t SH_FLD_PSITXLC_TADDR_PCK = 12014; // 1 -const static uint64_t SH_FLD_PSITXLC_TCTRL_PCK = 12015; // 1 -const static uint64_t SH_FLD_PSITXLC_TDO_PCK = 12016; // 1 -const static uint64_t SH_FLD_PSITXLC_UE_GX_2N = 12017; // 1 -const static uint64_t SH_FLD_PSITXLC_UE_RF = 12018; // 1 -const static uint64_t SH_FLD_PSI_ALERT1 = 12019; // 1 -const static uint64_t SH_FLD_PSI_ALERT2 = 12020; // 1 -const static uint64_t SH_FLD_PSI_LINK_ENABLE = 12021; // 1 -const static uint64_t SH_FLD_PSI_LINK_INACTIVE_TRANS = 12022; // 1 -const static uint64_t SH_FLD_PSI_RESERVED0 = 12023; // 2 -const static uint64_t SH_FLD_PSI_RESERVED1 = 12024; // 2 -const static uint64_t SH_FLD_PSI_RESERVED2 = 12025; // 2 -const static uint64_t SH_FLD_PSI_RESERVED3 = 12026; // 2 -const static uint64_t SH_FLD_PSI_RESERVED4 = 12027; // 2 -const static uint64_t SH_FLD_PSI_UE = 12028; // 1 -const static uint64_t SH_FLD_PSI_XMIT_ERROR = 12029; // 1 -const static uint64_t SH_FLD_PSL_CMD_SUE = 12030; // 4 -const static uint64_t SH_FLD_PSL_CMD_UE = 12031; // 4 -const static uint64_t SH_FLD_PSL_CREDIT_TIMEOUT_ERR = 12032; // 2 -const static uint64_t SH_FLD_PSSBRIDGE_ONGOING = 12033; // 1 -const static uint64_t SH_FLD_PSS_HAM = 12034; // 3 -const static uint64_t SH_FLD_PSS_HAM_CORE_INTERRUPT_MASK = 12035; // 1 -const static uint64_t SH_FLD_PSTATE_A_THRESHOLD = 12036; // 24 -const static uint64_t SH_FLD_PSTATE_A_THRESHOLD_LEN = 12037; // 24 -const static uint64_t SH_FLD_PSTATE_B_THRESHOLD = 12038; // 24 -const static uint64_t SH_FLD_PSTATE_B_THRESHOLD_LEN = 12039; // 24 -const static uint64_t SH_FLD_PS_SPARE1 = 12040; // 1 -const static uint64_t SH_FLD_PTCR = 12041; // 1 -const static uint64_t SH_FLD_PTCR_LEN = 12042; // 1 -const static uint64_t SH_FLD_PULL_EMPTY = 12043; // 4 -const static uint64_t SH_FLD_PULL_ENABLE = 12044; // 4 -const static uint64_t SH_FLD_PULL_FULL = 12045; // 4 -const static uint64_t SH_FLD_PULL_INTR_ACTION_0_1 = 12046; // 4 -const static uint64_t SH_FLD_PULL_INTR_ACTION_0_1_LEN = 12047; // 4 -const static uint64_t SH_FLD_PULL_LENGTH = 12048; // 4 -const static uint64_t SH_FLD_PULL_LENGTH_LEN = 12049; // 4 -const static uint64_t SH_FLD_PULL_READ_PTR = 12050; // 4 -const static uint64_t SH_FLD_PULL_READ_PTR_LEN = 12051; // 4 -const static uint64_t SH_FLD_PULL_READ_UNDERFLOW = 12052; // 4 -const static uint64_t SH_FLD_PULL_READ_UNDERFLOW_EN = 12053; // 4 -const static uint64_t SH_FLD_PULL_REGION = 12054; // 4 -const static uint64_t SH_FLD_PULL_REGION_LEN = 12055; // 4 -const static uint64_t SH_FLD_PULL_START = 12056; // 4 -const static uint64_t SH_FLD_PULL_START_LEN = 12057; // 4 -const static uint64_t SH_FLD_PULL_WRITE_OVERFLOW = 12058; // 4 -const static uint64_t SH_FLD_PULL_WRITE_PTR = 12059; // 4 -const static uint64_t SH_FLD_PULL_WRITE_PTR_LEN = 12060; // 4 -const static uint64_t SH_FLD_PULSE1_CNTR = 12061; // 1 -const static uint64_t SH_FLD_PULSE1_CNTR_LEN = 12062; // 1 -const static uint64_t SH_FLD_PULSE2_CNTR = 12063; // 1 -const static uint64_t SH_FLD_PULSE2_CNTR_LEN = 12064; // 1 -const static uint64_t SH_FLD_PULSE_DELAY = 12065; // 43 -const static uint64_t SH_FLD_PULSE_DELAY_LEN = 12066; // 43 -const static uint64_t SH_FLD_PUMP_MODE = 12067; // 1 -const static uint64_t SH_FLD_PUP_LITE_WAIT_SEL = 12068; // 4 -const static uint64_t SH_FLD_PUP_LITE_WAIT_SEL_LEN = 12069; // 4 -const static uint64_t SH_FLD_PUSH_EMPTY = 12070; // 6 -const static uint64_t SH_FLD_PUSH_ENABLE = 12071; // 6 -const static uint64_t SH_FLD_PUSH_FULL = 12072; // 6 -const static uint64_t SH_FLD_PUSH_INTR_ACTION_0_1 = 12073; // 6 -const static uint64_t SH_FLD_PUSH_INTR_ACTION_0_1_LEN = 12074; // 6 -const static uint64_t SH_FLD_PUSH_LENGTH = 12075; // 6 -const static uint64_t SH_FLD_PUSH_LENGTH_LEN = 12076; // 6 -const static uint64_t SH_FLD_PUSH_READ_PTR = 12077; // 6 -const static uint64_t SH_FLD_PUSH_READ_PTR_LEN = 12078; // 6 -const static uint64_t SH_FLD_PUSH_READ_UNDERFLOW = 12079; // 4 -const static uint64_t SH_FLD_PUSH_REGION = 12080; // 4 -const static uint64_t SH_FLD_PUSH_REGION_LEN = 12081; // 4 -const static uint64_t SH_FLD_PUSH_START = 12082; // 6 -const static uint64_t SH_FLD_PUSH_START_LEN = 12083; // 6 -const static uint64_t SH_FLD_PUSH_WRITE_OVERFLOW = 12084; // 4 -const static uint64_t SH_FLD_PUSH_WRITE_OVERFLOW_EN = 12085; // 4 -const static uint64_t SH_FLD_PUSH_WRITE_PTR = 12086; // 6 -const static uint64_t SH_FLD_PUSH_WRITE_PTR_LEN = 12087; // 6 -const static uint64_t SH_FLD_PU_BIT_ENABLES = 12088; // 1 -const static uint64_t SH_FLD_PU_BIT_ENABLES_LEN = 12089; // 1 -const static uint64_t SH_FLD_PU_COUNTS = 12090; // 8 -const static uint64_t SH_FLD_PU_COUNTS_LEN = 12091; // 8 -const static uint64_t SH_FLD_PVREF_ERROR_EN = 12092; // 1 -const static uint64_t SH_FLD_PVREF_ERROR_EN_LEN = 12093; // 1 -const static uint64_t SH_FLD_PVREF_ERROR_FINE = 12094; // 1 -const static uint64_t SH_FLD_PVREF_ERROR_GROSS = 12095; // 1 -const static uint64_t SH_FLD_PVREF_FAIL = 12096; // 12 -const static uint64_t SH_FLD_PVTN = 12097; // 16 -const static uint64_t SH_FLD_PVTNL_ENC = 12098; // 1 -const static uint64_t SH_FLD_PVTNL_ENC_LEN = 12099; // 1 -const static uint64_t SH_FLD_PVTN_LEN = 12100; // 16 -const static uint64_t SH_FLD_PVTP = 12101; // 16 -const static uint64_t SH_FLD_PVTPL_ENC = 12102; // 1 -const static uint64_t SH_FLD_PVTPL_ENC_LEN = 12103; // 1 -const static uint64_t SH_FLD_PVTP_LEN = 12104; // 16 -const static uint64_t SH_FLD_QPPM_ONGOING = 12105; // 24 -const static uint64_t SH_FLD_QPPM_RDATA = 12106; // 24 -const static uint64_t SH_FLD_QPPM_RDATA_LEN = 12107; // 24 -const static uint64_t SH_FLD_QPPM_REG = 12108; // 24 -const static uint64_t SH_FLD_QPPM_REG_LEN = 12109; // 24 -const static uint64_t SH_FLD_QPPM_RNW = 12110; // 24 -const static uint64_t SH_FLD_QPPM_STATUS = 12111; // 24 -const static uint64_t SH_FLD_QPPM_STATUS_LEN = 12112; // 24 -const static uint64_t SH_FLD_QPPM_WDATA = 12113; // 24 -const static uint64_t SH_FLD_QPPM_WDATA_LEN = 12114; // 24 -const static uint64_t SH_FLD_QUA = 12115; // 8 -const static uint64_t SH_FLD_QUAD_CHECKSTOP = 12116; // 12 -const static uint64_t SH_FLD_QUAD_CLK_SB_OVERRIDE = 12117; // 24 -const static uint64_t SH_FLD_QUAD_CLK_SW_OVERRIDE = 12118; // 24 -const static uint64_t SH_FLD_QUAD_SEL = 12119; // 6 -const static uint64_t SH_FLD_QUAD_SEL_LEN = 12120; // 6 -const static uint64_t SH_FLD_QUAD_STOPPED = 12121; // 1 -const static uint64_t SH_FLD_QUAD_STOPPED_LEN = 12122; // 1 -const static uint64_t SH_FLD_QUA_LEN = 12123; // 8 -const static uint64_t SH_FLD_QUA_V = 12124; // 8 -const static uint64_t SH_FLD_QUEUED_RD_EN = 12125; // 12 -const static uint64_t SH_FLD_QUEUED_WR_EN = 12126; // 12 -const static uint64_t SH_FLD_QUEUE_DISABLE = 12127; // 6 -const static uint64_t SH_FLD_QUEUE_NOT_EMPTY = 12128; // 6 -const static uint64_t SH_FLD_QUIESCE = 12129; // 1 -const static uint64_t SH_FLD_QUIESCED = 12130; // 1 -const static uint64_t SH_FLD_QUIESCE_ACHEIVED = 12131; // 1 -const static uint64_t SH_FLD_QUIESCE_AUTO_RESET = 12132; // 1 -const static uint64_t SH_FLD_QUIESCE_FAILED = 12133; // 1 -const static uint64_t SH_FLD_QUIESCE_PB = 12134; // 1 -const static uint64_t SH_FLD_QUIESCE_REQUEST = 12135; // 1 -const static uint64_t SH_FLD_R = 12136; // 8 -const static uint64_t SH_FLD_R0_COUNT = 12137; // 12 -const static uint64_t SH_FLD_R0_COUNT_LEN = 12138; // 12 -const static uint64_t SH_FLD_R15_BIT_MAP = 12139; // 8 -const static uint64_t SH_FLD_R15_BIT_MAP_LEN = 12140; // 8 -const static uint64_t SH_FLD_R16_BIT_MAP = 12141; // 8 -const static uint64_t SH_FLD_R16_BIT_MAP_LEN = 12142; // 8 -const static uint64_t SH_FLD_R17_BIT_MAP = 12143; // 8 -const static uint64_t SH_FLD_R17_BIT_MAP_LEN = 12144; // 8 -const static uint64_t SH_FLD_R1_COUNT = 12145; // 12 -const static uint64_t SH_FLD_R1_COUNT_LEN = 12146; // 12 -const static uint64_t SH_FLD_R2_COUNT = 12147; // 12 -const static uint64_t SH_FLD_R2_COUNT_LEN = 12148; // 12 -const static uint64_t SH_FLD_RAM_OVERRIDE = 12149; // 24 -const static uint64_t SH_FLD_RAND_ADDR_ALL_ADDR_MODE_EN = 12150; // 2 -const static uint64_t SH_FLD_RAND_EVENT = 12151; // 1 -const static uint64_t SH_FLD_RAND_EVENT_LEN = 12152; // 1 -const static uint64_t SH_FLD_RANGE = 12153; // 1 -const static uint64_t SH_FLD_RANGE_LEN = 12154; // 1 -const static uint64_t SH_FLD_RANK = 12155; // 8 -const static uint64_t SH_FLD_RANK_LEN = 12156; // 8 -const static uint64_t SH_FLD_RANK_OVERRIDE = 12157; // 8 -const static uint64_t SH_FLD_RANK_OVERRIDE_VALUE = 12158; // 8 -const static uint64_t SH_FLD_RANK_OVERRIDE_VALUE_LEN = 12159; // 8 -const static uint64_t SH_FLD_RANK_PAIR = 12160; // 8 -const static uint64_t SH_FLD_RANK_PAIR_LEN = 12161; // 8 -const static uint64_t SH_FLD_RANK_SM_1HOT = 12162; // 8 -const static uint64_t SH_FLD_RATE = 12163; // 14 -const static uint64_t SH_FLD_RATE_LEN = 12164; // 14 -const static uint64_t SH_FLD_RC = 12165; // 8 -const static uint64_t SH_FLD_RCDAT_RD_PARITY_ERR = 12166; // 12 -const static uint64_t SH_FLD_RCD_PARITY_ERROR = 12167; // 16 -const static uint64_t SH_FLD_RCE_COUNT = 12168; // 2 -const static uint64_t SH_FLD_RCE_COUNT_LEN = 12169; // 2 -const static uint64_t SH_FLD_RCE_ETE_ATTN = 12170; // 10 -const static uint64_t SH_FLD_RCMD0_ADDR_PARITY_ERROR = 12171; // 2 -const static uint64_t SH_FLD_RCMD0_ADDR_PERR = 12172; // 1 -const static uint64_t SH_FLD_RCMD0_TTAG_PERR = 12173; // 1 -const static uint64_t SH_FLD_RCMD1_ADDR_PARITY_ERROR = 12174; // 2 -const static uint64_t SH_FLD_RCMD1_ADDR_PERR = 12175; // 1 -const static uint64_t SH_FLD_RCMD1_TTAG_PERR = 12176; // 1 -const static uint64_t SH_FLD_RCMD2_ADDR_PARITY_ERROR = 12177; // 2 -const static uint64_t SH_FLD_RCMD2_ADDR_PERR = 12178; // 1 -const static uint64_t SH_FLD_RCMD2_TTAG_PERR = 12179; // 1 -const static uint64_t SH_FLD_RCMD3_ADDR_PARITY_ERROR = 12180; // 2 -const static uint64_t SH_FLD_RCMD3_ADDR_PERR = 12181; // 1 -const static uint64_t SH_FLD_RCMD3_TTAG_PERR = 12182; // 1 -const static uint64_t SH_FLD_RCMD_ADDR_P_ERR = 12183; // 12 -const static uint64_t SH_FLD_RCMD_ADDR_P_ERR_LEN = 12184; // 12 -const static uint64_t SH_FLD_RCMD_ERR_INJ = 12185; // 8 -const static uint64_t SH_FLD_RCMD_TTAG_P_ERR = 12186; // 12 -const static uint64_t SH_FLD_RCMD_TTAG_P_ERR_LEN = 12187; // 12 -const static uint64_t SH_FLD_RCV_BRDCST_GROUP = 12188; // 1 -const static uint64_t SH_FLD_RCV_BRDCST_GROUP_LEN = 12189; // 1 -const static uint64_t SH_FLD_RCV_CAPTURE = 12190; // 1 -const static uint64_t SH_FLD_RCV_CAPTURE_LEN = 12191; // 1 -const static uint64_t SH_FLD_RCV_CHIPID = 12192; // 1 -const static uint64_t SH_FLD_RCV_CHIPID_LEN = 12193; // 1 -const static uint64_t SH_FLD_RCV_CREDIT_OVERFLOW_ENA = 12194; // 6 -const static uint64_t SH_FLD_RCV_DATATO_DIV = 12195; // 1 -const static uint64_t SH_FLD_RCV_DATATO_DIV_LEN = 12196; // 1 -const static uint64_t SH_FLD_RCV_ERROR = 12197; // 1 -const static uint64_t SH_FLD_RCV_GROUPID = 12198; // 1 -const static uint64_t SH_FLD_RCV_GROUPID_LEN = 12199; // 1 -const static uint64_t SH_FLD_RCV_IN_PROGRESS = 12200; // 1 -const static uint64_t SH_FLD_RCV_PB_OP_HANG_ERR = 12201; // 1 -const static uint64_t SH_FLD_RCV_RESERVATION_SET = 12202; // 1 -const static uint64_t SH_FLD_RCV_RESET = 12203; // 1 -const static uint64_t SH_FLD_RCV_TOD_STATE = 12204; // 1 -const static uint64_t SH_FLD_RCV_TOD_STATE_LEN = 12205; // 1 -const static uint64_t SH_FLD_RCV_TTAG_PARITY_ERR = 12206; // 1 -const static uint64_t SH_FLD_RCV_WRITE_IN_PROGRESS = 12207; // 1 -const static uint64_t SH_FLD_RC_ADDR_PAR = 12208; // 1 -const static uint64_t SH_FLD_RC_ENABLE_AUTO_RECAL = 12209; // 2 -const static uint64_t SH_FLD_RC_ENABLE_BER_TEST = 12210; // 4 -const static uint64_t SH_FLD_RC_ENABLE_CM_COARSE_CAL = 12211; // 6 -const static uint64_t SH_FLD_RC_ENABLE_CM_FINE_CAL = 12212; // 6 -const static uint64_t SH_FLD_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 12213; // 6 -const static uint64_t SH_FLD_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 12214; // 6 -const static uint64_t SH_FLD_RC_ENABLE_CTLE_COARSE_CAL = 12215; // 6 -const static uint64_t SH_FLD_RC_ENABLE_CTLE_EDGE_OFFSET_CAL = 12216; // 2 -const static uint64_t SH_FLD_RC_ENABLE_CTLE_EDGE_TRACK_ONLY = 12217; // 4 -const static uint64_t SH_FLD_RC_ENABLE_DAC_H1_CAL = 12218; // 6 -const static uint64_t SH_FLD_RC_ENABLE_DAC_H1_TO_A_CAL = 12219; // 4 -const static uint64_t SH_FLD_RC_ENABLE_DDC = 12220; // 6 -const static uint64_t SH_FLD_RC_ENABLE_DFE_H1_CAL = 12221; // 6 -const static uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_CAL = 12222; // 4 -const static uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP = 12223; // 4 -const static uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 12224; // 4 -const static uint64_t SH_FLD_RC_ENABLE_DFE_VOLTAGE_MODE = 12225; // 4 -const static uint64_t SH_FLD_RC_ENABLE_H1AP_TWEAK = 12226; // 6 -const static uint64_t SH_FLD_RC_ENABLE_INTEG_LATCH_OFFSET_CAL = 12227; // 6 -const static uint64_t SH_FLD_RC_ENABLE_RESULT_CHECK = 12228; // 4 -const static uint64_t SH_FLD_RC_ENABLE_VGA_AMAX_MODE = 12229; // 6 -const static uint64_t SH_FLD_RC_ENABLE_VGA_CAL = 12230; // 6 -const static uint64_t SH_FLD_RC_ENABLE_VGA_EDGE_OFFSET_CAL = 12231; // 2 -const static uint64_t SH_FLD_RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV = 12232; // 12 -const static uint64_t SH_FLD_RC_LOAD_RECIVED_PB_CRESP_ADR_ERR = 12233; // 12 -const static uint64_t SH_FLD_RC_LOAD_RECIVED_PB_CRESP_ADR_ERR_FOR_HYP = 12234; // 12 -const static uint64_t SH_FLD_RC_MASK = 12235; // 8 -const static uint64_t SH_FLD_RC_POWBUS_DATA_CE_ERR_FROM_F2CHK = 12236; // 12 -const static uint64_t SH_FLD_RC_POWBUS_DATA_SUE_ERR_FROM_F2CHK = 12237; // 12 -const static uint64_t SH_FLD_RC_POWBUS_DATA_UE_ERR_FROM_F2CHK = 12238; // 12 -const static uint64_t SH_FLD_RC_POWERBUS_DATA_TIMEOUT = 12239; // 12 -const static uint64_t SH_FLD_RC_SLOWDOWN_TIMEOUT_SEL = 12240; // 6 -const static uint64_t SH_FLD_RC_SLOWDOWN_TIMEOUT_SEL_LEN = 12241; // 6 -const static uint64_t SH_FLD_RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV = 12242; // 12 -const static uint64_t SH_FLD_RC_STORE_RECIVED_PB_CRESP_ADR_ERR = 12243; // 12 -const static uint64_t SH_FLD_RC_TTAG_PAR = 12244; // 1 -const static uint64_t SH_FLD_RDADDR_ARB_BAD_HAND = 12245; // 2 -const static uint64_t SH_FLD_RDATA = 12246; // 1 -const static uint64_t SH_FLD_RDATA_LEN = 12247; // 1 -const static uint64_t SH_FLD_RDBUFF_ALLOC = 12248; // 2 -const static uint64_t SH_FLD_RDBUFF_ALLOC_LEN = 12249; // 2 -const static uint64_t SH_FLD_RDCLK_ALIGN = 12250; // 8 -const static uint64_t SH_FLD_RDCMP = 12251; // 2 -const static uint64_t SH_FLD_RDCMP_LEN = 12252; // 2 -const static uint64_t SH_FLD_RDIV = 12253; // 14 -const static uint64_t SH_FLD_RDIV_LEN = 12254; // 10 -const static uint64_t SH_FLD_RDQ_FSM_PERR = 12255; // 1 -const static uint64_t SH_FLD_RDQ_OVERFLOW = 12256; // 1 -const static uint64_t SH_FLD_RDWR_ACCESS_EN = 12257; // 2 -const static uint64_t SH_FLD_RDWR_ADDR = 12258; // 2 -const static uint64_t SH_FLD_RDWR_ADDR_LEN = 12259; // 2 -const static uint64_t SH_FLD_RDWR_OP_BUSY = 12260; // 1 -const static uint64_t SH_FLD_RDWR_RDWR_DATA = 12261; // 2 -const static uint64_t SH_FLD_RDWR_RDWR_DATA_LEN = 12262; // 2 -const static uint64_t SH_FLD_RDWR_READ_STATUS = 12263; // 2 -const static uint64_t SH_FLD_RDWR_REQ_PEND = 12264; // 2 -const static uint64_t SH_FLD_RDWR_UPDATE_ERROR = 12265; // 2 -const static uint64_t SH_FLD_RDWR_WRITE_MODE = 12266; // 2 -const static uint64_t SH_FLD_RDWR_WRITE_STATUS = 12267; // 2 -const static uint64_t SH_FLD_RDWR_WR_ENABLE = 12268; // 2 -const static uint64_t SH_FLD_RDX_BUS0_STG1_SEL = 12269; // 1 -const static uint64_t SH_FLD_RDX_BUS0_STG2_SEL = 12270; // 1 -const static uint64_t SH_FLD_RDX_BUS1_STG1_SEL = 12271; // 1 -const static uint64_t SH_FLD_RDX_BUS1_STG2_SEL = 12272; // 1 -const static uint64_t SH_FLD_RD_ADDR_0_7 = 12273; // 1 -const static uint64_t SH_FLD_RD_ADDR_0_7_LEN = 12274; // 1 -const static uint64_t SH_FLD_RD_ARE_ERRORS = 12275; // 9 -const static uint64_t SH_FLD_RD_ARE_ERRORS_MASK = 12276; // 9 -const static uint64_t SH_FLD_RD_CNTL = 12277; // 8 -const static uint64_t SH_FLD_RD_CNTL_MASK = 12278; // 8 -const static uint64_t SH_FLD_RD_DATA_COUNT = 12279; // 1 -const static uint64_t SH_FLD_RD_DATA_COUNT_LEN = 12280; // 1 -const static uint64_t SH_FLD_RD_DATA_PARITY_ERROR = 12281; // 3 -const static uint64_t SH_FLD_RD_GO_M_QOS = 12282; // 2 -const static uint64_t SH_FLD_RD_MACHINE_HANG_ERR = 12283; // 12 -const static uint64_t SH_FLD_RD_RST_INTRPT_FACES = 12284; // 1 -const static uint64_t SH_FLD_RD_RST_INTRPT_PIB = 12285; // 1 -const static uint64_t SH_FLD_RD_SCOPE = 12286; // 24 -const static uint64_t SH_FLD_RD_SCOPE_LEN = 12287; // 24 -const static uint64_t SH_FLD_RD_SLVNUM = 12288; // 6 -const static uint64_t SH_FLD_RD_SLVNUM_LEN = 12289; // 6 -const static uint64_t SH_FLD_READ_ASYNC_INTERFACE_PARITY_ERROR = 12290; // 8 -const static uint64_t SH_FLD_READ_ASYNC_INTERFACE_SEQUENCE_ERROR = 12291; // 8 -const static uint64_t SH_FLD_READ_BUFFER_OVERFLOW_ERROR = 12292; // 8 -const static uint64_t SH_FLD_READ_COMPARE_REQUIRED = 12293; // 64 -const static uint64_t SH_FLD_READ_COMPLETE = 12294; // 1 -const static uint64_t SH_FLD_READ_CONTINUE_0 = 12295; // 1 -const static uint64_t SH_FLD_READ_CONTINUE_1 = 12296; // 1 -const static uint64_t SH_FLD_READ_CONTINUE_2 = 12297; // 1 -const static uint64_t SH_FLD_READ_CONTINUE_3 = 12298; // 1 -const static uint64_t SH_FLD_READ_COUNT = 12299; // 8 -const static uint64_t SH_FLD_READ_COUNT_LEN = 12300; // 8 -const static uint64_t SH_FLD_READ_CRD_POOL = 12301; // 1 -const static uint64_t SH_FLD_READ_CRD_POOL_LEN = 12302; // 1 -const static uint64_t SH_FLD_READ_CTR = 12303; // 8 -const static uint64_t SH_FLD_READ_ENABLE = 12304; // 129 -const static uint64_t SH_FLD_READ_ENABLE_0 = 12305; // 1 -const static uint64_t SH_FLD_READ_ENABLE_1 = 12306; // 1 -const static uint64_t SH_FLD_READ_ENABLE_2 = 12307; // 1 -const static uint64_t SH_FLD_READ_ENABLE_3 = 12308; // 1 -const static uint64_t SH_FLD_READ_EPSILON_MODE = 12309; // 2 -const static uint64_t SH_FLD_READ_EPSILON_TIER0 = 12310; // 2 -const static uint64_t SH_FLD_READ_EPSILON_TIER0_LEN = 12311; // 2 -const static uint64_t SH_FLD_READ_EPSILON_TIER1 = 12312; // 2 -const static uint64_t SH_FLD_READ_EPSILON_TIER1_LEN = 12313; // 2 -const static uint64_t SH_FLD_READ_EPSILON_TIER2 = 12314; // 2 -const static uint64_t SH_FLD_READ_EPSILON_TIER2_LEN = 12315; // 2 -const static uint64_t SH_FLD_READ_ERR_INJECT0 = 12316; // 8 -const static uint64_t SH_FLD_READ_ERR_INJECT0_LEN = 12317; // 8 -const static uint64_t SH_FLD_READ_INVALID_FACES = 12318; // 1 -const static uint64_t SH_FLD_READ_INVALID_PIB = 12319; // 1 -const static uint64_t SH_FLD_READ_LATENCY_OFFSET = 12320; // 8 -const static uint64_t SH_FLD_READ_LATENCY_OFFSET_LEN = 12321; // 8 -const static uint64_t SH_FLD_READ_NOT_WRITE_0 = 12322; // 1 -const static uint64_t SH_FLD_READ_NOT_WRITE_1 = 12323; // 1 -const static uint64_t SH_FLD_READ_NOT_WRITE_2 = 12324; // 1 -const static uint64_t SH_FLD_READ_NOT_WRITE_3 = 12325; // 1 -const static uint64_t SH_FLD_READ_NVLD = 12326; // 1 -const static uint64_t SH_FLD_READ_OR_WRITE_DATA = 12327; // 64 -const static uint64_t SH_FLD_READ_OR_WRITE_DATA_LEN = 12328; // 64 -const static uint64_t SH_FLD_READ_PAR_NOT_SEQ = 12329; // 8 -const static uint64_t SH_FLD_READ_PREFETCH_CTL = 12330; // 4 -const static uint64_t SH_FLD_READ_PREFETCH_CTL_LEN = 12331; // 4 -const static uint64_t SH_FLD_READ_RAMP_PERF_TRESHOLD = 12332; // 4 -const static uint64_t SH_FLD_READ_RAMP_PERF_TRESHOLD_LEN = 12333; // 4 -const static uint64_t SH_FLD_READ_RESPONSE_DELAY_ENABLE = 12334; // 2 -const static uint64_t SH_FLD_READ_RST_INTERRUPT_FACES = 12335; // 1 -const static uint64_t SH_FLD_READ_RST_INTERRUPT_PIB = 12336; // 1 -const static uint64_t SH_FLD_READ_SPECULATION_DISABLE_THRESHOLD = 12337; // 4 -const static uint64_t SH_FLD_READ_SPECULATION_DISABLE_THRESHOLD_LEN = 12338; // 4 -const static uint64_t SH_FLD_READ_TTYPE = 12339; // 4 -const static uint64_t SH_FLD_RECAL_ABORT = 12340; // 48 -const static uint64_t SH_FLD_RECAL_ABORT_DL_MASK = 12341; // 2 -const static uint64_t SH_FLD_RECAL_DONE_DL_MASK = 12342; // 2 -const static uint64_t SH_FLD_RECAL_ERROR = 12343; // 8 -const static uint64_t SH_FLD_RECAL_MAX_SPARES_EXCEEDED = 12344; // 8 -const static uint64_t SH_FLD_RECAL_REQ = 12345; // 48 -const static uint64_t SH_FLD_RECAL_REQ_DL_MASK = 12346; // 2 -const static uint64_t SH_FLD_RECAL_SPARE_DEPLOYED = 12347; // 8 -const static uint64_t SH_FLD_RECEIVED = 12348; // 1 -const static uint64_t SH_FLD_RECEIVED_ERROR = 12349; // 1 -const static uint64_t SH_FLD_RECEIVER_MODE = 12350; // 3 -const static uint64_t SH_FLD_RECEIVER_MODE_LEN = 12351; // 3 -const static uint64_t SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER = 12352; // 1 -const static uint64_t SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER_LEN = 12353; // 1 -const static uint64_t SH_FLD_RECOVERABLE_ERROR = 12354; // 2 -const static uint64_t SH_FLD_RECOVERY_FAILED = 12355; // 6 -const static uint64_t SH_FLD_RECOVERY_HANG_DETECTED = 12356; // 2 -const static uint64_t SH_FLD_REC_PB_SM_ERROR_ERR = 12357; // 2 -const static uint64_t SH_FLD_REC_SM_ERROR_ERR = 12358; // 2 -const static uint64_t SH_FLD_REC_UPDATE_ERROR = 12359; // 2 -const static uint64_t SH_FLD_REDIS_PRIORITY = 12360; // 1 -const static uint64_t SH_FLD_REDIS_PRIORITY_LEN = 12361; // 1 -const static uint64_t SH_FLD_REDIS_RSD = 12362; // 1 -const static uint64_t SH_FLD_REDIS_RSD_LEN = 12363; // 1 -const static uint64_t SH_FLD_REFCLKSEL = 12364; // 4 -const static uint64_t SH_FLD_REFCLK_0_TERM_DIS_DC = 12365; // 1 -const static uint64_t SH_FLD_REFCLK_1_TERM_DIS_DC = 12366; // 1 -const static uint64_t SH_FLD_REFISINK = 12367; // 3 -const static uint64_t SH_FLD_REFISINK_LEN = 12368; // 3 -const static uint64_t SH_FLD_REFISRC = 12369; // 3 -const static uint64_t SH_FLD_REFISRC_LEN = 12370; // 3 -const static uint64_t SH_FLD_REFRESH_ALL_RANKS = 12371; // 8 -const static uint64_t SH_FLD_REFRESH_BLOCK_CONFIG = 12372; // 8 -const static uint64_t SH_FLD_REFRESH_BLOCK_CONFIG_LEN = 12373; // 8 -const static uint64_t SH_FLD_REFRESH_CONTROL = 12374; // 8 -const static uint64_t SH_FLD_REFRESH_CONTROL_LEN = 12375; // 8 -const static uint64_t SH_FLD_REFRESH_COUNT = 12376; // 8 -const static uint64_t SH_FLD_REFRESH_COUNT_LEN = 12377; // 8 -const static uint64_t SH_FLD_REFRESH_INTERVAL = 12378; // 8 -const static uint64_t SH_FLD_REFRESH_INTERVAL_LEN = 12379; // 8 -const static uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_EN = 12380; // 2 -const static uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL = 12381; // 2 -const static uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN = 12382; // 2 -const static uint64_t SH_FLD_REFRESH_OVERRUN = 12383; // 16 -const static uint64_t SH_FLD_REFVREG = 12384; // 3 -const static uint64_t SH_FLD_REFVREG_LEN = 12385; // 3 -const static uint64_t SH_FLD_REG = 12386; // 19 -const static uint64_t SH_FLD_REGF = 12387; // 43 -const static uint64_t SH_FLD_REGION = 12388; // 72 -const static uint64_t SH_FLD_REGION_LEN = 12389; // 72 -const static uint64_t SH_FLD_REGISTER = 12390; // 3 -const static uint64_t SH_FLD_REGISTER_ARRAY_PE = 12391; // 9 -const static uint64_t SH_FLD_REGISTER_ARRAY_PE_MASK = 12392; // 9 -const static uint64_t SH_FLD_REGISTER_LEN = 12393; // 3 -const static uint64_t SH_FLD_REGISTER_PE = 12394; // 4 -const static uint64_t SH_FLD_REGISTER_VALID = 12395; // 4 -const static uint64_t SH_FLD_REGS = 12396; // 1 -const static uint64_t SH_FLD_REGSEL = 12397; // 4 -const static uint64_t SH_FLD_REGSEL_LEN = 12398; // 4 -const static uint64_t SH_FLD_REGS_LEN = 12399; // 1 -const static uint64_t SH_FLD_REG_ADDR_LEN = 12400; // 1 -const static uint64_t SH_FLD_REG_ADDR_LEN_0 = 12401; // 1 -const static uint64_t SH_FLD_REG_ADDR_LEN_0_LEN = 12402; // 1 -const static uint64_t SH_FLD_REG_ADDR_LEN_1 = 12403; // 1 -const static uint64_t SH_FLD_REG_ADDR_LEN_1_LEN = 12404; // 1 -const static uint64_t SH_FLD_REG_ADDR_LEN_2 = 12405; // 1 -const static uint64_t SH_FLD_REG_ADDR_LEN_2_LEN = 12406; // 1 -const static uint64_t SH_FLD_REG_ADDR_LEN_3 = 12407; // 1 -const static uint64_t SH_FLD_REG_ADDR_LEN_3_LEN = 12408; // 1 -const static uint64_t SH_FLD_REG_ADDR_LEN_LEN = 12409; // 1 -const static uint64_t SH_FLD_REG_ENABLE = 12410; // 1 -const static uint64_t SH_FLD_REG_FIFO_SIZE_EQ_1 = 12411; // 1 -const static uint64_t SH_FLD_REG_LEN = 12412; // 19 -const static uint64_t SH_FLD_REG_UNUSED = 12413; // 1 -const static uint64_t SH_FLD_REG_UNUSED_LEN = 12414; // 1 -const static uint64_t SH_FLD_REG_WAKEUP_C0 = 12415; // 24 -const static uint64_t SH_FLD_REG_WAKEUP_C1 = 12416; // 24 -const static uint64_t SH_FLD_REINIT_CREDITS = 12417; // 1 -const static uint64_t SH_FLD_REJECTED_PASTE_CMD = 12418; // 2 -const static uint64_t SH_FLD_REL_ASYNC_PARITY_ERROR = 12419; // 8 -const static uint64_t SH_FLD_REL_ASYNC_SEQUENCE_ERROR = 12420; // 8 -const static uint64_t SH_FLD_REL_MERGE_ASYNC_PARITY_ERROR = 12421; // 8 -const static uint64_t SH_FLD_REL_MERGE_ASYNC_SEQUENCE_ERROR = 12422; // 8 -const static uint64_t SH_FLD_REMAINING_WORDS = 12423; // 1 -const static uint64_t SH_FLD_REMAINING_WORDS_LEN = 12424; // 1 -const static uint64_t SH_FLD_REMAP_DEST = 12425; // 1 -const static uint64_t SH_FLD_REMAP_DEST_LEN = 12426; // 1 -const static uint64_t SH_FLD_REMAP_SOURCE = 12427; // 1 -const static uint64_t SH_FLD_REMAP_SOURCE_LEN = 12428; // 1 -const static uint64_t SH_FLD_REMOTE_NODAL_EPSILON = 12429; // 8 -const static uint64_t SH_FLD_REMOTE_NODAL_EPSILON_LEN = 12430; // 8 -const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION = 12431; // 1 -const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR = 12432; // 1 -const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR_LEN = 12433; // 1 -const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_LEN = 12434; // 1 -const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_M_CPS_DISABLE = 12435; // 1 -const static uint64_t SH_FLD_REMOTE_SYNC_DISABLE = 12436; // 1 -const static uint64_t SH_FLD_REMOTE_SYNC_ERROR_DISABLE = 12437; // 1 -const static uint64_t SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX = 12438; // 1 -const static uint64_t SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX_LEN = 12439; // 1 -const static uint64_t SH_FLD_REM_0 = 12440; // 6 -const static uint64_t SH_FLD_REM_0_LEN = 12441; // 6 -const static uint64_t SH_FLD_REM_1 = 12442; // 6 -const static uint64_t SH_FLD_REM_1_LEN = 12443; // 6 -const static uint64_t SH_FLD_REM_2 = 12444; // 6 -const static uint64_t SH_FLD_REM_2_LEN = 12445; // 6 -const static uint64_t SH_FLD_REM_3 = 12446; // 6 -const static uint64_t SH_FLD_REM_3_LEN = 12447; // 6 -const static uint64_t SH_FLD_REPAIR_DONE = 12448; // 4 -const static uint64_t SH_FLD_REPAIR_FAILED = 12449; // 4 -const static uint64_t SH_FLD_REPEAT_CMD_CNT = 12450; // 64 -const static uint64_t SH_FLD_REPEAT_CMD_CNT_LEN = 12451; // 64 -const static uint64_t SH_FLD_REPR = 12452; // 43 -const static uint64_t SH_FLD_REPTEST_ENABLE = 12453; // 1 -const static uint64_t SH_FLD_REPTEST_MATCH_TH = 12454; // 1 -const static uint64_t SH_FLD_REPTEST_MATCH_TH_LEN = 12455; // 1 -const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0 = 12456; // 1 -const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0_LEN = 12457; // 1 -const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1 = 12458; // 1 -const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN = 12459; // 1 -const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_TH = 12460; // 1 -const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_TH_LEN = 12461; // 1 -const static uint64_t SH_FLD_REQ = 12462; // 43 -const static uint64_t SH_FLD_REQUEST = 12463; // 1 -const static uint64_t SH_FLD_REQUEST_LEN = 12464; // 1 -const static uint64_t SH_FLD_REQ_INTR_PAYLOAD = 12465; // 30 -const static uint64_t SH_FLD_REQ_INTR_PAYLOAD_LEN = 12466; // 30 -const static uint64_t SH_FLD_REQ_INTR_TYPE = 12467; // 30 -const static uint64_t SH_FLD_REQ_INTR_TYPE_LEN = 12468; // 30 -const static uint64_t SH_FLD_REQ_RESET_FR_SBE = 12469; // 1 -const static uint64_t SH_FLD_REQ_RESET_FR_SP = 12470; // 1 -const static uint64_t SH_FLD_REQ_STOP_LEVEL = 12471; // 30 -const static uint64_t SH_FLD_REQ_STOP_LEVEL_FSP = 12472; // 30 -const static uint64_t SH_FLD_REQ_STOP_LEVEL_FSP_LEN = 12473; // 30 -const static uint64_t SH_FLD_REQ_STOP_LEVEL_HYP = 12474; // 30 -const static uint64_t SH_FLD_REQ_STOP_LEVEL_HYP_LEN = 12475; // 30 -const static uint64_t SH_FLD_REQ_STOP_LEVEL_LEN = 12476; // 30 -const static uint64_t SH_FLD_REQ_STOP_LEVEL_OCC = 12477; // 30 -const static uint64_t SH_FLD_REQ_STOP_LEVEL_OCC_LEN = 12478; // 30 -const static uint64_t SH_FLD_REQ_STOP_LEVEL_OTR = 12479; // 30 -const static uint64_t SH_FLD_REQ_STOP_LEVEL_OTR_LEN = 12480; // 30 -const static uint64_t SH_FLD_RESCLK_DIS = 12481; // 43 -const static uint64_t SH_FLD_RESERVATION_EN = 12482; // 1 -const static uint64_t SH_FLD_RESERVED = 12483; // 120 -const static uint64_t SH_FLD_RESERVED1 = 12484; // 248 -const static uint64_t SH_FLD_RESERVED12 = 12485; // 4 -const static uint64_t SH_FLD_RESERVED13 = 12486; // 4 -const static uint64_t SH_FLD_RESERVED13_15 = 12487; // 6 -const static uint64_t SH_FLD_RESERVED13_15_LEN = 12488; // 6 -const static uint64_t SH_FLD_RESERVED17 = 12489; // 4 -const static uint64_t SH_FLD_RESERVED18 = 12490; // 4 -const static uint64_t SH_FLD_RESERVED19 = 12491; // 4 -const static uint64_t SH_FLD_RESERVED19_23 = 12492; // 4 -const static uint64_t SH_FLD_RESERVED19_23_LEN = 12493; // 4 -const static uint64_t SH_FLD_RESERVED1_2 = 12494; // 4 -const static uint64_t SH_FLD_RESERVED1_2_LEN = 12495; // 4 -const static uint64_t SH_FLD_RESERVED1_LEN = 12496; // 164 -const static uint64_t SH_FLD_RESERVED2 = 12497; // 63 -const static uint64_t SH_FLD_RESERVED20 = 12498; // 4 -const static uint64_t SH_FLD_RESERVED21 = 12499; // 4 -const static uint64_t SH_FLD_RESERVED22 = 12500; // 4 -const static uint64_t SH_FLD_RESERVED23 = 12501; // 4 -const static uint64_t SH_FLD_RESERVED24 = 12502; // 4 -const static uint64_t SH_FLD_RESERVED25 = 12503; // 8 -const static uint64_t SH_FLD_RESERVED26 = 12504; // 12 -const static uint64_t SH_FLD_RESERVED27 = 12505; // 4 -const static uint64_t SH_FLD_RESERVED28_29 = 12506; // 6 -const static uint64_t SH_FLD_RESERVED28_29_LEN = 12507; // 6 -const static uint64_t SH_FLD_RESERVED2_LEN = 12508; // 15 -const static uint64_t SH_FLD_RESERVED3 = 12509; // 21 -const static uint64_t SH_FLD_RESERVED3_LEN = 12510; // 15 -const static uint64_t SH_FLD_RESERVED4 = 12511; // 6 -const static uint64_t SH_FLD_RESERVED46_48 = 12512; // 4 -const static uint64_t SH_FLD_RESERVED46_48_LEN = 12513; // 4 -const static uint64_t SH_FLD_RESERVED4_LEN = 12514; // 6 -const static uint64_t SH_FLD_RESERVED515 = 12515; // 4 -const static uint64_t SH_FLD_RESERVED515_LEN = 12516; // 4 -const static uint64_t SH_FLD_RESERVED54 = 12517; // 4 -const static uint64_t SH_FLD_RESERVED55 = 12518; // 4 -const static uint64_t SH_FLD_RESERVED57_63 = 12519; // 4 -const static uint64_t SH_FLD_RESERVED57_63_LEN = 12520; // 4 -const static uint64_t SH_FLD_RESERVED6 = 12521; // 1 -const static uint64_t SH_FLD_RESERVED61_63 = 12522; // 4 -const static uint64_t SH_FLD_RESERVED61_63_LEN = 12523; // 4 -const static uint64_t SH_FLD_RESERVED_0 = 12524; // 4 -const static uint64_t SH_FLD_RESERVED_00 = 12525; // 1 -const static uint64_t SH_FLD_RESERVED_02 = 12526; // 1 -const static uint64_t SH_FLD_RESERVED_03 = 12527; // 1 -const static uint64_t SH_FLD_RESERVED_0_1 = 12528; // 20 -const static uint64_t SH_FLD_RESERVED_0_11 = 12529; // 6 -const static uint64_t SH_FLD_RESERVED_0_11_LEN = 12530; // 6 -const static uint64_t SH_FLD_RESERVED_0_17 = 12531; // 2 -const static uint64_t SH_FLD_RESERVED_0_17_LEN = 12532; // 2 -const static uint64_t SH_FLD_RESERVED_0_1_LEN = 12533; // 20 -const static uint64_t SH_FLD_RESERVED_0_20 = 12534; // 5 -const static uint64_t SH_FLD_RESERVED_0_20_LEN = 12535; // 5 -const static uint64_t SH_FLD_RESERVED_0_3 = 12536; // 1 -const static uint64_t SH_FLD_RESERVED_0_31 = 12537; // 2 -const static uint64_t SH_FLD_RESERVED_0_31_LEN = 12538; // 2 -const static uint64_t SH_FLD_RESERVED_0_32 = 12539; // 1 -const static uint64_t SH_FLD_RESERVED_0_32_LEN = 12540; // 1 -const static uint64_t SH_FLD_RESERVED_0_3_LEN = 12541; // 1 -const static uint64_t SH_FLD_RESERVED_0_7 = 12542; // 24 -const static uint64_t SH_FLD_RESERVED_0_7_LEN = 12543; // 24 -const static uint64_t SH_FLD_RESERVED_1 = 12544; // 11 -const static uint64_t SH_FLD_RESERVED_10 = 12545; // 2 -const static uint64_t SH_FLD_RESERVED_10_11 = 12546; // 30 -const static uint64_t SH_FLD_RESERVED_10_11_LEN = 12547; // 30 -const static uint64_t SH_FLD_RESERVED_10_LEN = 12548; // 1 -const static uint64_t SH_FLD_RESERVED_11 = 12549; // 2 -const static uint64_t SH_FLD_RESERVED_11A = 12550; // 43 -const static uint64_t SH_FLD_RESERVED_11_12 = 12551; // 4 -const static uint64_t SH_FLD_RESERVED_11_12_LEN = 12552; // 4 -const static uint64_t SH_FLD_RESERVED_11_14 = 12553; // 4 -const static uint64_t SH_FLD_RESERVED_11_14_LEN = 12554; // 4 -const static uint64_t SH_FLD_RESERVED_11_LEN = 12555; // 1 -const static uint64_t SH_FLD_RESERVED_12 = 12556; // 1 -const static uint64_t SH_FLD_RESERVED_12_13 = 12557; // 8 -const static uint64_t SH_FLD_RESERVED_12_13_LEN = 12558; // 8 -const static uint64_t SH_FLD_RESERVED_12_15 = 12559; // 1 -const static uint64_t SH_FLD_RESERVED_12_15_LEN = 12560; // 1 -const static uint64_t SH_FLD_RESERVED_12_23 = 12561; // 1 -const static uint64_t SH_FLD_RESERVED_12_23_LEN = 12562; // 1 -const static uint64_t SH_FLD_RESERVED_12_31 = 12563; // 2 -const static uint64_t SH_FLD_RESERVED_12_31_LEN = 12564; // 2 -const static uint64_t SH_FLD_RESERVED_12_34 = 12565; // 2 -const static uint64_t SH_FLD_RESERVED_12_34_LEN = 12566; // 2 -const static uint64_t SH_FLD_RESERVED_13 = 12567; // 17 -const static uint64_t SH_FLD_RESERVED_13_31 = 12568; // 2 -const static uint64_t SH_FLD_RESERVED_13_31_LEN = 12569; // 2 -const static uint64_t SH_FLD_RESERVED_13_LEN = 12570; // 1 -const static uint64_t SH_FLD_RESERVED_14 = 12571; // 1 -const static uint64_t SH_FLD_RESERVED_14C = 12572; // 43 -const static uint64_t SH_FLD_RESERVED_14_15 = 12573; // 6 -const static uint64_t SH_FLD_RESERVED_14_15_LEN = 12574; // 6 -const static uint64_t SH_FLD_RESERVED_14_LEN = 12575; // 1 -const static uint64_t SH_FLD_RESERVED_15 = 12576; // 12 -const static uint64_t SH_FLD_RESERVED_15C = 12577; // 43 -const static uint64_t SH_FLD_RESERVED_16 = 12578; // 13 -const static uint64_t SH_FLD_RESERVED_16_17 = 12579; // 12 -const static uint64_t SH_FLD_RESERVED_16_17_LEN = 12580; // 12 -const static uint64_t SH_FLD_RESERVED_16_18 = 12581; // 30 -const static uint64_t SH_FLD_RESERVED_16_18_LEN = 12582; // 30 -const static uint64_t SH_FLD_RESERVED_16_26 = 12583; // 2 -const static uint64_t SH_FLD_RESERVED_16_26_LEN = 12584; // 2 -const static uint64_t SH_FLD_RESERVED_16_LEN = 12585; // 1 -const static uint64_t SH_FLD_RESERVED_17 = 12586; // 11 -const static uint64_t SH_FLD_RESERVED_17_18 = 12587; // 6 -const static uint64_t SH_FLD_RESERVED_17_18_LEN = 12588; // 6 -const static uint64_t SH_FLD_RESERVED_17_19 = 12589; // 6 -const static uint64_t SH_FLD_RESERVED_17_19_LEN = 12590; // 6 -const static uint64_t SH_FLD_RESERVED_17_LEN = 12591; // 1 -const static uint64_t SH_FLD_RESERVED_18A = 12592; // 43 -const static uint64_t SH_FLD_RESERVED_18_23 = 12593; // 10 -const static uint64_t SH_FLD_RESERVED_18_23_LEN = 12594; // 10 -const static uint64_t SH_FLD_RESERVED_18_31 = 12595; // 3 -const static uint64_t SH_FLD_RESERVED_18_31_LEN = 12596; // 3 -const static uint64_t SH_FLD_RESERVED_19 = 12597; // 1 -const static uint64_t SH_FLD_RESERVED_19A = 12598; // 43 -const static uint64_t SH_FLD_RESERVED_19_31 = 12599; // 8 -const static uint64_t SH_FLD_RESERVED_19_31_LEN = 12600; // 8 -const static uint64_t SH_FLD_RESERVED_1_12 = 12601; // 4 -const static uint64_t SH_FLD_RESERVED_1_12_LEN = 12602; // 4 -const static uint64_t SH_FLD_RESERVED_1_2 = 12603; // 54 -const static uint64_t SH_FLD_RESERVED_1_2_LEN = 12604; // 54 -const static uint64_t SH_FLD_RESERVED_1_5 = 12605; // 1 -const static uint64_t SH_FLD_RESERVED_1_5_LEN = 12606; // 1 -const static uint64_t SH_FLD_RESERVED_1_7 = 12607; // 1 -const static uint64_t SH_FLD_RESERVED_1_7_LEN = 12608; // 1 -const static uint64_t SH_FLD_RESERVED_2 = 12609; // 2 -const static uint64_t SH_FLD_RESERVED_20 = 12610; // 1 -const static uint64_t SH_FLD_RESERVED_20_22 = 12611; // 1 -const static uint64_t SH_FLD_RESERVED_20_22_LEN = 12612; // 1 -const static uint64_t SH_FLD_RESERVED_20_23 = 12613; // 12 -const static uint64_t SH_FLD_RESERVED_20_23_LEN = 12614; // 12 -const static uint64_t SH_FLD_RESERVED_20_31 = 12615; // 2 -const static uint64_t SH_FLD_RESERVED_20_31_LEN = 12616; // 2 -const static uint64_t SH_FLD_RESERVED_20_LEN = 12617; // 1 -const static uint64_t SH_FLD_RESERVED_21 = 12618; // 8 -const static uint64_t SH_FLD_RESERVED_22C = 12619; // 43 -const static uint64_t SH_FLD_RESERVED_23 = 12620; // 4 -const static uint64_t SH_FLD_RESERVED_23C = 12621; // 43 -const static uint64_t SH_FLD_RESERVED_23_26 = 12622; // 8 -const static uint64_t SH_FLD_RESERVED_23_26_LEN = 12623; // 8 -const static uint64_t SH_FLD_RESERVED_23_63 = 12624; // 2 -const static uint64_t SH_FLD_RESERVED_23_63_LEN = 12625; // 2 -const static uint64_t SH_FLD_RESERVED_24 = 12626; // 3 -const static uint64_t SH_FLD_RESERVED_24_25 = 12627; // 2 -const static uint64_t SH_FLD_RESERVED_24_25_LEN = 12628; // 2 -const static uint64_t SH_FLD_RESERVED_24_29 = 12629; // 1 -const static uint64_t SH_FLD_RESERVED_24_29_LEN = 12630; // 1 -const static uint64_t SH_FLD_RESERVED_24_31 = 12631; // 1 -const static uint64_t SH_FLD_RESERVED_24_31_LEN = 12632; // 1 -const static uint64_t SH_FLD_RESERVED_24_LEN = 12633; // 1 -const static uint64_t SH_FLD_RESERVED_25 = 12634; // 11 -const static uint64_t SH_FLD_RESERVED_25_26 = 12635; // 3 -const static uint64_t SH_FLD_RESERVED_25_26_LEN = 12636; // 3 -const static uint64_t SH_FLD_RESERVED_26_49 = 12637; // 2 -const static uint64_t SH_FLD_RESERVED_26_49_LEN = 12638; // 2 -const static uint64_t SH_FLD_RESERVED_28 = 12639; // 3 -const static uint64_t SH_FLD_RESERVED_28_31 = 12640; // 68 -const static uint64_t SH_FLD_RESERVED_28_31_LEN = 12641; // 68 -const static uint64_t SH_FLD_RESERVED_28_LEN = 12642; // 2 -const static uint64_t SH_FLD_RESERVED_2E = 12643; // 43 -const static uint64_t SH_FLD_RESERVED_2_11 = 12644; // 24 -const static uint64_t SH_FLD_RESERVED_2_11_LEN = 12645; // 24 -const static uint64_t SH_FLD_RESERVED_2_3 = 12646; // 3 -const static uint64_t SH_FLD_RESERVED_2_3_LEN = 12647; // 3 -const static uint64_t SH_FLD_RESERVED_3 = 12648; // 8 -const static uint64_t SH_FLD_RESERVED_30 = 12649; // 1 -const static uint64_t SH_FLD_RESERVED_30C = 12650; // 43 -const static uint64_t SH_FLD_RESERVED_31 = 12651; // 3 -const static uint64_t SH_FLD_RESERVED_31C = 12652; // 43 -const static uint64_t SH_FLD_RESERVED_31_LEN = 12653; // 2 -const static uint64_t SH_FLD_RESERVED_32 = 12654; // 26 -const static uint64_t SH_FLD_RESERVED_32_33 = 12655; // 4 -const static uint64_t SH_FLD_RESERVED_32_33_LEN = 12656; // 4 -const static uint64_t SH_FLD_RESERVED_32_34 = 12657; // 7 -const static uint64_t SH_FLD_RESERVED_32_34_LEN = 12658; // 7 -const static uint64_t SH_FLD_RESERVED_32_35 = 12659; // 3 -const static uint64_t SH_FLD_RESERVED_32_35_LEN = 12660; // 3 -const static uint64_t SH_FLD_RESERVED_32_39 = 12661; // 3 -const static uint64_t SH_FLD_RESERVED_32_39_LEN = 12662; // 3 -const static uint64_t SH_FLD_RESERVED_32_40 = 12663; // 10 -const static uint64_t SH_FLD_RESERVED_32_40_LEN = 12664; // 10 -const static uint64_t SH_FLD_RESERVED_32_43 = 12665; // 1 -const static uint64_t SH_FLD_RESERVED_32_43_LEN = 12666; // 1 -const static uint64_t SH_FLD_RESERVED_32_63 = 12667; // 8 -const static uint64_t SH_FLD_RESERVED_32_63_LEN = 12668; // 8 -const static uint64_t SH_FLD_RESERVED_33A = 12669; // 43 -const static uint64_t SH_FLD_RESERVED_33_63 = 12670; // 2 -const static uint64_t SH_FLD_RESERVED_33_63_LEN = 12671; // 2 -const static uint64_t SH_FLD_RESERVED_34 = 12672; // 1 -const static uint64_t SH_FLD_RESERVED_34A = 12673; // 43 -const static uint64_t SH_FLD_RESERVED_34_35 = 12674; // 6 -const static uint64_t SH_FLD_RESERVED_34_35_LEN = 12675; // 6 -const static uint64_t SH_FLD_RESERVED_35 = 12676; // 1 -const static uint64_t SH_FLD_RESERVED_35A = 12677; // 43 -const static uint64_t SH_FLD_RESERVED_36_37 = 12678; // 8 -const static uint64_t SH_FLD_RESERVED_36_37_LEN = 12679; // 8 -const static uint64_t SH_FLD_RESERVED_36_39 = 12680; // 12 -const static uint64_t SH_FLD_RESERVED_36_39_LEN = 12681; // 12 -const static uint64_t SH_FLD_RESERVED_37 = 12682; // 1 -const static uint64_t SH_FLD_RESERVED_37_38 = 12683; // 6 -const static uint64_t SH_FLD_RESERVED_37_38_LEN = 12684; // 6 -const static uint64_t SH_FLD_RESERVED_37_51 = 12685; // 1 -const static uint64_t SH_FLD_RESERVED_37_51_LEN = 12686; // 1 -const static uint64_t SH_FLD_RESERVED_37_56 = 12687; // 8 -const static uint64_t SH_FLD_RESERVED_37_56_LEN = 12688; // 8 -const static uint64_t SH_FLD_RESERVED_38 = 12689; // 1 -const static uint64_t SH_FLD_RESERVED_38A = 12690; // 43 -const static uint64_t SH_FLD_RESERVED_38_39 = 12691; // 24 -const static uint64_t SH_FLD_RESERVED_38_39_LEN = 12692; // 24 -const static uint64_t SH_FLD_RESERVED_38_41 = 12693; // 2 -const static uint64_t SH_FLD_RESERVED_38_41_LEN = 12694; // 2 -const static uint64_t SH_FLD_RESERVED_38_63 = 12695; // 2 -const static uint64_t SH_FLD_RESERVED_38_63_LEN = 12696; // 2 -const static uint64_t SH_FLD_RESERVED_39 = 12697; // 12 -const static uint64_t SH_FLD_RESERVED_39A = 12698; // 43 -const static uint64_t SH_FLD_RESERVED_39_47 = 12699; // 64 -const static uint64_t SH_FLD_RESERVED_39_47_LEN = 12700; // 64 -const static uint64_t SH_FLD_RESERVED_3E = 12701; // 43 -const static uint64_t SH_FLD_RESERVED_4 = 12702; // 15 -const static uint64_t SH_FLD_RESERVED_40 = 12703; // 35 -const static uint64_t SH_FLD_RESERVED_40_41 = 12704; // 7 -const static uint64_t SH_FLD_RESERVED_40_41_LEN = 12705; // 7 -const static uint64_t SH_FLD_RESERVED_40_42 = 12706; // 1 -const static uint64_t SH_FLD_RESERVED_40_42_LEN = 12707; // 1 -const static uint64_t SH_FLD_RESERVED_40_47 = 12708; // 1 -const static uint64_t SH_FLD_RESERVED_40_47_LEN = 12709; // 1 -const static uint64_t SH_FLD_RESERVED_41 = 12710; // 2 -const static uint64_t SH_FLD_RESERVED_41_42 = 12711; // 10 -const static uint64_t SH_FLD_RESERVED_41_42_LEN = 12712; // 10 -const static uint64_t SH_FLD_RESERVED_41_43 = 12713; // 1 -const static uint64_t SH_FLD_RESERVED_41_43_LEN = 12714; // 1 -const static uint64_t SH_FLD_RESERVED_41_63 = 12715; // 8 -const static uint64_t SH_FLD_RESERVED_41_63_LEN = 12716; // 8 -const static uint64_t SH_FLD_RESERVED_42 = 12717; // 2 -const static uint64_t SH_FLD_RESERVED_42A = 12718; // 43 -const static uint64_t SH_FLD_RESERVED_42_43 = 12719; // 12 -const static uint64_t SH_FLD_RESERVED_42_43_LEN = 12720; // 12 -const static uint64_t SH_FLD_RESERVED_43 = 12721; // 2 -const static uint64_t SH_FLD_RESERVED_43A = 12722; // 43 -const static uint64_t SH_FLD_RESERVED_43C = 12723; // 43 -const static uint64_t SH_FLD_RESERVED_43_44 = 12724; // 2 -const static uint64_t SH_FLD_RESERVED_43_44_LEN = 12725; // 2 -const static uint64_t SH_FLD_RESERVED_44 = 12726; // 1 -const static uint64_t SH_FLD_RESERVED_44_47 = 12727; // 1 -const static uint64_t SH_FLD_RESERVED_44_47_LEN = 12728; // 1 -const static uint64_t SH_FLD_RESERVED_45 = 12729; // 1 -const static uint64_t SH_FLD_RESERVED_45_63 = 12730; // 1 -const static uint64_t SH_FLD_RESERVED_45_63_LEN = 12731; // 1 -const static uint64_t SH_FLD_RESERVED_46 = 12732; // 1 -const static uint64_t SH_FLD_RESERVED_47 = 12733; // 1 -const static uint64_t SH_FLD_RESERVED_47_48 = 12734; // 2 -const static uint64_t SH_FLD_RESERVED_47_48_LEN = 12735; // 2 -const static uint64_t SH_FLD_RESERVED_48 = 12736; // 26 -const static uint64_t SH_FLD_RESERVED_48_49 = 12737; // 1 -const static uint64_t SH_FLD_RESERVED_48_49_LEN = 12738; // 1 -const static uint64_t SH_FLD_RESERVED_48_50 = 12739; // 2 -const static uint64_t SH_FLD_RESERVED_48_50_LEN = 12740; // 2 -const static uint64_t SH_FLD_RESERVED_48_55 = 12741; // 1 -const static uint64_t SH_FLD_RESERVED_48_55_LEN = 12742; // 1 -const static uint64_t SH_FLD_RESERVED_48_63 = 12743; // 10 -const static uint64_t SH_FLD_RESERVED_48_63_LEN = 12744; // 10 -const static uint64_t SH_FLD_RESERVED_49_63 = 12745; // 8 -const static uint64_t SH_FLD_RESERVED_49_63_LEN = 12746; // 8 -const static uint64_t SH_FLD_RESERVED_4_5 = 12747; // 12 -const static uint64_t SH_FLD_RESERVED_4_5_LEN = 12748; // 12 -const static uint64_t SH_FLD_RESERVED_4_7 = 12749; // 33 -const static uint64_t SH_FLD_RESERVED_4_7_LEN = 12750; // 33 -const static uint64_t SH_FLD_RESERVED_4_LEN = 12751; // 1 -const static uint64_t SH_FLD_RESERVED_5 = 12752; // 1 -const static uint64_t SH_FLD_RESERVED_50 = 12753; // 4 -const static uint64_t SH_FLD_RESERVED_50_51 = 12754; // 1 -const static uint64_t SH_FLD_RESERVED_50_51_LEN = 12755; // 1 -const static uint64_t SH_FLD_RESERVED_51 = 12756; // 8 -const static uint64_t SH_FLD_RESERVED_51_63 = 12757; // 1 -const static uint64_t SH_FLD_RESERVED_51_63_LEN = 12758; // 1 -const static uint64_t SH_FLD_RESERVED_52 = 12759; // 38 -const static uint64_t SH_FLD_RESERVED_52_55 = 12760; // 64 -const static uint64_t SH_FLD_RESERVED_52_55_LEN = 12761; // 64 -const static uint64_t SH_FLD_RESERVED_52_56 = 12762; // 8 -const static uint64_t SH_FLD_RESERVED_52_56_LEN = 12763; // 8 -const static uint64_t SH_FLD_RESERVED_53 = 12764; // 8 -const static uint64_t SH_FLD_RESERVED_53_55 = 12765; // 6 -const static uint64_t SH_FLD_RESERVED_53_55_LEN = 12766; // 6 -const static uint64_t SH_FLD_RESERVED_53_59 = 12767; // 2 -const static uint64_t SH_FLD_RESERVED_53_59_LEN = 12768; // 2 -const static uint64_t SH_FLD_RESERVED_53_63 = 12769; // 1 -const static uint64_t SH_FLD_RESERVED_53_63_LEN = 12770; // 1 -const static uint64_t SH_FLD_RESERVED_54_63 = 12771; // 8 -const static uint64_t SH_FLD_RESERVED_54_63_LEN = 12772; // 8 -const static uint64_t SH_FLD_RESERVED_55_63 = 12773; // 8 -const static uint64_t SH_FLD_RESERVED_55_63_LEN = 12774; // 8 -const static uint64_t SH_FLD_RESERVED_56 = 12775; // 40 -const static uint64_t SH_FLD_RESERVED_56_57 = 12776; // 1 -const static uint64_t SH_FLD_RESERVED_56_57_LEN = 12777; // 1 -const static uint64_t SH_FLD_RESERVED_56_58 = 12778; // 4 -const static uint64_t SH_FLD_RESERVED_56_58_LEN = 12779; // 4 -const static uint64_t SH_FLD_RESERVED_56_59 = 12780; // 1 -const static uint64_t SH_FLD_RESERVED_56_59_LEN = 12781; // 1 -const static uint64_t SH_FLD_RESERVED_56_63 = 12782; // 17 -const static uint64_t SH_FLD_RESERVED_56_63_LEN = 12783; // 17 -const static uint64_t SH_FLD_RESERVED_57 = 12784; // 24 -const static uint64_t SH_FLD_RESERVED_57_58 = 12785; // 1 -const static uint64_t SH_FLD_RESERVED_57_58_LEN = 12786; // 1 -const static uint64_t SH_FLD_RESERVED_57_59 = 12787; // 2 -const static uint64_t SH_FLD_RESERVED_57_59_LEN = 12788; // 2 -const static uint64_t SH_FLD_RESERVED_57_60 = 12789; // 6 -const static uint64_t SH_FLD_RESERVED_57_60_LEN = 12790; // 6 -const static uint64_t SH_FLD_RESERVED_57_63 = 12791; // 8 -const static uint64_t SH_FLD_RESERVED_57_63_LEN = 12792; // 8 -const static uint64_t SH_FLD_RESERVED_58_63 = 12793; // 16 -const static uint64_t SH_FLD_RESERVED_58_63_LEN = 12794; // 16 -const static uint64_t SH_FLD_RESERVED_59 = 12795; // 1 -const static uint64_t SH_FLD_RESERVED_5_15 = 12796; // 1 -const static uint64_t SH_FLD_RESERVED_5_15_LEN = 12797; // 1 -const static uint64_t SH_FLD_RESERVED_5_LEN = 12798; // 1 -const static uint64_t SH_FLD_RESERVED_6 = 12799; // 2 -const static uint64_t SH_FLD_RESERVED_60 = 12800; // 24 -const static uint64_t SH_FLD_RESERVED_60_63 = 12801; // 15 -const static uint64_t SH_FLD_RESERVED_60_63_LEN = 12802; // 15 -const static uint64_t SH_FLD_RESERVED_61 = 12803; // 24 -const static uint64_t SH_FLD_RESERVED_61_63 = 12804; // 16 -const static uint64_t SH_FLD_RESERVED_61_63_LEN = 12805; // 16 -const static uint64_t SH_FLD_RESERVED_62 = 12806; // 3 -const static uint64_t SH_FLD_RESERVED_62_63 = 12807; // 8 -const static uint64_t SH_FLD_RESERVED_62_63_LEN = 12808; // 8 -const static uint64_t SH_FLD_RESERVED_63 = 12809; // 12 -const static uint64_t SH_FLD_RESERVED_6C = 12810; // 43 -const static uint64_t SH_FLD_RESERVED_6E = 12811; // 43 -const static uint64_t SH_FLD_RESERVED_6_14 = 12812; // 2 -const static uint64_t SH_FLD_RESERVED_6_14_LEN = 12813; // 2 -const static uint64_t SH_FLD_RESERVED_6_7 = 12814; // 26 -const static uint64_t SH_FLD_RESERVED_6_7_LEN = 12815; // 26 -const static uint64_t SH_FLD_RESERVED_7 = 12816; // 2 -const static uint64_t SH_FLD_RESERVED_7C = 12817; // 43 -const static uint64_t SH_FLD_RESERVED_7_9 = 12818; // 8 -const static uint64_t SH_FLD_RESERVED_7_9_LEN = 12819; // 8 -const static uint64_t SH_FLD_RESERVED_7_LEN = 12820; // 1 -const static uint64_t SH_FLD_RESERVED_8 = 12821; // 5 -const static uint64_t SH_FLD_RESERVED_8_10 = 12822; // 38 -const static uint64_t SH_FLD_RESERVED_8_10_LEN = 12823; // 38 -const static uint64_t SH_FLD_RESERVED_8_11 = 12824; // 12 -const static uint64_t SH_FLD_RESERVED_8_11_LEN = 12825; // 12 -const static uint64_t SH_FLD_RESERVED_8_9 = 12826; // 1 -const static uint64_t SH_FLD_RESERVED_8_9_LEN = 12827; // 1 -const static uint64_t SH_FLD_RESERVED_8_LEN = 12828; // 1 -const static uint64_t SH_FLD_RESERVED_9 = 12829; // 27 -const static uint64_t SH_FLD_RESERVED_9_15 = 12830; // 2 -const static uint64_t SH_FLD_RESERVED_9_15_LEN = 12831; // 2 -const static uint64_t SH_FLD_RESERVED_9_27 = 12832; // 1 -const static uint64_t SH_FLD_RESERVED_9_27_LEN = 12833; // 1 -const static uint64_t SH_FLD_RESERVED_CERR_24 = 12834; // 8 -const static uint64_t SH_FLD_RESERVED_CERR_25 = 12835; // 8 -const static uint64_t SH_FLD_RESERVED_FOR_ADDRESS = 12836; // 1 -const static uint64_t SH_FLD_RESERVED_FOR_ADDRESS_LEN = 12837; // 1 -const static uint64_t SH_FLD_RESERVED_FOR_CONFIGS = 12838; // 1 -const static uint64_t SH_FLD_RESERVED_FOR_CONFIGS_LEN = 12839; // 1 -const static uint64_t SH_FLD_RESERVED_FOR_ERRS = 12840; // 1 -const static uint64_t SH_FLD_RESERVED_FOR_ERRS_LEN = 12841; // 1 -const static uint64_t SH_FLD_RESERVED_ID_55C = 12842; // 43 -const static uint64_t SH_FLD_RESERVED_ID_61C = 12843; // 43 -const static uint64_t SH_FLD_RESERVED_ID_62C = 12844; // 43 -const static uint64_t SH_FLD_RESERVED_ID_63C = 12845; // 43 -const static uint64_t SH_FLD_RESERVED_LEN = 12846; // 65 -const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_35C = 12847; // 43 -const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_36C = 12848; // 43 -const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_37C = 12849; // 43 -const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_38C = 12850; // 43 -const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_39C = 12851; // 43 -const static uint64_t SH_FLD_RESERVE_11 = 12852; // 2 -const static uint64_t SH_FLD_RESERVE_39_52 = 12853; // 2 -const static uint64_t SH_FLD_RESERVE_39_52_LEN = 12854; // 2 -const static uint64_t SH_FLD_RESERVE_5_63 = 12855; // 2 -const static uint64_t SH_FLD_RESERVE_5_63_LEN = 12856; // 2 -const static uint64_t SH_FLD_RESET = 12857; // 28 -const static uint64_t SH_FLD_RESETMODE = 12858; // 3 -const static uint64_t SH_FLD_RESET_0_7 = 12859; // 1 -const static uint64_t SH_FLD_RESET_0_7_LEN = 12860; // 1 -const static uint64_t SH_FLD_RESET_EP = 12861; // 43 -const static uint64_t SH_FLD_RESET_ERROR_LOGS = 12862; // 2 -const static uint64_t SH_FLD_RESET_ERR_RPT = 12863; // 8 -const static uint64_t SH_FLD_RESET_IMPRECISE_QERR = 12864; // 12 -const static uint64_t SH_FLD_RESET_KEEPER = 12865; // 26 -const static uint64_t SH_FLD_RESET_LEN = 12866; // 2 -const static uint64_t SH_FLD_RESET_ON_PARITY = 12867; // 1 -const static uint64_t SH_FLD_RESET_PIB = 12868; // 1 -const static uint64_t SH_FLD_RESET_RECOVER = 12869; // 8 -const static uint64_t SH_FLD_RESET_TOD_STATE = 12870; // 1 -const static uint64_t SH_FLD_RESET_TRAP_CNFG = 12871; // 2 -const static uint64_t SH_FLD_RESET_TRIG_SEL = 12872; // 43 -const static uint64_t SH_FLD_RESET_TRIG_SEL_LEN = 12873; // 43 -const static uint64_t SH_FLD_RESET_ZCAL = 12874; // 8 -const static uint64_t SH_FLD_RESID_FE_LEN_0 = 12875; // 1 -const static uint64_t SH_FLD_RESID_FE_LEN_0_LEN = 12876; // 1 -const static uint64_t SH_FLD_RESID_FE_LEN_1 = 12877; // 1 -const static uint64_t SH_FLD_RESID_FE_LEN_1_LEN = 12878; // 1 -const static uint64_t SH_FLD_RESID_FE_LEN_2 = 12879; // 1 -const static uint64_t SH_FLD_RESID_FE_LEN_2_LEN = 12880; // 1 -const static uint64_t SH_FLD_RESID_FE_LEN_3 = 12881; // 1 -const static uint64_t SH_FLD_RESID_FE_LEN_3_LEN = 12882; // 1 -const static uint64_t SH_FLD_RESPONSE = 12883; // 1 -const static uint64_t SH_FLD_RESP_PKT_RCV = 12884; // 2 -const static uint64_t SH_FLD_RESSEL = 12885; // 4 -const static uint64_t SH_FLD_RESULT = 12886; // 1 -const static uint64_t SH_FLD_RESULT_AVAILABLE = 12887; // 2 -const static uint64_t SH_FLD_RESULT_LEN = 12888; // 1 -const static uint64_t SH_FLD_RESUME_FROM_PAUSE = 12889; // 2 -const static uint64_t SH_FLD_RETRAIN_PERCAL_SW = 12890; // 8 -const static uint64_t SH_FLD_RETRY_LPC_LFSR_SELECT = 12891; // 4 -const static uint64_t SH_FLD_RETRY_LPC_LFSR_SELECT_LEN = 12892; // 4 -const static uint64_t SH_FLD_RETRY_VALUE = 12893; // 1 -const static uint64_t SH_FLD_RETRY_VALUE_LEN = 12894; // 1 -const static uint64_t SH_FLD_RETURNQ_ERR = 12895; // 4 -const static uint64_t SH_FLD_RG_CERR_BITS = 12896; // 1 -const static uint64_t SH_FLD_RG_CERR_BITS_LEN = 12897; // 1 -const static uint64_t SH_FLD_RG_CERR_RESET = 12898; // 1 -const static uint64_t SH_FLD_RG_ECC_CE_ERROR = 12899; // 2 -const static uint64_t SH_FLD_RG_ECC_SUE_ERROR = 12900; // 2 -const static uint64_t SH_FLD_RG_ECC_UE_ERROR = 12901; // 2 -const static uint64_t SH_FLD_RG_LOGIC_HW_ERROR = 12902; // 2 -const static uint64_t SH_FLD_RG_TRACE_GROUP_SEL_HI = 12903; // 1 -const static uint64_t SH_FLD_RG_TRACE_GROUP_SEL_HI_LEN = 12904; // 1 -const static uint64_t SH_FLD_RG_TRACE_GROUP_SEL_LO = 12905; // 1 -const static uint64_t SH_FLD_RG_TRACE_GROUP_SEL_LO_LEN = 12906; // 1 -const static uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_01 = 12907; // 1 -const static uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_01_LEN = 12908; // 1 -const static uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_23 = 12909; // 1 -const static uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_23_LEN = 12910; // 1 -const static uint64_t SH_FLD_RIC = 12911; // 8 -const static uint64_t SH_FLD_RIC_LEN = 12912; // 8 -const static uint64_t SH_FLD_RI_N = 12913; // 43 -const static uint64_t SH_FLD_RMA_BAR = 12914; // 1 -const static uint64_t SH_FLD_RMA_BAR_LEN = 12915; // 1 -const static uint64_t SH_FLD_RMA_BAR_MASK = 12916; // 1 -const static uint64_t SH_FLD_RMA_BAR_MASK_LEN = 12917; // 1 -const static uint64_t SH_FLD_RND_BACKOFF_ENABLE = 12918; // 2 -const static uint64_t SH_FLD_RNG0_BIST_FAIL = 12919; // 1 -const static uint64_t SH_FLD_RNG0_FAIL = 12920; // 1 -const static uint64_t SH_FLD_RNG0_INJ_CONTINOUS_ERROR = 12921; // 1 -const static uint64_t SH_FLD_RNG1_BIST_FAIL = 12922; // 1 -const static uint64_t SH_FLD_RNG1_FAIL = 12923; // 1 -const static uint64_t SH_FLD_RNG1_INJ_CONTINOUS_ERROR = 12924; // 1 -const static uint64_t SH_FLD_RNG_CNTRL_LOGIC_ERR = 12925; // 1 -const static uint64_t SH_FLD_RNG_FIRST_FAIL = 12926; // 1 -const static uint64_t SH_FLD_RNG_SECOND_FAIL = 12927; // 1 -const static uint64_t SH_FLD_RNW = 12928; // 15 -const static uint64_t SH_FLD_RPT = 12929; // 2 -const static uint64_t SH_FLD_RPT1 = 12930; // 1 -const static uint64_t SH_FLD_RPT1_LEN = 12931; // 1 -const static uint64_t SH_FLD_RPT_LEN = 12932; // 2 -const static uint64_t SH_FLD_RRDM_DLY = 12933; // 8 -const static uint64_t SH_FLD_RRDM_DLY_LEN = 12934; // 8 -const static uint64_t SH_FLD_RRN_BYPASS_ENABLE = 12935; // 1 -const static uint64_t SH_FLD_RRN_DATA = 12936; // 1 -const static uint64_t SH_FLD_RRN_DATA_LEN = 12937; // 1 -const static uint64_t SH_FLD_RROP_DLY = 12938; // 8 -const static uint64_t SH_FLD_RROP_DLY_LEN = 12939; // 8 -const static uint64_t SH_FLD_RRQ_CAPACITY_LIMIT = 12940; // 4 -const static uint64_t SH_FLD_RRQ_CAPACITY_LIMIT_LEN = 12941; // 4 -const static uint64_t SH_FLD_RRQ_HANG = 12942; // 8 -const static uint64_t SH_FLD_RRQ_PE = 12943; // 8 -const static uint64_t SH_FLD_RRSBG_DLY = 12944; // 8 -const static uint64_t SH_FLD_RRSBG_DLY_LEN = 12945; // 8 -const static uint64_t SH_FLD_RRSMDR_DLY = 12946; // 8 -const static uint64_t SH_FLD_RRSMDR_DLY_LEN = 12947; // 8 -const static uint64_t SH_FLD_RRSMSR_DLY = 12948; // 8 -const static uint64_t SH_FLD_RRSMSR_DLY_LEN = 12949; // 8 -const static uint64_t SH_FLD_RSD_CRD_AT_MACRO = 12950; // 1 -const static uint64_t SH_FLD_RSD_CRD_AT_MACRO_LEN = 12951; // 1 -const static uint64_t SH_FLD_RSD_CRD_DMA_READ = 12952; // 1 -const static uint64_t SH_FLD_RSD_CRD_DMA_READ_LEN = 12953; // 1 -const static uint64_t SH_FLD_RSD_CRD_DMA_WRITE = 12954; // 1 -const static uint64_t SH_FLD_RSD_CRD_DMA_WRITE_LEN = 12955; // 1 -const static uint64_t SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD = 12956; // 1 -const static uint64_t SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD_LEN = 12957; // 1 -const static uint64_t SH_FLD_RSD_CRD_EQ_POST = 12958; // 1 -const static uint64_t SH_FLD_RSD_CRD_EQ_POST_LEN = 12959; // 1 -const static uint64_t SH_FLD_RSD_CRD_TRIG_FWD_1 = 12960; // 1 -const static uint64_t SH_FLD_RSD_CRD_TRIG_FWD_1_LEN = 12961; // 1 -const static uint64_t SH_FLD_RSD_CRD_TRIG_FWD_2 = 12962; // 1 -const static uint64_t SH_FLD_RSD_CRD_TRIG_FWD_2_LEN = 12963; // 1 -const static uint64_t SH_FLD_RSEL = 12964; // 10 -const static uint64_t SH_FLD_RSEL_LEN = 12965; // 10 -const static uint64_t SH_FLD_RSPOUT_CE_ESR = 12966; // 1 -const static uint64_t SH_FLD_RSPOUT_UE_ESR = 12967; // 1 -const static uint64_t SH_FLD_RSP_AE_ALWAYS = 12968; // 6 -const static uint64_t SH_FLD_RSP_CTL_CRED_SINGLE_ENA = 12969; // 6 -const static uint64_t SH_FLD_RSV17 = 12970; // 2 -const static uint64_t SH_FLD_RSV18 = 12971; // 2 -const static uint64_t SH_FLD_RSV19 = 12972; // 2 -const static uint64_t SH_FLD_RSV26 = 12973; // 2 -const static uint64_t SH_FLD_RSV27 = 12974; // 2 -const static uint64_t SH_FLD_RSV34 = 12975; // 2 -const static uint64_t SH_FLD_RSV35 = 12976; // 2 -const static uint64_t SH_FLD_RSV6 = 12977; // 2 -const static uint64_t SH_FLD_RSV7 = 12978; // 2 -const static uint64_t SH_FLD_RSVD = 12979; // 1 -const static uint64_t SH_FLD_RSVD0 = 12980; // 1 -const static uint64_t SH_FLD_RTAGFLUSH_FAILED = 12981; // 2 -const static uint64_t SH_FLD_RTAG_PARITY = 12982; // 1 -const static uint64_t SH_FLD_RTAG_PERR = 12983; // 1 -const static uint64_t SH_FLD_RTIM_THOLD_FORCE = 12984; // 43 -const static uint64_t SH_FLD_RTY_COUNT = 12985; // 2 -const static uint64_t SH_FLD_RTY_COUNT_LEN = 12986; // 2 -const static uint64_t SH_FLD_RUNNING = 12987; // 2 -const static uint64_t SH_FLD_RUNN_MODE = 12988; // 43 -const static uint64_t SH_FLD_RUN_CHIPLET_SCAN0 = 12989; // 43 -const static uint64_t SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL = 12990; // 43 -const static uint64_t SH_FLD_RUN_DCCAL = 12991; // 48 -const static uint64_t SH_FLD_RUN_DYN_RECAL_TIMER = 12992; // 4 -const static uint64_t SH_FLD_RUN_LANE = 12993; // 48 -const static uint64_t SH_FLD_RUN_LANE_DL_MASK = 12994; // 2 -const static uint64_t SH_FLD_RUN_ON_CAPTURE_DR = 12995; // 43 -const static uint64_t SH_FLD_RUN_ON_UPDATE_DR = 12996; // 43 -const static uint64_t SH_FLD_RUN_SCAN0 = 12997; // 43 -const static uint64_t SH_FLD_RUN_STATE_MASK = 12998; // 43 -const static uint64_t SH_FLD_RUN_STOP_HYP = 12999; // 30 -const static uint64_t SH_FLD_RUN_STOP_OCC = 13000; // 30 -const static uint64_t SH_FLD_RUN_STOP_OTR = 13001; // 30 -const static uint64_t SH_FLD_RUN_TCK = 13002; // 1 -const static uint64_t SH_FLD_RUN_TCK_EQ0_ERR = 13003; // 1 -const static uint64_t SH_FLD_RWDM_DLY = 13004; // 8 -const static uint64_t SH_FLD_RWDM_DLY_LEN = 13005; // 8 -const static uint64_t SH_FLD_RWSMDR_DLY = 13006; // 8 -const static uint64_t SH_FLD_RWSMDR_DLY_LEN = 13007; // 8 -const static uint64_t SH_FLD_RWSMSR_DLY = 13008; // 8 -const static uint64_t SH_FLD_RWSMSR_DLY_LEN = 13009; // 8 -const static uint64_t SH_FLD_RXAERR = 13010; // 6 -const static uint64_t SH_FLD_RXBERR = 13011; // 6 -const static uint64_t SH_FLD_RXCAL = 13012; // 116 -const static uint64_t SH_FLD_RXCERR = 13013; // 6 -const static uint64_t SH_FLD_RXDERR = 13014; // 6 -const static uint64_t SH_FLD_RXEERR = 13015; // 6 -const static uint64_t SH_FLD_RXFERR = 13016; // 6 -const static uint64_t SH_FLD_RXGERR = 13017; // 6 -const static uint64_t SH_FLD_RXHERR = 13018; // 6 -const static uint64_t SH_FLD_RXIERR = 13019; // 6 -const static uint64_t SH_FLD_RXJERR = 13020; // 6 -const static uint64_t SH_FLD_RXKERR = 13021; // 6 -const static uint64_t SH_FLD_RXLERR = 13022; // 6 -const static uint64_t SH_FLD_RXMERR = 13023; // 6 -const static uint64_t SH_FLD_RXNERR = 13024; // 6 -const static uint64_t SH_FLD_RXOERR = 13025; // 6 -const static uint64_t SH_FLD_RXPERR = 13026; // 6 -const static uint64_t SH_FLD_RX_BUS_WIDTH = 13027; // 4 -const static uint64_t SH_FLD_RX_BUS_WIDTH_LEN = 13028; // 4 -const static uint64_t SH_FLD_RX_PCB_DATA_P = 13029; // 1 -const static uint64_t SH_FLD_RX_PCB_DATA_P_ERR = 13030; // 1 -const static uint64_t SH_FLD_RX_SELECT = 13031; // 4 -const static uint64_t SH_FLD_RX_SELECT_LEN = 13032; // 4 -const static uint64_t SH_FLD_RX_TTYPE_0 = 13033; // 4 -const static uint64_t SH_FLD_RX_TTYPE_1 = 13034; // 4 -const static uint64_t SH_FLD_RX_TTYPE_1_ON_STEP_ENABLE = 13035; // 1 -const static uint64_t SH_FLD_RX_TTYPE_2 = 13036; // 4 -const static uint64_t SH_FLD_RX_TTYPE_3 = 13037; // 4 -const static uint64_t SH_FLD_RX_TTYPE_4 = 13038; // 4 -const static uint64_t SH_FLD_RX_TTYPE_4_DATA_PARITY = 13039; // 4 -const static uint64_t SH_FLD_RX_TTYPE_5 = 13040; // 4 -const static uint64_t SH_FLD_RX_TTYPE_INVALID = 13041; // 4 -const static uint64_t SH_FLD_S0_BIT_MAP = 13042; // 8 -const static uint64_t SH_FLD_S0_BIT_MAP_LEN = 13043; // 8 -const static uint64_t SH_FLD_S1_BIT_MAP = 13044; // 8 -const static uint64_t SH_FLD_S1_BIT_MAP_LEN = 13045; // 8 -const static uint64_t SH_FLD_S2_BIT_MAP = 13046; // 8 -const static uint64_t SH_FLD_S2_BIT_MAP_LEN = 13047; // 8 -const static uint64_t SH_FLD_SAFE_REFRESH_MODE = 13048; // 8 -const static uint64_t SH_FLD_SAFE_REFRESH_MODE_CLR = 13049; // 8 -const static uint64_t SH_FLD_SAMPLED_SMD_PIN = 13050; // 1 -const static uint64_t SH_FLD_SAMPLE_GUTS = 13051; // 43 -const static uint64_t SH_FLD_SAMPLE_GUTS_LEN = 13052; // 43 -const static uint64_t SH_FLD_SAMPLE_PULSE_CNT = 13053; // 43 -const static uint64_t SH_FLD_SAMPLE_PULSE_CNT_LEN = 13054; // 43 -const static uint64_t SH_FLD_SAMPLE_VALID = 13055; // 12 -const static uint64_t SH_FLD_SAMPTEST_ENABLE = 13056; // 1 -const static uint64_t SH_FLD_SAMPTEST_MATCH_TH_MAX = 13057; // 1 -const static uint64_t SH_FLD_SAMPTEST_MATCH_TH_MAX_LEN = 13058; // 1 -const static uint64_t SH_FLD_SAMPTEST_MATCH_TH_MIN = 13059; // 1 -const static uint64_t SH_FLD_SAMPTEST_MATCH_TH_MIN_LEN = 13060; // 1 -const static uint64_t SH_FLD_SAMPTEST_RRN_ENABLE = 13061; // 1 -const static uint64_t SH_FLD_SAMPTEST_WINDOW_SIZE = 13062; // 1 -const static uint64_t SH_FLD_SAMPTEST_WINDOW_SIZE_LEN = 13063; // 1 -const static uint64_t SH_FLD_SBASE = 13064; // 12 -const static uint64_t SH_FLD_SBASE_LEN = 13065; // 12 -const static uint64_t SH_FLD_SBC_DMA = 13066; // 1 -const static uint64_t SH_FLD_SBC_DMA_LEN = 13067; // 1 -const static uint64_t SH_FLD_SBC_EOI = 13068; // 1 -const static uint64_t SH_FLD_SBC_EOI_LEN = 13069; // 1 -const static uint64_t SH_FLD_SBC_LOOKUP = 13070; // 1 -const static uint64_t SH_FLD_SBC_LOOKUP_LEN = 13071; // 1 -const static uint64_t SH_FLD_SBEFIFO_DATA = 13072; // 5 -const static uint64_t SH_FLD_SBEFIFO_RESET = 13073; // 5 -const static uint64_t SH_FLD_SB_STRENGTH = 13074; // 43 -const static uint64_t SH_FLD_SB_STRENGTH_LEN = 13075; // 43 -const static uint64_t SH_FLD_SCAN0_MODE = 13076; // 43 -const static uint64_t SH_FLD_SCAN_CLK_USE_EVEN = 13077; // 43 -const static uint64_t SH_FLD_SCAN_COUNT = 13078; // 43 -const static uint64_t SH_FLD_SCAN_COUNT_LEN = 13079; // 43 -const static uint64_t SH_FLD_SCAN_INIT_VERSION_PARITY_MASK = 13080; // 43 -const static uint64_t SH_FLD_SCAN_RATIO = 13081; // 43 -const static uint64_t SH_FLD_SCAN_RATIO_LEN = 13082; // 43 -const static uint64_t SH_FLD_SCOM1_SAT_ERR = 13083; // 2 -const static uint64_t SH_FLD_SCOM_CMD_REG_INJ = 13084; // 2 -const static uint64_t SH_FLD_SCOM_CMD_REG_INJ_MODE = 13085; // 2 -const static uint64_t SH_FLD_SCOM_ERR = 13086; // 6 -const static uint64_t SH_FLD_SCOM_ERR1 = 13087; // 48 -const static uint64_t SH_FLD_SCOM_ERR2 = 13088; // 52 -const static uint64_t SH_FLD_SCOM_ERROR = 13089; // 8 -const static uint64_t SH_FLD_SCOM_ERR_DUP = 13090; // 2 -const static uint64_t SH_FLD_SCOM_FATAL_REG_PE = 13091; // 10 -const static uint64_t SH_FLD_SCOM_FIR_HMI = 13092; // 96 -const static uint64_t SH_FLD_SCOM_LINK01_RESET_KEEPER = 13093; // 2 -const static uint64_t SH_FLD_SCOM_LINK23_RESET_KEEPER = 13094; // 2 -const static uint64_t SH_FLD_SCOM_LINK45_RESET_KEEPER = 13095; // 2 -const static uint64_t SH_FLD_SCOM_LINK67_RESET_KEEPER = 13096; // 1 -const static uint64_t SH_FLD_SCOM_MMIO_ADDR_ERR = 13097; // 2 -const static uint64_t SH_FLD_SCOM_PARITY_CLASS_RECOVERABLE = 13098; // 8 -const static uint64_t SH_FLD_SCOM_PARITY_CLASS_STATUS = 13099; // 8 -const static uint64_t SH_FLD_SCOM_PARITY_CLASS_UNRECOVERABLE = 13100; // 8 -const static uint64_t SH_FLD_SCOM_PARITY_ERR = 13101; // 3 -const static uint64_t SH_FLD_SCOM_PARITY_ERR2 = 13102; // 3 -const static uint64_t SH_FLD_SCOM_PE = 13103; // 3 -const static uint64_t SH_FLD_SCOM_PERFMON_START_COMMAND = 13104; // 4 -const static uint64_t SH_FLD_SCOM_PERFMON_STOP_COMMAND = 13105; // 4 -const static uint64_t SH_FLD_SCOM_PERR0 = 13106; // 6 -const static uint64_t SH_FLD_SCOM_PERR1 = 13107; // 6 -const static uint64_t SH_FLD_SCOM_PE_DUP = 13108; // 3 -const static uint64_t SH_FLD_SCOM_RECOVERABLE_REG_PE = 13109; // 10 -const static uint64_t SH_FLD_SCOPE_ATTN_BAR = 13110; // 1 -const static uint64_t SH_FLD_SCOPE_ATTN_BAR_LEN = 13111; // 1 -const static uint64_t SH_FLD_SCOPE_CONTROL = 13112; // 6 -const static uint64_t SH_FLD_SCOPE_CONTROL_LEN = 13113; // 6 -const static uint64_t SH_FLD_SCOPE_MODE = 13114; // 48 -const static uint64_t SH_FLD_SCOPE_MODE_LEN = 13115; // 48 -const static uint64_t SH_FLD_SCPTGT_LFSR_MODE = 13116; // 2 -const static uint64_t SH_FLD_SCPTGT_LFSR_MODE_LEN = 13117; // 2 -const static uint64_t SH_FLD_SCRATCH_ATOMIC_DATA = 13118; // 24 -const static uint64_t SH_FLD_SCRATCH_ATOMIC_DATA_LEN = 13119; // 24 -const static uint64_t SH_FLD_SCRATCH_N = 13120; // 4 -const static uint64_t SH_FLD_SCRATCH_N_LEN = 13121; // 4 -const static uint64_t SH_FLD_SEC = 13122; // 8 -const static uint64_t SH_FLD_SECURE_ACCESS = 13123; // 1 -const static uint64_t SH_FLD_SECURE_ACCESS_BIT = 13124; // 1 -const static uint64_t SH_FLD_SECURE_DEBUG = 13125; // 1 -const static uint64_t SH_FLD_SECURE_DEBUG_MODE = 13126; // 1 -const static uint64_t SH_FLD_SECURE_ERR = 13127; // 2 -const static uint64_t SH_FLD_SECURE_MODE = 13128; // 1 -const static uint64_t SH_FLD_SECURE_SCOM_ERROR = 13129; // 4 -const static uint64_t SH_FLD_SECURITY_DEBUG_MODE = 13130; // 43 -const static uint64_t SH_FLD_SEC_I_PATH_STEP_CHECK_ENABLE = 13131; // 1 -const static uint64_t SH_FLD_SEC_LEN = 13132; // 8 -const static uint64_t SH_FLD_SEC_M_PATH_0_STEP_CHECK_ENABLE = 13133; // 1 -const static uint64_t SH_FLD_SEC_M_PATH_1_STEP_CHECK_ENABLE = 13134; // 1 -const static uint64_t SH_FLD_SEC_M_PATH_SELECT = 13135; // 2 -const static uint64_t SH_FLD_SEC_M_S_DRAWER_SELECT = 13136; // 2 -const static uint64_t SH_FLD_SEC_M_S_SELECT = 13137; // 2 -const static uint64_t SH_FLD_SEC_SELECT = 13138; // 1 -const static uint64_t SH_FLD_SEC_S_PATH_0_STEP_CHECK_ENABLE = 13139; // 1 -const static uint64_t SH_FLD_SEC_S_PATH_1_STEP_CHECK_ENABLE = 13140; // 1 -const static uint64_t SH_FLD_SEC_S_PATH_SELECT = 13141; // 1 -const static uint64_t SH_FLD_SEC_V = 13142; // 8 -const static uint64_t SH_FLD_SEC_WBRD_DEBUG_0_SELECT = 13143; // 8 -const static uint64_t SH_FLD_SEC_WBRD_DEBUG_1_SELECT = 13144; // 8 -const static uint64_t SH_FLD_SEEPROM_UPDATE_LOCK = 13145; // 1 -const static uint64_t SH_FLD_SEG_TEST_CLK_STATUS = 13146; // 4 -const static uint64_t SH_FLD_SEG_TEST_CLK_STATUS_LEN = 13147; // 4 -const static uint64_t SH_FLD_SEG_TEST_LEAKAGE_CTRL = 13148; // 6 -const static uint64_t SH_FLD_SEG_TEST_MODE = 13149; // 6 -const static uint64_t SH_FLD_SEG_TEST_MODE_LEN = 13150; // 6 -const static uint64_t SH_FLD_SEG_TEST_STATUS = 13151; // 116 -const static uint64_t SH_FLD_SEG_TEST_STATUS_LEN = 13152; // 116 -const static uint64_t SH_FLD_SEIDBAR = 13153; // 1 -const static uint64_t SH_FLD_SEIDBAR_LEN = 13154; // 1 -const static uint64_t SH_FLD_SEL = 13155; // 10 -const static uint64_t SH_FLD_SEL0 = 13156; // 1 -const static uint64_t SH_FLD_SEL0_LEN = 13157; // 1 -const static uint64_t SH_FLD_SEL1 = 13158; // 1 -const static uint64_t SH_FLD_SEL1_LEN = 13159; // 1 -const static uint64_t SH_FLD_SELD2SPR = 13160; // 10 -const static uint64_t SH_FLD_SELECT = 13161; // 2 -const static uint64_t SH_FLD_SELECT_LEN = 13162; // 2 -const static uint64_t SH_FLD_SELECT_REGISTER_FSP2PIB = 13163; // 1 -const static uint64_t SH_FLD_SELECT_REGISTER_FSP2PIB_LEN = 13164; // 1 -const static uint64_t SH_FLD_SELFBOOT_DONE = 13165; // 1 -const static uint64_t SH_FLD_SELFBOOT_ENGINE_ATTENTION = 13166; // 1 -const static uint64_t SH_FLD_SELF_BUSY_0 = 13167; // 2 -const static uint64_t SH_FLD_SELF_BUSY_1 = 13168; // 2 -const static uint64_t SH_FLD_SELF_BUSY_2 = 13169; // 2 -const static uint64_t SH_FLD_SELF_BUSY_3 = 13170; // 2 -const static uint64_t SH_FLD_SELPFDPW = 13171; // 10 -const static uint64_t SH_FLD_SELPREFB = 13172; // 10 -const static uint64_t SH_FLD_SELPRESPE = 13173; // 10 -const static uint64_t SH_FLD_SEL_03_NPU_NOT = 13174; // 1 -const static uint64_t SH_FLD_SEL_04_NPU_NOT = 13175; // 1 -const static uint64_t SH_FLD_SEL_05_NPU_NOT = 13176; // 1 -const static uint64_t SH_FLD_SEL_0_2 = 13177; // 16 -const static uint64_t SH_FLD_SEL_0_2_LEN = 13178; // 16 -const static uint64_t SH_FLD_SEL_1_3 = 13179; // 16 -const static uint64_t SH_FLD_SEL_1_3_LEN = 13180; // 16 -const static uint64_t SH_FLD_SEL_LEN = 13181; // 10 -const static uint64_t SH_FLD_SEL_RG_PMU_DATA_HI = 13182; // 1 -const static uint64_t SH_FLD_SEL_RG_PMU_DATA_HI_LEN = 13183; // 1 -const static uint64_t SH_FLD_SEL_RG_PMU_DATA_LO = 13184; // 1 -const static uint64_t SH_FLD_SEL_RG_PMU_DATA_LO_LEN = 13185; // 1 -const static uint64_t SH_FLD_SEL_RG_TRACE_DATA_HI = 13186; // 1 -const static uint64_t SH_FLD_SEL_RG_TRACE_DATA_HI_LEN = 13187; // 1 -const static uint64_t SH_FLD_SEL_RG_TRACE_DATA_LO = 13188; // 1 -const static uint64_t SH_FLD_SEL_RG_TRACE_DATA_LO_LEN = 13189; // 1 -const static uint64_t SH_FLD_SEL_RG_TRIGGERS_01 = 13190; // 1 -const static uint64_t SH_FLD_SEL_RG_TRIGGERS_01_LEN = 13191; // 1 -const static uint64_t SH_FLD_SEL_RG_TRIGGERS_23 = 13192; // 1 -const static uint64_t SH_FLD_SEL_RG_TRIGGERS_23_LEN = 13193; // 1 -const static uint64_t SH_FLD_SEL_THOLD_ARY = 13194; // 43 -const static uint64_t SH_FLD_SEL_THOLD_NSL = 13195; // 43 -const static uint64_t SH_FLD_SEL_THOLD_SL = 13196; // 43 -const static uint64_t SH_FLD_SEL_TYPE_0_2 = 13197; // 16 -const static uint64_t SH_FLD_SEL_TYPE_1_3 = 13198; // 16 -const static uint64_t SH_FLD_SEND_DELAY_CYCLES = 13199; // 2 -const static uint64_t SH_FLD_SEND_DELAY_CYCLES_LEN = 13200; // 2 -const static uint64_t SH_FLD_SEND_PACKET_TIMER_VALUE = 13201; // 2 -const static uint64_t SH_FLD_SEND_PACKET_TIMER_VALUE_LEN = 13202; // 2 -const static uint64_t SH_FLD_SEQ = 13203; // 8 -const static uint64_t SH_FLD_SEQ_01 = 13204; // 43 -const static uint64_t SH_FLD_SEQ_01_LEN = 13205; // 43 -const static uint64_t SH_FLD_SEQ_02 = 13206; // 43 -const static uint64_t SH_FLD_SEQ_02_LEN = 13207; // 43 -const static uint64_t SH_FLD_SEQ_03 = 13208; // 43 -const static uint64_t SH_FLD_SEQ_03_LEN = 13209; // 43 -const static uint64_t SH_FLD_SEQ_04 = 13210; // 43 -const static uint64_t SH_FLD_SEQ_04_LEN = 13211; // 43 -const static uint64_t SH_FLD_SEQ_05 = 13212; // 43 -const static uint64_t SH_FLD_SEQ_05_LEN = 13213; // 43 -const static uint64_t SH_FLD_SEQ_06 = 13214; // 43 -const static uint64_t SH_FLD_SEQ_06_LEN = 13215; // 43 -const static uint64_t SH_FLD_SEQ_07 = 13216; // 43 -const static uint64_t SH_FLD_SEQ_07EVEN = 13217; // 43 -const static uint64_t SH_FLD_SEQ_07EVEN_LEN = 13218; // 43 -const static uint64_t SH_FLD_SEQ_07ODD = 13219; // 43 -const static uint64_t SH_FLD_SEQ_07ODD_LEN = 13220; // 43 -const static uint64_t SH_FLD_SEQ_07_LEN = 13221; // 43 -const static uint64_t SH_FLD_SEQ_08 = 13222; // 43 -const static uint64_t SH_FLD_SEQ_08EVEN = 13223; // 43 -const static uint64_t SH_FLD_SEQ_08EVEN_LEN = 13224; // 43 -const static uint64_t SH_FLD_SEQ_08ODD = 13225; // 43 -const static uint64_t SH_FLD_SEQ_08ODD_LEN = 13226; // 43 -const static uint64_t SH_FLD_SEQ_08_LEN = 13227; // 43 -const static uint64_t SH_FLD_SEQ_09 = 13228; // 43 -const static uint64_t SH_FLD_SEQ_09EVEN = 13229; // 43 -const static uint64_t SH_FLD_SEQ_09EVEN_LEN = 13230; // 43 -const static uint64_t SH_FLD_SEQ_09ODD = 13231; // 43 -const static uint64_t SH_FLD_SEQ_09ODD_LEN = 13232; // 43 -const static uint64_t SH_FLD_SEQ_09_LEN = 13233; // 43 -const static uint64_t SH_FLD_SEQ_10 = 13234; // 43 -const static uint64_t SH_FLD_SEQ_10EVEN = 13235; // 43 -const static uint64_t SH_FLD_SEQ_10EVEN_LEN = 13236; // 43 -const static uint64_t SH_FLD_SEQ_10ODD = 13237; // 43 -const static uint64_t SH_FLD_SEQ_10ODD_LEN = 13238; // 43 -const static uint64_t SH_FLD_SEQ_10_LEN = 13239; // 43 -const static uint64_t SH_FLD_SEQ_11 = 13240; // 43 -const static uint64_t SH_FLD_SEQ_11EVEN = 13241; // 43 -const static uint64_t SH_FLD_SEQ_11EVEN_LEN = 13242; // 43 -const static uint64_t SH_FLD_SEQ_11ODD = 13243; // 43 -const static uint64_t SH_FLD_SEQ_11ODD_LEN = 13244; // 43 -const static uint64_t SH_FLD_SEQ_11_LEN = 13245; // 43 -const static uint64_t SH_FLD_SEQ_12 = 13246; // 43 -const static uint64_t SH_FLD_SEQ_12EVEN = 13247; // 43 -const static uint64_t SH_FLD_SEQ_12EVEN_LEN = 13248; // 43 -const static uint64_t SH_FLD_SEQ_12ODD = 13249; // 43 -const static uint64_t SH_FLD_SEQ_12ODD_LEN = 13250; // 43 -const static uint64_t SH_FLD_SEQ_12_LEN = 13251; // 43 -const static uint64_t SH_FLD_SEQ_13_01EVEN = 13252; // 43 -const static uint64_t SH_FLD_SEQ_13_01EVEN_LEN = 13253; // 43 -const static uint64_t SH_FLD_SEQ_14_01ODD = 13254; // 43 -const static uint64_t SH_FLD_SEQ_14_01ODD_LEN = 13255; // 43 -const static uint64_t SH_FLD_SEQ_15_02EVEN = 13256; // 43 -const static uint64_t SH_FLD_SEQ_15_02EVEN_LEN = 13257; // 43 -const static uint64_t SH_FLD_SEQ_16_02ODD = 13258; // 43 -const static uint64_t SH_FLD_SEQ_16_02ODD_LEN = 13259; // 43 -const static uint64_t SH_FLD_SEQ_17_03EVEN = 13260; // 43 -const static uint64_t SH_FLD_SEQ_17_03EVEN_LEN = 13261; // 43 -const static uint64_t SH_FLD_SEQ_18_03ODD = 13262; // 43 -const static uint64_t SH_FLD_SEQ_18_03ODD_LEN = 13263; // 43 -const static uint64_t SH_FLD_SEQ_19_04EVEN = 13264; // 43 -const static uint64_t SH_FLD_SEQ_19_04EVEN_LEN = 13265; // 43 -const static uint64_t SH_FLD_SEQ_20_04ODD = 13266; // 43 -const static uint64_t SH_FLD_SEQ_20_04ODD_LEN = 13267; // 43 -const static uint64_t SH_FLD_SEQ_21_05EVEN = 13268; // 43 -const static uint64_t SH_FLD_SEQ_21_05EVEN_LEN = 13269; // 43 -const static uint64_t SH_FLD_SEQ_22_05ODD = 13270; // 43 -const static uint64_t SH_FLD_SEQ_22_05ODD_LEN = 13271; // 43 -const static uint64_t SH_FLD_SEQ_23_06EVEN = 13272; // 43 -const static uint64_t SH_FLD_SEQ_23_06EVEN_LEN = 13273; // 43 -const static uint64_t SH_FLD_SEQ_24_06ODD = 13274; // 43 -const static uint64_t SH_FLD_SEQ_24_06ODD_LEN = 13275; // 43 -const static uint64_t SH_FLD_SEQ_MASK = 13276; // 8 -const static uint64_t SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK = 13277; // 43 -const static uint64_t SH_FLD_SERVO_CHG_CFG = 13278; // 6 -const static uint64_t SH_FLD_SERVO_CHG_CFG_LEN = 13279; // 6 -const static uint64_t SH_FLD_SERVO_DONE = 13280; // 6 -const static uint64_t SH_FLD_SERVO_OP = 13281; // 6 -const static uint64_t SH_FLD_SERVO_OP_LEN = 13282; // 6 -const static uint64_t SH_FLD_SERVO_RECAL_IP = 13283; // 4 -const static uint64_t SH_FLD_SERVO_RESULT = 13284; // 6 -const static uint64_t SH_FLD_SERVO_RESULT_LEN = 13285; // 6 -const static uint64_t SH_FLD_SERVO_THRESH1 = 13286; // 6 -const static uint64_t SH_FLD_SERVO_THRESH1_LEN = 13287; // 6 -const static uint64_t SH_FLD_SERVO_THRESH2 = 13288; // 6 -const static uint64_t SH_FLD_SERVO_THRESH2_LEN = 13289; // 6 -const static uint64_t SH_FLD_SET = 13290; // 6 -const static uint64_t SH_FLD_SET_CMDS = 13291; // 2 -const static uint64_t SH_FLD_SET_CMDS_EN = 13292; // 2 -const static uint64_t SH_FLD_SET_CMDS_LEN = 13293; // 2 -const static uint64_t SH_FLD_SET_ECC_INJECT_ERR = 13294; // 12 -const static uint64_t SH_FLD_SET_INDEX = 13295; // 2 -const static uint64_t SH_FLD_SET_INDEX_LEN = 13296; // 2 -const static uint64_t SH_FLD_SET_LEN = 13297; // 6 -const static uint64_t SH_FLD_SGB_BYTE_VALID = 13298; // 21 -const static uint64_t SH_FLD_SGB_BYTE_VALID_LEN = 13299; // 21 -const static uint64_t SH_FLD_SGB_FLUSH_PENDING = 13300; // 21 -const static uint64_t SH_FLD_SG_HIGH_DURING_FILL = 13301; // 43 -const static uint64_t SH_FLD_SHADOW_ANALOGTUNE = 13302; // 14 -const static uint64_t SH_FLD_SHADOW_ANALOGTUNE_LEN = 13303; // 14 -const static uint64_t SH_FLD_SHADOW_ATSTSEL = 13304; // 14 -const static uint64_t SH_FLD_SHADOW_ATSTSEL_LEN = 13305; // 14 -const static uint64_t SH_FLD_SHADOW_BANDSEL = 13306; // 14 -const static uint64_t SH_FLD_SHADOW_BANDSEL_LEN = 13307; // 14 -const static uint64_t SH_FLD_SHADOW_BGOFFSET = 13308; // 14 -const static uint64_t SH_FLD_SHADOW_BGOFFSET_LEN = 13309; // 14 -const static uint64_t SH_FLD_SHADOW_BYPASSN = 13310; // 10 -const static uint64_t SH_FLD_SHADOW_CALRECAL = 13311; // 10 -const static uint64_t SH_FLD_SHADOW_CALREQ = 13312; // 10 -const static uint64_t SH_FLD_SHADOW_CAPSEL = 13313; // 4 -const static uint64_t SH_FLD_SHADOW_CCALBANDSEL = 13314; // 10 -const static uint64_t SH_FLD_SHADOW_CCALBANDSEL_LEN = 13315; // 10 -const static uint64_t SH_FLD_SHADOW_CCALCOMP = 13316; // 10 -const static uint64_t SH_FLD_SHADOW_CCALCVHOLD = 13317; // 10 -const static uint64_t SH_FLD_SHADOW_CCALERR = 13318; // 10 -const static uint64_t SH_FLD_SHADOW_CCALFMAX = 13319; // 10 -const static uint64_t SH_FLD_SHADOW_CCALFMIN = 13320; // 10 -const static uint64_t SH_FLD_SHADOW_CCALLOAD = 13321; // 10 -const static uint64_t SH_FLD_SHADOW_CCALMETH = 13322; // 10 -const static uint64_t SH_FLD_SHADOW_CMLEN = 13323; // 10 -const static uint64_t SH_FLD_SHADOW_CPISEL = 13324; // 14 -const static uint64_t SH_FLD_SHADOW_CPISEL_LEN = 13325; // 14 -const static uint64_t SH_FLD_SHADOW_CSEL = 13326; // 10 -const static uint64_t SH_FLD_SHADOW_CSEL_LEN = 13327; // 10 -const static uint64_t SH_FLD_SHADOW_DIVSELB = 13328; // 10 -const static uint64_t SH_FLD_SHADOW_DIVSELB_LEN = 13329; // 10 -const static uint64_t SH_FLD_SHADOW_DIVSELFB = 13330; // 4 -const static uint64_t SH_FLD_SHADOW_DIVSELFB_LEN = 13331; // 4 -const static uint64_t SH_FLD_SHADOW_EN = 13332; // 10 -const static uint64_t SH_FLD_SHADOW_ENABLE = 13333; // 10 -const static uint64_t SH_FLD_SHADOW_FILTDIVSEL = 13334; // 3 -const static uint64_t SH_FLD_SHADOW_FILTDIVSEL_LEN = 13335; // 3 -const static uint64_t SH_FLD_SHADOW_FRAC1 = 13336; // 3 -const static uint64_t SH_FLD_SHADOW_FRAC1_LEN = 13337; // 3 -const static uint64_t SH_FLD_SHADOW_FRAC2 = 13338; // 3 -const static uint64_t SH_FLD_SHADOW_FRAC2_LEN = 13339; // 3 -const static uint64_t SH_FLD_SHADOW_ITUNE = 13340; // 4 -const static uint64_t SH_FLD_SHADOW_ITUNE_LEN = 13341; // 4 -const static uint64_t SH_FLD_SHADOW_LOCK = 13342; // 10 -const static uint64_t SH_FLD_SHADOW_MUXEN = 13343; // 4 -const static uint64_t SH_FLD_SHADOW_MUXSEL = 13344; // 4 -const static uint64_t SH_FLD_SHADOW_MUXSEL_LEN = 13345; // 4 -const static uint64_t SH_FLD_SHADOW_PCLKDIFSEL = 13346; // 10 -const static uint64_t SH_FLD_SHADOW_PCLKSEL = 13347; // 14 -const static uint64_t SH_FLD_SHADOW_PCLKSEL_LEN = 13348; // 14 -const static uint64_t SH_FLD_SHADOW_PFD360SEL = 13349; // 4 -const static uint64_t SH_FLD_SHADOW_PHASEFB = 13350; // 4 -const static uint64_t SH_FLD_SHADOW_PHASEFB_LEN = 13351; // 4 -const static uint64_t SH_FLD_SHADOW_PLLLOCK = 13352; // 4 -const static uint64_t SH_FLD_SHADOW_RDIV = 13353; // 14 -const static uint64_t SH_FLD_SHADOW_RDIV_LEN = 13354; // 10 -const static uint64_t SH_FLD_SHADOW_REFCLKSEL = 13355; // 4 -const static uint64_t SH_FLD_SHADOW_RESET = 13356; // 10 -const static uint64_t SH_FLD_SHADOW_RESSEL = 13357; // 4 -const static uint64_t SH_FLD_SHADOW_RSEL = 13358; // 10 -const static uint64_t SH_FLD_SHADOW_RSEL_LEN = 13359; // 10 -const static uint64_t SH_FLD_SHADOW_SEL = 13360; // 10 -const static uint64_t SH_FLD_SHADOW_SELD2SPR = 13361; // 10 -const static uint64_t SH_FLD_SHADOW_SELPFDPW = 13362; // 10 -const static uint64_t SH_FLD_SHADOW_SELPREFB = 13363; // 10 -const static uint64_t SH_FLD_SHADOW_SELPRESPE = 13364; // 10 -const static uint64_t SH_FLD_SHADOW_SEL_LEN = 13365; // 10 -const static uint64_t SH_FLD_SHADOW_SPARE = 13366; // 7 -const static uint64_t SH_FLD_SHADOW_SPARE_LEN = 13367; // 3 -const static uint64_t SH_FLD_SHADOW_SPEDIV = 13368; // 10 -const static uint64_t SH_FLD_SHADOW_SPEDIV_LEN = 13369; // 10 -const static uint64_t SH_FLD_SHADOW_SSCGEN = 13370; // 3 -const static uint64_t SH_FLD_SHADOW_SYNCEN = 13371; // 7 -const static uint64_t SH_FLD_SHADOW_THREEPHAS = 13372; // 3 -const static uint64_t SH_FLD_SHADOW_UNUSED23_31 = 13373; // 7 -const static uint64_t SH_FLD_SHADOW_UNUSED23_31_LEN = 13374; // 7 -const static uint64_t SH_FLD_SHADOW_UNUSED4 = 13375; // 7 -const static uint64_t SH_FLD_SHADOW_UNUSED5 = 13376; // 7 -const static uint64_t SH_FLD_SHADOW_UNUSED63 = 13377; // 3 -const static uint64_t SH_FLD_SHADOW_UNUSED88 = 13378; // 3 -const static uint64_t SH_FLD_SHADOW_UNUSED88_LEN = 13379; // 3 -const static uint64_t SH_FLD_SHADOW_VCORANGE = 13380; // 10 -const static uint64_t SH_FLD_SHADOW_VCORANGE_LEN = 13381; // 10 -const static uint64_t SH_FLD_SHADOW_VCOSEL = 13382; // 10 -const static uint64_t SH_FLD_SHADOW_VREGBYPASS = 13383; // 4 -const static uint64_t SH_FLD_SHADOW_VREGENABLE_N = 13384; // 4 -const static uint64_t SH_FLD_SHADOW_VSEL = 13385; // 10 -const static uint64_t SH_FLD_SHADOW_VSEL_LEN = 13386; // 10 -const static uint64_t SH_FLD_SHA_LATENCY_CFG = 13387; // 1 -const static uint64_t SH_FLD_SHIFTER_PARITY_MASK = 13388; // 43 -const static uint64_t SH_FLD_SHIFTER_VALID_MASK = 13389; // 43 -const static uint64_t SH_FLD_SIGNATURE = 13390; // 1 -const static uint64_t SH_FLD_SIGNATURE_LEN = 13391; // 1 -const static uint64_t SH_FLD_SINGLE_BIT_MPR_RP0 = 13392; // 8 -const static uint64_t SH_FLD_SINGLE_BIT_MPR_RP1 = 13393; // 8 -const static uint64_t SH_FLD_SINGLE_BIT_MPR_RP2 = 13394; // 8 -const static uint64_t SH_FLD_SINGLE_BIT_MPR_RP3 = 13395; // 8 -const static uint64_t SH_FLD_SINGLE_OUTSTANDING_CMD = 13396; // 1 -const static uint64_t SH_FLD_SIR_CERR = 13397; // 8 -const static uint64_t SH_FLD_SIZE = 13398; // 33 -const static uint64_t SH_FLD_SIZE_LEN = 13399; // 33 -const static uint64_t SH_FLD_SKIP_G = 13400; // 3 -const static uint64_t SH_FLD_SKIP_INVALID_ADDR_DIMM_DIS = 13401; // 2 -const static uint64_t SH_FLD_SKITTER0 = 13402; // 43 -const static uint64_t SH_FLD_SKITTER0_LEN = 13403; // 43 -const static uint64_t SH_FLD_SKITTER_FORCEREG_PARITY_MASK = 13404; // 43 -const static uint64_t SH_FLD_SKITTER_MODEREG_PARITY_MASK = 13405; // 43 -const static uint64_t SH_FLD_SLAVE10_ERROR_CODE = 13406; // 1 -const static uint64_t SH_FLD_SLAVE10_ERROR_CODE_LEN = 13407; // 1 -const static uint64_t SH_FLD_SLAVE10_RESPONSE_BIT = 13408; // 1 -const static uint64_t SH_FLD_SLAVE11_ERROR_CODE = 13409; // 1 -const static uint64_t SH_FLD_SLAVE11_ERROR_CODE_LEN = 13410; // 1 -const static uint64_t SH_FLD_SLAVE11_RESPONSE_BIT = 13411; // 1 -const static uint64_t SH_FLD_SLAVE12_ERROR_CODE = 13412; // 1 -const static uint64_t SH_FLD_SLAVE12_ERROR_CODE_LEN = 13413; // 1 -const static uint64_t SH_FLD_SLAVE12_RESPONSE_BIT = 13414; // 1 -const static uint64_t SH_FLD_SLAVE13_ERROR_CODE = 13415; // 1 -const static uint64_t SH_FLD_SLAVE13_ERROR_CODE_LEN = 13416; // 1 -const static uint64_t SH_FLD_SLAVE13_RESPONSE_BIT = 13417; // 1 -const static uint64_t SH_FLD_SLAVE14_ERROR_CODE = 13418; // 1 -const static uint64_t SH_FLD_SLAVE14_ERROR_CODE_LEN = 13419; // 1 -const static uint64_t SH_FLD_SLAVE14_RESPONSE_BIT = 13420; // 1 -const static uint64_t SH_FLD_SLAVE15_ERROR_CODE = 13421; // 1 -const static uint64_t SH_FLD_SLAVE15_ERROR_CODE_LEN = 13422; // 1 -const static uint64_t SH_FLD_SLAVE15_RESPONSE_BIT = 13423; // 1 -const static uint64_t SH_FLD_SLAVE16_ERROR_CODE = 13424; // 1 -const static uint64_t SH_FLD_SLAVE16_ERROR_CODE_LEN = 13425; // 1 -const static uint64_t SH_FLD_SLAVE16_RESPONSE_BIT = 13426; // 1 -const static uint64_t SH_FLD_SLAVE17_ERROR_CODE = 13427; // 1 -const static uint64_t SH_FLD_SLAVE17_ERROR_CODE_LEN = 13428; // 1 -const static uint64_t SH_FLD_SLAVE17_RESPONSE_BIT = 13429; // 1 -const static uint64_t SH_FLD_SLAVE18_ERROR_CODE = 13430; // 1 -const static uint64_t SH_FLD_SLAVE18_ERROR_CODE_LEN = 13431; // 1 -const static uint64_t SH_FLD_SLAVE18_RESPONSE_BIT = 13432; // 1 -const static uint64_t SH_FLD_SLAVE19_ERROR_CODE = 13433; // 1 -const static uint64_t SH_FLD_SLAVE19_ERROR_CODE_LEN = 13434; // 1 -const static uint64_t SH_FLD_SLAVE19_RESPONSE_BIT = 13435; // 1 -const static uint64_t SH_FLD_SLAVE1_ERROR_CODE = 13436; // 1 -const static uint64_t SH_FLD_SLAVE1_ERROR_CODE_LEN = 13437; // 1 -const static uint64_t SH_FLD_SLAVE1_RESPONSE_BIT = 13438; // 1 -const static uint64_t SH_FLD_SLAVE20_ERROR_CODE = 13439; // 1 -const static uint64_t SH_FLD_SLAVE20_ERROR_CODE_LEN = 13440; // 1 -const static uint64_t SH_FLD_SLAVE20_RESPONSE_BIT = 13441; // 1 -const static uint64_t SH_FLD_SLAVE21_ERROR_CODE = 13442; // 1 -const static uint64_t SH_FLD_SLAVE21_ERROR_CODE_LEN = 13443; // 1 -const static uint64_t SH_FLD_SLAVE21_RESPONSE_BIT = 13444; // 1 -const static uint64_t SH_FLD_SLAVE22_ERROR_CODE = 13445; // 1 -const static uint64_t SH_FLD_SLAVE22_ERROR_CODE_LEN = 13446; // 1 -const static uint64_t SH_FLD_SLAVE22_RESPONSE_BIT = 13447; // 1 -const static uint64_t SH_FLD_SLAVE23_ERROR_CODE = 13448; // 1 -const static uint64_t SH_FLD_SLAVE23_ERROR_CODE_LEN = 13449; // 1 -const static uint64_t SH_FLD_SLAVE23_RESPONSE_BIT = 13450; // 1 -const static uint64_t SH_FLD_SLAVE24_ERROR_CODE = 13451; // 1 -const static uint64_t SH_FLD_SLAVE24_ERROR_CODE_LEN = 13452; // 1 -const static uint64_t SH_FLD_SLAVE24_RESPONSE_BIT = 13453; // 1 -const static uint64_t SH_FLD_SLAVE25_ERROR_CODE = 13454; // 1 -const static uint64_t SH_FLD_SLAVE25_ERROR_CODE_LEN = 13455; // 1 -const static uint64_t SH_FLD_SLAVE25_RESPONSE_BIT = 13456; // 1 -const static uint64_t SH_FLD_SLAVE26_ERROR_CODE = 13457; // 1 -const static uint64_t SH_FLD_SLAVE26_ERROR_CODE_LEN = 13458; // 1 -const static uint64_t SH_FLD_SLAVE26_RESPONSE_BIT = 13459; // 1 -const static uint64_t SH_FLD_SLAVE27_ERROR_CODE = 13460; // 1 -const static uint64_t SH_FLD_SLAVE27_ERROR_CODE_LEN = 13461; // 1 -const static uint64_t SH_FLD_SLAVE27_RESPONSE_BIT = 13462; // 1 -const static uint64_t SH_FLD_SLAVE28_ERROR_CODE = 13463; // 1 -const static uint64_t SH_FLD_SLAVE28_ERROR_CODE_LEN = 13464; // 1 -const static uint64_t SH_FLD_SLAVE28_RESPONSE_BIT = 13465; // 1 -const static uint64_t SH_FLD_SLAVE29_ERROR_CODE = 13466; // 1 -const static uint64_t SH_FLD_SLAVE29_ERROR_CODE_LEN = 13467; // 1 -const static uint64_t SH_FLD_SLAVE29_RESPONSE_BIT = 13468; // 1 -const static uint64_t SH_FLD_SLAVE2_ERROR_CODE = 13469; // 1 -const static uint64_t SH_FLD_SLAVE2_ERROR_CODE_LEN = 13470; // 1 -const static uint64_t SH_FLD_SLAVE2_RESPONSE_BIT = 13471; // 1 -const static uint64_t SH_FLD_SLAVE30_ERROR_CODE = 13472; // 1 -const static uint64_t SH_FLD_SLAVE30_ERROR_CODE_LEN = 13473; // 1 -const static uint64_t SH_FLD_SLAVE30_RESPONSE_BIT = 13474; // 1 -const static uint64_t SH_FLD_SLAVE31_ERROR_CODE = 13475; // 1 -const static uint64_t SH_FLD_SLAVE31_ERROR_CODE_LEN = 13476; // 1 -const static uint64_t SH_FLD_SLAVE31_RESPONSE_BIT = 13477; // 1 -const static uint64_t SH_FLD_SLAVE32_ERROR_CODE = 13478; // 1 -const static uint64_t SH_FLD_SLAVE32_ERROR_CODE_LEN = 13479; // 1 -const static uint64_t SH_FLD_SLAVE32_RESPONSE_BIT = 13480; // 1 -const static uint64_t SH_FLD_SLAVE33_ERROR_CODE = 13481; // 1 -const static uint64_t SH_FLD_SLAVE33_ERROR_CODE_LEN = 13482; // 1 -const static uint64_t SH_FLD_SLAVE33_RESPONSE_BIT = 13483; // 1 -const static uint64_t SH_FLD_SLAVE34_ERROR_CODE = 13484; // 1 -const static uint64_t SH_FLD_SLAVE34_ERROR_CODE_LEN = 13485; // 1 -const static uint64_t SH_FLD_SLAVE34_RESPONSE_BIT = 13486; // 1 -const static uint64_t SH_FLD_SLAVE35_ERROR_CODE = 13487; // 1 -const static uint64_t SH_FLD_SLAVE35_ERROR_CODE_LEN = 13488; // 1 -const static uint64_t SH_FLD_SLAVE35_RESPONSE_BIT = 13489; // 1 -const static uint64_t SH_FLD_SLAVE36_ERROR_CODE = 13490; // 1 -const static uint64_t SH_FLD_SLAVE36_ERROR_CODE_LEN = 13491; // 1 -const static uint64_t SH_FLD_SLAVE36_RESPONSE_BIT = 13492; // 1 -const static uint64_t SH_FLD_SLAVE37_ERROR_CODE = 13493; // 1 -const static uint64_t SH_FLD_SLAVE37_ERROR_CODE_LEN = 13494; // 1 -const static uint64_t SH_FLD_SLAVE37_RESPONSE_BIT = 13495; // 1 -const static uint64_t SH_FLD_SLAVE38_ERROR_CODE = 13496; // 1 -const static uint64_t SH_FLD_SLAVE38_ERROR_CODE_LEN = 13497; // 1 -const static uint64_t SH_FLD_SLAVE38_RESPONSE_BIT = 13498; // 1 -const static uint64_t SH_FLD_SLAVE39_ERROR_CODE = 13499; // 1 -const static uint64_t SH_FLD_SLAVE39_ERROR_CODE_LEN = 13500; // 1 -const static uint64_t SH_FLD_SLAVE39_RESPONSE_BIT = 13501; // 1 -const static uint64_t SH_FLD_SLAVE3_ERROR_CODE = 13502; // 1 -const static uint64_t SH_FLD_SLAVE3_ERROR_CODE_LEN = 13503; // 1 -const static uint64_t SH_FLD_SLAVE3_RESPONSE_BIT = 13504; // 1 -const static uint64_t SH_FLD_SLAVE40_ERROR_CODE = 13505; // 1 -const static uint64_t SH_FLD_SLAVE40_ERROR_CODE_LEN = 13506; // 1 -const static uint64_t SH_FLD_SLAVE40_RESPONSE_BIT = 13507; // 1 -const static uint64_t SH_FLD_SLAVE41_ERROR_CODE = 13508; // 1 -const static uint64_t SH_FLD_SLAVE41_ERROR_CODE_LEN = 13509; // 1 -const static uint64_t SH_FLD_SLAVE41_RESPONSE_BIT = 13510; // 1 -const static uint64_t SH_FLD_SLAVE42_ERROR_CODE = 13511; // 1 -const static uint64_t SH_FLD_SLAVE42_ERROR_CODE_LEN = 13512; // 1 -const static uint64_t SH_FLD_SLAVE42_RESPONSE_BIT = 13513; // 1 -const static uint64_t SH_FLD_SLAVE43_ERROR_CODE = 13514; // 1 -const static uint64_t SH_FLD_SLAVE43_ERROR_CODE_LEN = 13515; // 1 -const static uint64_t SH_FLD_SLAVE43_RESPONSE_BIT = 13516; // 1 -const static uint64_t SH_FLD_SLAVE44_ERROR_CODE = 13517; // 1 -const static uint64_t SH_FLD_SLAVE44_ERROR_CODE_LEN = 13518; // 1 -const static uint64_t SH_FLD_SLAVE44_RESPONSE_BIT = 13519; // 1 -const static uint64_t SH_FLD_SLAVE45_ERROR_CODE = 13520; // 1 -const static uint64_t SH_FLD_SLAVE45_ERROR_CODE_LEN = 13521; // 1 -const static uint64_t SH_FLD_SLAVE45_RESPONSE_BIT = 13522; // 1 -const static uint64_t SH_FLD_SLAVE46_ERROR_CODE = 13523; // 1 -const static uint64_t SH_FLD_SLAVE46_ERROR_CODE_LEN = 13524; // 1 -const static uint64_t SH_FLD_SLAVE46_RESPONSE_BIT = 13525; // 1 -const static uint64_t SH_FLD_SLAVE47_ERROR_CODE = 13526; // 1 -const static uint64_t SH_FLD_SLAVE47_ERROR_CODE_LEN = 13527; // 1 -const static uint64_t SH_FLD_SLAVE47_RESPONSE_BIT = 13528; // 1 -const static uint64_t SH_FLD_SLAVE48_ERROR_CODE = 13529; // 1 -const static uint64_t SH_FLD_SLAVE48_ERROR_CODE_LEN = 13530; // 1 -const static uint64_t SH_FLD_SLAVE48_RESPONSE_BIT = 13531; // 1 -const static uint64_t SH_FLD_SLAVE49_ERROR_CODE = 13532; // 1 -const static uint64_t SH_FLD_SLAVE49_ERROR_CODE_LEN = 13533; // 1 -const static uint64_t SH_FLD_SLAVE49_RESPONSE_BIT = 13534; // 1 -const static uint64_t SH_FLD_SLAVE4_ERROR_CODE = 13535; // 1 -const static uint64_t SH_FLD_SLAVE4_ERROR_CODE_LEN = 13536; // 1 -const static uint64_t SH_FLD_SLAVE4_RESPONSE_BIT = 13537; // 1 -const static uint64_t SH_FLD_SLAVE50_ERROR_CODE = 13538; // 1 -const static uint64_t SH_FLD_SLAVE50_ERROR_CODE_LEN = 13539; // 1 -const static uint64_t SH_FLD_SLAVE50_RESPONSE_BIT = 13540; // 1 -const static uint64_t SH_FLD_SLAVE51_ERROR_CODE = 13541; // 1 -const static uint64_t SH_FLD_SLAVE51_ERROR_CODE_LEN = 13542; // 1 -const static uint64_t SH_FLD_SLAVE51_RESPONSE_BIT = 13543; // 1 -const static uint64_t SH_FLD_SLAVE52_ERROR_CODE = 13544; // 1 -const static uint64_t SH_FLD_SLAVE52_ERROR_CODE_LEN = 13545; // 1 -const static uint64_t SH_FLD_SLAVE52_RESPONSE_BIT = 13546; // 1 -const static uint64_t SH_FLD_SLAVE53_ERROR_CODE = 13547; // 1 -const static uint64_t SH_FLD_SLAVE53_ERROR_CODE_LEN = 13548; // 1 -const static uint64_t SH_FLD_SLAVE53_RESPONSE_BIT = 13549; // 1 -const static uint64_t SH_FLD_SLAVE54_ERROR_CODE = 13550; // 1 -const static uint64_t SH_FLD_SLAVE54_ERROR_CODE_LEN = 13551; // 1 -const static uint64_t SH_FLD_SLAVE54_RESPONSE_BIT = 13552; // 1 -const static uint64_t SH_FLD_SLAVE55_ERROR_CODE = 13553; // 1 -const static uint64_t SH_FLD_SLAVE55_ERROR_CODE_LEN = 13554; // 1 -const static uint64_t SH_FLD_SLAVE55_RESPONSE_BIT = 13555; // 1 -const static uint64_t SH_FLD_SLAVE56_ERROR_CODE = 13556; // 1 -const static uint64_t SH_FLD_SLAVE56_ERROR_CODE_LEN = 13557; // 1 -const static uint64_t SH_FLD_SLAVE56_RESPONSE_BIT = 13558; // 1 -const static uint64_t SH_FLD_SLAVE57_ERROR_CODE = 13559; // 1 -const static uint64_t SH_FLD_SLAVE57_ERROR_CODE_LEN = 13560; // 1 -const static uint64_t SH_FLD_SLAVE57_RESPONSE_BIT = 13561; // 1 -const static uint64_t SH_FLD_SLAVE58_ERROR_CODE = 13562; // 1 -const static uint64_t SH_FLD_SLAVE58_ERROR_CODE_LEN = 13563; // 1 -const static uint64_t SH_FLD_SLAVE58_RESPONSE_BIT = 13564; // 1 -const static uint64_t SH_FLD_SLAVE59_ERROR_CODE = 13565; // 1 -const static uint64_t SH_FLD_SLAVE59_ERROR_CODE_LEN = 13566; // 1 -const static uint64_t SH_FLD_SLAVE59_RESPONSE_BIT = 13567; // 1 -const static uint64_t SH_FLD_SLAVE5_ERROR_CODE = 13568; // 1 -const static uint64_t SH_FLD_SLAVE5_ERROR_CODE_LEN = 13569; // 1 -const static uint64_t SH_FLD_SLAVE5_RESPONSE_BIT = 13570; // 1 -const static uint64_t SH_FLD_SLAVE60_ERROR_CODE = 13571; // 1 -const static uint64_t SH_FLD_SLAVE60_ERROR_CODE_LEN = 13572; // 1 -const static uint64_t SH_FLD_SLAVE60_RESPONSE_BIT = 13573; // 1 -const static uint64_t SH_FLD_SLAVE61_ERROR_CODE = 13574; // 1 -const static uint64_t SH_FLD_SLAVE61_ERROR_CODE_LEN = 13575; // 1 -const static uint64_t SH_FLD_SLAVE61_RESPONSE_BIT = 13576; // 1 -const static uint64_t SH_FLD_SLAVE62_ERROR_CODE = 13577; // 1 -const static uint64_t SH_FLD_SLAVE62_ERROR_CODE_LEN = 13578; // 1 -const static uint64_t SH_FLD_SLAVE62_RESPONSE_BIT = 13579; // 1 -const static uint64_t SH_FLD_SLAVE63_ERROR_CODE = 13580; // 1 -const static uint64_t SH_FLD_SLAVE63_ERROR_CODE_LEN = 13581; // 1 -const static uint64_t SH_FLD_SLAVE63_RESPONSE_BIT = 13582; // 1 -const static uint64_t SH_FLD_SLAVE6_ERROR_CODE = 13583; // 1 -const static uint64_t SH_FLD_SLAVE6_ERROR_CODE_LEN = 13584; // 1 -const static uint64_t SH_FLD_SLAVE6_RESPONSE_BIT = 13585; // 1 -const static uint64_t SH_FLD_SLAVE7_ERROR_CODE = 13586; // 1 -const static uint64_t SH_FLD_SLAVE7_ERROR_CODE_LEN = 13587; // 1 -const static uint64_t SH_FLD_SLAVE7_RESPONSE_BIT = 13588; // 1 -const static uint64_t SH_FLD_SLAVE8_ERROR_CODE = 13589; // 1 -const static uint64_t SH_FLD_SLAVE8_ERROR_CODE_LEN = 13590; // 1 -const static uint64_t SH_FLD_SLAVE8_RESPONSE_BIT = 13591; // 1 -const static uint64_t SH_FLD_SLAVE9_ERROR_CODE = 13592; // 1 -const static uint64_t SH_FLD_SLAVE9_ERROR_CODE_LEN = 13593; // 1 -const static uint64_t SH_FLD_SLAVE9_RESPONSE_BIT = 13594; // 1 -const static uint64_t SH_FLD_SLAVE_IDLE = 13595; // 1 -const static uint64_t SH_FLD_SLAVE_MODE = 13596; // 43 -const static uint64_t SH_FLD_SLAVE_RESET_TO_405_ENABLE = 13597; // 1 -const static uint64_t SH_FLD_SLBI_GROUP_PUMP_EN = 13598; // 12 -const static uint64_t SH_FLD_SLB_BUS0_STG1_SEL = 13599; // 1 -const static uint64_t SH_FLD_SLB_BUS0_STG2_SEL = 13600; // 1 -const static uint64_t SH_FLD_SLB_BUS1_STG1_SEL = 13601; // 1 -const static uint64_t SH_FLD_SLB_BUS1_STG2_SEL = 13602; // 1 -const static uint64_t SH_FLD_SLEWCTL = 13603; // 1 -const static uint64_t SH_FLD_SLEWCTL_LEN = 13604; // 1 -const static uint64_t SH_FLD_SLICE = 13605; // 3 -const static uint64_t SH_FLD_SLICE0_CFG_ECC_CE_ERR = 13606; // 2 -const static uint64_t SH_FLD_SLICE0_CFG_ECC_UE_ERR = 13607; // 2 -const static uint64_t SH_FLD_SLICE1_CFG_ECC_CE_ERR = 13608; // 2 -const static uint64_t SH_FLD_SLICE1_CFG_ECC_UE_ERR = 13609; // 2 -const static uint64_t SH_FLD_SLICE2_CFG_ECC_CE_ERR = 13610; // 2 -const static uint64_t SH_FLD_SLICE2_CFG_ECC_UE_ERR = 13611; // 2 -const static uint64_t SH_FLD_SLICE3_CFG_ECC_CE_ERR = 13612; // 2 -const static uint64_t SH_FLD_SLICE3_CFG_ECC_UE_ERR = 13613; // 2 -const static uint64_t SH_FLD_SLICE_LEN = 13614; // 3 -const static uint64_t SH_FLD_SLOT0_B2_VALID = 13615; // 8 -const static uint64_t SH_FLD_SLOT0_D_VALUE = 13616; // 8 -const static uint64_t SH_FLD_SLOT0_M0_VALID = 13617; // 8 -const static uint64_t SH_FLD_SLOT0_M1_VALID = 13618; // 8 -const static uint64_t SH_FLD_SLOT0_ROW15_VALID = 13619; // 8 -const static uint64_t SH_FLD_SLOT0_ROW16_VALID = 13620; // 8 -const static uint64_t SH_FLD_SLOT0_ROW17_VALID = 13621; // 8 -const static uint64_t SH_FLD_SLOT0_S0_VALID = 13622; // 8 -const static uint64_t SH_FLD_SLOT0_S1_VALID = 13623; // 8 -const static uint64_t SH_FLD_SLOT0_S2_VALID = 13624; // 8 -const static uint64_t SH_FLD_SLOT0_VALID = 13625; // 8 -const static uint64_t SH_FLD_SLOT1_B2_VALID = 13626; // 8 -const static uint64_t SH_FLD_SLOT1_D_VALUE = 13627; // 8 -const static uint64_t SH_FLD_SLOT1_M0_VALID = 13628; // 8 -const static uint64_t SH_FLD_SLOT1_M1_VALID = 13629; // 8 -const static uint64_t SH_FLD_SLOT1_ROW15_VALID = 13630; // 8 -const static uint64_t SH_FLD_SLOT1_ROW16_VALID = 13631; // 8 -const static uint64_t SH_FLD_SLOT1_ROW17_VALID = 13632; // 8 -const static uint64_t SH_FLD_SLOT1_S0_VALID = 13633; // 8 -const static uint64_t SH_FLD_SLOT1_S1_VALID = 13634; // 8 -const static uint64_t SH_FLD_SLOT1_S2_VALID = 13635; // 8 -const static uint64_t SH_FLD_SLOT1_VALID = 13636; // 8 -const static uint64_t SH_FLD_SLOW_CMD_RATE = 13637; // 1 -const static uint64_t SH_FLD_SLS_CMD_GCRMSG = 13638; // 4 -const static uint64_t SH_FLD_SLS_CMD_GCRMSG_LEN = 13639; // 4 -const static uint64_t SH_FLD_SLS_CNTR_TAP_PTS = 13640; // 4 -const static uint64_t SH_FLD_SLS_CNTR_TAP_PTS_LEN = 13641; // 4 -const static uint64_t SH_FLD_SLS_DISABLE = 13642; // 4 -const static uint64_t SH_FLD_SLS_EXCEPTION2_CS = 13643; // 4 -const static uint64_t SH_FLD_SLS_EXTEND_SEL = 13644; // 4 -const static uint64_t SH_FLD_SLS_EXTEND_SEL_LEN = 13645; // 4 -const static uint64_t SH_FLD_SLS_LANE_GCRMSG = 13646; // 4 -const static uint64_t SH_FLD_SLS_LANE_GCRMSG_LEN = 13647; // 4 -const static uint64_t SH_FLD_SLS_LANE_SEL_LG_GCRMSG = 13648; // 4 -const static uint64_t SH_FLD_SLS_LANE_SHDW_GCRMSG = 13649; // 4 -const static uint64_t SH_FLD_SLS_LANE_UNSEL_LG_GCRMSG = 13650; // 4 -const static uint64_t SH_FLD_SLS_LANE_VAL_GCRMSG = 13651; // 4 -const static uint64_t SH_FLD_SLS_SCRAMBLE_MODE = 13652; // 4 -const static uint64_t SH_FLD_SLS_SCRAMBLE_MODE_LEN = 13653; // 4 -const static uint64_t SH_FLD_SLS_TIMEOUT_SEL = 13654; // 4 -const static uint64_t SH_FLD_SLS_TIMEOUT_SEL_LEN = 13655; // 4 -const static uint64_t SH_FLD_SLV_DIS_ABUSPAR = 13656; // 1 -const static uint64_t SH_FLD_SLV_DIS_BE = 13657; // 1 -const static uint64_t SH_FLD_SLV_DIS_BEPAR = 13658; // 1 -const static uint64_t SH_FLD_SLV_DIS_RDDBUSPAREN = 13659; // 1 -const static uint64_t SH_FLD_SLV_DIS_SACK = 13660; // 1 -const static uint64_t SH_FLD_SLV_DIS_WRDBUSPAR = 13661; // 1 -const static uint64_t SH_FLD_SLV_EVENT_MUX = 13662; // 1 -const static uint64_t SH_FLD_SLV_EVENT_MUX_LEN = 13663; // 1 -const static uint64_t SH_FLD_SLV_LGL_RPR_REQ_GCRMSG = 13664; // 4 -const static uint64_t SH_FLD_SLV_MV_SLS_RPR_REQ_GCRMSG = 13665; // 4 -const static uint64_t SH_FLD_SLV_MV_SLS_SHDW_REQ_GCRMSG = 13666; // 4 -const static uint64_t SH_FLD_SLV_MV_SLS_SHDW_RPR_REQ_GCRMSG = 13667; // 4 -const static uint64_t SH_FLD_SLV_MV_SLS_UNSHDW_REQ_GCRMSG = 13668; // 4 -const static uint64_t SH_FLD_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG = 13669; // 4 -const static uint64_t SH_FLD_SLV_RECAL_ABORT_ACK_FIN_GCRMSG = 13670; // 4 -const static uint64_t SH_FLD_SLV_RECAL_ABORT_MNOP_FIN_GCRMSG = 13671; // 4 -const static uint64_t SH_FLD_SLV_RECAL_ABORT_SNOP_FIN_GCRMSG = 13672; // 4 -const static uint64_t SH_FLD_SLV_RECAL_DONE_NOP_FIN_GCRMSG = 13673; // 4 -const static uint64_t SH_FLD_SLV_RECAL_FAIL_NOP_FIN_GCRMSG = 13674; // 4 -const static uint64_t SH_FLD_SLV_RECAL_FRESULTS_FIN_GCRMSG = 13675; // 4 -const static uint64_t SH_FLD_SLV_SHDW_DONE_FIN_GCRMSG = 13676; // 4 -const static uint64_t SH_FLD_SLV_SHDW_NOP_FIN_GCRMSG = 13677; // 4 -const static uint64_t SH_FLD_SLV_SHDW_RPR_DONE_FIN_GCRMSG = 13678; // 4 -const static uint64_t SH_FLD_SLV_SHDW_RPR_NOP_FIN_GCRMSG = 13679; // 4 -const static uint64_t SH_FLD_SLV_SPARE = 13680; // 1 -const static uint64_t SH_FLD_SLV_UNSHDW_DONE_FIN_GCRMSG = 13681; // 4 -const static uint64_t SH_FLD_SLV_UNSHDW_NOP_FIN_GCRMSG = 13682; // 4 -const static uint64_t SH_FLD_SLV_UNSHDW_RPR_DONE_FIN_GCRMSG = 13683; // 4 -const static uint64_t SH_FLD_SLV_UNSHDW_RPR_NOP_FIN_GCRMSG = 13684; // 4 -const static uint64_t SH_FLD_SMALL_STEP = 13685; // 8 -const static uint64_t SH_FLD_SMALL_STEP_LEN = 13686; // 8 -const static uint64_t SH_FLD_SMASK_IN = 13687; // 43 -const static uint64_t SH_FLD_SMASK_IN_LEN = 13688; // 43 -const static uint64_t SH_FLD_SM_1HOT_ERR = 13689; // 16 -const static uint64_t SH_FLD_SM_RESET = 13690; // 1 -const static uint64_t SH_FLD_SND_CHIPID = 13691; // 1 -const static uint64_t SH_FLD_SND_CHIPID_LEN = 13692; // 1 -const static uint64_t SH_FLD_SND_CNT = 13693; // 1 -const static uint64_t SH_FLD_SND_CNT_LEN = 13694; // 1 -const static uint64_t SH_FLD_SND_CNT_STATUS = 13695; // 1 -const static uint64_t SH_FLD_SND_CNT_STATUS_LEN = 13696; // 1 -const static uint64_t SH_FLD_SND_ERROR = 13697; // 1 -const static uint64_t SH_FLD_SND_GROUPID = 13698; // 1 -const static uint64_t SH_FLD_SND_GROUPID_LEN = 13699; // 1 -const static uint64_t SH_FLD_SND_IN_PROGRESS = 13700; // 1 -const static uint64_t SH_FLD_SND_PHASE_STATUS = 13701; // 1 -const static uint64_t SH_FLD_SND_PHASE_STATUS_LEN = 13702; // 1 -const static uint64_t SH_FLD_SND_QID = 13703; // 1 -const static uint64_t SH_FLD_SND_RESERVATION = 13704; // 1 -const static uint64_t SH_FLD_SND_RESET = 13705; // 1 -const static uint64_t SH_FLD_SND_RETRY_COUNT = 13706; // 1 -const static uint64_t SH_FLD_SND_RETRY_COUNT_LEN = 13707; // 1 -const static uint64_t SH_FLD_SND_RETRY_COUNT_OVERCOM = 13708; // 1 -const static uint64_t SH_FLD_SND_RETRY_THRESH = 13709; // 1 -const static uint64_t SH_FLD_SND_RETRY_THRESH_LEN = 13710; // 1 -const static uint64_t SH_FLD_SND_RSVTO_DIV = 13711; // 1 -const static uint64_t SH_FLD_SND_RSVTO_DIV_LEN = 13712; // 1 -const static uint64_t SH_FLD_SND_SCOPE = 13713; // 1 -const static uint64_t SH_FLD_SND_SCOPE_LEN = 13714; // 1 -const static uint64_t SH_FLD_SND_SLS_CMD_GCRMSG = 13715; // 4 -const static uint64_t SH_FLD_SND_SLS_CMD_PREV_GCRMSG = 13716; // 4 -const static uint64_t SH_FLD_SND_SLS_USING_REG_SCRAMBLE = 13717; // 4 -const static uint64_t SH_FLD_SND_STOP = 13718; // 1 -const static uint64_t SH_FLD_SND_TYPE = 13719; // 1 -const static uint64_t SH_FLD_SNFSM_ADDR_ERR = 13720; // 12 -const static uint64_t SH_FLD_SNGL_THD_EN = 13721; // 2 -const static uint64_t SH_FLD_SNOOPER_RECOVERABLE_ERROR = 13722; // 4 -const static uint64_t SH_FLD_SNOOPER_SYS_XSTOP_ERROR = 13723; // 4 -const static uint64_t SH_FLD_SNOOP_ARRAY_CE = 13724; // 4 -const static uint64_t SH_FLD_SNOOP_ARRAY_UE = 13725; // 4 -const static uint64_t SH_FLD_SNOOP_DIS = 13726; // 8 -const static uint64_t SH_FLD_SNOP = 13727; // 43 -const static uint64_t SH_FLD_SNOP_FORCE_SG = 13728; // 43 -const static uint64_t SH_FLD_SNOP_LEN = 13729; // 43 -const static uint64_t SH_FLD_SNOP_WAIT = 13730; // 43 -const static uint64_t SH_FLD_SNOP_WAIT_LEN = 13731; // 43 -const static uint64_t SH_FLD_SNP_REG_ERR0 = 13732; // 1 -const static uint64_t SH_FLD_SNP_REG_ERR1 = 13733; // 1 -const static uint64_t SH_FLD_SNP_REG_ERR2 = 13734; // 1 -const static uint64_t SH_FLD_SNP_REG_ERR3 = 13735; // 1 -const static uint64_t SH_FLD_SNP_REG_ERR4 = 13736; // 1 -const static uint64_t SH_FLD_SNP_REG_ERR5 = 13737; // 1 -const static uint64_t SH_FLD_SNP_REG_ERR6 = 13738; // 1 -const static uint64_t SH_FLD_SNS1_UNUSED_0_31 = 13739; // 1 -const static uint64_t SH_FLD_SNS1_UNUSED_0_31_LEN = 13740; // 1 -const static uint64_t SH_FLD_SNS2_UNUSED_0_31 = 13741; // 1 -const static uint64_t SH_FLD_SNS2_UNUSED_0_31_LEN = 13742; // 1 -const static uint64_t SH_FLD_SN_MACHINE_HANG_ERR = 13743; // 12 -const static uint64_t SH_FLD_SN_MSG_MAX_CREDIT = 13744; // 2 -const static uint64_t SH_FLD_SN_MSG_MAX_CREDIT_LEN = 13745; // 2 -const static uint64_t SH_FLD_SN_UNSOLICITED_CRESP_ERR = 13746; // 12 -const static uint64_t SH_FLD_SN_UNSOLICITED_CRESP_ERR_LEN = 13747; // 12 -const static uint64_t SH_FLD_SN_WRT_DBUF_MAX_CREDIT = 13748; // 2 -const static uint64_t SH_FLD_SN_WRT_DBUF_MAX_CREDIT_LEN = 13749; // 2 -const static uint64_t SH_FLD_SOFT_CE_COUNT = 13750; // 2 -const static uint64_t SH_FLD_SOFT_CE_COUNT_LEN = 13751; // 2 -const static uint64_t SH_FLD_SOFT_MCE_COUNT = 13752; // 2 -const static uint64_t SH_FLD_SOFT_MCE_COUNT_LEN = 13753; // 2 -const static uint64_t SH_FLD_SOFT_NCE_ETE_ATTN = 13754; // 10 -const static uint64_t SH_FLD_SOURCE_SELECT = 13755; // 43 -const static uint64_t SH_FLD_SOURCE_SELECT_LEN = 13756; // 43 -const static uint64_t SH_FLD_SOURCE_SUBUNIT_0_1 = 13757; // 1 -const static uint64_t SH_FLD_SOURCE_SUBUNIT_0_1_LEN = 13758; // 1 -const static uint64_t SH_FLD_SOUTH_CTL_DISABLE_WC_ECC = 13759; // 1 -const static uint64_t SH_FLD_SOUTH_CTL_DISABLE_WC_SCRUB = 13760; // 1 -const static uint64_t SH_FLD_SOUTH_CTL_EG_SINGLE_THREAD = 13761; // 1 -const static uint64_t SH_FLD_SOUTH_CTL_EG_STAMP_DEBUG = 13762; // 1 -const static uint64_t SH_FLD_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE = 13763; // 1 -const static uint64_t SH_FLD_SPAM_EN = 13764; // 8 -const static uint64_t SH_FLD_SPARE = 13765; // 86 -const static uint64_t SH_FLD_SPARE0 = 13766; // 105 -const static uint64_t SH_FLD_SPARE0_LEN = 13767; // 8 -const static uint64_t SH_FLD_SPARE1 = 13768; // 5 -const static uint64_t SH_FLD_SPARE10 = 13769; // 1 -const static uint64_t SH_FLD_SPARE11 = 13770; // 13 -const static uint64_t SH_FLD_SPARE13 = 13771; // 1 -const static uint64_t SH_FLD_SPARE14 = 13772; // 1 -const static uint64_t SH_FLD_SPARE15 = 13773; // 1 -const static uint64_t SH_FLD_SPARE1_ERR = 13774; // 12 -const static uint64_t SH_FLD_SPARE1_ERR_LEN = 13775; // 12 -const static uint64_t SH_FLD_SPARE2 = 13776; // 4 -const static uint64_t SH_FLD_SPARE2_ERR = 13777; // 12 -const static uint64_t SH_FLD_SPARE2_ERR_LEN = 13778; // 12 -const static uint64_t SH_FLD_SPARE3 = 13779; // 1 -const static uint64_t SH_FLD_SPARE4_TIMEOUT = 13780; // 6 -const static uint64_t SH_FLD_SPARE4_TIMEOUT_LEN = 13781; // 6 -const static uint64_t SH_FLD_SPARE7 = 13782; // 1 -const static uint64_t SH_FLD_SPARE8 = 13783; // 1 -const static uint64_t SH_FLD_SPARE9 = 13784; // 1 -const static uint64_t SH_FLD_SPARES = 13785; // 4 -const static uint64_t SH_FLD_SPARES_LEN = 13786; // 4 -const static uint64_t SH_FLD_SPARE_0 = 13787; // 4 -const static uint64_t SH_FLD_SPARE_0_LEN = 13788; // 4 -const static uint64_t SH_FLD_SPARE_1_3 = 13789; // 1 -const static uint64_t SH_FLD_SPARE_1_3_LEN = 13790; // 1 -const static uint64_t SH_FLD_SPARE_2 = 13791; // 4 -const static uint64_t SH_FLD_SPARE_21_23 = 13792; // 12 -const static uint64_t SH_FLD_SPARE_21_23_LEN = 13793; // 12 -const static uint64_t SH_FLD_SPARE_24_31 = 13794; // 1 -const static uint64_t SH_FLD_SPARE_24_31_LEN = 13795; // 1 -const static uint64_t SH_FLD_SPARE_25_27 = 13796; // 12 -const static uint64_t SH_FLD_SPARE_25_27_LEN = 13797; // 12 -const static uint64_t SH_FLD_SPARE_27_28 = 13798; // 12 -const static uint64_t SH_FLD_SPARE_27_28_LEN = 13799; // 12 -const static uint64_t SH_FLD_SPARE_3 = 13800; // 4 -const static uint64_t SH_FLD_SPARE_31 = 13801; // 1 -const static uint64_t SH_FLD_SPARE_32_33 = 13802; // 12 -const static uint64_t SH_FLD_SPARE_32_33_LEN = 13803; // 12 -const static uint64_t SH_FLD_SPARE_38_39 = 13804; // 12 -const static uint64_t SH_FLD_SPARE_38_39_LEN = 13805; // 12 -const static uint64_t SH_FLD_SPARE_4 = 13806; // 2 -const static uint64_t SH_FLD_SPARE_58 = 13807; // 4 -const static uint64_t SH_FLD_SPARE_59 = 13808; // 4 -const static uint64_t SH_FLD_SPARE_60 = 13809; // 4 -const static uint64_t SH_FLD_SPARE_61 = 13810; // 4 -const static uint64_t SH_FLD_SPARE_63 = 13811; // 3 -const static uint64_t SH_FLD_SPARE_6_7 = 13812; // 33 -const static uint64_t SH_FLD_SPARE_6_7_LEN = 13813; // 33 -const static uint64_t SH_FLD_SPARE_9 = 13814; // 12 -const static uint64_t SH_FLD_SPARE_DI_CONTROL = 13815; // 1 -const static uint64_t SH_FLD_SPARE_FENCE_CONTROL = 13816; // 1 -const static uint64_t SH_FLD_SPARE_LEN = 13817; // 69 -const static uint64_t SH_FLD_SPARE_MODE_0 = 13818; // 116 -const static uint64_t SH_FLD_SPARE_MODE_1 = 13819; // 116 -const static uint64_t SH_FLD_SPARE_MODE_2 = 13820; // 116 -const static uint64_t SH_FLD_SPARE_MODE_3 = 13821; // 116 -const static uint64_t SH_FLD_SPARE_N = 13822; // 2 -const static uint64_t SH_FLD_SPARE_N_LEN = 13823; // 2 -const static uint64_t SH_FLD_SPARE_PIB_CONTROL = 13824; // 1 -const static uint64_t SH_FLD_SPARE_RI_CONTROL = 13825; // 1 -const static uint64_t SH_FLD_SPARE_TANK_PLL_CONTROL = 13826; // 1 -const static uint64_t SH_FLD_SPECIAL_ATTENTION = 13827; // 1 -const static uint64_t SH_FLD_SPECIAL_WAKEUP_C0 = 13828; // 24 -const static uint64_t SH_FLD_SPECIAL_WAKEUP_C1 = 13829; // 24 -const static uint64_t SH_FLD_SPECIAL_WKUP_ACTIVE_FSP = 13830; // 30 -const static uint64_t SH_FLD_SPECIAL_WKUP_ACTIVE_HYP = 13831; // 30 -const static uint64_t SH_FLD_SPECIAL_WKUP_ACTIVE_OCC = 13832; // 30 -const static uint64_t SH_FLD_SPECIAL_WKUP_ACTIVE_OTR = 13833; // 30 -const static uint64_t SH_FLD_SPECIAL_WKUP_DONE = 13834; // 30 -const static uint64_t SH_FLD_SPECIAL_WKUP_PROTOCOL = 13835; // 30 -const static uint64_t SH_FLD_SPECIFIC_GAP_CONDITION = 13836; // 8 -const static uint64_t SH_FLD_SPECIFIC_GAP_CONDITION_LEN = 13837; // 8 -const static uint64_t SH_FLD_SPECIFIC_GAP_COUNT = 13838; // 8 -const static uint64_t SH_FLD_SPECIFIC_GAP_COUNT_LEN = 13839; // 8 -const static uint64_t SH_FLD_SPECULATIVE_CHECKIN_COUNT = 13840; // 1 -const static uint64_t SH_FLD_SPECULATIVE_CHECKIN_COUNT_LEN = 13841; // 1 -const static uint64_t SH_FLD_SPEC_CILD_G = 13842; // 1 -const static uint64_t SH_FLD_SPEC_HPC_DIR_STATE = 13843; // 2 -const static uint64_t SH_FLD_SPEC_HPC_DIR_STATE_LEN = 13844; // 2 -const static uint64_t SH_FLD_SPEC_READ_FILTER_NO_HASH_MODE = 13845; // 4 -const static uint64_t SH_FLD_SPEDIV = 13846; // 20 -const static uint64_t SH_FLD_SPEDIV_LEN = 13847; // 20 -const static uint64_t SH_FLD_SPIPSS_ERROR = 13848; // 1 -const static uint64_t SH_FLD_SPLURGE = 13849; // 1 -const static uint64_t SH_FLD_SPRC0_SEL = 13850; // 24 -const static uint64_t SH_FLD_SPRC1_SEL = 13851; // 24 -const static uint64_t SH_FLD_SPRC2_SEL = 13852; // 24 -const static uint64_t SH_FLD_SPRC3_SEL = 13853; // 24 -const static uint64_t SH_FLD_SPRC_T0_SEL = 13854; // 24 -const static uint64_t SH_FLD_SPRC_T1_SEL = 13855; // 24 -const static uint64_t SH_FLD_SPRC_T2_SEL = 13856; // 24 -const static uint64_t SH_FLD_SPRC_T3_SEL = 13857; // 24 -const static uint64_t SH_FLD_SPRC_WR_EN = 13858; // 24 -const static uint64_t SH_FLD_SPRG0 = 13859; // 21 -const static uint64_t SH_FLD_SPRG0_LEN = 13860; // 21 -const static uint64_t SH_FLD_SPR_LNS_PDWN_LITE_GCRMSG = 13861; // 4 -const static uint64_t SH_FLD_SR = 13862; // 8 -const static uint64_t SH_FLD_SRAM_ABIST_DONE_DC = 13863; // 43 -const static uint64_t SH_FLD_SRAM_ACCESS_MODE = 13864; // 15 -const static uint64_t SH_FLD_SRAM_ADDRESS = 13865; // 15 -const static uint64_t SH_FLD_SRAM_ADDRESS_LEN = 13866; // 15 -const static uint64_t SH_FLD_SRAM_CE = 13867; // 12 -const static uint64_t SH_FLD_SRAM_DATA = 13868; // 15 -const static uint64_t SH_FLD_SRAM_DATA_LEN = 13869; // 15 -const static uint64_t SH_FLD_SRAM_HIGH_PRIORITY = 13870; // 4 -const static uint64_t SH_FLD_SRAM_HIGH_PRIORITY_LEN = 13871; // 4 -const static uint64_t SH_FLD_SRAM_LOW_PRIORITY = 13872; // 4 -const static uint64_t SH_FLD_SRAM_LOW_PRIORITY_LEN = 13873; // 4 -const static uint64_t SH_FLD_SRAM_SCRUB_ENABLE = 13874; // 15 -const static uint64_t SH_FLD_SRAM_SCRUB_ERR = 13875; // 12 -const static uint64_t SH_FLD_SRAM_SCRUB_INDEX = 13876; // 15 -const static uint64_t SH_FLD_SRAM_SCRUB_INDEX_LEN = 13877; // 15 -const static uint64_t SH_FLD_SRAM_UE = 13878; // 12 -const static uint64_t SH_FLD_SRC_DDE = 13879; // 3 -const static uint64_t SH_FLD_SRC_DDE_LEN = 13880; // 3 -const static uint64_t SH_FLD_SRC_SEL_EQ1_ERR = 13881; // 1 -const static uint64_t SH_FLD_SRQ_MCBIST_OUT_OF_SYNC_HOLD_OUT = 13882; // 2 -const static uint64_t SH_FLD_SRT_ERROR = 13883; // 1 -const static uint64_t SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL = 13884; // 4 -const static uint64_t SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL_LEN = 13885; // 4 -const static uint64_t SH_FLD_SR_LEN = 13886; // 8 -const static uint64_t SH_FLD_SSCGEN = 13887; // 3 -const static uint64_t SH_FLD_SS_ENABLE = 13888; // 6 -const static uint64_t SH_FLD_ST2_RESET_PERIOD = 13889; // 1 -const static uint64_t SH_FLD_ST2_RESET_PERIOD_LEN = 13890; // 1 -const static uint64_t SH_FLD_STACK = 13891; // 16 -const static uint64_t SH_FLD_STACK_LEN = 13892; // 16 -const static uint64_t SH_FLD_STACK_SCOM_ERR0 = 13893; // 9 -const static uint64_t SH_FLD_STACK_SCOM_ERR0_MASK = 13894; // 9 -const static uint64_t SH_FLD_STACK_SCOM_ERR1 = 13895; // 9 -const static uint64_t SH_FLD_STACK_SCOM_ERR1_MASK = 13896; // 9 -const static uint64_t SH_FLD_STAGGERED_PATTERN = 13897; // 8 -const static uint64_t SH_FLD_START = 13898; // 23 -const static uint64_t SH_FLD_START0 = 13899; // 5 -const static uint64_t SH_FLD_START1 = 13900; // 5 -const static uint64_t SH_FLD_STARTING_ADDRESS = 13901; // 4 -const static uint64_t SH_FLD_STARTING_ADDRESS_LEN = 13902; // 4 -const static uint64_t SH_FLD_STARTS_BIST = 13903; // 43 -const static uint64_t SH_FLD_START_BOOT_SEQUENCER = 13904; // 1 -const static uint64_t SH_FLD_START_DESKEW = 13905; // 4 -const static uint64_t SH_FLD_START_EYE_OPT = 13906; // 4 -const static uint64_t SH_FLD_START_FUNC_MODE = 13907; // 4 -const static uint64_t SH_FLD_START_INIT = 13908; // 8 -const static uint64_t SH_FLD_START_JTAG_CMD = 13909; // 1 -const static uint64_t SH_FLD_START_LANE_ID = 13910; // 8 -const static uint64_t SH_FLD_START_LANE_ID_LEN = 13911; // 8 -const static uint64_t SH_FLD_START_PPE_ADDR = 13912; // 4 -const static uint64_t SH_FLD_START_PPE_ADDR_LEN = 13913; // 4 -const static uint64_t SH_FLD_START_READ = 13914; // 1 -const static uint64_t SH_FLD_START_REPAIR = 13915; // 4 -const static uint64_t SH_FLD_START_RESTART_VECTOR0 = 13916; // 1 -const static uint64_t SH_FLD_START_RESTART_VECTOR1 = 13917; // 1 -const static uint64_t SH_FLD_START_SEEPROM_ADDRESS = 13918; // 4 -const static uint64_t SH_FLD_START_SEEPROM_ADDRESS_LEN = 13919; // 4 -const static uint64_t SH_FLD_START_WIRETEST = 13920; // 4 -const static uint64_t SH_FLD_START_WRITE = 13921; // 1 -const static uint64_t SH_FLD_START_WR_ADDR = 13922; // 2 -const static uint64_t SH_FLD_START_WR_ADDR_LEN = 13923; // 2 -const static uint64_t SH_FLD_STAT = 13924; // 2 -const static uint64_t SH_FLD_STATE = 13925; // 44 -const static uint64_t SH_FLD_STATE_LEN = 13926; // 43 -const static uint64_t SH_FLD_STATE_LOSS_ENABLE_A_N = 13927; // 96 -const static uint64_t SH_FLD_STATE_MACHINE_TRANSITION_DELAY = 13928; // 1 -const static uint64_t SH_FLD_STATE_MACHINE_TRANSITION_DELAY_LEN = 13929; // 1 -const static uint64_t SH_FLD_STATIC_MAX_SPARES_EXCEEDED = 13930; // 8 -const static uint64_t SH_FLD_STATIC_SPARE_DEPLOYED = 13931; // 8 -const static uint64_t SH_FLD_STATUS = 13932; // 3 -const static uint64_t SH_FLD_STATUS_INVALID_CRESP = 13933; // 2 -const static uint64_t SH_FLD_STATUS_PARITY_ERROR = 13934; // 2 -const static uint64_t SH_FLD_STATUS_PERV = 13935; // 129 -const static uint64_t SH_FLD_STATUS_REC_DROPPED_Q = 13936; // 26 -const static uint64_t SH_FLD_STATUS_REG = 13937; // 1 -const static uint64_t SH_FLD_STATUS_REG_LEN = 13938; // 1 -const static uint64_t SH_FLD_STATUS_SCOM_ERROR = 13939; // 26 -const static uint64_t SH_FLD_STATUS_TRIG_DROPPED_Q = 13940; // 26 -const static uint64_t SH_FLD_STATUS_UNIT1 = 13941; // 129 -const static uint64_t SH_FLD_STATUS_UNIT10 = 13942; // 129 -const static uint64_t SH_FLD_STATUS_UNIT2 = 13943; // 129 -const static uint64_t SH_FLD_STATUS_UNIT3 = 13944; // 129 -const static uint64_t SH_FLD_STATUS_UNIT4 = 13945; // 129 -const static uint64_t SH_FLD_STATUS_UNIT5 = 13946; // 129 -const static uint64_t SH_FLD_STATUS_UNIT6 = 13947; // 129 -const static uint64_t SH_FLD_STATUS_UNIT7 = 13948; // 129 -const static uint64_t SH_FLD_STATUS_UNIT8 = 13949; // 129 -const static uint64_t SH_FLD_STATUS_UNIT9 = 13950; // 129 -const static uint64_t SH_FLD_STATUS_UNUSED = 13951; // 24 -const static uint64_t SH_FLD_STATUS_UNUSED_LEN = 13952; // 24 -const static uint64_t SH_FLD_STAT_LEN = 13953; // 2 -const static uint64_t SH_FLD_STEP_CHECK_CONSTANT_CPS_ENABLE = 13954; // 1 -const static uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION = 13955; // 1 -const static uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR = 13956; // 3 -const static uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN = 13957; // 3 -const static uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_LEN = 13958; // 1 -const static uint64_t SH_FLD_STEP_CHECK_ENABLE_CHICKEN_SWITCH = 13959; // 1 -const static uint64_t SH_FLD_STEP_CHECK_STEP_SELECT = 13960; // 1 -const static uint64_t SH_FLD_STEP_CHECK_VALIDITY_COUNT = 13961; // 1 -const static uint64_t SH_FLD_STEP_CHECK_VALIDITY_COUNT_LEN = 13962; // 1 -const static uint64_t SH_FLD_STEP_CREATE_DUAL_EDGE_DISABLE = 13963; // 1 -const static uint64_t SH_FLD_STICKY_CACHE_VDM_DATA = 13964; // 12 -const static uint64_t SH_FLD_STICKY_CACHE_VDM_DATA_LEN = 13965; // 12 -const static uint64_t SH_FLD_STICKY_CORE0_VDM_DATA = 13966; // 12 -const static uint64_t SH_FLD_STICKY_CORE0_VDM_DATA_LEN = 13967; // 12 -const static uint64_t SH_FLD_STICKY_CORE1_VDM_DATA = 13968; // 12 -const static uint64_t SH_FLD_STICKY_CORE1_VDM_DATA_LEN = 13969; // 12 -const static uint64_t SH_FLD_STICKY_CORE2_VDM_DATA = 13970; // 12 -const static uint64_t SH_FLD_STICKY_CORE2_VDM_DATA_LEN = 13971; // 12 -const static uint64_t SH_FLD_STICKY_CORE3_VDM_DATA = 13972; // 12 -const static uint64_t SH_FLD_STICKY_CORE3_VDM_DATA_LEN = 13973; // 12 -const static uint64_t SH_FLD_STICKY_ERROR_INJECT_ENABLE = 13974; // 1 -const static uint64_t SH_FLD_STICKY_VDM_CONTROL_SUMMARY = 13975; // 12 -const static uint64_t SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN = 13976; // 12 -const static uint64_t SH_FLD_STOP = 13977; // 6 -const static uint64_t SH_FLD_STOP1_ACTIVE_ENABLE = 13978; // 12 -const static uint64_t SH_FLD_STOPPED = 13979; // 2 -const static uint64_t SH_FLD_STOP_ACTIVE_MASK = 13980; // 12 -const static uint64_t SH_FLD_STOP_ERROR_0 = 13981; // 2 -const static uint64_t SH_FLD_STOP_ERROR_1 = 13982; // 2 -const static uint64_t SH_FLD_STOP_ERROR_2 = 13983; // 2 -const static uint64_t SH_FLD_STOP_ERROR_3 = 13984; // 2 -const static uint64_t SH_FLD_STOP_GATED = 13985; // 30 -const static uint64_t SH_FLD_STOP_GATED_FSP = 13986; // 30 -const static uint64_t SH_FLD_STOP_ON_ERR = 13987; // 2 -const static uint64_t SH_FLD_STOP_OVERRIDE_MODE = 13988; // 12 -const static uint64_t SH_FLD_STOP_REQUEST_LEVEL_A_N = 13989; // 96 -const static uint64_t SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN = 13990; // 96 -const static uint64_t SH_FLD_STOP_RUNN_ON_XSTOP = 13991; // 43 -const static uint64_t SH_FLD_STOP_TRANSITION = 13992; // 30 -const static uint64_t SH_FLD_STOP_TRANSITION_FSP = 13993; // 30 -const static uint64_t SH_FLD_STOP_TRANSITION_FSP_LEN = 13994; // 30 -const static uint64_t SH_FLD_STOP_TRANSITION_HYP = 13995; // 30 -const static uint64_t SH_FLD_STOP_TRANSITION_HYP_LEN = 13996; // 30 -const static uint64_t SH_FLD_STOP_TRANSITION_LEN = 13997; // 30 -const static uint64_t SH_FLD_STOP_TRANSITION_OCC = 13998; // 30 -const static uint64_t SH_FLD_STOP_TRANSITION_OCC_LEN = 13999; // 30 -const static uint64_t SH_FLD_STOP_TRANSITION_OTR = 14000; // 30 -const static uint64_t SH_FLD_STOP_TRANSITION_OTR_LEN = 14001; // 30 -const static uint64_t SH_FLD_STORE_ADDRESS = 14002; // 21 -const static uint64_t SH_FLD_STORE_ADDRESS_LEN = 14003; // 21 -const static uint64_t SH_FLD_STORE_TIMEOUT = 14004; // 24 -const static uint64_t SH_FLD_STQ_DATA_PARITY_ERR = 14005; // 24 -const static uint64_t SH_FLD_STQ_ERR = 14006; // 12 -const static uint64_t SH_FLD_STQ_ERR_LEN = 14007; // 12 -const static uint64_t SH_FLD_STQ_HW_MAX_0_4 = 14008; // 1 -const static uint64_t SH_FLD_STQ_HW_MAX_0_4_LEN = 14009; // 1 -const static uint64_t SH_FLD_STQ_HW_MIN_0_4 = 14010; // 1 -const static uint64_t SH_FLD_STQ_HW_MIN_0_4_LEN = 14011; // 1 -const static uint64_t SH_FLD_STQ_HYP_MAX_0_4 = 14012; // 1 -const static uint64_t SH_FLD_STQ_HYP_MAX_0_4_LEN = 14013; // 1 -const static uint64_t SH_FLD_STQ_HYP_MIN_0_4 = 14014; // 1 -const static uint64_t SH_FLD_STQ_HYP_MIN_0_4_LEN = 14015; // 1 -const static uint64_t SH_FLD_STQ_INVALID_ST = 14016; // 1 -const static uint64_t SH_FLD_STQ_IPI_MAX_0_4 = 14017; // 1 -const static uint64_t SH_FLD_STQ_IPI_MAX_0_4_LEN = 14018; // 1 -const static uint64_t SH_FLD_STQ_IPI_MIN_0_4 = 14019; // 1 -const static uint64_t SH_FLD_STQ_IPI_MIN_0_4_LEN = 14020; // 1 -const static uint64_t SH_FLD_STQ_OS_MAX_0_4 = 14021; // 1 -const static uint64_t SH_FLD_STQ_OS_MAX_0_4_LEN = 14022; // 1 -const static uint64_t SH_FLD_STQ_OS_MIN_0_4 = 14023; // 1 -const static uint64_t SH_FLD_STQ_OS_MIN_0_4_LEN = 14024; // 1 -const static uint64_t SH_FLD_STQ_RDI_MAX_0_4 = 14025; // 1 -const static uint64_t SH_FLD_STQ_RDI_MAX_0_4_LEN = 14026; // 1 -const static uint64_t SH_FLD_STQ_RDI_MIN_0_4 = 14027; // 1 -const static uint64_t SH_FLD_STQ_RDI_MIN_0_4_LEN = 14028; // 1 -const static uint64_t SH_FLD_STQ_REG_MAX_0_4 = 14029; // 1 -const static uint64_t SH_FLD_STQ_REG_MAX_0_4_LEN = 14030; // 1 -const static uint64_t SH_FLD_STQ_REG_MIN_0_4 = 14031; // 1 -const static uint64_t SH_FLD_STQ_REG_MIN_0_4_LEN = 14032; // 1 -const static uint64_t SH_FLD_STQ_THR_MAX_0_4 = 14033; // 1 -const static uint64_t SH_FLD_STQ_THR_MAX_0_4_LEN = 14034; // 1 -const static uint64_t SH_FLD_STQ_THR_MIN_0_4 = 14035; // 1 -const static uint64_t SH_FLD_STQ_THR_MIN_0_4_LEN = 14036; // 1 -const static uint64_t SH_FLD_STQ_TYPE = 14037; // 12 -const static uint64_t SH_FLD_STQ_TYPE_LEN = 14038; // 12 -const static uint64_t SH_FLD_STQ_VPC_MAX_0_4 = 14039; // 1 -const static uint64_t SH_FLD_STQ_VPC_MAX_0_4_LEN = 14040; // 1 -const static uint64_t SH_FLD_STQ_VPC_MIN_0_4 = 14041; // 1 -const static uint64_t SH_FLD_STQ_VPC_MIN_0_4_LEN = 14042; // 1 -const static uint64_t SH_FLD_STREAM_MODE = 14043; // 4 -const static uint64_t SH_FLD_STREAM_TYPE = 14044; // 4 -const static uint64_t SH_FLD_STRICT_IPI_RULES = 14045; // 1 -const static uint64_t SH_FLD_STRICT_ORDER = 14046; // 1 -const static uint64_t SH_FLD_ST_ACK_DEAD = 14047; // 12 -const static uint64_t SH_FLD_ST_ADDR_ERR = 14048; // 24 -const static uint64_t SH_FLD_ST_CLASS_CMD_ADDR_ERR = 14049; // 4 -const static uint64_t SH_FLD_ST_CLASS_CMD_FOREIGN_LINK_FAIL = 14050; // 4 -const static uint64_t SH_FLD_ST_FOREIGN0_ACK_DEAD = 14051; // 12 -const static uint64_t SH_FLD_ST_FOREIGN1_ACK_DEAD = 14052; // 12 -const static uint64_t SH_FLD_SUE_0 = 14053; // 8 -const static uint64_t SH_FLD_SUE_1 = 14054; // 8 -const static uint64_t SH_FLD_SUE_DIS_BR = 14055; // 3 -const static uint64_t SH_FLD_SUE_DIS_BR_PERR = 14056; // 3 -const static uint64_t SH_FLD_SUE_DIS_IR = 14057; // 3 -const static uint64_t SH_FLD_SUE_DIS_IR_PERR = 14058; // 3 -const static uint64_t SH_FLD_SUE_DIS_OR = 14059; // 3 -const static uint64_t SH_FLD_SUE_DIS_OR_PERR = 14060; // 3 -const static uint64_t SH_FLD_SUE_DIS_PR = 14061; // 3 -const static uint64_t SH_FLD_SUE_DIS_PT = 14062; // 3 -const static uint64_t SH_FLD_SUMMARY = 14063; // 1 -const static uint64_t SH_FLD_SUOP_ERROR_1 = 14064; // 4 -const static uint64_t SH_FLD_SUOP_ERROR_2 = 14065; // 4 -const static uint64_t SH_FLD_SUOP_ERROR_3 = 14066; // 4 -const static uint64_t SH_FLD_SUPPRESS = 14067; // 301 -const static uint64_t SH_FLD_SUPPRESS_EVEN_CLK = 14068; // 43 -const static uint64_t SH_FLD_SWC_VALUE = 14069; // 1 -const static uint64_t SH_FLD_SWC_VALUE_LEN = 14070; // 1 -const static uint64_t SH_FLD_SWITCH_SYNC_ERROR_DISABLE = 14071; // 1 -const static uint64_t SH_FLD_SYM_CPB_CHECK_DISABLE = 14072; // 1 -const static uint64_t SH_FLD_SYM_MAX_INRD = 14073; // 1 -const static uint64_t SH_FLD_SYM_MAX_INRD_LEN = 14074; // 1 -const static uint64_t SH_FLD_SYNCEN = 14075; // 7 -const static uint64_t SH_FLD_SYNC_BRK = 14076; // 1 -const static uint64_t SH_FLD_SYNC_BRK_LEN = 14077; // 1 -const static uint64_t SH_FLD_SYNC_CREATE_SPS_SELECT = 14078; // 1 -const static uint64_t SH_FLD_SYNC_CREATE_SPS_SELECT_LEN = 14079; // 1 -const static uint64_t SH_FLD_SYNC_DONE = 14080; // 1 -const static uint64_t SH_FLD_SYNC_DONE_LEN = 14081; // 1 -const static uint64_t SH_FLD_SYNC_FENCE = 14082; // 4 -const static uint64_t SH_FLD_SYNC_GO_CH0 = 14083; // 4 -const static uint64_t SH_FLD_SYNC_GO_CH1 = 14084; // 4 -const static uint64_t SH_FLD_SYNC_MODE = 14085; // 4 -const static uint64_t SH_FLD_SYNC_REPLAY_COUNT = 14086; // 4 -const static uint64_t SH_FLD_SYNC_REPLAY_COUNT_LEN = 14087; // 4 -const static uint64_t SH_FLD_SYNC_RESERVED = 14088; // 4 -const static uint64_t SH_FLD_SYNC_RESERVED_LEN = 14089; // 4 -const static uint64_t SH_FLD_SYNC_RESET = 14090; // 1 -const static uint64_t SH_FLD_SYNC_TIMER_SEL = 14091; // 17 -const static uint64_t SH_FLD_SYNC_TIMER_SEL_LEN = 14092; // 17 -const static uint64_t SH_FLD_SYNC_TYPE = 14093; // 4 -const static uint64_t SH_FLD_SYNC_TYPE_LEN = 14094; // 4 -const static uint64_t SH_FLD_SYNC_WAIT = 14095; // 1 -const static uint64_t SH_FLD_SYNC_WAIT_LEN = 14096; // 1 -const static uint64_t SH_FLD_SYN_HI_0_7 = 14097; // 1 -const static uint64_t SH_FLD_SYN_HI_0_7_LEN = 14098; // 1 -const static uint64_t SH_FLD_SYN_LO_0_7 = 14099; // 1 -const static uint64_t SH_FLD_SYN_LO_0_7_LEN = 14100; // 1 -const static uint64_t SH_FLD_SYSCLK_2X_MEMINTCLKO = 14101; // 8 -const static uint64_t SH_FLD_SYSCLK_CLK_GATE = 14102; // 8 -const static uint64_t SH_FLD_SYSCLK_RESET = 14103; // 8 -const static uint64_t SH_FLD_SYSMAP_SM_NOT_LG_SEL = 14104; // 12 -const static uint64_t SH_FLD_SYSTEM = 14105; // 2 -const static uint64_t SH_FLD_SYSTEM_CHECKSTOP = 14106; // 1 -const static uint64_t SH_FLD_SYSTEM_FAST_INIT = 14107; // 43 -const static uint64_t SH_FLD_SYSTEM_LEN = 14108; // 2 -const static uint64_t SH_FLD_SYSTEM_RESET = 14109; // 1 -const static uint64_t SH_FLD_S_PATH_0_PARITY = 14110; // 4 -const static uint64_t SH_FLD_S_PATH_0_STEP_CHECK = 14111; // 4 -const static uint64_t SH_FLD_S_PATH_0_STEP_CHECK_VALID = 14112; // 1 -const static uint64_t SH_FLD_S_PATH_1_PARITY = 14113; // 4 -const static uint64_t SH_FLD_S_PATH_1_STEP_CHECK = 14114; // 4 -const static uint64_t SH_FLD_S_PATH_1_STEP_CHECK_VALID = 14115; // 1 -const static uint64_t SH_FLD_S_PATH_SELECT = 14116; // 1 -const static uint64_t SH_FLD_T0_RUN_Q = 14117; // 24 -const static uint64_t SH_FLD_T1_RUN_Q = 14118; // 24 -const static uint64_t SH_FLD_T2_RUN_Q = 14119; // 24 -const static uint64_t SH_FLD_T3_RUN_Q = 14120; // 24 -const static uint64_t SH_FLD_T4_RUN_Q = 14121; // 24 -const static uint64_t SH_FLD_T5_RUN_Q = 14122; // 24 -const static uint64_t SH_FLD_T6_RUN_Q = 14123; // 24 -const static uint64_t SH_FLD_T7_RUN_Q = 14124; // 24 -const static uint64_t SH_FLD_TABLE_ADDRESS = 14125; // 1 -const static uint64_t SH_FLD_TABLE_ADDRESS_LEN = 14126; // 1 -const static uint64_t SH_FLD_TABLE_DATA = 14127; // 1 -const static uint64_t SH_FLD_TABLE_DATA_LEN = 14128; // 1 -const static uint64_t SH_FLD_TABLE_SELECT = 14129; // 1 -const static uint64_t SH_FLD_TABLE_SELECT_LEN = 14130; // 1 -const static uint64_t SH_FLD_TABLE_SEL_0_3 = 14131; // 1 -const static uint64_t SH_FLD_TABLE_SEL_0_3_LEN = 14132; // 1 -const static uint64_t SH_FLD_TAG_ECC = 14133; // 12 -const static uint64_t SH_FLD_TAG_ECC_LEN = 14134; // 12 -const static uint64_t SH_FLD_TARGET_DDE = 14135; // 3 -const static uint64_t SH_FLD_TARGET_DDE_LEN = 14136; // 3 -const static uint64_t SH_FLD_TARGET_ID0 = 14137; // 2 -const static uint64_t SH_FLD_TARGET_MIN = 14138; // 2 -const static uint64_t SH_FLD_TARGET_MIN_LEN = 14139; // 2 -const static uint64_t SH_FLD_TARGET_VALID = 14140; // 2 -const static uint64_t SH_FLD_TARGET_VALID_LEN = 14141; // 2 -const static uint64_t SH_FLD_TCBR_TP_PSI_GLB_ERR_0 = 14142; // 4 -const static uint64_t SH_FLD_TCBR_TP_PSI_GLB_ERR_1 = 14143; // 4 -const static uint64_t SH_FLD_TCD_PERR_ESR = 14144; // 1 -const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_EQ = 14145; // 6 -const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_EQ_LEN = 14146; // 6 -const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_DN = 14147; // 6 -const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_DN_LEN = 14148; // 6 -const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_UP = 14149; // 6 -const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_UP_LEN = 14150; // 6 -const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_DN = 14151; // 6 -const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_DN_LEN = 14152; // 6 -const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_UP = 14153; // 6 -const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_UP_LEN = 14154; // 6 -const static uint64_t SH_FLD_TCE_CACHE_1W = 14155; // 1 -const static uint64_t SH_FLD_TCE_CACHE_DISABLE = 14156; // 1 -const static uint64_t SH_FLD_TCE_CACHE_MULT_HIT_ERR_ESR = 14157; // 1 -const static uint64_t SH_FLD_TCE_PAGE_ACCESS_ERR_ESR = 14158; // 1 -const static uint64_t SH_FLD_TCE_REQ_TO_ERR_ESR = 14159; // 1 -const static uint64_t SH_FLD_TCE_RESPONSE = 14160; // 1 -const static uint64_t SH_FLD_TCE_TIMEOUT = 14161; // 1 -const static uint64_t SH_FLD_TCE_TIMEOUT_LEN = 14162; // 1 -const static uint64_t SH_FLD_TCK_WIDTH = 14163; // 1 -const static uint64_t SH_FLD_TCK_WIDTH_LEN = 14164; // 1 -const static uint64_t SH_FLD_TCPERV_AMUX_VSELECT_CHIP = 14165; // 1 -const static uint64_t SH_FLD_TCPERV_AMUX_VSELECT_CHIP_LEN = 14166; // 1 -const static uint64_t SH_FLD_TC_BSC_EXTMODE_DC = 14167; // 43 -const static uint64_t SH_FLD_TC_BSC_INTMODE_DC = 14168; // 43 -const static uint64_t SH_FLD_TC_BSC_INV_DC = 14169; // 43 -const static uint64_t SH_FLD_TC_BSC_WRAPSEL_DC = 14170; // 43 -const static uint64_t SH_FLD_TC_DIAG_PORT0_OUT = 14171; // 43 -const static uint64_t SH_FLD_TC_DIAG_PORT1_OUT = 14172; // 43 -const static uint64_t SH_FLD_TC_EDRAM_ABIST_MODE_DC = 14173; // 43 -const static uint64_t SH_FLD_TC_IOBIST_MODE_DC = 14174; // 43 -const static uint64_t SH_FLD_TC_IOM_DPHY01_PLL_RESET_N = 14175; // 2 -const static uint64_t SH_FLD_TC_IOM_DPHY23_PLL_RESET_N = 14176; // 2 -const static uint64_t SH_FLD_TC_IOP_HSSPCLKOUTEN = 14177; // 3 -const static uint64_t SH_FLD_TC_IOP_HSSPORWREN = 14178; // 3 -const static uint64_t SH_FLD_TC_IOP_SYS_RESET_PCS = 14179; // 3 -const static uint64_t SH_FLD_TC_IOP_SYS_RESET_PMA = 14180; // 3 -const static uint64_t SH_FLD_TC_LP_RESET = 14181; // 1 -const static uint64_t SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC = 14182; // 43 -const static uint64_t SH_FLD_TC_NBTI_PROBE_GATE_DC = 14183; // 43 -const static uint64_t SH_FLD_TC_OB_RATIO_DC = 14184; // 2 -const static uint64_t SH_FLD_TC_OB_RATIO_DC_LEN = 14185; // 2 -const static uint64_t SH_FLD_TC_OELCC_ALIGN_FLUSH_DC = 14186; // 43 -const static uint64_t SH_FLD_TC_OELCC_EDGE_DELAYED_DC = 14187; // 43 -const static uint64_t SH_FLD_TC_PBE0_IOVALID_DC = 14188; // 1 -const static uint64_t SH_FLD_TC_PBE1_IOVALID_DC = 14189; // 1 -const static uint64_t SH_FLD_TC_PBE2_IOVALID_DC = 14190; // 1 -const static uint64_t SH_FLD_TC_PBE3_IOVALID_DC = 14191; // 1 -const static uint64_t SH_FLD_TC_PBE4_IOVALID_DC = 14192; // 1 -const static uint64_t SH_FLD_TC_PBE5_IOVALID_DC = 14193; // 1 -const static uint64_t SH_FLD_TC_PBIOO0_IOVALID = 14194; // 2 -const static uint64_t SH_FLD_TC_PBIOO1_IOVALID = 14195; // 2 -const static uint64_t SH_FLD_TC_PCI0_IOVALID = 14196; // 1 -const static uint64_t SH_FLD_TC_PCI0_LANE_CFG_DC = 14197; // 1 -const static uint64_t SH_FLD_TC_PCI0_LANE_CFG_DC_LEN = 14198; // 1 -const static uint64_t SH_FLD_TC_PCI0_RATIO_DC = 14199; // 1 -const static uint64_t SH_FLD_TC_PCI0_RATIO_DC_LEN = 14200; // 1 -const static uint64_t SH_FLD_TC_PCI0_RATIO_OVERRIDE = 14201; // 1 -const static uint64_t SH_FLD_TC_PCI0_SWAP_DC = 14202; // 1 -const static uint64_t SH_FLD_TC_PCI1X_IOVALID = 14203; // 1 -const static uint64_t SH_FLD_TC_PCI1X_IOVALID_LEN = 14204; // 1 -const static uint64_t SH_FLD_TC_PCI1_LANE_CFG_DC = 14205; // 1 -const static uint64_t SH_FLD_TC_PCI1_LANE_CFG_DC_LEN = 14206; // 1 -const static uint64_t SH_FLD_TC_PCI1_PIPE1_RATIO_DC = 14207; // 1 -const static uint64_t SH_FLD_TC_PCI1_PIPE1_RATIO_DC_LEN = 14208; // 1 -const static uint64_t SH_FLD_TC_PCI1_PIPE2_RATIO_DC = 14209; // 1 -const static uint64_t SH_FLD_TC_PCI1_PIPE2_RATIO_DC_LEN = 14210; // 1 -const static uint64_t SH_FLD_TC_PCI1_RATIO_OVERRIDE = 14211; // 1 -const static uint64_t SH_FLD_TC_PCI1_RATIO_OVERRIDE_LEN = 14212; // 1 -const static uint64_t SH_FLD_TC_PCI1_SWAP_DC = 14213; // 1 -const static uint64_t SH_FLD_TC_PCI1_SWAP_DC_LEN = 14214; // 1 -const static uint64_t SH_FLD_TC_PCI2_IOVALID = 14215; // 1 -const static uint64_t SH_FLD_TC_PCI2_IOVALID_LEN = 14216; // 1 -const static uint64_t SH_FLD_TC_PCI2_LANE_CFG_DC = 14217; // 1 -const static uint64_t SH_FLD_TC_PCI2_LANE_CFG_DC_LEN = 14218; // 1 -const static uint64_t SH_FLD_TC_PCI2_PIPE1_RATIO_DC = 14219; // 1 -const static uint64_t SH_FLD_TC_PCI2_PIPE1_RATIO_DC_LEN = 14220; // 1 -const static uint64_t SH_FLD_TC_PCI2_PIPE2_RATIO_DC = 14221; // 1 -const static uint64_t SH_FLD_TC_PCI2_PIPE2_RATIO_DC_LEN = 14222; // 1 -const static uint64_t SH_FLD_TC_PCI2_PIPE3_RATIO_DC = 14223; // 1 -const static uint64_t SH_FLD_TC_PCI2_PIPE3_RATIO_DC_LEN = 14224; // 1 -const static uint64_t SH_FLD_TC_PCI2_RATIO_OVERRIDE = 14225; // 1 -const static uint64_t SH_FLD_TC_PCI2_RATIO_OVERRIDE_LEN = 14226; // 1 -const static uint64_t SH_FLD_TC_PCI2_SWAP_DC = 14227; // 1 -const static uint64_t SH_FLD_TC_PCI2_SWAP_DC_LEN = 14228; // 1 -const static uint64_t SH_FLD_TC_PERV_EXPORT_FREEZE = 14229; // 1 -const static uint64_t SH_FLD_TC_PERV_REGION_FENCE = 14230; // 43 -const static uint64_t SH_FLD_TC_PSI_IOVALID_DC = 14231; // 1 -const static uint64_t SH_FLD_TC_PSRO_SEL_DC = 14232; // 43 -const static uint64_t SH_FLD_TC_PSRO_SEL_DC_LEN = 14233; // 43 -const static uint64_t SH_FLD_TC_REFCLK_DRVR_EN_DC = 14234; // 43 -const static uint64_t SH_FLD_TC_REGION1_FENCE = 14235; // 42 -const static uint64_t SH_FLD_TC_REGION2_FENCE = 14236; // 42 -const static uint64_t SH_FLD_TC_REGION3_FENCE = 14237; // 16 -const static uint64_t SH_FLD_TC_REGION4_FENCE = 14238; // 12 -const static uint64_t SH_FLD_TC_REGION5_FENCE = 14239; // 10 -const static uint64_t SH_FLD_TC_REGION6_FENCE = 14240; // 8 -const static uint64_t SH_FLD_TC_REGION7_FENCE = 14241; // 7 -const static uint64_t SH_FLD_TC_REGION8_FENCE = 14242; // 6 -const static uint64_t SH_FLD_TC_REGION9_FENCE = 14243; // 6 -const static uint64_t SH_FLD_TC_SKIT_MODE_BIST_DC = 14244; // 43 -const static uint64_t SH_FLD_TC_SRAM_ABIST_MODE_DC = 14245; // 43 -const static uint64_t SH_FLD_TC_START_TEST_DC = 14246; // 43 -const static uint64_t SH_FLD_TC_UNIT_ARY_WRT_THRU_DC = 14247; // 43 -const static uint64_t SH_FLD_TC_UNIT_AVP_MODE = 14248; // 43 -const static uint64_t SH_FLD_TC_UNIT_CHIP_ID_DC = 14249; // 43 -const static uint64_t SH_FLD_TC_UNIT_CHIP_ID_DC_LEN = 14250; // 43 -const static uint64_t SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC = 14251; // 43 -const static uint64_t SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC = 14252; // 43 -const static uint64_t SH_FLD_TC_UNIT_GROUP_ID_DC = 14253; // 43 -const static uint64_t SH_FLD_TC_UNIT_GROUP_ID_DC_LEN = 14254; // 43 -const static uint64_t SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC = 14255; // 43 -const static uint64_t SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE = 14256; // 43 -const static uint64_t SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC = 14257; // 43 -const static uint64_t SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC = 14258; // 43 -const static uint64_t SH_FLD_TC_UNIT_SYS_ID_DC = 14259; // 43 -const static uint64_t SH_FLD_TC_UNIT_SYS_ID_DC_LEN = 14260; // 43 -const static uint64_t SH_FLD_TC_VITL_REGION_FENCE = 14261; // 43 -const static uint64_t SH_FLD_TDR_DAC_CNTL = 14262; // 4 -const static uint64_t SH_FLD_TDR_DAC_CNTL_LEN = 14263; // 4 -const static uint64_t SH_FLD_TDR_PERR_ESR = 14264; // 1 -const static uint64_t SH_FLD_TDR_PHASE_SEL = 14265; // 4 -const static uint64_t SH_FLD_TDR_PULSE_OFFSET = 14266; // 4 -const static uint64_t SH_FLD_TDR_PULSE_OFFSET_LEN = 14267; // 4 -const static uint64_t SH_FLD_TDR_PULSE_WIDTH = 14268; // 4 -const static uint64_t SH_FLD_TDR_PULSE_WIDTH_LEN = 14269; // 4 -const static uint64_t SH_FLD_TER = 14270; // 8 -const static uint64_t SH_FLD_TERM_ENC = 14271; // 1 -const static uint64_t SH_FLD_TERM_ENC_LEN = 14272; // 1 -const static uint64_t SH_FLD_TERM_TEST = 14273; // 1 -const static uint64_t SH_FLD_TER_LEN = 14274; // 8 -const static uint64_t SH_FLD_TER_V = 14275; // 8 -const static uint64_t SH_FLD_TEST_ENABLE = 14276; // 43 -const static uint64_t SH_FLD_TFAC_ERR = 14277; // 96 -const static uint64_t SH_FLD_TFMR_PARITY_ERR = 14278; // 96 -const static uint64_t SH_FLD_TGT_NODAL_DINC_ERR = 14279; // 12 -const static uint64_t SH_FLD_TGT_NODAL_REQ_DINC_ERR = 14280; // 12 -const static uint64_t SH_FLD_THERM_MODE = 14281; // 43 -const static uint64_t SH_FLD_THERM_MODEREG_PARITY_MASK = 14282; // 43 -const static uint64_t SH_FLD_THERM_MODE_LEN = 14283; // 43 -const static uint64_t SH_FLD_THERM_TRIP = 14284; // 43 -const static uint64_t SH_FLD_THERM_TRIP_LEN = 14285; // 43 -const static uint64_t SH_FLD_THRDID = 14286; // 4 -const static uint64_t SH_FLD_THRDID_LEN = 14287; // 4 -const static uint64_t SH_FLD_THREEPHAS = 14288; // 3 -const static uint64_t SH_FLD_THRESHOLD = 14289; // 1 -const static uint64_t SH_FLD_THRESH_0 = 14290; // 3 -const static uint64_t SH_FLD_THRESH_0_LEN = 14291; // 3 -const static uint64_t SH_FLD_THRESH_1 = 14292; // 3 -const static uint64_t SH_FLD_THRESH_1_LEN = 14293; // 3 -const static uint64_t SH_FLD_THRESH_2 = 14294; // 3 -const static uint64_t SH_FLD_THRESH_2_LEN = 14295; // 3 -const static uint64_t SH_FLD_THRES_ENA = 14296; // 43 -const static uint64_t SH_FLD_THRES_ENA_LEN = 14297; // 43 -const static uint64_t SH_FLD_THRES_OVERFLOW_MASK = 14298; // 43 -const static uint64_t SH_FLD_THRES_STATE_MASK = 14299; // 43 -const static uint64_t SH_FLD_THRES_TRIP_ENA = 14300; // 43 -const static uint64_t SH_FLD_THRES_TRIP_ENA_LEN = 14301; // 43 -const static uint64_t SH_FLD_THRID = 14302; // 1 -const static uint64_t SH_FLD_THRID_LEN = 14303; // 1 -const static uint64_t SH_FLD_THR_ID = 14304; // 1 -const static uint64_t SH_FLD_THR_ID_LEN = 14305; // 1 -const static uint64_t SH_FLD_TID = 14306; // 8 -const static uint64_t SH_FLD_TID_LEN = 14307; // 8 -const static uint64_t SH_FLD_TIER0_VALUE = 14308; // 12 -const static uint64_t SH_FLD_TIER0_VALUE_LEN = 14309; // 12 -const static uint64_t SH_FLD_TIER1_VALUE = 14310; // 24 -const static uint64_t SH_FLD_TIER1_VALUE_LEN = 14311; // 24 -const static uint64_t SH_FLD_TIER2_VALUE = 14312; // 24 -const static uint64_t SH_FLD_TIER2_VALUE_LEN = 14313; // 24 -const static uint64_t SH_FLD_TIME = 14314; // 43 -const static uint64_t SH_FLD_TIMEBASE = 14315; // 330 -const static uint64_t SH_FLD_TIMEBASE_ENABLE = 14316; // 1 -const static uint64_t SH_FLD_TIMEBASE_LEN = 14317; // 330 -const static uint64_t SH_FLD_TIMEFAC_ERROR_INJ = 14318; // 24 -const static uint64_t SH_FLD_TIMEFAC_ERROR_INJ_LEN = 14319; // 24 -const static uint64_t SH_FLD_TIMEOUT_ACTIVE = 14320; // 2 -const static uint64_t SH_FLD_TIMEOUT_EN = 14321; // 1 -const static uint64_t SH_FLD_TIMEOUT_MASK = 14322; // 43 -const static uint64_t SH_FLD_TIMEOUT_N = 14323; // 2 -const static uint64_t SH_FLD_TIMEOUT_PARITY = 14324; // 43 -const static uint64_t SH_FLD_TIMEOUT_SEL = 14325; // 3 -const static uint64_t SH_FLD_TIMEOUT_SEL_LEN = 14326; // 3 -const static uint64_t SH_FLD_TIMEOUT_VALUE = 14327; // 1 -const static uint64_t SH_FLD_TIMEOUT_VALUE_LEN = 14328; // 1 -const static uint64_t SH_FLD_TIMER = 14329; // 4 -const static uint64_t SH_FLD_TIMER_ENABLE = 14330; // 4 -const static uint64_t SH_FLD_TIMER_EXPIRED_RECOV_ERROR = 14331; // 4 -const static uint64_t SH_FLD_TIMER_EXPIRED_XSTOP_ERROR = 14332; // 4 -const static uint64_t SH_FLD_TIMER_LEN = 14333; // 4 -const static uint64_t SH_FLD_TIMER_N = 14334; // 2 -const static uint64_t SH_FLD_TIMER_N_LEN = 14335; // 2 -const static uint64_t SH_FLD_TIMER_PERIOD_MASK = 14336; // 4 -const static uint64_t SH_FLD_TIMER_PERIOD_MASK_LEN = 14337; // 4 -const static uint64_t SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR = 14338; // 43 -const static uint64_t SH_FLD_TIMESTAMP_COUNTER_VALUE = 14339; // 43 -const static uint64_t SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN = 14340; // 43 -const static uint64_t SH_FLD_TIME_BASE_ERR = 14341; // 4 -const static uint64_t SH_FLD_TLBIE_CNT_THRESH = 14342; // 13 -const static uint64_t SH_FLD_TLBIE_CNT_THRESH_LEN = 14343; // 13 -const static uint64_t SH_FLD_TLBIE_CNT_WT4TX_CORE_EN = 14344; // 12 -const static uint64_t SH_FLD_TLBIE_CONTROL_ERR = 14345; // 24 -const static uint64_t SH_FLD_TLBIE_DEC_RATE = 14346; // 13 -const static uint64_t SH_FLD_TLBIE_DEC_RATE_LEN = 14347; // 13 -const static uint64_t SH_FLD_TLBIE_INC_RATE = 14348; // 13 -const static uint64_t SH_FLD_TLBIE_INC_RATE_LEN = 14349; // 13 -const static uint64_t SH_FLD_TLBIE_MASTER_TIMEOUT = 14350; // 24 -const static uint64_t SH_FLD_TLBIE_PACING_CNT_EN = 14351; // 12 -const static uint64_t SH_FLD_TLBIE_SLBIEG_SW_ERR = 14352; // 12 -const static uint64_t SH_FLD_TLBIE_SNOOP_TIMEOUT = 14353; // 24 -const static uint64_t SH_FLD_TLBIE_STALL_CMPLT_CNT = 14354; // 14 -const static uint64_t SH_FLD_TLBIE_STALL_CMPLT_CNT_LEN = 14355; // 14 -const static uint64_t SH_FLD_TLBIE_STALL_DELAY_CNT = 14356; // 14 -const static uint64_t SH_FLD_TLBIE_STALL_DELAY_CNT_LEN = 14357; // 14 -const static uint64_t SH_FLD_TLBIE_STALL_EN = 14358; // 14 -const static uint64_t SH_FLD_TLBIE_STALL_THRESHOLD = 14359; // 14 -const static uint64_t SH_FLD_TLBIE_STALL_THRESHOLD_LEN = 14360; // 14 -const static uint64_t SH_FLD_TLBIE_SW_ERR = 14361; // 12 -const static uint64_t SH_FLD_TLBI_BAD_OP_ERR = 14362; // 4 -const static uint64_t SH_FLD_TLBI_DATA_POLL_PULSE_DIV = 14363; // 2 -const static uint64_t SH_FLD_TLBI_DATA_POLL_PULSE_DIV_LEN = 14364; // 2 -const static uint64_t SH_FLD_TLBI_FENCE = 14365; // 2 -const static uint64_t SH_FLD_TLBI_GROUP_PUMP_EN = 14366; // 12 -const static uint64_t SH_FLD_TLBI_PSL_DEAD = 14367; // 2 -const static uint64_t SH_FLD_TLBI_SEQ_ERR = 14368; // 4 -const static uint64_t SH_FLD_TLBI_SEQ_NUM_PARITY_ERR = 14369; // 4 -const static uint64_t SH_FLD_TLBI_TIMEOUT = 14370; // 4 -const static uint64_t SH_FLD_TLB_BUS0_STG1_SEL = 14371; // 1 -const static uint64_t SH_FLD_TLB_BUS0_STG2_SEL = 14372; // 1 -const static uint64_t SH_FLD_TLB_BUS1_STG1_SEL = 14373; // 1 -const static uint64_t SH_FLD_TLB_BUS1_STG2_SEL = 14374; // 1 -const static uint64_t SH_FLD_TLB_CHK_WAIT_DEC = 14375; // 12 -const static uint64_t SH_FLD_TLB_CHK_WAIT_DEC_LEN = 14376; // 12 -const static uint64_t SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV = 14377; // 12 -const static uint64_t SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN = 14378; // 12 -const static uint64_t SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV = 14379; // 12 -const static uint64_t SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV_LEN = 14380; // 12 -const static uint64_t SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV = 14381; // 12 -const static uint64_t SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV_LEN = 14382; // 12 -const static uint64_t SH_FLD_TMOD_CYCLES = 14383; // 8 -const static uint64_t SH_FLD_TMOD_CYCLES_LEN = 14384; // 8 -const static uint64_t SH_FLD_TMRSC_CYCLES = 14385; // 8 -const static uint64_t SH_FLD_TMRSC_CYCLES_LEN = 14386; // 8 -const static uint64_t SH_FLD_TMR_PE = 14387; // 8 -const static uint64_t SH_FLD_TM_CAM_ERR = 14388; // 12 -const static uint64_t SH_FLD_TM_CAM_ERR_LEN = 14389; // 12 -const static uint64_t SH_FLD_TODTLON_OFF_CYCLES = 14390; // 8 -const static uint64_t SH_FLD_TODTLON_OFF_CYCLES_LEN = 14391; // 8 -const static uint64_t SH_FLD_TOD_CMD_OVERRUN = 14392; // 1 -const static uint64_t SH_FLD_TOD_CNTR_REF = 14393; // 1 -const static uint64_t SH_FLD_TOD_CNTR_REF_LEN = 14394; // 1 -const static uint64_t SH_FLD_TOD_HANG_ERR = 14395; // 1 -const static uint64_t SH_FLD_TOO_MANY_BUS_ERRORS = 14396; // 8 -const static uint64_t SH_FLD_TOR_PERR_ESR = 14397; // 1 -const static uint64_t SH_FLD_TOTAL_FREE_BUF_COUNT = 14398; // 1 -const static uint64_t SH_FLD_TOTAL_FREE_BUF_COUNT_LEN = 14399; // 1 -const static uint64_t SH_FLD_TOTAL_GAP_COUNTS = 14400; // 8 -const static uint64_t SH_FLD_TOTAL_GAP_COUNTS_LEN = 14401; // 8 -const static uint64_t SH_FLD_TPCFSI_OPB_SW0_FENCE_DC = 14402; // 1 -const static uint64_t SH_FLD_TPCFSI_OPB_SW0_FENCE_DC_LEN = 14403; // 1 -const static uint64_t SH_FLD_TPCFSI_OPB_SW1_FENCE_DC = 14404; // 1 -const static uint64_t SH_FLD_TPCFSI_OPB_SW1_FENCE_DC_LEN = 14405; // 1 -const static uint64_t SH_FLD_TPCFSI_OPB_SW_RESET_DC = 14406; // 1 -const static uint64_t SH_FLD_TPFSI_ALTREFCLK_SE1 = 14407; // 1 -const static uint64_t SH_FLD_TPFSI_ALTREFCLK_SEL = 14408; // 1 -const static uint64_t SH_FLD_TPFSI_ARRAY_SET_VBL_TO_VDD_DC = 14409; // 1 -const static uint64_t SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC = 14410; // 1 -const static uint64_t SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN = 14411; // 1 -const static uint64_t SH_FLD_TPFSI_OSCSW0_PGOOD_N = 14412; // 1 -const static uint64_t SH_FLD_TPFSI_OSCSW1_PGOOD = 14413; // 1 -const static uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ0_DC = 14414; // 1 -const static uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ0_DC_LEN = 14415; // 1 -const static uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ1_DC = 14416; // 1 -const static uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ1_DC_LEN = 14417; // 1 -const static uint64_t SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC = 14418; // 1 -const static uint64_t SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN = 14419; // 1 -const static uint64_t SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC = 14420; // 1 -const static uint64_t SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN = 14421; // 1 -const static uint64_t SH_FLD_TPFSI_OSCSW_TWEAK_DC = 14422; // 1 -const static uint64_t SH_FLD_TPFSI_OSCSW_TWEAK_DC_LEN = 14423; // 1 -const static uint64_t SH_FLD_TPFSI_SBE_FENCE_VTLIO_DC = 14424; // 1 -const static uint64_t SH_FLD_TPFSI_TPI2C_BUS_FENCE_DC = 14425; // 1 -const static uint64_t SH_FLD_TPFSI_TP_FENCE_VTLIO_DC = 14426; // 1 -const static uint64_t SH_FLD_TPFSI_TP_LOWFREQTEST_REFCLK_DC = 14427; // 1 -const static uint64_t SH_FLD_TPFSI_TP_PFET_FORCE_OFF_DC = 14428; // 1 -const static uint64_t SH_FLD_TPFSI_TP_PFET_OVERRIDE_ON_DC_N = 14429; // 1 -const static uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC = 14430; // 1 -const static uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC = 14431; // 1 -const static uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC = 14432; // 1 -const static uint64_t SH_FLD_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC = 14433; // 1 -const static uint64_t SH_FLD_TP_ARRAY_WRITE_ASSIST_EN_DC = 14434; // 1 -const static uint64_t SH_FLD_TP_CHIPLET_EN_DC = 14435; // 1 -const static uint64_t SH_FLD_TP_CLK_ASYNC_RESET_DC = 14436; // 1 -const static uint64_t SH_FLD_TP_CLK_DIV_BYPASS_EN_DC = 14437; // 1 -const static uint64_t SH_FLD_TP_CLK_PDLY_BYPASS1_EN_DC = 14438; // 1 -const static uint64_t SH_FLD_TP_CLK_PDLY_BYPASS2_EN_DC = 14439; // 1 -const static uint64_t SH_FLD_TP_CLK_PULSE_ENABLE_DC = 14440; // 1 -const static uint64_t SH_FLD_TP_CLK_PULSE_MODE_DC = 14441; // 1 -const static uint64_t SH_FLD_TP_CLK_PULSE_MODE_DC_LEN = 14442; // 1 -const static uint64_t SH_FLD_TP_CPM_CAL_SET = 14443; // 1 -const static uint64_t SH_FLD_TP_DI1_DC_B = 14444; // 1 -const static uint64_t SH_FLD_TP_DI1_DC_N = 14445; // 1 -const static uint64_t SH_FLD_TP_DI2_DC_B = 14446; // 1 -const static uint64_t SH_FLD_TP_DI2_DC_N = 14447; // 1 -const static uint64_t SH_FLD_TP_EDRAM_ENABLE_DC = 14448; // 1 -const static uint64_t SH_FLD_TP_EXSD_FULLSPEED_DC = 14449; // 1 -const static uint64_t SH_FLD_TP_EX_FUSE_FP_THROTTLE_EN_DC = 14450; // 1 -const static uint64_t SH_FLD_TP_EX_FUSE_VMX_CRYPTO_DIS_DC = 14451; // 1 -const static uint64_t SH_FLD_TP_FENCE_EN_DC = 14452; // 1 -const static uint64_t SH_FLD_TP_FENCE_PCB = 14453; // 43 -const static uint64_t SH_FLD_TP_FENCE_PCB_DC = 14454; // 1 -const static uint64_t SH_FLD_TP_FILTPLL_CP_ALT_BYPASS_DC = 14455; // 1 -const static uint64_t SH_FLD_TP_FILTPLL_IO_ALT_BYPASS_DC = 14456; // 1 -const static uint64_t SH_FLD_TP_FILTPLL_PLL_BYPASS1_DC = 14457; // 1 -const static uint64_t SH_FLD_TP_FILTPLL_PLL_RESET1_DC = 14458; // 1 -const static uint64_t SH_FLD_TP_FLUSH_ALIGN_OVERWRITE = 14459; // 1 -const static uint64_t SH_FLD_TP_FLUSH_SCAN_DC_N = 14460; // 1 -const static uint64_t SH_FLD_TP_FSI_CLKIN_SEL_DC = 14461; // 1 -const static uint64_t SH_FLD_TP_FSI_PROBE_SEL_DC = 14462; // 1 -const static uint64_t SH_FLD_TP_FSI_PROBE_SEL_DC_LEN = 14463; // 1 -const static uint64_t SH_FLD_TP_GLBCK_MEM_TESTCLK_SEL_DC = 14464; // 1 -const static uint64_t SH_FLD_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC = 14465; // 1 -const static uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC = 14466; // 1 -const static uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN = 14467; // 1 -const static uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC = 14468; // 1 -const static uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN = 14469; // 1 -const static uint64_t SH_FLD_TP_GPIO_PIB_TIMEOUT = 14470; // 1 -const static uint64_t SH_FLD_TP_GPIO_PIB_TIMEOUT_LEN = 14471; // 1 -const static uint64_t SH_FLD_TP_IDDQ_DC = 14472; // 1 -const static uint64_t SH_FLD_TP_LVLTRANS_FENCE_DC = 14473; // 1 -const static uint64_t SH_FLD_TP_NX_ALLOW_CRYPTO_DC = 14474; // 1 -const static uint64_t SH_FLD_TP_OSCSWITCH_VSB = 14475; // 1 -const static uint64_t SH_FLD_TP_OSCSWITCH_VSB_LEN = 14476; // 1 -const static uint64_t SH_FLD_TP_PCB_EP_RESET_DC = 14477; // 1 -const static uint64_t SH_FLD_TP_PCB_PM_MUX_SEL_DC = 14478; // 1 -const static uint64_t SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC = 14479; // 1 -const static uint64_t SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC_LEN = 14480; // 1 -const static uint64_t SH_FLD_TP_PIB_TRACE_MODE_DATA_DC = 14481; // 1 -const static uint64_t SH_FLD_TP_PIB_VSB_DISABLE_PARITY_DC = 14482; // 1 -const static uint64_t SH_FLD_TP_PIB_VSB_SBE_TRACE_MODE = 14483; // 1 -const static uint64_t SH_FLD_TP_PLLBYP_DC = 14484; // 1 -const static uint64_t SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC = 14485; // 1 -const static uint64_t SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC_LEN = 14486; // 1 -const static uint64_t SH_FLD_TP_PLLRST_DC = 14487; // 1 -const static uint64_t SH_FLD_TP_PLL_CLKIN_SEL1_DC = 14488; // 1 -const static uint64_t SH_FLD_TP_PLL_CLKIN_SEL2_DC = 14489; // 1 -const static uint64_t SH_FLD_TP_PLL_CLKIN_SEL3_DC = 14490; // 1 -const static uint64_t SH_FLD_TP_PLL_CLKIN_SEL4_DC = 14491; // 1 -const static uint64_t SH_FLD_TP_PLL_FORCE_OUT_EN_DC = 14492; // 1 -const static uint64_t SH_FLD_TP_PLL_TEST_ENABLE_DC = 14493; // 1 -const static uint64_t SH_FLD_TP_PLL_TEST_EN_DC = 14494; // 1 -const static uint64_t SH_FLD_TP_PROBE0_SEL_DC = 14495; // 1 -const static uint64_t SH_FLD_TP_PROBE0_SEL_DC_LEN = 14496; // 1 -const static uint64_t SH_FLD_TP_PROBE1_SEL_DC = 14497; // 1 -const static uint64_t SH_FLD_TP_PROBE1_SEL_DC_LEN = 14498; // 1 -const static uint64_t SH_FLD_TP_PROBE_DRV_EN_DC = 14499; // 1 -const static uint64_t SH_FLD_TP_PROBE_HIGHDRIVE_DC = 14500; // 1 -const static uint64_t SH_FLD_TP_PROBE_MESH_SEL_DC = 14501; // 1 -const static uint64_t SH_FLD_TP_RESCLK_DIS_DC = 14502; // 1 -const static uint64_t SH_FLD_TP_RI_DC_B = 14503; // 1 -const static uint64_t SH_FLD_TP_RI_DC_N = 14504; // 1 -const static uint64_t SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC = 14505; // 1 -const static uint64_t SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC_LEN = 14506; // 1 -const static uint64_t SH_FLD_TP_SSPLL_PLL_BYPASS0_DC = 14507; // 1 -const static uint64_t SH_FLD_TP_SSPLL_PLL_RESET0_DC = 14508; // 1 -const static uint64_t SH_FLD_TP_TANKPLL_TEST_PLL_BYPASS2_DC = 14509; // 1 -const static uint64_t SH_FLD_TP_TEST_BURNIN_MODE_DC = 14510; // 1 -const static uint64_t SH_FLD_TP_TPCPERV_VSB_TRACE_STOP = 14511; // 1 -const static uint64_t SH_FLD_TP_TPFSI_ACK = 14512; // 43 -const static uint64_t SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL = 14513; // 30 -const static uint64_t SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL_LEN = 14514; // 30 -const static uint64_t SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL = 14515; // 30 -const static uint64_t SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL_LEN = 14516; // 30 -const static uint64_t SH_FLD_TP_VITL_ACT_DIS_DC = 14517; // 1 -const static uint64_t SH_FLD_TP_VITL_CLKOFF_DC = 14518; // 1 -const static uint64_t SH_FLD_TP_VITL_DELAY_LCLKR_DC = 14519; // 1 -const static uint64_t SH_FLD_TP_VITL_MPW1_DC_N = 14520; // 1 -const static uint64_t SH_FLD_TP_VITL_MPW2_DC_N = 14521; // 1 -const static uint64_t SH_FLD_TP_VITL_MPW3_DC_N = 14522; // 1 -const static uint64_t SH_FLD_TP_VITL_SCAN_CLK_DC = 14523; // 1 -const static uint64_t SH_FLD_TP_VITL_SCIN_DC = 14524; // 1 -const static uint64_t SH_FLD_TRACE_BUS_BITS_64_87 = 14525; // 1 -const static uint64_t SH_FLD_TRACE_BUS_BITS_64_87_LEN = 14526; // 1 -const static uint64_t SH_FLD_TRACE_BUS_EN = 14527; // 1 -const static uint64_t SH_FLD_TRACE_BUS_SEL_0_1 = 14528; // 1 -const static uint64_t SH_FLD_TRACE_BUS_SEL_0_1_LEN = 14529; // 1 -const static uint64_t SH_FLD_TRACE_BUS_TRIGGER_BITS = 14530; // 1 -const static uint64_t SH_FLD_TRACE_BUS_TRIGGER_BITS_LEN = 14531; // 1 -const static uint64_t SH_FLD_TRACE_DATA_SELECT = 14532; // 1 -const static uint64_t SH_FLD_TRACE_DATA_SELECT_LEN = 14533; // 1 -const static uint64_t SH_FLD_TRACE_DISABLE = 14534; // 1 -const static uint64_t SH_FLD_TRACE_ENABLE = 14535; // 6 -const static uint64_t SH_FLD_TRACE_EVENT = 14536; // 1 -const static uint64_t SH_FLD_TRACE_MUX_SEL = 14537; // 1 -const static uint64_t SH_FLD_TRACE_SEL = 14538; // 1 -const static uint64_t SH_FLD_TRACE_SELECT = 14539; // 2 -const static uint64_t SH_FLD_TRACE_SELECT_LEN = 14540; // 2 -const static uint64_t SH_FLD_TRACE_SEL_0_1 = 14541; // 1 -const static uint64_t SH_FLD_TRACE_SEL_0_1_LEN = 14542; // 1 -const static uint64_t SH_FLD_TRACE_SEL_LEN = 14543; // 1 -const static uint64_t SH_FLD_TRACE_TRIGGER = 14544; // 1 -const static uint64_t SH_FLD_TRACKING_TIMEOUT_SEL = 14545; // 6 -const static uint64_t SH_FLD_TRACKING_TIMEOUT_SEL_LEN = 14546; // 6 -const static uint64_t SH_FLD_TRANSPORT_INFORMATIONAL_ERR = 14547; // 4 -const static uint64_t SH_FLD_TRANS_DELAY = 14548; // 1 -const static uint64_t SH_FLD_TRANS_DELAY_LEN = 14549; // 1 -const static uint64_t SH_FLD_TRASH_EN = 14550; // 12 -const static uint64_t SH_FLD_TRCD_CYCLES = 14551; // 8 -const static uint64_t SH_FLD_TRCD_CYCLES_LEN = 14552; // 8 -const static uint64_t SH_FLD_TRC_CMD_OVERRUN = 14553; // 1 -const static uint64_t SH_FLD_TRC_CYCLES = 14554; // 8 -const static uint64_t SH_FLD_TRC_CYCLES_LEN = 14555; // 8 -const static uint64_t SH_FLD_TRC_MODE = 14556; // 6 -const static uint64_t SH_FLD_TRC_MODE_LEN = 14557; // 6 -const static uint64_t SH_FLD_TRFC_CYCLES = 14558; // 8 -const static uint64_t SH_FLD_TRFC_CYCLES_LEN = 14559; // 8 -const static uint64_t SH_FLD_TRIG = 14560; // 17 -const static uint64_t SH_FLD_TRIGGER = 14561; // 31 -const static uint64_t SH_FLD_TRIGGER_OPCG_ON = 14562; // 129 -const static uint64_t SH_FLD_TRIG_FIR_HMI = 14563; // 96 -const static uint64_t SH_FLD_TRIG_OVERIDE = 14564; // 24 -const static uint64_t SH_FLD_TRP_CYCLES = 14565; // 8 -const static uint64_t SH_FLD_TRP_CYCLES_LEN = 14566; // 8 -const static uint64_t SH_FLD_TRRD = 14567; // 8 -const static uint64_t SH_FLD_TRRD_LEN = 14568; // 8 -const static uint64_t SH_FLD_TRRD_SBG = 14569; // 8 -const static uint64_t SH_FLD_TRRD_SBG_LEN = 14570; // 8 -const static uint64_t SH_FLD_TRST_B_EQ0_ERR = 14571; // 1 -const static uint64_t SH_FLD_TRY_ATR_RO = 14572; // 1 -const static uint64_t SH_FLD_TSIZE = 14573; // 1 -const static uint64_t SH_FLD_TSIZE_4_6 = 14574; // 1 -const static uint64_t SH_FLD_TSIZE_4_6_LEN = 14575; // 1 -const static uint64_t SH_FLD_TSIZE_MASK = 14576; // 8 -const static uint64_t SH_FLD_TSIZE_MASK_LEN = 14577; // 8 -const static uint64_t SH_FLD_TSIZE_MATCH = 14578; // 8 -const static uint64_t SH_FLD_TSIZE_MATCH_LEN = 14579; // 8 -const static uint64_t SH_FLD_TTAG_PARITY_ERROR = 14580; // 2 -const static uint64_t SH_FLD_TTYPE_MATCH = 14581; // 8 -const static uint64_t SH_FLD_TTYPE_MATCH_LEN = 14582; // 8 -const static uint64_t SH_FLD_TTYPE_REPLACE = 14583; // 8 -const static uint64_t SH_FLD_TTYPE_REPLACE_LEN = 14584; // 8 -const static uint64_t SH_FLD_TVT0_PAGE_SIZE = 14585; // 1 -const static uint64_t SH_FLD_TVT0_PAGE_SIZE_LEN = 14586; // 1 -const static uint64_t SH_FLD_TVT0_SPARE = 14587; // 1 -const static uint64_t SH_FLD_TVT0_SPARE_LEN = 14588; // 1 -const static uint64_t SH_FLD_TVT0_TABLE_LEVEL = 14589; // 1 -const static uint64_t SH_FLD_TVT0_TABLE_LEVEL_LEN = 14590; // 1 -const static uint64_t SH_FLD_TVT0_TABLE_SIZE = 14591; // 1 -const static uint64_t SH_FLD_TVT0_TABLE_SIZE_LEN = 14592; // 1 -const static uint64_t SH_FLD_TVT0_XLAT_ADDR = 14593; // 1 -const static uint64_t SH_FLD_TVT0_XLAT_ADDR_LEN = 14594; // 1 -const static uint64_t SH_FLD_TVT_ADDR_RANGE_ERR_ESR = 14595; // 1 -const static uint64_t SH_FLD_TVT_ENTRY_INVALID_ESR = 14596; // 1 -const static uint64_t SH_FLD_TVT_PERR_ESR = 14597; // 1 -const static uint64_t SH_FLD_TWLDQSEN_CYCLES = 14598; // 8 -const static uint64_t SH_FLD_TWLDQSEN_CYCLES_LEN = 14599; // 8 -const static uint64_t SH_FLD_TWLO_TWLOE = 14600; // 8 -const static uint64_t SH_FLD_TWLO_TWLOE_LEN = 14601; // 8 -const static uint64_t SH_FLD_TWO_CYCLE_ADDR_EN = 14602; // 8 -const static uint64_t SH_FLD_TWRMRD_CYCLES = 14603; // 8 -const static uint64_t SH_FLD_TWRMRD_CYCLES_LEN = 14604; // 8 -const static uint64_t SH_FLD_TWSM_DIS = 14605; // 1 -const static uint64_t SH_FLD_TWSM_DIS_LEN = 14606; // 1 -const static uint64_t SH_FLD_TW_ATT_HPT_SAO_FOLD_DIS = 14607; // 1 -const static uint64_t SH_FLD_TW_ATT_RDX_NIO_FOLD_DIS = 14608; // 1 -const static uint64_t SH_FLD_TW_ATT_RDX_SAO_FOLD_DIS = 14609; // 1 -const static uint64_t SH_FLD_TW_ATT_RDX_TIO_FOLD_DIS = 14610; // 1 -const static uint64_t SH_FLD_TW_BUS0_STG1_SEL = 14611; // 1 -const static uint64_t SH_FLD_TW_BUS0_STG2_SEL = 14612; // 1 -const static uint64_t SH_FLD_TW_BUS1_STG1_SEL = 14613; // 1 -const static uint64_t SH_FLD_TW_BUS1_STG2_SEL = 14614; // 1 -const static uint64_t SH_FLD_TW_LCO_RDX_C_DIS = 14615; // 1 -const static uint64_t SH_FLD_TW_LCO_RDX_EN = 14616; // 1 -const static uint64_t SH_FLD_TW_LCO_RDX_PDE_EN = 14617; // 1 -const static uint64_t SH_FLD_TW_LCO_RDX_PWC_L2_DIS = 14618; // 1 -const static uint64_t SH_FLD_TW_LCO_RDX_PWC_L3_DIS = 14619; // 1 -const static uint64_t SH_FLD_TW_LCO_RDX_PWC_L4_DIS = 14620; // 1 -const static uint64_t SH_FLD_TW_LCO_RDX_P_DIS = 14621; // 1 -const static uint64_t SH_FLD_TXAERR = 14622; // 6 -const static uint64_t SH_FLD_TXBERR = 14623; // 6 -const static uint64_t SH_FLD_TXCERR = 14624; // 6 -const static uint64_t SH_FLD_TXDERR = 14625; // 6 -const static uint64_t SH_FLD_TXEERR = 14626; // 6 -const static uint64_t SH_FLD_TXFERR = 14627; // 6 -const static uint64_t SH_FLD_TXGERR = 14628; // 6 -const static uint64_t SH_FLD_TXHERR = 14629; // 6 -const static uint64_t SH_FLD_TXIERR = 14630; // 6 -const static uint64_t SH_FLD_TXJERR = 14631; // 6 -const static uint64_t SH_FLD_TXKERR = 14632; // 6 -const static uint64_t SH_FLD_TXLERR = 14633; // 6 -const static uint64_t SH_FLD_TXMERR = 14634; // 6 -const static uint64_t SH_FLD_TXNERR = 14635; // 6 -const static uint64_t SH_FLD_TXOERR = 14636; // 6 -const static uint64_t SH_FLD_TXPERR = 14637; // 6 -const static uint64_t SH_FLD_TX_BUS_WIDTH = 14638; // 4 -const static uint64_t SH_FLD_TX_BUS_WIDTH_LEN = 14639; // 4 -const static uint64_t SH_FLD_TX_DATA_ECC_CORR_ENA = 14640; // 6 -const static uint64_t SH_FLD_TX_ECC_DATA_POISON_ENA = 14641; // 6 -const static uint64_t SH_FLD_TX_SLS_DISABLE = 14642; // 4 -const static uint64_t SH_FLD_TX_TRISTATE_CNTL = 14643; // 8 -const static uint64_t SH_FLD_TX_TTYPE_PIB_MST_FSM_STATE_DISABLE = 14644; // 1 -const static uint64_t SH_FLD_TX_TTYPE_PIB_MST_IF_RESET = 14645; // 1 -const static uint64_t SH_FLD_TYPE = 14646; // 108 -const static uint64_t SH_FLD_TYPE_LEN = 14647; // 44 -const static uint64_t SH_FLD_TZQCS_CYCLES = 14648; // 8 -const static uint64_t SH_FLD_TZQCS_CYCLES_LEN = 14649; // 8 -const static uint64_t SH_FLD_TZQINIT_CYCLES = 14650; // 8 -const static uint64_t SH_FLD_TZQINIT_CYCLES_LEN = 14651; // 8 -const static uint64_t SH_FLD_UE1_0_OUT = 14652; // 4 -const static uint64_t SH_FLD_UE1_1_OUT = 14653; // 4 -const static uint64_t SH_FLD_UE1_2_OUT = 14654; // 4 -const static uint64_t SH_FLD_UE1_3_OUT = 14655; // 4 -const static uint64_t SH_FLD_UE1_4_OUT = 14656; // 4 -const static uint64_t SH_FLD_UE1_5_OUT = 14657; // 4 -const static uint64_t SH_FLD_UE1_6_OUT = 14658; // 4 -const static uint64_t SH_FLD_UE1_7_OUT = 14659; // 4 -const static uint64_t SH_FLD_UE2_0_OUT = 14660; // 4 -const static uint64_t SH_FLD_UE2_1_OUT = 14661; // 4 -const static uint64_t SH_FLD_UE2_2_OUT = 14662; // 4 -const static uint64_t SH_FLD_UE2_3_OUT = 14663; // 4 -const static uint64_t SH_FLD_UE2_4_OUT = 14664; // 4 -const static uint64_t SH_FLD_UE2_5_OUT = 14665; // 4 -const static uint64_t SH_FLD_UE2_6_OUT = 14666; // 4 -const static uint64_t SH_FLD_UE2_7_OUT = 14667; // 4 -const static uint64_t SH_FLD_UE_COUNT = 14668; // 2 -const static uint64_t SH_FLD_UE_COUNT_LEN = 14669; // 2 -const static uint64_t SH_FLD_UE_DISABLE = 14670; // 2 -const static uint64_t SH_FLD_UMAC_CRB_SUE = 14671; // 1 -const static uint64_t SH_FLD_UMAC_CRB_UE = 14672; // 1 -const static uint64_t SH_FLD_UMAC_LD_LINK_ERR = 14673; // 1 -const static uint64_t SH_FLD_UMAC_LINK_ABORT = 14674; // 1 -const static uint64_t SH_FLD_UMAC_MUX_SELECT = 14675; // 1 -const static uint64_t SH_FLD_UMAC_MUX_SELECT_LEN = 14676; // 1 -const static uint64_t SH_FLD_UMAC_RD_DISABLE_GROUP = 14677; // 1 -const static uint64_t SH_FLD_UMAC_RD_DISABLE_LN = 14678; // 1 -const static uint64_t SH_FLD_UMAC_RD_DISABLE_NN_RN = 14679; // 1 -const static uint64_t SH_FLD_UMAC_RD_DISABLE_VG_NOT_SYS = 14680; // 1 -const static uint64_t SH_FLD_UMAC_WC_INT_ADDR_UE = 14681; // 1 -const static uint64_t SH_FLD_UMAC_WR_DISABLE_GROUP = 14682; // 1 -const static uint64_t SH_FLD_UMAC_WR_DISABLE_LN = 14683; // 1 -const static uint64_t SH_FLD_UMAC_WR_DISABLE_NN_RN = 14684; // 1 -const static uint64_t SH_FLD_UMAC_WR_DISABLE_VG_NOT_SYS = 14685; // 1 -const static uint64_t SH_FLD_UNCORR_ERROR = 14686; // 1 -const static uint64_t SH_FLD_UNEXPECTEDCRESP = 14687; // 9 -const static uint64_t SH_FLD_UNEXPECTEDCRESP_MASK = 14688; // 9 -const static uint64_t SH_FLD_UNEXPECTED_PB = 14689; // 4 -const static uint64_t SH_FLD_UNEXPECT_DATA = 14690; // 1 -const static uint64_t SH_FLD_UNIT1 = 14691; // 215 -const static uint64_t SH_FLD_UNIT10 = 14692; // 215 -const static uint64_t SH_FLD_UNIT2 = 14693; // 215 -const static uint64_t SH_FLD_UNIT3 = 14694; // 215 -const static uint64_t SH_FLD_UNIT4 = 14695; // 215 -const static uint64_t SH_FLD_UNIT5 = 14696; // 215 -const static uint64_t SH_FLD_UNIT6 = 14697; // 215 -const static uint64_t SH_FLD_UNIT7 = 14698; // 215 -const static uint64_t SH_FLD_UNIT8 = 14699; // 215 -const static uint64_t SH_FLD_UNIT9 = 14700; // 215 -const static uint64_t SH_FLD_UNIT_REGION_CLKCMD_ENABLE = 14701; // 43 -const static uint64_t SH_FLD_UNLOAD_CLK_DISABLE = 14702; // 116 -const static uint64_t SH_FLD_UNLOAD_SEL = 14703; // 116 -const static uint64_t SH_FLD_UNLOAD_SEL_LEN = 14704; // 116 -const static uint64_t SH_FLD_UNSOLICITIEDPBDATA = 14705; // 9 -const static uint64_t SH_FLD_UNSOLICITIEDPBDATA_MASK = 14706; // 9 -const static uint64_t SH_FLD_UNTRUSTED = 14707; // 4 -const static uint64_t SH_FLD_UNTRUSTED_LEN = 14708; // 4 -const static uint64_t SH_FLD_UNUSED = 14709; // 131 -const static uint64_t SH_FLD_UNUSED0 = 14710; // 1 -const static uint64_t SH_FLD_UNUSED1 = 14711; // 46 -const static uint64_t SH_FLD_UNUSED1520 = 14712; // 43 -const static uint64_t SH_FLD_UNUSED1520_LEN = 14713; // 43 -const static uint64_t SH_FLD_UNUSED1_LEN = 14714; // 45 -const static uint64_t SH_FLD_UNUSED2 = 14715; // 48 -const static uint64_t SH_FLD_UNUSED23_31 = 14716; // 7 -const static uint64_t SH_FLD_UNUSED23_31_LEN = 14717; // 7 -const static uint64_t SH_FLD_UNUSED2_LEN = 14718; // 44 -const static uint64_t SH_FLD_UNUSED3 = 14719; // 47 -const static uint64_t SH_FLD_UNUSED3_LEN = 14720; // 1 -const static uint64_t SH_FLD_UNUSED4 = 14721; // 9 -const static uint64_t SH_FLD_UNUSED41_63 = 14722; // 43 -const static uint64_t SH_FLD_UNUSED41_63_LEN = 14723; // 43 -const static uint64_t SH_FLD_UNUSED46 = 14724; // 43 -const static uint64_t SH_FLD_UNUSED4_LEN = 14725; // 1 -const static uint64_t SH_FLD_UNUSED5 = 14726; // 7 -const static uint64_t SH_FLD_UNUSED63 = 14727; // 3 -const static uint64_t SH_FLD_UNUSED78 = 14728; // 43 -const static uint64_t SH_FLD_UNUSED78_LEN = 14729; // 43 -const static uint64_t SH_FLD_UNUSED88 = 14730; // 3 -const static uint64_t SH_FLD_UNUSED88_LEN = 14731; // 3 -const static uint64_t SH_FLD_UNUSED919 = 14732; // 43 -const static uint64_t SH_FLD_UNUSED919_LEN = 14733; // 43 -const static uint64_t SH_FLD_UNUSED_0 = 14734; // 44 -const static uint64_t SH_FLD_UNUSED_0B = 14735; // 43 -const static uint64_t SH_FLD_UNUSED_0D = 14736; // 36 -const static uint64_t SH_FLD_UNUSED_0_LEN = 14737; // 1 -const static uint64_t SH_FLD_UNUSED_1 = 14738; // 44 -const static uint64_t SH_FLD_UNUSED_10B = 14739; // 35 -const static uint64_t SH_FLD_UNUSED_11B = 14740; // 36 -const static uint64_t SH_FLD_UNUSED_12B = 14741; // 37 -const static uint64_t SH_FLD_UNUSED_13B = 14742; // 37 -const static uint64_t SH_FLD_UNUSED_14B = 14743; // 43 -const static uint64_t SH_FLD_UNUSED_16_22 = 14744; // 1 -const static uint64_t SH_FLD_UNUSED_16_22_LEN = 14745; // 1 -const static uint64_t SH_FLD_UNUSED_17B = 14746; // 43 -const static uint64_t SH_FLD_UNUSED_18B = 14747; // 43 -const static uint64_t SH_FLD_UNUSED_19B = 14748; // 43 -const static uint64_t SH_FLD_UNUSED_1B = 14749; // 43 -const static uint64_t SH_FLD_UNUSED_1D = 14750; // 36 -const static uint64_t SH_FLD_UNUSED_1_LEN = 14751; // 1 -const static uint64_t SH_FLD_UNUSED_2 = 14752; // 1 -const static uint64_t SH_FLD_UNUSED_20B = 14753; // 42 -const static uint64_t SH_FLD_UNUSED_21B = 14754; // 43 -const static uint64_t SH_FLD_UNUSED_22B = 14755; // 43 -const static uint64_t SH_FLD_UNUSED_23B = 14756; // 43 -const static uint64_t SH_FLD_UNUSED_24B = 14757; // 43 -const static uint64_t SH_FLD_UNUSED_25B = 14758; // 43 -const static uint64_t SH_FLD_UNUSED_26B = 14759; // 43 -const static uint64_t SH_FLD_UNUSED_26_31 = 14760; // 1 -const static uint64_t SH_FLD_UNUSED_26_31_LEN = 14761; // 1 -const static uint64_t SH_FLD_UNUSED_27B = 14762; // 43 -const static uint64_t SH_FLD_UNUSED_28B = 14763; // 43 -const static uint64_t SH_FLD_UNUSED_29B = 14764; // 43 -const static uint64_t SH_FLD_UNUSED_2B = 14765; // 43 -const static uint64_t SH_FLD_UNUSED_2D = 14766; // 36 -const static uint64_t SH_FLD_UNUSED_2_LEN = 14767; // 1 -const static uint64_t SH_FLD_UNUSED_3 = 14768; // 1 -const static uint64_t SH_FLD_UNUSED_30B = 14769; // 43 -const static uint64_t SH_FLD_UNUSED_31B = 14770; // 43 -const static uint64_t SH_FLD_UNUSED_39_43 = 14771; // 1 -const static uint64_t SH_FLD_UNUSED_39_43_LEN = 14772; // 1 -const static uint64_t SH_FLD_UNUSED_3D = 14773; // 36 -const static uint64_t SH_FLD_UNUSED_3_LEN = 14774; // 1 -const static uint64_t SH_FLD_UNUSED_47_51 = 14775; // 1 -const static uint64_t SH_FLD_UNUSED_47_51_LEN = 14776; // 1 -const static uint64_t SH_FLD_UNUSED_4_15 = 14777; // 1 -const static uint64_t SH_FLD_UNUSED_4_15_LEN = 14778; // 1 -const static uint64_t SH_FLD_UNUSED_53 = 14779; // 1 -const static uint64_t SH_FLD_UNUSED_5B = 14780; // 1 -const static uint64_t SH_FLD_UNUSED_6B = 14781; // 1 -const static uint64_t SH_FLD_UNUSED_7B = 14782; // 27 -const static uint64_t SH_FLD_UNUSED_8B = 14783; // 31 -const static uint64_t SH_FLD_UNUSED_8_14 = 14784; // 1 -const static uint64_t SH_FLD_UNUSED_8_14_LEN = 14785; // 1 -const static uint64_t SH_FLD_UNUSED_9B = 14786; // 33 -const static uint64_t SH_FLD_UNUSED_LEN = 14787; // 88 -const static uint64_t SH_FLD_UPSTREAM = 14788; // 4 -const static uint64_t SH_FLD_USERDEF_CFG = 14789; // 6 -const static uint64_t SH_FLD_USERDEF_CFG_LEN = 14790; // 6 -const static uint64_t SH_FLD_USERDEF_TIMEOUT = 14791; // 6 -const static uint64_t SH_FLD_USERDEF_TIMEOUT_LEN = 14792; // 6 -const static uint64_t SH_FLD_USER_FILTER_MASK = 14793; // 6 -const static uint64_t SH_FLD_USER_FILTER_MASK_LEN = 14794; // 6 -const static uint64_t SH_FLD_USE_ARY_CLK_DURING_FILL = 14795; // 43 -const static uint64_t SH_FLD_USE_FOR_SCAN = 14796; // 43 -const static uint64_t SH_FLD_USE_OSC_OBSERVATION = 14797; // 1 -const static uint64_t SH_FLD_USE_OSC_OBSERVATION_LEN = 14798; // 1 -const static uint64_t SH_FLD_USE_PECE = 14799; // 24 -const static uint64_t SH_FLD_USE_PECE_LEN = 14800; // 24 -const static uint64_t SH_FLD_USE_SLS_AS_SPR = 14801; // 4 -const static uint64_t SH_FLD_USE_TB_STEP_SYNC = 14802; // 1 -const static uint64_t SH_FLD_USE_TB_SYNC_MECHANISM = 14803; // 1 -const static uint64_t SH_FLD_USE_WATCH_TO_READ_CTRL_ARY = 14804; // 1 -const static uint64_t SH_FLD_VALID = 14805; // 61 -const static uint64_t SH_FLD_VALID_ATRGPA0 = 14806; // 256 -const static uint64_t SH_FLD_VALID_ATRGPA1 = 14807; // 256 -const static uint64_t SH_FLD_VALID_ATSD = 14808; // 256 -const static uint64_t SH_FLD_VALID_ENTRY = 14809; // 1 -const static uint64_t SH_FLD_VALUE = 14810; // 50 -const static uint64_t SH_FLD_VALUES0 = 14811; // 16 -const static uint64_t SH_FLD_VALUES0_LEN = 14812; // 16 -const static uint64_t SH_FLD_VALUES1 = 14813; // 16 -const static uint64_t SH_FLD_VALUES1_LEN = 14814; // 16 -const static uint64_t SH_FLD_VALUES2 = 14815; // 16 -const static uint64_t SH_FLD_VALUES2_LEN = 14816; // 16 -const static uint64_t SH_FLD_VALUES3 = 14817; // 16 -const static uint64_t SH_FLD_VALUES3_LEN = 14818; // 16 -const static uint64_t SH_FLD_VALUES4 = 14819; // 16 -const static uint64_t SH_FLD_VALUES4_LEN = 14820; // 16 -const static uint64_t SH_FLD_VALUES5 = 14821; // 16 -const static uint64_t SH_FLD_VALUES5_LEN = 14822; // 16 -const static uint64_t SH_FLD_VALUES6 = 14823; // 16 -const static uint64_t SH_FLD_VALUES6_LEN = 14824; // 16 -const static uint64_t SH_FLD_VALUES7 = 14825; // 16 -const static uint64_t SH_FLD_VALUES7_LEN = 14826; // 16 -const static uint64_t SH_FLD_VALUE_LEN = 14827; // 50 -const static uint64_t SH_FLD_VAS_LOCAL_XSTOP = 14828; // 1 -const static uint64_t SH_FLD_VBGENDOC = 14829; // 3 -const static uint64_t SH_FLD_VBGENDOC_LEN = 14830; // 3 -const static uint64_t SH_FLD_VCC_REG_PD = 14831; // 8 -const static uint64_t SH_FLD_VCORANGE = 14832; // 10 -const static uint64_t SH_FLD_VCORANGE_LEN = 14833; // 10 -const static uint64_t SH_FLD_VCOSEL = 14834; // 16 -const static uint64_t SH_FLD_VCS_PFETS_DISABLED_SENSE = 14835; // 30 -const static uint64_t SH_FLD_VCS_PFETS_ENABLED_SENSE = 14836; // 30 -const static uint64_t SH_FLD_VCS_PFET_ENABLE_VALUE = 14837; // 30 -const static uint64_t SH_FLD_VCS_PFET_ENABLE_VALUE_LEN = 14838; // 30 -const static uint64_t SH_FLD_VCS_PFET_FORCE_STATE = 14839; // 30 -const static uint64_t SH_FLD_VCS_PFET_FORCE_STATE_LEN = 14840; // 30 -const static uint64_t SH_FLD_VCS_PFET_SEL_OVERRIDE = 14841; // 30 -const static uint64_t SH_FLD_VCS_PFET_SEL_VALUE = 14842; // 30 -const static uint64_t SH_FLD_VCS_PFET_SEL_VALUE_LEN = 14843; // 30 -const static uint64_t SH_FLD_VCS_PFET_VAL_OVERRIDE = 14844; // 30 -const static uint64_t SH_FLD_VCS_PG_SEL = 14845; // 30 -const static uint64_t SH_FLD_VCS_PG_SEL_LEN = 14846; // 30 -const static uint64_t SH_FLD_VCS_PG_STATE = 14847; // 30 -const static uint64_t SH_FLD_VCS_PG_STATE_LEN = 14848; // 30 -const static uint64_t SH_FLD_VCS_VOFF_SEL = 14849; // 30 -const static uint64_t SH_FLD_VCS_VOFF_SEL_LEN = 14850; // 30 -const static uint64_t SH_FLD_VC_PRIORITY_LIMIT_0_3 = 14851; // 1 -const static uint64_t SH_FLD_VC_PRIORITY_LIMIT_0_3_LEN = 14852; // 1 -const static uint64_t SH_FLD_VDD2VIO_LVL_FENCE_DC = 14853; // 1 -const static uint64_t SH_FLD_VDD_NEST_OBSERVE = 14854; // 1 -const static uint64_t SH_FLD_VDD_PFETS_DISABLED_SENSE = 14855; // 30 -const static uint64_t SH_FLD_VDD_PFETS_ENABLED_SENSE = 14856; // 30 -const static uint64_t SH_FLD_VDD_PFET_ENABLE_VALUE = 14857; // 30 -const static uint64_t SH_FLD_VDD_PFET_ENABLE_VALUE_LEN = 14858; // 30 -const static uint64_t SH_FLD_VDD_PFET_FORCE_STATE = 14859; // 30 -const static uint64_t SH_FLD_VDD_PFET_FORCE_STATE_LEN = 14860; // 30 -const static uint64_t SH_FLD_VDD_PFET_REGULATION_FINGER_EN = 14861; // 30 -const static uint64_t SH_FLD_VDD_PFET_REGULATION_FINGER_VALUE = 14862; // 30 -const static uint64_t SH_FLD_VDD_PFET_SEL_OVERRIDE = 14863; // 30 -const static uint64_t SH_FLD_VDD_PFET_SEL_VALUE = 14864; // 30 -const static uint64_t SH_FLD_VDD_PFET_SEL_VALUE_LEN = 14865; // 30 -const static uint64_t SH_FLD_VDD_PFET_VAL_OVERRIDE = 14866; // 30 -const static uint64_t SH_FLD_VDD_PG_SEL = 14867; // 30 -const static uint64_t SH_FLD_VDD_PG_SEL_LEN = 14868; // 30 -const static uint64_t SH_FLD_VDD_PG_STATE = 14869; // 30 -const static uint64_t SH_FLD_VDD_PG_STATE_LEN = 14870; // 30 -const static uint64_t SH_FLD_VDD_VOFF_SEL = 14871; // 30 -const static uint64_t SH_FLD_VDD_VOFF_SEL_LEN = 14872; // 30 -const static uint64_t SH_FLD_VDM_DISABLE = 14873; // 30 -const static uint64_t SH_FLD_VDM_DROOP_LARGE = 14874; // 6 -const static uint64_t SH_FLD_VDM_DROOP_LARGE_LEN = 14875; // 6 -const static uint64_t SH_FLD_VDM_DROOP_SMALL = 14876; // 6 -const static uint64_t SH_FLD_VDM_DROOP_SMALL_LEN = 14877; // 6 -const static uint64_t SH_FLD_VDM_DROOP_XTREME = 14878; // 6 -const static uint64_t SH_FLD_VDM_DROOP_XTREME_LEN = 14879; // 6 -const static uint64_t SH_FLD_VDM_EXTREME_DROOP_CTR = 14880; // 12 -const static uint64_t SH_FLD_VDM_EXTREME_DROOP_CTR_LEN = 14881; // 12 -const static uint64_t SH_FLD_VDM_LARGE_DROOP_CTR = 14882; // 12 -const static uint64_t SH_FLD_VDM_LARGE_DROOP_CTR_LEN = 14883; // 12 -const static uint64_t SH_FLD_VDM_LCL_SAMPLE_EN = 14884; // 12 -const static uint64_t SH_FLD_VDM_NO_DROOP_CTR = 14885; // 12 -const static uint64_t SH_FLD_VDM_NO_DROOP_CTR_LEN = 14886; // 12 -const static uint64_t SH_FLD_VDM_OVERVOLT = 14887; // 6 -const static uint64_t SH_FLD_VDM_OVERVOLT_CTR = 14888; // 12 -const static uint64_t SH_FLD_VDM_OVERVOLT_CTR_LEN = 14889; // 12 -const static uint64_t SH_FLD_VDM_OVERVOLT_LEN = 14890; // 6 -const static uint64_t SH_FLD_VDM_POWERON = 14891; // 30 -const static uint64_t SH_FLD_VDM_SMALL_DROOP_CTR = 14892; // 12 -const static uint64_t SH_FLD_VDM_SMALL_DROOP_CTR_LEN = 14893; // 12 -const static uint64_t SH_FLD_VDM_VID_COMPARE = 14894; // 6 -const static uint64_t SH_FLD_VDM_VID_COMPARE_LEN = 14895; // 6 -const static uint64_t SH_FLD_VECTOR_GROUP_EPSILON = 14896; // 8 -const static uint64_t SH_FLD_VECTOR_GROUP_EPSILON_LEN = 14897; // 8 -const static uint64_t SH_FLD_VG_COUNT = 14898; // 2 -const static uint64_t SH_FLD_VG_COUNT_LEN = 14899; // 2 -const static uint64_t SH_FLD_VG_TARGE = 14900; // 1 -const static uint64_t SH_FLD_VG_TARGET_SEL = 14901; // 24 -const static uint64_t SH_FLD_VG_TARGE_LEN = 14902; // 1 -const static uint64_t SH_FLD_VID_COMPARE_MAX = 14903; // 6 -const static uint64_t SH_FLD_VID_COMPARE_MAX_LEN = 14904; // 6 -const static uint64_t SH_FLD_VID_COMPARE_MIN = 14905; // 6 -const static uint64_t SH_FLD_VID_COMPARE_MIN_LEN = 14906; // 6 -const static uint64_t SH_FLD_VITAL_SCAN = 14907; // 43 -const static uint64_t SH_FLD_VITAL_SCAN_IN = 14908; // 43 -const static uint64_t SH_FLD_VITAL_THOLD = 14909; // 43 -const static uint64_t SH_FLD_VITL = 14910; // 43 -const static uint64_t SH_FLD_VITL_CLKOFF = 14911; // 43 -const static uint64_t SH_FLD_VLD = 14912; // 4 -const static uint64_t SH_FLD_VOFF_CFG = 14913; // 6 -const static uint64_t SH_FLD_VOFF_CFG_LEN = 14914; // 6 -const static uint64_t SH_FLD_VOLT_MODEREG_PARITY_MASK = 14915; // 43 -const static uint64_t SH_FLD_VPROTH_CTL = 14916; // 8 -const static uint64_t SH_FLD_VPROTH_CTL_LEN = 14917; // 8 -const static uint64_t SH_FLD_VREF = 14918; // 1 -const static uint64_t SH_FLD_VREFDQ0D = 14919; // 8 -const static uint64_t SH_FLD_VREFDQ0DSGN = 14920; // 8 -const static uint64_t SH_FLD_VREFDQ0D_LEN = 14921; // 8 -const static uint64_t SH_FLD_VREFDQ1D = 14922; // 8 -const static uint64_t SH_FLD_VREFDQ1DSGN = 14923; // 8 -const static uint64_t SH_FLD_VREFDQ1D_LEN = 14924; // 8 -const static uint64_t SH_FLD_VREFTUNE = 14925; // 3 -const static uint64_t SH_FLD_VREFTUNE_LEN = 14926; // 3 -const static uint64_t SH_FLD_VREF_LEN = 14927; // 1 -const static uint64_t SH_FLD_VREGBYP = 14928; // 6 -const static uint64_t SH_FLD_VREGBYPASS = 14929; // 4 -const static uint64_t SH_FLD_VREGENABLE_N = 14930; // 4 -const static uint64_t SH_FLD_VSEL = 14931; // 10 -const static uint64_t SH_FLD_VSEL_LEN = 14932; // 10 -const static uint64_t SH_FLD_VST_TYPE = 14933; // 1 -const static uint64_t SH_FLD_VST_TYPE_LEN = 14934; // 1 -const static uint64_t SH_FLD_VTARGET = 14935; // 4 -const static uint64_t SH_FLD_VTARGET_LEN = 14936; // 4 -const static uint64_t SH_FLD_V_TARG = 14937; // 1 -const static uint64_t SH_FLD_V_TARG_LEN = 14938; // 1 -const static uint64_t SH_FLD_W0_COUNT = 14939; // 12 -const static uint64_t SH_FLD_W0_COUNT_LEN = 14940; // 12 -const static uint64_t SH_FLD_W1_COUNT = 14941; // 12 -const static uint64_t SH_FLD_W1_COUNT_LEN = 14942; // 12 -const static uint64_t SH_FLD_WAITING = 14943; // 2 -const static uint64_t SH_FLD_WAIT_ALLWAYS = 14944; // 129 -const static uint64_t SH_FLD_WAIT_CYCLES = 14945; // 172 -const static uint64_t SH_FLD_WAIT_CYCLES_LEN = 14946; // 172 -const static uint64_t SH_FLD_WAKEUP_PULSE = 14947; // 1 -const static uint64_t SH_FLD_WAKEUP_PULSE_LEN = 14948; // 1 -const static uint64_t SH_FLD_WANT_CACHE_DISABLE = 14949; // 3 -const static uint64_t SH_FLD_WANT_INVALIDATE = 14950; // 2 -const static uint64_t SH_FLD_WARB_INVALID_CASE_ERROR = 14951; // 2 -const static uint64_t SH_FLD_WARM_START_COMPLETED = 14952; // 2 -const static uint64_t SH_FLD_WATCHDOG_SEL = 14953; // 17 -const static uint64_t SH_FLD_WATCHDOG_SEL_LEN = 14954; // 17 -const static uint64_t SH_FLD_WATERMARK_REG = 14955; // 1 -const static uint64_t SH_FLD_WATERMARK_REG_0 = 14956; // 1 -const static uint64_t SH_FLD_WATERMARK_REG_0_LEN = 14957; // 1 -const static uint64_t SH_FLD_WATERMARK_REG_1 = 14958; // 1 -const static uint64_t SH_FLD_WATERMARK_REG_1_LEN = 14959; // 1 -const static uint64_t SH_FLD_WATERMARK_REG_2 = 14960; // 1 -const static uint64_t SH_FLD_WATERMARK_REG_2_LEN = 14961; // 1 -const static uint64_t SH_FLD_WATERMARK_REG_3 = 14962; // 1 -const static uint64_t SH_FLD_WATERMARK_REG_3_LEN = 14963; // 1 -const static uint64_t SH_FLD_WATERMARK_REG_LEN = 14964; // 1 -const static uint64_t SH_FLD_WAT_DEBUG_ATTN = 14965; // 10 -const static uint64_t SH_FLD_WAT_ERROR = 14966; // 16 -const static uint64_t SH_FLD_WBMGR_DBG_0_SELECT = 14967; // 8 -const static uint64_t SH_FLD_WBMGR_DBG_1_SELECT = 14968; // 8 -const static uint64_t SH_FLD_WBRD_DEBUG_0_SELECT = 14969; // 8 -const static uint64_t SH_FLD_WBRD_DEBUG_1_SELECT = 14970; // 8 -const static uint64_t SH_FLD_WC = 14971; // 8 -const static uint64_t SH_FLD_WC_BS_BAR = 14972; // 1 -const static uint64_t SH_FLD_WC_BS_BAR_LEN = 14973; // 1 -const static uint64_t SH_FLD_WC_CERR_BITS = 14974; // 1 -const static uint64_t SH_FLD_WC_CERR_BITS_LEN = 14975; // 1 -const static uint64_t SH_FLD_WC_CERR_RESET = 14976; // 1 -const static uint64_t SH_FLD_WC_ECC_CE_ERROR = 14977; // 2 -const static uint64_t SH_FLD_WC_ECC_SUE_ERROR = 14978; // 2 -const static uint64_t SH_FLD_WC_ECC_UE_ERROR = 14979; // 2 -const static uint64_t SH_FLD_WC_LOGIC_HW_ERROR = 14980; // 2 -const static uint64_t SH_FLD_WC_MASK = 14981; // 8 -const static uint64_t SH_FLD_WC_TRACE_GROUP_SEL_HI = 14982; // 1 -const static uint64_t SH_FLD_WC_TRACE_GROUP_SEL_HI_LEN = 14983; // 1 -const static uint64_t SH_FLD_WC_TRACE_GROUP_SEL_LO = 14984; // 1 -const static uint64_t SH_FLD_WC_TRACE_GROUP_SEL_LO_LEN = 14985; // 1 -const static uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_01 = 14986; // 1 -const static uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_01_LEN = 14987; // 1 -const static uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_23 = 14988; // 1 -const static uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_23_LEN = 14989; // 1 -const static uint64_t SH_FLD_WDATA = 14990; // 1 -const static uint64_t SH_FLD_WDATA_LEN = 14991; // 1 -const static uint64_t SH_FLD_WDF_ASYNC_INTERFACE_ERROR = 14992; // 8 -const static uint64_t SH_FLD_WDF_ERR_INJECT0 = 14993; // 8 -const static uint64_t SH_FLD_WDF_ERR_INJECT0_LEN = 14994; // 8 -const static uint64_t SH_FLD_WDF_MISC_REGISTER_PARITY_ERROR = 14995; // 8 -const static uint64_t SH_FLD_WDF_OVERRUN_ERROR_0 = 14996; // 8 -const static uint64_t SH_FLD_WDF_OVERRUN_ERROR_1 = 14997; // 8 -const static uint64_t SH_FLD_WDF_SCOM_SEQUENCE_ERROR = 14998; // 8 -const static uint64_t SH_FLD_WDF_STATE_MACHINE_ERROR = 14999; // 8 -const static uint64_t SH_FLD_WINDOW_SELECT = 15000; // 3 -const static uint64_t SH_FLD_WINDOW_SELECT_LEN = 15001; // 3 -const static uint64_t SH_FLD_WIRETEST_DONE = 15002; // 4 -const static uint64_t SH_FLD_WIRETEST_FAILED = 15003; // 4 -const static uint64_t SH_FLD_WITH_ADDRESS_0 = 15004; // 1 -const static uint64_t SH_FLD_WITH_ADDRESS_1 = 15005; // 1 -const static uint64_t SH_FLD_WITH_ADDRESS_2 = 15006; // 1 -const static uint64_t SH_FLD_WITH_ADDRESS_3 = 15007; // 1 -const static uint64_t SH_FLD_WITH_START_0 = 15008; // 1 -const static uint64_t SH_FLD_WITH_START_1 = 15009; // 1 -const static uint64_t SH_FLD_WITH_START_2 = 15010; // 1 -const static uint64_t SH_FLD_WITH_START_3 = 15011; // 1 -const static uint64_t SH_FLD_WITH_STOP_0 = 15012; // 1 -const static uint64_t SH_FLD_WITH_STOP_1 = 15013; // 1 -const static uint64_t SH_FLD_WITH_STOP_2 = 15014; // 1 -const static uint64_t SH_FLD_WITH_STOP_3 = 15015; // 1 -const static uint64_t SH_FLD_WI_MACHINE_HANG_ERR = 15016; // 12 -const static uint64_t SH_FLD_WI_MACHINE_W4DT_HANG_ERR = 15017; // 12 -const static uint64_t SH_FLD_WI_UNSOLICITED_DATA_ERR = 15018; // 12 -const static uint64_t SH_FLD_WKUP_NOTIFY_SELECT = 15019; // 24 -const static uint64_t SH_FLD_WL_ONE_DQS_PULSE = 15020; // 8 -const static uint64_t SH_FLD_WM_MULTIHIT_ERR = 15021; // 2 -const static uint64_t SH_FLD_WM_WIN_NOT_OPEN_ERR = 15022; // 2 -const static uint64_t SH_FLD_WOF = 15023; // 5 -const static uint64_t SH_FLD_WOF_COUNTER = 15024; // 1 -const static uint64_t SH_FLD_WOF_COUNTER_LEN = 15025; // 1 -const static uint64_t SH_FLD_WOF_LEN = 15026; // 5 -const static uint64_t SH_FLD_WOF_LOW_ORDER_STEP_COUNTER_PARITY = 15027; // 4 -const static uint64_t SH_FLD_WORD = 15028; // 8 -const static uint64_t SH_FLD_WORD_LEN = 15029; // 8 -const static uint64_t SH_FLD_WRAP = 15030; // 1 -const static uint64_t SH_FLD_WRAP_0 = 15031; // 1 -const static uint64_t SH_FLD_WRAP_1 = 15032; // 1 -const static uint64_t SH_FLD_WRAP_2 = 15033; // 1 -const static uint64_t SH_FLD_WRAP_3 = 15034; // 1 -const static uint64_t SH_FLD_WRCMP = 15035; // 2 -const static uint64_t SH_FLD_WRCMP_LEN = 15036; // 2 -const static uint64_t SH_FLD_WRCNTL_DBG_SELECT = 15037; // 8 -const static uint64_t SH_FLD_WRDM_DLY = 15038; // 8 -const static uint64_t SH_FLD_WRDM_DLY_LEN = 15039; // 8 -const static uint64_t SH_FLD_WRD_MCBIST_OUT_OF_SYNC_HOLD_OUT = 15040; // 2 -const static uint64_t SH_FLD_WRITE = 15041; // 9 -const static uint64_t SH_FLD_WRITE_CMD = 15042; // 1 -const static uint64_t SH_FLD_WRITE_COMPLETE = 15043; // 1 -const static uint64_t SH_FLD_WRITE_COUNT = 15044; // 8 -const static uint64_t SH_FLD_WRITE_COUNTER = 15045; // 1 -const static uint64_t SH_FLD_WRITE_COUNTER_LEN = 15046; // 1 -const static uint64_t SH_FLD_WRITE_COUNT_LEN = 15047; // 8 -const static uint64_t SH_FLD_WRITE_CRD_POOL = 15048; // 1 -const static uint64_t SH_FLD_WRITE_CRD_POOL_LEN = 15049; // 1 -const static uint64_t SH_FLD_WRITE_CTR = 15050; // 8 -const static uint64_t SH_FLD_WRITE_ENABLE = 15051; // 129 -const static uint64_t SH_FLD_WRITE_ENABLE_0 = 15052; // 1 -const static uint64_t SH_FLD_WRITE_ENABLE_1 = 15053; // 1 -const static uint64_t SH_FLD_WRITE_ENABLE_2 = 15054; // 1 -const static uint64_t SH_FLD_WRITE_ENABLE_3 = 15055; // 1 -const static uint64_t SH_FLD_WRITE_ERR_INJECT0 = 15056; // 8 -const static uint64_t SH_FLD_WRITE_ERR_INJECT0_LEN = 15057; // 8 -const static uint64_t SH_FLD_WRITE_INVALID_FACES = 15058; // 1 -const static uint64_t SH_FLD_WRITE_INVALID_PIB = 15059; // 1 -const static uint64_t SH_FLD_WRITE_LATENCY_OFFSET = 15060; // 8 -const static uint64_t SH_FLD_WRITE_LATENCY_OFFSET_LEN = 15061; // 8 -const static uint64_t SH_FLD_WRITE_NOT_READ = 15062; // 3 -const static uint64_t SH_FLD_WRITE_NVLD = 15063; // 1 -const static uint64_t SH_FLD_WRITE_RMW_CE = 15064; // 8 -const static uint64_t SH_FLD_WRITE_RMW_SUE = 15065; // 8 -const static uint64_t SH_FLD_WRITE_RMW_UE = 15066; // 8 -const static uint64_t SH_FLD_WRITE_RST_INTERRUPT_FACES = 15067; // 1 -const static uint64_t SH_FLD_WRITE_RST_INTERRUPT_PIB = 15068; // 1 -const static uint64_t SH_FLD_WRITE_TSIZE = 15069; // 4 -const static uint64_t SH_FLD_WRITE_TSIZE_LEN = 15070; // 4 -const static uint64_t SH_FLD_WRITE_TTYPE = 15071; // 4 -const static uint64_t SH_FLD_WRITE_TTYPE_LEN = 15072; // 4 -const static uint64_t SH_FLD_WRITE_WHILE_BRIDGE_BUSY_ERR = 15073; // 1 -const static uint64_t SH_FLD_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 15074; // 1 -const static uint64_t SH_FLD_WRMON_BAR0_BA = 15075; // 1 -const static uint64_t SH_FLD_WRMON_BAR0_BA_LEN = 15076; // 1 -const static uint64_t SH_FLD_WRMON_BAR0_SIZE = 15077; // 1 -const static uint64_t SH_FLD_WRMON_BAR0_SIZE_LEN = 15078; // 1 -const static uint64_t SH_FLD_WRMON_BAR1_BA = 15079; // 1 -const static uint64_t SH_FLD_WRMON_BAR1_BA_LEN = 15080; // 1 -const static uint64_t SH_FLD_WRMON_BAR1_SIZE = 15081; // 1 -const static uint64_t SH_FLD_WRMON_BAR1_SIZE_LEN = 15082; // 1 -const static uint64_t SH_FLD_WRMON_BAR2_BA = 15083; // 1 -const static uint64_t SH_FLD_WRMON_BAR2_BA_LEN = 15084; // 1 -const static uint64_t SH_FLD_WRMON_BAR2_SIZE = 15085; // 1 -const static uint64_t SH_FLD_WRMON_BAR2_SIZE_LEN = 15086; // 1 -const static uint64_t SH_FLD_WRMON_BAR3_BA = 15087; // 1 -const static uint64_t SH_FLD_WRMON_BAR3_BA_LEN = 15088; // 1 -const static uint64_t SH_FLD_WRMON_BAR3_SIZE = 15089; // 1 -const static uint64_t SH_FLD_WRMON_BAR3_SIZE_LEN = 15090; // 1 -const static uint64_t SH_FLD_WRMON_BAR4_BA = 15091; // 1 -const static uint64_t SH_FLD_WRMON_BAR4_BA_LEN = 15092; // 1 -const static uint64_t SH_FLD_WRMON_BAR4_SIZE = 15093; // 1 -const static uint64_t SH_FLD_WRMON_BAR4_SIZE_LEN = 15094; // 1 -const static uint64_t SH_FLD_WRMON_BAR5_BA = 15095; // 1 -const static uint64_t SH_FLD_WRMON_BAR5_BA_LEN = 15096; // 1 -const static uint64_t SH_FLD_WRMON_BAR5_SIZE = 15097; // 1 -const static uint64_t SH_FLD_WRMON_BAR5_SIZE_LEN = 15098; // 1 -const static uint64_t SH_FLD_WRMON_BAR6_BA = 15099; // 1 -const static uint64_t SH_FLD_WRMON_BAR6_BA_LEN = 15100; // 1 -const static uint64_t SH_FLD_WRMON_BAR6_SIZE = 15101; // 1 -const static uint64_t SH_FLD_WRMON_BAR6_SIZE_LEN = 15102; // 1 -const static uint64_t SH_FLD_WRMON_BAR7_BA = 15103; // 1 -const static uint64_t SH_FLD_WRMON_BAR7_BA_LEN = 15104; // 1 -const static uint64_t SH_FLD_WRMON_BAR7_SIZE = 15105; // 1 -const static uint64_t SH_FLD_WRMON_BAR7_SIZE_LEN = 15106; // 1 -const static uint64_t SH_FLD_WRMON_CMP0_ENADTTYPE = 15107; // 1 -const static uint64_t SH_FLD_WRMON_CMP0_TSIZE = 15108; // 1 -const static uint64_t SH_FLD_WRMON_CMP0_TSIZEMSK = 15109; // 1 -const static uint64_t SH_FLD_WRMON_CMP0_TSIZEMSK_LEN = 15110; // 1 -const static uint64_t SH_FLD_WRMON_CMP0_TSIZE_LEN = 15111; // 1 -const static uint64_t SH_FLD_WRMON_CMP0_TTYPE = 15112; // 1 -const static uint64_t SH_FLD_WRMON_CMP0_TTYPEDIS = 15113; // 1 -const static uint64_t SH_FLD_WRMON_CMP0_TTYPEDIS_LEN = 15114; // 1 -const static uint64_t SH_FLD_WRMON_CMP0_TTYPEMSK = 15115; // 1 -const static uint64_t SH_FLD_WRMON_CMP0_TTYPEMSK_LEN = 15116; // 1 -const static uint64_t SH_FLD_WRMON_CMP0_TTYPE_LEN = 15117; // 1 -const static uint64_t SH_FLD_WRMON_CMP0_VAL = 15118; // 1 -const static uint64_t SH_FLD_WRMON_CMP1_ENADTTYPE = 15119; // 1 -const static uint64_t SH_FLD_WRMON_CMP1_TSIZE = 15120; // 1 -const static uint64_t SH_FLD_WRMON_CMP1_TSIZEMSK = 15121; // 1 -const static uint64_t SH_FLD_WRMON_CMP1_TSIZEMSK_LEN = 15122; // 1 -const static uint64_t SH_FLD_WRMON_CMP1_TSIZE_LEN = 15123; // 1 -const static uint64_t SH_FLD_WRMON_CMP1_TTYPE = 15124; // 1 -const static uint64_t SH_FLD_WRMON_CMP1_TTYPEDIS = 15125; // 1 -const static uint64_t SH_FLD_WRMON_CMP1_TTYPEDIS_LEN = 15126; // 1 -const static uint64_t SH_FLD_WRMON_CMP1_TTYPEMSK = 15127; // 1 -const static uint64_t SH_FLD_WRMON_CMP1_TTYPEMSK_LEN = 15128; // 1 -const static uint64_t SH_FLD_WRMON_CMP1_TTYPE_LEN = 15129; // 1 -const static uint64_t SH_FLD_WRMON_CMP1_VAL = 15130; // 1 -const static uint64_t SH_FLD_WRMON_CMP2_ENADTTYPE = 15131; // 1 -const static uint64_t SH_FLD_WRMON_CMP2_TSIZE = 15132; // 1 -const static uint64_t SH_FLD_WRMON_CMP2_TSIZEMSK = 15133; // 1 -const static uint64_t SH_FLD_WRMON_CMP2_TSIZEMSK_LEN = 15134; // 1 -const static uint64_t SH_FLD_WRMON_CMP2_TSIZE_LEN = 15135; // 1 -const static uint64_t SH_FLD_WRMON_CMP2_TTYPE = 15136; // 1 -const static uint64_t SH_FLD_WRMON_CMP2_TTYPEDIS = 15137; // 1 -const static uint64_t SH_FLD_WRMON_CMP2_TTYPEDIS_LEN = 15138; // 1 -const static uint64_t SH_FLD_WRMON_CMP2_TTYPEMSK = 15139; // 1 -const static uint64_t SH_FLD_WRMON_CMP2_TTYPEMSK_LEN = 15140; // 1 -const static uint64_t SH_FLD_WRMON_CMP2_TTYPE_LEN = 15141; // 1 -const static uint64_t SH_FLD_WRMON_CMP2_VAL = 15142; // 1 -const static uint64_t SH_FLD_WRMON_CMP3_ENADTTYPE = 15143; // 1 -const static uint64_t SH_FLD_WRMON_CMP3_TSIZE = 15144; // 1 -const static uint64_t SH_FLD_WRMON_CMP3_TSIZEMSK = 15145; // 1 -const static uint64_t SH_FLD_WRMON_CMP3_TSIZEMSK_LEN = 15146; // 1 -const static uint64_t SH_FLD_WRMON_CMP3_TSIZE_LEN = 15147; // 1 -const static uint64_t SH_FLD_WRMON_CMP3_TTYPE = 15148; // 1 -const static uint64_t SH_FLD_WRMON_CMP3_TTYPEDIS = 15149; // 1 -const static uint64_t SH_FLD_WRMON_CMP3_TTYPEDIS_LEN = 15150; // 1 -const static uint64_t SH_FLD_WRMON_CMP3_TTYPEMSK = 15151; // 1 -const static uint64_t SH_FLD_WRMON_CMP3_TTYPEMSK_LEN = 15152; // 1 -const static uint64_t SH_FLD_WRMON_CMP3_TTYPE_LEN = 15153; // 1 -const static uint64_t SH_FLD_WRMON_CMP3_VAL = 15154; // 1 -const static uint64_t SH_FLD_WRMON_CMP4_ENADTTYPE = 15155; // 1 -const static uint64_t SH_FLD_WRMON_CMP4_TSIZE = 15156; // 1 -const static uint64_t SH_FLD_WRMON_CMP4_TSIZEMSK = 15157; // 1 -const static uint64_t SH_FLD_WRMON_CMP4_TSIZEMSK_LEN = 15158; // 1 -const static uint64_t SH_FLD_WRMON_CMP4_TSIZE_LEN = 15159; // 1 -const static uint64_t SH_FLD_WRMON_CMP4_TTYPE = 15160; // 1 -const static uint64_t SH_FLD_WRMON_CMP4_TTYPEDIS = 15161; // 1 -const static uint64_t SH_FLD_WRMON_CMP4_TTYPEDIS_LEN = 15162; // 1 -const static uint64_t SH_FLD_WRMON_CMP4_TTYPEMSK = 15163; // 1 -const static uint64_t SH_FLD_WRMON_CMP4_TTYPEMSK_LEN = 15164; // 1 -const static uint64_t SH_FLD_WRMON_CMP4_TTYPE_LEN = 15165; // 1 -const static uint64_t SH_FLD_WRMON_CMP4_VAL = 15166; // 1 -const static uint64_t SH_FLD_WRMON_CMP5_ENADTTYPE = 15167; // 1 -const static uint64_t SH_FLD_WRMON_CMP5_TSIZE = 15168; // 1 -const static uint64_t SH_FLD_WRMON_CMP5_TSIZEMSK = 15169; // 1 -const static uint64_t SH_FLD_WRMON_CMP5_TSIZEMSK_LEN = 15170; // 1 -const static uint64_t SH_FLD_WRMON_CMP5_TSIZE_LEN = 15171; // 1 -const static uint64_t SH_FLD_WRMON_CMP5_TTYPE = 15172; // 1 -const static uint64_t SH_FLD_WRMON_CMP5_TTYPEDIS = 15173; // 1 -const static uint64_t SH_FLD_WRMON_CMP5_TTYPEDIS_LEN = 15174; // 1 -const static uint64_t SH_FLD_WRMON_CMP5_TTYPEMSK = 15175; // 1 -const static uint64_t SH_FLD_WRMON_CMP5_TTYPEMSK_LEN = 15176; // 1 -const static uint64_t SH_FLD_WRMON_CMP5_TTYPE_LEN = 15177; // 1 -const static uint64_t SH_FLD_WRMON_CMP5_VAL = 15178; // 1 -const static uint64_t SH_FLD_WRMON_CMP6_ENADTTYPE = 15179; // 1 -const static uint64_t SH_FLD_WRMON_CMP6_TSIZE = 15180; // 1 -const static uint64_t SH_FLD_WRMON_CMP6_TSIZEMSK = 15181; // 1 -const static uint64_t SH_FLD_WRMON_CMP6_TSIZEMSK_LEN = 15182; // 1 -const static uint64_t SH_FLD_WRMON_CMP6_TSIZE_LEN = 15183; // 1 -const static uint64_t SH_FLD_WRMON_CMP6_TTYPE = 15184; // 1 -const static uint64_t SH_FLD_WRMON_CMP6_TTYPEDIS = 15185; // 1 -const static uint64_t SH_FLD_WRMON_CMP6_TTYPEDIS_LEN = 15186; // 1 -const static uint64_t SH_FLD_WRMON_CMP6_TTYPEMSK = 15187; // 1 -const static uint64_t SH_FLD_WRMON_CMP6_TTYPEMSK_LEN = 15188; // 1 -const static uint64_t SH_FLD_WRMON_CMP6_TTYPE_LEN = 15189; // 1 -const static uint64_t SH_FLD_WRMON_CMP6_VAL = 15190; // 1 -const static uint64_t SH_FLD_WRMON_CMP7_ENADTTYPE = 15191; // 1 -const static uint64_t SH_FLD_WRMON_CMP7_TSIZE = 15192; // 1 -const static uint64_t SH_FLD_WRMON_CMP7_TSIZEMSK = 15193; // 1 -const static uint64_t SH_FLD_WRMON_CMP7_TSIZEMSK_LEN = 15194; // 1 -const static uint64_t SH_FLD_WRMON_CMP7_TSIZE_LEN = 15195; // 1 -const static uint64_t SH_FLD_WRMON_CMP7_TTYPE = 15196; // 1 -const static uint64_t SH_FLD_WRMON_CMP7_TTYPEDIS = 15197; // 1 -const static uint64_t SH_FLD_WRMON_CMP7_TTYPEDIS_LEN = 15198; // 1 -const static uint64_t SH_FLD_WRMON_CMP7_TTYPEMSK = 15199; // 1 -const static uint64_t SH_FLD_WRMON_CMP7_TTYPEMSK_LEN = 15200; // 1 -const static uint64_t SH_FLD_WRMON_CMP7_TTYPE_LEN = 15201; // 1 -const static uint64_t SH_FLD_WRMON_CMP7_VAL = 15202; // 1 -const static uint64_t SH_FLD_WRMON_WID0 = 15203; // 1 -const static uint64_t SH_FLD_WRMON_WID0_LEN = 15204; // 1 -const static uint64_t SH_FLD_WRMON_WID1 = 15205; // 1 -const static uint64_t SH_FLD_WRMON_WID1_LEN = 15206; // 1 -const static uint64_t SH_FLD_WRMON_WID2 = 15207; // 1 -const static uint64_t SH_FLD_WRMON_WID2_LEN = 15208; // 1 -const static uint64_t SH_FLD_WRMON_WID3 = 15209; // 1 -const static uint64_t SH_FLD_WRMON_WID3_LEN = 15210; // 1 -const static uint64_t SH_FLD_WRMON_WID4 = 15211; // 1 -const static uint64_t SH_FLD_WRMON_WID4_LEN = 15212; // 1 -const static uint64_t SH_FLD_WRMON_WID5 = 15213; // 1 -const static uint64_t SH_FLD_WRMON_WID5_LEN = 15214; // 1 -const static uint64_t SH_FLD_WRMON_WID6 = 15215; // 1 -const static uint64_t SH_FLD_WRMON_WID6_LEN = 15216; // 1 -const static uint64_t SH_FLD_WRMON_WID7 = 15217; // 1 -const static uint64_t SH_FLD_WRMON_WID7_LEN = 15218; // 1 -const static uint64_t SH_FLD_WRQ_CAPACITY_LIMIT = 15219; // 4 -const static uint64_t SH_FLD_WRQ_CAPACITY_LIMIT_LEN = 15220; // 4 -const static uint64_t SH_FLD_WRQ_FSM_PERR = 15221; // 1 -const static uint64_t SH_FLD_WRQ_HANG = 15222; // 8 -const static uint64_t SH_FLD_WRQ_OVERFLOW = 15223; // 1 -const static uint64_t SH_FLD_WRQ_PE = 15224; // 8 -const static uint64_t SH_FLD_WRQ_RRQ_HANG_ERR = 15225; // 16 -const static uint64_t SH_FLD_WRSBG_DLY = 15226; // 8 -const static uint64_t SH_FLD_WRSBG_DLY_LEN = 15227; // 8 -const static uint64_t SH_FLD_WRSMDR_DLY = 15228; // 8 -const static uint64_t SH_FLD_WRSMDR_DLY_LEN = 15229; // 8 -const static uint64_t SH_FLD_WRSMSR_DLY = 15230; // 8 -const static uint64_t SH_FLD_WRSMSR_DLY_LEN = 15231; // 8 -const static uint64_t SH_FLD_WRTO_AMO_COLLISION_RULES = 15232; // 8 -const static uint64_t SH_FLD_WRTO_AMO_COLLISION_RULES_LEN = 15233; // 8 -const static uint64_t SH_FLD_WRT_MISC_REGISTER_PARITY_ERROR = 15234; // 8 -const static uint64_t SH_FLD_WRT_RST_INTRPT_FACES = 15235; // 1 -const static uint64_t SH_FLD_WRT_RST_INTRPT_PIB = 15236; // 1 -const static uint64_t SH_FLD_WRT_SCOM_SEQUENCE_ERROR = 15237; // 8 -const static uint64_t SH_FLD_WR_BUFFER_STATUS = 15238; // 2 -const static uint64_t SH_FLD_WR_BUFFER_STATUS_LEN = 15239; // 2 -const static uint64_t SH_FLD_WR_BYTE_COUNT = 15240; // 2 -const static uint64_t SH_FLD_WR_BYTE_COUNT_LEN = 15241; // 2 -const static uint64_t SH_FLD_WR_CNTL = 15242; // 8 -const static uint64_t SH_FLD_WR_CNTL_MASK = 15243; // 8 -const static uint64_t SH_FLD_WR_DATA_PARITY_ERROR = 15244; // 3 -const static uint64_t SH_FLD_WR_EPSILON_VALUE = 15245; // 2 -const static uint64_t SH_FLD_WR_EPSILON_VALUE_LEN = 15246; // 2 -const static uint64_t SH_FLD_WR_FIFO_STAB = 15247; // 8 -const static uint64_t SH_FLD_WR_GATHER_TIMEOUT = 15248; // 4 -const static uint64_t SH_FLD_WR_GATHER_TIMEOUT_LEN = 15249; // 4 -const static uint64_t SH_FLD_WR_LEVEL = 15250; // 8 -const static uint64_t SH_FLD_WR_MON_NOT_DISABLED_ERR = 15251; // 2 -const static uint64_t SH_FLD_WR_PAR_ERR = 15252; // 8 -const static uint64_t SH_FLD_WR_PAR_ERR_MASK = 15253; // 8 -const static uint64_t SH_FLD_WR_PRE_DLY = 15254; // 8 -const static uint64_t SH_FLD_WR_PRE_DLY_LEN = 15255; // 8 -const static uint64_t SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT = 15256; // 8 -const static uint64_t SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN = 15257; // 8 -const static uint64_t SH_FLD_WR_RSVD_UPPER_LIMIT = 15258; // 8 -const static uint64_t SH_FLD_WR_RSVD_UPPER_LIMIT_LEN = 15259; // 8 -const static uint64_t SH_FLD_WR_SCOPE = 15260; // 24 -const static uint64_t SH_FLD_WR_SLVNUM = 15261; // 2 -const static uint64_t SH_FLD_WR_SLVNUM_LEN = 15262; // 2 -const static uint64_t SH_FLD_WR_SPLIT_UT0_ENA = 15263; // 6 -const static uint64_t SH_FLD_WR_SPLIT_UT1_ENA = 15264; // 6 -const static uint64_t SH_FLD_WR_VALID = 15265; // 1 -const static uint64_t SH_FLD_WSIZE = 15266; // 1 -const static uint64_t SH_FLD_WSIZE_LEN = 15267; // 1 -const static uint64_t SH_FLD_WT4CR_TIER0_EPS_VAL = 15268; // 12 -const static uint64_t SH_FLD_WT4CR_TIER0_EPS_VAL_LEN = 15269; // 12 -const static uint64_t SH_FLD_WT4CR_TIER1_EPS_VAL = 15270; // 24 -const static uint64_t SH_FLD_WT4CR_TIER1_EPS_VAL_LEN = 15271; // 24 -const static uint64_t SH_FLD_WT4CR_TIER2_EPS_VAL = 15272; // 24 -const static uint64_t SH_FLD_WT4CR_TIER2_EPS_VAL_LEN = 15273; // 24 -const static uint64_t SH_FLD_WTL_SM_STATUS = 15274; // 4 -const static uint64_t SH_FLD_WTL_SM_STATUS_LEN = 15275; // 4 -const static uint64_t SH_FLD_WTL_TEST_CLOCK = 15276; // 4 -const static uint64_t SH_FLD_WTL_TEST_DATA = 15277; // 4 -const static uint64_t SH_FLD_WTR_MAX_BAD_LANES = 15278; // 4 -const static uint64_t SH_FLD_WTR_MAX_BAD_LANES_LEN = 15279; // 4 -const static uint64_t SH_FLD_WT_ALL_DONE_GCRMSG = 15280; // 4 -const static uint64_t SH_FLD_WT_BS_CLOCK_EN_BYP = 15281; // 4 -const static uint64_t SH_FLD_WT_BS_DATA_EN_BYP = 15282; // 4 -const static uint64_t SH_FLD_WT_CHECK_COUNT = 15283; // 4 -const static uint64_t SH_FLD_WT_CHECK_COUNT_LEN = 15284; // 4 -const static uint64_t SH_FLD_WT_CLK_LANE_BAD_CODE = 15285; // 4 -const static uint64_t SH_FLD_WT_CLK_LANE_BAD_CODE_LEN = 15286; // 4 -const static uint64_t SH_FLD_WT_CLK_LANE_INVERTED = 15287; // 4 -const static uint64_t SH_FLD_WT_CU_BYP_PLL_LOCK = 15288; // 4 -const static uint64_t SH_FLD_WT_CU_PLL_PGOOD = 15289; // 4 -const static uint64_t SH_FLD_WT_CU_PLL_PGOODDLY = 15290; // 4 -const static uint64_t SH_FLD_WT_CU_PLL_PGOODDLY_LEN = 15291; // 4 -const static uint64_t SH_FLD_WT_CU_PLL_RESET = 15292; // 4 -const static uint64_t SH_FLD_WT_EN_ALL_CLK_SEGS_GCRMSG = 15293; // 4 -const static uint64_t SH_FLD_WT_EN_ALL_DATA_SEGS_GCRMSG = 15294; // 4 -const static uint64_t SH_FLD_WT_LANE_BAD_CODE = 15295; // 96 -const static uint64_t SH_FLD_WT_LANE_BAD_CODE_LEN = 15296; // 96 -const static uint64_t SH_FLD_WT_LANE_DISABLED = 15297; // 96 -const static uint64_t SH_FLD_WT_PATTERN_LENGTH = 15298; // 8 -const static uint64_t SH_FLD_WT_PATTERN_LENGTH_LEN = 15299; // 8 -const static uint64_t SH_FLD_WT_PLL_REFCLKSEL = 15300; // 4 -const static uint64_t SH_FLD_WT_PREV_DONE_GCRMSG = 15301; // 4 -const static uint64_t SH_FLD_WT_TIMEOUT_SEL = 15302; // 4 -const static uint64_t SH_FLD_WT_TIMEOUT_SEL_LEN = 15303; // 4 -const static uint64_t SH_FLD_WWDM_DLY = 15304; // 8 -const static uint64_t SH_FLD_WWDM_DLY_LEN = 15305; // 8 -const static uint64_t SH_FLD_WWOP_DLY = 15306; // 8 -const static uint64_t SH_FLD_WWOP_DLY_LEN = 15307; // 8 -const static uint64_t SH_FLD_WWSMDR_DLY = 15308; // 8 -const static uint64_t SH_FLD_WWSMDR_DLY_LEN = 15309; // 8 -const static uint64_t SH_FLD_WWSMSR_DLY = 15310; // 8 -const static uint64_t SH_FLD_WWSMSR_DLY_LEN = 15311; // 8 -const static uint64_t SH_FLD_X0_ACT = 15312; // 1 -const static uint64_t SH_FLD_X0_TX_ENABLE = 15313; // 4 -const static uint64_t SH_FLD_X0_TX_SELECT = 15314; // 4 -const static uint64_t SH_FLD_X0_TX_SELECT_LEN = 15315; // 4 -const static uint64_t SH_FLD_X1_ACT = 15316; // 1 -const static uint64_t SH_FLD_X1_TX_ENABLE = 15317; // 4 -const static uint64_t SH_FLD_X1_TX_SELECT = 15318; // 4 -const static uint64_t SH_FLD_X1_TX_SELECT_LEN = 15319; // 4 -const static uint64_t SH_FLD_X2_ACT = 15320; // 1 -const static uint64_t SH_FLD_X2_TX_ENABLE = 15321; // 4 -const static uint64_t SH_FLD_X2_TX_SELECT = 15322; // 4 -const static uint64_t SH_FLD_X2_TX_SELECT_LEN = 15323; // 4 -const static uint64_t SH_FLD_X3_TX_ENABLE = 15324; // 4 -const static uint64_t SH_FLD_X3_TX_SELECT = 15325; // 4 -const static uint64_t SH_FLD_X3_TX_SELECT_LEN = 15326; // 4 -const static uint64_t SH_FLD_X4_TX_ENABLE = 15327; // 4 -const static uint64_t SH_FLD_X4_TX_SELECT = 15328; // 4 -const static uint64_t SH_FLD_X4_TX_SELECT_LEN = 15329; // 4 -const static uint64_t SH_FLD_X5_TX_ENABLE = 15330; // 4 -const static uint64_t SH_FLD_X5_TX_SELECT = 15331; // 4 -const static uint64_t SH_FLD_X5_TX_SELECT_LEN = 15332; // 4 -const static uint64_t SH_FLD_X6_TX_ENABLE = 15333; // 4 -const static uint64_t SH_FLD_X6_TX_SELECT = 15334; // 4 -const static uint64_t SH_FLD_X6_TX_SELECT_LEN = 15335; // 4 -const static uint64_t SH_FLD_X7_TX_ENABLE = 15336; // 4 -const static uint64_t SH_FLD_X7_TX_SELECT = 15337; // 4 -const static uint64_t SH_FLD_X7_TX_SELECT_LEN = 15338; // 4 -const static uint64_t SH_FLD_XCR = 15339; // 21 -const static uint64_t SH_FLD_XCR_LEN = 15340; // 21 -const static uint64_t SH_FLD_XIMEM_MEM_IFETCH_PENDING = 15341; // 21 -const static uint64_t SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 15342; // 21 -const static uint64_t SH_FLD_XIRAMGA_IR = 15343; // 21 -const static uint64_t SH_FLD_XIRAMGA_IR_LEN = 15344; // 21 -const static uint64_t SH_FLD_XIRAMRA_SPRG0 = 15345; // 42 -const static uint64_t SH_FLD_XIRAMRA_SPRG0_LEN = 15346; // 42 -const static uint64_t SH_FLD_XISIB_PIB_IFETCH_PENDING = 15347; // 21 -const static uint64_t SH_FLD_XIXCR_XCR = 15348; // 21 -const static uint64_t SH_FLD_XIXCR_XCR_LEN = 15349; // 21 -const static uint64_t SH_FLD_XLAT = 15350; // 16 -const static uint64_t SH_FLD_XLATE_TO_ADDR_ID_ENABLE = 15351; // 2 -const static uint64_t SH_FLD_XLAT_LEN = 15352; // 16 -const static uint64_t SH_FLD_XPT_POWERBUS_CE = 15353; // 4 -const static uint64_t SH_FLD_XPT_POWERBUS_SUE = 15354; // 4 -const static uint64_t SH_FLD_XPT_POWERBUS_UE = 15355; // 4 -const static uint64_t SH_FLD_XPT_RECOVERABLE_ERROR = 15356; // 4 -const static uint64_t SH_FLD_XPT_SYS_XSTOP_ERROR = 15357; // 4 -const static uint64_t SH_FLD_XSCOM_DONE = 15358; // 96 -const static uint64_t SH_FLD_XSCOM_FAIL = 15359; // 96 -const static uint64_t SH_FLD_XSCOM_STATUS = 15360; // 96 -const static uint64_t SH_FLD_XSCOM_STATUS_LEN = 15361; // 96 -const static uint64_t SH_FLD_XSC_CMD_OVERRUN = 15362; // 1 -const static uint64_t SH_FLD_XSTOP = 15363; // 5 -const static uint64_t SH_FLD_XSTOP_GATE = 15364; // 1 -const static uint64_t SH_FLD_XTS_CONFIG_P = 15365; // 1 -const static uint64_t SH_FLD_XTS_INT = 15366; // 1 -const static uint64_t SH_FLD_XTS_PBUS_PROTOCOL = 15367; // 1 -const static uint64_t SH_FLD_XTS_PROTOCOL_CE = 15368; // 1 -const static uint64_t SH_FLD_XTS_PROTOCOL_UE = 15369; // 1 -const static uint64_t SH_FLD_XTS_SRAM_CE = 15370; // 1 -const static uint64_t SH_FLD_XTS_SRAM_UE = 15371; // 1 -const static uint64_t SH_FLD_Z = 15372; // 1 -const static uint64_t SH_FLD_ZCAL = 15373; // 4 -const static uint64_t SH_FLD_ZCAL_CYA_DATA_INV = 15374; // 4 -const static uint64_t SH_FLD_ZCAL_LEN = 15375; // 4 -const static uint64_t SH_FLD_ZCAL_N = 15376; // 4 -const static uint64_t SH_FLD_ZCAL_NOT_CONT = 15377; // 8 -const static uint64_t SH_FLD_ZCAL_N_LEN = 15378; // 4 -const static uint64_t SH_FLD_ZCAL_P = 15379; // 4 -const static uint64_t SH_FLD_ZCAL_P_LEN = 15380; // 4 -const static uint64_t SH_FLD_ZCAL_RANGE_CHECK = 15381; // 4 -const static uint64_t SH_FLD_ZCAL_SM_MAX_VAL = 15382; // 4 -const static uint64_t SH_FLD_ZCAL_SM_MAX_VAL_LEN = 15383; // 4 -const static uint64_t SH_FLD_ZCAL_SM_MIN_VAL = 15384; // 4 -const static uint64_t SH_FLD_ZCAL_SM_MIN_VAL_LEN = 15385; // 4 -const static uint64_t SH_FLD_ZCAL_SWO_CAL_SEGS = 15386; // 4 -const static uint64_t SH_FLD_ZCAL_SWO_CMP_INV = 15387; // 4 -const static uint64_t SH_FLD_ZCAL_SWO_CMP_OFFSET = 15388; // 4 -const static uint64_t SH_FLD_ZCAL_SWO_CMP_RESET = 15389; // 4 -const static uint64_t SH_FLD_ZCAL_SWO_EN = 15390; // 4 -const static uint64_t SH_FLD_ZCAL_SWO_POWERDOWN = 15391; // 4 -const static uint64_t SH_FLD_ZCAL_SWO_TCOIL = 15392; // 4 -const static uint64_t SH_FLD_ZCAL_TEST_CLK_DIV = 15393; // 4 -const static uint64_t SH_FLD_ZCAL_TEST_OVR_1R = 15394; // 4 -const static uint64_t SH_FLD_ZCAL_TEST_OVR_2R = 15395; // 4 -const static uint64_t SH_FLD_ZCAL_TEST_OVR_4X_SEG = 15396; // 4 +const static uint64_t SH_FLD_01_ATEST_SEL_0 = 12; // 8 +const static uint64_t SH_FLD_01_ATEST_SEL_0_LEN = 13; // 8 +const static uint64_t SH_FLD_01_ATEST_SEL_1 = 14; // 8 +const static uint64_t SH_FLD_01_ATEST_SEL_1_LEN = 15; // 8 +const static uint64_t SH_FLD_01_BB_LOCK0 = 16; // 16 +const static uint64_t SH_FLD_01_BB_LOCK1 = 17; // 16 +const static uint64_t SH_FLD_01_BIG_STEP_RIGHT = 18; // 16 +const static uint64_t SH_FLD_01_BIT_CENTERED = 19; // 16 +const static uint64_t SH_FLD_01_BIT_CENTERED_LEN = 20; // 16 +const static uint64_t SH_FLD_01_BLFIFO_DIS = 21; // 16 +const static uint64_t SH_FLD_01_BUMP = 22; // 16 +const static uint64_t SH_FLD_01_CALGATE_ON = 23; // 16 +const static uint64_t SH_FLD_01_CALIBRATE_BIT = 24; // 16 +const static uint64_t SH_FLD_01_CALIBRATE_BIT_LEN = 25; // 16 +const static uint64_t SH_FLD_01_CAL_CKTS_ACTIVE = 26; // 32 +const static uint64_t SH_FLD_01_CAL_ERROR = 27; // 32 +const static uint64_t SH_FLD_01_CAL_ERROR_FINE = 28; // 32 +const static uint64_t SH_FLD_01_CAL_GOOD = 29; // 32 +const static uint64_t SH_FLD_01_CHECKER_ENABLE = 30; // 16 +const static uint64_t SH_FLD_01_CHECKER_RESET = 31; // 16 +const static uint64_t SH_FLD_01_CLK16_SINGLE_ENDED = 32; // 128 +const static uint64_t SH_FLD_01_CLK18_SINGLE_ENDED = 33; // 128 +const static uint64_t SH_FLD_01_CLK20_SINGLE_ENDED = 34; // 128 +const static uint64_t SH_FLD_01_CLK22_SINGLE_ENDED = 35; // 128 +const static uint64_t SH_FLD_01_CLK_LEVEL = 36; // 16 +const static uint64_t SH_FLD_01_CLK_LEVEL_LEN = 37; // 16 +const static uint64_t SH_FLD_01_CNTL_POL = 38; // 16 +const static uint64_t SH_FLD_01_CNTL_SRC = 39; // 16 +const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N0 = 40; // 16 +const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N0_MASK = 41; // 16 +const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N1 = 42; // 16 +const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N1_MASK = 43; // 16 +const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N2 = 44; // 16 +const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N2_MASK = 45; // 16 +const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N3 = 46; // 16 +const static uint64_t SH_FLD_01_COARSE_PATTERN_ERR_N3_MASK = 47; // 16 +const static uint64_t SH_FLD_01_CONTINUOUS_UPDATE = 48; // 32 +const static uint64_t SH_FLD_01_CTR_1D_CHICKEN_SWITCH = 49; // 16 +const static uint64_t SH_FLD_01_CTR_2D_SMALL_STEP_VAL = 50; // 16 +const static uint64_t SH_FLD_01_CTR_2D_SMALL_STEP_VAL_LEN = 51; // 16 +const static uint64_t SH_FLD_01_CTR_3D_BIG_STEP_VAL = 52; // 16 +const static uint64_t SH_FLD_01_CTR_3D_BIG_STEP_VAL_LEN = 53; // 16 +const static uint64_t SH_FLD_01_CTR_CUR = 54; // 16 +const static uint64_t SH_FLD_01_CTR_CUR_LEN = 55; // 16 +const static uint64_t SH_FLD_01_CTR_NUM_BITS_TO_SKIP = 56; // 16 +const static uint64_t SH_FLD_01_CTR_NUM_BITS_TO_SKIP_LEN = 57; // 16 +const static uint64_t SH_FLD_01_CTR_NUM_NO_INC_COMP = 58; // 16 +const static uint64_t SH_FLD_01_CTR_NUM_NO_INC_COMP_LEN = 59; // 16 +const static uint64_t SH_FLD_01_CTR_NUM_VREFREQ_CNT = 60; // 16 +const static uint64_t SH_FLD_01_CTR_NUM_VREFREQ_CNT_LEN = 61; // 16 +const static uint64_t SH_FLD_01_CTR_NUM_WRRDREQ_CNT = 62; // 16 +const static uint64_t SH_FLD_01_CTR_NUM_WRRDREQ_CNT_LEN = 63; // 16 +const static uint64_t SH_FLD_01_CTR_RANGE_CROSSOVER = 64; // 16 +const static uint64_t SH_FLD_01_CTR_RANGE_CROSSOVER_LEN = 65; // 16 +const static uint64_t SH_FLD_01_CTR_RANGE_SEL = 66; // 64 +const static uint64_t SH_FLD_01_CTR_RANGE_SELECT = 67; // 16 +const static uint64_t SH_FLD_01_CTR_RUN_FULL_1D = 68; // 16 +const static uint64_t SH_FLD_01_CTR_SINGLE_RANGE_MAX = 69; // 16 +const static uint64_t SH_FLD_01_CTR_SINGLE_RANGE_MAX_LEN = 70; // 16 +const static uint64_t SH_FLD_01_DD2_DQS_FIX_DIS = 71; // 16 +const static uint64_t SH_FLD_01_DD2_FIX_DIS = 72; // 16 +const static uint64_t SH_FLD_01_DD2_WTRFL_SYNC_DIS = 73; // 16 +const static uint64_t SH_FLD_01_DELAY1 = 74; // 16 +const static uint64_t SH_FLD_01_DELAY10 = 75; // 16 +const static uint64_t SH_FLD_01_DELAY10_LEN = 76; // 16 +const static uint64_t SH_FLD_01_DELAY11 = 77; // 16 +const static uint64_t SH_FLD_01_DELAY11_LEN = 78; // 16 +const static uint64_t SH_FLD_01_DELAY12 = 79; // 16 +const static uint64_t SH_FLD_01_DELAY12_LEN = 80; // 16 +const static uint64_t SH_FLD_01_DELAY13 = 81; // 16 +const static uint64_t SH_FLD_01_DELAY13_LEN = 82; // 16 +const static uint64_t SH_FLD_01_DELAY14 = 83; // 16 +const static uint64_t SH_FLD_01_DELAY14_LEN = 84; // 16 +const static uint64_t SH_FLD_01_DELAY15 = 85; // 16 +const static uint64_t SH_FLD_01_DELAY15_LEN = 86; // 16 +const static uint64_t SH_FLD_01_DELAY1_LEN = 87; // 16 +const static uint64_t SH_FLD_01_DELAY2 = 88; // 16 +const static uint64_t SH_FLD_01_DELAY2_LEN = 89; // 16 +const static uint64_t SH_FLD_01_DELAY3 = 90; // 16 +const static uint64_t SH_FLD_01_DELAY3_LEN = 91; // 16 +const static uint64_t SH_FLD_01_DELAY4 = 92; // 16 +const static uint64_t SH_FLD_01_DELAY4_LEN = 93; // 16 +const static uint64_t SH_FLD_01_DELAY5 = 94; // 16 +const static uint64_t SH_FLD_01_DELAY5_LEN = 95; // 16 +const static uint64_t SH_FLD_01_DELAY6 = 96; // 16 +const static uint64_t SH_FLD_01_DELAY6_LEN = 97; // 16 +const static uint64_t SH_FLD_01_DELAY7 = 98; // 16 +const static uint64_t SH_FLD_01_DELAY7_LEN = 99; // 16 +const static uint64_t SH_FLD_01_DELAY8 = 100; // 16 +const static uint64_t SH_FLD_01_DELAY8_LEN = 101; // 16 +const static uint64_t SH_FLD_01_DELAY9 = 102; // 16 +const static uint64_t SH_FLD_01_DELAY9_LEN = 103; // 16 +const static uint64_t SH_FLD_01_DELAYG = 104; // 1280 +const static uint64_t SH_FLD_01_DELAYG_LEN = 105; // 1280 +const static uint64_t SH_FLD_01_DELAY_PING_PONG_HALF = 106; // 16 +const static uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH = 107; // 16 +const static uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 108; // 16 +const static uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW = 109; // 16 +const static uint64_t SH_FLD_01_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 110; // 16 +const static uint64_t SH_FLD_01_DFT_FORCE_OUTPUTS = 111; // 16 +const static uint64_t SH_FLD_01_DFT_PRBS7_GEN_EN = 112; // 16 +const static uint64_t SH_FLD_01_DIGITAL_EN = 113; // 16 +const static uint64_t SH_FLD_01_DIR_0_15 = 114; // 8 +const static uint64_t SH_FLD_01_DIR_0_15_LEN = 115; // 8 +const static uint64_t SH_FLD_01_DIR_15 = 116; // 8 +const static uint64_t SH_FLD_01_DIR_15_LEN = 117; // 8 +const static uint64_t SH_FLD_01_DISABLE_0_15 = 118; // 32 +const static uint64_t SH_FLD_01_DISABLE_0_15_LEN = 119; // 32 +const static uint64_t SH_FLD_01_DISABLE_15 = 120; // 32 +const static uint64_t SH_FLD_01_DISABLE_15_LEN = 121; // 32 +const static uint64_t SH_FLD_01_DISABLE_16_23 = 122; // 64 +const static uint64_t SH_FLD_01_DISABLE_16_23_LEN = 123; // 64 +const static uint64_t SH_FLD_01_DISABLE_PING_PONG = 124; // 16 +const static uint64_t SH_FLD_01_DISABLE_TERMINATION = 125; // 16 +const static uint64_t SH_FLD_01_DIS_CLK_GATE = 126; // 16 +const static uint64_t SH_FLD_01_DI_ADR0 = 127; // 8 +const static uint64_t SH_FLD_01_DI_ADR1 = 128; // 8 +const static uint64_t SH_FLD_01_DI_ADR10_ADR11 = 129; // 16 +const static uint64_t SH_FLD_01_DI_ADR12_ADR13 = 130; // 16 +const static uint64_t SH_FLD_01_DI_ADR14_ADR15 = 131; // 16 +const static uint64_t SH_FLD_01_DI_ADR2_ADR3 = 132; // 16 +const static uint64_t SH_FLD_01_DI_ADR4_ADR5 = 133; // 16 +const static uint64_t SH_FLD_01_DI_ADR6_ADR7 = 134; // 16 +const static uint64_t SH_FLD_01_DI_ADR8_ADR9 = 135; // 16 +const static uint64_t SH_FLD_01_DLL_ADJUST = 136; // 32 +const static uint64_t SH_FLD_01_DLL_ADJUST_LEN = 137; // 32 +const static uint64_t SH_FLD_01_DLL_COMPARE_OUT = 138; // 32 +const static uint64_t SH_FLD_01_DLL_CORRECT_EN = 139; // 32 +const static uint64_t SH_FLD_01_DLL_ITER_A = 140; // 32 +const static uint64_t SH_FLD_01_DL_FORCE_ON = 141; // 16 +const static uint64_t SH_FLD_01_DONE = 142; // 32 +const static uint64_t SH_FLD_01_DQS = 143; // 16 +const static uint64_t SH_FLD_01_DQSCLK_SELECT0 = 144; // 64 +const static uint64_t SH_FLD_01_DQSCLK_SELECT0_LEN = 145; // 64 +const static uint64_t SH_FLD_01_DQSCLK_SELECT1 = 146; // 64 +const static uint64_t SH_FLD_01_DQSCLK_SELECT1_LEN = 147; // 64 +const static uint64_t SH_FLD_01_DQSCLK_SELECT2 = 148; // 64 +const static uint64_t SH_FLD_01_DQSCLK_SELECT2_LEN = 149; // 64 +const static uint64_t SH_FLD_01_DQSCLK_SELECT3 = 150; // 64 +const static uint64_t SH_FLD_01_DQSCLK_SELECT3_LEN = 151; // 64 +const static uint64_t SH_FLD_01_DQS_ALIGN_CNTR = 152; // 16 +const static uint64_t SH_FLD_01_DQS_ALIGN_CNTR_LEN = 153; // 16 +const static uint64_t SH_FLD_01_DQS_ALIGN_FIX_DIS = 154; // 16 +const static uint64_t SH_FLD_01_DQS_ALIGN_JITTER = 155; // 16 +const static uint64_t SH_FLD_01_DQS_ALIGN_QUAD = 156; // 16 +const static uint64_t SH_FLD_01_DQS_ALIGN_QUAD_LEN = 157; // 16 +const static uint64_t SH_FLD_01_DQS_ALIGN_SM = 158; // 16 +const static uint64_t SH_FLD_01_DQS_ALIGN_SM_LEN = 159; // 16 +const static uint64_t SH_FLD_01_DQS_LEN = 160; // 16 +const static uint64_t SH_FLD_01_DQS_PIPE_FIX_DIS = 161; // 16 +const static uint64_t SH_FLD_01_DQS_PIPE_FIX_DIS_LEN = 162; // 16 +const static uint64_t SH_FLD_01_DQS_QUAD_CONFIG = 163; // 16 +const static uint64_t SH_FLD_01_DQS_QUAD_CONFIG_LEN = 164; // 16 +const static uint64_t SH_FLD_01_DRIFT_ERROR = 165; // 16 +const static uint64_t SH_FLD_01_DRIFT_MASK = 166; // 16 +const static uint64_t SH_FLD_01_DRVREN_MODE = 167; // 32 +const static uint64_t SH_FLD_01_DYN_MCTERM_CNTL_EN = 168; // 16 +const static uint64_t SH_FLD_01_DYN_POWER_CNTL_EN = 169; // 16 +const static uint64_t SH_FLD_01_DYN_RX_GATE_CNTL_EN = 170; // 16 +const static uint64_t SH_FLD_01_ENABLE_0_15 = 171; // 8 +const static uint64_t SH_FLD_01_ENABLE_0_15_LEN = 172; // 8 +const static uint64_t SH_FLD_01_ENABLE_15 = 173; // 8 +const static uint64_t SH_FLD_01_ENABLE_15_LEN = 174; // 8 +const static uint64_t SH_FLD_01_ENABLE_16_23 = 175; // 16 +const static uint64_t SH_FLD_01_ENABLE_16_23_LEN = 176; // 16 +const static uint64_t SH_FLD_01_EN_DQS_OFFSET = 177; // 16 +const static uint64_t SH_FLD_01_EN_DRIVER_INVFB_DC = 178; // 32 +const static uint64_t SH_FLD_01_EN_N_WR = 179; // 16 +const static uint64_t SH_FLD_01_EN_N_WR_LEN = 180; // 16 +const static uint64_t SH_FLD_01_EN_P_WR = 181; // 32 +const static uint64_t SH_FLD_01_EN_P_WR_LEN = 182; // 32 +const static uint64_t SH_FLD_01_ERROR = 183; // 16 +const static uint64_t SH_FLD_01_ERROR_LEN = 184; // 16 +const static uint64_t SH_FLD_01_ERR_CLK22_MASK = 185; // 16 +const static uint64_t SH_FLD_01_EYE_CLIPPING = 186; // 16 +const static uint64_t SH_FLD_01_EYE_CLIPPING_MASK = 187; // 16 +const static uint64_t SH_FLD_01_FINE_STEPPING = 188; // 16 +const static uint64_t SH_FLD_01_FLUSH = 189; // 16 +const static uint64_t SH_FLD_01_FORCE_DQS_LANES_ON = 190; // 16 +const static uint64_t SH_FLD_01_FORCE_FIFO_CAPTURE = 191; // 16 +const static uint64_t SH_FLD_01_FRZSULV = 192; // 32 +const static uint64_t SH_FLD_01_FW_LEFT_SIDE = 193; // 16 +const static uint64_t SH_FLD_01_FW_LEFT_SIDE_LEN = 194; // 16 +const static uint64_t SH_FLD_01_FW_RIGHT_SIDE = 195; // 16 +const static uint64_t SH_FLD_01_FW_RIGHT_SIDE_LEN = 196; // 16 +const static uint64_t SH_FLD_01_HS_DLLMUX_SEL_0_0_3 = 197; // 8 +const static uint64_t SH_FLD_01_HS_DLLMUX_SEL_0_0_3_LEN = 198; // 8 +const static uint64_t SH_FLD_01_HS_DLLMUX_SEL_0_3 = 199; // 16 +const static uint64_t SH_FLD_01_HS_DLLMUX_SEL_0_3_LEN = 200; // 16 +const static uint64_t SH_FLD_01_HS_DLLMUX_SEL_1_3 = 201; // 8 +const static uint64_t SH_FLD_01_HS_DLLMUX_SEL_1_3_LEN = 202; // 8 +const static uint64_t SH_FLD_01_HS_PROBE_A = 203; // 16 +const static uint64_t SH_FLD_01_HS_PROBE_A_LEN = 204; // 16 +const static uint64_t SH_FLD_01_HS_PROBE_B = 205; // 16 +const static uint64_t SH_FLD_01_HS_PROBE_B_LEN = 206; // 16 +const static uint64_t SH_FLD_01_HW_VALUE = 207; // 16 +const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N0 = 208; // 16 +const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N0_MASK = 209; // 16 +const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N1 = 210; // 16 +const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N1_MASK = 211; // 16 +const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N2 = 212; // 16 +const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N2_MASK = 213; // 16 +const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N3 = 214; // 16 +const static uint64_t SH_FLD_01_INCOMPLETE_CAL_N3_MASK = 215; // 16 +const static uint64_t SH_FLD_01_INIT_IO = 216; // 16 +const static uint64_t SH_FLD_01_INIT_RXDLL_CAL_RESET = 217; // 32 +const static uint64_t SH_FLD_01_INIT_RXDLL_CAL_UPDATE = 218; // 32 +const static uint64_t SH_FLD_01_INTERP_SIG_SLEW = 219; // 16 +const static uint64_t SH_FLD_01_INTERP_SIG_SLEW_LEN = 220; // 16 +const static uint64_t SH_FLD_01_INVALID_NS_BIG_R = 221; // 16 +const static uint64_t SH_FLD_01_INVALID_NS_BIG_R_MASK = 222; // 16 +const static uint64_t SH_FLD_01_INVALID_NS_SMALL_L = 223; // 16 +const static uint64_t SH_FLD_01_INVALID_NS_SMALL_L_MASK = 224; // 16 +const static uint64_t SH_FLD_01_INVALID_NS_SMALL_R = 225; // 16 +const static uint64_t SH_FLD_01_INVALID_NS_SMALL_R_MASK = 226; // 16 +const static uint64_t SH_FLD_01_ITERATION_CNTR = 227; // 16 +const static uint64_t SH_FLD_01_ITERATION_CNTR_LEN = 228; // 16 +const static uint64_t SH_FLD_01_JUMP_BACK_RIGHT = 229; // 16 +const static uint64_t SH_FLD_01_LANE__0_11_PD = 230; // 16 +const static uint64_t SH_FLD_01_LANE__0_11_PD_LEN = 231; // 16 +const static uint64_t SH_FLD_01_LANE__12_15_PD = 232; // 16 +const static uint64_t SH_FLD_01_LANE__12_15_PD_LEN = 233; // 16 +const static uint64_t SH_FLD_01_LEADING_EDGE_FOUND_MASK = 234; // 16 +const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND = 235; // 16 +const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_0_15 = 236; // 8 +const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_0_15_LEN = 237; // 8 +const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_15 = 238; // 8 +const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_15_LEN = 239; // 8 +const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23 = 240; // 16 +const static uint64_t SH_FLD_01_LEADING_EDGE_NOT_FOUND_16_23_LEN = 241; // 16 +const static uint64_t SH_FLD_01_LEN = 242; // 112 +const static uint64_t SH_FLD_01_LOOPBACK_DLY12 = 243; // 16 +const static uint64_t SH_FLD_01_LOOPBACK_FIX_EN = 244; // 16 +const static uint64_t SH_FLD_01_MATCH_STEP_RIGHT = 245; // 16 +const static uint64_t SH_FLD_01_MAX_DQS = 246; // 16 +const static uint64_t SH_FLD_01_MAX_DQS_ITER = 247; // 16 +const static uint64_t SH_FLD_01_MAX_DQS_LEN = 248; // 16 +const static uint64_t SH_FLD_01_MEMINTD00 = 249; // 16 +const static uint64_t SH_FLD_01_MEMINTD00_LEN = 250; // 16 +const static uint64_t SH_FLD_01_MEMINTD01 = 251; // 16 +const static uint64_t SH_FLD_01_MEMINTD01_LEN = 252; // 16 +const static uint64_t SH_FLD_01_MEMINTD02 = 253; // 16 +const static uint64_t SH_FLD_01_MEMINTD02_LEN = 254; // 16 +const static uint64_t SH_FLD_01_MEMINTD03 = 255; // 16 +const static uint64_t SH_FLD_01_MEMINTD03_LEN = 256; // 16 +const static uint64_t SH_FLD_01_MEMINTD04 = 257; // 16 +const static uint64_t SH_FLD_01_MEMINTD04_LEN = 258; // 16 +const static uint64_t SH_FLD_01_MEMINTD05 = 259; // 16 +const static uint64_t SH_FLD_01_MEMINTD05_LEN = 260; // 16 +const static uint64_t SH_FLD_01_MEMINTD06 = 261; // 16 +const static uint64_t SH_FLD_01_MEMINTD06_LEN = 262; // 16 +const static uint64_t SH_FLD_01_MEMINTD07 = 263; // 16 +const static uint64_t SH_FLD_01_MEMINTD07_LEN = 264; // 16 +const static uint64_t SH_FLD_01_MEMINTD08 = 265; // 16 +const static uint64_t SH_FLD_01_MEMINTD08_LEN = 266; // 16 +const static uint64_t SH_FLD_01_MEMINTD09 = 267; // 16 +const static uint64_t SH_FLD_01_MEMINTD09_LEN = 268; // 16 +const static uint64_t SH_FLD_01_MEMINTD10 = 269; // 16 +const static uint64_t SH_FLD_01_MEMINTD10_LEN = 270; // 16 +const static uint64_t SH_FLD_01_MEMINTD11 = 271; // 16 +const static uint64_t SH_FLD_01_MEMINTD11_LEN = 272; // 16 +const static uint64_t SH_FLD_01_MEMINTD12 = 273; // 16 +const static uint64_t SH_FLD_01_MEMINTD12_LEN = 274; // 16 +const static uint64_t SH_FLD_01_MEMINTD13 = 275; // 16 +const static uint64_t SH_FLD_01_MEMINTD13_LEN = 276; // 16 +const static uint64_t SH_FLD_01_MEMINTD14 = 277; // 16 +const static uint64_t SH_FLD_01_MEMINTD14_LEN = 278; // 16 +const static uint64_t SH_FLD_01_MEMINTD15 = 279; // 16 +const static uint64_t SH_FLD_01_MEMINTD15_LEN = 280; // 16 +const static uint64_t SH_FLD_01_MEMINTD16 = 281; // 16 +const static uint64_t SH_FLD_01_MEMINTD16_LEN = 282; // 16 +const static uint64_t SH_FLD_01_MEMINTD17 = 283; // 16 +const static uint64_t SH_FLD_01_MEMINTD17_LEN = 284; // 16 +const static uint64_t SH_FLD_01_MEMINTD18 = 285; // 16 +const static uint64_t SH_FLD_01_MEMINTD18_LEN = 286; // 16 +const static uint64_t SH_FLD_01_MEMINTD19 = 287; // 16 +const static uint64_t SH_FLD_01_MEMINTD19_LEN = 288; // 16 +const static uint64_t SH_FLD_01_MEMINTD20 = 289; // 16 +const static uint64_t SH_FLD_01_MEMINTD20_LEN = 290; // 16 +const static uint64_t SH_FLD_01_MEMINTD21 = 291; // 16 +const static uint64_t SH_FLD_01_MEMINTD21_LEN = 292; // 16 +const static uint64_t SH_FLD_01_MEMINTD22 = 293; // 16 +const static uint64_t SH_FLD_01_MEMINTD22_LEN = 294; // 16 +const static uint64_t SH_FLD_01_MEMINTD23 = 295; // 16 +const static uint64_t SH_FLD_01_MEMINTD23_LEN = 296; // 16 +const static uint64_t SH_FLD_01_MIN_EYE = 297; // 16 +const static uint64_t SH_FLD_01_MIN_EYE_MASK = 298; // 16 +const static uint64_t SH_FLD_01_MIN_RD_EYE_SIZE = 299; // 16 +const static uint64_t SH_FLD_01_MIN_RD_EYE_SIZE_LEN = 300; // 16 +const static uint64_t SH_FLD_01_MRS_CMD_N0 = 301; // 16 +const static uint64_t SH_FLD_01_MRS_CMD_N1 = 302; // 16 +const static uint64_t SH_FLD_01_MRS_CMD_N2 = 303; // 16 +const static uint64_t SH_FLD_01_MRS_CMD_N3 = 304; // 16 +const static uint64_t SH_FLD_01_N0 = 305; // 128 +const static uint64_t SH_FLD_01_N0_LEN = 306; // 128 +const static uint64_t SH_FLD_01_N1 = 307; // 128 +const static uint64_t SH_FLD_01_N1_LEN = 308; // 128 +const static uint64_t SH_FLD_01_N2 = 309; // 128 +const static uint64_t SH_FLD_01_N2_LEN = 310; // 128 +const static uint64_t SH_FLD_01_N3 = 311; // 128 +const static uint64_t SH_FLD_01_N3_LEN = 312; // 128 +const static uint64_t SH_FLD_01_NIB0 = 313; // 16 +const static uint64_t SH_FLD_01_NIB0TCFLIP_DC = 314; // 16 +const static uint64_t SH_FLD_01_NIB0_LEN = 315; // 16 +const static uint64_t SH_FLD_01_NIB1 = 316; // 16 +const static uint64_t SH_FLD_01_NIB1TCFLIP_DC = 317; // 16 +const static uint64_t SH_FLD_01_NIB1_LEN = 318; // 16 +const static uint64_t SH_FLD_01_NIB2 = 319; // 16 +const static uint64_t SH_FLD_01_NIB2TCFLIP_DC = 320; // 16 +const static uint64_t SH_FLD_01_NIB2_LEN = 321; // 16 +const static uint64_t SH_FLD_01_NIB3 = 322; // 16 +const static uint64_t SH_FLD_01_NIB3TCFLIP_DC = 323; // 16 +const static uint64_t SH_FLD_01_NIB3_LEN = 324; // 16 +const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_CAP = 325; // 16 +const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_CAP_LEN = 326; // 16 +const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_RES = 327; // 16 +const static uint64_t SH_FLD_01_NIB_0_2_DQSEL_RES_LEN = 328; // 16 +const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_CAP = 329; // 16 +const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_CAP_LEN = 330; // 16 +const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_RES = 331; // 16 +const static uint64_t SH_FLD_01_NIB_1_3_DQSEL_RES_LEN = 332; // 16 +const static uint64_t SH_FLD_01_NIB_2_DQSEL_CAP = 333; // 16 +const static uint64_t SH_FLD_01_NIB_2_DQSEL_CAP_LEN = 334; // 16 +const static uint64_t SH_FLD_01_NIB_2_DQSEL_RES = 335; // 16 +const static uint64_t SH_FLD_01_NIB_2_DQSEL_RES_LEN = 336; // 16 +const static uint64_t SH_FLD_01_NIB_3_DQSEL_CAP = 337; // 16 +const static uint64_t SH_FLD_01_NIB_3_DQSEL_CAP_LEN = 338; // 16 +const static uint64_t SH_FLD_01_NIB_3_DQSEL_RES = 339; // 16 +const static uint64_t SH_FLD_01_NIB_3_DQSEL_RES_LEN = 340; // 16 +const static uint64_t SH_FLD_01_NO_DQS = 341; // 16 +const static uint64_t SH_FLD_01_NO_DQS_MASK = 342; // 16 +const static uint64_t SH_FLD_01_NO_EYE_DETECTED = 343; // 16 +const static uint64_t SH_FLD_01_NO_EYE_DETECTED_MASK = 344; // 16 +const static uint64_t SH_FLD_01_NO_LOCK = 345; // 16 +const static uint64_t SH_FLD_01_NO_LOCK_MASK = 346; // 16 +const static uint64_t SH_FLD_01_OFFSET0 = 347; // 16 +const static uint64_t SH_FLD_01_OFFSET0_LEN = 348; // 16 +const static uint64_t SH_FLD_01_OFFSET1 = 349; // 16 +const static uint64_t SH_FLD_01_OFFSET1_LEN = 350; // 16 +const static uint64_t SH_FLD_01_OFFSET2 = 351; // 32 +const static uint64_t SH_FLD_01_OFFSET2_LEN = 352; // 32 +const static uint64_t SH_FLD_01_OFFSET3 = 353; // 32 +const static uint64_t SH_FLD_01_OFFSET3_LEN = 354; // 32 +const static uint64_t SH_FLD_01_OFFSET4 = 355; // 32 +const static uint64_t SH_FLD_01_OFFSET4_LEN = 356; // 32 +const static uint64_t SH_FLD_01_OFFSET5 = 357; // 32 +const static uint64_t SH_FLD_01_OFFSET5_LEN = 358; // 32 +const static uint64_t SH_FLD_01_OFFSET6 = 359; // 32 +const static uint64_t SH_FLD_01_OFFSET6_LEN = 360; // 32 +const static uint64_t SH_FLD_01_OFFSET7 = 361; // 32 +const static uint64_t SH_FLD_01_OFFSET7_LEN = 362; // 32 +const static uint64_t SH_FLD_01_OFFSET_ERR = 363; // 16 +const static uint64_t SH_FLD_01_OFFSET_ERR_MASK = 364; // 16 +const static uint64_t SH_FLD_01_OPERATE_MODE = 365; // 16 +const static uint64_t SH_FLD_01_OPERATE_MODE_LEN = 366; // 16 +const static uint64_t SH_FLD_01_PERCAL_PWR_DIS = 367; // 16 +const static uint64_t SH_FLD_01_PER_CAL_UPDATE_DISABLE = 368; // 16 +const static uint64_t SH_FLD_01_PHASE_ALIGN_RESET = 369; // 32 +const static uint64_t SH_FLD_01_PHASE_CNTL_EN = 370; // 32 +const static uint64_t SH_FLD_01_PHASE_DEFAULT_EN = 371; // 32 +const static uint64_t SH_FLD_01_POS_EDGE_ALIGN = 372; // 32 +const static uint64_t SH_FLD_01_QUAD0 = 373; // 16 +const static uint64_t SH_FLD_01_QUAD0_CLK16 = 374; // 128 +const static uint64_t SH_FLD_01_QUAD0_CLK18 = 375; // 128 +const static uint64_t SH_FLD_01_QUAD0_LEN = 376; // 16 +const static uint64_t SH_FLD_01_QUAD1 = 377; // 16 +const static uint64_t SH_FLD_01_QUAD1_CLK16 = 378; // 128 +const static uint64_t SH_FLD_01_QUAD1_CLK18 = 379; // 128 +const static uint64_t SH_FLD_01_QUAD1_LEN = 380; // 16 +const static uint64_t SH_FLD_01_QUAD2 = 381; // 16 +const static uint64_t SH_FLD_01_QUAD2_CLK16 = 382; // 128 +const static uint64_t SH_FLD_01_QUAD2_CLK18 = 383; // 64 +const static uint64_t SH_FLD_01_QUAD2_CLK20 = 384; // 128 +const static uint64_t SH_FLD_01_QUAD2_CLK22 = 385; // 128 +const static uint64_t SH_FLD_01_QUAD2_LEN = 386; // 16 +const static uint64_t SH_FLD_01_QUAD3 = 387; // 16 +const static uint64_t SH_FLD_01_QUAD3_CLK16 = 388; // 128 +const static uint64_t SH_FLD_01_QUAD3_CLK18 = 389; // 64 +const static uint64_t SH_FLD_01_QUAD3_CLK20 = 390; // 128 +const static uint64_t SH_FLD_01_QUAD3_CLK22 = 391; // 128 +const static uint64_t SH_FLD_01_QUAD3_LEN = 392; // 16 +const static uint64_t SH_FLD_01_RANGE_DRAM0 = 393; // 64 +const static uint64_t SH_FLD_01_RANGE_DRAM1 = 394; // 64 +const static uint64_t SH_FLD_01_RANGE_DRAM2 = 395; // 64 +const static uint64_t SH_FLD_01_RANGE_DRAM3 = 396; // 64 +const static uint64_t SH_FLD_01_RD = 397; // 272 +const static uint64_t SH_FLD_01_RDCLK_SELECT0 = 398; // 64 +const static uint64_t SH_FLD_01_RDCLK_SELECT0_LEN = 399; // 64 +const static uint64_t SH_FLD_01_RDCLK_SELECT1 = 400; // 64 +const static uint64_t SH_FLD_01_RDCLK_SELECT1_LEN = 401; // 64 +const static uint64_t SH_FLD_01_RDCLK_SELECT2 = 402; // 64 +const static uint64_t SH_FLD_01_RDCLK_SELECT2_LEN = 403; // 64 +const static uint64_t SH_FLD_01_RDCLK_SELECT3 = 404; // 64 +const static uint64_t SH_FLD_01_RDCLK_SELECT3_LEN = 405; // 64 +const static uint64_t SH_FLD_01_RD_DELAY0 = 406; // 112 +const static uint64_t SH_FLD_01_RD_DELAY0_LEN = 407; // 112 +const static uint64_t SH_FLD_01_RD_DELAY1 = 408; // 112 +const static uint64_t SH_FLD_01_RD_DELAY1_LEN = 409; // 112 +const static uint64_t SH_FLD_01_RD_DELAY2 = 410; // 112 +const static uint64_t SH_FLD_01_RD_DELAY2_LEN = 411; // 112 +const static uint64_t SH_FLD_01_RD_DELAY3 = 412; // 112 +const static uint64_t SH_FLD_01_RD_DELAY3_LEN = 413; // 112 +const static uint64_t SH_FLD_01_RD_DELAY4 = 414; // 112 +const static uint64_t SH_FLD_01_RD_DELAY4_LEN = 415; // 112 +const static uint64_t SH_FLD_01_RD_DELAY5 = 416; // 112 +const static uint64_t SH_FLD_01_RD_DELAY5_LEN = 417; // 112 +const static uint64_t SH_FLD_01_RD_DELAY6 = 418; // 112 +const static uint64_t SH_FLD_01_RD_DELAY6_LEN = 419; // 112 +const static uint64_t SH_FLD_01_RD_DELAY7 = 420; // 112 +const static uint64_t SH_FLD_01_RD_DELAY7_LEN = 421; // 112 +const static uint64_t SH_FLD_01_RD_LEN = 422; // 272 +const static uint64_t SH_FLD_01_RD_SIZE0 = 423; // 176 +const static uint64_t SH_FLD_01_RD_SIZE0_LEN = 424; // 176 +const static uint64_t SH_FLD_01_RD_SIZE1 = 425; // 176 +const static uint64_t SH_FLD_01_RD_SIZE1_LEN = 426; // 176 +const static uint64_t SH_FLD_01_RD_SIZE2 = 427; // 176 +const static uint64_t SH_FLD_01_RD_SIZE2_LEN = 428; // 176 +const static uint64_t SH_FLD_01_RD_SIZE3 = 429; // 176 +const static uint64_t SH_FLD_01_RD_SIZE3_LEN = 430; // 176 +const static uint64_t SH_FLD_01_RD_SIZE4 = 431; // 176 +const static uint64_t SH_FLD_01_RD_SIZE4_LEN = 432; // 176 +const static uint64_t SH_FLD_01_RD_SIZE5 = 433; // 176 +const static uint64_t SH_FLD_01_RD_SIZE5_LEN = 434; // 176 +const static uint64_t SH_FLD_01_RD_SIZE6 = 435; // 176 +const static uint64_t SH_FLD_01_RD_SIZE6_LEN = 436; // 176 +const static uint64_t SH_FLD_01_RD_SIZE7 = 437; // 176 +const static uint64_t SH_FLD_01_RD_SIZE7_LEN = 438; // 176 +const static uint64_t SH_FLD_01_READ_CENTERING_MODE = 439; // 16 +const static uint64_t SH_FLD_01_READ_CENTERING_MODE_LEN = 440; // 16 +const static uint64_t SH_FLD_01_REFERENCE1 = 441; // 16 +const static uint64_t SH_FLD_01_REFERENCE1_LEN = 442; // 16 +const static uint64_t SH_FLD_01_REFERENCE2 = 443; // 16 +const static uint64_t SH_FLD_01_REFERENCE2_LEN = 444; // 16 +const static uint64_t SH_FLD_01_REFERENCE3 = 445; // 16 +const static uint64_t SH_FLD_01_REFERENCE3_LEN = 446; // 16 +const static uint64_t SH_FLD_01_REGS_RXDLL_CAL_SKIP = 447; // 32 +const static uint64_t SH_FLD_01_REGS_RXDLL_CAL_SKIP_LEN = 448; // 32 +const static uint64_t SH_FLD_01_REGS_RXDLL_COARSE_ADJ_BY2 = 449; // 32 +const static uint64_t SH_FLD_01_REGS_RXDLL_COARSE_EN = 450; // 32 +const static uint64_t SH_FLD_01_REGS_RXDLL_COARSE_EN_LEN = 451; // 32 +const static uint64_t SH_FLD_01_REGS_RXDLL_DAC_COARSE = 452; // 32 +const static uint64_t SH_FLD_01_REGS_RXDLL_DAC_COARSE_LEN = 453; // 32 +const static uint64_t SH_FLD_01_REGS_RXDLL_VREG_LOWER = 454; // 32 +const static uint64_t SH_FLD_01_REGS_RXDLL_VREG_LOWER_LEN = 455; // 32 +const static uint64_t SH_FLD_01_REGS_RXDLL_VREG_UPPER = 456; // 32 +const static uint64_t SH_FLD_01_REGS_RXDLL_VREG_UPPER_LEN = 457; // 32 +const static uint64_t SH_FLD_01_RESERVED_50_52 = 458; // 32 +const static uint64_t SH_FLD_01_RESERVED_50_52_LEN = 459; // 32 +const static uint64_t SH_FLD_01_RESERVED_56_63 = 460; // 16 +const static uint64_t SH_FLD_01_RESERVED_56_63_LEN = 461; // 16 +const static uint64_t SH_FLD_01_RESERVED_58_60 = 462; // 32 +const static uint64_t SH_FLD_01_RESERVED_58_60_LEN = 463; // 32 +const static uint64_t SH_FLD_01_ROT0 = 464; // 16 +const static uint64_t SH_FLD_01_ROT0_LEN = 465; // 16 +const static uint64_t SH_FLD_01_ROT1 = 466; // 16 +const static uint64_t SH_FLD_01_ROT1_LEN = 467; // 16 +const static uint64_t SH_FLD_01_ROT_CLK_N0 = 468; // 128 +const static uint64_t SH_FLD_01_ROT_CLK_N0_LEN = 469; // 128 +const static uint64_t SH_FLD_01_ROT_CLK_N1 = 470; // 128 +const static uint64_t SH_FLD_01_ROT_CLK_N1_LEN = 471; // 128 +const static uint64_t SH_FLD_01_ROT_N0 = 472; // 128 +const static uint64_t SH_FLD_01_ROT_N0_LEN = 473; // 128 +const static uint64_t SH_FLD_01_ROT_N1 = 474; // 128 +const static uint64_t SH_FLD_01_ROT_N1_LEN = 475; // 128 +const static uint64_t SH_FLD_01_ROT_OVERRIDE = 476; // 32 +const static uint64_t SH_FLD_01_ROT_OVERRIDE_EN = 477; // 32 +const static uint64_t SH_FLD_01_ROT_OVERRIDE_LEN = 478; // 32 +const static uint64_t SH_FLD_01_RXREG_COMPCON_DC = 479; // 32 +const static uint64_t SH_FLD_01_RXREG_COMPCON_DC_LEN = 480; // 32 +const static uint64_t SH_FLD_01_RXREG_CON_DC = 481; // 32 +const static uint64_t SH_FLD_01_RXREG_DAC_PULLUP_DC = 482; // 32 +const static uint64_t SH_FLD_01_RXREG_DRVCON_DC = 483; // 32 +const static uint64_t SH_FLD_01_RXREG_DRVCON_DC_LEN = 484; // 32 +const static uint64_t SH_FLD_01_RXREG_FILTER_LENGTH_DC = 485; // 32 +const static uint64_t SH_FLD_01_RXREG_FILTER_LENGTH_DC_LEN = 486; // 32 +const static uint64_t SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC = 487; // 32 +const static uint64_t SH_FLD_01_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 488; // 32 +const static uint64_t SH_FLD_01_RXREG_REF_SEL_DC = 489; // 32 +const static uint64_t SH_FLD_01_RXREG_REF_SEL_DC_LEN = 490; // 32 +const static uint64_t SH_FLD_01_S0ACENSLICENDRV_DC = 491; // 16 +const static uint64_t SH_FLD_01_S0ACENSLICENDRV_DC_LEN = 492; // 16 +const static uint64_t SH_FLD_01_S0ACENSLICEPDRV_DC = 493; // 16 +const static uint64_t SH_FLD_01_S0ACENSLICEPDRV_DC_LEN = 494; // 16 +const static uint64_t SH_FLD_01_S0ACENSLICEPTERM_DC = 495; // 16 +const static uint64_t SH_FLD_01_S0ACENSLICEPTERM_DC_LEN = 496; // 16 +const static uint64_t SH_FLD_01_S0INSDLYTAP = 497; // 16 +const static uint64_t SH_FLD_01_S1ACENSLICENDRV_DC = 498; // 16 +const static uint64_t SH_FLD_01_S1ACENSLICENDRV_DC_LEN = 499; // 16 +const static uint64_t SH_FLD_01_S1ACENSLICEPDRV_DC = 500; // 16 +const static uint64_t SH_FLD_01_S1ACENSLICEPDRV_DC_LEN = 501; // 16 +const static uint64_t SH_FLD_01_S1ACENSLICEPTERM_DC = 502; // 16 +const static uint64_t SH_FLD_01_S1ACENSLICEPTERM_DC_LEN = 503; // 16 +const static uint64_t SH_FLD_01_S1INSDLYTAP = 504; // 16 +const static uint64_t SH_FLD_01_SEL0 = 505; // 32 +const static uint64_t SH_FLD_01_SEL0_LEN = 506; // 16 +const static uint64_t SH_FLD_01_SEL1 = 507; // 32 +const static uint64_t SH_FLD_01_SEL10 = 508; // 32 +const static uint64_t SH_FLD_01_SEL10_LEN = 509; // 32 +const static uint64_t SH_FLD_01_SEL11 = 510; // 32 +const static uint64_t SH_FLD_01_SEL11_LEN = 511; // 32 +const static uint64_t SH_FLD_01_SEL12 = 512; // 32 +const static uint64_t SH_FLD_01_SEL12_LEN = 513; // 32 +const static uint64_t SH_FLD_01_SEL13 = 514; // 32 +const static uint64_t SH_FLD_01_SEL13_LEN = 515; // 32 +const static uint64_t SH_FLD_01_SEL14 = 516; // 32 +const static uint64_t SH_FLD_01_SEL14_LEN = 517; // 32 +const static uint64_t SH_FLD_01_SEL15 = 518; // 32 +const static uint64_t SH_FLD_01_SEL15_LEN = 519; // 32 +const static uint64_t SH_FLD_01_SEL1_LEN = 520; // 32 +const static uint64_t SH_FLD_01_SEL2 = 521; // 32 +const static uint64_t SH_FLD_01_SEL2_LEN = 522; // 32 +const static uint64_t SH_FLD_01_SEL3 = 523; // 32 +const static uint64_t SH_FLD_01_SEL3_LEN = 524; // 32 +const static uint64_t SH_FLD_01_SEL4 = 525; // 32 +const static uint64_t SH_FLD_01_SEL4_LEN = 526; // 32 +const static uint64_t SH_FLD_01_SEL5 = 527; // 32 +const static uint64_t SH_FLD_01_SEL5_LEN = 528; // 32 +const static uint64_t SH_FLD_01_SEL6 = 529; // 32 +const static uint64_t SH_FLD_01_SEL6_LEN = 530; // 32 +const static uint64_t SH_FLD_01_SEL7 = 531; // 32 +const static uint64_t SH_FLD_01_SEL7_LEN = 532; // 32 +const static uint64_t SH_FLD_01_SEL8 = 533; // 32 +const static uint64_t SH_FLD_01_SEL8_LEN = 534; // 16 +const static uint64_t SH_FLD_01_SEL9 = 535; // 32 +const static uint64_t SH_FLD_01_SEL9_LEN = 536; // 32 +const static uint64_t SH_FLD_01_SEL_A = 537; // 16 +const static uint64_t SH_FLD_01_SEL_A_LEN = 538; // 16 +const static uint64_t SH_FLD_01_SEL_B = 539; // 16 +const static uint64_t SH_FLD_01_SEL_B_LEN = 540; // 16 +const static uint64_t SH_FLD_01_SMALL_STEP_LEFT = 541; // 16 +const static uint64_t SH_FLD_01_SMALL_STEP_RIGHT = 542; // 16 +const static uint64_t SH_FLD_01_SYNC = 543; // 16 +const static uint64_t SH_FLD_01_SYNC_LEN = 544; // 16 +const static uint64_t SH_FLD_01_SYSCLK_DQSCLK_OFFSET = 545; // 16 +const static uint64_t SH_FLD_01_SYSCLK_DQSCLK_OFFSET_LEN = 546; // 16 +const static uint64_t SH_FLD_01_SYSCLK_RDCLK_OFFSET = 547; // 16 +const static uint64_t SH_FLD_01_SYSCLK_RDCLK_OFFSET_LEN = 548; // 16 +const static uint64_t SH_FLD_01_TEST_4TO1_MODE = 549; // 16 +const static uint64_t SH_FLD_01_TEST_CHECK_EN = 550; // 16 +const static uint64_t SH_FLD_01_TEST_CLEAR_ERROR = 551; // 16 +const static uint64_t SH_FLD_01_TEST_DATA_EN = 552; // 16 +const static uint64_t SH_FLD_01_TEST_GEN_EN = 553; // 16 +const static uint64_t SH_FLD_01_TEST_LANE_PAIR_FAIL = 554; // 16 +const static uint64_t SH_FLD_01_TEST_LANE_PAIR_FAIL_LEN = 555; // 16 +const static uint64_t SH_FLD_01_TEST_MODE = 556; // 16 +const static uint64_t SH_FLD_01_TEST_MODE_LEN = 557; // 16 +const static uint64_t SH_FLD_01_TEST_RESET = 558; // 16 +const static uint64_t SH_FLD_01_TRAILING_EDGE_FOUND_MASK = 559; // 16 +const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND = 560; // 16 +const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15 = 561; // 8 +const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 562; // 8 +const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15 = 563; // 8 +const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_15_LEN = 564; // 8 +const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23 = 565; // 16 +const static uint64_t SH_FLD_01_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 566; // 16 +const static uint64_t SH_FLD_01_TRIG_PERIOD = 567; // 16 +const static uint64_t SH_FLD_01_TSYS = 568; // 16 +const static uint64_t SH_FLD_01_TSYS_LEN = 569; // 16 +const static uint64_t SH_FLD_01_VALID_NS_BIG_L = 570; // 16 +const static uint64_t SH_FLD_01_VALID_NS_BIG_L_MASK = 571; // 16 +const static uint64_t SH_FLD_01_VALID_NS_BIG_R = 572; // 16 +const static uint64_t SH_FLD_01_VALID_NS_BIG_R_MASK = 573; // 16 +const static uint64_t SH_FLD_01_VALID_NS_JUMP_BACK = 574; // 16 +const static uint64_t SH_FLD_01_VALID_NS_JUMP_BACK_MASK = 575; // 16 +const static uint64_t SH_FLD_01_VALUE_DRAM0 = 576; // 64 +const static uint64_t SH_FLD_01_VALUE_DRAM0_LEN = 577; // 64 +const static uint64_t SH_FLD_01_VALUE_DRAM1 = 578; // 64 +const static uint64_t SH_FLD_01_VALUE_DRAM1_LEN = 579; // 64 +const static uint64_t SH_FLD_01_VALUE_DRAM2 = 580; // 64 +const static uint64_t SH_FLD_01_VALUE_DRAM2_LEN = 581; // 64 +const static uint64_t SH_FLD_01_VALUE_DRAM3 = 582; // 64 +const static uint64_t SH_FLD_01_VALUE_DRAM3_LEN = 583; // 64 +const static uint64_t SH_FLD_01_WL_ADVANCE_DISABLE = 584; // 16 +const static uint64_t SH_FLD_01_WL_ERR_CLK16 = 585; // 32 +const static uint64_t SH_FLD_01_WL_ERR_CLK16_MASK = 586; // 16 +const static uint64_t SH_FLD_01_WL_ERR_CLK18 = 587; // 32 +const static uint64_t SH_FLD_01_WL_ERR_CLK18_MASK = 588; // 16 +const static uint64_t SH_FLD_01_WL_ERR_CLK20 = 589; // 32 +const static uint64_t SH_FLD_01_WL_ERR_CLK20_MASK = 590; // 16 +const static uint64_t SH_FLD_01_WL_ERR_CLK22 = 591; // 32 +const static uint64_t SH_FLD_01_WRAPSEL = 592; // 16 +const static uint64_t SH_FLD_01_WTRFL_AVE_DIS = 593; // 16 +const static uint64_t SH_FLD_01_ZERO_DETECTED = 594; // 16 +const static uint64_t SH_FLD_0X00_DATA_PARITY = 595; // 4 +const static uint64_t SH_FLD_0X00_SPARE_30_31 = 596; // 1 +const static uint64_t SH_FLD_0X00_SPARE_30_31_LEN = 597; // 1 +const static uint64_t SH_FLD_0X01_DATA_PARITY = 598; // 4 +const static uint64_t SH_FLD_0X01_SPARE_03 = 599; // 1 +const static uint64_t SH_FLD_0X01_SPARE_28_31 = 600; // 1 +const static uint64_t SH_FLD_0X01_SPARE_28_31_LEN = 601; // 1 +const static uint64_t SH_FLD_0X02_DATA_PARITY = 602; // 4 +const static uint64_t SH_FLD_0X02_SPARE_03 = 603; // 1 +const static uint64_t SH_FLD_0X02_SPARE_28_31 = 604; // 1 +const static uint64_t SH_FLD_0X02_SPARE_28_31_LEN = 605; // 1 +const static uint64_t SH_FLD_0X03_DATA_PARITY = 606; // 4 +const static uint64_t SH_FLD_0X03_SPARE_03 = 607; // 1 +const static uint64_t SH_FLD_0X03_SPARE_28_31 = 608; // 1 +const static uint64_t SH_FLD_0X03_SPARE_28_31_LEN = 609; // 1 +const static uint64_t SH_FLD_0X04_DATA_PARITY = 610; // 4 +const static uint64_t SH_FLD_0X04_SPARE_03 = 611; // 1 +const static uint64_t SH_FLD_0X04_SPARE_28_31 = 612; // 1 +const static uint64_t SH_FLD_0X04_SPARE_28_31_LEN = 613; // 1 +const static uint64_t SH_FLD_0X05_DATA_PARITY = 614; // 4 +const static uint64_t SH_FLD_0X05_SPARE_01 = 615; // 1 +const static uint64_t SH_FLD_0X05_SPARE_05 = 616; // 1 +const static uint64_t SH_FLD_0X06_DATA_PARITY = 617; // 4 +const static uint64_t SH_FLD_0X06_SPARE_02_04 = 618; // 1 +const static uint64_t SH_FLD_0X06_SPARE_02_04_LEN = 619; // 1 +const static uint64_t SH_FLD_0X06_SPARE_16_21 = 620; // 1 +const static uint64_t SH_FLD_0X06_SPARE_16_21_LEN = 621; // 1 +const static uint64_t SH_FLD_0X07_DATA_PARITY = 622; // 4 +const static uint64_t SH_FLD_0X07_SPARE_19 = 623; // 1 +const static uint64_t SH_FLD_0X07_SPARE_20 = 624; // 1 +const static uint64_t SH_FLD_0X07_SPARE_22_31 = 625; // 1 +const static uint64_t SH_FLD_0X07_SPARE_22_31_LEN = 626; // 1 +const static uint64_t SH_FLD_0X08_DATA_PARITY = 627; // 4 +const static uint64_t SH_FLD_0X08_SPARE_03 = 628; // 1 +const static uint64_t SH_FLD_0X08_SPARE_30 = 629; // 1 +const static uint64_t SH_FLD_0X09_DATA_PARITY = 630; // 4 +const static uint64_t SH_FLD_0X0A_DATA_PARITY = 631; // 4 +const static uint64_t SH_FLD_0X0A_SPARE_13_15 = 632; // 1 +const static uint64_t SH_FLD_0X0A_SPARE_13_15_LEN = 633; // 1 +const static uint64_t SH_FLD_0X0B_DATA_PARITY = 634; // 4 +const static uint64_t SH_FLD_0X0B_SPARE_04_05 = 635; // 1 +const static uint64_t SH_FLD_0X0B_SPARE_04_05_LEN = 636; // 1 +const static uint64_t SH_FLD_0X0B_SPARE_17 = 637; // 1 +const static uint64_t SH_FLD_0X0B_SPARE_33_39 = 638; // 1 +const static uint64_t SH_FLD_0X0B_SPARE_33_39_LEN = 639; // 1 +const static uint64_t SH_FLD_0X0C_DATA_PARITY = 640; // 4 +const static uint64_t SH_FLD_0X0D_SPARE_60_62 = 641; // 1 +const static uint64_t SH_FLD_0X0D_SPARE_60_62_LEN = 642; // 1 +const static uint64_t SH_FLD_0X10_DATA_PARITY = 643; // 4 +const static uint64_t SH_FLD_0X10_SPARE_17_18 = 644; // 1 +const static uint64_t SH_FLD_0X10_SPARE_17_18_LEN = 645; // 1 +const static uint64_t SH_FLD_0X10_SPARE_19_23 = 646; // 1 +const static uint64_t SH_FLD_0X10_SPARE_19_23_LEN = 647; // 1 +const static uint64_t SH_FLD_0X10_SPARE_24_25 = 648; // 1 +const static uint64_t SH_FLD_0X10_SPARE_24_25_LEN = 649; // 1 +const static uint64_t SH_FLD_0X10_SPARE_27 = 650; // 1 +const static uint64_t SH_FLD_0X10_SPARE_29 = 651; // 1 +const static uint64_t SH_FLD_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY = 652; // 4 +const static uint64_t SH_FLD_0X17_0X18_0X21_0X22_DATA_PARITY = 653; // 4 +const static uint64_t SH_FLD_0X1D_0X1E_0X1F_DATA_PARITY = 654; // 4 +const static uint64_t SH_FLD_0X20_DATA_PARITY = 655; // 4 +const static uint64_t SH_FLD_0X22_SPARE_01 = 656; // 1 +const static uint64_t SH_FLD_0X22_SPARE_03_07 = 657; // 1 +const static uint64_t SH_FLD_0X22_SPARE_03_07_LEN = 658; // 1 +const static uint64_t SH_FLD_0X23_DATA_PARITY = 659; // 4 +const static uint64_t SH_FLD_0X23_SPARE_06_07 = 660; // 1 +const static uint64_t SH_FLD_0X23_SPARE_06_07_LEN = 661; // 1 +const static uint64_t SH_FLD_0X24_DATA_PARITY = 662; // 4 +const static uint64_t SH_FLD_0X24_SPARE_05_07 = 663; // 1 +const static uint64_t SH_FLD_0X24_SPARE_05_07_LEN = 664; // 1 +const static uint64_t SH_FLD_0X27_DATA_PARITY = 665; // 4 +const static uint64_t SH_FLD_0X27_SPARE_34 = 666; // 1 +const static uint64_t SH_FLD_0X27_SPARE_36 = 667; // 1 +const static uint64_t SH_FLD_0X29_DATA_PARITY = 668; // 4 +const static uint64_t SH_FLD_0X30_0X31_0X32_0X33_DATA_PARITY = 669; // 4 +const static uint64_t SH_FLD_0_2 = 670; // 16 +const static uint64_t SH_FLD_0_CANNED_0 = 671; // 2 +const static uint64_t SH_FLD_0_CANNED_0_LEN = 672; // 2 +const static uint64_t SH_FLD_0_CANNED_1 = 673; // 2 +const static uint64_t SH_FLD_0_CANNED_1_LEN = 674; // 2 +const static uint64_t SH_FLD_0_CPS = 675; // 2 +const static uint64_t SH_FLD_0_CPS_LEN = 676; // 2 +const static uint64_t SH_FLD_0_DATA = 677; // 1 +const static uint64_t SH_FLD_0_DATA_LEN = 678; // 1 +const static uint64_t SH_FLD_0_LEN = 679; // 62 +const static uint64_t SH_FLD_0_LOCAL_STEP_MODE_ENABLE = 680; // 1 +const static uint64_t SH_FLD_0_OSC_NOT_VALID = 681; // 1 +const static uint64_t SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT = 682; // 1 +const static uint64_t SH_FLD_0_REMOTE_SYNC_LATE_SYNC_COUNT_LEN = 683; // 1 +const static uint64_t SH_FLD_0_RESULT = 684; // 43 +const static uint64_t SH_FLD_0_RESULT_LEN = 685; // 43 +const static uint64_t SH_FLD_0_SELECT = 686; // 1 +const static uint64_t SH_FLD_0_SELECT_LEN = 687; // 1 +const static uint64_t SH_FLD_0_SPARE_SECTOR_BUFFER_CONTROL = 688; // 3 +const static uint64_t SH_FLD_0_STEP_ALIGN_DISABLE = 689; // 1 +const static uint64_t SH_FLD_0_STEP_ALIGN_THRESHOLD = 690; // 1 +const static uint64_t SH_FLD_0_STEP_ALIGN_THRESHOLD_LEN = 691; // 1 +const static uint64_t SH_FLD_0_STEP_CHECK_CONSTANT_CPS_ENABLE = 692; // 2 +const static uint64_t SH_FLD_0_STEP_CHECK_CPS_DEVIATION = 693; // 2 +const static uint64_t SH_FLD_0_STEP_CHECK_CPS_DEVIATION_LEN = 694; // 2 +const static uint64_t SH_FLD_0_STEP_CHECK_VALIDITY_COUNT = 695; // 2 +const static uint64_t SH_FLD_0_STEP_CHECK_VALIDITY_COUNT_LEN = 696; // 2 +const static uint64_t SH_FLD_0_STEP_STEER_ENABLE = 697; // 1 +const static uint64_t SH_FLD_1 = 698; // 525 +const static uint64_t SH_FLD_10 = 699; // 6 +const static uint64_t SH_FLD_10_RESERVED = 700; // 3 +const static uint64_t SH_FLD_10_SPARE_REFCLOCK = 701; // 3 +const static uint64_t SH_FLD_10_SPARE_SECTOR_BUFFER_CONTROL = 702; // 3 +const static uint64_t SH_FLD_11 = 703; // 6 +const static uint64_t SH_FLD_11_RESERVED = 704; // 3 +const static uint64_t SH_FLD_11_SPARE_REFCLOCK = 705; // 3 +const static uint64_t SH_FLD_11_SPARE_SECTOR_BUFFER_CONTROL = 706; // 3 +const static uint64_t SH_FLD_12 = 707; // 6 +const static uint64_t SH_FLD_12GB_ENABLE = 708; // 8 +const static uint64_t SH_FLD_12_RESERVED = 709; // 3 +const static uint64_t SH_FLD_12_SPARE_SECTOR_BUFFER_CONTROL = 710; // 3 +const static uint64_t SH_FLD_13 = 711; // 6 +const static uint64_t SH_FLD_13_RESERVED = 712; // 3 +const static uint64_t SH_FLD_13_SPARE_OPB_CONTROL = 713; // 3 +const static uint64_t SH_FLD_13_SPARE_PROBE = 714; // 3 +const static uint64_t SH_FLD_13_SPARE_SECTOR_BUFFER_CONTROL = 715; // 3 +const static uint64_t SH_FLD_14 = 716; // 6 +const static uint64_t SH_FLD_14_RESERVED = 717; // 3 +const static uint64_t SH_FLD_14_SPARE_OPB_CONTROL = 718; // 3 +const static uint64_t SH_FLD_14_SPARE_PLL = 719; // 3 +const static uint64_t SH_FLD_14_SPARE_PROBE = 720; // 3 +const static uint64_t SH_FLD_14_SPARE_SECTOR_BUFFER_CONTROL = 721; // 3 +const static uint64_t SH_FLD_15 = 722; // 6 +const static uint64_t SH_FLD_15_RESERVED = 723; // 3 +const static uint64_t SH_FLD_15_SPARE_OPB_CONTROL = 724; // 3 +const static uint64_t SH_FLD_15_SPARE_OSC = 725; // 3 +const static uint64_t SH_FLD_15_SPARE_PLL = 726; // 3 +const static uint64_t SH_FLD_15_SPARE_PROBE = 727; // 3 +const static uint64_t SH_FLD_15_SPARE_SECTOR_BUFFER_CONTROL = 728; // 3 +const static uint64_t SH_FLD_16 = 729; // 6 +const static uint64_t SH_FLD_16_FREE_USAGE = 730; // 3 +const static uint64_t SH_FLD_16_SPARE_OSC = 731; // 3 +const static uint64_t SH_FLD_16_SPARE_RESONANT_CLOCKING_CONTROL = 732; // 3 +const static uint64_t SH_FLD_17 = 733; // 6 +const static uint64_t SH_FLD_17_SPARE_OSC = 734; // 3 +const static uint64_t SH_FLD_17_SPARE_RESONANT_CLOCKING_CONTROL = 735; // 3 +const static uint64_t SH_FLD_18 = 736; // 6 +const static uint64_t SH_FLD_18_31_SPARE = 737; // 8 +const static uint64_t SH_FLD_18_31_SPARE_LEN = 738; // 8 +const static uint64_t SH_FLD_18_SPARE_MUX_CONTROL = 739; // 3 +const static uint64_t SH_FLD_18_SPARE_OSC = 740; // 3 +const static uint64_t SH_FLD_18_SPARE_RESONANT_CLOCKING_CONTROL = 741; // 3 +const static uint64_t SH_FLD_19 = 742; // 6 +const static uint64_t SH_FLD_19_SPARE_MUX_CONTROL = 743; // 3 +const static uint64_t SH_FLD_19_SPARE_OSC = 744; // 3 +const static uint64_t SH_FLD_19_SPARE_RESONANT_CLOCKING_CONTROL = 745; // 3 +const static uint64_t SH_FLD_1_3 = 746; // 16 +const static uint64_t SH_FLD_1_CANNED_0 = 747; // 2 +const static uint64_t SH_FLD_1_CANNED_0_LEN = 748; // 2 +const static uint64_t SH_FLD_1_CANNED_1 = 749; // 2 +const static uint64_t SH_FLD_1_CANNED_1_LEN = 750; // 2 +const static uint64_t SH_FLD_1_CPS = 751; // 2 +const static uint64_t SH_FLD_1_CPS_LEN = 752; // 2 +const static uint64_t SH_FLD_1_DATA = 753; // 1 +const static uint64_t SH_FLD_1_DATA_LEN = 754; // 1 +const static uint64_t SH_FLD_1_LEN = 755; // 105 +const static uint64_t SH_FLD_1_LOCAL_STEP_MODE_ENABLE = 756; // 1 +const static uint64_t SH_FLD_1_OSC_NOT_VALID = 757; // 1 +const static uint64_t SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT = 758; // 1 +const static uint64_t SH_FLD_1_REMOTE_SYNC_LATE_SYNC_COUNT_LEN = 759; // 1 +const static uint64_t SH_FLD_1_RESULT = 760; // 43 +const static uint64_t SH_FLD_1_RESULT_LEN = 761; // 43 +const static uint64_t SH_FLD_1_SELECT = 762; // 1 +const static uint64_t SH_FLD_1_SELECT_LEN = 763; // 1 +const static uint64_t SH_FLD_1_SPARE_SECTOR_BUFFER_CONTROL = 764; // 3 +const static uint64_t SH_FLD_1_STEP_ALIGN_DISABLE = 765; // 1 +const static uint64_t SH_FLD_1_STEP_ALIGN_THRESHOLD = 766; // 1 +const static uint64_t SH_FLD_1_STEP_ALIGN_THRESHOLD_LEN = 767; // 1 +const static uint64_t SH_FLD_1_STEP_CHECK_CONSTANT_CPS_ENABLE = 768; // 2 +const static uint64_t SH_FLD_1_STEP_CHECK_CPS_DEVIATION = 769; // 2 +const static uint64_t SH_FLD_1_STEP_CHECK_CPS_DEVIATION_LEN = 770; // 2 +const static uint64_t SH_FLD_1_STEP_CHECK_VALIDITY_COUNT = 771; // 2 +const static uint64_t SH_FLD_1_STEP_CHECK_VALIDITY_COUNT_LEN = 772; // 2 +const static uint64_t SH_FLD_1_STEP_STEER_ENABLE = 773; // 1 +const static uint64_t SH_FLD_2 = 774; // 466 +const static uint64_t SH_FLD_20 = 775; // 6 +const static uint64_t SH_FLD_20_RESERVED = 776; // 3 +const static uint64_t SH_FLD_20_SPARE_OSC = 777; // 3 +const static uint64_t SH_FLD_20_SPARE_PLL_CONTROL = 778; // 3 +const static uint64_t SH_FLD_20_SPARE_RESONANT_CLOCKING_CONTROL = 779; // 3 +const static uint64_t SH_FLD_21 = 780; // 6 +const static uint64_t SH_FLD_21_RESERVED = 781; // 3 +const static uint64_t SH_FLD_21_SPARE_OSC = 782; // 3 +const static uint64_t SH_FLD_21_SPARE_PLL_CONTROL = 783; // 3 +const static uint64_t SH_FLD_21_SPARE_RESONANT_CLOCKING_CONTROL = 784; // 3 +const static uint64_t SH_FLD_22 = 785; // 6 +const static uint64_t SH_FLD_22_RESERVED = 786; // 6 +const static uint64_t SH_FLD_22_SPARE_OSC = 787; // 3 +const static uint64_t SH_FLD_22_SPARE_PLL_CONTROL = 788; // 3 +const static uint64_t SH_FLD_22_SPARE_RESONANT_CLOCKING_CONTROL = 789; // 3 +const static uint64_t SH_FLD_22_SPARE_TEST = 790; // 3 +const static uint64_t SH_FLD_23 = 791; // 118 +const static uint64_t SH_FLD_23_0_11 = 792; // 16 +const static uint64_t SH_FLD_23_0_11_LEN = 793; // 16 +const static uint64_t SH_FLD_23_12_15 = 794; // 16 +const static uint64_t SH_FLD_23_12_15_LEN = 795; // 16 +const static uint64_t SH_FLD_23_ADVANCE_PING_PONG = 796; // 16 +const static uint64_t SH_FLD_23_ADVANCE_PR_VALUE = 797; // 16 +const static uint64_t SH_FLD_23_ATESTSEL_0_4 = 798; // 16 +const static uint64_t SH_FLD_23_ATESTSEL_0_4_LEN = 799; // 16 +const static uint64_t SH_FLD_23_ATEST_SEL_0_1 = 800; // 16 +const static uint64_t SH_FLD_23_ATEST_SEL_0_1_LEN = 801; // 16 +const static uint64_t SH_FLD_23_BB_LOCK0 = 802; // 16 +const static uint64_t SH_FLD_23_BB_LOCK1 = 803; // 16 +const static uint64_t SH_FLD_23_BIG_STEP_RIGHT = 804; // 16 +const static uint64_t SH_FLD_23_BIT_CENTERED = 805; // 16 +const static uint64_t SH_FLD_23_BIT_CENTERED_LEN = 806; // 16 +const static uint64_t SH_FLD_23_BLFIFO_DIS = 807; // 16 +const static uint64_t SH_FLD_23_BUMP = 808; // 16 +const static uint64_t SH_FLD_23_CALGATE_ON = 809; // 16 +const static uint64_t SH_FLD_23_CALIBRATE_BIT = 810; // 16 +const static uint64_t SH_FLD_23_CALIBRATE_BIT_LEN = 811; // 16 +const static uint64_t SH_FLD_23_CAL_CKTS_ACTIVE = 812; // 32 +const static uint64_t SH_FLD_23_CAL_ERROR = 813; // 32 +const static uint64_t SH_FLD_23_CAL_ERROR_FINE = 814; // 32 +const static uint64_t SH_FLD_23_CAL_GOOD = 815; // 32 +const static uint64_t SH_FLD_23_CHECKER_ENABLE = 816; // 16 +const static uint64_t SH_FLD_23_CHECKER_RESET = 817; // 16 +const static uint64_t SH_FLD_23_CLK16_SINGLE_ENDED = 818; // 128 +const static uint64_t SH_FLD_23_CLK18_SINGLE_ENDED = 819; // 128 +const static uint64_t SH_FLD_23_CLK20_SINGLE_ENDED = 820; // 128 +const static uint64_t SH_FLD_23_CLK22_SINGLE_ENDED = 821; // 128 +const static uint64_t SH_FLD_23_CLK_LEVEL = 822; // 16 +const static uint64_t SH_FLD_23_CLK_LEVEL_LEN = 823; // 16 +const static uint64_t SH_FLD_23_CNTL_POL = 824; // 16 +const static uint64_t SH_FLD_23_CNTL_SRC = 825; // 16 +const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N0 = 826; // 16 +const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N0_MASK = 827; // 16 +const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N1 = 828; // 16 +const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N1_MASK = 829; // 16 +const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N2 = 830; // 16 +const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N2_MASK = 831; // 16 +const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N3 = 832; // 16 +const static uint64_t SH_FLD_23_COARSE_PATTERN_ERR_N3_MASK = 833; // 16 +const static uint64_t SH_FLD_23_CONTINUOUS_UPDATE = 834; // 32 +const static uint64_t SH_FLD_23_CTR_1D_CHICKEN_SWITCH = 835; // 16 +const static uint64_t SH_FLD_23_CTR_2D_SMALL_STEP_VAL = 836; // 16 +const static uint64_t SH_FLD_23_CTR_2D_SMALL_STEP_VAL_LEN = 837; // 16 +const static uint64_t SH_FLD_23_CTR_3D_BIG_STEP_VAL = 838; // 16 +const static uint64_t SH_FLD_23_CTR_3D_BIG_STEP_VAL_LEN = 839; // 16 +const static uint64_t SH_FLD_23_CTR_CUR = 840; // 16 +const static uint64_t SH_FLD_23_CTR_CUR_LEN = 841; // 16 +const static uint64_t SH_FLD_23_CTR_NUM_BITS_TO_SKIP = 842; // 16 +const static uint64_t SH_FLD_23_CTR_NUM_BITS_TO_SKIP_LEN = 843; // 16 +const static uint64_t SH_FLD_23_CTR_NUM_NO_INC_COMP = 844; // 16 +const static uint64_t SH_FLD_23_CTR_NUM_NO_INC_COMP_LEN = 845; // 16 +const static uint64_t SH_FLD_23_CTR_NUM_VREFREQ_CNT = 846; // 16 +const static uint64_t SH_FLD_23_CTR_NUM_VREFREQ_CNT_LEN = 847; // 16 +const static uint64_t SH_FLD_23_CTR_NUM_WRRDREQ_CNT = 848; // 16 +const static uint64_t SH_FLD_23_CTR_NUM_WRRDREQ_CNT_LEN = 849; // 16 +const static uint64_t SH_FLD_23_CTR_RANGE_CROSSOVER = 850; // 16 +const static uint64_t SH_FLD_23_CTR_RANGE_CROSSOVER_LEN = 851; // 16 +const static uint64_t SH_FLD_23_CTR_RANGE_SEL = 852; // 64 +const static uint64_t SH_FLD_23_CTR_RANGE_SELECT = 853; // 16 +const static uint64_t SH_FLD_23_CTR_RUN_FULL_1D = 854; // 16 +const static uint64_t SH_FLD_23_CTR_SINGLE_RANGE_MAX = 855; // 16 +const static uint64_t SH_FLD_23_CTR_SINGLE_RANGE_MAX_LEN = 856; // 16 +const static uint64_t SH_FLD_23_DD2_DQS_FIX_DIS = 857; // 16 +const static uint64_t SH_FLD_23_DD2_FIX_DIS = 858; // 16 +const static uint64_t SH_FLD_23_DD2_WTRFL_SYNC_DIS = 859; // 16 +const static uint64_t SH_FLD_23_DELAY1 = 860; // 16 +const static uint64_t SH_FLD_23_DELAY10 = 861; // 16 +const static uint64_t SH_FLD_23_DELAY10_LEN = 862; // 16 +const static uint64_t SH_FLD_23_DELAY11 = 863; // 16 +const static uint64_t SH_FLD_23_DELAY11_LEN = 864; // 16 +const static uint64_t SH_FLD_23_DELAY12 = 865; // 16 +const static uint64_t SH_FLD_23_DELAY12_LEN = 866; // 16 +const static uint64_t SH_FLD_23_DELAY13 = 867; // 16 +const static uint64_t SH_FLD_23_DELAY13_LEN = 868; // 16 +const static uint64_t SH_FLD_23_DELAY14 = 869; // 16 +const static uint64_t SH_FLD_23_DELAY14_LEN = 870; // 16 +const static uint64_t SH_FLD_23_DELAY15 = 871; // 16 +const static uint64_t SH_FLD_23_DELAY15_LEN = 872; // 16 +const static uint64_t SH_FLD_23_DELAY1_LEN = 873; // 16 +const static uint64_t SH_FLD_23_DELAY2 = 874; // 16 +const static uint64_t SH_FLD_23_DELAY2_LEN = 875; // 16 +const static uint64_t SH_FLD_23_DELAY3 = 876; // 16 +const static uint64_t SH_FLD_23_DELAY3_LEN = 877; // 16 +const static uint64_t SH_FLD_23_DELAY4 = 878; // 16 +const static uint64_t SH_FLD_23_DELAY4_LEN = 879; // 16 +const static uint64_t SH_FLD_23_DELAY5 = 880; // 16 +const static uint64_t SH_FLD_23_DELAY5_LEN = 881; // 16 +const static uint64_t SH_FLD_23_DELAY6 = 882; // 16 +const static uint64_t SH_FLD_23_DELAY6_LEN = 883; // 16 +const static uint64_t SH_FLD_23_DELAY7 = 884; // 16 +const static uint64_t SH_FLD_23_DELAY7_LEN = 885; // 16 +const static uint64_t SH_FLD_23_DELAY8 = 886; // 16 +const static uint64_t SH_FLD_23_DELAY8_LEN = 887; // 16 +const static uint64_t SH_FLD_23_DELAY9 = 888; // 16 +const static uint64_t SH_FLD_23_DELAY9_LEN = 889; // 16 +const static uint64_t SH_FLD_23_DELAYG = 890; // 1280 +const static uint64_t SH_FLD_23_DELAYG_LEN = 891; // 1280 +const static uint64_t SH_FLD_23_DELAY_PING_PONG_HALF = 892; // 16 +const static uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH = 893; // 16 +const static uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 894; // 16 +const static uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW = 895; // 16 +const static uint64_t SH_FLD_23_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 896; // 16 +const static uint64_t SH_FLD_23_DFT_FORCE_OUTPUTS = 897; // 16 +const static uint64_t SH_FLD_23_DFT_PRBS7_GEN_EN = 898; // 16 +const static uint64_t SH_FLD_23_DIGITAL_EN = 899; // 16 +const static uint64_t SH_FLD_23_DIR_0_15 = 900; // 16 +const static uint64_t SH_FLD_23_DIR_0_15_LEN = 901; // 16 +const static uint64_t SH_FLD_23_DISABLE_0_15 = 902; // 64 +const static uint64_t SH_FLD_23_DISABLE_0_15_LEN = 903; // 64 +const static uint64_t SH_FLD_23_DISABLE_16_23 = 904; // 64 +const static uint64_t SH_FLD_23_DISABLE_16_23_LEN = 905; // 64 +const static uint64_t SH_FLD_23_DISABLE_PING_PONG = 906; // 16 +const static uint64_t SH_FLD_23_DISABLE_TERMINATION = 907; // 16 +const static uint64_t SH_FLD_23_DIS_CLK_GATE = 908; // 16 +const static uint64_t SH_FLD_23_DI_ADR0_ADR1 = 909; // 16 +const static uint64_t SH_FLD_23_DI_ADR10_ADR11 = 910; // 16 +const static uint64_t SH_FLD_23_DI_ADR12_ADR13 = 911; // 16 +const static uint64_t SH_FLD_23_DI_ADR14_ADR15 = 912; // 16 +const static uint64_t SH_FLD_23_DI_ADR2 = 913; // 8 +const static uint64_t SH_FLD_23_DI_ADR3 = 914; // 8 +const static uint64_t SH_FLD_23_DI_ADR4_ADR5 = 915; // 16 +const static uint64_t SH_FLD_23_DI_ADR6_ADR7 = 916; // 16 +const static uint64_t SH_FLD_23_DI_ADR8_ADR9 = 917; // 16 +const static uint64_t SH_FLD_23_DLL_ADJUST = 918; // 32 +const static uint64_t SH_FLD_23_DLL_ADJUST_LEN = 919; // 32 +const static uint64_t SH_FLD_23_DLL_COMPARE_OUT = 920; // 32 +const static uint64_t SH_FLD_23_DLL_CORRECT_EN = 921; // 32 +const static uint64_t SH_FLD_23_DLL_ITER_A = 922; // 32 +const static uint64_t SH_FLD_23_DL_FORCE_ON = 923; // 16 +const static uint64_t SH_FLD_23_DONE = 924; // 32 +const static uint64_t SH_FLD_23_DQS = 925; // 16 +const static uint64_t SH_FLD_23_DQSCLK_SELECT0 = 926; // 64 +const static uint64_t SH_FLD_23_DQSCLK_SELECT0_LEN = 927; // 64 +const static uint64_t SH_FLD_23_DQSCLK_SELECT1 = 928; // 64 +const static uint64_t SH_FLD_23_DQSCLK_SELECT1_LEN = 929; // 64 +const static uint64_t SH_FLD_23_DQSCLK_SELECT2 = 930; // 64 +const static uint64_t SH_FLD_23_DQSCLK_SELECT2_LEN = 931; // 64 +const static uint64_t SH_FLD_23_DQSCLK_SELECT3 = 932; // 64 +const static uint64_t SH_FLD_23_DQSCLK_SELECT3_LEN = 933; // 64 +const static uint64_t SH_FLD_23_DQS_ALIGN_CNTR = 934; // 16 +const static uint64_t SH_FLD_23_DQS_ALIGN_CNTR_LEN = 935; // 16 +const static uint64_t SH_FLD_23_DQS_ALIGN_FIX_DIS = 936; // 16 +const static uint64_t SH_FLD_23_DQS_ALIGN_JITTER = 937; // 16 +const static uint64_t SH_FLD_23_DQS_ALIGN_QUAD = 938; // 16 +const static uint64_t SH_FLD_23_DQS_ALIGN_QUAD_LEN = 939; // 16 +const static uint64_t SH_FLD_23_DQS_ALIGN_SM = 940; // 16 +const static uint64_t SH_FLD_23_DQS_ALIGN_SM_LEN = 941; // 16 +const static uint64_t SH_FLD_23_DQS_LEN = 942; // 16 +const static uint64_t SH_FLD_23_DQS_PIPE_FIX_DIS = 943; // 16 +const static uint64_t SH_FLD_23_DQS_PIPE_FIX_DIS_LEN = 944; // 16 +const static uint64_t SH_FLD_23_DQS_QUAD_CONFIG = 945; // 16 +const static uint64_t SH_FLD_23_DQS_QUAD_CONFIG_LEN = 946; // 16 +const static uint64_t SH_FLD_23_DRIFT_ERROR = 947; // 16 +const static uint64_t SH_FLD_23_DRIFT_MASK = 948; // 16 +const static uint64_t SH_FLD_23_DRVREN_MODE = 949; // 32 +const static uint64_t SH_FLD_23_DYN_MCTERM_CNTL_EN = 950; // 16 +const static uint64_t SH_FLD_23_DYN_POWER_CNTL_EN = 951; // 16 +const static uint64_t SH_FLD_23_DYN_RX_GATE_CNTL_EN = 952; // 16 +const static uint64_t SH_FLD_23_ENABLE_0_15 = 953; // 16 +const static uint64_t SH_FLD_23_ENABLE_0_15_LEN = 954; // 16 +const static uint64_t SH_FLD_23_ENABLE_16_23 = 955; // 16 +const static uint64_t SH_FLD_23_ENABLE_16_23_LEN = 956; // 16 +const static uint64_t SH_FLD_23_EN_DQS_OFFSET = 957; // 16 +const static uint64_t SH_FLD_23_EN_DRIVER_INVFB_DC = 958; // 32 +const static uint64_t SH_FLD_23_EN_N_WR = 959; // 16 +const static uint64_t SH_FLD_23_EN_N_WR_LEN = 960; // 16 +const static uint64_t SH_FLD_23_EN_P_WR = 961; // 32 +const static uint64_t SH_FLD_23_EN_P_WR_LEN = 962; // 32 +const static uint64_t SH_FLD_23_ERROR = 963; // 16 +const static uint64_t SH_FLD_23_ERROR_LEN = 964; // 16 +const static uint64_t SH_FLD_23_ERR_CLK22_MASK = 965; // 16 +const static uint64_t SH_FLD_23_EYE_CLIPPING = 966; // 16 +const static uint64_t SH_FLD_23_EYE_CLIPPING_MASK = 967; // 16 +const static uint64_t SH_FLD_23_FINE_STEPPING = 968; // 16 +const static uint64_t SH_FLD_23_FLUSH = 969; // 16 +const static uint64_t SH_FLD_23_FORCE_DQS_LANES_ON = 970; // 16 +const static uint64_t SH_FLD_23_FORCE_FIFO_CAPTURE = 971; // 16 +const static uint64_t SH_FLD_23_FRZSULV = 972; // 32 +const static uint64_t SH_FLD_23_FW_LEFT_SIDE = 973; // 16 +const static uint64_t SH_FLD_23_FW_LEFT_SIDE_LEN = 974; // 16 +const static uint64_t SH_FLD_23_FW_RIGHT_SIDE = 975; // 16 +const static uint64_t SH_FLD_23_FW_RIGHT_SIDE_LEN = 976; // 16 +const static uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0 = 977; // 8 +const static uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0_3 = 978; // 8 +const static uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0_3_LEN = 979; // 8 +const static uint64_t SH_FLD_23_HS_DLLMUX_SEL_0_0_LEN = 980; // 8 +const static uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0 = 981; // 8 +const static uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0_3 = 982; // 8 +const static uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0_3_LEN = 983; // 8 +const static uint64_t SH_FLD_23_HS_DLLMUX_SEL_1_0_LEN = 984; // 8 +const static uint64_t SH_FLD_23_HS_PROBE_A = 985; // 16 +const static uint64_t SH_FLD_23_HS_PROBE_A_LEN = 986; // 16 +const static uint64_t SH_FLD_23_HS_PROBE_B = 987; // 16 +const static uint64_t SH_FLD_23_HS_PROBE_B_LEN = 988; // 16 +const static uint64_t SH_FLD_23_HW_VALUE = 989; // 16 +const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N0 = 990; // 16 +const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N0_MASK = 991; // 16 +const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N1 = 992; // 16 +const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N1_MASK = 993; // 16 +const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N2 = 994; // 16 +const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N2_MASK = 995; // 16 +const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N3 = 996; // 16 +const static uint64_t SH_FLD_23_INCOMPLETE_CAL_N3_MASK = 997; // 16 +const static uint64_t SH_FLD_23_INIT_IO = 998; // 16 +const static uint64_t SH_FLD_23_INIT_RXDLL_CAL_RESET = 999; // 32 +const static uint64_t SH_FLD_23_INIT_RXDLL_CAL_UPDATE = 1000; // 32 +const static uint64_t SH_FLD_23_INTERP_SIG_SLEW = 1001; // 16 +const static uint64_t SH_FLD_23_INTERP_SIG_SLEW_LEN = 1002; // 16 +const static uint64_t SH_FLD_23_INVALID_NS_BIG_R = 1003; // 16 +const static uint64_t SH_FLD_23_INVALID_NS_BIG_R_MASK = 1004; // 16 +const static uint64_t SH_FLD_23_INVALID_NS_SMALL_L = 1005; // 16 +const static uint64_t SH_FLD_23_INVALID_NS_SMALL_L_MASK = 1006; // 16 +const static uint64_t SH_FLD_23_INVALID_NS_SMALL_R = 1007; // 16 +const static uint64_t SH_FLD_23_INVALID_NS_SMALL_R_MASK = 1008; // 16 +const static uint64_t SH_FLD_23_ITERATION_CNTR = 1009; // 16 +const static uint64_t SH_FLD_23_ITERATION_CNTR_LEN = 1010; // 16 +const static uint64_t SH_FLD_23_JUMP_BACK_RIGHT = 1011; // 16 +const static uint64_t SH_FLD_23_LANE__0_11_PD = 1012; // 16 +const static uint64_t SH_FLD_23_LANE__0_11_PD_LEN = 1013; // 16 +const static uint64_t SH_FLD_23_LANE__12_15_PD = 1014; // 16 +const static uint64_t SH_FLD_23_LANE__12_15_PD_LEN = 1015; // 16 +const static uint64_t SH_FLD_23_LEADING_EDGE_FOUND_MASK = 1016; // 16 +const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND = 1017; // 16 +const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15 = 1018; // 16 +const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_0_15_LEN = 1019; // 16 +const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23 = 1020; // 16 +const static uint64_t SH_FLD_23_LEADING_EDGE_NOT_FOUND_16_23_LEN = 1021; // 16 +const static uint64_t SH_FLD_23_LEN = 1022; // 112 +const static uint64_t SH_FLD_23_LOOPBACK_DLY12 = 1023; // 16 +const static uint64_t SH_FLD_23_LOOPBACK_FIX_EN = 1024; // 16 +const static uint64_t SH_FLD_23_MATCH_STEP_RIGHT = 1025; // 16 +const static uint64_t SH_FLD_23_MAX_DQS = 1026; // 16 +const static uint64_t SH_FLD_23_MAX_DQS_ITER = 1027; // 16 +const static uint64_t SH_FLD_23_MAX_DQS_LEN = 1028; // 16 +const static uint64_t SH_FLD_23_MEMINTD00 = 1029; // 16 +const static uint64_t SH_FLD_23_MEMINTD00_LEN = 1030; // 16 +const static uint64_t SH_FLD_23_MEMINTD01 = 1031; // 16 +const static uint64_t SH_FLD_23_MEMINTD01_LEN = 1032; // 16 +const static uint64_t SH_FLD_23_MEMINTD02 = 1033; // 16 +const static uint64_t SH_FLD_23_MEMINTD02_LEN = 1034; // 16 +const static uint64_t SH_FLD_23_MEMINTD03 = 1035; // 16 +const static uint64_t SH_FLD_23_MEMINTD03_LEN = 1036; // 16 +const static uint64_t SH_FLD_23_MEMINTD04 = 1037; // 16 +const static uint64_t SH_FLD_23_MEMINTD04_LEN = 1038; // 16 +const static uint64_t SH_FLD_23_MEMINTD05 = 1039; // 16 +const static uint64_t SH_FLD_23_MEMINTD05_LEN = 1040; // 16 +const static uint64_t SH_FLD_23_MEMINTD06 = 1041; // 16 +const static uint64_t SH_FLD_23_MEMINTD06_LEN = 1042; // 16 +const static uint64_t SH_FLD_23_MEMINTD07 = 1043; // 16 +const static uint64_t SH_FLD_23_MEMINTD07_LEN = 1044; // 16 +const static uint64_t SH_FLD_23_MEMINTD08 = 1045; // 16 +const static uint64_t SH_FLD_23_MEMINTD08_LEN = 1046; // 16 +const static uint64_t SH_FLD_23_MEMINTD09 = 1047; // 16 +const static uint64_t SH_FLD_23_MEMINTD09_LEN = 1048; // 16 +const static uint64_t SH_FLD_23_MEMINTD10 = 1049; // 16 +const static uint64_t SH_FLD_23_MEMINTD10_LEN = 1050; // 16 +const static uint64_t SH_FLD_23_MEMINTD11 = 1051; // 16 +const static uint64_t SH_FLD_23_MEMINTD11_LEN = 1052; // 16 +const static uint64_t SH_FLD_23_MEMINTD12 = 1053; // 16 +const static uint64_t SH_FLD_23_MEMINTD12_LEN = 1054; // 16 +const static uint64_t SH_FLD_23_MEMINTD13 = 1055; // 16 +const static uint64_t SH_FLD_23_MEMINTD13_LEN = 1056; // 16 +const static uint64_t SH_FLD_23_MEMINTD14 = 1057; // 16 +const static uint64_t SH_FLD_23_MEMINTD14_LEN = 1058; // 16 +const static uint64_t SH_FLD_23_MEMINTD15 = 1059; // 16 +const static uint64_t SH_FLD_23_MEMINTD15_LEN = 1060; // 16 +const static uint64_t SH_FLD_23_MEMINTD16 = 1061; // 16 +const static uint64_t SH_FLD_23_MEMINTD16_LEN = 1062; // 16 +const static uint64_t SH_FLD_23_MEMINTD17 = 1063; // 16 +const static uint64_t SH_FLD_23_MEMINTD17_LEN = 1064; // 16 +const static uint64_t SH_FLD_23_MEMINTD18 = 1065; // 16 +const static uint64_t SH_FLD_23_MEMINTD18_LEN = 1066; // 16 +const static uint64_t SH_FLD_23_MEMINTD19 = 1067; // 16 +const static uint64_t SH_FLD_23_MEMINTD19_LEN = 1068; // 16 +const static uint64_t SH_FLD_23_MEMINTD20 = 1069; // 16 +const static uint64_t SH_FLD_23_MEMINTD20_LEN = 1070; // 16 +const static uint64_t SH_FLD_23_MEMINTD21 = 1071; // 16 +const static uint64_t SH_FLD_23_MEMINTD21_LEN = 1072; // 16 +const static uint64_t SH_FLD_23_MEMINTD22 = 1073; // 16 +const static uint64_t SH_FLD_23_MEMINTD22_LEN = 1074; // 16 +const static uint64_t SH_FLD_23_MEMINTD23 = 1075; // 16 +const static uint64_t SH_FLD_23_MEMINTD23_LEN = 1076; // 16 +const static uint64_t SH_FLD_23_MIN_EYE = 1077; // 16 +const static uint64_t SH_FLD_23_MIN_EYE_MASK = 1078; // 16 +const static uint64_t SH_FLD_23_MIN_RD_EYE_SIZE = 1079; // 16 +const static uint64_t SH_FLD_23_MIN_RD_EYE_SIZE_LEN = 1080; // 16 +const static uint64_t SH_FLD_23_MRS_CMD_N0 = 1081; // 16 +const static uint64_t SH_FLD_23_MRS_CMD_N1 = 1082; // 16 +const static uint64_t SH_FLD_23_MRS_CMD_N2 = 1083; // 16 +const static uint64_t SH_FLD_23_MRS_CMD_N3 = 1084; // 16 +const static uint64_t SH_FLD_23_N0 = 1085; // 128 +const static uint64_t SH_FLD_23_N0_LEN = 1086; // 128 +const static uint64_t SH_FLD_23_N1 = 1087; // 128 +const static uint64_t SH_FLD_23_N1_LEN = 1088; // 128 +const static uint64_t SH_FLD_23_N2 = 1089; // 128 +const static uint64_t SH_FLD_23_N2_LEN = 1090; // 128 +const static uint64_t SH_FLD_23_N3 = 1091; // 128 +const static uint64_t SH_FLD_23_N3_LEN = 1092; // 128 +const static uint64_t SH_FLD_23_NIB0 = 1093; // 16 +const static uint64_t SH_FLD_23_NIB0TCFLIP_DC = 1094; // 16 +const static uint64_t SH_FLD_23_NIB0_LEN = 1095; // 16 +const static uint64_t SH_FLD_23_NIB1 = 1096; // 16 +const static uint64_t SH_FLD_23_NIB1TCFLIP_DC = 1097; // 16 +const static uint64_t SH_FLD_23_NIB1_LEN = 1098; // 16 +const static uint64_t SH_FLD_23_NIB2 = 1099; // 16 +const static uint64_t SH_FLD_23_NIB2TCFLIP_DC = 1100; // 16 +const static uint64_t SH_FLD_23_NIB2_LEN = 1101; // 16 +const static uint64_t SH_FLD_23_NIB3 = 1102; // 16 +const static uint64_t SH_FLD_23_NIB3TCFLIP_DC = 1103; // 16 +const static uint64_t SH_FLD_23_NIB3_LEN = 1104; // 16 +const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_CAP = 1105; // 16 +const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_CAP_LEN = 1106; // 16 +const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_RES = 1107; // 16 +const static uint64_t SH_FLD_23_NIB_0_2_DQSEL_RES_LEN = 1108; // 16 +const static uint64_t SH_FLD_23_NIB_0_DQSEL_CAP = 1109; // 16 +const static uint64_t SH_FLD_23_NIB_0_DQSEL_CAP_LEN = 1110; // 16 +const static uint64_t SH_FLD_23_NIB_0_DQSEL_RES = 1111; // 16 +const static uint64_t SH_FLD_23_NIB_0_DQSEL_RES_LEN = 1112; // 16 +const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_CAP = 1113; // 16 +const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_CAP_LEN = 1114; // 16 +const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_RES = 1115; // 16 +const static uint64_t SH_FLD_23_NIB_1_3_DQSEL_RES_LEN = 1116; // 16 +const static uint64_t SH_FLD_23_NIB_1_DQSEL_CAP = 1117; // 16 +const static uint64_t SH_FLD_23_NIB_1_DQSEL_CAP_LEN = 1118; // 16 +const static uint64_t SH_FLD_23_NIB_1_DQSEL_RES = 1119; // 16 +const static uint64_t SH_FLD_23_NIB_1_DQSEL_RES_LEN = 1120; // 16 +const static uint64_t SH_FLD_23_NO_DQS = 1121; // 16 +const static uint64_t SH_FLD_23_NO_DQS_MASK = 1122; // 16 +const static uint64_t SH_FLD_23_NO_EYE_DETECTED = 1123; // 16 +const static uint64_t SH_FLD_23_NO_EYE_DETECTED_MASK = 1124; // 16 +const static uint64_t SH_FLD_23_NO_LOCK = 1125; // 16 +const static uint64_t SH_FLD_23_NO_LOCK_MASK = 1126; // 16 +const static uint64_t SH_FLD_23_OFFSET0 = 1127; // 16 +const static uint64_t SH_FLD_23_OFFSET0_LEN = 1128; // 16 +const static uint64_t SH_FLD_23_OFFSET1 = 1129; // 16 +const static uint64_t SH_FLD_23_OFFSET1_LEN = 1130; // 16 +const static uint64_t SH_FLD_23_OFFSET2 = 1131; // 32 +const static uint64_t SH_FLD_23_OFFSET2_LEN = 1132; // 32 +const static uint64_t SH_FLD_23_OFFSET3 = 1133; // 32 +const static uint64_t SH_FLD_23_OFFSET3_LEN = 1134; // 32 +const static uint64_t SH_FLD_23_OFFSET4 = 1135; // 32 +const static uint64_t SH_FLD_23_OFFSET4_LEN = 1136; // 32 +const static uint64_t SH_FLD_23_OFFSET5 = 1137; // 32 +const static uint64_t SH_FLD_23_OFFSET5_LEN = 1138; // 32 +const static uint64_t SH_FLD_23_OFFSET6 = 1139; // 32 +const static uint64_t SH_FLD_23_OFFSET6_LEN = 1140; // 32 +const static uint64_t SH_FLD_23_OFFSET7 = 1141; // 32 +const static uint64_t SH_FLD_23_OFFSET7_LEN = 1142; // 32 +const static uint64_t SH_FLD_23_OFFSET_ERR = 1143; // 16 +const static uint64_t SH_FLD_23_OFFSET_ERR_MASK = 1144; // 16 +const static uint64_t SH_FLD_23_OPERATE_MODE = 1145; // 16 +const static uint64_t SH_FLD_23_OPERATE_MODE_LEN = 1146; // 16 +const static uint64_t SH_FLD_23_PERCAL_PWR_DIS = 1147; // 16 +const static uint64_t SH_FLD_23_PER_CAL_UPDATE_DISABLE = 1148; // 16 +const static uint64_t SH_FLD_23_PHASE_ALIGN_RESET = 1149; // 32 +const static uint64_t SH_FLD_23_PHASE_CNTL_EN = 1150; // 32 +const static uint64_t SH_FLD_23_PHASE_DEFAULT_EN = 1151; // 32 +const static uint64_t SH_FLD_23_POS_EDGE_ALIGN = 1152; // 32 +const static uint64_t SH_FLD_23_QUAD0 = 1153; // 16 +const static uint64_t SH_FLD_23_QUAD0_CLK16 = 1154; // 128 +const static uint64_t SH_FLD_23_QUAD0_CLK18 = 1155; // 128 +const static uint64_t SH_FLD_23_QUAD0_LEN = 1156; // 16 +const static uint64_t SH_FLD_23_QUAD1 = 1157; // 16 +const static uint64_t SH_FLD_23_QUAD1_CLK16 = 1158; // 128 +const static uint64_t SH_FLD_23_QUAD1_CLK18 = 1159; // 128 +const static uint64_t SH_FLD_23_QUAD1_LEN = 1160; // 16 +const static uint64_t SH_FLD_23_QUAD2 = 1161; // 16 +const static uint64_t SH_FLD_23_QUAD2_CLK16 = 1162; // 128 +const static uint64_t SH_FLD_23_QUAD2_CLK18 = 1163; // 64 +const static uint64_t SH_FLD_23_QUAD2_CLK20 = 1164; // 128 +const static uint64_t SH_FLD_23_QUAD2_CLK22 = 1165; // 128 +const static uint64_t SH_FLD_23_QUAD2_LEN = 1166; // 16 +const static uint64_t SH_FLD_23_QUAD3 = 1167; // 16 +const static uint64_t SH_FLD_23_QUAD3_CLK16 = 1168; // 128 +const static uint64_t SH_FLD_23_QUAD3_CLK18 = 1169; // 64 +const static uint64_t SH_FLD_23_QUAD3_CLK20 = 1170; // 128 +const static uint64_t SH_FLD_23_QUAD3_CLK22 = 1171; // 128 +const static uint64_t SH_FLD_23_QUAD3_LEN = 1172; // 16 +const static uint64_t SH_FLD_23_RANGE_DRAM0 = 1173; // 64 +const static uint64_t SH_FLD_23_RANGE_DRAM1 = 1174; // 64 +const static uint64_t SH_FLD_23_RANGE_DRAM2 = 1175; // 64 +const static uint64_t SH_FLD_23_RANGE_DRAM3 = 1176; // 64 +const static uint64_t SH_FLD_23_RD = 1177; // 272 +const static uint64_t SH_FLD_23_RDCLK_SELECT0 = 1178; // 64 +const static uint64_t SH_FLD_23_RDCLK_SELECT0_LEN = 1179; // 64 +const static uint64_t SH_FLD_23_RDCLK_SELECT1 = 1180; // 64 +const static uint64_t SH_FLD_23_RDCLK_SELECT1_LEN = 1181; // 64 +const static uint64_t SH_FLD_23_RDCLK_SELECT2 = 1182; // 64 +const static uint64_t SH_FLD_23_RDCLK_SELECT2_LEN = 1183; // 64 +const static uint64_t SH_FLD_23_RDCLK_SELECT3 = 1184; // 64 +const static uint64_t SH_FLD_23_RDCLK_SELECT3_LEN = 1185; // 64 +const static uint64_t SH_FLD_23_RD_DELAY0 = 1186; // 112 +const static uint64_t SH_FLD_23_RD_DELAY0_LEN = 1187; // 112 +const static uint64_t SH_FLD_23_RD_DELAY1 = 1188; // 112 +const static uint64_t SH_FLD_23_RD_DELAY1_LEN = 1189; // 112 +const static uint64_t SH_FLD_23_RD_DELAY2 = 1190; // 112 +const static uint64_t SH_FLD_23_RD_DELAY2_LEN = 1191; // 112 +const static uint64_t SH_FLD_23_RD_DELAY3 = 1192; // 112 +const static uint64_t SH_FLD_23_RD_DELAY3_LEN = 1193; // 112 +const static uint64_t SH_FLD_23_RD_DELAY4 = 1194; // 112 +const static uint64_t SH_FLD_23_RD_DELAY4_LEN = 1195; // 112 +const static uint64_t SH_FLD_23_RD_DELAY5 = 1196; // 112 +const static uint64_t SH_FLD_23_RD_DELAY5_LEN = 1197; // 112 +const static uint64_t SH_FLD_23_RD_DELAY6 = 1198; // 112 +const static uint64_t SH_FLD_23_RD_DELAY6_LEN = 1199; // 112 +const static uint64_t SH_FLD_23_RD_DELAY7 = 1200; // 112 +const static uint64_t SH_FLD_23_RD_DELAY7_LEN = 1201; // 112 +const static uint64_t SH_FLD_23_RD_LEN = 1202; // 272 +const static uint64_t SH_FLD_23_RD_SIZE0 = 1203; // 176 +const static uint64_t SH_FLD_23_RD_SIZE0_LEN = 1204; // 176 +const static uint64_t SH_FLD_23_RD_SIZE1 = 1205; // 176 +const static uint64_t SH_FLD_23_RD_SIZE1_LEN = 1206; // 176 +const static uint64_t SH_FLD_23_RD_SIZE2 = 1207; // 176 +const static uint64_t SH_FLD_23_RD_SIZE2_LEN = 1208; // 176 +const static uint64_t SH_FLD_23_RD_SIZE3 = 1209; // 176 +const static uint64_t SH_FLD_23_RD_SIZE3_LEN = 1210; // 176 +const static uint64_t SH_FLD_23_RD_SIZE4 = 1211; // 176 +const static uint64_t SH_FLD_23_RD_SIZE4_LEN = 1212; // 176 +const static uint64_t SH_FLD_23_RD_SIZE5 = 1213; // 176 +const static uint64_t SH_FLD_23_RD_SIZE5_LEN = 1214; // 176 +const static uint64_t SH_FLD_23_RD_SIZE6 = 1215; // 176 +const static uint64_t SH_FLD_23_RD_SIZE6_LEN = 1216; // 176 +const static uint64_t SH_FLD_23_RD_SIZE7 = 1217; // 176 +const static uint64_t SH_FLD_23_RD_SIZE7_LEN = 1218; // 176 +const static uint64_t SH_FLD_23_READ_CENTERING_MODE = 1219; // 16 +const static uint64_t SH_FLD_23_READ_CENTERING_MODE_LEN = 1220; // 16 +const static uint64_t SH_FLD_23_REFERENCE1 = 1221; // 16 +const static uint64_t SH_FLD_23_REFERENCE1_LEN = 1222; // 16 +const static uint64_t SH_FLD_23_REFERENCE2 = 1223; // 16 +const static uint64_t SH_FLD_23_REFERENCE2_LEN = 1224; // 16 +const static uint64_t SH_FLD_23_REFERENCE3 = 1225; // 16 +const static uint64_t SH_FLD_23_REFERENCE3_LEN = 1226; // 16 +const static uint64_t SH_FLD_23_REGS_RXDLL_CAL_SKIP = 1227; // 32 +const static uint64_t SH_FLD_23_REGS_RXDLL_CAL_SKIP_LEN = 1228; // 32 +const static uint64_t SH_FLD_23_REGS_RXDLL_COARSE_ADJ_BY2 = 1229; // 32 +const static uint64_t SH_FLD_23_REGS_RXDLL_COARSE_EN = 1230; // 32 +const static uint64_t SH_FLD_23_REGS_RXDLL_COARSE_EN_LEN = 1231; // 32 +const static uint64_t SH_FLD_23_REGS_RXDLL_DAC_COARSE = 1232; // 32 +const static uint64_t SH_FLD_23_REGS_RXDLL_DAC_COARSE_LEN = 1233; // 32 +const static uint64_t SH_FLD_23_REGS_RXDLL_VREG_LOWER = 1234; // 32 +const static uint64_t SH_FLD_23_REGS_RXDLL_VREG_LOWER_LEN = 1235; // 32 +const static uint64_t SH_FLD_23_REGS_RXDLL_VREG_UPPER = 1236; // 32 +const static uint64_t SH_FLD_23_REGS_RXDLL_VREG_UPPER_LEN = 1237; // 32 +const static uint64_t SH_FLD_23_RESERVED = 1238; // 6 +const static uint64_t SH_FLD_23_RESERVED_50_52 = 1239; // 32 +const static uint64_t SH_FLD_23_RESERVED_50_52_LEN = 1240; // 32 +const static uint64_t SH_FLD_23_RESERVED_56_63 = 1241; // 16 +const static uint64_t SH_FLD_23_RESERVED_56_63_LEN = 1242; // 16 +const static uint64_t SH_FLD_23_RESERVED_58_60 = 1243; // 32 +const static uint64_t SH_FLD_23_RESERVED_58_60_LEN = 1244; // 32 +const static uint64_t SH_FLD_23_ROT0 = 1245; // 16 +const static uint64_t SH_FLD_23_ROT0_LEN = 1246; // 16 +const static uint64_t SH_FLD_23_ROT1 = 1247; // 16 +const static uint64_t SH_FLD_23_ROT1_LEN = 1248; // 16 +const static uint64_t SH_FLD_23_ROT_CLK_N0 = 1249; // 128 +const static uint64_t SH_FLD_23_ROT_CLK_N0_LEN = 1250; // 128 +const static uint64_t SH_FLD_23_ROT_CLK_N1 = 1251; // 128 +const static uint64_t SH_FLD_23_ROT_CLK_N1_LEN = 1252; // 128 +const static uint64_t SH_FLD_23_ROT_N0 = 1253; // 128 +const static uint64_t SH_FLD_23_ROT_N0_LEN = 1254; // 128 +const static uint64_t SH_FLD_23_ROT_N1 = 1255; // 128 +const static uint64_t SH_FLD_23_ROT_N1_LEN = 1256; // 128 +const static uint64_t SH_FLD_23_ROT_OVERRIDE = 1257; // 32 +const static uint64_t SH_FLD_23_ROT_OVERRIDE_EN = 1258; // 32 +const static uint64_t SH_FLD_23_ROT_OVERRIDE_LEN = 1259; // 32 +const static uint64_t SH_FLD_23_RXREG_COMPCON_DC = 1260; // 32 +const static uint64_t SH_FLD_23_RXREG_COMPCON_DC_LEN = 1261; // 32 +const static uint64_t SH_FLD_23_RXREG_CON_DC = 1262; // 32 +const static uint64_t SH_FLD_23_RXREG_DAC_PULLUP_DC = 1263; // 32 +const static uint64_t SH_FLD_23_RXREG_DRVCON_DC = 1264; // 32 +const static uint64_t SH_FLD_23_RXREG_DRVCON_DC_LEN = 1265; // 32 +const static uint64_t SH_FLD_23_RXREG_FILTER_LENGTH_DC = 1266; // 32 +const static uint64_t SH_FLD_23_RXREG_FILTER_LENGTH_DC_LEN = 1267; // 32 +const static uint64_t SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC = 1268; // 32 +const static uint64_t SH_FLD_23_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 1269; // 32 +const static uint64_t SH_FLD_23_RXREG_REF_SEL_DC = 1270; // 32 +const static uint64_t SH_FLD_23_RXREG_REF_SEL_DC_LEN = 1271; // 32 +const static uint64_t SH_FLD_23_S0ACENSLICENDRV_DC = 1272; // 16 +const static uint64_t SH_FLD_23_S0ACENSLICENDRV_DC_LEN = 1273; // 16 +const static uint64_t SH_FLD_23_S0ACENSLICEPDRV_DC = 1274; // 16 +const static uint64_t SH_FLD_23_S0ACENSLICEPDRV_DC_LEN = 1275; // 16 +const static uint64_t SH_FLD_23_S0ACENSLICEPTERM_DC = 1276; // 16 +const static uint64_t SH_FLD_23_S0ACENSLICEPTERM_DC_LEN = 1277; // 16 +const static uint64_t SH_FLD_23_S0INSDLYTAP = 1278; // 16 +const static uint64_t SH_FLD_23_S1ACENSLICENDRV_DC = 1279; // 16 +const static uint64_t SH_FLD_23_S1ACENSLICENDRV_DC_LEN = 1280; // 16 +const static uint64_t SH_FLD_23_S1ACENSLICEPDRV_DC = 1281; // 16 +const static uint64_t SH_FLD_23_S1ACENSLICEPDRV_DC_LEN = 1282; // 16 +const static uint64_t SH_FLD_23_S1ACENSLICEPTERM_DC = 1283; // 16 +const static uint64_t SH_FLD_23_S1ACENSLICEPTERM_DC_LEN = 1284; // 16 +const static uint64_t SH_FLD_23_S1INSDLYTAP = 1285; // 16 +const static uint64_t SH_FLD_23_SEL0 = 1286; // 32 +const static uint64_t SH_FLD_23_SEL0_LEN = 1287; // 16 +const static uint64_t SH_FLD_23_SEL1 = 1288; // 32 +const static uint64_t SH_FLD_23_SEL10 = 1289; // 32 +const static uint64_t SH_FLD_23_SEL10_LEN = 1290; // 32 +const static uint64_t SH_FLD_23_SEL11 = 1291; // 32 +const static uint64_t SH_FLD_23_SEL11_LEN = 1292; // 32 +const static uint64_t SH_FLD_23_SEL12 = 1293; // 32 +const static uint64_t SH_FLD_23_SEL12_LEN = 1294; // 32 +const static uint64_t SH_FLD_23_SEL13 = 1295; // 32 +const static uint64_t SH_FLD_23_SEL13_LEN = 1296; // 32 +const static uint64_t SH_FLD_23_SEL14 = 1297; // 32 +const static uint64_t SH_FLD_23_SEL14_LEN = 1298; // 32 +const static uint64_t SH_FLD_23_SEL15 = 1299; // 32 +const static uint64_t SH_FLD_23_SEL15_LEN = 1300; // 32 +const static uint64_t SH_FLD_23_SEL1_LEN = 1301; // 32 +const static uint64_t SH_FLD_23_SEL2 = 1302; // 32 +const static uint64_t SH_FLD_23_SEL2_LEN = 1303; // 32 +const static uint64_t SH_FLD_23_SEL3 = 1304; // 32 +const static uint64_t SH_FLD_23_SEL3_LEN = 1305; // 32 +const static uint64_t SH_FLD_23_SEL4 = 1306; // 32 +const static uint64_t SH_FLD_23_SEL4_LEN = 1307; // 32 +const static uint64_t SH_FLD_23_SEL5 = 1308; // 32 +const static uint64_t SH_FLD_23_SEL5_LEN = 1309; // 32 +const static uint64_t SH_FLD_23_SEL6 = 1310; // 32 +const static uint64_t SH_FLD_23_SEL6_LEN = 1311; // 32 +const static uint64_t SH_FLD_23_SEL7 = 1312; // 32 +const static uint64_t SH_FLD_23_SEL7_LEN = 1313; // 32 +const static uint64_t SH_FLD_23_SEL8 = 1314; // 32 +const static uint64_t SH_FLD_23_SEL8_LEN = 1315; // 16 +const static uint64_t SH_FLD_23_SEL9 = 1316; // 32 +const static uint64_t SH_FLD_23_SEL9_LEN = 1317; // 32 +const static uint64_t SH_FLD_23_SEL_A = 1318; // 16 +const static uint64_t SH_FLD_23_SEL_A_LEN = 1319; // 16 +const static uint64_t SH_FLD_23_SEL_B = 1320; // 16 +const static uint64_t SH_FLD_23_SEL_B_LEN = 1321; // 16 +const static uint64_t SH_FLD_23_SMALL_STEP_LEFT = 1322; // 16 +const static uint64_t SH_FLD_23_SMALL_STEP_RIGHT = 1323; // 16 +const static uint64_t SH_FLD_23_SPARE_OSC = 1324; // 3 +const static uint64_t SH_FLD_23_SPARE_PLL_CONTROL = 1325; // 3 +const static uint64_t SH_FLD_23_SPARE_RESONANT_CLOCKING_CONTROL = 1326; // 3 +const static uint64_t SH_FLD_23_SPARE_TEST = 1327; // 3 +const static uint64_t SH_FLD_23_SYNC = 1328; // 16 +const static uint64_t SH_FLD_23_SYNC_LEN = 1329; // 16 +const static uint64_t SH_FLD_23_SYSCLK_DQSCLK_OFFSET = 1330; // 16 +const static uint64_t SH_FLD_23_SYSCLK_DQSCLK_OFFSET_LEN = 1331; // 16 +const static uint64_t SH_FLD_23_SYSCLK_RDCLK_OFFSET = 1332; // 16 +const static uint64_t SH_FLD_23_SYSCLK_RDCLK_OFFSET_LEN = 1333; // 16 +const static uint64_t SH_FLD_23_TEST_4TO1_MODE = 1334; // 16 +const static uint64_t SH_FLD_23_TEST_CHECK_EN = 1335; // 16 +const static uint64_t SH_FLD_23_TEST_CLEAR_ERROR = 1336; // 16 +const static uint64_t SH_FLD_23_TEST_DATA_EN = 1337; // 16 +const static uint64_t SH_FLD_23_TEST_GEN_EN = 1338; // 16 +const static uint64_t SH_FLD_23_TEST_LANE_PAIR_FAIL = 1339; // 16 +const static uint64_t SH_FLD_23_TEST_LANE_PAIR_FAIL_LEN = 1340; // 16 +const static uint64_t SH_FLD_23_TEST_MODE = 1341; // 16 +const static uint64_t SH_FLD_23_TEST_MODE_LEN = 1342; // 16 +const static uint64_t SH_FLD_23_TEST_RESET = 1343; // 16 +const static uint64_t SH_FLD_23_TRAILING_EDGE_FOUND_MASK = 1344; // 16 +const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND = 1345; // 16 +const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15 = 1346; // 16 +const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 1347; // 16 +const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23 = 1348; // 16 +const static uint64_t SH_FLD_23_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 1349; // 16 +const static uint64_t SH_FLD_23_TRIG_PERIOD = 1350; // 16 +const static uint64_t SH_FLD_23_TSYS = 1351; // 16 +const static uint64_t SH_FLD_23_TSYS_LEN = 1352; // 16 +const static uint64_t SH_FLD_23_VALID_NS_BIG_L = 1353; // 16 +const static uint64_t SH_FLD_23_VALID_NS_BIG_L_MASK = 1354; // 16 +const static uint64_t SH_FLD_23_VALID_NS_BIG_R = 1355; // 16 +const static uint64_t SH_FLD_23_VALID_NS_BIG_R_MASK = 1356; // 16 +const static uint64_t SH_FLD_23_VALID_NS_JUMP_BACK = 1357; // 16 +const static uint64_t SH_FLD_23_VALID_NS_JUMP_BACK_MASK = 1358; // 16 +const static uint64_t SH_FLD_23_VALUE_DRAM0 = 1359; // 64 +const static uint64_t SH_FLD_23_VALUE_DRAM0_LEN = 1360; // 64 +const static uint64_t SH_FLD_23_VALUE_DRAM1 = 1361; // 64 +const static uint64_t SH_FLD_23_VALUE_DRAM1_LEN = 1362; // 64 +const static uint64_t SH_FLD_23_VALUE_DRAM2 = 1363; // 64 +const static uint64_t SH_FLD_23_VALUE_DRAM2_LEN = 1364; // 64 +const static uint64_t SH_FLD_23_VALUE_DRAM3 = 1365; // 64 +const static uint64_t SH_FLD_23_VALUE_DRAM3_LEN = 1366; // 64 +const static uint64_t SH_FLD_23_WL_ADVANCE_DISABLE = 1367; // 16 +const static uint64_t SH_FLD_23_WL_ERR_CLK16 = 1368; // 32 +const static uint64_t SH_FLD_23_WL_ERR_CLK16_MASK = 1369; // 16 +const static uint64_t SH_FLD_23_WL_ERR_CLK18 = 1370; // 32 +const static uint64_t SH_FLD_23_WL_ERR_CLK18_MASK = 1371; // 16 +const static uint64_t SH_FLD_23_WL_ERR_CLK20 = 1372; // 32 +const static uint64_t SH_FLD_23_WL_ERR_CLK20_MASK = 1373; // 16 +const static uint64_t SH_FLD_23_WL_ERR_CLK22 = 1374; // 32 +const static uint64_t SH_FLD_23_WRAPSEL = 1375; // 16 +const static uint64_t SH_FLD_23_WTRFL_AVE_DIS = 1376; // 16 +const static uint64_t SH_FLD_23_ZERO_DETECTED = 1377; // 16 +const static uint64_t SH_FLD_24 = 1378; // 6 +const static uint64_t SH_FLD_24_RESERVED = 1379; // 6 +const static uint64_t SH_FLD_24_SPARE_CBS_CONTROL = 1380; // 3 +const static uint64_t SH_FLD_24_SPARE_OSC = 1381; // 3 +const static uint64_t SH_FLD_24_SPARE_RESONANT_CLOCKING_CONTROL = 1382; // 3 +const static uint64_t SH_FLD_25 = 1383; // 6 +const static uint64_t SH_FLD_256K = 1384; // 12 +const static uint64_t SH_FLD_25_SPARE_CBS_CONTROL = 1385; // 3 +const static uint64_t SH_FLD_25_SPARE_CLKIN_CONTROL = 1386; // 3 +const static uint64_t SH_FLD_25_SPARE_OSC = 1387; // 3 +const static uint64_t SH_FLD_25_SPARE_REFCLOCK_CONTROL = 1388; // 3 +const static uint64_t SH_FLD_25_SPARE_RESONANT_CLOCKING_CONTROL = 1389; // 3 +const static uint64_t SH_FLD_26 = 1390; // 6 +const static uint64_t SH_FLD_26_FREE_USAGE = 1391; // 3 +const static uint64_t SH_FLD_26_SPARE_CBS_CONTROL = 1392; // 3 +const static uint64_t SH_FLD_26_SPARE_CLKIN_CONTROL = 1393; // 3 +const static uint64_t SH_FLD_26_SPARE_OSC = 1394; // 3 +const static uint64_t SH_FLD_26_SPARE_REFCLOCK_CONTROL = 1395; // 3 +const static uint64_t SH_FLD_26_SPARE_RESONANT_CLOCKING_CONTROL = 1396; // 3 +const static uint64_t SH_FLD_27 = 1397; // 6 +const static uint64_t SH_FLD_27_FREE_USAGE = 1398; // 3 +const static uint64_t SH_FLD_27_SPARE_CBS_CONTROL = 1399; // 3 +const static uint64_t SH_FLD_27_SPARE_CLKIN_CONTROL = 1400; // 3 +const static uint64_t SH_FLD_27_SPARE_OSC = 1401; // 3 +const static uint64_t SH_FLD_27_SPARE_RESONANT_CLOCKING_CONTROL = 1402; // 3 +const static uint64_t SH_FLD_28 = 1403; // 6 +const static uint64_t SH_FLD_28_FREE_USAGE = 1404; // 3 +const static uint64_t SH_FLD_28_RESERVED_FOR_HTB = 1405; // 3 +const static uint64_t SH_FLD_28_SPARE_OSC = 1406; // 3 +const static uint64_t SH_FLD_28_SPARE_RESET = 1407; // 3 +const static uint64_t SH_FLD_28_SPARE_RESONANT_CLOCKING_CONTROL = 1408; // 3 +const static uint64_t SH_FLD_28_SPARE_TEST_CONTROL = 1409; // 3 +const static uint64_t SH_FLD_29 = 1410; // 6 +const static uint64_t SH_FLD_29_FREE_USAGE = 1411; // 3 +const static uint64_t SH_FLD_29_RESERVED_FOR_HTB = 1412; // 3 +const static uint64_t SH_FLD_29_SPARE_OSC = 1413; // 3 +const static uint64_t SH_FLD_29_SPARE_REFCLOCK_CONTROL = 1414; // 3 +const static uint64_t SH_FLD_29_SPARE_RESET = 1415; // 3 +const static uint64_t SH_FLD_29_SPARE_RESONANT_CLOCKING_CONTROL = 1416; // 3 +const static uint64_t SH_FLD_29_SPARE_TEST_CONTROL = 1417; // 3 +const static uint64_t SH_FLD_2_CANNED_0 = 1418; // 2 +const static uint64_t SH_FLD_2_CANNED_0_LEN = 1419; // 2 +const static uint64_t SH_FLD_2_CANNED_1 = 1420; // 2 +const static uint64_t SH_FLD_2_CANNED_1_LEN = 1421; // 2 +const static uint64_t SH_FLD_2_DATA = 1422; // 1 +const static uint64_t SH_FLD_2_DATA_LEN = 1423; // 1 +const static uint64_t SH_FLD_2_LEN = 1424; // 46 +const static uint64_t SH_FLD_2_RESERVED = 1425; // 3 +const static uint64_t SH_FLD_2_SPARE_SECTOR_BUFFER_CONTROL = 1426; // 3 +const static uint64_t SH_FLD_3 = 1427; // 466 +const static uint64_t SH_FLD_30 = 1428; // 6 +const static uint64_t SH_FLD_30_FREE_USAGE = 1429; // 3 +const static uint64_t SH_FLD_30_RESERVED = 1430; // 3 +const static uint64_t SH_FLD_30_RESERVED_FOR_HTB = 1431; // 3 +const static uint64_t SH_FLD_30_SPARE_OSC = 1432; // 3 +const static uint64_t SH_FLD_30_SPARE_REFCLOCK_CONTROL = 1433; // 3 +const static uint64_t SH_FLD_30_SPARE_RESONANT_CLOCKING_CONTROL = 1434; // 3 +const static uint64_t SH_FLD_30_SPARE_TEST_CONTROL = 1435; // 3 +const static uint64_t SH_FLD_31 = 1436; // 6 +const static uint64_t SH_FLD_31_FREE_USAGE = 1437; // 3 +const static uint64_t SH_FLD_31_RESERVED_FOR_HTB = 1438; // 3 +const static uint64_t SH_FLD_31_SPARE_OSC = 1439; // 3 +const static uint64_t SH_FLD_31_SPARE_REFCLOCK_CONTROL = 1440; // 3 +const static uint64_t SH_FLD_31_SPARE_RESONANT_CLOCKING_CONTROL = 1441; // 3 +const static uint64_t SH_FLD_31_SPARE_TEST_CONTROL = 1442; // 3 +const static uint64_t SH_FLD_3_DATA = 1443; // 1 +const static uint64_t SH_FLD_3_DATA_LEN = 1444; // 1 +const static uint64_t SH_FLD_3_LEN = 1445; // 46 +const static uint64_t SH_FLD_3_RESERVED = 1446; // 3 +const static uint64_t SH_FLD_3_SPARE_SECTOR_BUFFER_CONTROL = 1447; // 3 +const static uint64_t SH_FLD_3_SPARE_SS_PLL_CONTROL = 1448; // 3 +const static uint64_t SH_FLD_4 = 1449; // 510 +const static uint64_t SH_FLD_4X4_MODE = 1450; // 2 +const static uint64_t SH_FLD_4_ADVANCE_PING_PONG = 1451; // 8 +const static uint64_t SH_FLD_4_ADVANCE_PR_VALUE = 1452; // 8 +const static uint64_t SH_FLD_4_ATESTSEL_0 = 1453; // 8 +const static uint64_t SH_FLD_4_ATESTSEL_0_LEN = 1454; // 8 +const static uint64_t SH_FLD_4_ATEST_SEL_0_1 = 1455; // 8 +const static uint64_t SH_FLD_4_ATEST_SEL_0_1_LEN = 1456; // 8 +const static uint64_t SH_FLD_4_BB_LOCK0 = 1457; // 8 +const static uint64_t SH_FLD_4_BB_LOCK1 = 1458; // 8 +const static uint64_t SH_FLD_4_BIG_STEP_RIGHT = 1459; // 8 +const static uint64_t SH_FLD_4_BIT_CENTERED = 1460; // 8 +const static uint64_t SH_FLD_4_BIT_CENTERED_LEN = 1461; // 8 +const static uint64_t SH_FLD_4_BLFIFO_DIS = 1462; // 8 +const static uint64_t SH_FLD_4_BUMP = 1463; // 8 +const static uint64_t SH_FLD_4_CALGATE_ON = 1464; // 8 +const static uint64_t SH_FLD_4_CALIBRATE_BIT = 1465; // 8 +const static uint64_t SH_FLD_4_CALIBRATE_BIT_LEN = 1466; // 8 +const static uint64_t SH_FLD_4_CAL_CKTS_ACTIVE = 1467; // 16 +const static uint64_t SH_FLD_4_CAL_ERROR = 1468; // 16 +const static uint64_t SH_FLD_4_CAL_ERROR_FINE = 1469; // 16 +const static uint64_t SH_FLD_4_CAL_GOOD = 1470; // 16 +const static uint64_t SH_FLD_4_CHECKER_ENABLE = 1471; // 8 +const static uint64_t SH_FLD_4_CHECKER_RESET = 1472; // 8 +const static uint64_t SH_FLD_4_CLK16_SINGLE_ENDED = 1473; // 64 +const static uint64_t SH_FLD_4_CLK18_SINGLE_ENDED = 1474; // 64 +const static uint64_t SH_FLD_4_CLK20_SINGLE_ENDED = 1475; // 64 +const static uint64_t SH_FLD_4_CLK22_SINGLE_ENDED = 1476; // 64 +const static uint64_t SH_FLD_4_CLK_LEVEL = 1477; // 8 +const static uint64_t SH_FLD_4_CLK_LEVEL_LEN = 1478; // 8 +const static uint64_t SH_FLD_4_CNTL_POL = 1479; // 8 +const static uint64_t SH_FLD_4_CNTL_SRC = 1480; // 8 +const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N0 = 1481; // 8 +const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N0_MASK = 1482; // 8 +const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N1 = 1483; // 8 +const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N1_MASK = 1484; // 8 +const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N2 = 1485; // 8 +const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N2_MASK = 1486; // 8 +const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N3 = 1487; // 8 +const static uint64_t SH_FLD_4_COARSE_PATTERN_ERR_N3_MASK = 1488; // 8 +const static uint64_t SH_FLD_4_CONTINUOUS_UPDATE = 1489; // 16 +const static uint64_t SH_FLD_4_CTR_1D_CHICKEN_SWITCH = 1490; // 8 +const static uint64_t SH_FLD_4_CTR_2D_SMALL_STEP_VAL = 1491; // 8 +const static uint64_t SH_FLD_4_CTR_2D_SMALL_STEP_VAL_LEN = 1492; // 8 +const static uint64_t SH_FLD_4_CTR_3D_BIG_STEP_VAL = 1493; // 8 +const static uint64_t SH_FLD_4_CTR_3D_BIG_STEP_VAL_LEN = 1494; // 8 +const static uint64_t SH_FLD_4_CTR_CUR = 1495; // 8 +const static uint64_t SH_FLD_4_CTR_CUR_LEN = 1496; // 8 +const static uint64_t SH_FLD_4_CTR_NUM_BITS_TO_SKIP = 1497; // 8 +const static uint64_t SH_FLD_4_CTR_NUM_BITS_TO_SKIP_LEN = 1498; // 8 +const static uint64_t SH_FLD_4_CTR_NUM_NO_INC_COMP = 1499; // 8 +const static uint64_t SH_FLD_4_CTR_NUM_NO_INC_COMP_LEN = 1500; // 8 +const static uint64_t SH_FLD_4_CTR_NUM_VREFREQ_CNT = 1501; // 8 +const static uint64_t SH_FLD_4_CTR_NUM_VREFREQ_CNT_LEN = 1502; // 8 +const static uint64_t SH_FLD_4_CTR_NUM_WRRDREQ_CNT = 1503; // 8 +const static uint64_t SH_FLD_4_CTR_NUM_WRRDREQ_CNT_LEN = 1504; // 8 +const static uint64_t SH_FLD_4_CTR_RANGE_CROSSOVER = 1505; // 8 +const static uint64_t SH_FLD_4_CTR_RANGE_CROSSOVER_LEN = 1506; // 8 +const static uint64_t SH_FLD_4_CTR_RANGE_SEL = 1507; // 32 +const static uint64_t SH_FLD_4_CTR_RANGE_SELECT = 1508; // 8 +const static uint64_t SH_FLD_4_CTR_RUN_FULL_1D = 1509; // 8 +const static uint64_t SH_FLD_4_CTR_SINGLE_RANGE_MAX = 1510; // 8 +const static uint64_t SH_FLD_4_CTR_SINGLE_RANGE_MAX_LEN = 1511; // 8 +const static uint64_t SH_FLD_4_DD2_DQS_FIX_DIS = 1512; // 8 +const static uint64_t SH_FLD_4_DD2_FIX_DIS = 1513; // 8 +const static uint64_t SH_FLD_4_DD2_WTRFL_SYNC_DIS = 1514; // 8 +const static uint64_t SH_FLD_4_DELAYG = 1515; // 608 +const static uint64_t SH_FLD_4_DELAYG_LEN = 1516; // 608 +const static uint64_t SH_FLD_4_DELAY_PING_PONG_HALF = 1517; // 8 +const static uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH = 1518; // 8 +const static uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_HIGH_LEN = 1519; // 8 +const static uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW = 1520; // 8 +const static uint64_t SH_FLD_4_DESIRED_EDGE_CNTR_TARGET_LOW_LEN = 1521; // 8 +const static uint64_t SH_FLD_4_DFT_FORCE_OUTPUTS = 1522; // 8 +const static uint64_t SH_FLD_4_DFT_PRBS7_GEN_EN = 1523; // 8 +const static uint64_t SH_FLD_4_DIGITAL_EN = 1524; // 8 +const static uint64_t SH_FLD_4_DIR_0_15 = 1525; // 8 +const static uint64_t SH_FLD_4_DIR_0_15_LEN = 1526; // 8 +const static uint64_t SH_FLD_4_DISABLE_0_15 = 1527; // 32 +const static uint64_t SH_FLD_4_DISABLE_0_15_LEN = 1528; // 32 +const static uint64_t SH_FLD_4_DISABLE_16_23 = 1529; // 32 +const static uint64_t SH_FLD_4_DISABLE_16_23_LEN = 1530; // 32 +const static uint64_t SH_FLD_4_DISABLE_PING_PONG = 1531; // 8 +const static uint64_t SH_FLD_4_DISABLE_TERMINATION = 1532; // 8 +const static uint64_t SH_FLD_4_DIS_CLK_GATE = 1533; // 8 +const static uint64_t SH_FLD_4_DLL_ADJUST = 1534; // 16 +const static uint64_t SH_FLD_4_DLL_ADJUST_LEN = 1535; // 16 +const static uint64_t SH_FLD_4_DLL_COMPARE_OUT = 1536; // 16 +const static uint64_t SH_FLD_4_DLL_CORRECT_EN = 1537; // 16 +const static uint64_t SH_FLD_4_DLL_ITER_A = 1538; // 16 +const static uint64_t SH_FLD_4_DL_FORCE_ON = 1539; // 8 +const static uint64_t SH_FLD_4_DONE = 1540; // 16 +const static uint64_t SH_FLD_4_DQS = 1541; // 8 +const static uint64_t SH_FLD_4_DQSCLK_SELECT0 = 1542; // 32 +const static uint64_t SH_FLD_4_DQSCLK_SELECT0_LEN = 1543; // 32 +const static uint64_t SH_FLD_4_DQSCLK_SELECT1 = 1544; // 32 +const static uint64_t SH_FLD_4_DQSCLK_SELECT1_LEN = 1545; // 32 +const static uint64_t SH_FLD_4_DQSCLK_SELECT2 = 1546; // 32 +const static uint64_t SH_FLD_4_DQSCLK_SELECT2_LEN = 1547; // 32 +const static uint64_t SH_FLD_4_DQSCLK_SELECT3 = 1548; // 32 +const static uint64_t SH_FLD_4_DQSCLK_SELECT3_LEN = 1549; // 32 +const static uint64_t SH_FLD_4_DQS_ALIGN_CNTR = 1550; // 8 +const static uint64_t SH_FLD_4_DQS_ALIGN_CNTR_LEN = 1551; // 8 +const static uint64_t SH_FLD_4_DQS_ALIGN_FIX_DIS = 1552; // 8 +const static uint64_t SH_FLD_4_DQS_ALIGN_JITTER = 1553; // 8 +const static uint64_t SH_FLD_4_DQS_ALIGN_QUAD = 1554; // 8 +const static uint64_t SH_FLD_4_DQS_ALIGN_QUAD_LEN = 1555; // 8 +const static uint64_t SH_FLD_4_DQS_ALIGN_SM = 1556; // 8 +const static uint64_t SH_FLD_4_DQS_ALIGN_SM_LEN = 1557; // 8 +const static uint64_t SH_FLD_4_DQS_LEN = 1558; // 8 +const static uint64_t SH_FLD_4_DQS_PIPE_FIX_DIS = 1559; // 8 +const static uint64_t SH_FLD_4_DQS_PIPE_FIX_DIS_LEN = 1560; // 8 +const static uint64_t SH_FLD_4_DQS_QUAD_CONFIG = 1561; // 8 +const static uint64_t SH_FLD_4_DQS_QUAD_CONFIG_LEN = 1562; // 8 +const static uint64_t SH_FLD_4_DRIFT_ERROR = 1563; // 8 +const static uint64_t SH_FLD_4_DRIFT_MASK = 1564; // 8 +const static uint64_t SH_FLD_4_DRVREN_MODE = 1565; // 16 +const static uint64_t SH_FLD_4_DYN_MCTERM_CNTL_EN = 1566; // 8 +const static uint64_t SH_FLD_4_DYN_POWER_CNTL_EN = 1567; // 8 +const static uint64_t SH_FLD_4_DYN_RX_GATE_CNTL_EN = 1568; // 8 +const static uint64_t SH_FLD_4_ENABLE_0_15 = 1569; // 8 +const static uint64_t SH_FLD_4_ENABLE_0_15_LEN = 1570; // 8 +const static uint64_t SH_FLD_4_ENABLE_16_23 = 1571; // 8 +const static uint64_t SH_FLD_4_ENABLE_16_23_LEN = 1572; // 8 +const static uint64_t SH_FLD_4_EN_DQS_OFFSET = 1573; // 8 +const static uint64_t SH_FLD_4_EN_DRIVER_INVFB_DC = 1574; // 16 +const static uint64_t SH_FLD_4_EN_N_WR = 1575; // 8 +const static uint64_t SH_FLD_4_EN_N_WR_LEN = 1576; // 8 +const static uint64_t SH_FLD_4_EN_P_WR = 1577; // 16 +const static uint64_t SH_FLD_4_EN_P_WR_LEN = 1578; // 16 +const static uint64_t SH_FLD_4_ERROR = 1579; // 8 +const static uint64_t SH_FLD_4_ERROR_LEN = 1580; // 8 +const static uint64_t SH_FLD_4_ERR_CLK22_MASK = 1581; // 8 +const static uint64_t SH_FLD_4_EYE_CLIPPING = 1582; // 8 +const static uint64_t SH_FLD_4_EYE_CLIPPING_MASK = 1583; // 8 +const static uint64_t SH_FLD_4_FINE_STEPPING = 1584; // 8 +const static uint64_t SH_FLD_4_FLUSH = 1585; // 8 +const static uint64_t SH_FLD_4_FORCE_DQS_LANES_ON = 1586; // 8 +const static uint64_t SH_FLD_4_FORCE_FIFO_CAPTURE = 1587; // 8 +const static uint64_t SH_FLD_4_FRZSULV = 1588; // 16 +const static uint64_t SH_FLD_4_FW_LEFT_SIDE = 1589; // 8 +const static uint64_t SH_FLD_4_FW_LEFT_SIDE_LEN = 1590; // 8 +const static uint64_t SH_FLD_4_FW_RIGHT_SIDE = 1591; // 8 +const static uint64_t SH_FLD_4_FW_RIGHT_SIDE_LEN = 1592; // 8 +const static uint64_t SH_FLD_4_HS_DLLMUX_SEL_0_0_3 = 1593; // 8 +const static uint64_t SH_FLD_4_HS_DLLMUX_SEL_0_0_3_LEN = 1594; // 8 +const static uint64_t SH_FLD_4_HS_DLLMUX_SEL_1_0_3 = 1595; // 8 +const static uint64_t SH_FLD_4_HS_DLLMUX_SEL_1_0_3_LEN = 1596; // 8 +const static uint64_t SH_FLD_4_HS_PROBE_A = 1597; // 8 +const static uint64_t SH_FLD_4_HS_PROBE_A_LEN = 1598; // 8 +const static uint64_t SH_FLD_4_HS_PROBE_B = 1599; // 8 +const static uint64_t SH_FLD_4_HS_PROBE_B_LEN = 1600; // 8 +const static uint64_t SH_FLD_4_HW_VALUE = 1601; // 8 +const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N0 = 1602; // 8 +const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N0_MASK = 1603; // 8 +const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N1 = 1604; // 8 +const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N1_MASK = 1605; // 8 +const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N2 = 1606; // 8 +const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N2_MASK = 1607; // 8 +const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N3 = 1608; // 8 +const static uint64_t SH_FLD_4_INCOMPLETE_CAL_N3_MASK = 1609; // 8 +const static uint64_t SH_FLD_4_INIT_IO = 1610; // 8 +const static uint64_t SH_FLD_4_INIT_RXDLL_CAL_RESET = 1611; // 16 +const static uint64_t SH_FLD_4_INIT_RXDLL_CAL_UPDATE = 1612; // 16 +const static uint64_t SH_FLD_4_INTERP_SIG_SLEW = 1613; // 8 +const static uint64_t SH_FLD_4_INTERP_SIG_SLEW_LEN = 1614; // 8 +const static uint64_t SH_FLD_4_INVALID_NS_BIG_R = 1615; // 8 +const static uint64_t SH_FLD_4_INVALID_NS_BIG_R_MASK = 1616; // 8 +const static uint64_t SH_FLD_4_INVALID_NS_SMALL_L = 1617; // 8 +const static uint64_t SH_FLD_4_INVALID_NS_SMALL_L_MASK = 1618; // 8 +const static uint64_t SH_FLD_4_INVALID_NS_SMALL_R = 1619; // 8 +const static uint64_t SH_FLD_4_INVALID_NS_SMALL_R_MASK = 1620; // 8 +const static uint64_t SH_FLD_4_ITERATION_CNTR = 1621; // 8 +const static uint64_t SH_FLD_4_ITERATION_CNTR_LEN = 1622; // 8 +const static uint64_t SH_FLD_4_JUMP_BACK_RIGHT = 1623; // 8 +const static uint64_t SH_FLD_4_LEADING_EDGE_FOUND_MASK = 1624; // 8 +const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND = 1625; // 8 +const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15 = 1626; // 8 +const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_0_15_LEN = 1627; // 8 +const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23 = 1628; // 8 +const static uint64_t SH_FLD_4_LEADING_EDGE_NOT_FOUND_16_23_LEN = 1629; // 8 +const static uint64_t SH_FLD_4_LEN = 1630; // 92 +const static uint64_t SH_FLD_4_LOOPBACK_DLY12 = 1631; // 8 +const static uint64_t SH_FLD_4_LOOPBACK_FIX_EN = 1632; // 8 +const static uint64_t SH_FLD_4_MATCH_STEP_RIGHT = 1633; // 8 +const static uint64_t SH_FLD_4_MAX_DQS = 1634; // 8 +const static uint64_t SH_FLD_4_MAX_DQS_ITER = 1635; // 8 +const static uint64_t SH_FLD_4_MAX_DQS_LEN = 1636; // 8 +const static uint64_t SH_FLD_4_MEMINTD00 = 1637; // 8 +const static uint64_t SH_FLD_4_MEMINTD00_LEN = 1638; // 8 +const static uint64_t SH_FLD_4_MEMINTD01 = 1639; // 8 +const static uint64_t SH_FLD_4_MEMINTD01_LEN = 1640; // 8 +const static uint64_t SH_FLD_4_MEMINTD02 = 1641; // 8 +const static uint64_t SH_FLD_4_MEMINTD02_LEN = 1642; // 8 +const static uint64_t SH_FLD_4_MEMINTD03 = 1643; // 8 +const static uint64_t SH_FLD_4_MEMINTD03_LEN = 1644; // 8 +const static uint64_t SH_FLD_4_MEMINTD04 = 1645; // 8 +const static uint64_t SH_FLD_4_MEMINTD04_LEN = 1646; // 8 +const static uint64_t SH_FLD_4_MEMINTD05 = 1647; // 8 +const static uint64_t SH_FLD_4_MEMINTD05_LEN = 1648; // 8 +const static uint64_t SH_FLD_4_MEMINTD06 = 1649; // 8 +const static uint64_t SH_FLD_4_MEMINTD06_LEN = 1650; // 8 +const static uint64_t SH_FLD_4_MEMINTD07 = 1651; // 8 +const static uint64_t SH_FLD_4_MEMINTD07_LEN = 1652; // 8 +const static uint64_t SH_FLD_4_MEMINTD08 = 1653; // 8 +const static uint64_t SH_FLD_4_MEMINTD08_LEN = 1654; // 8 +const static uint64_t SH_FLD_4_MEMINTD09 = 1655; // 8 +const static uint64_t SH_FLD_4_MEMINTD09_LEN = 1656; // 8 +const static uint64_t SH_FLD_4_MEMINTD10 = 1657; // 8 +const static uint64_t SH_FLD_4_MEMINTD10_LEN = 1658; // 8 +const static uint64_t SH_FLD_4_MEMINTD11 = 1659; // 8 +const static uint64_t SH_FLD_4_MEMINTD11_LEN = 1660; // 8 +const static uint64_t SH_FLD_4_MEMINTD12 = 1661; // 8 +const static uint64_t SH_FLD_4_MEMINTD12_LEN = 1662; // 8 +const static uint64_t SH_FLD_4_MEMINTD13 = 1663; // 8 +const static uint64_t SH_FLD_4_MEMINTD13_LEN = 1664; // 8 +const static uint64_t SH_FLD_4_MEMINTD14 = 1665; // 8 +const static uint64_t SH_FLD_4_MEMINTD14_LEN = 1666; // 8 +const static uint64_t SH_FLD_4_MEMINTD15 = 1667; // 8 +const static uint64_t SH_FLD_4_MEMINTD15_LEN = 1668; // 8 +const static uint64_t SH_FLD_4_MEMINTD16 = 1669; // 8 +const static uint64_t SH_FLD_4_MEMINTD16_LEN = 1670; // 8 +const static uint64_t SH_FLD_4_MEMINTD17 = 1671; // 8 +const static uint64_t SH_FLD_4_MEMINTD17_LEN = 1672; // 8 +const static uint64_t SH_FLD_4_MEMINTD18 = 1673; // 8 +const static uint64_t SH_FLD_4_MEMINTD18_LEN = 1674; // 8 +const static uint64_t SH_FLD_4_MEMINTD19 = 1675; // 8 +const static uint64_t SH_FLD_4_MEMINTD19_LEN = 1676; // 8 +const static uint64_t SH_FLD_4_MEMINTD20 = 1677; // 8 +const static uint64_t SH_FLD_4_MEMINTD20_LEN = 1678; // 8 +const static uint64_t SH_FLD_4_MEMINTD21 = 1679; // 8 +const static uint64_t SH_FLD_4_MEMINTD21_LEN = 1680; // 8 +const static uint64_t SH_FLD_4_MEMINTD22 = 1681; // 8 +const static uint64_t SH_FLD_4_MEMINTD22_LEN = 1682; // 8 +const static uint64_t SH_FLD_4_MEMINTD23 = 1683; // 8 +const static uint64_t SH_FLD_4_MEMINTD23_LEN = 1684; // 8 +const static uint64_t SH_FLD_4_MIN_EYE = 1685; // 8 +const static uint64_t SH_FLD_4_MIN_EYE_MASK = 1686; // 8 +const static uint64_t SH_FLD_4_MIN_RD_EYE_SIZE = 1687; // 8 +const static uint64_t SH_FLD_4_MIN_RD_EYE_SIZE_LEN = 1688; // 8 +const static uint64_t SH_FLD_4_MRS_CMD_N0 = 1689; // 8 +const static uint64_t SH_FLD_4_MRS_CMD_N1 = 1690; // 8 +const static uint64_t SH_FLD_4_MRS_CMD_N2 = 1691; // 8 +const static uint64_t SH_FLD_4_MRS_CMD_N3 = 1692; // 8 +const static uint64_t SH_FLD_4_N0 = 1693; // 64 +const static uint64_t SH_FLD_4_N0_LEN = 1694; // 64 +const static uint64_t SH_FLD_4_N1 = 1695; // 64 +const static uint64_t SH_FLD_4_N1_LEN = 1696; // 64 +const static uint64_t SH_FLD_4_N2 = 1697; // 64 +const static uint64_t SH_FLD_4_N2_LEN = 1698; // 64 +const static uint64_t SH_FLD_4_N3 = 1699; // 64 +const static uint64_t SH_FLD_4_N3_LEN = 1700; // 64 +const static uint64_t SH_FLD_4_NIB0 = 1701; // 8 +const static uint64_t SH_FLD_4_NIB0TCFLIP_DC = 1702; // 8 +const static uint64_t SH_FLD_4_NIB0_LEN = 1703; // 8 +const static uint64_t SH_FLD_4_NIB1 = 1704; // 8 +const static uint64_t SH_FLD_4_NIB1TCFLIP_DC = 1705; // 8 +const static uint64_t SH_FLD_4_NIB1_LEN = 1706; // 8 +const static uint64_t SH_FLD_4_NIB2 = 1707; // 8 +const static uint64_t SH_FLD_4_NIB2TCFLIP_DC = 1708; // 8 +const static uint64_t SH_FLD_4_NIB2_LEN = 1709; // 8 +const static uint64_t SH_FLD_4_NIB3 = 1710; // 8 +const static uint64_t SH_FLD_4_NIB3TCFLIP_DC = 1711; // 8 +const static uint64_t SH_FLD_4_NIB3_LEN = 1712; // 8 +const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_CAP = 1713; // 16 +const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_CAP_LEN = 1714; // 16 +const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_RES = 1715; // 16 +const static uint64_t SH_FLD_4_NIB_0_2_DQSEL_RES_LEN = 1716; // 16 +const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_CAP = 1717; // 16 +const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_CAP_LEN = 1718; // 16 +const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_RES = 1719; // 16 +const static uint64_t SH_FLD_4_NIB_1_3_DQSEL_RES_LEN = 1720; // 16 +const static uint64_t SH_FLD_4_NO_DQS = 1721; // 8 +const static uint64_t SH_FLD_4_NO_DQS_MASK = 1722; // 8 +const static uint64_t SH_FLD_4_NO_EYE_DETECTED = 1723; // 8 +const static uint64_t SH_FLD_4_NO_EYE_DETECTED_MASK = 1724; // 8 +const static uint64_t SH_FLD_4_NO_LOCK = 1725; // 8 +const static uint64_t SH_FLD_4_NO_LOCK_MASK = 1726; // 8 +const static uint64_t SH_FLD_4_OFFSET0 = 1727; // 8 +const static uint64_t SH_FLD_4_OFFSET0_LEN = 1728; // 8 +const static uint64_t SH_FLD_4_OFFSET1 = 1729; // 8 +const static uint64_t SH_FLD_4_OFFSET1_LEN = 1730; // 8 +const static uint64_t SH_FLD_4_OFFSET2 = 1731; // 16 +const static uint64_t SH_FLD_4_OFFSET2_LEN = 1732; // 16 +const static uint64_t SH_FLD_4_OFFSET3 = 1733; // 16 +const static uint64_t SH_FLD_4_OFFSET3_LEN = 1734; // 16 +const static uint64_t SH_FLD_4_OFFSET4 = 1735; // 16 +const static uint64_t SH_FLD_4_OFFSET4_LEN = 1736; // 16 +const static uint64_t SH_FLD_4_OFFSET5 = 1737; // 16 +const static uint64_t SH_FLD_4_OFFSET5_LEN = 1738; // 16 +const static uint64_t SH_FLD_4_OFFSET6 = 1739; // 16 +const static uint64_t SH_FLD_4_OFFSET6_LEN = 1740; // 16 +const static uint64_t SH_FLD_4_OFFSET7 = 1741; // 16 +const static uint64_t SH_FLD_4_OFFSET7_LEN = 1742; // 16 +const static uint64_t SH_FLD_4_OFFSET_ERR = 1743; // 8 +const static uint64_t SH_FLD_4_OFFSET_ERR_MASK = 1744; // 8 +const static uint64_t SH_FLD_4_OPERATE_MODE = 1745; // 8 +const static uint64_t SH_FLD_4_OPERATE_MODE_LEN = 1746; // 8 +const static uint64_t SH_FLD_4_PERCAL_PWR_DIS = 1747; // 8 +const static uint64_t SH_FLD_4_PER_CAL_UPDATE_DISABLE = 1748; // 8 +const static uint64_t SH_FLD_4_PHASE_ALIGN_RESET = 1749; // 16 +const static uint64_t SH_FLD_4_PHASE_CNTL_EN = 1750; // 16 +const static uint64_t SH_FLD_4_PHASE_DEFAULT_EN = 1751; // 16 +const static uint64_t SH_FLD_4_POS_EDGE_ALIGN = 1752; // 16 +const static uint64_t SH_FLD_4_QUAD0 = 1753; // 8 +const static uint64_t SH_FLD_4_QUAD0_CLK16 = 1754; // 64 +const static uint64_t SH_FLD_4_QUAD0_CLK18 = 1755; // 64 +const static uint64_t SH_FLD_4_QUAD0_LEN = 1756; // 8 +const static uint64_t SH_FLD_4_QUAD1 = 1757; // 8 +const static uint64_t SH_FLD_4_QUAD1_CLK16 = 1758; // 64 +const static uint64_t SH_FLD_4_QUAD1_CLK18 = 1759; // 64 +const static uint64_t SH_FLD_4_QUAD1_LEN = 1760; // 8 +const static uint64_t SH_FLD_4_QUAD2 = 1761; // 8 +const static uint64_t SH_FLD_4_QUAD2_CLK16 = 1762; // 64 +const static uint64_t SH_FLD_4_QUAD2_CLK18 = 1763; // 32 +const static uint64_t SH_FLD_4_QUAD2_CLK20 = 1764; // 64 +const static uint64_t SH_FLD_4_QUAD2_CLK22 = 1765; // 64 +const static uint64_t SH_FLD_4_QUAD2_LEN = 1766; // 8 +const static uint64_t SH_FLD_4_QUAD3 = 1767; // 8 +const static uint64_t SH_FLD_4_QUAD3_CLK16 = 1768; // 64 +const static uint64_t SH_FLD_4_QUAD3_CLK18 = 1769; // 32 +const static uint64_t SH_FLD_4_QUAD3_CLK20 = 1770; // 64 +const static uint64_t SH_FLD_4_QUAD3_CLK22 = 1771; // 64 +const static uint64_t SH_FLD_4_QUAD3_LEN = 1772; // 8 +const static uint64_t SH_FLD_4_RANGE_DRAM0 = 1773; // 32 +const static uint64_t SH_FLD_4_RANGE_DRAM1 = 1774; // 32 +const static uint64_t SH_FLD_4_RANGE_DRAM2 = 1775; // 32 +const static uint64_t SH_FLD_4_RANGE_DRAM3 = 1776; // 32 +const static uint64_t SH_FLD_4_RD = 1777; // 136 +const static uint64_t SH_FLD_4_RDCLK_SELECT0 = 1778; // 32 +const static uint64_t SH_FLD_4_RDCLK_SELECT0_LEN = 1779; // 32 +const static uint64_t SH_FLD_4_RDCLK_SELECT1 = 1780; // 32 +const static uint64_t SH_FLD_4_RDCLK_SELECT1_LEN = 1781; // 32 +const static uint64_t SH_FLD_4_RDCLK_SELECT2 = 1782; // 32 +const static uint64_t SH_FLD_4_RDCLK_SELECT2_LEN = 1783; // 32 +const static uint64_t SH_FLD_4_RDCLK_SELECT3 = 1784; // 32 +const static uint64_t SH_FLD_4_RDCLK_SELECT3_LEN = 1785; // 32 +const static uint64_t SH_FLD_4_RD_DELAY0 = 1786; // 56 +const static uint64_t SH_FLD_4_RD_DELAY0_LEN = 1787; // 56 +const static uint64_t SH_FLD_4_RD_DELAY1 = 1788; // 56 +const static uint64_t SH_FLD_4_RD_DELAY1_LEN = 1789; // 56 +const static uint64_t SH_FLD_4_RD_DELAY2 = 1790; // 56 +const static uint64_t SH_FLD_4_RD_DELAY2_LEN = 1791; // 56 +const static uint64_t SH_FLD_4_RD_DELAY3 = 1792; // 56 +const static uint64_t SH_FLD_4_RD_DELAY3_LEN = 1793; // 56 +const static uint64_t SH_FLD_4_RD_DELAY4 = 1794; // 56 +const static uint64_t SH_FLD_4_RD_DELAY4_LEN = 1795; // 56 +const static uint64_t SH_FLD_4_RD_DELAY5 = 1796; // 56 +const static uint64_t SH_FLD_4_RD_DELAY5_LEN = 1797; // 56 +const static uint64_t SH_FLD_4_RD_DELAY6 = 1798; // 56 +const static uint64_t SH_FLD_4_RD_DELAY6_LEN = 1799; // 56 +const static uint64_t SH_FLD_4_RD_DELAY7 = 1800; // 56 +const static uint64_t SH_FLD_4_RD_DELAY7_LEN = 1801; // 56 +const static uint64_t SH_FLD_4_RD_LEN = 1802; // 136 +const static uint64_t SH_FLD_4_RD_SIZE0 = 1803; // 88 +const static uint64_t SH_FLD_4_RD_SIZE0_LEN = 1804; // 88 +const static uint64_t SH_FLD_4_RD_SIZE1 = 1805; // 88 +const static uint64_t SH_FLD_4_RD_SIZE1_LEN = 1806; // 88 +const static uint64_t SH_FLD_4_RD_SIZE2 = 1807; // 88 +const static uint64_t SH_FLD_4_RD_SIZE2_LEN = 1808; // 88 +const static uint64_t SH_FLD_4_RD_SIZE3 = 1809; // 88 +const static uint64_t SH_FLD_4_RD_SIZE3_LEN = 1810; // 88 +const static uint64_t SH_FLD_4_RD_SIZE4 = 1811; // 88 +const static uint64_t SH_FLD_4_RD_SIZE4_LEN = 1812; // 88 +const static uint64_t SH_FLD_4_RD_SIZE5 = 1813; // 88 +const static uint64_t SH_FLD_4_RD_SIZE5_LEN = 1814; // 88 +const static uint64_t SH_FLD_4_RD_SIZE6 = 1815; // 88 +const static uint64_t SH_FLD_4_RD_SIZE6_LEN = 1816; // 88 +const static uint64_t SH_FLD_4_RD_SIZE7 = 1817; // 88 +const static uint64_t SH_FLD_4_RD_SIZE7_LEN = 1818; // 88 +const static uint64_t SH_FLD_4_READ_CENTERING_MODE = 1819; // 8 +const static uint64_t SH_FLD_4_READ_CENTERING_MODE_LEN = 1820; // 8 +const static uint64_t SH_FLD_4_REFERENCE1 = 1821; // 8 +const static uint64_t SH_FLD_4_REFERENCE1_LEN = 1822; // 8 +const static uint64_t SH_FLD_4_REFERENCE2 = 1823; // 8 +const static uint64_t SH_FLD_4_REFERENCE2_LEN = 1824; // 8 +const static uint64_t SH_FLD_4_REFERENCE3 = 1825; // 8 +const static uint64_t SH_FLD_4_REFERENCE3_LEN = 1826; // 8 +const static uint64_t SH_FLD_4_REGS_RXDLL_CAL_SKIP = 1827; // 16 +const static uint64_t SH_FLD_4_REGS_RXDLL_CAL_SKIP_LEN = 1828; // 16 +const static uint64_t SH_FLD_4_REGS_RXDLL_COARSE_ADJ_BY2 = 1829; // 16 +const static uint64_t SH_FLD_4_REGS_RXDLL_COARSE_EN = 1830; // 16 +const static uint64_t SH_FLD_4_REGS_RXDLL_COARSE_EN_LEN = 1831; // 16 +const static uint64_t SH_FLD_4_REGS_RXDLL_DAC_COARSE = 1832; // 16 +const static uint64_t SH_FLD_4_REGS_RXDLL_DAC_COARSE_LEN = 1833; // 16 +const static uint64_t SH_FLD_4_REGS_RXDLL_VREG_LOWER = 1834; // 16 +const static uint64_t SH_FLD_4_REGS_RXDLL_VREG_LOWER_LEN = 1835; // 16 +const static uint64_t SH_FLD_4_REGS_RXDLL_VREG_UPPER = 1836; // 16 +const static uint64_t SH_FLD_4_REGS_RXDLL_VREG_UPPER_LEN = 1837; // 16 +const static uint64_t SH_FLD_4_RESERVED = 1838; // 3 +const static uint64_t SH_FLD_4_RESERVED_50_52 = 1839; // 16 +const static uint64_t SH_FLD_4_RESERVED_50_52_LEN = 1840; // 16 +const static uint64_t SH_FLD_4_RESERVED_56_63 = 1841; // 8 +const static uint64_t SH_FLD_4_RESERVED_56_63_LEN = 1842; // 8 +const static uint64_t SH_FLD_4_RESERVED_58_60 = 1843; // 16 +const static uint64_t SH_FLD_4_RESERVED_58_60_LEN = 1844; // 16 +const static uint64_t SH_FLD_4_ROT0 = 1845; // 8 +const static uint64_t SH_FLD_4_ROT0_LEN = 1846; // 8 +const static uint64_t SH_FLD_4_ROT1 = 1847; // 8 +const static uint64_t SH_FLD_4_ROT1_LEN = 1848; // 8 +const static uint64_t SH_FLD_4_ROT_CLK_N0 = 1849; // 64 +const static uint64_t SH_FLD_4_ROT_CLK_N0_LEN = 1850; // 64 +const static uint64_t SH_FLD_4_ROT_CLK_N1 = 1851; // 64 +const static uint64_t SH_FLD_4_ROT_CLK_N1_LEN = 1852; // 64 +const static uint64_t SH_FLD_4_ROT_N0 = 1853; // 64 +const static uint64_t SH_FLD_4_ROT_N0_LEN = 1854; // 64 +const static uint64_t SH_FLD_4_ROT_N1 = 1855; // 64 +const static uint64_t SH_FLD_4_ROT_N1_LEN = 1856; // 64 +const static uint64_t SH_FLD_4_ROT_OVERRIDE = 1857; // 16 +const static uint64_t SH_FLD_4_ROT_OVERRIDE_EN = 1858; // 16 +const static uint64_t SH_FLD_4_ROT_OVERRIDE_LEN = 1859; // 16 +const static uint64_t SH_FLD_4_RXREG_COMPCON_DC = 1860; // 16 +const static uint64_t SH_FLD_4_RXREG_COMPCON_DC_LEN = 1861; // 16 +const static uint64_t SH_FLD_4_RXREG_CON_DC = 1862; // 16 +const static uint64_t SH_FLD_4_RXREG_DAC_PULLUP_DC = 1863; // 16 +const static uint64_t SH_FLD_4_RXREG_DRVCON_DC = 1864; // 16 +const static uint64_t SH_FLD_4_RXREG_DRVCON_DC_LEN = 1865; // 16 +const static uint64_t SH_FLD_4_RXREG_FILTER_LENGTH_DC = 1866; // 16 +const static uint64_t SH_FLD_4_RXREG_FILTER_LENGTH_DC_LEN = 1867; // 16 +const static uint64_t SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC = 1868; // 16 +const static uint64_t SH_FLD_4_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 1869; // 16 +const static uint64_t SH_FLD_4_RXREG_REF_SEL_DC = 1870; // 16 +const static uint64_t SH_FLD_4_RXREG_REF_SEL_DC_LEN = 1871; // 16 +const static uint64_t SH_FLD_4_S0ACENSLICENDRV_DC = 1872; // 8 +const static uint64_t SH_FLD_4_S0ACENSLICENDRV_DC_LEN = 1873; // 8 +const static uint64_t SH_FLD_4_S0ACENSLICEPDRV_DC = 1874; // 8 +const static uint64_t SH_FLD_4_S0ACENSLICEPDRV_DC_LEN = 1875; // 8 +const static uint64_t SH_FLD_4_S0ACENSLICEPTERM_DC = 1876; // 8 +const static uint64_t SH_FLD_4_S0ACENSLICEPTERM_DC_LEN = 1877; // 8 +const static uint64_t SH_FLD_4_S0INSDLYTAP = 1878; // 8 +const static uint64_t SH_FLD_4_S1ACENSLICENDRV_DC = 1879; // 8 +const static uint64_t SH_FLD_4_S1ACENSLICENDRV_DC_LEN = 1880; // 8 +const static uint64_t SH_FLD_4_S1ACENSLICEPDRV_DC = 1881; // 8 +const static uint64_t SH_FLD_4_S1ACENSLICEPDRV_DC_LEN = 1882; // 8 +const static uint64_t SH_FLD_4_S1ACENSLICEPTERM_DC = 1883; // 8 +const static uint64_t SH_FLD_4_S1ACENSLICEPTERM_DC_LEN = 1884; // 8 +const static uint64_t SH_FLD_4_S1INSDLYTAP = 1885; // 8 +const static uint64_t SH_FLD_4_SEL_A = 1886; // 8 +const static uint64_t SH_FLD_4_SEL_A_LEN = 1887; // 8 +const static uint64_t SH_FLD_4_SEL_B = 1888; // 8 +const static uint64_t SH_FLD_4_SEL_B_LEN = 1889; // 8 +const static uint64_t SH_FLD_4_SEND_ENABLE = 1890; // 1 +const static uint64_t SH_FLD_4_SEND_MODE = 1891; // 1 +const static uint64_t SH_FLD_4_SMALL_STEP_LEFT = 1892; // 8 +const static uint64_t SH_FLD_4_SMALL_STEP_RIGHT = 1893; // 8 +const static uint64_t SH_FLD_4_SPARE_SECTOR_BUFFER_CONTROL = 1894; // 3 +const static uint64_t SH_FLD_4_SYNC = 1895; // 8 +const static uint64_t SH_FLD_4_SYNC_LEN = 1896; // 8 +const static uint64_t SH_FLD_4_SYSCLK_DQSCLK_OFFSET = 1897; // 8 +const static uint64_t SH_FLD_4_SYSCLK_DQSCLK_OFFSET_LEN = 1898; // 8 +const static uint64_t SH_FLD_4_SYSCLK_RDCLK_OFFSET = 1899; // 8 +const static uint64_t SH_FLD_4_SYSCLK_RDCLK_OFFSET_LEN = 1900; // 8 +const static uint64_t SH_FLD_4_TRAILING_EDGE_FOUND_MASK = 1901; // 8 +const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND = 1902; // 8 +const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15 = 1903; // 8 +const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_0_15_LEN = 1904; // 8 +const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23 = 1905; // 8 +const static uint64_t SH_FLD_4_TRAILING_EDGE_NOT_FOUND_16_23_LEN = 1906; // 8 +const static uint64_t SH_FLD_4_TRIG_PERIOD = 1907; // 8 +const static uint64_t SH_FLD_4_TSYS = 1908; // 8 +const static uint64_t SH_FLD_4_TSYS_LEN = 1909; // 8 +const static uint64_t SH_FLD_4_VALID_NS_BIG_L = 1910; // 8 +const static uint64_t SH_FLD_4_VALID_NS_BIG_L_MASK = 1911; // 8 +const static uint64_t SH_FLD_4_VALID_NS_BIG_R = 1912; // 8 +const static uint64_t SH_FLD_4_VALID_NS_BIG_R_MASK = 1913; // 8 +const static uint64_t SH_FLD_4_VALID_NS_JUMP_BACK = 1914; // 8 +const static uint64_t SH_FLD_4_VALID_NS_JUMP_BACK_MASK = 1915; // 8 +const static uint64_t SH_FLD_4_VALUE_DRAM0 = 1916; // 32 +const static uint64_t SH_FLD_4_VALUE_DRAM0_LEN = 1917; // 32 +const static uint64_t SH_FLD_4_VALUE_DRAM1 = 1918; // 32 +const static uint64_t SH_FLD_4_VALUE_DRAM1_LEN = 1919; // 32 +const static uint64_t SH_FLD_4_VALUE_DRAM2 = 1920; // 32 +const static uint64_t SH_FLD_4_VALUE_DRAM2_LEN = 1921; // 32 +const static uint64_t SH_FLD_4_VALUE_DRAM3 = 1922; // 32 +const static uint64_t SH_FLD_4_VALUE_DRAM3_LEN = 1923; // 32 +const static uint64_t SH_FLD_4_WL_ADVANCE_DISABLE = 1924; // 8 +const static uint64_t SH_FLD_4_WL_ERR_CLK16 = 1925; // 16 +const static uint64_t SH_FLD_4_WL_ERR_CLK16_MASK = 1926; // 8 +const static uint64_t SH_FLD_4_WL_ERR_CLK18 = 1927; // 16 +const static uint64_t SH_FLD_4_WL_ERR_CLK18_MASK = 1928; // 8 +const static uint64_t SH_FLD_4_WL_ERR_CLK20 = 1929; // 16 +const static uint64_t SH_FLD_4_WL_ERR_CLK20_MASK = 1930; // 8 +const static uint64_t SH_FLD_4_WL_ERR_CLK22 = 1931; // 16 +const static uint64_t SH_FLD_4_WRAPSEL = 1932; // 8 +const static uint64_t SH_FLD_4_WTRFL_AVE_DIS = 1933; // 8 +const static uint64_t SH_FLD_4_ZERO_DETECTED = 1934; // 8 +const static uint64_t SH_FLD_5 = 1935; // 455 +const static uint64_t SH_FLD_5_LEN = 1936; // 43 +const static uint64_t SH_FLD_5_RESERVED = 1937; // 3 +const static uint64_t SH_FLD_5_SPARE_SECTOR_BUFFER_CONTROL = 1938; // 3 +const static uint64_t SH_FLD_6 = 1939; // 455 +const static uint64_t SH_FLD_6_LEN = 1940; // 43 +const static uint64_t SH_FLD_6_RESERVED = 1941; // 3 +const static uint64_t SH_FLD_6_SPARE_SECTOR_BUFFER_CONTROL = 1942; // 3 +const static uint64_t SH_FLD_6_SPARE_TERM_DIS = 1943; // 3 +const static uint64_t SH_FLD_7 = 1944; // 412 +const static uint64_t SH_FLD_7_RESERVED = 1945; // 3 +const static uint64_t SH_FLD_7_SPARE_SECTOR_BUFFER_CONTROL = 1946; // 3 +const static uint64_t SH_FLD_7_SPARE_TERM_DIS = 1947; // 3 +const static uint64_t SH_FLD_8 = 1948; // 6 +const static uint64_t SH_FLD_842_FC_SELECT = 1949; // 1 +const static uint64_t SH_FLD_842_FC_SELECT_LEN = 1950; // 1 +const static uint64_t SH_FLD_842_LATENCY_CFG = 1951; // 1 +const static uint64_t SH_FLD_8_11_SPARE = 1952; // 8 +const static uint64_t SH_FLD_8_11_SPARE_LEN = 1953; // 8 +const static uint64_t SH_FLD_8_9 = 1954; // 6 +const static uint64_t SH_FLD_8_9_LEN = 1955; // 6 +const static uint64_t SH_FLD_8_RESERVED = 1956; // 6 +const static uint64_t SH_FLD_8_SPARE_SECTOR_BUFFER_CONTROL = 1957; // 3 +const static uint64_t SH_FLD_9 = 1958; // 6 +const static uint64_t SH_FLD_9_RESERVED = 1959; // 3 +const static uint64_t SH_FLD_9_SPARE_SECTOR_BUFFER_CONTROL = 1960; // 3 +const static uint64_t SH_FLD_AACR_PE = 1961; // 8 +const static uint64_t SH_FLD_AADR_PE = 1962; // 8 +const static uint64_t SH_FLD_AAER_PE = 1963; // 8 +const static uint64_t SH_FLD_ABIST = 1964; // 43 +const static uint64_t SH_FLD_ABORT = 1965; // 6 +const static uint64_t SH_FLD_ABORTED_CMD = 1966; // 1 +const static uint64_t SH_FLD_ABORT_CHECK_TIMEOUT_SEL = 1967; // 6 +const static uint64_t SH_FLD_ABORT_CHECK_TIMEOUT_SEL_LEN = 1968; // 6 +const static uint64_t SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR = 1969; // 43 +const static uint64_t SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 1970; // 43 +const static uint64_t SH_FLD_ABORT_ON_ERROR = 1971; // 8 +const static uint64_t SH_FLD_ABORT_ON_ERR_EN = 1972; // 8 +const static uint64_t SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR = 1973; // 43 +const static uint64_t SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1974; // 43 +const static uint64_t SH_FLD_ACCR_OVERRIDE_EN = 1975; // 12 +const static uint64_t SH_FLD_ACCUM = 1976; // 6 +const static uint64_t SH_FLD_ACCUMULATED_DL_RETURN_P0 = 1977; // 43 +const static uint64_t SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY = 1978; // 43 +const static uint64_t SH_FLD_ACCUMULATED_GENERAL_TIMEOUT = 1979; // 43 +const static uint64_t SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID = 1980; // 43 +const static uint64_t SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD = 1981; // 43 +const static uint64_t SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD = 1982; // 43 +const static uint64_t SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE = 1983; // 43 +const static uint64_t SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE = 1984; // 43 +const static uint64_t SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY = 1985; // 43 +const static uint64_t SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY = 1986; // 43 +const static uint64_t SH_FLD_ACCUMULATED_PCB_WDATA_PARITY = 1987; // 43 +const static uint64_t SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 1988; // 43 +const static uint64_t SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 1989; // 43 +const static uint64_t SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 1990; // 43 +const static uint64_t SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 1991; // 43 +const static uint64_t SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 1992; // 43 +const static uint64_t SH_FLD_ACCUMULATED_UL_P0 = 1993; // 43 +const static uint64_t SH_FLD_ACCUMULATED_UL_RDATA_PARITY = 1994; // 43 +const static uint64_t SH_FLD_ACCUM_HIST = 1995; // 43 +const static uint64_t SH_FLD_ACCUM_LEN = 1996; // 6 +const static uint64_t SH_FLD_ACK = 1997; // 1 +const static uint64_t SH_FLD_ACT = 1998; // 63 +const static uint64_t SH_FLD_ACTCYCLECNT = 1999; // 3 +const static uint64_t SH_FLD_ACTCYCLECNT_LEN = 2000; // 3 +const static uint64_t SH_FLD_ACTION0 = 2001; // 53 +const static uint64_t SH_FLD_ACTION0_LEN = 2002; // 53 +const static uint64_t SH_FLD_ACTION1 = 2003; // 53 +const static uint64_t SH_FLD_ACTION1_LEN = 2004; // 53 +const static uint64_t SH_FLD_ACTION_0 = 2005; // 4 +const static uint64_t SH_FLD_ACTION_0_LEN = 2006; // 4 +const static uint64_t SH_FLD_ACTION_1 = 2007; // 4 +const static uint64_t SH_FLD_ACTION_1_LEN = 2008; // 4 +const static uint64_t SH_FLD_ACTIVATE_COUNT = 2009; // 8 +const static uint64_t SH_FLD_ACTIVATE_COUNT_LEN = 2010; // 8 +const static uint64_t SH_FLD_ACTIVE_CHANNEL_CNT = 2011; // 1 +const static uint64_t SH_FLD_ACTIVE_CHANNEL_CNT_LEN = 2012; // 1 +const static uint64_t SH_FLD_ACTIVE_MASK = 2013; // 24 +const static uint64_t SH_FLD_ACTIVE_MASK_LEN = 2014; // 24 +const static uint64_t SH_FLD_ACTIVITY = 2015; // 129 +const static uint64_t SH_FLD_ACTIVITY_LEN = 2016; // 129 +const static uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE = 2017; // 24 +const static uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_EN = 2018; // 24 +const static uint64_t SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_LEN = 2019; // 24 +const static uint64_t SH_FLD_ACTUAL_CLK_SB_SPARE = 2020; // 24 +const static uint64_t SH_FLD_ACTUAL_CLK_SB_STRENGTH = 2021; // 24 +const static uint64_t SH_FLD_ACTUAL_CLK_SB_STRENGTH_LEN = 2022; // 24 +const static uint64_t SH_FLD_ACTUAL_CLK_SW_RESCLK = 2023; // 24 +const static uint64_t SH_FLD_ACTUAL_CLK_SW_RESCLK_LEN = 2024; // 24 +const static uint64_t SH_FLD_ACTUAL_CLK_SW_SPARE = 2025; // 24 +const static uint64_t SH_FLD_ACTUAL_ERROR = 2026; // 3 +const static uint64_t SH_FLD_ACTUAL_ERROR_LEN = 2027; // 3 +const static uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE = 2028; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_EN = 2029; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_LEN = 2030; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_SPARE0 = 2031; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_STRENGTH = 2032; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SB_STRENGTH_LEN = 2033; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SW_RESCLK = 2034; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SW_RESCLK_LEN = 2035; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX0_CLK_SW_SPARE1 = 2036; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE = 2037; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_EN = 2038; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_LEN = 2039; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_SPARE0 = 2040; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_STRENGTH = 2041; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SB_STRENGTH_LEN = 2042; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SW_RESCLK = 2043; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SW_RESCLK_LEN = 2044; // 6 +const static uint64_t SH_FLD_ACTUAL_L2_EX1_CLK_SW_SPARE1 = 2045; // 6 +const static uint64_t SH_FLD_ACT_CHECK_TIMEOUT_SEL = 2046; // 4 +const static uint64_t SH_FLD_ACT_CHECK_TIMEOUT_SEL_LEN = 2047; // 4 +const static uint64_t SH_FLD_ACT_DIS = 2048; // 43 +const static uint64_t SH_FLD_ADAPTEST_1BIT_ENABLE = 2049; // 1 +const static uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX = 2050; // 1 +const static uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX_LEN = 2051; // 1 +const static uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN = 2052; // 1 +const static uint64_t SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN_LEN = 2053; // 1 +const static uint64_t SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH = 2054; // 1 +const static uint64_t SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH_LEN = 2055; // 1 +const static uint64_t SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH = 2056; // 1 +const static uint64_t SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH_LEN = 2057; // 1 +const static uint64_t SH_FLD_ADAPTEST_ENABLE = 2058; // 1 +const static uint64_t SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH = 2059; // 1 +const static uint64_t SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH_LEN = 2060; // 1 +const static uint64_t SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH = 2061; // 1 +const static uint64_t SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH_LEN = 2062; // 1 +const static uint64_t SH_FLD_ADAPTEST_SAMPLE_SIZE = 2063; // 1 +const static uint64_t SH_FLD_ADAPTEST_SAMPLE_SIZE_LEN = 2064; // 1 +const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0 = 2065; // 1 +const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0_LEN = 2066; // 1 +const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1 = 2067; // 1 +const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1_LEN = 2068; // 1 +const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0 = 2069; // 1 +const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0_LEN = 2070; // 1 +const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1 = 2071; // 1 +const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1_LEN = 2072; // 1 +const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_TH = 2073; // 1 +const static uint64_t SH_FLD_ADAPTEST_SOFT_FAIL_TH_LEN = 2074; // 1 +const static uint64_t SH_FLD_ADAPTEST_WINDOW_SIZE = 2075; // 1 +const static uint64_t SH_FLD_ADAPTEST_WINDOW_SIZE_LEN = 2076; // 1 +const static uint64_t SH_FLD_ADCFSM_ONGOING = 2077; // 1 +const static uint64_t SH_FLD_ADDR = 2078; // 38 +const static uint64_t SH_FLD_ADDR0 = 2079; // 8 +const static uint64_t SH_FLD_ADDR0_LEN = 2080; // 8 +const static uint64_t SH_FLD_ADDR1 = 2081; // 8 +const static uint64_t SH_FLD_ADDR1_LEN = 2082; // 8 +const static uint64_t SH_FLD_ADDR2 = 2083; // 16 +const static uint64_t SH_FLD_ADDR2_LEN = 2084; // 16 +const static uint64_t SH_FLD_ADDR3 = 2085; // 16 +const static uint64_t SH_FLD_ADDR3_LEN = 2086; // 16 +const static uint64_t SH_FLD_ADDR4 = 2087; // 16 +const static uint64_t SH_FLD_ADDR4_LEN = 2088; // 16 +const static uint64_t SH_FLD_ADDRESS = 2089; // 221 +const static uint64_t SH_FLD_ADDRESS_8_63 = 2090; // 1 +const static uint64_t SH_FLD_ADDRESS_8_63_LEN = 2091; // 1 +const static uint64_t SH_FLD_ADDRESS_LEN = 2092; // 220 +const static uint64_t SH_FLD_ADDRESS_PARITY = 2093; // 43 +const static uint64_t SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT = 2094; // 2 +const static uint64_t SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT_LEN = 2095; // 2 +const static uint64_t SH_FLD_ADDR_21_37 = 2096; // 1 +const static uint64_t SH_FLD_ADDR_21_37_LEN = 2097; // 1 +const static uint64_t SH_FLD_ADDR_26_38 = 2098; // 1 +const static uint64_t SH_FLD_ADDR_26_38_LEN = 2099; // 1 +const static uint64_t SH_FLD_ADDR_8_37 = 2100; // 1 +const static uint64_t SH_FLD_ADDR_8_37_LEN = 2101; // 1 +const static uint64_t SH_FLD_ADDR_8_38 = 2102; // 1 +const static uint64_t SH_FLD_ADDR_8_38_LEN = 2103; // 1 +const static uint64_t SH_FLD_ADDR_8_48 = 2104; // 1 +const static uint64_t SH_FLD_ADDR_8_48_LEN = 2105; // 1 +const static uint64_t SH_FLD_ADDR_8_49 = 2106; // 2 +const static uint64_t SH_FLD_ADDR_8_49_LEN = 2107; // 2 +const static uint64_t SH_FLD_ADDR_BAR = 2108; // 2 +const static uint64_t SH_FLD_ADDR_BAR_MODE = 2109; // 2 +const static uint64_t SH_FLD_ADDR_BUFFER = 2110; // 43 +const static uint64_t SH_FLD_ADDR_ERROR = 2111; // 2 +const static uint64_t SH_FLD_ADDR_ERROR_PULSE = 2112; // 2 +const static uint64_t SH_FLD_ADDR_INVALID_FACES = 2113; // 1 +const static uint64_t SH_FLD_ADDR_INVALID_PIB = 2114; // 1 +const static uint64_t SH_FLD_ADDR_LEN = 2115; // 38 +const static uint64_t SH_FLD_ADDR_MIRROR_A11_A13 = 2116; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_A3_A4 = 2117; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_A5_A6 = 2118; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_A7_A8 = 2119; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_BA0_BA1 = 2120; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_BG0_BG1 = 2121; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP0_PRI = 2122; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP0_QUA = 2123; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP0_SEC = 2124; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP0_TER = 2125; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP1_PRI = 2126; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP1_QUA = 2127; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP1_SEC = 2128; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP1_TER = 2129; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP2_PRI = 2130; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP2_QUA = 2131; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP2_SEC = 2132; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP2_TER = 2133; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP3_PRI = 2134; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP3_QUA = 2135; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP3_SEC = 2136; // 8 +const static uint64_t SH_FLD_ADDR_MIRROR_RP3_TER = 2137; // 8 +const static uint64_t SH_FLD_ADDR_NVLD = 2138; // 1 +const static uint64_t SH_FLD_ADDR_PARITY_ERR = 2139; // 4 +const static uint64_t SH_FLD_ADDR_RESET_INTR_FACES = 2140; // 1 +const static uint64_t SH_FLD_ADDR_RESET_INTR_FACES_LEN = 2141; // 1 +const static uint64_t SH_FLD_ADDR_RESET_INTR_PIB = 2142; // 1 +const static uint64_t SH_FLD_ADDR_RESET_INTR_PIB_LEN = 2143; // 1 +const static uint64_t SH_FLD_ADDR_TAG = 2144; // 1 +const static uint64_t SH_FLD_ADDR_TAG_LEN = 2145; // 1 +const static uint64_t SH_FLD_ADR = 2146; // 4 +const static uint64_t SH_FLD_ADR0_ANALOG_WRAPON = 2147; // 8 +const static uint64_t SH_FLD_ADR0_ATESTSEL_0_2 = 2148; // 8 +const static uint64_t SH_FLD_ADR0_ATESTSEL_0_2_LEN = 2149; // 8 +const static uint64_t SH_FLD_ADR0_ATEST_SEL_0 = 2150; // 8 +const static uint64_t SH_FLD_ADR0_ATEST_SEL_0_LEN = 2151; // 8 +const static uint64_t SH_FLD_ADR0_BB_LOCK = 2152; // 8 +const static uint64_t SH_FLD_ADR0_CAL_CKTS_ACTIVE = 2153; // 8 +const static uint64_t SH_FLD_ADR0_CAL_ERROR = 2154; // 8 +const static uint64_t SH_FLD_ADR0_CAL_ERROR_FINE = 2155; // 8 +const static uint64_t SH_FLD_ADR0_CAL_GOOD = 2156; // 8 +const static uint64_t SH_FLD_ADR0_CONTINUOUS_UPDATE = 2157; // 8 +const static uint64_t SH_FLD_ADR0_DLL_ADJUST = 2158; // 8 +const static uint64_t SH_FLD_ADR0_DLL_ADJUST_LEN = 2159; // 8 +const static uint64_t SH_FLD_ADR0_DLL_COMPARE_OUT = 2160; // 8 +const static uint64_t SH_FLD_ADR0_DLL_CORRECT_EN = 2161; // 8 +const static uint64_t SH_FLD_ADR0_DLL_ITER_A = 2162; // 8 +const static uint64_t SH_FLD_ADR0_EN = 2163; // 8 +const static uint64_t SH_FLD_ADR0_EN_DRIVER_INVFB_DC = 2164; // 8 +const static uint64_t SH_FLD_ADR0_FLUSH = 2165; // 8 +const static uint64_t SH_FLD_ADR0_FRZSULV = 2166; // 8 +const static uint64_t SH_FLD_ADR0_HS_DLLMUX_SEL_0_3 = 2167; // 8 +const static uint64_t SH_FLD_ADR0_HS_DLLMUX_SEL_0_3_LEN = 2168; // 8 +const static uint64_t SH_FLD_ADR0_HS_PROBE_A_SEL_0_3 = 2169; // 8 +const static uint64_t SH_FLD_ADR0_HS_PROBE_A_SEL_0_3_LEN = 2170; // 8 +const static uint64_t SH_FLD_ADR0_HS_PROBE_B_SEL_0_3 = 2171; // 8 +const static uint64_t SH_FLD_ADR0_HS_PROBE_B_SEL_0_3_LEN = 2172; // 8 +const static uint64_t SH_FLD_ADR0_INIT_IO = 2173; // 8 +const static uint64_t SH_FLD_ADR0_INIT_RXDLL_CAL_RESET = 2174; // 8 +const static uint64_t SH_FLD_ADR0_INIT_RXDLL_CAL_UPDATE = 2175; // 8 +const static uint64_t SH_FLD_ADR0_INTERP_SIG_SLEW = 2176; // 8 +const static uint64_t SH_FLD_ADR0_INTERP_SIG_SLEW_LEN = 2177; // 8 +const static uint64_t SH_FLD_ADR0_OVERRIDE = 2178; // 8 +const static uint64_t SH_FLD_ADR0_OVERRIDE_EN = 2179; // 8 +const static uint64_t SH_FLD_ADR0_OVERRIDE_LEN = 2180; // 8 +const static uint64_t SH_FLD_ADR0_PHASE_ALIGN_RESET = 2181; // 8 +const static uint64_t SH_FLD_ADR0_PHASE_DEFAULT_EN = 2182; // 8 +const static uint64_t SH_FLD_ADR0_PHASE_EN = 2183; // 8 +const static uint64_t SH_FLD_ADR0_POS_EDGE_ALIGN = 2184; // 8 +const static uint64_t SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP = 2185; // 8 +const static uint64_t SH_FLD_ADR0_REGS_RXDLL_CAL_SKIP_LEN = 2186; // 8 +const static uint64_t SH_FLD_ADR0_REGS_RXDLL_COARSE_ADJ_BY2 = 2187; // 8 +const static uint64_t SH_FLD_ADR0_REGS_RXDLL_DAC = 2188; // 8 +const static uint64_t SH_FLD_ADR0_REGS_RXDLL_DAC_LEN = 2189; // 8 +const static uint64_t SH_FLD_ADR0_REGS_RXDLL_EN = 2190; // 8 +const static uint64_t SH_FLD_ADR0_REGS_RXDLL_EN_LEN = 2191; // 8 +const static uint64_t SH_FLD_ADR0_REGS_RXDLL_VREG = 2192; // 16 +const static uint64_t SH_FLD_ADR0_REGS_RXDLL_VREG_LEN = 2193; // 16 +const static uint64_t SH_FLD_ADR0_ROT = 2194; // 8 +const static uint64_t SH_FLD_ADR0_ROT_LEN = 2195; // 8 +const static uint64_t SH_FLD_ADR0_ROT_OVERRIDE = 2196; // 8 +const static uint64_t SH_FLD_ADR0_ROT_OVERRIDE_EN = 2197; // 8 +const static uint64_t SH_FLD_ADR0_ROT_OVERRIDE_LEN = 2198; // 8 +const static uint64_t SH_FLD_ADR0_RXREG_COMPCON_DC = 2199; // 8 +const static uint64_t SH_FLD_ADR0_RXREG_COMPCON_DC_LEN = 2200; // 8 +const static uint64_t SH_FLD_ADR0_RXREG_CON_DC = 2201; // 8 +const static uint64_t SH_FLD_ADR0_RXREG_DAC_PULLUP_DC = 2202; // 8 +const static uint64_t SH_FLD_ADR0_RXREG_DRVCON_DC = 2203; // 8 +const static uint64_t SH_FLD_ADR0_RXREG_DRVCON_DC_LEN = 2204; // 8 +const static uint64_t SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC = 2205; // 8 +const static uint64_t SH_FLD_ADR0_RXREG_FILTER_LENGTH_DC_LEN = 2206; // 8 +const static uint64_t SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC = 2207; // 8 +const static uint64_t SH_FLD_ADR0_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2208; // 8 +const static uint64_t SH_FLD_ADR0_RXREG_REF_SEL_DC = 2209; // 8 +const static uint64_t SH_FLD_ADR0_RXREG_REF_SEL_DC_LEN = 2210; // 8 +const static uint64_t SH_FLD_ADR0_SLEW_DONE_STATUS = 2211; // 8 +const static uint64_t SH_FLD_ADR0_SLEW_DONE_STATUS_LEN = 2212; // 8 +const static uint64_t SH_FLD_ADR0_START = 2213; // 8 +const static uint64_t SH_FLD_ADR0_TARGET_PR_OFFSET = 2214; // 8 +const static uint64_t SH_FLD_ADR0_TARGET_PR_OFFSET_LEN = 2215; // 8 +const static uint64_t SH_FLD_ADR0_TSYS = 2216; // 8 +const static uint64_t SH_FLD_ADR0_TSYS_LEN = 2217; // 8 +const static uint64_t SH_FLD_ADR0_VALUE = 2218; // 16 +const static uint64_t SH_FLD_ADR0_VALUE_LEN = 2219; // 16 +const static uint64_t SH_FLD_ADR1_ANALOG_WRAPON = 2220; // 8 +const static uint64_t SH_FLD_ADR1_ATESTSEL_0_2 = 2221; // 8 +const static uint64_t SH_FLD_ADR1_ATESTSEL_0_2_LEN = 2222; // 8 +const static uint64_t SH_FLD_ADR1_ATEST_SEL_0 = 2223; // 8 +const static uint64_t SH_FLD_ADR1_ATEST_SEL_0_LEN = 2224; // 8 +const static uint64_t SH_FLD_ADR1_BB_LOCK = 2225; // 8 +const static uint64_t SH_FLD_ADR1_CAL_CKTS_ACTIVE = 2226; // 8 +const static uint64_t SH_FLD_ADR1_CAL_ERROR = 2227; // 8 +const static uint64_t SH_FLD_ADR1_CAL_ERROR_FINE = 2228; // 8 +const static uint64_t SH_FLD_ADR1_CAL_GOOD = 2229; // 8 +const static uint64_t SH_FLD_ADR1_CONTINUOUS_UPDATE = 2230; // 8 +const static uint64_t SH_FLD_ADR1_DLL_ADJUST = 2231; // 8 +const static uint64_t SH_FLD_ADR1_DLL_ADJUST_LEN = 2232; // 8 +const static uint64_t SH_FLD_ADR1_DLL_COMPARE_OUT = 2233; // 8 +const static uint64_t SH_FLD_ADR1_DLL_CORRECT_EN = 2234; // 8 +const static uint64_t SH_FLD_ADR1_DLL_ITER_A = 2235; // 8 +const static uint64_t SH_FLD_ADR1_EN = 2236; // 8 +const static uint64_t SH_FLD_ADR1_EN_DRIVER_INVFB_DC = 2237; // 8 +const static uint64_t SH_FLD_ADR1_FLUSH = 2238; // 8 +const static uint64_t SH_FLD_ADR1_FRZSULV = 2239; // 8 +const static uint64_t SH_FLD_ADR1_HS_DLLMUX_SEL_0_3 = 2240; // 8 +const static uint64_t SH_FLD_ADR1_HS_DLLMUX_SEL_0_3_LEN = 2241; // 8 +const static uint64_t SH_FLD_ADR1_HS_PROBE_A_SEL_0_3 = 2242; // 8 +const static uint64_t SH_FLD_ADR1_HS_PROBE_A_SEL_0_3_LEN = 2243; // 8 +const static uint64_t SH_FLD_ADR1_HS_PROBE_B_SEL_0_3 = 2244; // 8 +const static uint64_t SH_FLD_ADR1_HS_PROBE_B_SEL_0_3_LEN = 2245; // 8 +const static uint64_t SH_FLD_ADR1_INIT_IO = 2246; // 8 +const static uint64_t SH_FLD_ADR1_INIT_RXDLL_CAL_RESET = 2247; // 8 +const static uint64_t SH_FLD_ADR1_INIT_RXDLL_CAL_UPDATE = 2248; // 8 +const static uint64_t SH_FLD_ADR1_INTERP_SIG_SLEW = 2249; // 8 +const static uint64_t SH_FLD_ADR1_INTERP_SIG_SLEW_LEN = 2250; // 8 +const static uint64_t SH_FLD_ADR1_OVERRIDE = 2251; // 8 +const static uint64_t SH_FLD_ADR1_OVERRIDE_EN = 2252; // 8 +const static uint64_t SH_FLD_ADR1_OVERRIDE_LEN = 2253; // 8 +const static uint64_t SH_FLD_ADR1_PHASE_ALIGN_RESET = 2254; // 8 +const static uint64_t SH_FLD_ADR1_PHASE_DEFAULT_EN = 2255; // 8 +const static uint64_t SH_FLD_ADR1_PHASE_EN = 2256; // 8 +const static uint64_t SH_FLD_ADR1_POS_EDGE_ALIGN = 2257; // 8 +const static uint64_t SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP = 2258; // 8 +const static uint64_t SH_FLD_ADR1_REGS_RXDLL_CAL_SKIP_LEN = 2259; // 8 +const static uint64_t SH_FLD_ADR1_REGS_RXDLL_COARSE_ADJ_BY2 = 2260; // 8 +const static uint64_t SH_FLD_ADR1_REGS_RXDLL_DAC = 2261; // 8 +const static uint64_t SH_FLD_ADR1_REGS_RXDLL_DAC_LEN = 2262; // 8 +const static uint64_t SH_FLD_ADR1_REGS_RXDLL_EN = 2263; // 8 +const static uint64_t SH_FLD_ADR1_REGS_RXDLL_EN_LEN = 2264; // 8 +const static uint64_t SH_FLD_ADR1_REGS_RXDLL_VREG = 2265; // 16 +const static uint64_t SH_FLD_ADR1_REGS_RXDLL_VREG_LEN = 2266; // 16 +const static uint64_t SH_FLD_ADR1_ROT = 2267; // 8 +const static uint64_t SH_FLD_ADR1_ROT_LEN = 2268; // 8 +const static uint64_t SH_FLD_ADR1_ROT_OVERRIDE = 2269; // 8 +const static uint64_t SH_FLD_ADR1_ROT_OVERRIDE_EN = 2270; // 8 +const static uint64_t SH_FLD_ADR1_ROT_OVERRIDE_LEN = 2271; // 8 +const static uint64_t SH_FLD_ADR1_RXREG_COMPCON_DC = 2272; // 8 +const static uint64_t SH_FLD_ADR1_RXREG_COMPCON_DC_LEN = 2273; // 8 +const static uint64_t SH_FLD_ADR1_RXREG_CON_DC = 2274; // 8 +const static uint64_t SH_FLD_ADR1_RXREG_DAC_PULLUP_DC = 2275; // 8 +const static uint64_t SH_FLD_ADR1_RXREG_DRVCON_DC = 2276; // 8 +const static uint64_t SH_FLD_ADR1_RXREG_DRVCON_DC_LEN = 2277; // 8 +const static uint64_t SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC = 2278; // 8 +const static uint64_t SH_FLD_ADR1_RXREG_FILTER_LENGTH_DC_LEN = 2279; // 8 +const static uint64_t SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC = 2280; // 8 +const static uint64_t SH_FLD_ADR1_RXREG_LEAD_LAG_SEPARATION_DC_LEN = 2281; // 8 +const static uint64_t SH_FLD_ADR1_RXREG_REF_SEL_DC = 2282; // 8 +const static uint64_t SH_FLD_ADR1_RXREG_REF_SEL_DC_LEN = 2283; // 8 +const static uint64_t SH_FLD_ADR1_SLEW_DONE_STATUS = 2284; // 8 +const static uint64_t SH_FLD_ADR1_SLEW_DONE_STATUS_LEN = 2285; // 8 +const static uint64_t SH_FLD_ADR1_START = 2286; // 8 +const static uint64_t SH_FLD_ADR1_TARGET_PR_OFFSET = 2287; // 8 +const static uint64_t SH_FLD_ADR1_TARGET_PR_OFFSET_LEN = 2288; // 8 +const static uint64_t SH_FLD_ADR1_TSYS = 2289; // 8 +const static uint64_t SH_FLD_ADR1_TSYS_LEN = 2290; // 8 +const static uint64_t SH_FLD_ADR1_VALUE = 2291; // 16 +const static uint64_t SH_FLD_ADR1_VALUE_LEN = 2292; // 16 +const static uint64_t SH_FLD_ADR_ERROR = 2293; // 8 +const static uint64_t SH_FLD_ADR_ERROR_FINE = 2294; // 8 +const static uint64_t SH_FLD_ADR_GOOD = 2295; // 8 +const static uint64_t SH_FLD_ADR_LEN = 2296; // 4 +const static uint64_t SH_FLD_ADR_SLAVE_SEL = 2297; // 8 +const static uint64_t SH_FLD_ADS_HANG = 2298; // 1 +const static uint64_t SH_FLD_ADU_MALF_ALERT = 2299; // 1 +const static uint64_t SH_FLD_ADVANCE_RD_VALID = 2300; // 8 +const static uint64_t SH_FLD_AECS = 2301; // 6 +const static uint64_t SH_FLD_AECS_LEN = 2302; // 6 +const static uint64_t SH_FLD_AESSHA_LATENCY_CFG = 2303; // 1 +const static uint64_t SH_FLD_AES_LATENCY_CFG = 2304; // 1 +const static uint64_t SH_FLD_AIB_ACCESS_ERROR = 2305; // 6 +const static uint64_t SH_FLD_AIB_ADDRESS_INVALID = 2306; // 6 +const static uint64_t SH_FLD_AIB_COMMAND_INVALID = 2307; // 6 +const static uint64_t SH_FLD_AIB_FATAL_CLASS_ERROR = 2308; // 6 +const static uint64_t SH_FLD_AIB_FENCE = 2309; // 9 +const static uint64_t SH_FLD_AIB_FENCE_MASK = 2310; // 9 +const static uint64_t SH_FLD_AIB_INF_CLASS_ERROR = 2311; // 6 +const static uint64_t SH_FLD_AIB_IN_CMD_CTL_PERR = 2312; // 1 +const static uint64_t SH_FLD_AIB_IN_CMD_PERR = 2313; // 1 +const static uint64_t SH_FLD_AIB_IN_DAT_CTL_PERR = 2314; // 1 +const static uint64_t SH_FLD_AIB_PE = 2315; // 9 +const static uint64_t SH_FLD_AIB_PE_MASK = 2316; // 9 +const static uint64_t SH_FLD_AI_ECC_CE = 2317; // 1 +const static uint64_t SH_FLD_AI_ECC_UE = 2318; // 1 +const static uint64_t SH_FLD_ALIGN_ON_EVEN_CYCLES = 2319; // 8 +const static uint64_t SH_FLD_ALLOC = 2320; // 24 +const static uint64_t SH_FLD_ALLOC_LEN = 2321; // 24 +const static uint64_t SH_FLD_ALLOW_CRYPTO = 2322; // 1 +const static uint64_t SH_FLD_ALLOW_RD_FIFO_AUTO_RESET = 2323; // 8 +const static uint64_t SH_FLD_ALLOW_REG_WAKEUP_C0 = 2324; // 12 +const static uint64_t SH_FLD_ALLOW_REG_WAKEUP_C1 = 2325; // 12 +const static uint64_t SH_FLD_ALTD_DATA_ITAG = 2326; // 1 +const static uint64_t SH_FLD_ALTD_DATA_TX = 2327; // 1 +const static uint64_t SH_FLD_ALTD_DATA_TX_LEN = 2328; // 1 +const static uint64_t SH_FLD_ALTD_DATA_TX_OVERWRITE = 2329; // 1 +const static uint64_t SH_FLD_ALT_M = 2330; // 8 +const static uint64_t SH_FLD_ALT_M_LEN = 2331; // 8 +const static uint64_t SH_FLD_ALT_SEGSZ_DIS = 2332; // 1 +const static uint64_t SH_FLD_ALU_ADR = 2333; // 3 +const static uint64_t SH_FLD_ALU_ADR_LEN = 2334; // 3 +const static uint64_t SH_FLD_ALU_FLIP_ENDIAN_BIG = 2335; // 3 +const static uint64_t SH_FLD_ALU_FLIP_ENDIAN_LITTLE = 2336; // 3 +const static uint64_t SH_FLD_ALU_SAFE_LATENCY = 2337; // 3 +const static uint64_t SH_FLD_ALU_SZ = 2338; // 3 +const static uint64_t SH_FLD_ALU_TYPE = 2339; // 3 +const static uint64_t SH_FLD_ALU_TYPE_LEN = 2340; // 3 +const static uint64_t SH_FLD_ALWAYS_RTY = 2341; // 8 +const static uint64_t SH_FLD_AMAX_HIGH = 2342; // 6 +const static uint64_t SH_FLD_AMAX_HIGH_LEN = 2343; // 6 +const static uint64_t SH_FLD_AMAX_LOW = 2344; // 6 +const static uint64_t SH_FLD_AMAX_LOW_LEN = 2345; // 6 +const static uint64_t SH_FLD_AMIN_CFG = 2346; // 6 +const static uint64_t SH_FLD_AMIN_CFG_LEN = 2347; // 6 +const static uint64_t SH_FLD_AMIN_ENABLE_HDAC = 2348; // 4 +const static uint64_t SH_FLD_AMIN_TIMEOUT = 2349; // 6 +const static uint64_t SH_FLD_AMIN_TIMEOUT_LEN = 2350; // 6 +const static uint64_t SH_FLD_AMO_DRAM_SIZE_128B = 2351; // 8 +const static uint64_t SH_FLD_AMO_LIMIT = 2352; // 8 +const static uint64_t SH_FLD_AMO_LIMIT_LEN = 2353; // 8 +const static uint64_t SH_FLD_AMP0_FILTER_MASK = 2354; // 6 +const static uint64_t SH_FLD_AMP0_FILTER_MASK_LEN = 2355; // 6 +const static uint64_t SH_FLD_AMP1_FILTER_MASK = 2356; // 6 +const static uint64_t SH_FLD_AMP1_FILTER_MASK_LEN = 2357; // 6 +const static uint64_t SH_FLD_AMP_CFG = 2358; // 6 +const static uint64_t SH_FLD_AMP_CFG_LEN = 2359; // 6 +const static uint64_t SH_FLD_AMP_GAIN_CNT_MAX = 2360; // 6 +const static uint64_t SH_FLD_AMP_GAIN_CNT_MAX_LEN = 2361; // 6 +const static uint64_t SH_FLD_AMP_INIT_CFG = 2362; // 6 +const static uint64_t SH_FLD_AMP_INIT_CFG_LEN = 2363; // 6 +const static uint64_t SH_FLD_AMP_INIT_TIMEOUT = 2364; // 6 +const static uint64_t SH_FLD_AMP_INIT_TIMEOUT_LEN = 2365; // 6 +const static uint64_t SH_FLD_AMP_RECAL_CFG = 2366; // 6 +const static uint64_t SH_FLD_AMP_RECAL_CFG_LEN = 2367; // 6 +const static uint64_t SH_FLD_AMP_RECAL_TIMEOUT = 2368; // 6 +const static uint64_t SH_FLD_AMP_RECAL_TIMEOUT_LEN = 2369; // 6 +const static uint64_t SH_FLD_AMP_START_VAL = 2370; // 6 +const static uint64_t SH_FLD_AMP_START_VAL_LEN = 2371; // 6 +const static uint64_t SH_FLD_AMP_TIMEOUT = 2372; // 6 +const static uint64_t SH_FLD_AMP_TIMEOUT_LEN = 2373; // 6 +const static uint64_t SH_FLD_AMP_VAL = 2374; // 120 +const static uint64_t SH_FLD_AMP_VAL_LEN = 2375; // 120 +const static uint64_t SH_FLD_AMR = 2376; // 256 +const static uint64_t SH_FLD_AMR_LEN = 2377; // 256 +const static uint64_t SH_FLD_ANALOGTUNE = 2378; // 20 +const static uint64_t SH_FLD_ANALOGTUNE_LEN = 2379; // 20 +const static uint64_t SH_FLD_ANALOG_INPUT_STAB = 2380; // 8 +const static uint64_t SH_FLD_AND_TRIGGER_MODE1 = 2381; // 86 +const static uint64_t SH_FLD_AND_TRIGGER_MODE2 = 2382; // 86 +const static uint64_t SH_FLD_ANY_ERROR = 2383; // 1 +const static uint64_t SH_FLD_ANY_REQ_ACTIVE = 2384; // 12 +const static uint64_t SH_FLD_AP = 2385; // 8 +const static uint64_t SH_FLD_AP110_AP010_DELTA_MAX = 2386; // 6 +const static uint64_t SH_FLD_AP110_AP010_DELTA_MAX_LEN = 2387; // 6 +const static uint64_t SH_FLD_APB = 2388; // 8 +const static uint64_t SH_FLD_APB_MASK = 2389; // 8 +const static uint64_t SH_FLD_APCARY = 2390; // 4 +const static uint64_t SH_FLD_APCARY_ADDRESS = 2391; // 2 +const static uint64_t SH_FLD_APCARY_ADDRESS_LEN = 2392; // 2 +const static uint64_t SH_FLD_APCARY_LEN = 2393; // 4 +const static uint64_t SH_FLD_APCCTL_ADR_BAR_MODE = 2394; // 2 +const static uint64_t SH_FLD_APCCTL_CFG_BKILL_INC = 2395; // 2 +const static uint64_t SH_FLD_APCCTL_DISABLE_G = 2396; // 2 +const static uint64_t SH_FLD_APCCTL_DISABLE_LN = 2397; // 2 +const static uint64_t SH_FLD_APCCTL_DISABLE_NN_RN = 2398; // 2 +const static uint64_t SH_FLD_APCCTL_DISABLE_PSL_CMDQUEUE = 2399; // 2 +const static uint64_t SH_FLD_APCCTL_DISABLE_VG_NOT_SYS = 2400; // 2 +const static uint64_t SH_FLD_APCCTL_ENABLE_MASTER_RETRY_BACKOFF = 2401; // 2 +const static uint64_t SH_FLD_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT = 2402; // 2 +const static uint64_t SH_FLD_APCCTL_ENB_CRESP_EXAM = 2403; // 2 +const static uint64_t SH_FLD_APCCTL_ENB_FRC_ADDR13 = 2404; // 2 +const static uint64_t SH_FLD_APCCTL_HANG_ARE = 2405; // 2 +const static uint64_t SH_FLD_APCCTL_HANG_DEAD = 2406; // 2 +const static uint64_t SH_FLD_APCCTL_MAX_RETRY = 2407; // 2 +const static uint64_t SH_FLD_APCCTL_MAX_RETRY_LEN = 2408; // 2 +const static uint64_t SH_FLD_APCCTL_MEM_SEL_MODE = 2409; // 2 +const static uint64_t SH_FLD_APCCTL_P9_MODE = 2410; // 2 +const static uint64_t SH_FLD_APCCTL_PHB_SEL = 2411; // 2 +const static uint64_t SH_FLD_APCCTL_PHB_SEL_LEN = 2412; // 2 +const static uint64_t SH_FLD_APCCTL_SKIP_G = 2413; // 2 +const static uint64_t SH_FLD_APCCTL_SYSADDR = 2414; // 2 +const static uint64_t SH_FLD_APCCTL_SYSADDR_LEN = 2415; // 2 +const static uint64_t SH_FLD_APC_ARRAY_CMD_CE_ERPT = 2416; // 4 +const static uint64_t SH_FLD_APC_ARRAY_CMD_UE_ERPT = 2417; // 4 +const static uint64_t SH_FLD_APC_RDFSM_MASK = 2418; // 2 +const static uint64_t SH_FLD_APC_RDFSM_MASK_LEN = 2419; // 2 +const static uint64_t SH_FLD_APX111_HIGH = 2420; // 6 +const static uint64_t SH_FLD_APX111_HIGH_LEN = 2421; // 6 +const static uint64_t SH_FLD_APX111_LOW = 2422; // 6 +const static uint64_t SH_FLD_APX111_LOW_LEN = 2423; // 6 +const static uint64_t SH_FLD_AP_LEN = 2424; // 8 +const static uint64_t SH_FLD_ARBITRATION_LOST_ERROR_0 = 2425; // 4 +const static uint64_t SH_FLD_ARBITRATION_LOST_ERROR_1 = 2426; // 2 +const static uint64_t SH_FLD_ARBITRATION_LOST_ERROR_2 = 2427; // 2 +const static uint64_t SH_FLD_ARBITRATION_LOST_ERROR_3 = 2428; // 2 +const static uint64_t SH_FLD_ARB_BLIF_COMPLETION_ERROR = 2429; // 6 +const static uint64_t SH_FLD_ARB_COMMON_FATAL_ERROR = 2430; // 6 +const static uint64_t SH_FLD_ARB_ECC_CORRECTABLE_ERROR = 2431; // 6 +const static uint64_t SH_FLD_ARB_ECC_INJECT_ERR = 2432; // 3 +const static uint64_t SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR = 2433; // 6 +const static uint64_t SH_FLD_ARB_EN_SEND_ALL_WRITES = 2434; // 1 +const static uint64_t SH_FLD_ARB_IODA_FATAL_ERROR = 2435; // 6 +const static uint64_t SH_FLD_ARB_MSI_ADDRESS_ERROR = 2436; // 6 +const static uint64_t SH_FLD_ARB_MSI_PE_MATCH_ERROR = 2437; // 6 +const static uint64_t SH_FLD_ARB_PCT_TIMEOUT_ERROR = 2438; // 6 +const static uint64_t SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG = 2439; // 6 +const static uint64_t SH_FLD_ARB_RCVD_FATAL_ERROR_MSG = 2440; // 6 +const static uint64_t SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG = 2441; // 6 +const static uint64_t SH_FLD_ARB_RTT_PENUM_INVALID_ERROR = 2442; // 6 +const static uint64_t SH_FLD_ARB_STALL = 2443; // 1 +const static uint64_t SH_FLD_ARB_STOP = 2444; // 1 +const static uint64_t SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR = 2445; // 6 +const static uint64_t SH_FLD_ARB_TLP_POISON_SIGNALED = 2446; // 6 +const static uint64_t SH_FLD_ARB_TVT_ERROR = 2447; // 6 +const static uint64_t SH_FLD_ARM_SEL = 2448; // 43 +const static uint64_t SH_FLD_ARM_SEL_LEN = 2449; // 43 +const static uint64_t SH_FLD_ARRAY_ADDR = 2450; // 6 +const static uint64_t SH_FLD_ARRAY_ADDR_LEN = 2451; // 6 +const static uint64_t SH_FLD_ARRAY_ECC_CE = 2452; // 2 +const static uint64_t SH_FLD_ARRAY_ECC_UE = 2453; // 2 +const static uint64_t SH_FLD_ARRAY_POINTER_SELECT = 2454; // 6 +const static uint64_t SH_FLD_ARRAY_POINTER_SELECT_LEN = 2455; // 6 +const static uint64_t SH_FLD_ARRAY_SELECT = 2456; // 1 +const static uint64_t SH_FLD_ARRAY_SELECT_LEN = 2457; // 1 +const static uint64_t SH_FLD_ARRAY_WRITE_ASSIST_EN = 2458; // 43 +const static uint64_t SH_FLD_ARY_ECC_CE = 2459; // 9 +const static uint64_t SH_FLD_ARY_ECC_CE_MASK = 2460; // 9 +const static uint64_t SH_FLD_ARY_ECC_SUE = 2461; // 9 +const static uint64_t SH_FLD_ARY_ECC_SUE_MASK = 2462; // 9 +const static uint64_t SH_FLD_ARY_ECC_UE = 2463; // 9 +const static uint64_t SH_FLD_ARY_ECC_UE_MASK = 2464; // 9 +const static uint64_t SH_FLD_ASSIGN_DONE = 2465; // 1 +const static uint64_t SH_FLD_ASYNC_IF_ERROR = 2466; // 16 +const static uint64_t SH_FLD_ASYNC_INJ = 2467; // 16 +const static uint64_t SH_FLD_ASYNC_INJ_LEN = 2468; // 16 +const static uint64_t SH_FLD_ASYNC_MODE = 2469; // 6 +const static uint64_t SH_FLD_ASYNC_OBS = 2470; // 43 +const static uint64_t SH_FLD_ASYNC_TYPE = 2471; // 43 +const static uint64_t SH_FLD_ATAG_0_15 = 2472; // 1 +const static uint64_t SH_FLD_ATAG_0_15_LEN = 2473; // 1 +const static uint64_t SH_FLD_ATOMIC_ALT_CE_INJ = 2474; // 2 +const static uint64_t SH_FLD_ATOMIC_ALT_CHIP_KILL_INJ = 2475; // 2 +const static uint64_t SH_FLD_ATOMIC_ALT_INJ_SYM_SEL = 2476; // 2 +const static uint64_t SH_FLD_ATOMIC_ALT_INJ_SYM_SEL_LEN = 2477; // 2 +const static uint64_t SH_FLD_ATOMIC_ALT_SUE_INJ = 2478; // 2 +const static uint64_t SH_FLD_ATOMIC_ALT_UE_INJ = 2479; // 2 +const static uint64_t SH_FLD_ATRR = 2480; // 3 +const static uint64_t SH_FLD_ATR_ARBSTATE = 2481; // 1 +const static uint64_t SH_FLD_ATR_ERR_INJ_PEND = 2482; // 1 +const static uint64_t SH_FLD_ATR_SM_STATE = 2483; // 1 +const static uint64_t SH_FLD_ATR_TIMEOUT = 2484; // 2 +const static uint64_t SH_FLD_ATR_TIMEOUT_LEN = 2485; // 1 +const static uint64_t SH_FLD_ATSD_BAD_TAG = 2486; // 1 +const static uint64_t SH_FLD_ATSD_SM_STATE = 2487; // 1 +const static uint64_t SH_FLD_ATSD_TIMEOUT = 2488; // 2 +const static uint64_t SH_FLD_ATSD_TIMEOUT_LEN = 2489; // 1 +const static uint64_t SH_FLD_ATSREQ = 2490; // 3 +const static uint64_t SH_FLD_ATSTSEL = 2491; // 17 +const static uint64_t SH_FLD_ATSTSEL_LEN = 2492; // 17 +const static uint64_t SH_FLD_ATSXLATE = 2493; // 12 +const static uint64_t SH_FLD_ATS_AT_EA_CE = 2494; // 1 +const static uint64_t SH_FLD_ATS_AT_EA_UE = 2495; // 1 +const static uint64_t SH_FLD_ATS_AT_RSPOUT_CE = 2496; // 1 +const static uint64_t SH_FLD_ATS_AT_RSPOUT_UE = 2497; // 1 +const static uint64_t SH_FLD_ATS_AT_TDRMEM_CE = 2498; // 1 +const static uint64_t SH_FLD_ATS_AT_TDRMEM_UE = 2499; // 1 +const static uint64_t SH_FLD_ATS_INVAL_IODA_TBL_SEL = 2500; // 1 +const static uint64_t SH_FLD_ATS_IODA_ADDR_PERR = 2501; // 1 +const static uint64_t SH_FLD_ATS_NPU_CTRL_PERR = 2502; // 1 +const static uint64_t SH_FLD_ATS_NPU_TOR_PERR = 2503; // 1 +const static uint64_t SH_FLD_ATS_RSVD_19 = 2504; // 1 +const static uint64_t SH_FLD_ATS_SYNC = 2505; // 3 +const static uint64_t SH_FLD_ATS_TCD_PERR = 2506; // 1 +const static uint64_t SH_FLD_ATS_TCE_CACHE_MULT_HIT_ERR = 2507; // 1 +const static uint64_t SH_FLD_ATS_TCE_PAGE_ACCESS_CA_ERR = 2508; // 1 +const static uint64_t SH_FLD_ATS_TCE_PAGE_ACCESS_TW_ERR = 2509; // 1 +const static uint64_t SH_FLD_ATS_TCE_REQ_TO_ERR = 2510; // 1 +const static uint64_t SH_FLD_ATS_TDR_PERR = 2511; // 1 +const static uint64_t SH_FLD_ATS_TVT_ADDR_RANGE_ERR = 2512; // 1 +const static uint64_t SH_FLD_ATS_TVT_ENTRY_INVALID = 2513; // 1 +const static uint64_t SH_FLD_ATS_TVT_PERR = 2514; // 1 +const static uint64_t SH_FLD_ATTENTION = 2515; // 1 +const static uint64_t SH_FLD_ATX_FOR_BLCK_UPD = 2516; // 1 +const static uint64_t SH_FLD_ATX_FOR_BLCK_UPD_LEN = 2517; // 1 +const static uint64_t SH_FLD_ATX_FOR_REGS = 2518; // 1 +const static uint64_t SH_FLD_ATX_FOR_REGS_LEN = 2519; // 1 +const static uint64_t SH_FLD_ATX_FOR_SBC_EOI_RESP = 2520; // 1 +const static uint64_t SH_FLD_ATX_FOR_SBC_EOI_RESP_LEN = 2521; // 1 +const static uint64_t SH_FLD_ATX_FOR_TCTXT_RSP_WR = 2522; // 1 +const static uint64_t SH_FLD_ATX_FOR_TCTXT_RSP_WR_LEN = 2523; // 1 +const static uint64_t SH_FLD_ATX_FOR_VPC_DMA = 2524; // 1 +const static uint64_t SH_FLD_ATX_FOR_VPC_DMA_LEN = 2525; // 1 +const static uint64_t SH_FLD_ATX_FOR_VPC_LD_RMT = 2526; // 1 +const static uint64_t SH_FLD_ATX_FOR_VPC_LD_RMT_LEN = 2527; // 1 +const static uint64_t SH_FLD_ATX_FOR_VPC_ST_LCL_VC = 2528; // 1 +const static uint64_t SH_FLD_ATX_FOR_VPC_ST_LCL_VC_LEN = 2529; // 1 +const static uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT = 2530; // 1 +const static uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT_LEN = 2531; // 1 +const static uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT_VC = 2532; // 1 +const static uint64_t SH_FLD_ATX_FOR_VPC_ST_RMT_VC_LEN = 2533; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP = 2534; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP_LEN = 2535; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_EQD_DMA = 2536; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_EQD_DMA_LEN = 2537; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_IRQ = 2538; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_IRQ_LEN = 2539; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_IVC = 2540; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_IVC_LEN = 2541; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD = 2542; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD_LEN = 2543; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_REGS = 2544; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_REGS_LEN = 2545; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_SBC_DMA = 2546; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_SBC_DMA_LEN = 2547; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP = 2548; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP_LEN = 2549; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_TRIG_FWD = 2550; // 1 +const static uint64_t SH_FLD_ATX_PRIO_FOR_TRIG_FWD_LEN = 2551; // 1 +const static uint64_t SH_FLD_ATYPE = 2552; // 24 +const static uint64_t SH_FLD_ATYPE_LEN = 2553; // 24 +const static uint64_t SH_FLD_AT_EA_CE_ESR = 2554; // 1 +const static uint64_t SH_FLD_AT_EA_UE_ESR = 2555; // 1 +const static uint64_t SH_FLD_AT_TDRMEM_CE_ESR = 2556; // 1 +const static uint64_t SH_FLD_AT_TDRMEM_UE_ESR = 2557; // 1 +const static uint64_t SH_FLD_AUE = 2558; // 2 +const static uint64_t SH_FLD_AUE_LEN = 2559; // 2 +const static uint64_t SH_FLD_AUTOINC = 2560; // 12 +const static uint64_t SH_FLD_AUTO_INC = 2561; // 7 +const static uint64_t SH_FLD_AUTO_INCREMENT = 2562; // 3 +const static uint64_t SH_FLD_AUTO_INC_TRIG = 2563; // 6 +const static uint64_t SH_FLD_AUTO_INC_TRIG_LEN = 2564; // 6 +const static uint64_t SH_FLD_AUTO_POST_DECREMENT_FACES = 2565; // 1 +const static uint64_t SH_FLD_AUTO_POST_DECREMENT_PIB = 2566; // 1 +const static uint64_t SH_FLD_AUTO_PRE_INCREMENT_FACES = 2567; // 1 +const static uint64_t SH_FLD_AUTO_PRE_INCREMENT_PIB = 2568; // 1 +const static uint64_t SH_FLD_AUTO_RELOAD_N = 2569; // 2 +const static uint64_t SH_FLD_AUTO_STOP1_DISABLE = 2570; // 12 +const static uint64_t SH_FLD_AVA = 2571; // 8 +const static uint64_t SH_FLD_AVAIL_GROUPS = 2572; // 2 +const static uint64_t SH_FLD_AVAIL_GROUPS_LEN = 2573; // 2 +const static uint64_t SH_FLD_AVA_LEN = 2574; // 8 +const static uint64_t SH_FLD_AVG_CYCLE_SAMPLE = 2575; // 12 +const static uint64_t SH_FLD_AVG_CYCLE_SAMPLE_LEN = 2576; // 12 +const static uint64_t SH_FLD_AVG_FREQ_TSEL = 2577; // 12 +const static uint64_t SH_FLD_AVG_FREQ_TSEL_LEN = 2578; // 12 +const static uint64_t SH_FLD_AVS_SLAVE0 = 2579; // 1 +const static uint64_t SH_FLD_AVS_SLAVE1 = 2580; // 1 +const static uint64_t SH_FLD_AXFLOW_ERR = 2581; // 1 +const static uint64_t SH_FLD_AXFLOW_ERR_MASK = 2582; // 1 +const static uint64_t SH_FLD_AXPUSH_WRERR = 2583; // 1 +const static uint64_t SH_FLD_AXPUSH_WRERR_MASK = 2584; // 1 +const static uint64_t SH_FLD_AXRCV_DLO_ERR = 2585; // 1 +const static uint64_t SH_FLD_AXRCV_DLO_ERR_MASK = 2586; // 1 +const static uint64_t SH_FLD_AXRCV_DLO_TO = 2587; // 1 +const static uint64_t SH_FLD_AXRCV_DLO_TO_MASK = 2588; // 1 +const static uint64_t SH_FLD_AXRCV_RSVDATA_TO = 2589; // 1 +const static uint64_t SH_FLD_AXRCV_RSVDATA_TO_MASK = 2590; // 1 +const static uint64_t SH_FLD_AXSND_DHI_RTYTO = 2591; // 1 +const static uint64_t SH_FLD_AXSND_DHI_RTYTO_MASK = 2592; // 1 +const static uint64_t SH_FLD_AXSND_DLO_RTYTO = 2593; // 1 +const static uint64_t SH_FLD_AXSND_DLO_RTYTO_MASK = 2594; // 1 +const static uint64_t SH_FLD_AXSND_RSVERR = 2595; // 1 +const static uint64_t SH_FLD_AXSND_RSVERR_MASK = 2596; // 1 +const static uint64_t SH_FLD_AXSND_RSVTO = 2597; // 1 +const static uint64_t SH_FLD_AXSND_RSVTO_MASK = 2598; // 1 +const static uint64_t SH_FLD_A_AP = 2599; // 144 +const static uint64_t SH_FLD_A_AP_LEN = 2600; // 144 +const static uint64_t SH_FLD_A_BAD_DFE_CONV = 2601; // 144 +const static uint64_t SH_FLD_A_BANK_CONTROLS = 2602; // 120 +const static uint64_t SH_FLD_A_BANK_CONTROLS_LEN = 2603; // 120 +const static uint64_t SH_FLD_A_BIST_EN = 2604; // 6 +const static uint64_t SH_FLD_A_CONTROLS = 2605; // 120 +const static uint64_t SH_FLD_A_CONTROLS_LEN = 2606; // 120 +const static uint64_t SH_FLD_A_CTLE_COARSE = 2607; // 48 +const static uint64_t SH_FLD_A_CTLE_COARSE_LEN = 2608; // 48 +const static uint64_t SH_FLD_A_CTLE_GAIN = 2609; // 120 +const static uint64_t SH_FLD_A_CTLE_GAIN_LEN = 2610; // 120 +const static uint64_t SH_FLD_A_CTLE_PEAK = 2611; // 72 +const static uint64_t SH_FLD_A_CTLE_PEAK_LEN = 2612; // 72 +const static uint64_t SH_FLD_A_EVEN_INTEG_FINE_GAIN = 2613; // 120 +const static uint64_t SH_FLD_A_EVEN_INTEG_FINE_GAIN_LEN = 2614; // 120 +const static uint64_t SH_FLD_A_H10_VAL = 2615; // 72 +const static uint64_t SH_FLD_A_H10_VAL_LEN = 2616; // 72 +const static uint64_t SH_FLD_A_H11_VAL = 2617; // 72 +const static uint64_t SH_FLD_A_H11_VAL_LEN = 2618; // 72 +const static uint64_t SH_FLD_A_H12_VAL = 2619; // 72 +const static uint64_t SH_FLD_A_H12_VAL_LEN = 2620; // 72 +const static uint64_t SH_FLD_A_H1AP_AT_LIMIT = 2621; // 144 +const static uint64_t SH_FLD_A_H1ARATIO_VAL = 2622; // 72 +const static uint64_t SH_FLD_A_H1ARATIO_VAL_LEN = 2623; // 72 +const static uint64_t SH_FLD_A_H1CAL_EN = 2624; // 72 +const static uint64_t SH_FLD_A_H1CAL_VAL = 2625; // 72 +const static uint64_t SH_FLD_A_H1CAL_VAL_LEN = 2626; // 72 +const static uint64_t SH_FLD_A_H1E_VAL = 2627; // 120 +const static uint64_t SH_FLD_A_H1E_VAL_LEN = 2628; // 120 +const static uint64_t SH_FLD_A_H1O_VAL = 2629; // 120 +const static uint64_t SH_FLD_A_H1O_VAL_LEN = 2630; // 120 +const static uint64_t SH_FLD_A_H2E_VAL = 2631; // 72 +const static uint64_t SH_FLD_A_H2E_VAL_LEN = 2632; // 72 +const static uint64_t SH_FLD_A_H2O_VAL = 2633; // 72 +const static uint64_t SH_FLD_A_H2O_VAL_LEN = 2634; // 72 +const static uint64_t SH_FLD_A_H3E_VAL = 2635; // 72 +const static uint64_t SH_FLD_A_H3E_VAL_LEN = 2636; // 72 +const static uint64_t SH_FLD_A_H3O_VAL = 2637; // 72 +const static uint64_t SH_FLD_A_H3O_VAL_LEN = 2638; // 72 +const static uint64_t SH_FLD_A_H4E_VAL = 2639; // 72 +const static uint64_t SH_FLD_A_H4E_VAL_LEN = 2640; // 72 +const static uint64_t SH_FLD_A_H4O_VAL = 2641; // 72 +const static uint64_t SH_FLD_A_H4O_VAL_LEN = 2642; // 72 +const static uint64_t SH_FLD_A_H5E_VAL = 2643; // 72 +const static uint64_t SH_FLD_A_H5E_VAL_LEN = 2644; // 72 +const static uint64_t SH_FLD_A_H5O_VAL = 2645; // 72 +const static uint64_t SH_FLD_A_H5O_VAL_LEN = 2646; // 72 +const static uint64_t SH_FLD_A_H6_VAL = 2647; // 72 +const static uint64_t SH_FLD_A_H6_VAL_LEN = 2648; // 72 +const static uint64_t SH_FLD_A_H7_VAL = 2649; // 72 +const static uint64_t SH_FLD_A_H7_VAL_LEN = 2650; // 72 +const static uint64_t SH_FLD_A_H8_VAL = 2651; // 72 +const static uint64_t SH_FLD_A_H8_VAL_LEN = 2652; // 72 +const static uint64_t SH_FLD_A_H9_VAL = 2653; // 72 +const static uint64_t SH_FLD_A_H9_VAL_LEN = 2654; // 72 +const static uint64_t SH_FLD_A_INTEG_COARSE_GAIN = 2655; // 120 +const static uint64_t SH_FLD_A_INTEG_COARSE_GAIN_LEN = 2656; // 120 +const static uint64_t SH_FLD_A_ODD_INTEG_FINE_GAIN = 2657; // 120 +const static uint64_t SH_FLD_A_ODD_INTEG_FINE_GAIN_LEN = 2658; // 120 +const static uint64_t SH_FLD_A_OFFSET_E0 = 2659; // 120 +const static uint64_t SH_FLD_A_OFFSET_E0_LEN = 2660; // 120 +const static uint64_t SH_FLD_A_OFFSET_E1 = 2661; // 120 +const static uint64_t SH_FLD_A_OFFSET_E1_LEN = 2662; // 120 +const static uint64_t SH_FLD_A_OFFSET_O0 = 2663; // 120 +const static uint64_t SH_FLD_A_OFFSET_O0_LEN = 2664; // 120 +const static uint64_t SH_FLD_A_OFFSET_O1 = 2665; // 120 +const static uint64_t SH_FLD_A_OFFSET_O1_LEN = 2666; // 120 +const static uint64_t SH_FLD_A_PATH_OFF_EVEN = 2667; // 144 +const static uint64_t SH_FLD_A_PATH_OFF_EVEN_LEN = 2668; // 144 +const static uint64_t SH_FLD_A_PATH_OFF_ODD = 2669; // 144 +const static uint64_t SH_FLD_A_PATH_OFF_ODD_LEN = 2670; // 144 +const static uint64_t SH_FLD_A_PR_DFE_CLKADJ = 2671; // 120 +const static uint64_t SH_FLD_A_PR_DFE_CLKADJ_LEN = 2672; // 120 +const static uint64_t SH_FLD_B = 2673; // 8 +const static uint64_t SH_FLD_B0_63 = 2674; // 2 +const static uint64_t SH_FLD_B0_63_LEN = 2675; // 2 +const static uint64_t SH_FLD_B64_87 = 2676; // 2 +const static uint64_t SH_FLD_B64_87_LEN = 2677; // 2 +const static uint64_t SH_FLD_BACKUP_SEEPROM_SELECT = 2678; // 1 +const static uint64_t SH_FLD_BAD_128K_VP_OP = 2679; // 1 +const static uint64_t SH_FLD_BAD_ARRAY_ADDRESS_FACES = 2680; // 1 +const static uint64_t SH_FLD_BAD_ARRAY_ADDR_FACES = 2681; // 1 +const static uint64_t SH_FLD_BAD_ARRAY_ADDR_PIB = 2682; // 1 +const static uint64_t SH_FLD_BAD_BLOCK_LOCK = 2683; // 96 +const static uint64_t SH_FLD_BAD_BUS_LANE_ERR_CNTR_DIS_CLR = 2684; // 4 +const static uint64_t SH_FLD_BAD_DESKEW = 2685; // 96 +const static uint64_t SH_FLD_BAD_EYE_OPT_BER = 2686; // 96 +const static uint64_t SH_FLD_BAD_EYE_OPT_DDC = 2687; // 96 +const static uint64_t SH_FLD_BAD_EYE_OPT_HEIGHT = 2688; // 96 +const static uint64_t SH_FLD_BAD_EYE_OPT_WIDTH = 2689; // 96 +const static uint64_t SH_FLD_BAD_LANE1_GCRMSG = 2690; // 4 +const static uint64_t SH_FLD_BAD_LANE1_GCRMSG_LEN = 2691; // 4 +const static uint64_t SH_FLD_BAD_LANE2_GCRMSG = 2692; // 4 +const static uint64_t SH_FLD_BAD_LANE2_GCRMSG_LEN = 2693; // 4 +const static uint64_t SH_FLD_BAD_LANE_CODE_GCRMSG = 2694; // 4 +const static uint64_t SH_FLD_BAD_LANE_CODE_GCRMSG_LEN = 2695; // 4 +const static uint64_t SH_FLD_BAD_SKEW = 2696; // 96 +const static uint64_t SH_FLD_BANDSEL = 2697; // 20 +const static uint64_t SH_FLD_BANDSEL_LEN = 2698; // 20 +const static uint64_t SH_FLD_BANK = 2699; // 24 +const static uint64_t SH_FLD_BANK0_BIT_MAP = 2700; // 8 +const static uint64_t SH_FLD_BANK0_BIT_MAP_LEN = 2701; // 8 +const static uint64_t SH_FLD_BANK1_BIT_MAP = 2702; // 8 +const static uint64_t SH_FLD_BANK1_BIT_MAP_LEN = 2703; // 8 +const static uint64_t SH_FLD_BANK2_BIT_MAP = 2704; // 8 +const static uint64_t SH_FLD_BANK2_BIT_MAP_LEN = 2705; // 8 +const static uint64_t SH_FLD_BANK_GROUP0_BIT_MAP = 2706; // 8 +const static uint64_t SH_FLD_BANK_GROUP0_BIT_MAP_LEN = 2707; // 8 +const static uint64_t SH_FLD_BANK_GROUP1_BIT_MAP = 2708; // 8 +const static uint64_t SH_FLD_BANK_GROUP1_BIT_MAP_LEN = 2709; // 8 +const static uint64_t SH_FLD_BANK_ON_RUNN_MATCH = 2710; // 43 +const static uint64_t SH_FLD_BANK_PDWN = 2711; // 48 +const static uint64_t SH_FLD_BANK_PDWN_LEN = 2712; // 48 +const static uint64_t SH_FLD_BANK_SEL_A = 2713; // 48 +const static uint64_t SH_FLD_BAR = 2714; // 6 +const static uint64_t SH_FLD_BAR1_EN = 2715; // 4 +const static uint64_t SH_FLD_BAR1_MS_GROUP_CHIP = 2716; // 2 +const static uint64_t SH_FLD_BAR1_MS_GROUP_CHIP_LEN = 2717; // 2 +const static uint64_t SH_FLD_BAR1_SIZE = 2718; // 2 +const static uint64_t SH_FLD_BAR1_SIZE_LEN = 2719; // 2 +const static uint64_t SH_FLD_BAR1_STARTING_ADDRESS = 2720; // 4 +const static uint64_t SH_FLD_BAR1_STARTING_ADDRESS_LEN = 2721; // 4 +const static uint64_t SH_FLD_BAR1_SYSTEM = 2722; // 2 +const static uint64_t SH_FLD_BAR1_SYSTEM_LEN = 2723; // 2 +const static uint64_t SH_FLD_BARSEL = 2724; // 12 +const static uint64_t SH_FLD_BAR_LEN = 2725; // 6 +const static uint64_t SH_FLD_BAR_PE = 2726; // 13 +const static uint64_t SH_FLD_BAR_PE_MASK = 2727; // 9 +const static uint64_t SH_FLD_BAR_PIB_ON_ERROR1 = 2728; // 1 +const static uint64_t SH_FLD_BAR_PIB_ON_ERROR2 = 2729; // 1 +const static uint64_t SH_FLD_BAR_PIB_ON_ERROR3 = 2730; // 1 +const static uint64_t SH_FLD_BAR_PIB_ON_ERROR4 = 2731; // 1 +const static uint64_t SH_FLD_BAR_PIB_ON_ERROR5 = 2732; // 1 +const static uint64_t SH_FLD_BAR_PIB_ON_ERROR6 = 2733; // 1 +const static uint64_t SH_FLD_BAR_PIB_ON_ERROR7 = 2734; // 1 +const static uint64_t SH_FLD_BASE = 2735; // 26 +const static uint64_t SH_FLD_BASE_ADDR = 2736; // 2 +const static uint64_t SH_FLD_BASE_ADDR_LEN = 2737; // 2 +const static uint64_t SH_FLD_BASE_IDLE_COUNT = 2738; // 8 +const static uint64_t SH_FLD_BASE_IDLE_COUNT_LEN = 2739; // 8 +const static uint64_t SH_FLD_BASE_LEN = 2740; // 26 +const static uint64_t SH_FLD_BASE_UPPER_BITS = 2741; // 1 +const static uint64_t SH_FLD_BASE_UPPER_BITS_LEN = 2742; // 1 +const static uint64_t SH_FLD_BBUF_AIDX = 2743; // 3 +const static uint64_t SH_FLD_BBUF_AIDX_LEN = 2744; // 3 +const static uint64_t SH_FLD_BBUF_RSRC = 2745; // 3 +const static uint64_t SH_FLD_BBUF_RSRC_LEN = 2746; // 3 +const static uint64_t SH_FLD_BBUF_WSRC = 2747; // 3 +const static uint64_t SH_FLD_BBUF_WSRC_LEN = 2748; // 3 +const static uint64_t SH_FLD_BBWR_MASK = 2749; // 3 +const static uint64_t SH_FLD_BBWR_MASK_LEN = 2750; // 3 +const static uint64_t SH_FLD_BCAST_DONE = 2751; // 1 +const static uint64_t SH_FLD_BCDE_CE = 2752; // 1 +const static uint64_t SH_FLD_BCDE_CE_MASK = 2753; // 1 +const static uint64_t SH_FLD_BCDE_OCITRANS = 2754; // 1 +const static uint64_t SH_FLD_BCDE_OCITRANS_LEN = 2755; // 1 +const static uint64_t SH_FLD_BCDE_OCI_DATERR = 2756; // 1 +const static uint64_t SH_FLD_BCDE_OCI_DATERR_MASK = 2757; // 1 +const static uint64_t SH_FLD_BCDE_PB_ACK_DEAD = 2758; // 1 +const static uint64_t SH_FLD_BCDE_PB_ACK_DEAD_MASK = 2759; // 1 +const static uint64_t SH_FLD_BCDE_PB_ADRERR = 2760; // 1 +const static uint64_t SH_FLD_BCDE_PB_ADRERR_MASK = 2761; // 1 +const static uint64_t SH_FLD_BCDE_RDDATATO_ERR = 2762; // 1 +const static uint64_t SH_FLD_BCDE_RDDATATO_ERR_MASK = 2763; // 1 +const static uint64_t SH_FLD_BCDE_SETUP_ERR = 2764; // 1 +const static uint64_t SH_FLD_BCDE_SETUP_ERR_MASK = 2765; // 1 +const static uint64_t SH_FLD_BCDE_SUE_ERR = 2766; // 1 +const static uint64_t SH_FLD_BCDE_SUE_ERR_MASK = 2767; // 1 +const static uint64_t SH_FLD_BCDE_UE_ERR = 2768; // 1 +const static uint64_t SH_FLD_BCDE_UE_ERR_MASK = 2769; // 1 +const static uint64_t SH_FLD_BCESCR_OVERRIDE_EN = 2770; // 12 +const static uint64_t SH_FLD_BCE_BUSY_HIGH = 2771; // 12 +const static uint64_t SH_FLD_BCE_BUSY_LOW = 2772; // 12 +const static uint64_t SH_FLD_BCE_ERROR = 2773; // 12 +const static uint64_t SH_FLD_BCE_TIMEOUT = 2774; // 24 +const static uint64_t SH_FLD_BCUE_OCITRANS = 2775; // 1 +const static uint64_t SH_FLD_BCUE_OCITRANS_LEN = 2776; // 1 +const static uint64_t SH_FLD_BCUE_OCI_DATERR = 2777; // 1 +const static uint64_t SH_FLD_BCUE_OCI_DATERR_MASK = 2778; // 1 +const static uint64_t SH_FLD_BCUE_PB_ACK_DEAD = 2779; // 1 +const static uint64_t SH_FLD_BCUE_PB_ACK_DEAD_MASK = 2780; // 1 +const static uint64_t SH_FLD_BCUE_PB_ADRERR = 2781; // 1 +const static uint64_t SH_FLD_BCUE_PB_ADRERR_MASK = 2782; // 1 +const static uint64_t SH_FLD_BCUE_SETUP_ERR = 2783; // 1 +const static uint64_t SH_FLD_BCUE_SETUP_ERR_MASK = 2784; // 1 +const static uint64_t SH_FLD_BDF = 2785; // 52 +const static uint64_t SH_FLD_BDF2PE_00 = 2786; // 1 +const static uint64_t SH_FLD_BDF2PE_01 = 2787; // 1 +const static uint64_t SH_FLD_BDF2PE_02 = 2788; // 1 +const static uint64_t SH_FLD_BDF2PE_10 = 2789; // 1 +const static uint64_t SH_FLD_BDF2PE_11 = 2790; // 1 +const static uint64_t SH_FLD_BDF2PE_12 = 2791; // 1 +const static uint64_t SH_FLD_BDF2PE_20 = 2792; // 1 +const static uint64_t SH_FLD_BDF2PE_21 = 2793; // 1 +const static uint64_t SH_FLD_BDF2PE_22 = 2794; // 1 +const static uint64_t SH_FLD_BDF2PE_30 = 2795; // 1 +const static uint64_t SH_FLD_BDF2PE_31 = 2796; // 1 +const static uint64_t SH_FLD_BDF2PE_32 = 2797; // 1 +const static uint64_t SH_FLD_BDF2PE_40 = 2798; // 1 +const static uint64_t SH_FLD_BDF2PE_41 = 2799; // 1 +const static uint64_t SH_FLD_BDF2PE_42 = 2800; // 1 +const static uint64_t SH_FLD_BDF2PE_50 = 2801; // 1 +const static uint64_t SH_FLD_BDF2PE_51 = 2802; // 1 +const static uint64_t SH_FLD_BDF2PE_52 = 2803; // 1 +const static uint64_t SH_FLD_BDF_LEN = 2804; // 52 +const static uint64_t SH_FLD_BE = 2805; // 6 +const static uint64_t SH_FLD_BEAT_NUM = 2806; // 1 +const static uint64_t SH_FLD_BEAT_NUM_ERR = 2807; // 1 +const static uint64_t SH_FLD_BEAT_REC = 2808; // 1 +const static uint64_t SH_FLD_BEAT_REC_ERR = 2809; // 1 +const static uint64_t SH_FLD_BENIGN_PTR_DATA = 2810; // 2 +const static uint64_t SH_FLD_BER_CFG = 2811; // 120 +const static uint64_t SH_FLD_BER_CFG_LEN = 2812; // 120 +const static uint64_t SH_FLD_BER_CLR_COUNT_ON_READ_EN = 2813; // 6 +const static uint64_t SH_FLD_BER_CLR_TIMER_ON_READ_EN = 2814; // 6 +const static uint64_t SH_FLD_BER_COUNT_FREEZE_EN = 2815; // 6 +const static uint64_t SH_FLD_BER_COUNT_SEL = 2816; // 6 +const static uint64_t SH_FLD_BER_COUNT_SEL_LEN = 2817; // 6 +const static uint64_t SH_FLD_BER_DPIPE_MUX_SEL = 2818; // 120 +const static uint64_t SH_FLD_BER_EN = 2819; // 6 +const static uint64_t SH_FLD_BER_TIMEOUT = 2820; // 6 +const static uint64_t SH_FLD_BER_TIMEOUT_LEN = 2821; // 6 +const static uint64_t SH_FLD_BER_TIMER_FREEZE_EN = 2822; // 6 +const static uint64_t SH_FLD_BER_TIMER_SEL = 2823; // 6 +const static uint64_t SH_FLD_BER_TIMER_SEL_LEN = 2824; // 6 +const static uint64_t SH_FLD_BE_ACC_ERROR_0 = 2825; // 4 +const static uint64_t SH_FLD_BE_ACC_ERROR_1 = 2826; // 2 +const static uint64_t SH_FLD_BE_ACC_ERROR_2 = 2827; // 2 +const static uint64_t SH_FLD_BE_ACC_ERROR_3 = 2828; // 2 +const static uint64_t SH_FLD_BE_OV_ERROR_0 = 2829; // 4 +const static uint64_t SH_FLD_BE_OV_ERROR_1 = 2830; // 2 +const static uint64_t SH_FLD_BE_OV_ERROR_2 = 2831; // 2 +const static uint64_t SH_FLD_BE_OV_ERROR_3 = 2832; // 2 +const static uint64_t SH_FLD_BGOFFSET = 2833; // 14 +const static uint64_t SH_FLD_BGOFFSET_LEN = 2834; // 14 +const static uint64_t SH_FLD_BG_SCAN_RATE = 2835; // 3 +const static uint64_t SH_FLD_BG_SCAN_RATE_LEN = 2836; // 3 +const static uint64_t SH_FLD_BHR_DIR_STATE = 2837; // 2 +const static uint64_t SH_FLD_BHR_DIR_STATE_LEN = 2838; // 2 +const static uint64_t SH_FLD_BIG_RSP = 2839; // 1 +const static uint64_t SH_FLD_BIG_STEP = 2840; // 8 +const static uint64_t SH_FLD_BIG_STEP_LEN = 2841; // 8 +const static uint64_t SH_FLD_BISTCLK_EN = 2842; // 2 +const static uint64_t SH_FLD_BISTCLK_EN_LEN = 2843; // 2 +const static uint64_t SH_FLD_BIST_BIT_FAIL_TH = 2844; // 1 +const static uint64_t SH_FLD_BIST_BIT_FAIL_TH_LEN = 2845; // 1 +const static uint64_t SH_FLD_BIST_BUS_DATA_MODE = 2846; // 6 +const static uint64_t SH_FLD_BIST_COMPLETE = 2847; // 1 +const static uint64_t SH_FLD_BIST_CUPLL_LOCK_CHECK_EN = 2848; // 6 +const static uint64_t SH_FLD_BIST_CU_PLL_ERR = 2849; // 4 +const static uint64_t SH_FLD_BIST_DONE = 2850; // 6 +const static uint64_t SH_FLD_BIST_EN = 2851; // 13 +const static uint64_t SH_FLD_BIST_ENABLE = 2852; // 1 +const static uint64_t SH_FLD_BIST_ERR = 2853; // 96 +const static uint64_t SH_FLD_BIST_ERROR = 2854; // 1 +const static uint64_t SH_FLD_BIST_ERROR_LEN = 2855; // 1 +const static uint64_t SH_FLD_BIST_ERR_A = 2856; // 48 +const static uint64_t SH_FLD_BIST_ERR_B = 2857; // 48 +const static uint64_t SH_FLD_BIST_ERR_E = 2858; // 48 +const static uint64_t SH_FLD_BIST_EXT_START_MODE = 2859; // 6 +const static uint64_t SH_FLD_BIST_EYE_A_WIDTH = 2860; // 6 +const static uint64_t SH_FLD_BIST_EYE_A_WIDTH_LEN = 2861; // 6 +const static uint64_t SH_FLD_BIST_EYE_B_WIDTH = 2862; // 6 +const static uint64_t SH_FLD_BIST_EYE_B_WIDTH_LEN = 2863; // 6 +const static uint64_t SH_FLD_BIST_INIT_DISABLE = 2864; // 6 +const static uint64_t SH_FLD_BIST_INIT_DISABLE_LEN = 2865; // 6 +const static uint64_t SH_FLD_BIST_INIT_DONE = 2866; // 6 +const static uint64_t SH_FLD_BIST_JITTER_PULSE_SEL = 2867; // 4 +const static uint64_t SH_FLD_BIST_JITTER_PULSE_SEL_LEN = 2868; // 4 +const static uint64_t SH_FLD_BIST_LL_ERR = 2869; // 2 +const static uint64_t SH_FLD_BIST_LL_TEST_EN = 2870; // 2 +const static uint64_t SH_FLD_BIST_MIN_EYE_WIDTH = 2871; // 6 +const static uint64_t SH_FLD_BIST_MIN_EYE_WIDTH_LEN = 2872; // 6 +const static uint64_t SH_FLD_BIST_NO_EDGE_DET = 2873; // 6 +const static uint64_t SH_FLD_BIST_PLL_LOCK_TIMEOUT = 2874; // 4 +const static uint64_t SH_FLD_BIST_PLL_LOCK_TIMEOUT_LEN = 2875; // 4 +const static uint64_t SH_FLD_BIST_PRBS_PROP_TIME = 2876; // 6 +const static uint64_t SH_FLD_BIST_PRBS_PROP_TIME_LEN = 2877; // 6 +const static uint64_t SH_FLD_BIST_PRBS_TEST_TIME = 2878; // 6 +const static uint64_t SH_FLD_BIST_PRBS_TEST_TIME_LEN = 2879; // 6 +const static uint64_t SH_FLD_BIST_STORE_EYES_BANK_SEL = 2880; // 6 +const static uint64_t SH_FLD_BIST_STORE_EYES_BANK_SEL_LEN = 2881; // 6 +const static uint64_t SH_FLD_BIST_STORE_EYES_LANE_SEL = 2882; // 6 +const static uint64_t SH_FLD_BIST_STORE_EYES_LANE_SEL_LEN = 2883; // 6 +const static uint64_t SH_FLD_BITS = 2884; // 27 +const static uint64_t SH_FLD_BITSEL = 2885; // 4 +const static uint64_t SH_FLD_BITSEL_LEN = 2886; // 4 +const static uint64_t SH_FLD_BITS_LEN = 2887; // 27 +const static uint64_t SH_FLD_BIT_RATE_DIVISOR_0 = 2888; // 6 +const static uint64_t SH_FLD_BIT_RATE_DIVISOR_0_LEN = 2889; // 6 +const static uint64_t SH_FLD_BIT_RATE_DIVISOR_1 = 2890; // 3 +const static uint64_t SH_FLD_BIT_RATE_DIVISOR_1_LEN = 2891; // 3 +const static uint64_t SH_FLD_BIT_RATE_DIVISOR_2 = 2892; // 3 +const static uint64_t SH_FLD_BIT_RATE_DIVISOR_2_LEN = 2893; // 3 +const static uint64_t SH_FLD_BIT_RATE_DIVISOR_3 = 2894; // 3 +const static uint64_t SH_FLD_BIT_RATE_DIVISOR_3_LEN = 2895; // 3 +const static uint64_t SH_FLD_BIT_RATE_DIVISOR_VALUE = 2896; // 1 +const static uint64_t SH_FLD_BIT_RATE_DIVISOR_VALUE_LEN = 2897; // 1 +const static uint64_t SH_FLD_BKINV_INTERLOCK_DIS = 2898; // 1 +const static uint64_t SH_FLD_BKLG0 = 2899; // 1 +const static uint64_t SH_FLD_BKLG0_LEN = 2900; // 1 +const static uint64_t SH_FLD_BKLG1 = 2901; // 1 +const static uint64_t SH_FLD_BKLG1_LEN = 2902; // 1 +const static uint64_t SH_FLD_BKLG2 = 2903; // 1 +const static uint64_t SH_FLD_BKLG2_LEN = 2904; // 1 +const static uint64_t SH_FLD_BKLG3 = 2905; // 1 +const static uint64_t SH_FLD_BKLG3_LEN = 2906; // 1 +const static uint64_t SH_FLD_BKLG4 = 2907; // 1 +const static uint64_t SH_FLD_BKLG4_LEN = 2908; // 1 +const static uint64_t SH_FLD_BKLG5 = 2909; // 1 +const static uint64_t SH_FLD_BKLG5_LEN = 2910; // 1 +const static uint64_t SH_FLD_BKLG6 = 2911; // 1 +const static uint64_t SH_FLD_BKLG6_LEN = 2912; // 1 +const static uint64_t SH_FLD_BKLG7 = 2913; // 1 +const static uint64_t SH_FLD_BKLG7_LEN = 2914; // 1 +const static uint64_t SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR = 2915; // 6 +const static uint64_t SH_FLD_BLK_UPDT_DONE = 2916; // 1 +const static uint64_t SH_FLD_BLOCK = 2917; // 24 +const static uint64_t SH_FLD_BLOCKID = 2918; // 15 +const static uint64_t SH_FLD_BLOCKID_LEN = 2919; // 15 +const static uint64_t SH_FLD_BLOCKY0 = 2920; // 24 +const static uint64_t SH_FLD_BLOCKY1 = 2921; // 24 +const static uint64_t SH_FLD_BLOCK_ACTIVE = 2922; // 6 +const static uint64_t SH_FLD_BLOCK_CMD_OVERLAP = 2923; // 1 +const static uint64_t SH_FLD_BLOCK_INTR_INPUTS = 2924; // 24 +const static uint64_t SH_FLD_BLOCK_LEN = 2925; // 24 +const static uint64_t SH_FLD_BLOCK_MUX_PORT_SEL = 2926; // 2 +const static uint64_t SH_FLD_BLOCK_MUX_PORT_SEL_LEN = 2927; // 2 +const static uint64_t SH_FLD_BLOCK_SEL = 2928; // 2 +const static uint64_t SH_FLD_BLOCK_SEL_LEN = 2929; // 2 +const static uint64_t SH_FLD_BNDY = 2930; // 43 +const static uint64_t SH_FLD_BOOT_VECTOR_WORD0 = 2931; // 1 +const static uint64_t SH_FLD_BOOT_VECTOR_WORD0_LEN = 2932; // 1 +const static uint64_t SH_FLD_BOOT_VECTOR_WORD1 = 2933; // 1 +const static uint64_t SH_FLD_BOOT_VECTOR_WORD1_LEN = 2934; // 1 +const static uint64_t SH_FLD_BOOT_VECTOR_WORD2 = 2935; // 1 +const static uint64_t SH_FLD_BOOT_VECTOR_WORD2_LEN = 2936; // 1 +const static uint64_t SH_FLD_BOOT_VECTOR_WORD3 = 2937; // 1 +const static uint64_t SH_FLD_BOOT_VECTOR_WORD3_LEN = 2938; // 1 +const static uint64_t SH_FLD_BRAZOS = 2939; // 1 +const static uint64_t SH_FLD_BRICK = 2940; // 16 +const static uint64_t SH_FLD_BRICK_DEBUG_MODE = 2941; // 6 +const static uint64_t SH_FLD_BRICK_ENABLE = 2942; // 6 +const static uint64_t SH_FLD_BRIDGE_ENABLE = 2943; // 1 +const static uint64_t SH_FLD_BRK0 = 2944; // 1 +const static uint64_t SH_FLD_BRK0_CLUSTER = 2945; // 1 +const static uint64_t SH_FLD_BRK0_CLUSTER_LEN = 2946; // 1 +const static uint64_t SH_FLD_BRK0_NVL = 2947; // 3 +const static uint64_t SH_FLD_BRK0_RLX = 2948; // 3 +const static uint64_t SH_FLD_BRK1 = 2949; // 1 +const static uint64_t SH_FLD_BRK1_CLUSTER = 2950; // 1 +const static uint64_t SH_FLD_BRK1_CLUSTER_LEN = 2951; // 1 +const static uint64_t SH_FLD_BRK1_NVL = 2952; // 3 +const static uint64_t SH_FLD_BRK1_RLX = 2953; // 3 +const static uint64_t SH_FLD_BRK2 = 2954; // 1 +const static uint64_t SH_FLD_BRK2_CLUSTER = 2955; // 1 +const static uint64_t SH_FLD_BRK2_CLUSTER_LEN = 2956; // 1 +const static uint64_t SH_FLD_BRK3 = 2957; // 1 +const static uint64_t SH_FLD_BRK3_CLUSTER = 2958; // 1 +const static uint64_t SH_FLD_BRK3_CLUSTER_LEN = 2959; // 1 +const static uint64_t SH_FLD_BRK4 = 2960; // 1 +const static uint64_t SH_FLD_BRK4_CLUSTER = 2961; // 1 +const static uint64_t SH_FLD_BRK4_CLUSTER_LEN = 2962; // 1 +const static uint64_t SH_FLD_BRK5 = 2963; // 1 +const static uint64_t SH_FLD_BRK5_CLUSTER = 2964; // 1 +const static uint64_t SH_FLD_BRK5_CLUSTER_LEN = 2965; // 1 +const static uint64_t SH_FLD_BROADCAST_SYNC_EN = 2966; // 2 +const static uint64_t SH_FLD_BROADCAST_SYNC_WAIT = 2967; // 2 +const static uint64_t SH_FLD_BROADCAST_SYNC_WAIT_LEN = 2968; // 2 +const static uint64_t SH_FLD_BUF0_REG_DATA0 = 2969; // 2 +const static uint64_t SH_FLD_BUF0_REG_DATA0_LEN = 2970; // 2 +const static uint64_t SH_FLD_BUF1_REG_DATA0 = 2971; // 1 +const static uint64_t SH_FLD_BUF1_REG_DATA0_LEN = 2972; // 1 +const static uint64_t SH_FLD_BUF1_REG_DATA1 = 2973; // 1 +const static uint64_t SH_FLD_BUF1_REG_DATA1_LEN = 2974; // 1 +const static uint64_t SH_FLD_BUFFER = 2975; // 12 +const static uint64_t SH_FLD_BUFFER_OVERRUN = 2976; // 8 +const static uint64_t SH_FLD_BUFFER_STATUS = 2977; // 6 +const static uint64_t SH_FLD_BUFFER_STATUS_LEN = 2978; // 6 +const static uint64_t SH_FLD_BUF_ALLOC_A = 2979; // 4 +const static uint64_t SH_FLD_BUF_ALLOC_B = 2980; // 4 +const static uint64_t SH_FLD_BUF_ALLOC_C = 2981; // 4 +const static uint64_t SH_FLD_BUF_ALLOC_W = 2982; // 4 +const static uint64_t SH_FLD_BUF_INVALIDATE_CTL = 2983; // 4 +const static uint64_t SH_FLD_BURST_WINDOW = 2984; // 8 +const static uint64_t SH_FLD_BURST_WINDOW_LEN = 2985; // 8 +const static uint64_t SH_FLD_BUSY = 2986; // 44 +const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD0 = 2987; // 8 +const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD0_LEN = 2988; // 8 +const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD1 = 2989; // 8 +const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD1_LEN = 2990; // 8 +const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD2 = 2991; // 8 +const static uint64_t SH_FLD_BUSY_COUNTER_THRESHOLD2_LEN = 2992; // 8 +const static uint64_t SH_FLD_BUSY_COUNTER_WINDOW_SELECT = 2993; // 8 +const static uint64_t SH_FLD_BUSY_COUNTER_WINDOW_SELECT_LEN = 2994; // 8 +const static uint64_t SH_FLD_BUSY_ENABLE = 2995; // 3 +const static uint64_t SH_FLD_BUSY_RESPONSE_CODE = 2996; // 1 +const static uint64_t SH_FLD_BUSY_RESPONSE_CODE_LEN = 2997; // 1 +const static uint64_t SH_FLD_BUSY_RESPONSE_CODE_NO_1 = 2998; // 1 +const static uint64_t SH_FLD_BUSY_RESPONSE_CODE_NO_1_LEN = 2999; // 1 +const static uint64_t SH_FLD_BUSY_STATUS = 3000; // 1 +const static uint64_t SH_FLD_BUSY_STATUS_LEN = 3001; // 1 +const static uint64_t SH_FLD_BUS_ADDR_NVLD_0 = 3002; // 1 +const static uint64_t SH_FLD_BUS_ADDR_NVLD_1 = 3003; // 1 +const static uint64_t SH_FLD_BUS_ADDR_NVLD_2 = 3004; // 1 +const static uint64_t SH_FLD_BUS_ADDR_NVLD_3 = 3005; // 1 +const static uint64_t SH_FLD_BUS_ADDR_P_ERR_0 = 3006; // 1 +const static uint64_t SH_FLD_BUS_ADDR_P_ERR_1 = 3007; // 1 +const static uint64_t SH_FLD_BUS_ADDR_P_ERR_2 = 3008; // 1 +const static uint64_t SH_FLD_BUS_ADDR_P_ERR_3 = 3009; // 1 +const static uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_0 = 3010; // 1 +const static uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_1 = 3011; // 1 +const static uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_2 = 3012; // 1 +const static uint64_t SH_FLD_BUS_ARBITRATION_LOST_ERROR_3 = 3013; // 1 +const static uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_0 = 3014; // 1 +const static uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_1 = 3015; // 1 +const static uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_2 = 3016; // 1 +const static uint64_t SH_FLD_BUS_BACK_END_ACCESS_ERROR_3 = 3017; // 1 +const static uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_0 = 3018; // 1 +const static uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_1 = 3019; // 1 +const static uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_2 = 3020; // 1 +const static uint64_t SH_FLD_BUS_BACK_END_OVERRUN_ERROR_3 = 3021; // 1 +const static uint64_t SH_FLD_BUS_BUSY_0 = 3022; // 1 +const static uint64_t SH_FLD_BUS_BUSY_1 = 3023; // 1 +const static uint64_t SH_FLD_BUS_BUSY_2 = 3024; // 1 +const static uint64_t SH_FLD_BUS_BUSY_3 = 3025; // 1 +const static uint64_t SH_FLD_BUS_COMMAND_COMPLETE_0 = 3026; // 1 +const static uint64_t SH_FLD_BUS_COMMAND_COMPLETE_1 = 3027; // 1 +const static uint64_t SH_FLD_BUS_COMMAND_COMPLETE_2 = 3028; // 1 +const static uint64_t SH_FLD_BUS_COMMAND_COMPLETE_3 = 3029; // 1 +const static uint64_t SH_FLD_BUS_DATA_REQUEST_0 = 3030; // 1 +const static uint64_t SH_FLD_BUS_DATA_REQUEST_1 = 3031; // 1 +const static uint64_t SH_FLD_BUS_DATA_REQUEST_2 = 3032; // 1 +const static uint64_t SH_FLD_BUS_DATA_REQUEST_3 = 3033; // 1 +const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_0 = 3034; // 1 +const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_0_LEN = 3035; // 1 +const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_1 = 3036; // 1 +const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_1_LEN = 3037; // 1 +const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_2 = 3038; // 1 +const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_2_LEN = 3039; // 1 +const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_3 = 3040; // 1 +const static uint64_t SH_FLD_BUS_FIFO_ENTRY_COUNT_3_LEN = 3041; // 1 +const static uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_0 = 3042; // 1 +const static uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_1 = 3043; // 1 +const static uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_2 = 3044; // 1 +const static uint64_t SH_FLD_BUS_I2C_INTERFACE_BUSY_3 = 3045; // 1 +const static uint64_t SH_FLD_BUS_I2C_PORT_BUSY_0 = 3046; // 1 +const static uint64_t SH_FLD_BUS_I2C_PORT_BUSY_1 = 3047; // 1 +const static uint64_t SH_FLD_BUS_I2C_PORT_BUSY_2 = 3048; // 1 +const static uint64_t SH_FLD_BUS_I2C_PORT_BUSY_3 = 3049; // 1 +const static uint64_t SH_FLD_BUS_ID = 3050; // 12 +const static uint64_t SH_FLD_BUS_ID_LEN = 3051; // 12 +const static uint64_t SH_FLD_BUS_INVALID_COMMAND_0 = 3052; // 1 +const static uint64_t SH_FLD_BUS_INVALID_COMMAND_1 = 3053; // 1 +const static uint64_t SH_FLD_BUS_INVALID_COMMAND_2 = 3054; // 1 +const static uint64_t SH_FLD_BUS_INVALID_COMMAND_3 = 3055; // 1 +const static uint64_t SH_FLD_BUS_LB_PARITY_ERROR_0 = 3056; // 1 +const static uint64_t SH_FLD_BUS_LB_PARITY_ERROR_1 = 3057; // 1 +const static uint64_t SH_FLD_BUS_LB_PARITY_ERROR_2 = 3058; // 1 +const static uint64_t SH_FLD_BUS_LB_PARITY_ERROR_3 = 3059; // 1 +const static uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_0 = 3060; // 1 +const static uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_1 = 3061; // 1 +const static uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_2 = 3062; // 1 +const static uint64_t SH_FLD_BUS_NACK_RECEIVED_ERROR_3 = 3063; // 1 +const static uint64_t SH_FLD_BUS_PARITY_ERROR_0 = 3064; // 1 +const static uint64_t SH_FLD_BUS_PARITY_ERROR_1 = 3065; // 1 +const static uint64_t SH_FLD_BUS_PARITY_ERROR_2 = 3066; // 1 +const static uint64_t SH_FLD_BUS_PARITY_ERROR_3 = 3067; // 1 +const static uint64_t SH_FLD_BUS_PAR_ERR_0 = 3068; // 1 +const static uint64_t SH_FLD_BUS_PAR_ERR_1 = 3069; // 1 +const static uint64_t SH_FLD_BUS_PAR_ERR_2 = 3070; // 1 +const static uint64_t SH_FLD_BUS_PAR_ERR_3 = 3071; // 1 +const static uint64_t SH_FLD_BUS_READ_NVLD_0 = 3072; // 1 +const static uint64_t SH_FLD_BUS_READ_NVLD_1 = 3073; // 1 +const static uint64_t SH_FLD_BUS_READ_NVLD_2 = 3074; // 1 +const static uint64_t SH_FLD_BUS_READ_NVLD_3 = 3075; // 1 +const static uint64_t SH_FLD_BUS_STOP_ERROR_0 = 3076; // 1 +const static uint64_t SH_FLD_BUS_STOP_ERROR_1 = 3077; // 1 +const static uint64_t SH_FLD_BUS_STOP_ERROR_2 = 3078; // 1 +const static uint64_t SH_FLD_BUS_STOP_ERROR_3 = 3079; // 1 +const static uint64_t SH_FLD_BUS_WIDTH = 3080; // 4 +const static uint64_t SH_FLD_BUS_WIDTH_LEN = 3081; // 4 +const static uint64_t SH_FLD_BUS_WRITE_NVLD_0 = 3082; // 1 +const static uint64_t SH_FLD_BUS_WRITE_NVLD_1 = 3083; // 1 +const static uint64_t SH_FLD_BUS_WRITE_NVLD_2 = 3084; // 1 +const static uint64_t SH_FLD_BUS_WRITE_NVLD_3 = 3085; // 1 +const static uint64_t SH_FLD_BYPASSCLKOUT = 3086; // 3 +const static uint64_t SH_FLD_BYPASSING_RESET_SEQUENCE_PIB_I2CM = 3087; // 1 +const static uint64_t SH_FLD_BYPASSN = 3088; // 10 +const static uint64_t SH_FLD_BYTE0_SEL = 3089; // 8 +const static uint64_t SH_FLD_BYTE0_SEL_LEN = 3090; // 8 +const static uint64_t SH_FLD_BYTE1_SEL = 3091; // 8 +const static uint64_t SH_FLD_BYTE1_SEL_LEN = 3092; // 8 +const static uint64_t SH_FLD_BYTE2_SEL = 3093; // 8 +const static uint64_t SH_FLD_BYTE2_SEL_LEN = 3094; // 8 +const static uint64_t SH_FLD_BYTE3_SEL = 3095; // 8 +const static uint64_t SH_FLD_BYTE3_SEL_LEN = 3096; // 8 +const static uint64_t SH_FLD_B_BAD_DFE_CONV = 3097; // 144 +const static uint64_t SH_FLD_B_BANK_CONTROLS = 3098; // 48 +const static uint64_t SH_FLD_B_BANK_CONTROLS_LEN = 3099; // 48 +const static uint64_t SH_FLD_B_BIST_EN = 3100; // 2 +const static uint64_t SH_FLD_B_CONTROLS = 3101; // 48 +const static uint64_t SH_FLD_B_CONTROLS_LEN = 3102; // 48 +const static uint64_t SH_FLD_B_CTLE_COARSE = 3103; // 48 +const static uint64_t SH_FLD_B_CTLE_COARSE_LEN = 3104; // 48 +const static uint64_t SH_FLD_B_CTLE_GAIN = 3105; // 48 +const static uint64_t SH_FLD_B_CTLE_GAIN_LEN = 3106; // 48 +const static uint64_t SH_FLD_B_EVEN_INTEG_FINE_GAIN = 3107; // 48 +const static uint64_t SH_FLD_B_EVEN_INTEG_FINE_GAIN_LEN = 3108; // 48 +const static uint64_t SH_FLD_B_H1AP_AT_LIMIT = 3109; // 144 +const static uint64_t SH_FLD_B_H1E_VAL = 3110; // 48 +const static uint64_t SH_FLD_B_H1E_VAL_LEN = 3111; // 48 +const static uint64_t SH_FLD_B_H1O_VAL = 3112; // 48 +const static uint64_t SH_FLD_B_H1O_VAL_LEN = 3113; // 48 +const static uint64_t SH_FLD_B_INTEG_COARSE_GAIN = 3114; // 48 +const static uint64_t SH_FLD_B_INTEG_COARSE_GAIN_LEN = 3115; // 48 +const static uint64_t SH_FLD_B_ODD_INTEG_FINE_GAIN = 3116; // 48 +const static uint64_t SH_FLD_B_ODD_INTEG_FINE_GAIN_LEN = 3117; // 48 +const static uint64_t SH_FLD_B_OFFSET_E0 = 3118; // 48 +const static uint64_t SH_FLD_B_OFFSET_E0_LEN = 3119; // 48 +const static uint64_t SH_FLD_B_OFFSET_E1 = 3120; // 48 +const static uint64_t SH_FLD_B_OFFSET_E1_LEN = 3121; // 48 +const static uint64_t SH_FLD_B_OFFSET_O0 = 3122; // 48 +const static uint64_t SH_FLD_B_OFFSET_O0_LEN = 3123; // 48 +const static uint64_t SH_FLD_B_OFFSET_O1 = 3124; // 48 +const static uint64_t SH_FLD_B_OFFSET_O1_LEN = 3125; // 48 +const static uint64_t SH_FLD_B_PATH_OFF_EVEN = 3126; // 48 +const static uint64_t SH_FLD_B_PATH_OFF_EVEN_LEN = 3127; // 48 +const static uint64_t SH_FLD_B_PATH_OFF_ODD = 3128; // 48 +const static uint64_t SH_FLD_B_PATH_OFF_ODD_LEN = 3129; // 48 +const static uint64_t SH_FLD_B_PR_DFE_CLKADJ = 3130; // 48 +const static uint64_t SH_FLD_B_PR_DFE_CLKADJ_LEN = 3131; // 48 +const static uint64_t SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE = 3132; // 12 +const static uint64_t SH_FLD_C1_COUNT_LT = 3133; // 86 +const static uint64_t SH_FLD_C1_COUNT_LT_LEN = 3134; // 86 +const static uint64_t SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE = 3135; // 12 +const static uint64_t SH_FLD_C1_INAROW_MODE = 3136; // 86 +const static uint64_t SH_FLD_C2_COUNT_LT = 3137; // 86 +const static uint64_t SH_FLD_C2_COUNT_LT_LEN = 3138; // 86 +const static uint64_t SH_FLD_C2_INAROW_MODE = 3139; // 86 +const static uint64_t SH_FLD_C405DCU_M_TIMEOUT = 3140; // 1 +const static uint64_t SH_FLD_C405DCU_M_TIMEOUT_MASK = 3141; // 1 +const static uint64_t SH_FLD_C405ICU_M_TIMEOUT = 3142; // 1 +const static uint64_t SH_FLD_C405ICU_M_TIMEOUT_MASK = 3143; // 1 +const static uint64_t SH_FLD_C405_DCU_ECC_CE = 3144; // 1 +const static uint64_t SH_FLD_C405_DCU_ECC_UE = 3145; // 1 +const static uint64_t SH_FLD_C405_ECC_CE = 3146; // 1 +const static uint64_t SH_FLD_C405_ECC_CE_MASK = 3147; // 1 +const static uint64_t SH_FLD_C405_ECC_UE = 3148; // 1 +const static uint64_t SH_FLD_C405_ECC_UE_MASK = 3149; // 1 +const static uint64_t SH_FLD_C405_ICU_ECC_CE = 3150; // 1 +const static uint64_t SH_FLD_C405_ICU_ECC_UE = 3151; // 1 +const static uint64_t SH_FLD_C405_OCI_MACHINECHECK = 3152; // 1 +const static uint64_t SH_FLD_C405_OCI_MACHINECHECK_MASK = 3153; // 1 +const static uint64_t SH_FLD_CACHE_CTRL_ARY_SELECT = 3154; // 4 +const static uint64_t SH_FLD_CACHE_CTRL_ARY_SELECT_LEN = 3155; // 4 +const static uint64_t SH_FLD_CACHE_INHIBITED_HIT_CACHEABLE_ERROR = 3156; // 12 +const static uint64_t SH_FLD_CACHE_RD_CE = 3157; // 12 +const static uint64_t SH_FLD_CACHE_RD_CE_AND_UE = 3158; // 12 +const static uint64_t SH_FLD_CACHE_RD_SUE = 3159; // 12 +const static uint64_t SH_FLD_CACHE_RD_UE = 3160; // 12 +const static uint64_t SH_FLD_CACHE_UE_SUE_DETECTED_ON_MODIFIED_LINE_BY_CO = 3161; // 12 +const static uint64_t SH_FLD_CACHE_UE_SUE_DETECTED_ON_NON_MODIFIED_LINE_BY_CO = 3162; // 12 +const static uint64_t SH_FLD_CAC_ALLOC_DIS = 3163; // 2 +const static uint64_t SH_FLD_CAC_PERR_CHK_DIS = 3164; // 2 +const static uint64_t SH_FLD_CAL0_INVALID_ACCESS = 3165; // 8 +const static uint64_t SH_FLD_CAL0_PE = 3166; // 8 +const static uint64_t SH_FLD_CAL1_INVALID_ACCESS = 3167; // 8 +const static uint64_t SH_FLD_CAL1_PE = 3168; // 8 +const static uint64_t SH_FLD_CAL2_INVALID_ACCESS = 3169; // 8 +const static uint64_t SH_FLD_CAL2_PE = 3170; // 8 +const static uint64_t SH_FLD_CAL3_INVALID_ACCESS = 3171; // 8 +const static uint64_t SH_FLD_CAL3_PE = 3172; // 8 +const static uint64_t SH_FLD_CALIBRATION_ENABLE = 3173; // 8 +const static uint64_t SH_FLD_CALRECAL = 3174; // 10 +const static uint64_t SH_FLD_CALREQ = 3175; // 10 +const static uint64_t SH_FLD_CAL_LANE_GCRMSG = 3176; // 4 +const static uint64_t SH_FLD_CAL_LANE_GCRMSG_LEN = 3177; // 4 +const static uint64_t SH_FLD_CAL_LANE_PHY_GCRMSG = 3178; // 6 +const static uint64_t SH_FLD_CAL_LANE_PHY_GCRMSG_LEN = 3179; // 6 +const static uint64_t SH_FLD_CAL_LANE_SEL = 3180; // 188 +const static uint64_t SH_FLD_CAL_LANE_VAL_GCRMSG = 3181; // 4 +const static uint64_t SH_FLD_CAL_SM_1HOT = 3182; // 8 +const static uint64_t SH_FLD_CAM256_MAX_CNT = 3183; // 6 +const static uint64_t SH_FLD_CAM256_MAX_CNT_LEN = 3184; // 6 +const static uint64_t SH_FLD_CAM_DISPLAY_REG_0 = 3185; // 1 +const static uint64_t SH_FLD_CAM_DISPLAY_REG_0_LEN = 3186; // 1 +const static uint64_t SH_FLD_CAM_DISPLAY_REG_1 = 3187; // 1 +const static uint64_t SH_FLD_CAM_DISPLAY_REG_1_LEN = 3188; // 1 +const static uint64_t SH_FLD_CAPP_ERROR = 3189; // 9 +const static uint64_t SH_FLD_CAPP_ERROR_MASK = 3190; // 9 +const static uint64_t SH_FLD_CAPSEL = 3191; // 4 +const static uint64_t SH_FLD_CASCADE = 3192; // 19 +const static uint64_t SH_FLD_CASCADE_LEN = 3193; // 19 +const static uint64_t SH_FLD_CC = 3194; // 10 +const static uint64_t SH_FLD_CCALBANDSEL = 3195; // 10 +const static uint64_t SH_FLD_CCALBANDSEL_LEN = 3196; // 10 +const static uint64_t SH_FLD_CCALCOMP = 3197; // 10 +const static uint64_t SH_FLD_CCALCVHOLD = 3198; // 10 +const static uint64_t SH_FLD_CCALERR = 3199; // 10 +const static uint64_t SH_FLD_CCALFMAX = 3200; // 10 +const static uint64_t SH_FLD_CCALFMIN = 3201; // 10 +const static uint64_t SH_FLD_CCALLOAD = 3202; // 10 +const static uint64_t SH_FLD_CCALMETH = 3203; // 10 +const static uint64_t SH_FLD_CCFG_GPTR = 3204; // 43 +const static uint64_t SH_FLD_CCS_ARRAY_CE_ERR_INJ = 3205; // 2 +const static uint64_t SH_FLD_CCS_ARRAY_CE_ERR_INJ_MODE = 3206; // 2 +const static uint64_t SH_FLD_CCS_ARRAY_UE_ERR_INJ = 3207; // 2 +const static uint64_t SH_FLD_CCS_ARRAY_UE_ERR_INJ_MODE = 3208; // 2 +const static uint64_t SH_FLD_CCS_CNTLQ_PE_HOLD_OUT = 3209; // 2 +const static uint64_t SH_FLD_CCS_FSM_INJ_MODE = 3210; // 2 +const static uint64_t SH_FLD_CCS_FSM_INJ_REG = 3211; // 2 +const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE0 = 3212; // 2 +const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE0_LEN = 3213; // 2 +const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE1 = 3214; // 2 +const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE1_LEN = 3215; // 2 +const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE2 = 3216; // 2 +const static uint64_t SH_FLD_CCS_LOOP_COUNTER_COMPARE2_LEN = 3217; // 2 +const static uint64_t SH_FLD_CC_ACTIVITY_0 = 3218; // 1 +const static uint64_t SH_FLD_CC_ACTIVITY_0_LEN = 3219; // 1 +const static uint64_t SH_FLD_CC_ACTIVITY_1 = 3220; // 1 +const static uint64_t SH_FLD_CC_ACTIVITY_1_LEN = 3221; // 1 +const static uint64_t SH_FLD_CC_ACTIVITY_2 = 3222; // 1 +const static uint64_t SH_FLD_CC_ACTIVITY_2_LEN = 3223; // 1 +const static uint64_t SH_FLD_CC_ACTIVITY_3 = 3224; // 1 +const static uint64_t SH_FLD_CC_ACTIVITY_3_LEN = 3225; // 1 +const static uint64_t SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC = 3226; // 43 +const static uint64_t SH_FLD_CC_CTRL_OPCG_DONE_DC = 3227; // 43 +const static uint64_t SH_FLD_CC_ENABLE_0 = 3228; // 1 +const static uint64_t SH_FLD_CC_ENABLE_1 = 3229; // 1 +const static uint64_t SH_FLD_CC_ENABLE_2 = 3230; // 1 +const static uint64_t SH_FLD_CC_ENABLE_3 = 3231; // 1 +const static uint64_t SH_FLD_CC_ID_0 = 3232; // 1 +const static uint64_t SH_FLD_CC_ID_0_LEN = 3233; // 1 +const static uint64_t SH_FLD_CC_ID_1 = 3234; // 1 +const static uint64_t SH_FLD_CC_ID_1_LEN = 3235; // 1 +const static uint64_t SH_FLD_CC_ID_2 = 3236; // 1 +const static uint64_t SH_FLD_CC_ID_2_LEN = 3237; // 1 +const static uint64_t SH_FLD_CC_ID_3 = 3238; // 1 +const static uint64_t SH_FLD_CC_ID_3_LEN = 3239; // 1 +const static uint64_t SH_FLD_CC_MASK = 3240; // 8 +const static uint64_t SH_FLD_CC_READ_ENABLE_0 = 3241; // 1 +const static uint64_t SH_FLD_CC_READ_ENABLE_1 = 3242; // 1 +const static uint64_t SH_FLD_CC_READ_ENABLE_2 = 3243; // 1 +const static uint64_t SH_FLD_CC_READ_ENABLE_3 = 3244; // 1 +const static uint64_t SH_FLD_CC_WRITE_ENABLE_0 = 3245; // 1 +const static uint64_t SH_FLD_CC_WRITE_ENABLE_1 = 3246; // 1 +const static uint64_t SH_FLD_CC_WRITE_ENABLE_2 = 3247; // 1 +const static uint64_t SH_FLD_CC_WRITE_ENABLE_3 = 3248; // 1 +const static uint64_t SH_FLD_CD_ALL_DONE_GCRMSG = 3249; // 4 +const static uint64_t SH_FLD_CD_PREV_DONE_GCRMSG = 3250; // 4 +const static uint64_t SH_FLD_CE = 3251; // 43 +const static uint64_t SH_FLD_CE1_0_OUT = 3252; // 4 +const static uint64_t SH_FLD_CE1_1_OUT = 3253; // 4 +const static uint64_t SH_FLD_CE1_2_OUT = 3254; // 4 +const static uint64_t SH_FLD_CE1_3_OUT = 3255; // 4 +const static uint64_t SH_FLD_CE1_4_OUT = 3256; // 4 +const static uint64_t SH_FLD_CE1_5_OUT = 3257; // 4 +const static uint64_t SH_FLD_CE1_6_OUT = 3258; // 4 +const static uint64_t SH_FLD_CE1_7_OUT = 3259; // 4 +const static uint64_t SH_FLD_CE2_0_OUT = 3260; // 4 +const static uint64_t SH_FLD_CE2_1_OUT = 3261; // 4 +const static uint64_t SH_FLD_CE2_2_OUT = 3262; // 4 +const static uint64_t SH_FLD_CE2_3_OUT = 3263; // 4 +const static uint64_t SH_FLD_CE2_4_OUT = 3264; // 4 +const static uint64_t SH_FLD_CE2_5_OUT = 3265; // 4 +const static uint64_t SH_FLD_CE2_6_OUT = 3266; // 4 +const static uint64_t SH_FLD_CE2_7_OUT = 3267; // 4 +const static uint64_t SH_FLD_CEC_PSI_INTERRUPT = 3268; // 1 +const static uint64_t SH_FLD_CENTAURP_ENABLE_BYPASS_CMD = 3269; // 4 +const static uint64_t SH_FLD_CENTAURP_ENABLE_CENTAURP_CMD = 3270; // 4 +const static uint64_t SH_FLD_CENTAURP_ENABLE_CP_ME = 3271; // 4 +const static uint64_t SH_FLD_CENTAURP_ENABLE_CR_SIDEBAND = 3272; // 4 +const static uint64_t SH_FLD_CENTAURP_ENABLE_DTAG_CR = 3273; // 4 +const static uint64_t SH_FLD_CENTAURP_ENABLE_DYNAMIC_WRBUF_ALLOC = 3274; // 4 +const static uint64_t SH_FLD_CENTAURP_ENABLE_ECRESP = 3275; // 4 +const static uint64_t SH_FLD_CENTAURP_ENABLE_NEW_AMO = 3276; // 4 +const static uint64_t SH_FLD_CENTAURP_INBAND_IS_63 = 3277; // 4 +const static uint64_t SH_FLD_CENTAUR_MODE = 3278; // 4 +const static uint64_t SH_FLD_CENTAUR_SYNC_COMMAND_DETECTED = 3279; // 4 +const static uint64_t SH_FLD_CERR_AXFLOW_ERR = 3280; // 1 +const static uint64_t SH_FLD_CERR_AXFLOW_ERR_LEN = 3281; // 1 +const static uint64_t SH_FLD_CERR_AXPUSH_WRERR = 3282; // 1 +const static uint64_t SH_FLD_CERR_AXPUSH_WRERR_LEN = 3283; // 1 +const static uint64_t SH_FLD_CERR_BAR_PARITY_ERR = 3284; // 1 +const static uint64_t SH_FLD_CERR_BCDE_INTERNAL_ERR = 3285; // 1 +const static uint64_t SH_FLD_CERR_BCDE_INTERNAL_ERR_LEN = 3286; // 1 +const static uint64_t SH_FLD_CERR_BCDE_SETUP_ERR = 3287; // 1 +const static uint64_t SH_FLD_CERR_BCDE_SETUP_ERR_LEN = 3288; // 1 +const static uint64_t SH_FLD_CERR_BCUE_INTERNAL_ERR = 3289; // 1 +const static uint64_t SH_FLD_CERR_BCUE_INTERNAL_ERR_LEN = 3290; // 1 +const static uint64_t SH_FLD_CERR_BCUE_OCI_DATAERR = 3291; // 1 +const static uint64_t SH_FLD_CERR_BCUE_OCI_DATAERR_LEN = 3292; // 1 +const static uint64_t SH_FLD_CERR_BCUE_SETUP_ERR = 3293; // 1 +const static uint64_t SH_FLD_CERR_BCUE_SETUP_ERR_LEN = 3294; // 1 +const static uint64_t SH_FLD_CERR_PBDOUT_PARITY_ERR = 3295; // 1 +const static uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_RD = 3296; // 1 +const static uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_RD_LEN = 3297; // 1 +const static uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_WR = 3298; // 1 +const static uint64_t SH_FLD_CERR_PB_ACKDEAD_FW_WR_LEN = 3299; // 1 +const static uint64_t SH_FLD_CERR_PB_BADCRESP = 3300; // 1 +const static uint64_t SH_FLD_CERR_PB_BADCRESP_LEN = 3301; // 1 +const static uint64_t SH_FLD_CERR_PB_OPERTO = 3302; // 1 +const static uint64_t SH_FLD_CERR_PB_OPERTO_LEN = 3303; // 1 +const static uint64_t SH_FLD_CERR_PB_PARITY_ERR = 3304; // 1 +const static uint64_t SH_FLD_CERR_PB_PARITY_ERR_LEN = 3305; // 1 +const static uint64_t SH_FLD_CERR_PB_RDADRERR_FW = 3306; // 1 +const static uint64_t SH_FLD_CERR_PB_RDADRERR_FW_LEN = 3307; // 1 +const static uint64_t SH_FLD_CERR_PB_RDDATATO_FW = 3308; // 1 +const static uint64_t SH_FLD_CERR_PB_RDDATATO_FW_LEN = 3309; // 1 +const static uint64_t SH_FLD_CERR_PB_UNEXPCRESP = 3310; // 1 +const static uint64_t SH_FLD_CERR_PB_UNEXPCRESP_LEN = 3311; // 1 +const static uint64_t SH_FLD_CERR_PB_UNEXPDATA = 3312; // 1 +const static uint64_t SH_FLD_CERR_PB_UNEXPDATA_LEN = 3313; // 1 +const static uint64_t SH_FLD_CERR_PB_WRADRERR_FW = 3314; // 1 +const static uint64_t SH_FLD_CERR_PB_WRADRERR_FW_LEN = 3315; // 1 +const static uint64_t SH_FLD_CERR_SCOMTB_ERR = 3316; // 1 +const static uint64_t SH_FLD_CERR_SLV_INTERNAL_ERR = 3317; // 1 +const static uint64_t SH_FLD_CERR_SLV_INTERNAL_ERR_LEN = 3318; // 1 +const static uint64_t SH_FLD_CERR_SPARE = 3319; // 1 +const static uint64_t SH_FLD_CERR_SPARE_LEN = 3320; // 1 +const static uint64_t SH_FLD_CFG = 3321; // 43 +const static uint64_t SH_FLD_CFG_2N_ADDR = 3322; // 8 +const static uint64_t SH_FLD_CFG_ACM_EN = 3323; // 1 +const static uint64_t SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY = 3324; // 8 +const static uint64_t SH_FLD_CFG_ACT_TO_DIFF_RANK_DLY_LEN = 3325; // 8 +const static uint64_t SH_FLD_CFG_ADDRESS_COUNTER = 3326; // 2 +const static uint64_t SH_FLD_CFG_ADDRESS_COUNTER_LEN = 3327; // 2 +const static uint64_t SH_FLD_CFG_ADDR_COUNTER_MODE = 3328; // 2 +const static uint64_t SH_FLD_CFG_ADDR_COUNTER_MODE_LEN = 3329; // 2 +const static uint64_t SH_FLD_CFG_ALL_PERIODIC_LENGTH = 3330; // 8 +const static uint64_t SH_FLD_CFG_ALL_PERIODIC_LENGTH_LEN = 3331; // 8 +const static uint64_t SH_FLD_CFG_ALL_PERIODIC_TB = 3332; // 8 +const static uint64_t SH_FLD_CFG_ALL_PERIODIC_TB_LEN = 3333; // 8 +const static uint64_t SH_FLD_CFG_ALWAYS_WAIT_ACT_TIME = 3334; // 8 +const static uint64_t SH_FLD_CFG_AMAP_BANK0 = 3335; // 2 +const static uint64_t SH_FLD_CFG_AMAP_BANK0_LEN = 3336; // 2 +const static uint64_t SH_FLD_CFG_AMAP_BANK1 = 3337; // 2 +const static uint64_t SH_FLD_CFG_AMAP_BANK1_LEN = 3338; // 2 +const static uint64_t SH_FLD_CFG_AMAP_BANK2 = 3339; // 2 +const static uint64_t SH_FLD_CFG_AMAP_BANK2_LEN = 3340; // 2 +const static uint64_t SH_FLD_CFG_AMAP_BANK_GROUP0 = 3341; // 2 +const static uint64_t SH_FLD_CFG_AMAP_BANK_GROUP0_LEN = 3342; // 2 +const static uint64_t SH_FLD_CFG_AMAP_BANK_GROUP1 = 3343; // 2 +const static uint64_t SH_FLD_CFG_AMAP_BANK_GROUP1_LEN = 3344; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL2 = 3345; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL2_LEN = 3346; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL3 = 3347; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL3_LEN = 3348; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL4 = 3349; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL4_LEN = 3350; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL5 = 3351; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL5_LEN = 3352; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL6 = 3353; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL6_LEN = 3354; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL7 = 3355; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL7_LEN = 3356; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL8 = 3357; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL8_LEN = 3358; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL9 = 3359; // 2 +const static uint64_t SH_FLD_CFG_AMAP_COL9_LEN = 3360; // 2 +const static uint64_t SH_FLD_CFG_AMAP_DIMM_SELECT = 3361; // 2 +const static uint64_t SH_FLD_CFG_AMAP_DIMM_SELECT_LEN = 3362; // 2 +const static uint64_t SH_FLD_CFG_AMAP_MRANK0 = 3363; // 2 +const static uint64_t SH_FLD_CFG_AMAP_MRANK0_LEN = 3364; // 2 +const static uint64_t SH_FLD_CFG_AMAP_MRANK1 = 3365; // 2 +const static uint64_t SH_FLD_CFG_AMAP_MRANK1_LEN = 3366; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW0 = 3367; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW0_LEN = 3368; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW1 = 3369; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW10 = 3370; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW10_LEN = 3371; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW11 = 3372; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW11_LEN = 3373; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW12 = 3374; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW12_LEN = 3375; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW13 = 3376; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW13_LEN = 3377; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW14 = 3378; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW14_LEN = 3379; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW15 = 3380; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW15_LEN = 3381; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW16 = 3382; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW16_LEN = 3383; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW17 = 3384; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW17_LEN = 3385; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW1_LEN = 3386; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW2 = 3387; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW2_LEN = 3388; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW3 = 3389; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW3_LEN = 3390; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW4 = 3391; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW4_LEN = 3392; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW5 = 3393; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW5_LEN = 3394; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW6 = 3395; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW6_LEN = 3396; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW7 = 3397; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW7_LEN = 3398; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW8 = 3399; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW8_LEN = 3400; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW9 = 3401; // 2 +const static uint64_t SH_FLD_CFG_AMAP_ROW9_LEN = 3402; // 2 +const static uint64_t SH_FLD_CFG_AMAP_SRANK0 = 3403; // 2 +const static uint64_t SH_FLD_CFG_AMAP_SRANK0_LEN = 3404; // 2 +const static uint64_t SH_FLD_CFG_AMAP_SRANK1 = 3405; // 2 +const static uint64_t SH_FLD_CFG_AMAP_SRANK1_LEN = 3406; // 2 +const static uint64_t SH_FLD_CFG_AMAP_SRANK2 = 3407; // 2 +const static uint64_t SH_FLD_CFG_AMAP_SRANK2_LEN = 3408; // 2 +const static uint64_t SH_FLD_CFG_BANK_BUSY_FSM_DIS = 3409; // 8 +const static uint64_t SH_FLD_CFG_BANK_BUSY_FSM_DIS_LEN = 3410; // 8 +const static uint64_t SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS = 3411; // 8 +const static uint64_t SH_FLD_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN = 3412; // 8 +const static uint64_t SH_FLD_CFG_BC4_EN = 3413; // 2 +const static uint64_t SH_FLD_CFG_BLOCK_EN = 3414; // 1 +const static uint64_t SH_FLD_CFG_BLOCK_GROUP_EN = 3415; // 1 +const static uint64_t SH_FLD_CFG_BLOCK_RCMD_FILTER_EN = 3416; // 1 +const static uint64_t SH_FLD_CFG_BLOCK_RESET_DELAY = 3417; // 1 +const static uint64_t SH_FLD_CFG_BLOCK_RESET_DELAY_LEN = 3418; // 1 +const static uint64_t SH_FLD_CFG_BLOCK_VPD_EN = 3419; // 1 +const static uint64_t SH_FLD_CFG_BW_SNAPSHOT = 3420; // 8 +const static uint64_t SH_FLD_CFG_BW_SNAPSHOT_LEN = 3421; // 8 +const static uint64_t SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL = 3422; // 12 +const static uint64_t SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL_LEN = 3423; // 12 +const static uint64_t SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL = 3424; // 12 +const static uint64_t SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL_LEN = 3425; // 12 +const static uint64_t SH_FLD_CFG_CAC_ERR_REPAIR_EN = 3426; // 12 +const static uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR0_ENABLE = 3427; // 8 +const static uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR1_ENABLE = 3428; // 8 +const static uint64_t SH_FLD_CFG_CAL_INTERVAL_TMR2_ENABLE = 3429; // 8 +const static uint64_t SH_FLD_CFG_CAL_RANK_ENABLE = 3430; // 8 +const static uint64_t SH_FLD_CFG_CAL_RANK_ENABLE_LEN = 3431; // 8 +const static uint64_t SH_FLD_CFG_CAL_SINGLE_PORT_MODE = 3432; // 8 +const static uint64_t SH_FLD_CFG_CAL_SINGLE_PORT_MODE_LEN = 3433; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_DDR_DONE = 3434; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_ENABLE = 3435; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_TYPE = 3436; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL1_TYPE_LEN = 3437; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_DDR_DONE = 3438; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_ENABLE = 3439; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_TYPE = 3440; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL2_TYPE_LEN = 3441; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_DDR_DONE = 3442; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_ENABLE = 3443; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_TYPE = 3444; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_CAL3_TYPE_LEN = 3445; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_ENABLE = 3446; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR = 3447; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_LEN = 3448; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB = 3449; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_DDR_RESET_TMR_TB_LEN = 3450; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_SINGLE_RANK = 3451; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_Z_SYNC = 3452; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR0_Z_SYNC_LEN = 3453; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_DDR_DONE = 3454; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_ENABLE = 3455; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_TYPE = 3456; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL1_TYPE_LEN = 3457; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_DDR_DONE = 3458; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_ENABLE = 3459; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_TYPE = 3460; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL2_TYPE_LEN = 3461; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_DDR_DONE = 3462; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_ENABLE = 3463; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_TYPE = 3464; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_CAL3_TYPE_LEN = 3465; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_SINGLE_RANK = 3466; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_Z_SYNC = 3467; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR1_Z_SYNC_LEN = 3468; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_DDR_DONE = 3469; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_ENABLE = 3470; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_TYPE = 3471; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL1_TYPE_LEN = 3472; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_DDR_DONE = 3473; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_ENABLE = 3474; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_TYPE = 3475; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL2_TYPE_LEN = 3476; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_DDR_DONE = 3477; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_ENABLE = 3478; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_TYPE = 3479; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_CAL3_TYPE_LEN = 3480; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_SINGLE_RANK = 3481; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_WAT_EVENT_ENABLE = 3482; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_Z_SYNC = 3483; // 8 +const static uint64_t SH_FLD_CFG_CAL_TMR2_Z_SYNC_LEN = 3484; // 8 +const static uint64_t SH_FLD_CFG_CCS_ADDR_MUX_SEL = 3485; // 8 +const static uint64_t SH_FLD_CFG_CCS_INST_RESET_ENABLE = 3486; // 8 +const static uint64_t SH_FLD_CFG_CCS_RETRY_DIS = 3487; // 2 +const static uint64_t SH_FLD_CFG_CHIPID = 3488; // 1 +const static uint64_t SH_FLD_CFG_CHIPID_LEN = 3489; // 1 +const static uint64_t SH_FLD_CFG_CHIPID_OVERRIDE = 3490; // 1 +const static uint64_t SH_FLD_CFG_CKE_PUP_STATE = 3491; // 8 +const static uint64_t SH_FLD_CFG_CKE_PUP_STATE_LEN = 3492; // 8 +const static uint64_t SH_FLD_CFG_CLOCK_MONITOR_EN = 3493; // 2 +const static uint64_t SH_FLD_CFG_CMD0_BANK = 3494; // 8 +const static uint64_t SH_FLD_CFG_CMD0_BANK_LEN = 3495; // 8 +const static uint64_t SH_FLD_CFG_CMD0_BANK_MATCH_EN = 3496; // 8 +const static uint64_t SH_FLD_CFG_CMD0_BG = 3497; // 8 +const static uint64_t SH_FLD_CFG_CMD0_BG_LEN = 3498; // 8 +const static uint64_t SH_FLD_CFG_CMD0_BG_MATCH_EN = 3499; // 8 +const static uint64_t SH_FLD_CFG_CMD0_MRANK = 3500; // 8 +const static uint64_t SH_FLD_CFG_CMD0_MRANK_LEN = 3501; // 8 +const static uint64_t SH_FLD_CFG_CMD0_MRANK_MATCH_EN = 3502; // 8 +const static uint64_t SH_FLD_CFG_CMD0_SRANK = 3503; // 8 +const static uint64_t SH_FLD_CFG_CMD0_SRANK_LEN = 3504; // 8 +const static uint64_t SH_FLD_CFG_CMD0_SRANK_MATCH_EN = 3505; // 8 +const static uint64_t SH_FLD_CFG_CMD0_TYPE = 3506; // 8 +const static uint64_t SH_FLD_CFG_CMD0_TYPE_LEN = 3507; // 8 +const static uint64_t SH_FLD_CFG_CMD1_BANK = 3508; // 8 +const static uint64_t SH_FLD_CFG_CMD1_BANK_LEN = 3509; // 8 +const static uint64_t SH_FLD_CFG_CMD1_BANK_MATCH_EN = 3510; // 8 +const static uint64_t SH_FLD_CFG_CMD1_BG = 3511; // 8 +const static uint64_t SH_FLD_CFG_CMD1_BG_LEN = 3512; // 8 +const static uint64_t SH_FLD_CFG_CMD1_BG_MATCH_EN = 3513; // 8 +const static uint64_t SH_FLD_CFG_CMD1_MRANK = 3514; // 8 +const static uint64_t SH_FLD_CFG_CMD1_MRANK_LEN = 3515; // 8 +const static uint64_t SH_FLD_CFG_CMD1_MRANK_MATCH_EN = 3516; // 8 +const static uint64_t SH_FLD_CFG_CMD1_SRANK = 3517; // 8 +const static uint64_t SH_FLD_CFG_CMD1_SRANK_LEN = 3518; // 8 +const static uint64_t SH_FLD_CFG_CMD1_SRANK_MATCH_EN = 3519; // 8 +const static uint64_t SH_FLD_CFG_CMD1_TYPE = 3520; // 8 +const static uint64_t SH_FLD_CFG_CMD1_TYPE_LEN = 3521; // 8 +const static uint64_t SH_FLD_CFG_CMD2_BANK = 3522; // 8 +const static uint64_t SH_FLD_CFG_CMD2_BANK_LEN = 3523; // 8 +const static uint64_t SH_FLD_CFG_CMD2_BANK_MATCH_EN = 3524; // 8 +const static uint64_t SH_FLD_CFG_CMD2_BG = 3525; // 8 +const static uint64_t SH_FLD_CFG_CMD2_BG_LEN = 3526; // 8 +const static uint64_t SH_FLD_CFG_CMD2_BG_MATCH_EN = 3527; // 8 +const static uint64_t SH_FLD_CFG_CMD2_MRANK = 3528; // 8 +const static uint64_t SH_FLD_CFG_CMD2_MRANK_LEN = 3529; // 8 +const static uint64_t SH_FLD_CFG_CMD2_MRANK_MATCH_EN = 3530; // 8 +const static uint64_t SH_FLD_CFG_CMD2_SRANK = 3531; // 8 +const static uint64_t SH_FLD_CFG_CMD2_SRANK_LEN = 3532; // 8 +const static uint64_t SH_FLD_CFG_CMD2_SRANK_MATCH_EN = 3533; // 8 +const static uint64_t SH_FLD_CFG_CMD2_TYPE = 3534; // 8 +const static uint64_t SH_FLD_CFG_CMD2_TYPE_LEN = 3535; // 8 +const static uint64_t SH_FLD_CFG_CMD_TIMEOUT_MODE = 3536; // 2 +const static uint64_t SH_FLD_CFG_CMD_TIMEOUT_MODE_LEN = 3537; // 2 +const static uint64_t SH_FLD_CFG_CORE_PUSH_EN = 3538; // 1 +const static uint64_t SH_FLD_CFG_CO_SOFT_PURGE_ALL_LINES_EN = 3539; // 12 +const static uint64_t SH_FLD_CFG_CO_SOFT_PURGE_ME_SX_EN = 3540; // 12 +const static uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP = 3541; // 2 +const static uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP_LEN = 3542; // 2 +const static uint64_t SH_FLD_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS = 3543; // 2 +const static uint64_t SH_FLD_CFG_CURRENT_PORT_DIMM_TRAP = 3544; // 2 +const static uint64_t SH_FLD_CFG_CURRENT_PORT_DIMM_TRAP_LEN = 3545; // 2 +const static uint64_t SH_FLD_CFG_DATA_ROT = 3546; // 2 +const static uint64_t SH_FLD_CFG_DATA_ROT_LEN = 3547; // 2 +const static uint64_t SH_FLD_CFG_DATA_ROT_SEED = 3548; // 4 +const static uint64_t SH_FLD_CFG_DATA_ROT_SEED_LEN = 3549; // 4 +const static uint64_t SH_FLD_CFG_DATA_SEED_MODE = 3550; // 2 +const static uint64_t SH_FLD_CFG_DATA_SEED_MODE_LEN = 3551; // 2 +const static uint64_t SH_FLD_CFG_DBG_ENABLE = 3552; // 2 +const static uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT01 = 3553; // 2 +const static uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT01_LEN = 3554; // 2 +const static uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT23 = 3555; // 2 +const static uint64_t SH_FLD_CFG_DBG_PICK_ASYNC_PORT23_LEN = 3556; // 2 +const static uint64_t SH_FLD_CFG_DBG_PICK_MCBIST01 = 3557; // 2 +const static uint64_t SH_FLD_CFG_DBG_PICK_MCBIST01_LEN = 3558; // 2 +const static uint64_t SH_FLD_CFG_DBG_PICK_MCBIST23 = 3559; // 2 +const static uint64_t SH_FLD_CFG_DBG_PICK_MCBIST23_LEN = 3560; // 2 +const static uint64_t SH_FLD_CFG_DBG_SRQ_ENABLE = 3561; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL0 = 3562; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL0_LEN = 3563; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL1 = 3564; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL1_LEN = 3565; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL2 = 3566; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL2_LEN = 3567; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL3 = 3568; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL3_LEN = 3569; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL4 = 3570; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL4_LEN = 3571; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL5 = 3572; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL5_LEN = 3573; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL6 = 3574; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL6_LEN = 3575; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL7 = 3576; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL7_LEN = 3577; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL_OTHER_SRQ = 3578; // 8 +const static uint64_t SH_FLD_CFG_DBG_SRQ_SEL_OTHER_SRQ_LEN = 3579; // 8 +const static uint64_t SH_FLD_CFG_DCACHE_CAPP_LPC_EN = 3580; // 12 +const static uint64_t SH_FLD_CFG_DCBZ_TRASHMODE_EN = 3581; // 12 +const static uint64_t SH_FLD_CFG_DDR4E_BLIND_STEER_MODE = 3582; // 2 +const static uint64_t SH_FLD_CFG_DDR4_PARITY_ON_CID_DIS = 3583; // 8 +const static uint64_t SH_FLD_CFG_DDR_DPHY_NCLK = 3584; // 8 +const static uint64_t SH_FLD_CFG_DDR_DPHY_NCLK_LEN = 3585; // 8 +const static uint64_t SH_FLD_CFG_DDR_DPHY_PCLK = 3586; // 8 +const static uint64_t SH_FLD_CFG_DDR_DPHY_PCLK_LEN = 3587; // 8 +const static uint64_t SH_FLD_CFG_DDR_RESETN = 3588; // 8 +const static uint64_t SH_FLD_CFG_DGEN_FIXED_MODE = 3589; // 2 +const static uint64_t SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK = 3590; // 43 +const static uint64_t SH_FLD_CFG_DISABLE_FAST_PATH = 3591; // 8 +const static uint64_t SH_FLD_CFG_DISABLE_FORCE_TO_ZERO = 3592; // 43 +const static uint64_t SH_FLD_CFG_DISABLE_HEARTBEAT = 3593; // 43 +const static uint64_t SH_FLD_CFG_DISABLE_MALF_PULSE_GEN = 3594; // 43 +const static uint64_t SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK = 3595; // 43 +const static uint64_t SH_FLD_CFG_DISABLE_RCD_RECOVERY = 3596; // 8 +const static uint64_t SH_FLD_CFG_DISABLE_RD_PG_MODE = 3597; // 8 +const static uint64_t SH_FLD_CFG_DISABLE_REFRESH_DURING_NOISE_WDW = 3598; // 8 +const static uint64_t SH_FLD_CFG_DISABLE_WR_PG_MODE = 3599; // 8 +const static uint64_t SH_FLD_CFG_DIS_CLK_IN_STR = 3600; // 8 +const static uint64_t SH_FLD_CFG_DIS_SMDR = 3601; // 8 +const static uint64_t SH_FLD_CFG_DONE_IACK_PRIO_HYP = 3602; // 1 +const static uint64_t SH_FLD_CFG_DONE_IACK_PRIO_HYP_LEN = 3603; // 1 +const static uint64_t SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL = 3604; // 1 +const static uint64_t SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL_LEN = 3605; // 1 +const static uint64_t SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL = 3606; // 1 +const static uint64_t SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL_LEN = 3607; // 1 +const static uint64_t SH_FLD_CFG_DONE_PRIO_IACK = 3608; // 1 +const static uint64_t SH_FLD_CFG_DONE_PRIO_IACK_LEN = 3609; // 1 +const static uint64_t SH_FLD_CFG_DONE_PULL_PRIO_HYP = 3610; // 1 +const static uint64_t SH_FLD_CFG_DONE_PULL_PRIO_HYP_LEN = 3611; // 1 +const static uint64_t SH_FLD_CFG_DQS_ALIGNMENT_LENGTH = 3612; // 8 +const static uint64_t SH_FLD_CFG_DQS_ALIGNMENT_LENGTH_LEN = 3613; // 8 +const static uint64_t SH_FLD_CFG_DQS_ALIGNMENT_TB = 3614; // 8 +const static uint64_t SH_FLD_CFG_DQS_ALIGNMENT_TB_LEN = 3615; // 8 +const static uint64_t SH_FLD_CFG_ECCCK_CE_UE_SUE_ERR_DET_DIS = 3616; // 12 +const static uint64_t SH_FLD_CFG_ECCCK_UE_SUE_DET_DIS = 3617; // 12 +const static uint64_t SH_FLD_CFG_EMER_MIN_MAX_DOMAIN = 3618; // 8 +const static uint64_t SH_FLD_CFG_EMER_MIN_MAX_DOMAIN_LEN = 3619; // 8 +const static uint64_t SH_FLD_CFG_EN = 3620; // 1 +const static uint64_t SH_FLD_CFG_ENABLE_HOST_ATTN = 3621; // 10 +const static uint64_t SH_FLD_CFG_ENABLE_SPEC_ATTN = 3622; // 10 +const static uint64_t SH_FLD_CFG_END_ADDR_0 = 3623; // 2 +const static uint64_t SH_FLD_CFG_END_ADDR_0_LEN = 3624; // 2 +const static uint64_t SH_FLD_CFG_END_ADDR_1 = 3625; // 2 +const static uint64_t SH_FLD_CFG_END_ADDR_1_LEN = 3626; // 2 +const static uint64_t SH_FLD_CFG_END_ADDR_2 = 3627; // 2 +const static uint64_t SH_FLD_CFG_END_ADDR_2_LEN = 3628; // 2 +const static uint64_t SH_FLD_CFG_END_ADDR_3 = 3629; // 2 +const static uint64_t SH_FLD_CFG_END_ADDR_3_LEN = 3630; // 2 +const static uint64_t SH_FLD_CFG_ENTER_STR_TIME = 3631; // 8 +const static uint64_t SH_FLD_CFG_ENTER_STR_TIME_LEN = 3632; // 8 +const static uint64_t SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR = 3633; // 8 +const static uint64_t SH_FLD_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN = 3634; // 8 +const static uint64_t SH_FLD_CFG_EN_RANDCMD_GAP = 3635; // 2 +const static uint64_t SH_FLD_CFG_EVENT0_SELECT = 3636; // 8 +const static uint64_t SH_FLD_CFG_EVENT0_SELECT_LEN = 3637; // 8 +const static uint64_t SH_FLD_CFG_EVENT1_SELECT = 3638; // 8 +const static uint64_t SH_FLD_CFG_EVENT1_SELECT_LEN = 3639; // 8 +const static uint64_t SH_FLD_CFG_EVENT2_SELECT = 3640; // 8 +const static uint64_t SH_FLD_CFG_EVENT2_SELECT_LEN = 3641; // 8 +const static uint64_t SH_FLD_CFG_EVENT3_SELECT = 3642; // 8 +const static uint64_t SH_FLD_CFG_EVENT3_SELECT_LEN = 3643; // 8 +const static uint64_t SH_FLD_CFG_EXTERNAL_ZQ_LENGTH = 3644; // 8 +const static uint64_t SH_FLD_CFG_EXTERNAL_ZQ_LENGTH_LEN = 3645; // 8 +const static uint64_t SH_FLD_CFG_EXTERNAL_ZQ_TB = 3646; // 8 +const static uint64_t SH_FLD_CFG_EXTERNAL_ZQ_TB_LEN = 3647; // 8 +const static uint64_t SH_FLD_CFG_FARB_CLOSE_ALL_PAGES = 3648; // 8 +const static uint64_t SH_FLD_CFG_FIXED_SEED = 3649; // 16 +const static uint64_t SH_FLD_CFG_FIXED_SEED1 = 3650; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED1_LEN = 3651; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED2 = 3652; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED2_LEN = 3653; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED3 = 3654; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED3_LEN = 3655; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED4 = 3656; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED4_LEN = 3657; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED5 = 3658; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED5_LEN = 3659; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED6 = 3660; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED6_LEN = 3661; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED7 = 3662; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED7_LEN = 3663; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED8 = 3664; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED8_LEN = 3665; // 2 +const static uint64_t SH_FLD_CFG_FIXED_SEED_LEN = 3666; // 16 +const static uint64_t SH_FLD_CFG_FIXED_WIDTH = 3667; // 2 +const static uint64_t SH_FLD_CFG_FIXED_WIDTH_LEN = 3668; // 2 +const static uint64_t SH_FLD_CFG_FORCE_MCLK_LOW_N = 3669; // 8 +const static uint64_t SH_FLD_CFG_FORCE_SPARE_PUP = 3670; // 8 +const static uint64_t SH_FLD_CFG_FREEZE_ON_PARITY_ERROR_DIS = 3671; // 8 +const static uint64_t SH_FLD_CFG_FUSE_CORE_EN = 3672; // 1 +const static uint64_t SH_FLD_CFG_GP_BIT_3_ENABLE = 3673; // 8 +const static uint64_t SH_FLD_CFG_HARD_CHIPID_IN_BLOCK_EN = 3674; // 1 +const static uint64_t SH_FLD_CFG_HASH_L3_ADDR_EN = 3675; // 12 +const static uint64_t SH_FLD_CFG_HW_TRIG_LINEDEL_LDDISP_CE_EN = 3676; // 12 +const static uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_ADDR5 = 3677; // 8 +const static uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_CONSTANT = 3678; // 8 +const static uint64_t SH_FLD_CFG_INJECT_PARITY_ERR_WEN = 3679; // 8 +const static uint64_t SH_FLD_CFG_INJ_CANCEL_ACK_ERR = 3680; // 8 +const static uint64_t SH_FLD_CFG_INTERNAL_ZQ_LENGTH = 3681; // 8 +const static uint64_t SH_FLD_CFG_INTERNAL_ZQ_LENGTH_LEN = 3682; // 8 +const static uint64_t SH_FLD_CFG_INTERNAL_ZQ_TB = 3683; // 8 +const static uint64_t SH_FLD_CFG_INTERNAL_ZQ_TB_LEN = 3684; // 8 +const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR0 = 3685; // 8 +const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR0_LEN = 3686; // 8 +const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR1 = 3687; // 8 +const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR1_LEN = 3688; // 8 +const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR2 = 3689; // 8 +const static uint64_t SH_FLD_CFG_INTERVAL_COUNTER_TMR2_LEN = 3690; // 8 +const static uint64_t SH_FLD_CFG_INVERT_DATA = 3691; // 2 +const static uint64_t SH_FLD_CFG_L3_DIS = 3692; // 12 +const static uint64_t SH_FLD_CFG_LDST_PRIO_RSP_LD = 3693; // 1 +const static uint64_t SH_FLD_CFG_LDST_PRIO_RSP_LD_LEN = 3694; // 1 +const static uint64_t SH_FLD_CFG_LDST_PRIO_SET_LD = 3695; // 1 +const static uint64_t SH_FLD_CFG_LDST_PRIO_SET_LD_LEN = 3696; // 1 +const static uint64_t SH_FLD_CFG_LFSR_MASK_A0 = 3697; // 2 +const static uint64_t SH_FLD_CFG_LFSR_MASK_A0_LEN = 3698; // 2 +const static uint64_t SH_FLD_CFG_LINEDEL_ON_CAC_UE_EN = 3699; // 12 +const static uint64_t SH_FLD_CFG_LOGIC_SIGNALED_ERROR = 3700; // 6 +const static uint64_t SH_FLD_CFG_LOG_COUNTS_IN_TRACE = 3701; // 2 +const static uint64_t SH_FLD_CFG_LP_SUB_CNT = 3702; // 8 +const static uint64_t SH_FLD_CFG_LP_SUB_CNT_LEN = 3703; // 8 +const static uint64_t SH_FLD_CFG_LRU_DIRECT_MAP = 3704; // 12 +const static uint64_t SH_FLD_CFG_LTE_MC = 3705; // 2 +const static uint64_t SH_FLD_CFG_LTE_MC_LEN = 3706; // 2 +const static uint64_t SH_FLD_CFG_MAINT_ADDR_MODE_EN = 3707; // 2 +const static uint64_t SH_FLD_CFG_MAINT_BROADCAST_MODE_EN = 3708; // 2 +const static uint64_t SH_FLD_CFG_MAINT_DETECT_SRANK_BOUNDARIES = 3709; // 2 +const static uint64_t SH_FLD_CFG_MAINT_RCE_WITH_CE = 3710; // 2 +const static uint64_t SH_FLD_CFG_MAX = 3711; // 1 +const static uint64_t SH_FLD_CFG_MAX_LEN = 3712; // 1 +const static uint64_t SH_FLD_CFG_MAX_READS_IN_A_ROW = 3713; // 8 +const static uint64_t SH_FLD_CFG_MAX_READS_IN_A_ROW_LEN = 3714; // 8 +const static uint64_t SH_FLD_CFG_MAX_WRITES_IN_A_ROW = 3715; // 8 +const static uint64_t SH_FLD_CFG_MAX_WRITES_IN_A_ROW_LEN = 3716; // 8 +const static uint64_t SH_FLD_CFG_MCB_LEN64 = 3717; // 2 +const static uint64_t SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS = 3718; // 2 +const static uint64_t SH_FLD_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS_LEN = 3719; // 2 +const static uint64_t SH_FLD_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE = 3720; // 2 +const static uint64_t SH_FLD_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE = 3721; // 2 +const static uint64_t SH_FLD_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE = 3722; // 2 +const static uint64_t SH_FLD_CFG_MIN_CMD_GAP = 3723; // 2 +const static uint64_t SH_FLD_CFG_MIN_CMD_GAP_BLIND_STEER = 3724; // 2 +const static uint64_t SH_FLD_CFG_MIN_CMD_GAP_BLIND_STEER_LEN = 3725; // 2 +const static uint64_t SH_FLD_CFG_MIN_CMD_GAP_LEN = 3726; // 2 +const static uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT = 3727; // 8 +const static uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_ENABLE = 3728; // 8 +const static uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME = 3729; // 8 +const static uint64_t SH_FLD_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN = 3730; // 8 +const static uint64_t SH_FLD_CFG_MIN_GAP_TIMEBASE = 3731; // 2 +const static uint64_t SH_FLD_CFG_MIN_GAP_TIMEBASE_BLIND_STEER = 3732; // 2 +const static uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS = 3733; // 8 +const static uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS_ENABLE = 3734; // 8 +const static uint64_t SH_FLD_CFG_MIN_MAX_DOMAINS_LEN = 3735; // 8 +const static uint64_t SH_FLD_CFG_MISR_BLOCK = 3736; // 8 +const static uint64_t SH_FLD_CFG_MISR_BLOCK_LEN = 3737; // 8 +const static uint64_t SH_FLD_CFG_MISR_FEEDBACK_ENABLE = 3738; // 8 +const static uint64_t SH_FLD_CFG_MPR_READEYE_LENGTH = 3739; // 8 +const static uint64_t SH_FLD_CFG_MPR_READEYE_LENGTH_LEN = 3740; // 8 +const static uint64_t SH_FLD_CFG_MPR_READEYE_TB = 3741; // 8 +const static uint64_t SH_FLD_CFG_MPR_READEYE_TB_LEN = 3742; // 8 +const static uint64_t SH_FLD_CFG_MSGSND = 3743; // 1 +const static uint64_t SH_FLD_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE = 3744; // 2 +const static uint64_t SH_FLD_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE = 3745; // 2 +const static uint64_t SH_FLD_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE = 3746; // 2 +const static uint64_t SH_FLD_CFG_NM_CAS_WEIGHT = 3747; // 8 +const static uint64_t SH_FLD_CFG_NM_CAS_WEIGHT_LEN = 3748; // 8 +const static uint64_t SH_FLD_CFG_NM_CHANGE_AFTER_SYNC = 3749; // 8 +const static uint64_t SH_FLD_CFG_NM_M = 3750; // 8 +const static uint64_t SH_FLD_CFG_NM_M_LEN = 3751; // 8 +const static uint64_t SH_FLD_CFG_NM_N_PER_PORT = 3752; // 8 +const static uint64_t SH_FLD_CFG_NM_N_PER_PORT_LEN = 3753; // 8 +const static uint64_t SH_FLD_CFG_NM_N_PER_SLOT = 3754; // 8 +const static uint64_t SH_FLD_CFG_NM_N_PER_SLOT_LEN = 3755; // 8 +const static uint64_t SH_FLD_CFG_NM_RAS_WEIGHT = 3756; // 8 +const static uint64_t SH_FLD_CFG_NM_RAS_WEIGHT_LEN = 3757; // 8 +const static uint64_t SH_FLD_CFG_NOISE_WAIT_TIME = 3758; // 8 +const static uint64_t SH_FLD_CFG_NOISE_WAIT_TIME_LEN = 3759; // 8 +const static uint64_t SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL = 3760; // 8 +const static uint64_t SH_FLD_CFG_OCC_DEADMAN_TIMER_SEL_LEN = 3761; // 8 +const static uint64_t SH_FLD_CFG_OE_ALL_CKE_POWERED_DOWN = 3762; // 8 +const static uint64_t SH_FLD_CFG_OE_ALWAYS_ON = 3763; // 8 +const static uint64_t SH_FLD_CFG_OPT_RD_SIZE = 3764; // 8 +const static uint64_t SH_FLD_CFG_OPT_RD_SIZE_LEN = 3765; // 8 +const static uint64_t SH_FLD_CFG_PARITY_AFTER_CMD = 3766; // 10 +const static uint64_t SH_FLD_CFG_PARITY_DETECT_TIME = 3767; // 8 +const static uint64_t SH_FLD_CFG_PARITY_DETECT_TIME_LEN = 3768; // 8 +const static uint64_t SH_FLD_CFG_PARSE_PULL_RR_SEL = 3769; // 1 +const static uint64_t SH_FLD_CFG_PARSE_PULL_RR_SEL_LEN = 3770; // 1 +const static uint64_t SH_FLD_CFG_PARSE_PUSH_RR_SEL = 3771; // 1 +const static uint64_t SH_FLD_CFG_PARSE_PUSH_RR_SEL_LEN = 3772; // 1 +const static uint64_t SH_FLD_CFG_PARSE_QUERY_RR_SEL = 3773; // 1 +const static uint64_t SH_FLD_CFG_PAUSE_MCB_ERROR = 3774; // 2 +const static uint64_t SH_FLD_CFG_PAUSE_MCB_LOG_FULL = 3775; // 2 +const static uint64_t SH_FLD_CFG_PAUSE_ON_AUE = 3776; // 2 +const static uint64_t SH_FLD_CFG_PAUSE_ON_ERROR_MODE = 3777; // 2 +const static uint64_t SH_FLD_CFG_PAUSE_ON_ERROR_MODE_LEN = 3778; // 2 +const static uint64_t SH_FLD_CFG_PAUSE_ON_MCE = 3779; // 2 +const static uint64_t SH_FLD_CFG_PAUSE_ON_MPE = 3780; // 2 +const static uint64_t SH_FLD_CFG_PAUSE_ON_RCD = 3781; // 2 +const static uint64_t SH_FLD_CFG_PAUSE_ON_SCE = 3782; // 2 +const static uint64_t SH_FLD_CFG_PAUSE_ON_SUE = 3783; // 2 +const static uint64_t SH_FLD_CFG_PAUSE_ON_UE = 3784; // 2 +const static uint64_t SH_FLD_CFG_PCMD_PRIO_DONE = 3785; // 1 +const static uint64_t SH_FLD_CFG_PCMD_PRIO_DONE_LEN = 3786; // 1 +const static uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_RSP = 3787; // 1 +const static uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_RSP_LEN = 3788; // 1 +const static uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_SET = 3789; // 1 +const static uint64_t SH_FLD_CFG_PCMD_PRIO_LDST_SET_LEN = 3790; // 1 +const static uint64_t SH_FLD_CFG_PCMD_PRIO_RR = 3791; // 1 +const static uint64_t SH_FLD_CFG_PCMD_PRIO_RR_LEN = 3792; // 1 +const static uint64_t SH_FLD_CFG_PDN_PUP = 3793; // 8 +const static uint64_t SH_FLD_CFG_PDN_PUP_LEN = 3794; // 8 +const static uint64_t SH_FLD_CFG_PERFMON_INFO_SRC_ED_SEL = 3795; // 12 +const static uint64_t SH_FLD_CFG_PER_BANK_REFRESH = 3796; // 8 +const static uint64_t SH_FLD_CFG_PE_MATCH0 = 3797; // 1 +const static uint64_t SH_FLD_CFG_PE_MATCH0_LEN = 3798; // 1 +const static uint64_t SH_FLD_CFG_PE_MATCH1 = 3799; // 1 +const static uint64_t SH_FLD_CFG_PE_MATCH1_LEN = 3800; // 1 +const static uint64_t SH_FLD_CFG_PM_DISABLE = 3801; // 43 +const static uint64_t SH_FLD_CFG_PM_MUX_DISABLE = 3802; // 43 +const static uint64_t SH_FLD_CFG_PRECHARGE_WAIT_TIME = 3803; // 8 +const static uint64_t SH_FLD_CFG_PRECHARGE_WAIT_TIME_LEN = 3804; // 8 +const static uint64_t SH_FLD_CFG_PRESCALER_C0 = 3805; // 8 +const static uint64_t SH_FLD_CFG_PRESCALER_C0_LEN = 3806; // 8 +const static uint64_t SH_FLD_CFG_PRESCALER_C1 = 3807; // 8 +const static uint64_t SH_FLD_CFG_PRESCALER_C1_LEN = 3808; // 8 +const static uint64_t SH_FLD_CFG_PRESCALER_C2 = 3809; // 8 +const static uint64_t SH_FLD_CFG_PRESCALER_C2_LEN = 3810; // 8 +const static uint64_t SH_FLD_CFG_PRESCALER_C3 = 3811; // 8 +const static uint64_t SH_FLD_CFG_PRESCALER_C3_LEN = 3812; // 8 +const static uint64_t SH_FLD_CFG_PRIO_LSI = 3813; // 1 +const static uint64_t SH_FLD_CFG_PRIO_LSI_LEN = 3814; // 1 +const static uint64_t SH_FLD_CFG_PRIO_MMIO = 3815; // 1 +const static uint64_t SH_FLD_CFG_PRIO_MMIO_LEN = 3816; // 1 +const static uint64_t SH_FLD_CFG_PRIO_PULL = 3817; // 2 +const static uint64_t SH_FLD_CFG_PRIO_PULL_LEN = 3818; // 2 +const static uint64_t SH_FLD_CFG_PRIO_PUSH = 3819; // 1 +const static uint64_t SH_FLD_CFG_PRIO_PUSH_ARX = 3820; // 1 +const static uint64_t SH_FLD_CFG_PRIO_PUSH_ARX_LEN = 3821; // 1 +const static uint64_t SH_FLD_CFG_PRIO_PUSH_LCL = 3822; // 1 +const static uint64_t SH_FLD_CFG_PRIO_PUSH_LCL_LEN = 3823; // 1 +const static uint64_t SH_FLD_CFG_PRIO_PUSH_LEN = 3824; // 1 +const static uint64_t SH_FLD_CFG_PRIO_QUERY = 3825; // 1 +const static uint64_t SH_FLD_CFG_PRIO_QUERY_LEN = 3826; // 1 +const static uint64_t SH_FLD_CFG_PRIO_RR = 3827; // 3 +const static uint64_t SH_FLD_CFG_PRIO_RR_LEN = 3828; // 3 +const static uint64_t SH_FLD_CFG_PRIO_RSVD = 3829; // 1 +const static uint64_t SH_FLD_CFG_PRIO_RSVD_LEN = 3830; // 1 +const static uint64_t SH_FLD_CFG_PRIO_VRQ_REQ = 3831; // 1 +const static uint64_t SH_FLD_CFG_PRIO_VRQ_REQ_LEN = 3832; // 1 +const static uint64_t SH_FLD_CFG_PRIO_VRQ_RSP = 3833; // 1 +const static uint64_t SH_FLD_CFG_PRIO_VRQ_RSP_LEN = 3834; // 1 +const static uint64_t SH_FLD_CFG_PULL_LMIT = 3835; // 1 +const static uint64_t SH_FLD_CFG_PULL_LMIT_LEN = 3836; // 1 +const static uint64_t SH_FLD_CFG_PULL_PRIO_HYP = 3837; // 1 +const static uint64_t SH_FLD_CFG_PULL_PRIO_HYP_LEN = 3838; // 1 +const static uint64_t SH_FLD_CFG_PULL_RSVD = 3839; // 1 +const static uint64_t SH_FLD_CFG_PULL_RSVD_LEN = 3840; // 1 +const static uint64_t SH_FLD_CFG_PULSE_WIDTH = 3841; // 1 +const static uint64_t SH_FLD_CFG_PULSE_WIDTH_LEN = 3842; // 1 +const static uint64_t SH_FLD_CFG_PUMP = 3843; // 2 +const static uint64_t SH_FLD_CFG_PUMP_MODE = 3844; // 1 +const static uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE = 3845; // 8 +const static uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME = 3846; // 8 +const static uint64_t SH_FLD_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN = 3847; // 8 +const static uint64_t SH_FLD_CFG_PUP_ALL_WRITES_PENDING = 3848; // 8 +const static uint64_t SH_FLD_CFG_PUP_AVAIL = 3849; // 8 +const static uint64_t SH_FLD_CFG_PUP_AVAIL_LEN = 3850; // 8 +const static uint64_t SH_FLD_CFG_PUP_PDN = 3851; // 8 +const static uint64_t SH_FLD_CFG_PUP_PDN_LEN = 3852; // 8 +const static uint64_t SH_FLD_CFG_PUSH_ARX_LMIT = 3853; // 1 +const static uint64_t SH_FLD_CFG_PUSH_ARX_LMIT_LEN = 3854; // 1 +const static uint64_t SH_FLD_CFG_PUSH_ARX_RSVD = 3855; // 1 +const static uint64_t SH_FLD_CFG_PUSH_ARX_RSVD_LEN = 3856; // 1 +const static uint64_t SH_FLD_CFG_PUSH_LCL_LMIT = 3857; // 1 +const static uint64_t SH_FLD_CFG_PUSH_LCL_LMIT_LEN = 3858; // 1 +const static uint64_t SH_FLD_CFG_PUSH_LCL_RSVD = 3859; // 1 +const static uint64_t SH_FLD_CFG_PUSH_LCL_RSVD_LEN = 3860; // 1 +const static uint64_t SH_FLD_CFG_PUSH_PRIO_HYP = 3861; // 1 +const static uint64_t SH_FLD_CFG_PUSH_PRIO_HYP_LEN = 3862; // 1 +const static uint64_t SH_FLD_CFG_QUEUE_SIZE_PULL = 3863; // 1 +const static uint64_t SH_FLD_CFG_QUEUE_SIZE_PULL_LEN = 3864; // 1 +const static uint64_t SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL = 3865; // 1 +const static uint64_t SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL_LEN = 3866; // 1 +const static uint64_t SH_FLD_CFG_Q_BIT_TID_MASK = 3867; // 12 +const static uint64_t SH_FLD_CFG_Q_BIT_TID_MASK_LEN = 3868; // 12 +const static uint64_t SH_FLD_CFG_RANDCMD_WGT = 3869; // 2 +const static uint64_t SH_FLD_CFG_RANDCMD_WGT_LEN = 3870; // 2 +const static uint64_t SH_FLD_CFG_RANDGAP_WGT = 3871; // 2 +const static uint64_t SH_FLD_CFG_RANDGAP_WGT_LEN = 3872; // 2 +const static uint64_t SH_FLD_CFG_RANDOM_EN = 3873; // 12 +const static uint64_t SH_FLD_CFG_RANK0_RD_ODT = 3874; // 8 +const static uint64_t SH_FLD_CFG_RANK0_RD_ODT_LEN = 3875; // 8 +const static uint64_t SH_FLD_CFG_RANK0_WR_ODT = 3876; // 8 +const static uint64_t SH_FLD_CFG_RANK0_WR_ODT_LEN = 3877; // 8 +const static uint64_t SH_FLD_CFG_RANK1_RD_ODT = 3878; // 8 +const static uint64_t SH_FLD_CFG_RANK1_RD_ODT_LEN = 3879; // 8 +const static uint64_t SH_FLD_CFG_RANK1_WR_ODT = 3880; // 8 +const static uint64_t SH_FLD_CFG_RANK1_WR_ODT_LEN = 3881; // 8 +const static uint64_t SH_FLD_CFG_RANK2_RD_ODT = 3882; // 8 +const static uint64_t SH_FLD_CFG_RANK2_RD_ODT_LEN = 3883; // 8 +const static uint64_t SH_FLD_CFG_RANK2_WR_ODT = 3884; // 8 +const static uint64_t SH_FLD_CFG_RANK2_WR_ODT_LEN = 3885; // 8 +const static uint64_t SH_FLD_CFG_RANK3_RD_ODT = 3886; // 8 +const static uint64_t SH_FLD_CFG_RANK3_RD_ODT_LEN = 3887; // 8 +const static uint64_t SH_FLD_CFG_RANK3_WR_ODT = 3888; // 8 +const static uint64_t SH_FLD_CFG_RANK3_WR_ODT_LEN = 3889; // 8 +const static uint64_t SH_FLD_CFG_RANK4_RD_ODT = 3890; // 8 +const static uint64_t SH_FLD_CFG_RANK4_RD_ODT_LEN = 3891; // 8 +const static uint64_t SH_FLD_CFG_RANK4_WR_ODT = 3892; // 8 +const static uint64_t SH_FLD_CFG_RANK4_WR_ODT_LEN = 3893; // 8 +const static uint64_t SH_FLD_CFG_RANK5_RD_ODT = 3894; // 8 +const static uint64_t SH_FLD_CFG_RANK5_RD_ODT_LEN = 3895; // 8 +const static uint64_t SH_FLD_CFG_RANK5_WR_ODT = 3896; // 8 +const static uint64_t SH_FLD_CFG_RANK5_WR_ODT_LEN = 3897; // 8 +const static uint64_t SH_FLD_CFG_RANK6_RD_ODT = 3898; // 8 +const static uint64_t SH_FLD_CFG_RANK6_RD_ODT_LEN = 3899; // 8 +const static uint64_t SH_FLD_CFG_RANK6_WR_ODT = 3900; // 8 +const static uint64_t SH_FLD_CFG_RANK6_WR_ODT_LEN = 3901; // 8 +const static uint64_t SH_FLD_CFG_RANK7_RD_ODT = 3902; // 8 +const static uint64_t SH_FLD_CFG_RANK7_RD_ODT_LEN = 3903; // 8 +const static uint64_t SH_FLD_CFG_RANK7_WR_ODT = 3904; // 8 +const static uint64_t SH_FLD_CFG_RANK7_WR_ODT_LEN = 3905; // 8 +const static uint64_t SH_FLD_CFG_RANK_SM_STALL_DISABLE = 3906; // 8 +const static uint64_t SH_FLD_CFG_RCD_PROTECTION_TIME = 3907; // 8 +const static uint64_t SH_FLD_CFG_RCD_PROTECTION_TIME_LEN = 3908; // 8 +const static uint64_t SH_FLD_CFG_RC_FRC_DISP_EQ_NTM_INIG_SI_TO_RCR_EN = 3909; // 12 +const static uint64_t SH_FLD_CFG_RD2PRE = 3910; // 8 +const static uint64_t SH_FLD_CFG_RD2PRE_LEN = 3911; // 8 +const static uint64_t SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT = 3912; // 8 +const static uint64_t SH_FLD_CFG_RDBUFF_CAPACITY_LIMIT_LEN = 3913; // 8 +const static uint64_t SH_FLD_CFG_RDCLK_SYSCLK_LENGTH = 3914; // 8 +const static uint64_t SH_FLD_CFG_RDCLK_SYSCLK_LENGTH_LEN = 3915; // 8 +const static uint64_t SH_FLD_CFG_RDCLK_SYSCLK_TB = 3916; // 8 +const static uint64_t SH_FLD_CFG_RDCLK_SYSCLK_TB_LEN = 3917; // 8 +const static uint64_t SH_FLD_CFG_RDTAG_DLY = 3918; // 8 +const static uint64_t SH_FLD_CFG_RDTAG_DLY_LEN = 3919; // 8 +const static uint64_t SH_FLD_CFG_RDTAG_MBX_CYCLE = 3920; // 8 +const static uint64_t SH_FLD_CFG_RD_IDLE_ALLOW_WR = 3921; // 8 +const static uint64_t SH_FLD_CFG_RD_IDLE_ALLOW_WR_LEN = 3922; // 8 +const static uint64_t SH_FLD_CFG_REFRESH_ENABLE = 3923; // 8 +const static uint64_t SH_FLD_CFG_REFRESH_HP_RANK_BLOCK_ENABLE = 3924; // 8 +const static uint64_t SH_FLD_CFG_REFRESH_INTERVAL = 3925; // 8 +const static uint64_t SH_FLD_CFG_REFRESH_INTERVAL_LEN = 3926; // 8 +const static uint64_t SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT = 3927; // 8 +const static uint64_t SH_FLD_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN = 3928; // 8 +const static uint64_t SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD = 3929; // 8 +const static uint64_t SH_FLD_CFG_REFRESH_PRIORITY_THRESHOLD_LEN = 3930; // 8 +const static uint64_t SH_FLD_CFG_REFRESH_RESET_INTERVAL = 3931; // 8 +const static uint64_t SH_FLD_CFG_REFRESH_RESET_INTERVAL_LEN = 3932; // 8 +const static uint64_t SH_FLD_CFG_REFR_CHECK_INTERVAL = 3933; // 8 +const static uint64_t SH_FLD_CFG_REFR_CHECK_INTERVAL_LEN = 3934; // 8 +const static uint64_t SH_FLD_CFG_REFR_TSV_STACK = 3935; // 8 +const static uint64_t SH_FLD_CFG_REFR_TSV_STACK_LEN = 3936; // 8 +const static uint64_t SH_FLD_CFG_REF_BLOCK_STOP_DLY = 3937; // 8 +const static uint64_t SH_FLD_CFG_REF_BLOCK_STOP_DLY_LEN = 3938; // 8 +const static uint64_t SH_FLD_CFG_RESET_CNTS_START_OF_RANK = 3939; // 2 +const static uint64_t SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT = 3940; // 8 +const static uint64_t SH_FLD_CFG_RMWBUFF_CAPACITY_LIMIT_LEN = 3941; // 8 +const static uint64_t SH_FLD_CFG_RODT_BC4_END_DLY = 3942; // 8 +const static uint64_t SH_FLD_CFG_RODT_BC4_END_DLY_LEN = 3943; // 8 +const static uint64_t SH_FLD_CFG_RODT_END_DLY = 3944; // 8 +const static uint64_t SH_FLD_CFG_RODT_END_DLY_LEN = 3945; // 8 +const static uint64_t SH_FLD_CFG_RODT_START_DLY = 3946; // 8 +const static uint64_t SH_FLD_CFG_RODT_START_DLY_LEN = 3947; // 8 +const static uint64_t SH_FLD_CFG_RQ_HANG_THRESHOLD = 3948; // 8 +const static uint64_t SH_FLD_CFG_RQ_HANG_THRESHOLD_LEN = 3949; // 8 +const static uint64_t SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING = 3950; // 8 +const static uint64_t SH_FLD_CFG_RRQ_ACT_NUM_READS_PENDING_LEN = 3951; // 8 +const static uint64_t SH_FLD_CFG_RRQ_DEPTH = 3952; // 8 +const static uint64_t SH_FLD_CFG_RRQ_DEPTH_LEN = 3953; // 8 +const static uint64_t SH_FLD_CFG_RRQ_FIFO_MODE = 3954; // 8 +const static uint64_t SH_FLD_CFG_RRQ_SINGLE_THREAD_MODE = 3955; // 8 +const static uint64_t SH_FLD_CFG_RRQ_SKIP_LIMIT = 3956; // 8 +const static uint64_t SH_FLD_CFG_RRQ_SKIP_LIMIT_LEN = 3957; // 8 +const static uint64_t SH_FLD_CFG_RSV0 = 3958; // 8 +const static uint64_t SH_FLD_CFG_RSV0_LEN = 3959; // 8 +const static uint64_t SH_FLD_CFG_RUNTIME_CTR = 3960; // 2 +const static uint64_t SH_FLD_CFG_RUNTIME_CTR_LEN = 3961; // 2 +const static uint64_t SH_FLD_CFG_RUNTIME_MCBALL = 3962; // 2 +const static uint64_t SH_FLD_CFG_RUNTIME_OVERHEAD = 3963; // 2 +const static uint64_t SH_FLD_CFG_RUNTIME_SUBTEST = 3964; // 2 +const static uint64_t SH_FLD_CFG_RUNTIME_SUBTEST_LEN = 3965; // 2 +const static uint64_t SH_FLD_CFG_SAFE_REFRESH_INTERVAL = 3966; // 8 +const static uint64_t SH_FLD_CFG_SAFE_REFRESH_INTERVAL_LEN = 3967; // 8 +const static uint64_t SH_FLD_CFG_SIM_FAST_NOISE_WINDOW = 3968; // 8 +const static uint64_t SH_FLD_CFG_SINGLE_MEM = 3969; // 12 +const static uint64_t SH_FLD_CFG_SINGLE_MEM_EN = 3970; // 12 +const static uint64_t SH_FLD_CFG_SINGLE_MEM_LEN = 3971; // 12 +const static uint64_t SH_FLD_CFG_SLOT0_S0_CID = 3972; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S0_CID_LEN = 3973; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S1_CID = 3974; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S1_CID_LEN = 3975; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S2_CID = 3976; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S2_CID_LEN = 3977; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S3_CID = 3978; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S3_CID_LEN = 3979; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S4_CID = 3980; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S4_CID_LEN = 3981; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S5_CID = 3982; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S5_CID_LEN = 3983; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S6_CID = 3984; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S6_CID_LEN = 3985; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S7_CID = 3986; // 8 +const static uint64_t SH_FLD_CFG_SLOT0_S7_CID_LEN = 3987; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S0_CID = 3988; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S0_CID_LEN = 3989; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S1_CID = 3990; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S1_CID_LEN = 3991; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S2_CID = 3992; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S2_CID_LEN = 3993; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S3_CID = 3994; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S3_CID_LEN = 3995; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S4_CID = 3996; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S4_CID_LEN = 3997; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S5_CID = 3998; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S5_CID_LEN = 3999; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S6_CID = 4000; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S6_CID_LEN = 4001; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S7_CID = 4002; // 8 +const static uint64_t SH_FLD_CFG_SLOT1_S7_CID_LEN = 4003; // 8 +const static uint64_t SH_FLD_CFG_SMT_MODE = 4004; // 1 +const static uint64_t SH_FLD_CFG_SMT_MODE_LEN = 4005; // 1 +const static uint64_t SH_FLD_CFG_STALL_PULL = 4006; // 1 +const static uint64_t SH_FLD_CFG_STALL_PUSH_ARX = 4007; // 1 +const static uint64_t SH_FLD_CFG_STALL_PUSH_LCL = 4008; // 1 +const static uint64_t SH_FLD_CFG_START_ADDR_0 = 4009; // 2 +const static uint64_t SH_FLD_CFG_START_ADDR_0_LEN = 4010; // 2 +const static uint64_t SH_FLD_CFG_START_ADDR_1 = 4011; // 2 +const static uint64_t SH_FLD_CFG_START_ADDR_1_LEN = 4012; // 2 +const static uint64_t SH_FLD_CFG_START_ADDR_2 = 4013; // 2 +const static uint64_t SH_FLD_CFG_START_ADDR_2_LEN = 4014; // 2 +const static uint64_t SH_FLD_CFG_START_ADDR_3 = 4015; // 2 +const static uint64_t SH_FLD_CFG_START_ADDR_3_LEN = 4016; // 2 +const static uint64_t SH_FLD_CFG_STATIC_IDLE_DLY = 4017; // 8 +const static uint64_t SH_FLD_CFG_STATIC_IDLE_DLY_LEN = 4018; // 8 +const static uint64_t SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP = 4019; // 43 +const static uint64_t SH_FLD_CFG_STQ_PF_EN = 4020; // 12 +const static uint64_t SH_FLD_CFG_STR_ENABLE = 4021; // 8 +const static uint64_t SH_FLD_CFG_STR_STATE = 4022; // 8 +const static uint64_t SH_FLD_CFG_SYMBOL_COUNTER_MODE = 4023; // 2 +const static uint64_t SH_FLD_CFG_SYMBOL_COUNTER_MODE_LEN = 4024; // 2 +const static uint64_t SH_FLD_CFG_SYSMAP_SM_NOT_LG_SEL = 4025; // 12 +const static uint64_t SH_FLD_CFG_TCKESR = 4026; // 8 +const static uint64_t SH_FLD_CFG_TCKESR_LEN = 4027; // 8 +const static uint64_t SH_FLD_CFG_TCKSRE = 4028; // 8 +const static uint64_t SH_FLD_CFG_TCKSRE_LEN = 4029; // 8 +const static uint64_t SH_FLD_CFG_TCKSRX = 4030; // 8 +const static uint64_t SH_FLD_CFG_TCKSRX_LEN = 4031; // 8 +const static uint64_t SH_FLD_CFG_TFAW = 4032; // 8 +const static uint64_t SH_FLD_CFG_TFAW_LEN = 4033; // 8 +const static uint64_t SH_FLD_CFG_THRD_C0_EN = 4034; // 1 +const static uint64_t SH_FLD_CFG_THRD_C0_EN_LEN = 4035; // 1 +const static uint64_t SH_FLD_CFG_THRD_C10_EN = 4036; // 1 +const static uint64_t SH_FLD_CFG_THRD_C10_EN_LEN = 4037; // 1 +const static uint64_t SH_FLD_CFG_THRD_C11_EN = 4038; // 1 +const static uint64_t SH_FLD_CFG_THRD_C11_EN_LEN = 4039; // 1 +const static uint64_t SH_FLD_CFG_THRD_C1_EN = 4040; // 1 +const static uint64_t SH_FLD_CFG_THRD_C1_EN_LEN = 4041; // 1 +const static uint64_t SH_FLD_CFG_THRD_C2_EN = 4042; // 1 +const static uint64_t SH_FLD_CFG_THRD_C2_EN_LEN = 4043; // 1 +const static uint64_t SH_FLD_CFG_THRD_C3_EN = 4044; // 1 +const static uint64_t SH_FLD_CFG_THRD_C3_EN_LEN = 4045; // 1 +const static uint64_t SH_FLD_CFG_THRD_C4_EN = 4046; // 1 +const static uint64_t SH_FLD_CFG_THRD_C4_EN_LEN = 4047; // 1 +const static uint64_t SH_FLD_CFG_THRD_C5_EN = 4048; // 1 +const static uint64_t SH_FLD_CFG_THRD_C5_EN_LEN = 4049; // 1 +const static uint64_t SH_FLD_CFG_THRD_C6_EN = 4050; // 1 +const static uint64_t SH_FLD_CFG_THRD_C6_EN_LEN = 4051; // 1 +const static uint64_t SH_FLD_CFG_THRD_C7_EN = 4052; // 1 +const static uint64_t SH_FLD_CFG_THRD_C7_EN_LEN = 4053; // 1 +const static uint64_t SH_FLD_CFG_THRD_C8_EN = 4054; // 1 +const static uint64_t SH_FLD_CFG_THRD_C8_EN_LEN = 4055; // 1 +const static uint64_t SH_FLD_CFG_THRD_C9_EN = 4056; // 1 +const static uint64_t SH_FLD_CFG_THRD_C9_EN_LEN = 4057; // 1 +const static uint64_t SH_FLD_CFG_THRESH_MAG_ICE = 4058; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_ICE_LEN = 4059; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_HARD = 4060; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_HARD_LEN = 4061; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_INT = 4062; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_INT_LEN = 4063; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_SOFT = 4064; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_MCE_SOFT_LEN = 4065; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_HARD = 4066; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_HARD_LEN = 4067; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_INT = 4068; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_INT_LEN = 4069; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_SOFT = 4070; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_NCE_SOFT_LEN = 4071; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_RCE = 4072; // 2 +const static uint64_t SH_FLD_CFG_THRESH_MAG_RCE_LEN = 4073; // 2 +const static uint64_t SH_FLD_CFG_TIME_BASE_TMR0 = 4074; // 8 +const static uint64_t SH_FLD_CFG_TIME_BASE_TMR0_LEN = 4075; // 8 +const static uint64_t SH_FLD_CFG_TIME_BASE_TMR1 = 4076; // 8 +const static uint64_t SH_FLD_CFG_TIME_BASE_TMR1_LEN = 4077; // 8 +const static uint64_t SH_FLD_CFG_TIME_BASE_TMR2 = 4078; // 8 +const static uint64_t SH_FLD_CFG_TIME_BASE_TMR2_LEN = 4079; // 8 +const static uint64_t SH_FLD_CFG_TRAS = 4080; // 8 +const static uint64_t SH_FLD_CFG_TRAS_LEN = 4081; // 8 +const static uint64_t SH_FLD_CFG_TRCD = 4082; // 8 +const static uint64_t SH_FLD_CFG_TRCD_LEN = 4083; // 8 +const static uint64_t SH_FLD_CFG_TRFC = 4084; // 8 +const static uint64_t SH_FLD_CFG_TRFC_COUNTER_DIS = 4085; // 8 +const static uint64_t SH_FLD_CFG_TRFC_COUNTER_DIS_LEN = 4086; // 8 +const static uint64_t SH_FLD_CFG_TRFC_LEN = 4087; // 8 +const static uint64_t SH_FLD_CFG_TRFC_STACK_GATE_ALL_REF = 4088; // 8 +const static uint64_t SH_FLD_CFG_TRP = 4089; // 8 +const static uint64_t SH_FLD_CFG_TRP_LEN = 4090; // 8 +const static uint64_t SH_FLD_CFG_TXSDLL = 4091; // 8 +const static uint64_t SH_FLD_CFG_TXSDLL_LEN = 4092; // 8 +const static uint64_t SH_FLD_CFG_WAT_ACT_FRC_TB_PULSE_PULSE = 4093; // 2 +const static uint64_t SH_FLD_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN = 4094; // 2 +const static uint64_t SH_FLD_CFG_WAT_ACT_MNT_GO_IDLE_PULSE = 4095; // 2 +const static uint64_t SH_FLD_CFG_WAT_ACT_MNT_GO_IDLE_PULSE_LEN = 4096; // 2 +const static uint64_t SH_FLD_CFG_WAT_ACT_SET_SPATTN_PULSE = 4097; // 2 +const static uint64_t SH_FLD_CFG_WAT_ACT_SET_SPATTN_PULSE_LEN = 4098; // 2 +const static uint64_t SH_FLD_CFG_WAT_CAL_SYNC = 4099; // 8 +const static uint64_t SH_FLD_CFG_WAT_CAL_SYNC_LEN = 4100; // 8 +const static uint64_t SH_FLD_CFG_WAT_DIS_RD_PG = 4101; // 8 +const static uint64_t SH_FLD_CFG_WAT_DIS_RD_PG_LEN = 4102; // 8 +const static uint64_t SH_FLD_CFG_WAT_DIS_WR_PG = 4103; // 8 +const static uint64_t SH_FLD_CFG_WAT_DIS_WR_PG_LEN = 4104; // 8 +const static uint64_t SH_FLD_CFG_WAT_EMER_TH = 4105; // 8 +const static uint64_t SH_FLD_CFG_WAT_EMER_TH_LEN = 4106; // 8 +const static uint64_t SH_FLD_CFG_WAT_ENABLE = 4107; // 2 +const static uint64_t SH_FLD_CFG_WAT_EXIT_STR = 4108; // 8 +const static uint64_t SH_FLD_CFG_WAT_EXIT_STR_LEN = 4109; // 8 +const static uint64_t SH_FLD_CFG_WAT_EXT_ARM_SEL = 4110; // 2 +const static uint64_t SH_FLD_CFG_WAT_EXT_ARM_SEL_LEN = 4111; // 2 +const static uint64_t SH_FLD_CFG_WAT_EXT_EVENT_TO_INT = 4112; // 2 +const static uint64_t SH_FLD_CFG_WAT_EXT_EVENT_TO_INT_LEN = 4113; // 2 +const static uint64_t SH_FLD_CFG_WAT_EXT_RESET_SEL = 4114; // 2 +const static uint64_t SH_FLD_CFG_WAT_EXT_RESET_SEL_LEN = 4115; // 2 +const static uint64_t SH_FLD_CFG_WAT_EXT_TRIGGER_SEL = 4116; // 2 +const static uint64_t SH_FLD_CFG_WAT_EXT_TRIGGER_SEL_LEN = 4117; // 2 +const static uint64_t SH_FLD_CFG_WAT_FARB_CAL_GT = 4118; // 8 +const static uint64_t SH_FLD_CFG_WAT_FARB_CAL_GT_LEN = 4119; // 8 +const static uint64_t SH_FLD_CFG_WAT_FARB_REF_GT = 4120; // 8 +const static uint64_t SH_FLD_CFG_WAT_FARB_REF_GT_LEN = 4121; // 8 +const static uint64_t SH_FLD_CFG_WAT_FARB_RRQ_GT = 4122; // 8 +const static uint64_t SH_FLD_CFG_WAT_FARB_RRQ_GT_LEN = 4123; // 8 +const static uint64_t SH_FLD_CFG_WAT_FARB_WRQ_GT = 4124; // 8 +const static uint64_t SH_FLD_CFG_WAT_FARB_WRQ_GT_LEN = 4125; // 8 +const static uint64_t SH_FLD_CFG_WAT_FORCE_RD_ENTRY0_HP = 4126; // 8 +const static uint64_t SH_FLD_CFG_WAT_FORCE_RD_ENTRY0_HP_LEN = 4127; // 8 +const static uint64_t SH_FLD_CFG_WAT_FORCE_WR_ENTRY0_HP = 4128; // 8 +const static uint64_t SH_FLD_CFG_WAT_FORCE_WR_ENTRY0_HP_LEN = 4129; // 8 +const static uint64_t SH_FLD_CFG_WAT_FP_DIS = 4130; // 8 +const static uint64_t SH_FLD_CFG_WAT_FP_DIS_LEN = 4131; // 8 +const static uint64_t SH_FLD_CFG_WAT_GLOB_EVENT0_SEL = 4132; // 2 +const static uint64_t SH_FLD_CFG_WAT_GLOB_EVENT0_SEL_LEN = 4133; // 2 +const static uint64_t SH_FLD_CFG_WAT_GLOB_EVENT1_SEL = 4134; // 2 +const static uint64_t SH_FLD_CFG_WAT_GLOB_EVENT1_SEL_LEN = 4135; // 2 +const static uint64_t SH_FLD_CFG_WAT_GLOB_EVENT2_SEL = 4136; // 2 +const static uint64_t SH_FLD_CFG_WAT_GLOB_EVENT2_SEL_LEN = 4137; // 2 +const static uint64_t SH_FLD_CFG_WAT_GLOB_EVENT3_SEL = 4138; // 2 +const static uint64_t SH_FLD_CFG_WAT_GLOB_EVENT3_SEL_LEN = 4139; // 2 +const static uint64_t SH_FLD_CFG_WAT_LOC_EVENT0_SEL = 4140; // 2 +const static uint64_t SH_FLD_CFG_WAT_LOC_EVENT0_SEL_LEN = 4141; // 2 +const static uint64_t SH_FLD_CFG_WAT_LOC_EVENT1_SEL = 4142; // 2 +const static uint64_t SH_FLD_CFG_WAT_LOC_EVENT1_SEL_LEN = 4143; // 2 +const static uint64_t SH_FLD_CFG_WAT_LOC_EVENT2_SEL = 4144; // 2 +const static uint64_t SH_FLD_CFG_WAT_LOC_EVENT2_SEL_LEN = 4145; // 2 +const static uint64_t SH_FLD_CFG_WAT_LOC_EVENT3_SEL = 4146; // 2 +const static uint64_t SH_FLD_CFG_WAT_LOC_EVENT3_SEL_LEN = 4147; // 2 +const static uint64_t SH_FLD_CFG_WAT_OUTPUT_PULSE = 4148; // 2 +const static uint64_t SH_FLD_CFG_WAT_PUP_ALL = 4149; // 8 +const static uint64_t SH_FLD_CFG_WAT_PUP_ALL_LEN = 4150; // 8 +const static uint64_t SH_FLD_CFG_WAT_REF_HP = 4151; // 8 +const static uint64_t SH_FLD_CFG_WAT_REF_HP_LEN = 4152; // 8 +const static uint64_t SH_FLD_CFG_WAT_REF_SAFE = 4153; // 8 +const static uint64_t SH_FLD_CFG_WAT_REF_SAFE_LEN = 4154; // 8 +const static uint64_t SH_FLD_CFG_WAT_REF_SYNC = 4155; // 8 +const static uint64_t SH_FLD_CFG_WAT_REF_SYNC_LEN = 4156; // 8 +const static uint64_t SH_FLD_CFG_WAT_RRQ_MNT_GT = 4157; // 8 +const static uint64_t SH_FLD_CFG_WAT_RRQ_MNT_GT_LEN = 4158; // 8 +const static uint64_t SH_FLD_CFG_WAT_SET_FIR = 4159; // 8 +const static uint64_t SH_FLD_CFG_WAT_SET_FIR_LEN = 4160; // 8 +const static uint64_t SH_FLD_CFG_WAT_START_RECOVERY = 4161; // 8 +const static uint64_t SH_FLD_CFG_WAT_START_RECOVERY_LEN = 4162; // 8 +const static uint64_t SH_FLD_CFG_WAT_WRQ_MNT_GT = 4163; // 8 +const static uint64_t SH_FLD_CFG_WAT_WRQ_MNT_GT_LEN = 4164; // 8 +const static uint64_t SH_FLD_CFG_WDF_SERIAL_SEQ_MODE = 4165; // 8 +const static uint64_t SH_FLD_CFG_WODT_BC4_END_DLY = 4166; // 8 +const static uint64_t SH_FLD_CFG_WODT_BC4_END_DLY_LEN = 4167; // 8 +const static uint64_t SH_FLD_CFG_WODT_END_DLY = 4168; // 8 +const static uint64_t SH_FLD_CFG_WODT_END_DLY_LEN = 4169; // 8 +const static uint64_t SH_FLD_CFG_WODT_START_DLY = 4170; // 8 +const static uint64_t SH_FLD_CFG_WODT_START_DLY_LEN = 4171; // 8 +const static uint64_t SH_FLD_CFG_WR2PRE = 4172; // 8 +const static uint64_t SH_FLD_CFG_WR2PRE_LEN = 4173; // 8 +const static uint64_t SH_FLD_CFG_WRDATA_DLY = 4174; // 8 +const static uint64_t SH_FLD_CFG_WRDATA_DLY_LEN = 4175; // 8 +const static uint64_t SH_FLD_CFG_WRDONE_DLY = 4176; // 8 +const static uint64_t SH_FLD_CFG_WRDONE_DLY_LEN = 4177; // 8 +const static uint64_t SH_FLD_CFG_WRITE_CA_OR_UR_RESPONSE = 4178; // 6 +const static uint64_t SH_FLD_CFG_WRITE_HW_MARK = 4179; // 8 +const static uint64_t SH_FLD_CFG_WRITE_HW_MARK_LEN = 4180; // 8 +const static uint64_t SH_FLD_CFG_WRITE_LW_MARK = 4181; // 8 +const static uint64_t SH_FLD_CFG_WRITE_LW_MARK_LEN = 4182; // 8 +const static uint64_t SH_FLD_CFG_WRITE_MODE_ECC_CHK_DIS = 4183; // 16 +const static uint64_t SH_FLD_CFG_WRITE_MODE_ECC_COR_DIS = 4184; // 16 +const static uint64_t SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING = 4185; // 8 +const static uint64_t SH_FLD_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN = 4186; // 8 +const static uint64_t SH_FLD_CFG_WRQ_DEPTH = 4187; // 8 +const static uint64_t SH_FLD_CFG_WRQ_DEPTH_LEN = 4188; // 8 +const static uint64_t SH_FLD_CFG_WRQ_ENABLE_NON_HP_WR = 4189; // 8 +const static uint64_t SH_FLD_CFG_WRQ_ENTRY0_HP_DLY = 4190; // 8 +const static uint64_t SH_FLD_CFG_WRQ_ENTRY0_HP_DLY_LEN = 4191; // 8 +const static uint64_t SH_FLD_CFG_WRQ_FIFO_MODE = 4192; // 8 +const static uint64_t SH_FLD_CFG_WRQ_FLUSH_WR_RANK = 4193; // 8 +const static uint64_t SH_FLD_CFG_WRQ_SINGLE_THREAD_MODE = 4194; // 8 +const static uint64_t SH_FLD_CFG_WRQ_SKIP_LIMIT = 4195; // 8 +const static uint64_t SH_FLD_CFG_WRQ_SKIP_LIMIT_LEN = 4196; // 8 +const static uint64_t SH_FLD_CGC = 4197; // 24 +const static uint64_t SH_FLD_CGC_LEN = 4198; // 24 +const static uint64_t SH_FLD_CH0EFT_ACTION = 4199; // 1 +const static uint64_t SH_FLD_CH0EFT_ENA = 4200; // 1 +const static uint64_t SH_FLD_CH0EFT_SELECT = 4201; // 1 +const static uint64_t SH_FLD_CH0EFT_SELECT_LEN = 4202; // 1 +const static uint64_t SH_FLD_CH0EFT_TYPE = 4203; // 1 +const static uint64_t SH_FLD_CH0_842_ECC_CE = 4204; // 1 +const static uint64_t SH_FLD_CH0_842_ECC_UE = 4205; // 1 +const static uint64_t SH_FLD_CH0_CMD_CREDITS_0_5 = 4206; // 1 +const static uint64_t SH_FLD_CH0_CMD_CREDITS_0_5_LEN = 4207; // 1 +const static uint64_t SH_FLD_CH0_EFT = 4208; // 1 +const static uint64_t SH_FLD_CH0_INVALID_STATE = 4209; // 1 +const static uint64_t SH_FLD_CH0_MAX = 4210; // 2 +const static uint64_t SH_FLD_CH0_MAX_LEN = 4211; // 2 +const static uint64_t SH_FLD_CH0_REF_DIV = 4212; // 1 +const static uint64_t SH_FLD_CH0_REF_DIV_LEN = 4213; // 1 +const static uint64_t SH_FLD_CH0_TIMER_ENBL = 4214; // 1 +const static uint64_t SH_FLD_CH1EFT_ACTION = 4215; // 1 +const static uint64_t SH_FLD_CH1EFT_ENA = 4216; // 1 +const static uint64_t SH_FLD_CH1EFT_SELECT = 4217; // 1 +const static uint64_t SH_FLD_CH1EFT_SELECT_LEN = 4218; // 1 +const static uint64_t SH_FLD_CH1EFT_TYPE = 4219; // 1 +const static uint64_t SH_FLD_CH1_842_ECC_CE = 4220; // 1 +const static uint64_t SH_FLD_CH1_842_ECC_UE = 4221; // 1 +const static uint64_t SH_FLD_CH1_CMD_CREDITS_0_5 = 4222; // 1 +const static uint64_t SH_FLD_CH1_CMD_CREDITS_0_5_LEN = 4223; // 1 +const static uint64_t SH_FLD_CH1_DAT_CREDITS_0_5 = 4224; // 1 +const static uint64_t SH_FLD_CH1_DAT_CREDITS_0_5_LEN = 4225; // 1 +const static uint64_t SH_FLD_CH1_EFT = 4226; // 1 +const static uint64_t SH_FLD_CH1_INVALID_STATE = 4227; // 1 +const static uint64_t SH_FLD_CH1_MAX = 4228; // 2 +const static uint64_t SH_FLD_CH1_MAX_LEN = 4229; // 2 +const static uint64_t SH_FLD_CH1_REF_DIV = 4230; // 1 +const static uint64_t SH_FLD_CH1_REF_DIV_LEN = 4231; // 1 +const static uint64_t SH_FLD_CH1_TIMER_ENBL = 4232; // 1 +const static uint64_t SH_FLD_CH2_CMD_CREDITS_PC_0_5 = 4233; // 1 +const static uint64_t SH_FLD_CH2_CMD_CREDITS_PC_0_5_LEN = 4234; // 1 +const static uint64_t SH_FLD_CH2_CMD_CREDITS_VC_0_5 = 4235; // 1 +const static uint64_t SH_FLD_CH2_CMD_CREDITS_VC_0_5_LEN = 4236; // 1 +const static uint64_t SH_FLD_CH2_INVALID_STATE = 4237; // 1 +const static uint64_t SH_FLD_CH2_MAX = 4238; // 2 +const static uint64_t SH_FLD_CH2_MAX_LEN = 4239; // 2 +const static uint64_t SH_FLD_CH2_REF_DIV = 4240; // 1 +const static uint64_t SH_FLD_CH2_REF_DIV_LEN = 4241; // 1 +const static uint64_t SH_FLD_CH2_SYM = 4242; // 1 +const static uint64_t SH_FLD_CH2_TIMER_ENBL = 4243; // 1 +const static uint64_t SH_FLD_CH3_INVALID_STATE = 4244; // 1 +const static uint64_t SH_FLD_CH3_MAX = 4245; // 2 +const static uint64_t SH_FLD_CH3_MAX_LEN = 4246; // 2 +const static uint64_t SH_FLD_CH3_REF_DIV = 4247; // 1 +const static uint64_t SH_FLD_CH3_REF_DIV_LEN = 4248; // 1 +const static uint64_t SH_FLD_CH3_SYM = 4249; // 1 +const static uint64_t SH_FLD_CH3_TIMER_ENBL = 4250; // 1 +const static uint64_t SH_FLD_CH4GZIP_ACTION = 4251; // 1 +const static uint64_t SH_FLD_CH4GZIP_ENA = 4252; // 1 +const static uint64_t SH_FLD_CH4GZIP_SELECT = 4253; // 1 +const static uint64_t SH_FLD_CH4GZIP_SELECT_LEN = 4254; // 1 +const static uint64_t SH_FLD_CH4GZIP_TYPE = 4255; // 1 +const static uint64_t SH_FLD_CH4_AMF_ECC_CE = 4256; // 1 +const static uint64_t SH_FLD_CH4_AMF_ECC_UE = 4257; // 1 +const static uint64_t SH_FLD_CH4_GZIP = 4258; // 1 +const static uint64_t SH_FLD_CH4_INVALID_STATE = 4259; // 1 +const static uint64_t SH_FLD_CH4_REF_DIV = 4260; // 1 +const static uint64_t SH_FLD_CH4_REF_DIV_LEN = 4261; // 1 +const static uint64_t SH_FLD_CH4_TIMER_ENBL = 4262; // 1 +const static uint64_t SH_FLD_CH5_AMF_ECC_CE = 4263; // 1 +const static uint64_t SH_FLD_CH5_AMF_ECC_UE = 4264; // 1 +const static uint64_t SH_FLD_CH5_INVALID_STATE = 4265; // 1 +const static uint64_t SH_FLD_CH6_AMF_ECC_CE = 4266; // 1 +const static uint64_t SH_FLD_CH6_AMF_ECC_UE = 4267; // 1 +const static uint64_t SH_FLD_CH6_INVALID_STATE = 4268; // 1 +const static uint64_t SH_FLD_CH7_AMF_ECC_CE = 4269; // 1 +const static uint64_t SH_FLD_CH7_AMF_ECC_UE = 4270; // 1 +const static uint64_t SH_FLD_CH7_INVALID_STATE = 4271; // 1 +const static uint64_t SH_FLD_CHANGE_IN_PROGRESS = 4272; // 2 +const static uint64_t SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION = 4273; // 4 +const static uint64_t SH_FLD_CHANNEL_0_GROUP_MEMBER_IDENTIFICATION_LEN = 4274; // 4 +const static uint64_t SH_FLD_CHANNEL_0_TIMEOUT_ERROR = 4275; // 4 +const static uint64_t SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION = 4276; // 4 +const static uint64_t SH_FLD_CHANNEL_1_GROUP_MEMBER_IDENTIFICATION_LEN = 4277; // 4 +const static uint64_t SH_FLD_CHANNEL_1_TIMEOUT_ERROR = 4278; // 4 +const static uint64_t SH_FLD_CHANNEL_SELECT = 4279; // 4 +const static uint64_t SH_FLD_CHANNEL_SELECT_LEN = 4280; // 4 +const static uint64_t SH_FLD_CHECKSTOP = 4281; // 1 +const static uint64_t SH_FLD_CHECK_CMDS = 4282; // 2 +const static uint64_t SH_FLD_CHECK_CMDS_EN = 4283; // 2 +const static uint64_t SH_FLD_CHECK_CMDS_LEN = 4284; // 2 +const static uint64_t SH_FLD_CHECK_STOP_GPE0 = 4285; // 1 +const static uint64_t SH_FLD_CHECK_STOP_GPE1 = 4286; // 1 +const static uint64_t SH_FLD_CHECK_STOP_GPE2 = 4287; // 1 +const static uint64_t SH_FLD_CHECK_STOP_GPE3 = 4288; // 1 +const static uint64_t SH_FLD_CHECK_STOP_PPC405 = 4289; // 1 +const static uint64_t SH_FLD_CHGRATE = 4290; // 12 +const static uint64_t SH_FLD_CHIPLET_ATOMIC_LOCK = 4291; // 43 +const static uint64_t SH_FLD_CHIPLET_ENABLE = 4292; // 43 +const static uint64_t SH_FLD_CHIPLET_ERRORS = 4293; // 43 +const static uint64_t SH_FLD_CHIPLET_ERRORS_LEN = 4294; // 43 +const static uint64_t SH_FLD_CHIPLET_GRID_SKITTER = 4295; // 43 +const static uint64_t SH_FLD_CHIPLET_INTERRUPT_FROM_HOST = 4296; // 1 +const static uint64_t SH_FLD_CHIPLET_IS_ALIGNED = 4297; // 43 +const static uint64_t SH_FLD_CHIPLET_OFFLINE = 4298; // 43 +const static uint64_t SH_FLD_CHIPMARK = 4299; // 72 +const static uint64_t SH_FLD_CHIPMARK_LEN = 4300; // 72 +const static uint64_t SH_FLD_CHIPPOS = 4301; // 1 +const static uint64_t SH_FLD_CHIP_INTERFACEMODE = 4302; // 2 +const static uint64_t SH_FLD_CHIP_PERSONALISATION = 4303; // 2 +const static uint64_t SH_FLD_CHIP_RESET = 4304; // 1 +const static uint64_t SH_FLD_CHIP_STATUS = 4305; // 194 +const static uint64_t SH_FLD_CHIP_STATUS_LEN = 4306; // 194 +const static uint64_t SH_FLD_CHIP_TOD_STATUS = 4307; // 98 +const static uint64_t SH_FLD_CHIP_TOD_STATUS_LEN = 4308; // 98 +const static uint64_t SH_FLD_CHKSW_ALLOW1_RD = 4309; // 1 +const static uint64_t SH_FLD_CHKSW_ALLOW1_RDWR = 4310; // 1 +const static uint64_t SH_FLD_CHKSW_ALLOW1_WR = 4311; // 1 +const static uint64_t SH_FLD_CHKSW_I2C_BUSY_0 = 4312; // 2 +const static uint64_t SH_FLD_CHKSW_I2C_BUSY_1 = 4313; // 1 +const static uint64_t SH_FLD_CHKSW_I2C_BUSY_2 = 4314; // 1 +const static uint64_t SH_FLD_CHKSW_I2C_BUSY_3 = 4315; // 1 +const static uint64_t SH_FLD_CHKSW_OCI_PARCHK_DIS = 4316; // 1 +const static uint64_t SH_FLD_CHKSW_SO_SPARE = 4317; // 1 +const static uint64_t SH_FLD_CHKSW_SO_SPARE_LEN = 4318; // 1 +const static uint64_t SH_FLD_CHKSW_SPARE_6 = 4319; // 1 +const static uint64_t SH_FLD_CHKSW_TANK_RDDATA_PARCHK_DIS = 4320; // 1 +const static uint64_t SH_FLD_CHKSW_VAL_BE_ADDR_CHK_DIS = 4321; // 1 +const static uint64_t SH_FLD_CHKSW_WRFSM_DLY_DIS = 4322; // 1 +const static uint64_t SH_FLD_CHOP1G = 4323; // 1 +const static uint64_t SH_FLD_CHSW_DIS_DATA_HANG = 4324; // 1 +const static uint64_t SH_FLD_CHSW_DIS_ECC_CHECK = 4325; // 1 +const static uint64_t SH_FLD_CHSW_DIS_GROUP_SCOPE = 4326; // 1 +const static uint64_t SH_FLD_CHSW_DIS_OCIABUSPAR_CHECK = 4327; // 1 +const static uint64_t SH_FLD_CHSW_DIS_OCIBEPAR_CHECK = 4328; // 1 +const static uint64_t SH_FLD_CHSW_DIS_OCIDATAPAR_CHECK = 4329; // 1 +const static uint64_t SH_FLD_CHSW_DIS_OCIDATAPAR_GEN = 4330; // 1 +const static uint64_t SH_FLD_CHSW_DIS_OPER_HANG = 4331; // 1 +const static uint64_t SH_FLD_CHSW_DIS_PB_PARITY_CHK = 4332; // 1 +const static uint64_t SH_FLD_CHSW_DIS_RETRY_BACKOFF = 4333; // 1 +const static uint64_t SH_FLD_CHSW_DIS_RTAG_PARITY_CHK = 4334; // 1 +const static uint64_t SH_FLD_CHSW_DIS_WRITE_MATCH_REARB = 4335; // 1 +const static uint64_t SH_FLD_CHSW_EXIT_ON_INVALID_CRESP = 4336; // 1 +const static uint64_t SH_FLD_CHSW_HANG_ON_ADRERROR = 4337; // 1 +const static uint64_t SH_FLD_CHSW_HANG_ON_DERROR = 4338; // 1 +const static uint64_t SH_FLD_CHSW_SKIP_GROUP_SCOPE = 4339; // 1 +const static uint64_t SH_FLD_CHSW_USE_CL_DMA_INJ = 4340; // 1 +const static uint64_t SH_FLD_CHSW_USE_PR_DMA_INJ = 4341; // 1 +const static uint64_t SH_FLD_CHTM_PURGE_C0 = 4342; // 12 +const static uint64_t SH_FLD_CHTM_PURGE_C1 = 4343; // 12 +const static uint64_t SH_FLD_CHTM_PURGE_DONE_C0 = 4344; // 24 +const static uint64_t SH_FLD_CHTM_PURGE_DONE_C1 = 4345; // 24 +const static uint64_t SH_FLD_CI_BUFF_AVAIL = 4346; // 2 +const static uint64_t SH_FLD_CI_BUFF_MIN = 4347; // 2 +const static uint64_t SH_FLD_CI_BUFF_MIN_LEN = 4348; // 2 +const static uint64_t SH_FLD_CI_LOAD = 4349; // 2 +const static uint64_t SH_FLD_CI_LOAD_LEN = 4350; // 2 +const static uint64_t SH_FLD_CI_MACHINE_HANG = 4351; // 12 +const static uint64_t SH_FLD_CI_READ = 4352; // 1 +const static uint64_t SH_FLD_CI_STORE = 4353; // 1 +const static uint64_t SH_FLD_CI_STORE_BUFFER_THRESHOLD = 4354; // 2 +const static uint64_t SH_FLD_CI_STORE_BUFFER_THRESHOLD_LEN = 4355; // 2 +const static uint64_t SH_FLD_CI_STORE_LEN = 4356; // 1 +const static uint64_t SH_FLD_CI_STORE_RMT = 4357; // 1 +const static uint64_t SH_FLD_CI_STORE_RMT_LEN = 4358; // 1 +const static uint64_t SH_FLD_CI_STORE_RMT_VC = 4359; // 1 +const static uint64_t SH_FLD_CI_STORE_RMT_VC_LEN = 4360; // 1 +const static uint64_t SH_FLD_CI_WRITE = 4361; // 1 +const static uint64_t SH_FLD_CKINSM_DIS = 4362; // 1 +const static uint64_t SH_FLD_CKINSM_DIS_LEN = 4363; // 1 +const static uint64_t SH_FLD_CKIN_PROT_ERR_CHK_DIS = 4364; // 1 +const static uint64_t SH_FLD_CKIN_TIMEOUT_CHK_DIS = 4365; // 1 +const static uint64_t SH_FLD_CL = 4366; // 1 +const static uint64_t SH_FLD_CLEAR = 4367; // 1 +const static uint64_t SH_FLD_CLEAR_CHIPLET_IS_ALIGNED = 4368; // 43 +const static uint64_t SH_FLD_CLEAR_STICKY_LEVEL = 4369; // 24 +const static uint64_t SH_FLD_CLKDIST_PDWN = 4370; // 12 +const static uint64_t SH_FLD_CLKDIST_PDWN_LEN = 4371; // 4 +const static uint64_t SH_FLD_CLKGLM_ASYNC_RESET = 4372; // 30 +const static uint64_t SH_FLD_CLKGLM_SEL = 4373; // 30 +const static uint64_t SH_FLD_CLK_ASYNC_RESET = 4374; // 43 +const static uint64_t SH_FLD_CLK_BIST_ACTIVITY_DET = 4375; // 4 +const static uint64_t SH_FLD_CLK_BIST_ERR = 4376; // 4 +const static uint64_t SH_FLD_CLK_DCC_BYPASS_EN = 4377; // 43 +const static uint64_t SH_FLD_CLK_DIV_BYPASS_EN = 4378; // 43 +const static uint64_t SH_FLD_CLK_DLY = 4379; // 1 +const static uint64_t SH_FLD_CLK_DLY_LEN = 4380; // 1 +const static uint64_t SH_FLD_CLK_HALF_WIDTH_MODE = 4381; // 4 +const static uint64_t SH_FLD_CLK_INVERT = 4382; // 6 +const static uint64_t SH_FLD_CLK_PDLY_BYPASS_EN = 4383; // 43 +const static uint64_t SH_FLD_CLK_PULSE_EN = 4384; // 43 +const static uint64_t SH_FLD_CLK_PULSE_MODE = 4385; // 43 +const static uint64_t SH_FLD_CLK_PULSE_MODE_LEN = 4386; // 43 +const static uint64_t SH_FLD_CLK_QUIESCE = 4387; // 4 +const static uint64_t SH_FLD_CLK_QUIESCE_LEN = 4388; // 4 +const static uint64_t SH_FLD_CLK_QUIESCE_N = 4389; // 1 +const static uint64_t SH_FLD_CLK_QUIESCE_N_LEN = 4390; // 1 +const static uint64_t SH_FLD_CLK_QUIESCE_P = 4391; // 1 +const static uint64_t SH_FLD_CLK_QUIESCE_P_LEN = 4392; // 1 +const static uint64_t SH_FLD_CLK_RATE = 4393; // 4 +const static uint64_t SH_FLD_CLK_RATE_LEN = 4394; // 4 +const static uint64_t SH_FLD_CLK_RATE_SEL = 4395; // 1 +const static uint64_t SH_FLD_CLK_RATE_SEL_LEN = 4396; // 1 +const static uint64_t SH_FLD_CLK_RUN_COUNT = 4397; // 4 +const static uint64_t SH_FLD_CLK_SB_PULSE_MODE = 4398; // 24 +const static uint64_t SH_FLD_CLK_SB_PULSE_MODE_EN = 4399; // 24 +const static uint64_t SH_FLD_CLK_SB_PULSE_MODE_LEN = 4400; // 24 +const static uint64_t SH_FLD_CLK_SB_SPARE = 4401; // 24 +const static uint64_t SH_FLD_CLK_SB_STRENGTH = 4402; // 24 +const static uint64_t SH_FLD_CLK_SB_STRENGTH_LEN = 4403; // 24 +const static uint64_t SH_FLD_CLK_SW_RESCLK = 4404; // 24 +const static uint64_t SH_FLD_CLK_SW_RESCLK_LEN = 4405; // 24 +const static uint64_t SH_FLD_CLK_SW_SPARE = 4406; // 24 +const static uint64_t SH_FLD_CLK_SYNC = 4407; // 24 +const static uint64_t SH_FLD_CLK_SYNC_DONE = 4408; // 24 +const static uint64_t SH_FLD_CLK_SYNC_ENABLE = 4409; // 24 +const static uint64_t SH_FLD_CLK_UNLOAD_CLK_DISABLE = 4410; // 4 +const static uint64_t SH_FLD_CLK_UNLOAD_SEL = 4411; // 4 +const static uint64_t SH_FLD_CLK_UNLOAD_SEL_LEN = 4412; // 4 +const static uint64_t SH_FLD_CLOCK_CMD = 4413; // 43 +const static uint64_t SH_FLD_CLOCK_CMD_LEN = 4414; // 43 +const static uint64_t SH_FLD_CLOCK_DIVIDER = 4415; // 1 +const static uint64_t SH_FLD_CLOCK_DIVIDER_LEN = 4416; // 1 +const static uint64_t SH_FLD_CLOCK_DIV_4 = 4417; // 3 +const static uint64_t SH_FLD_CLOCK_PERV = 4418; // 43 +const static uint64_t SH_FLD_CLOCK_PULSE_USE_EVEN = 4419; // 43 +const static uint64_t SH_FLD_CLOCK_RATE_SELECTION = 4420; // 3 +const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_0 = 4421; // 1 +const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_0_LEN = 4422; // 1 +const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_1 = 4423; // 2 +const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_1_LEN = 4424; // 2 +const static uint64_t SH_FLD_CLOCK_RATE_SELECTION_LEN = 4425; // 3 +const static uint64_t SH_FLD_CLOCK_UNIT1 = 4426; // 43 +const static uint64_t SH_FLD_CLOCK_UNIT10 = 4427; // 43 +const static uint64_t SH_FLD_CLOCK_UNIT2 = 4428; // 43 +const static uint64_t SH_FLD_CLOCK_UNIT3 = 4429; // 43 +const static uint64_t SH_FLD_CLOCK_UNIT4 = 4430; // 43 +const static uint64_t SH_FLD_CLOCK_UNIT5 = 4431; // 43 +const static uint64_t SH_FLD_CLOCK_UNIT6 = 4432; // 43 +const static uint64_t SH_FLD_CLOCK_UNIT7 = 4433; // 43 +const static uint64_t SH_FLD_CLOCK_UNIT8 = 4434; // 43 +const static uint64_t SH_FLD_CLOCK_UNIT9 = 4435; // 43 +const static uint64_t SH_FLD_CLONE_CS_MODE = 4436; // 8 +const static uint64_t SH_FLD_CLR_PAR_ERRS = 4437; // 16 +const static uint64_t SH_FLD_CL_DATA = 4438; // 43 +const static uint64_t SH_FLD_CL_ECC_CE = 4439; // 1 +const static uint64_t SH_FLD_CL_ECC_UE = 4440; // 1 +const static uint64_t SH_FLD_CL_FINE_DISABLE = 4441; // 4 +const static uint64_t SH_FLD_CL_FINE_DISABLE_LEN = 4442; // 4 +const static uint64_t SH_FLD_CL_FSM = 4443; // 43 +const static uint64_t SH_FLD_CL_GLOBAL_DISABLE = 4444; // 4 +const static uint64_t SH_FLD_CL_GLOBAL_DISABLE_LEN = 4445; // 4 +const static uint64_t SH_FLD_CL_LEN = 4446; // 1 +const static uint64_t SH_FLD_CL_PROBE_PB_HANG = 4447; // 2 +const static uint64_t SH_FLD_CL_TIMEOUT_SEL = 4448; // 4 +const static uint64_t SH_FLD_CL_TIMEOUT_SEL_LEN = 4449; // 4 +const static uint64_t SH_FLD_CMD = 4450; // 43 +const static uint64_t SH_FLD_CMDREG_BROADCAST_FLAG = 4451; // 1 +const static uint64_t SH_FLD_CMDREG_SCAN_ADDRESS = 4452; // 1 +const static uint64_t SH_FLD_CMDREG_SCAN_ADDRESS_LEN = 4453; // 1 +const static uint64_t SH_FLD_CMDREG_SCAN_REGION = 4454; // 1 +const static uint64_t SH_FLD_CMDREG_SCAN_REGION_LEN = 4455; // 1 +const static uint64_t SH_FLD_CMDREG_SCAN_TYPE = 4456; // 1 +const static uint64_t SH_FLD_CMDREG_SCAN_TYPE_LEN = 4457; // 1 +const static uint64_t SH_FLD_CMDREG_WRITE_FLAG = 4458; // 1 +const static uint64_t SH_FLD_CMD_BUFFER_PAR_ERR = 4459; // 4 +const static uint64_t SH_FLD_CMD_COUNT_ERR = 4460; // 1 +const static uint64_t SH_FLD_CMD_EXP_TIME = 4461; // 7 +const static uint64_t SH_FLD_CMD_EXP_TIME_LEN = 4462; // 7 +const static uint64_t SH_FLD_CMD_IN_PROG = 4463; // 1 +const static uint64_t SH_FLD_CMD_LEN = 4464; // 43 +const static uint64_t SH_FLD_CMD_PARITY_ERROR = 4465; // 19 +const static uint64_t SH_FLD_CMD_PRECEDE_TIME = 4466; // 8 +const static uint64_t SH_FLD_CMD_PRECEDE_TIME_LEN = 4467; // 8 +const static uint64_t SH_FLD_CMD_QX_SEVERE_ERR = 4468; // 1 +const static uint64_t SH_FLD_CMD_REG = 4469; // 1 +const static uint64_t SH_FLD_CMD_REG_ADDR_1 = 4470; // 1 +const static uint64_t SH_FLD_CMD_REG_ADDR_1_LEN = 4471; // 1 +const static uint64_t SH_FLD_CMD_REG_ADDR_2 = 4472; // 1 +const static uint64_t SH_FLD_CMD_REG_ADDR_2_LEN = 4473; // 1 +const static uint64_t SH_FLD_CMD_REG_ADDR_3 = 4474; // 1 +const static uint64_t SH_FLD_CMD_REG_ADDR_3_LEN = 4475; // 1 +const static uint64_t SH_FLD_CMD_REG_ADDR_4 = 4476; // 1 +const static uint64_t SH_FLD_CMD_REG_ADDR_4_LEN = 4477; // 1 +const static uint64_t SH_FLD_CMD_REG_BIT_READCONT = 4478; // 1 +const static uint64_t SH_FLD_CMD_REG_BIT_RNW = 4479; // 1 +const static uint64_t SH_FLD_CMD_REG_BIT_WITHADDR = 4480; // 1 +const static uint64_t SH_FLD_CMD_REG_BIT_WITHSTART = 4481; // 1 +const static uint64_t SH_FLD_CMD_REG_BIT_WITHSTOP = 4482; // 1 +const static uint64_t SH_FLD_CMD_REG_LEN = 4483; // 1 +const static uint64_t SH_FLD_CMD_REG_LENGTH = 4484; // 1 +const static uint64_t SH_FLD_CMD_REG_LENGTH_LEN = 4485; // 1 +const static uint64_t SH_FLD_CMD_SCOPE = 4486; // 4 +const static uint64_t SH_FLD_CMD_SCOPE_LEN = 4487; // 4 +const static uint64_t SH_FLD_CMD_STATUS = 4488; // 1 +const static uint64_t SH_FLD_CMD_STATUS_LEN = 4489; // 1 +const static uint64_t SH_FLD_CME0_IVRM_DROPOUT = 4490; // 6 +const static uint64_t SH_FLD_CME1_IVRM_DROPOUT = 4491; // 6 +const static uint64_t SH_FLD_CME_ERROR_NOTIFY = 4492; // 1 +const static uint64_t SH_FLD_CME_ERR_NOTIFY_DIS = 4493; // 24 +const static uint64_t SH_FLD_CME_INTERPPM_ACLK_ENABLE = 4494; // 6 +const static uint64_t SH_FLD_CME_INTERPPM_ACLK_SEL = 4495; // 6 +const static uint64_t SH_FLD_CME_INTERPPM_DPLL_ENABLE = 4496; // 6 +const static uint64_t SH_FLD_CME_INTERPPM_DPLL_SEL = 4497; // 6 +const static uint64_t SH_FLD_CME_INTERPPM_IVRM_ENABLE = 4498; // 6 +const static uint64_t SH_FLD_CME_INTERPPM_IVRM_SEL = 4499; // 6 +const static uint64_t SH_FLD_CME_INTERPPM_VDATA_ENABLE = 4500; // 6 +const static uint64_t SH_FLD_CME_INTERPPM_VDATA_SEL = 4501; // 6 +const static uint64_t SH_FLD_CME_MESSAGE = 4502; // 24 +const static uint64_t SH_FLD_CME_MESSAGE_HI = 4503; // 48 +const static uint64_t SH_FLD_CME_MESSAGE_HI_LEN = 4504; // 48 +const static uint64_t SH_FLD_CME_MESSAGE_LEN = 4505; // 24 +const static uint64_t SH_FLD_CME_MESSAGE_NUMBER0 = 4506; // 24 +const static uint64_t SH_FLD_CME_MESSAGE_NUMBER0_LEN = 4507; // 24 +const static uint64_t SH_FLD_CME_MESSAGE_NUMBER_N = 4508; // 72 +const static uint64_t SH_FLD_CME_MESSAGE_NUMBER_N_LEN = 4509; // 72 +const static uint64_t SH_FLD_CME_REQUEST = 4510; // 96 +const static uint64_t SH_FLD_CME_SPECIAL_WKUP_DONE_DIS = 4511; // 24 +const static uint64_t SH_FLD_CMFSI_ACCESS_PROTCT = 4512; // 1 +const static uint64_t SH_FLD_CMLEN = 4513; // 10 +const static uint64_t SH_FLD_CMP_MSK_LT_B_64_TO_87 = 4514; // 90 +const static uint64_t SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN = 4515; // 90 +const static uint64_t SH_FLD_CMP_MSK_LT_B_TO_63 = 4516; // 90 +const static uint64_t SH_FLD_CMP_MSK_LT_B_TO_63_LEN = 4517; // 90 +const static uint64_t SH_FLD_CMSK = 4518; // 43 +const static uint64_t SH_FLD_CM_CFG = 4519; // 6 +const static uint64_t SH_FLD_CM_CFG_LEN = 4520; // 6 +const static uint64_t SH_FLD_CM_CNTL = 4521; // 120 +const static uint64_t SH_FLD_CM_CNTL_LEN = 4522; // 120 +const static uint64_t SH_FLD_CM_OFFSET_VAL = 4523; // 6 +const static uint64_t SH_FLD_CM_OFFSET_VAL_LEN = 4524; // 6 +const static uint64_t SH_FLD_CM_TIMEOUT = 4525; // 6 +const static uint64_t SH_FLD_CM_TIMEOUT_LEN = 4526; // 6 +const static uint64_t SH_FLD_CND_HWD_DOES_DEM_IVE = 4527; // 1 +const static uint64_t SH_FLD_CND_HWD_DOES_DEM_IVE_LEN = 4528; // 1 +const static uint64_t SH_FLD_CNT0 = 4529; // 1 +const static uint64_t SH_FLD_CNT0_BIT_PAIR_SEL = 4530; // 1 +const static uint64_t SH_FLD_CNT0_BIT_PAIR_SEL_LEN = 4531; // 1 +const static uint64_t SH_FLD_CNT0_ENABLE = 4532; // 1 +const static uint64_t SH_FLD_CNT0_EVENT_SEL = 4533; // 1 +const static uint64_t SH_FLD_CNT0_EVENT_SEL_LEN = 4534; // 1 +const static uint64_t SH_FLD_CNT0_LEN = 4535; // 1 +const static uint64_t SH_FLD_CNT0_MUX_SEL = 4536; // 2 +const static uint64_t SH_FLD_CNT0_MUX_SEL_LEN = 4537; // 2 +const static uint64_t SH_FLD_CNT0_PAIR_OP = 4538; // 2 +const static uint64_t SH_FLD_CNT0_PAIR_OP_LEN = 4539; // 2 +const static uint64_t SH_FLD_CNT0_POSEDGE_SEL = 4540; // 1 +const static uint64_t SH_FLD_CNT1 = 4541; // 1 +const static uint64_t SH_FLD_CNT1_BIT_PAIR_SEL = 4542; // 1 +const static uint64_t SH_FLD_CNT1_BIT_PAIR_SEL_LEN = 4543; // 1 +const static uint64_t SH_FLD_CNT1_ENABLE = 4544; // 1 +const static uint64_t SH_FLD_CNT1_EVENT_SEL = 4545; // 1 +const static uint64_t SH_FLD_CNT1_EVENT_SEL_LEN = 4546; // 1 +const static uint64_t SH_FLD_CNT1_LEN = 4547; // 1 +const static uint64_t SH_FLD_CNT1_MUX_SEL = 4548; // 2 +const static uint64_t SH_FLD_CNT1_MUX_SEL_LEN = 4549; // 2 +const static uint64_t SH_FLD_CNT1_PAIR_OP = 4550; // 2 +const static uint64_t SH_FLD_CNT1_PAIR_OP_LEN = 4551; // 2 +const static uint64_t SH_FLD_CNT1_POSEDGE_SEL = 4552; // 1 +const static uint64_t SH_FLD_CNT2 = 4553; // 1 +const static uint64_t SH_FLD_CNT2_BIT_PAIR_SEL = 4554; // 1 +const static uint64_t SH_FLD_CNT2_BIT_PAIR_SEL_LEN = 4555; // 1 +const static uint64_t SH_FLD_CNT2_ENABLE = 4556; // 1 +const static uint64_t SH_FLD_CNT2_EVENT_SEL = 4557; // 1 +const static uint64_t SH_FLD_CNT2_EVENT_SEL_LEN = 4558; // 1 +const static uint64_t SH_FLD_CNT2_LEN = 4559; // 1 +const static uint64_t SH_FLD_CNT2_MUX_SEL = 4560; // 2 +const static uint64_t SH_FLD_CNT2_MUX_SEL_LEN = 4561; // 2 +const static uint64_t SH_FLD_CNT2_PAIR_OP = 4562; // 2 +const static uint64_t SH_FLD_CNT2_PAIR_OP_LEN = 4563; // 2 +const static uint64_t SH_FLD_CNT2_POSEDGE_SEL = 4564; // 1 +const static uint64_t SH_FLD_CNT3 = 4565; // 1 +const static uint64_t SH_FLD_CNT3_BIT_PAIR_SEL = 4566; // 1 +const static uint64_t SH_FLD_CNT3_BIT_PAIR_SEL_LEN = 4567; // 1 +const static uint64_t SH_FLD_CNT3_ENABLE = 4568; // 1 +const static uint64_t SH_FLD_CNT3_EVENT_SEL = 4569; // 1 +const static uint64_t SH_FLD_CNT3_EVENT_SEL_LEN = 4570; // 1 +const static uint64_t SH_FLD_CNT3_LEN = 4571; // 1 +const static uint64_t SH_FLD_CNT3_MUX_SEL = 4572; // 2 +const static uint64_t SH_FLD_CNT3_MUX_SEL_LEN = 4573; // 2 +const static uint64_t SH_FLD_CNT3_PAIR_OP = 4574; // 2 +const static uint64_t SH_FLD_CNT3_PAIR_OP_LEN = 4575; // 2 +const static uint64_t SH_FLD_CNT3_POSEDGE_SEL = 4576; // 1 +const static uint64_t SH_FLD_CNTL = 4577; // 8 +const static uint64_t SH_FLD_CNTLS_PREV_LDED_GCRMSG = 4578; // 4 +const static uint64_t SH_FLD_CNTL_LEN = 4579; // 8 +const static uint64_t SH_FLD_CNT_BROADCAST = 4580; // 1 +const static uint64_t SH_FLD_CNT_BROADCAST_LEN = 4581; // 1 +const static uint64_t SH_FLD_CNT_CI_STORE_REPLAY = 4582; // 1 +const static uint64_t SH_FLD_CNT_CI_STORE_REPLAY_LEN = 4583; // 1 +const static uint64_t SH_FLD_CNT_DEM_CACHE_HIT = 4584; // 1 +const static uint64_t SH_FLD_CNT_DEM_CACHE_HIT_LEN = 4585; // 1 +const static uint64_t SH_FLD_CNT_DMA_RD = 4586; // 6 +const static uint64_t SH_FLD_CNT_DMA_RD_LEN = 4587; // 6 +const static uint64_t SH_FLD_CNT_DMA_WR = 4588; // 6 +const static uint64_t SH_FLD_CNT_DMA_WR_LEN = 4589; // 6 +const static uint64_t SH_FLD_CNT_EOI_CACHE_HIT = 4590; // 1 +const static uint64_t SH_FLD_CNT_EOI_CACHE_HIT_LEN = 4591; // 1 +const static uint64_t SH_FLD_CNT_EOI_RESP_REPLAY = 4592; // 2 +const static uint64_t SH_FLD_CNT_EOI_RESP_REPLAY_LEN = 4593; // 2 +const static uint64_t SH_FLD_CNT_EQC_COMMAND = 4594; // 1 +const static uint64_t SH_FLD_CNT_EQC_COMMAND_LEN = 4595; // 1 +const static uint64_t SH_FLD_CNT_EQD_FETCH = 4596; // 1 +const static uint64_t SH_FLD_CNT_EQD_FETCH_LEN = 4597; // 1 +const static uint64_t SH_FLD_CNT_EQD_FETCH_REPLAY = 4598; // 1 +const static uint64_t SH_FLD_CNT_EQD_FETCH_REPLAY_LEN = 4599; // 1 +const static uint64_t SH_FLD_CNT_EQP = 4600; // 1 +const static uint64_t SH_FLD_CNT_EQP_LEN = 4601; // 1 +const static uint64_t SH_FLD_CNT_EQP_REPLAY = 4602; // 1 +const static uint64_t SH_FLD_CNT_EQP_REPLAY_LEN = 4603; // 1 +const static uint64_t SH_FLD_CNT_EQ_FWD = 4604; // 1 +const static uint64_t SH_FLD_CNT_EQ_FWD_LEN = 4605; // 1 +const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC = 4606; // 1 +const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC_LEN = 4607; // 1 +const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC = 4608; // 1 +const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC_LEN = 4609; // 1 +const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_HWD = 4610; // 1 +const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_HWD_LEN = 4611; // 1 +const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_IPI = 4612; // 1 +const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_IPI_LEN = 4613; // 1 +const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS = 4614; // 1 +const static uint64_t SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS_LEN = 4615; // 1 +const static uint64_t SH_FLD_CNT_EQ_TRIG_CACHE_HIT = 4616; // 1 +const static uint64_t SH_FLD_CNT_EQ_TRIG_CACHE_HIT_LEN = 4617; // 1 +const static uint64_t SH_FLD_CNT_ESCALATE = 4618; // 1 +const static uint64_t SH_FLD_CNT_ESCALATE_LEN = 4619; // 1 +const static uint64_t SH_FLD_CNT_FIFO_FULL = 4620; // 6 +const static uint64_t SH_FLD_CNT_FIFO_FULL_LEN = 4621; // 6 +const static uint64_t SH_FLD_CNT_GROUP = 4622; // 1 +const static uint64_t SH_FLD_CNT_GROUP_LEN = 4623; // 1 +const static uint64_t SH_FLD_CNT_GROUP_SCAN_CACHE_HIT = 4624; // 1 +const static uint64_t SH_FLD_CNT_GROUP_SCAN_CACHE_HIT_LEN = 4625; // 1 +const static uint64_t SH_FLD_CNT_HWD_DOES_PRF_IVE = 4626; // 1 +const static uint64_t SH_FLD_CNT_HWD_DOES_PRF_IVE_LEN = 4627; // 1 +const static uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE = 4628; // 1 +const static uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_LEN = 4629; // 1 +const static uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC = 4630; // 1 +const static uint64_t SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC_LEN = 4631; // 1 +const static uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE = 4632; // 1 +const static uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_LEN = 4633; // 1 +const static uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC = 4634; // 1 +const static uint64_t SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC_LEN = 4635; // 1 +const static uint64_t SH_FLD_CNT_ISB_FETCH = 4636; // 1 +const static uint64_t SH_FLD_CNT_ISB_FETCH_LEN = 4637; // 1 +const static uint64_t SH_FLD_CNT_ISB_FETCH_REPLAY = 4638; // 1 +const static uint64_t SH_FLD_CNT_ISB_FETCH_REPLAY_LEN = 4639; // 1 +const static uint64_t SH_FLD_CNT_ISB_WRITE = 4640; // 1 +const static uint64_t SH_FLD_CNT_ISB_WRITE_LEN = 4641; // 1 +const static uint64_t SH_FLD_CNT_IVC_DEMAND = 4642; // 1 +const static uint64_t SH_FLD_CNT_IVC_DEMAND_LEN = 4643; // 1 +const static uint64_t SH_FLD_CNT_IVC_PRF = 4644; // 1 +const static uint64_t SH_FLD_CNT_IVC_PRF_LEN = 4645; // 1 +const static uint64_t SH_FLD_CNT_IVC_RESP_REPLAY = 4646; // 1 +const static uint64_t SH_FLD_CNT_IVC_RESP_REPLAY_LEN = 4647; // 1 +const static uint64_t SH_FLD_CNT_IVE_FETCH = 4648; // 1 +const static uint64_t SH_FLD_CNT_IVE_FETCH_LEN = 4649; // 1 +const static uint64_t SH_FLD_CNT_IVE_FETCH_REPLAY = 4650; // 1 +const static uint64_t SH_FLD_CNT_IVE_FETCH_REPLAY_LEN = 4651; // 1 +const static uint64_t SH_FLD_CNT_IVVC_RESP = 4652; // 1 +const static uint64_t SH_FLD_CNT_IVVC_RESP_LEN = 4653; // 1 +const static uint64_t SH_FLD_CNT_LCL_GRPSCAN_REPLAY = 4654; // 1 +const static uint64_t SH_FLD_CNT_LCL_GRPSCAN_REPLAY_LEN = 4655; // 1 +const static uint64_t SH_FLD_CNT_LCL_PRESS_RELIEF = 4656; // 1 +const static uint64_t SH_FLD_CNT_LCL_PRESS_RELIEF_LEN = 4657; // 1 +const static uint64_t SH_FLD_CNT_LCL_REDIST = 4658; // 1 +const static uint64_t SH_FLD_CNT_LCL_REDIST_LEN = 4659; // 1 +const static uint64_t SH_FLD_CNT_LD_CACHE_HIT = 4660; // 1 +const static uint64_t SH_FLD_CNT_LD_CACHE_HIT_LEN = 4661; // 1 +const static uint64_t SH_FLD_CNT_LD_REQ_REPLAY = 4662; // 1 +const static uint64_t SH_FLD_CNT_LD_REQ_REPLAY_LEN = 4663; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_ESCALATE = 4664; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_ESCALATE_LEN = 4665; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_ESC_CACHE_HIT = 4666; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_ESC_CACHE_HIT_LEN = 4667; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_ESC_REPLAY = 4668; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_ESC_REPLAY_LEN = 4669; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_GROUP_SCAN = 4670; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_GROUP_SCAN_LEN = 4671; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_SBC_REPLAY = 4672; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_SBC_REPLAY_LEN = 4673; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_SBC_UPD = 4674; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_SBC_UPD_LEN = 4675; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_VPC_REPLAY = 4676; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_VPC_REPLAY_LEN = 4677; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_VPC_UPD = 4678; // 1 +const static uint64_t SH_FLD_CNT_LOCAL_VPC_UPD_LEN = 4679; // 1 +const static uint64_t SH_FLD_CNT_LS = 4680; // 1 +const static uint64_t SH_FLD_CNT_LS_LEN = 4681; // 1 +const static uint64_t SH_FLD_CNT_NEW_CMD_STALLED = 4682; // 1 +const static uint64_t SH_FLD_CNT_NEW_CMD_STALLED_LEN = 4683; // 1 +const static uint64_t SH_FLD_CNT_NON_SPEC_EOI = 4684; // 1 +const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_LEN = 4685; // 1 +const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED = 4686; // 1 +const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED_LEN = 4687; // 1 +const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_OWNED = 4688; // 1 +const static uint64_t SH_FLD_CNT_NON_SPEC_EOI_OWNED_LEN = 4689; // 1 +const static uint64_t SH_FLD_CNT_NON_SPEC_LOAD = 4690; // 1 +const static uint64_t SH_FLD_CNT_NON_SPEC_LOAD_LEN = 4691; // 1 +const static uint64_t SH_FLD_CNT_NON_SPEC_SW_LOAD = 4692; // 1 +const static uint64_t SH_FLD_CNT_NON_SPEC_SW_LOAD_LEN = 4693; // 1 +const static uint64_t SH_FLD_CNT_NON_SPEC_VC_LOAD = 4694; // 1 +const static uint64_t SH_FLD_CNT_NON_SPEC_VC_LOAD_LEN = 4695; // 1 +const static uint64_t SH_FLD_CNT_OTHER_CACHE_HIT = 4696; // 1 +const static uint64_t SH_FLD_CNT_OTHER_CACHE_HIT_LEN = 4697; // 1 +const static uint64_t SH_FLD_CNT_PRF_CACHE_HIT = 4698; // 2 +const static uint64_t SH_FLD_CNT_PRF_CACHE_HIT_LEN = 4699; // 2 +const static uint64_t SH_FLD_CNT_R0 = 4700; // 3 +const static uint64_t SH_FLD_CNT_R0_LEN = 4701; // 3 +const static uint64_t SH_FLD_CNT_R10R = 4702; // 3 +const static uint64_t SH_FLD_CNT_R10R_LEN = 4703; // 3 +const static uint64_t SH_FLD_CNT_R10W = 4704; // 3 +const static uint64_t SH_FLD_CNT_R10W_LEN = 4705; // 3 +const static uint64_t SH_FLD_CNT_R1R = 4706; // 3 +const static uint64_t SH_FLD_CNT_R1R_LEN = 4707; // 3 +const static uint64_t SH_FLD_CNT_R1W = 4708; // 3 +const static uint64_t SH_FLD_CNT_R1W_LEN = 4709; // 3 +const static uint64_t SH_FLD_CNT_R2 = 4710; // 3 +const static uint64_t SH_FLD_CNT_R2_LEN = 4711; // 3 +const static uint64_t SH_FLD_CNT_R3 = 4712; // 3 +const static uint64_t SH_FLD_CNT_R3_LEN = 4713; // 3 +const static uint64_t SH_FLD_CNT_R4 = 4714; // 3 +const static uint64_t SH_FLD_CNT_R4_LEN = 4715; // 3 +const static uint64_t SH_FLD_CNT_R5R = 4716; // 3 +const static uint64_t SH_FLD_CNT_R5R_LEN = 4717; // 3 +const static uint64_t SH_FLD_CNT_R5W = 4718; // 3 +const static uint64_t SH_FLD_CNT_R5W_LEN = 4719; // 3 +const static uint64_t SH_FLD_CNT_R6 = 4720; // 3 +const static uint64_t SH_FLD_CNT_R6_LEN = 4721; // 3 +const static uint64_t SH_FLD_CNT_R7EQP = 4722; // 3 +const static uint64_t SH_FLD_CNT_R7EQP_LEN = 4723; // 3 +const static uint64_t SH_FLD_CNT_R7INT = 4724; // 3 +const static uint64_t SH_FLD_CNT_R7INT_LEN = 4725; // 3 +const static uint64_t SH_FLD_CNT_R7RSP = 4726; // 3 +const static uint64_t SH_FLD_CNT_R7RSP_LEN = 4727; // 3 +const static uint64_t SH_FLD_CNT_R8 = 4728; // 3 +const static uint64_t SH_FLD_CNT_R8_LEN = 4729; // 3 +const static uint64_t SH_FLD_CNT_R9 = 4730; // 3 +const static uint64_t SH_FLD_CNT_R9_LEN = 4731; // 3 +const static uint64_t SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY = 4732; // 1 +const static uint64_t SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY_LEN = 4733; // 1 +const static uint64_t SH_FLD_CNT_REMOTE_SBC_UPD = 4734; // 1 +const static uint64_t SH_FLD_CNT_REMOTE_SBC_UPD_LEN = 4735; // 1 +const static uint64_t SH_FLD_CNT_REMOTE_VPC_UPD = 4736; // 1 +const static uint64_t SH_FLD_CNT_REMOTE_VPC_UPD_LEN = 4737; // 1 +const static uint64_t SH_FLD_CNT_REPLAY = 4738; // 1 +const static uint64_t SH_FLD_CNT_REPLAY_LEN = 4739; // 1 +const static uint64_t SH_FLD_CNT_RETRY = 4740; // 3 +const static uint64_t SH_FLD_CNT_RETRY_LEN = 4741; // 3 +const static uint64_t SH_FLD_CNT_RMT_PULL_1STGRP = 4742; // 1 +const static uint64_t SH_FLD_CNT_RMT_PULL_1STGRP_LEN = 4743; // 1 +const static uint64_t SH_FLD_CNT_RMT_PULL_1STVP = 4744; // 1 +const static uint64_t SH_FLD_CNT_RMT_PULL_1STVP_LEN = 4745; // 1 +const static uint64_t SH_FLD_CNT_RMT_PULL_GRP = 4746; // 1 +const static uint64_t SH_FLD_CNT_RMT_PULL_GRP_LEN = 4747; // 1 +const static uint64_t SH_FLD_CNT_RMT_PULL_VP = 4748; // 1 +const static uint64_t SH_FLD_CNT_RMT_PULL_VP_LEN = 4749; // 1 +const static uint64_t SH_FLD_CNT_RMT_PUSH = 4750; // 1 +const static uint64_t SH_FLD_CNT_RMT_PUSH_LEN = 4751; // 1 +const static uint64_t SH_FLD_CNT_RMT_PUSH_VC = 4752; // 1 +const static uint64_t SH_FLD_CNT_RMT_PUSH_VC_LEN = 4753; // 1 +const static uint64_t SH_FLD_CNT_RSP_ATX_REPLAY = 4754; // 1 +const static uint64_t SH_FLD_CNT_RSP_ATX_REPLAY_LEN = 4755; // 1 +const static uint64_t SH_FLD_CNT_RSP_LCL_TCTXT = 4756; // 1 +const static uint64_t SH_FLD_CNT_RSP_LCL_TCTXT_LEN = 4757; // 1 +const static uint64_t SH_FLD_CNT_RSP_LCL_VC = 4758; // 1 +const static uint64_t SH_FLD_CNT_RSP_LCL_VC_LEN = 4759; // 1 +const static uint64_t SH_FLD_CNT_RSP_RMT = 4760; // 1 +const static uint64_t SH_FLD_CNT_RSP_RMT_LEN = 4761; // 1 +const static uint64_t SH_FLD_CNT_RSP_RMT_VC = 4762; // 1 +const static uint64_t SH_FLD_CNT_RSP_RMT_VC_LEN = 4763; // 1 +const static uint64_t SH_FLD_CNT_RSP_SW_LD = 4764; // 1 +const static uint64_t SH_FLD_CNT_RSP_SW_LD_LEN = 4765; // 1 +const static uint64_t SH_FLD_CNT_RSP_TCTXT_REPLAY = 4766; // 1 +const static uint64_t SH_FLD_CNT_RSP_TCTXT_REPLAY_LEN = 4767; // 1 +const static uint64_t SH_FLD_CNT_SAME_VPD_REPLAY = 4768; // 1 +const static uint64_t SH_FLD_CNT_SAME_VPD_REPLAY_LEN = 4769; // 1 +const static uint64_t SH_FLD_CNT_SBC_LOOKUP = 4770; // 1 +const static uint64_t SH_FLD_CNT_SBC_LOOKUP_LEN = 4771; // 1 +const static uint64_t SH_FLD_CNT_SBC_LOOKUP_REPLAY = 4772; // 1 +const static uint64_t SH_FLD_CNT_SBC_LOOKUP_REPLAY_LEN = 4773; // 1 +const static uint64_t SH_FLD_CNT_SPEC_EOI = 4774; // 1 +const static uint64_t SH_FLD_CNT_SPEC_EOI_CACHE_HIT = 4775; // 1 +const static uint64_t SH_FLD_CNT_SPEC_EOI_CACHE_HIT_LEN = 4776; // 1 +const static uint64_t SH_FLD_CNT_SPEC_EOI_LEN = 4777; // 1 +const static uint64_t SH_FLD_CNT_ST_LCL_REPLAY = 4778; // 1 +const static uint64_t SH_FLD_CNT_ST_LCL_REPLAY_LEN = 4779; // 1 +const static uint64_t SH_FLD_CNT_ST_RMT_REPLAY = 4780; // 1 +const static uint64_t SH_FLD_CNT_ST_RMT_REPLAY_LEN = 4781; // 1 +const static uint64_t SH_FLD_CNT_ST_RMT_VC_REPLAY = 4782; // 1 +const static uint64_t SH_FLD_CNT_ST_RMT_VC_REPLAY_LEN = 4783; // 1 +const static uint64_t SH_FLD_CNT_TOO_MANY_ENTRIES = 4784; // 3 +const static uint64_t SH_FLD_CNT_TOO_MANY_ENTRIES_LEN = 4785; // 3 +const static uint64_t SH_FLD_CNT_TRIG_DROPPED = 4786; // 6 +const static uint64_t SH_FLD_CNT_TRIG_DROPPED_LEN = 4787; // 6 +const static uint64_t SH_FLD_CNT_TRIG_FROM_AIB = 4788; // 6 +const static uint64_t SH_FLD_CNT_TRIG_FROM_AIB_LEN = 4789; // 6 +const static uint64_t SH_FLD_CNT_TRIG_FWD_TO_EQC = 4790; // 6 +const static uint64_t SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN = 4791; // 6 +const static uint64_t SH_FLD_CNT_USE_L2_DIVIDER_EN = 4792; // 12 +const static uint64_t SH_FLD_CNT_VICTIM_IS_1ST_USABLE = 4793; // 2 +const static uint64_t SH_FLD_CNT_VICTIM_IS_1ST_USABLE_LEN = 4794; // 2 +const static uint64_t SH_FLD_CNT_VICTIM_IS_FIRST_USABLE = 4795; // 2 +const static uint64_t SH_FLD_CNT_VICTIM_IS_FIRST_USABLE_LEN = 4796; // 2 +const static uint64_t SH_FLD_CNT_VICTIM_IS_LRU = 4797; // 4 +const static uint64_t SH_FLD_CNT_VICTIM_IS_LRU_LEN = 4798; // 4 +const static uint64_t SH_FLD_CNT_VP = 4799; // 1 +const static uint64_t SH_FLD_CNT_VPD_FETCH = 4800; // 1 +const static uint64_t SH_FLD_CNT_VPD_FETCH_LEN = 4801; // 1 +const static uint64_t SH_FLD_CNT_VPD_FETCH_REPLAY = 4802; // 1 +const static uint64_t SH_FLD_CNT_VPD_FETCH_REPLAY_LEN = 4803; // 1 +const static uint64_t SH_FLD_CNT_VPD_WB = 4804; // 1 +const static uint64_t SH_FLD_CNT_VPD_WB_LEN = 4805; // 1 +const static uint64_t SH_FLD_CNT_VP_LEN = 4806; // 1 +const static uint64_t SH_FLD_CNT_VRQ_CACHE_HIT = 4807; // 1 +const static uint64_t SH_FLD_CNT_VRQ_CACHE_HIT_LEN = 4808; // 1 +const static uint64_t SH_FLD_CNT_VRQ_PULL = 4809; // 1 +const static uint64_t SH_FLD_CNT_VRQ_PULL_LEN = 4810; // 1 +const static uint64_t SH_FLD_CNT_VRQ_PUSH_LOCAL = 4811; // 1 +const static uint64_t SH_FLD_CNT_VRQ_PUSH_LOCAL_LEN = 4812; // 1 +const static uint64_t SH_FLD_CNT_VRQ_PUSH_REMOTE = 4813; // 1 +const static uint64_t SH_FLD_CNT_VRQ_PUSH_REMOTE_LEN = 4814; // 1 +const static uint64_t SH_FLD_CNT_WAKEUP = 4815; // 1 +const static uint64_t SH_FLD_CNT_WAKEUP_LEN = 4816; // 1 +const static uint64_t SH_FLD_COARSE_CAL_STEP_SIZE = 4817; // 8 +const static uint64_t SH_FLD_COARSE_CAL_STEP_SIZE_LEN = 4818; // 8 +const static uint64_t SH_FLD_COARSE_DIR_ENABLE = 4819; // 2 +const static uint64_t SH_FLD_COARSE_DIR_SECTORS = 4820; // 2 +const static uint64_t SH_FLD_COARSE_RD = 4821; // 8 +const static uint64_t SH_FLD_COFSM_ADDR = 4822; // 12 +const static uint64_t SH_FLD_COHERENCY_ERROR = 4823; // 2 +const static uint64_t SH_FLD_COL4_BIT_MAP = 4824; // 8 +const static uint64_t SH_FLD_COL4_BIT_MAP_LEN = 4825; // 8 +const static uint64_t SH_FLD_COL5_BIT_MAP = 4826; // 8 +const static uint64_t SH_FLD_COL5_BIT_MAP_LEN = 4827; // 8 +const static uint64_t SH_FLD_COL6_BIT_MAP = 4828; // 8 +const static uint64_t SH_FLD_COL6_BIT_MAP_LEN = 4829; // 8 +const static uint64_t SH_FLD_COL7_BIT_MAP = 4830; // 8 +const static uint64_t SH_FLD_COL7_BIT_MAP_LEN = 4831; // 8 +const static uint64_t SH_FLD_COL8_BIT_MAP = 4832; // 8 +const static uint64_t SH_FLD_COL8_BIT_MAP_LEN = 4833; // 8 +const static uint64_t SH_FLD_COL9_BIT_MAP = 4834; // 8 +const static uint64_t SH_FLD_COL9_BIT_MAP_LEN = 4835; // 8 +const static uint64_t SH_FLD_COLLISION_MODES = 4836; // 4 +const static uint64_t SH_FLD_COLLISION_MODES_LEN = 4837; // 4 +const static uint64_t SH_FLD_COLLISON = 4838; // 1 +const static uint64_t SH_FLD_COMMAND_ADDRESS_TIMEOUT = 4839; // 2 +const static uint64_t SH_FLD_COMMAND_COMPLETE = 4840; // 1 +const static uint64_t SH_FLD_COMMAND_LIST_TIMEOUT = 4841; // 4 +const static uint64_t SH_FLD_COMMON_CLK_SB_PULSE_MODE = 4842; // 6 +const static uint64_t SH_FLD_COMMON_CLK_SB_PULSE_MODE_EN = 4843; // 6 +const static uint64_t SH_FLD_COMMON_CLK_SB_PULSE_MODE_LEN = 4844; // 6 +const static uint64_t SH_FLD_COMMON_CLK_SB_SPARE = 4845; // 6 +const static uint64_t SH_FLD_COMMON_CLK_SB_STRENGTH = 4846; // 6 +const static uint64_t SH_FLD_COMMON_CLK_SB_STRENGTH_LEN = 4847; // 6 +const static uint64_t SH_FLD_COMMON_CLK_SW_RESCLK = 4848; // 6 +const static uint64_t SH_FLD_COMMON_CLK_SW_RESCLK_LEN = 4849; // 6 +const static uint64_t SH_FLD_COMMON_CLK_SW_SPARE = 4850; // 6 +const static uint64_t SH_FLD_COMMON_FREEZE_MODE = 4851; // 2 +const static uint64_t SH_FLD_COMM_ACK = 4852; // 12 +const static uint64_t SH_FLD_COMM_NACK = 4853; // 12 +const static uint64_t SH_FLD_COMM_RECV = 4854; // 12 +const static uint64_t SH_FLD_COMM_RECVD = 4855; // 12 +const static uint64_t SH_FLD_COMM_RECV_LEN = 4856; // 12 +const static uint64_t SH_FLD_COMM_SEND = 4857; // 12 +const static uint64_t SH_FLD_COMM_SEND_ACK = 4858; // 12 +const static uint64_t SH_FLD_COMM_SEND_LEN = 4859; // 12 +const static uint64_t SH_FLD_COMM_SEND_NACK = 4860; // 12 +const static uint64_t SH_FLD_COMPLETE = 4861; // 8 +const static uint64_t SH_FLD_COMPLETE_LEN = 4862; // 8 +const static uint64_t SH_FLD_COMPLEX_FAULT_SAFE = 4863; // 1 +const static uint64_t SH_FLD_COMPLEX_FAULT_SAFE_MASK = 4864; // 1 +const static uint64_t SH_FLD_COMPRESSED_RSP_ENA = 4865; // 6 +const static uint64_t SH_FLD_COMP_CNT_LIMIT = 4866; // 24 +const static uint64_t SH_FLD_COMP_CNT_LIMIT_LEN = 4867; // 24 +const static uint64_t SH_FLD_COMP_MASK = 4868; // 4 +const static uint64_t SH_FLD_COMP_MASK_LEN = 4869; // 4 +const static uint64_t SH_FLD_COND1_SEL_A = 4870; // 86 +const static uint64_t SH_FLD_COND1_SEL_A_LEN = 4871; // 86 +const static uint64_t SH_FLD_COND1_SEL_B = 4872; // 86 +const static uint64_t SH_FLD_COND1_SEL_B_LEN = 4873; // 86 +const static uint64_t SH_FLD_COND2_SEL_A = 4874; // 86 +const static uint64_t SH_FLD_COND2_SEL_A_LEN = 4875; // 86 +const static uint64_t SH_FLD_COND2_SEL_B = 4876; // 86 +const static uint64_t SH_FLD_COND2_SEL_B_LEN = 4877; // 86 +const static uint64_t SH_FLD_COND3_ENABLE_RESET = 4878; // 86 +const static uint64_t SH_FLD_COND3_STATE_LT = 4879; // 43 +const static uint64_t SH_FLD_COND3_STATE_LT_LEN = 4880; // 43 +const static uint64_t SH_FLD_COND5_STATE_LT = 4881; // 43 +const static uint64_t SH_FLD_COND5_STATE_LT_LEN = 4882; // 43 +const static uint64_t SH_FLD_COND_STARTUP_TEST_FAIL = 4883; // 1 +const static uint64_t SH_FLD_CONFIG = 4884; // 1 +const static uint64_t SH_FLD_CONFIG1_RESERVED0 = 4885; // 3 +const static uint64_t SH_FLD_CONFIG1_RESERVED1 = 4886; // 15 +const static uint64_t SH_FLD_CONFIG1_RESERVED1_LEN = 4887; // 3 +const static uint64_t SH_FLD_CONFIG1_RESERVED2 = 4888; // 15 +const static uint64_t SH_FLD_CONFIG1_RESERVED2_LEN = 4889; // 3 +const static uint64_t SH_FLD_CONFIG_ADDR = 4890; // 36 +const static uint64_t SH_FLD_CONFIG_ADDR_LEN = 4891; // 36 +const static uint64_t SH_FLD_CONFIG_ADR_BAR_MODE = 4892; // 15 +const static uint64_t SH_FLD_CONFIG_ARB_NONCRR_SAFETY = 4893; // 12 +const static uint64_t SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN = 4894; // 12 +const static uint64_t SH_FLD_CONFIG_BRAZOS = 4895; // 1 +const static uint64_t SH_FLD_CONFIG_BRAZOS_MODE = 4896; // 15 +const static uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB = 4897; // 12 +const static uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN = 4898; // 12 +const static uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ = 4899; // 12 +const static uint64_t SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN = 4900; // 12 +const static uint64_t SH_FLD_CONFIG_DCACHE_MODE = 4901; // 12 +const static uint64_t SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL = 4902; // 12 +const static uint64_t SH_FLD_CONFIG_DISABLE_G = 4903; // 12 +const static uint64_t SH_FLD_CONFIG_DISABLE_INJECT = 4904; // 12 +const static uint64_t SH_FLD_CONFIG_DISABLE_LN = 4905; // 12 +const static uint64_t SH_FLD_CONFIG_DISABLE_NN_RN = 4906; // 12 +const static uint64_t SH_FLD_CONFIG_DISABLE_PBM_ECC_COR = 4907; // 3 +const static uint64_t SH_FLD_CONFIG_DISABLE_VG_NOT_SYS = 4908; // 12 +const static uint64_t SH_FLD_CONFIG_ENABLE = 4909; // 36 +const static uint64_t SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC = 4910; // 12 +const static uint64_t SH_FLD_CONFIG_ENABLE_PBUS = 4911; // 12 +const static uint64_t SH_FLD_CONFIG_ENABLE_SNARF_CPM = 4912; // 12 +const static uint64_t SH_FLD_CONFIG_EPSILON_WLN_COUNT = 4913; // 12 +const static uint64_t SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN = 4914; // 12 +const static uint64_t SH_FLD_CONFIG_EVAPORATE_BY_LCO = 4915; // 12 +const static uint64_t SH_FLD_CONFIG_GEN_HEAD_DELAY = 4916; // 3 +const static uint64_t SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN = 4917; // 3 +const static uint64_t SH_FLD_CONFIG_GPU0_ADDR = 4918; // 12 +const static uint64_t SH_FLD_CONFIG_GPU0_ADDR_LEN = 4919; // 12 +const static uint64_t SH_FLD_CONFIG_GPU0_ENABLE = 4920; // 12 +const static uint64_t SH_FLD_CONFIG_GPU0_GRANULE = 4921; // 12 +const static uint64_t SH_FLD_CONFIG_GPU0_MEMTYPE = 4922; // 12 +const static uint64_t SH_FLD_CONFIG_GPU0_MEMTYPE_LEN = 4923; // 12 +const static uint64_t SH_FLD_CONFIG_GPU0_MODE = 4924; // 12 +const static uint64_t SH_FLD_CONFIG_GPU0_MODE_LEN = 4925; // 12 +const static uint64_t SH_FLD_CONFIG_GPU0_RESERVED = 4926; // 12 +const static uint64_t SH_FLD_CONFIG_GPU0_RESERVED_LEN = 4927; // 12 +const static uint64_t SH_FLD_CONFIG_GPU0_SIZE = 4928; // 12 +const static uint64_t SH_FLD_CONFIG_GPU0_SIZE_LEN = 4929; // 12 +const static uint64_t SH_FLD_CONFIG_GPU1_ADDR = 4930; // 12 +const static uint64_t SH_FLD_CONFIG_GPU1_ADDR_LEN = 4931; // 12 +const static uint64_t SH_FLD_CONFIG_GPU1_ENABLE = 4932; // 12 +const static uint64_t SH_FLD_CONFIG_GPU1_GRANULE = 4933; // 12 +const static uint64_t SH_FLD_CONFIG_GPU1_MEMTYPE = 4934; // 12 +const static uint64_t SH_FLD_CONFIG_GPU1_MEMTYPE_LEN = 4935; // 12 +const static uint64_t SH_FLD_CONFIG_GPU1_MODE = 4936; // 12 +const static uint64_t SH_FLD_CONFIG_GPU1_MODE_LEN = 4937; // 12 +const static uint64_t SH_FLD_CONFIG_GPU1_RESERVED = 4938; // 12 +const static uint64_t SH_FLD_CONFIG_GPU1_RESERVED_LEN = 4939; // 12 +const static uint64_t SH_FLD_CONFIG_GPU1_SIZE = 4940; // 12 +const static uint64_t SH_FLD_CONFIG_GPU1_SIZE_LEN = 4941; // 12 +const static uint64_t SH_FLD_CONFIG_INC_PRI_MASK = 4942; // 12 +const static uint64_t SH_FLD_CONFIG_INC_PRI_MASK_LEN = 4943; // 12 +const static uint64_t SH_FLD_CONFIG_LEN = 4944; // 1 +const static uint64_t SH_FLD_CONFIG_MACH_CORRENAB = 4945; // 12 +const static uint64_t SH_FLD_CONFIG_MACH_INJECT_ENABLE1 = 4946; // 12 +const static uint64_t SH_FLD_CONFIG_MACH_INJECT_ENABLE2 = 4947; // 12 +const static uint64_t SH_FLD_CONFIG_MAX_MACHINES = 4948; // 12 +const static uint64_t SH_FLD_CONFIG_MAX_MACHINES_LEN = 4949; // 12 +const static uint64_t SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR = 4950; // 12 +const static uint64_t SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG = 4951; // 12 +const static uint64_t SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR = 4952; // 12 +const static uint64_t SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE = 4953; // 12 +const static uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA = 4954; // 12 +const static uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ = 4955; // 12 +const static uint64_t SH_FLD_CONFIG_MA_MCRESP_OPT_WRP = 4956; // 12 +const static uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_B = 4957; // 12 +const static uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_C = 4958; // 12 +const static uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM = 4959; // 12 +const static uint64_t SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN = 4960; // 12 +const static uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_A = 4961; // 12 +const static uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_B = 4962; // 12 +const static uint64_t SH_FLD_CONFIG_MA_SCRESP_OPT_C = 4963; // 12 +const static uint64_t SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ = 4964; // 3 +const static uint64_t SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ = 4965; // 3 +const static uint64_t SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP = 4966; // 3 +const static uint64_t SH_FLD_CONFIG_MRBGP_MAX_LEVEL = 4967; // 3 +const static uint64_t SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN = 4968; // 3 +const static uint64_t SH_FLD_CONFIG_MRBGP_THRESH1 = 4969; // 3 +const static uint64_t SH_FLD_CONFIG_MRBGP_THRESH1_LEN = 4970; // 3 +const static uint64_t SH_FLD_CONFIG_MRBGP_THRESH2 = 4971; // 3 +const static uint64_t SH_FLD_CONFIG_MRBGP_THRESH2_LEN = 4972; // 3 +const static uint64_t SH_FLD_CONFIG_MRBGP_TRACK_ALL = 4973; // 12 +const static uint64_t SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ = 4974; // 3 +const static uint64_t SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ = 4975; // 3 +const static uint64_t SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP = 4976; // 3 +const static uint64_t SH_FLD_CONFIG_MRBSP_MAX_LEVEL = 4977; // 3 +const static uint64_t SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN = 4978; // 3 +const static uint64_t SH_FLD_CONFIG_MRBSP_THRESH1 = 4979; // 3 +const static uint64_t SH_FLD_CONFIG_MRBSP_THRESH1_LEN = 4980; // 3 +const static uint64_t SH_FLD_CONFIG_MRBSP_THRESH2 = 4981; // 3 +const static uint64_t SH_FLD_CONFIG_MRBSP_THRESH2_LEN = 4982; // 3 +const static uint64_t SH_FLD_CONFIG_MRBSP_TRACK_ALL = 4983; // 12 +const static uint64_t SH_FLD_CONFIG_NDT0_ADDR = 4984; // 12 +const static uint64_t SH_FLD_CONFIG_NDT0_ADDR_LEN = 4985; // 12 +const static uint64_t SH_FLD_CONFIG_NDT0_ENABLE = 4986; // 12 +const static uint64_t SH_FLD_CONFIG_NDT1_ADDR = 4987; // 12 +const static uint64_t SH_FLD_CONFIG_NDT1_ADDR_LEN = 4988; // 12 +const static uint64_t SH_FLD_CONFIG_NDT1_ENABLE = 4989; // 12 +const static uint64_t SH_FLD_CONFIG_P9P9_MODE = 4990; // 12 +const static uint64_t SH_FLD_CONFIG_PARITY = 4991; // 43 +const static uint64_t SH_FLD_CONFIG_PCKT_BLK_PRB = 4992; // 12 +const static uint64_t SH_FLD_CONFIG_PRB0 = 4993; // 24 +const static uint64_t SH_FLD_CONFIG_PRB0_LEN = 4994; // 24 +const static uint64_t SH_FLD_CONFIG_PRB1 = 4995; // 24 +const static uint64_t SH_FLD_CONFIG_PRB1_LEN = 4996; // 24 +const static uint64_t SH_FLD_CONFIG_PREALLOC2_PRB0 = 4997; // 12 +const static uint64_t SH_FLD_CONFIG_PREALLOC2_PRB1 = 4998; // 12 +const static uint64_t SH_FLD_CONFIG_PREALLOC2_REQ0 = 4999; // 12 +const static uint64_t SH_FLD_CONFIG_PREALLOC2_REQ1 = 5000; // 12 +const static uint64_t SH_FLD_CONFIG_PREALLOC2_XATS = 5001; // 12 +const static uint64_t SH_FLD_CONFIG_PWR0 = 5002; // 24 +const static uint64_t SH_FLD_CONFIG_PWR0_LEN = 5003; // 24 +const static uint64_t SH_FLD_CONFIG_PWR1 = 5004; // 24 +const static uint64_t SH_FLD_CONFIG_PWR1_LEN = 5005; // 24 +const static uint64_t SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK = 5006; // 12 +const static uint64_t SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN = 5007; // 12 +const static uint64_t SH_FLD_CONFIG_REQ0 = 5008; // 24 +const static uint64_t SH_FLD_CONFIG_REQ0_LEN = 5009; // 24 +const static uint64_t SH_FLD_CONFIG_REQ1 = 5010; // 24 +const static uint64_t SH_FLD_CONFIG_REQ1_LEN = 5011; // 24 +const static uint64_t SH_FLD_CONFIG_RESERVED4 = 5012; // 12 +const static uint64_t SH_FLD_CONFIG_RSI_CORRENAB = 5013; // 12 +const static uint64_t SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH = 5014; // 12 +const static uint64_t SH_FLD_CONFIG_RSI_INJECT_ENABLE1 = 5015; // 12 +const static uint64_t SH_FLD_CONFIG_RSI_INJECT_ENABLE2 = 5016; // 12 +const static uint64_t SH_FLD_CONFIG_RXO_CORRENAB = 5017; // 12 +const static uint64_t SH_FLD_CONFIG_RXO_INJECT_ENABLE1 = 5018; // 12 +const static uint64_t SH_FLD_CONFIG_RXO_INJECT_ENABLE2 = 5019; // 12 +const static uint64_t SH_FLD_CONFIG_SKIP_G = 5020; // 12 +const static uint64_t SH_FLD_CONFIG_SYNC_WAIT = 5021; // 1 +const static uint64_t SH_FLD_CONFIG_SYNC_WAIT_LEN = 5022; // 1 +const static uint64_t SH_FLD_CONFIG_XATS = 5023; // 24 +const static uint64_t SH_FLD_CONFIG_XATS_LEN = 5024; // 24 +const static uint64_t SH_FLD_CONFIRMED = 5025; // 64 +const static uint64_t SH_FLD_CONFLICT = 5026; // 2 +const static uint64_t SH_FLD_CONG = 5027; // 1 +const static uint64_t SH_FLD_CONG_LEN = 5028; // 1 +const static uint64_t SH_FLD_CONSEQ_PASS = 5029; // 8 +const static uint64_t SH_FLD_CONSEQ_PASS_LEN = 5030; // 8 +const static uint64_t SH_FLD_CONSUMED_BUF_COUNT = 5031; // 1 +const static uint64_t SH_FLD_CONSUMED_BUF_COUNT_LEN = 5032; // 1 +const static uint64_t SH_FLD_CONTENT = 5033; // 3 +const static uint64_t SH_FLD_CONTENT_LEN = 5034; // 3 +const static uint64_t SH_FLD_CONTINUOUS = 5035; // 2 +const static uint64_t SH_FLD_CONTROL = 5036; // 15 +const static uint64_t SH_FLD_CONTROL_ERR = 5037; // 12 +const static uint64_t SH_FLD_CONTROL_LEN = 5038; // 15 +const static uint64_t SH_FLD_CONTROL_N = 5039; // 2 +const static uint64_t SH_FLD_CONVERGED_END_COUNT = 5040; // 6 +const static uint64_t SH_FLD_CONVERGED_END_COUNT_LEN = 5041; // 6 +const static uint64_t SH_FLD_COPY_CKE_TO_SPARE_CKE = 5042; // 2 +const static uint64_t SH_FLD_COPY_LENGTH = 5043; // 2 +const static uint64_t SH_FLD_COPY_LENGTH_LEN = 5044; // 2 +const static uint64_t SH_FLD_CORE0_REQ_ACTIVE = 5045; // 12 +const static uint64_t SH_FLD_CORE1_REQ_ACTIVE = 5046; // 12 +const static uint64_t SH_FLD_COREID = 5047; // 1 +const static uint64_t SH_FLD_COREID_LEN = 5048; // 1 +const static uint64_t SH_FLD_CORES_ENABLED_0_23 = 5049; // 1 +const static uint64_t SH_FLD_CORES_ENABLED_0_23_LEN = 5050; // 1 +const static uint64_t SH_FLD_CORE_CHECKSTOP = 5051; // 12 +const static uint64_t SH_FLD_CORE_CONFIG = 5052; // 2 +const static uint64_t SH_FLD_CORE_CONFIG_LEN = 5053; // 2 +const static uint64_t SH_FLD_CORE_EXT_INTR = 5054; // 1 +const static uint64_t SH_FLD_CORE_LIMIT = 5055; // 24 +const static uint64_t SH_FLD_CORE_LIMIT_LEN = 5056; // 24 +const static uint64_t SH_FLD_CORE_OR_SNP_REQ_ACTIVE = 5057; // 12 +const static uint64_t SH_FLD_CORE_RAS0_TRIG_SEL = 5058; // 43 +const static uint64_t SH_FLD_CORE_RAS0_TRIG_SEL_LEN = 5059; // 43 +const static uint64_t SH_FLD_CORE_RAS1_TRIG_SEL = 5060; // 43 +const static uint64_t SH_FLD_CORE_RAS1_TRIG_SEL_LEN = 5061; // 43 +const static uint64_t SH_FLD_CORE_RESET = 5062; // 1 +const static uint64_t SH_FLD_CORE_STEP = 5063; // 1 +const static uint64_t SH_FLD_CORE_STEP_SYNC_TX_ENABLE = 5064; // 1 +const static uint64_t SH_FLD_CORE_STEP_SYNC_TX_SYNC_DISABLE = 5065; // 1 +const static uint64_t SH_FLD_CORE_STEP_SYNC_TX_TRIGGER = 5066; // 1 +const static uint64_t SH_FLD_CORR_DIS_BR = 5067; // 3 +const static uint64_t SH_FLD_CORR_DIS_IR = 5068; // 3 +const static uint64_t SH_FLD_CORR_DIS_OR = 5069; // 3 +const static uint64_t SH_FLD_CORR_DIS_PR = 5070; // 3 +const static uint64_t SH_FLD_CORR_DIS_PT = 5071; // 3 +const static uint64_t SH_FLD_CORR_ERR = 5072; // 1 +const static uint64_t SH_FLD_COUNT = 5073; // 44 +const static uint64_t SH_FLD_COUNTER = 5074; // 43 +const static uint64_t SH_FLD_COUNTER0 = 5075; // 16 +const static uint64_t SH_FLD_COUNTER0_LEN = 5076; // 16 +const static uint64_t SH_FLD_COUNTER1 = 5077; // 16 +const static uint64_t SH_FLD_COUNTER1_LEN = 5078; // 16 +const static uint64_t SH_FLD_COUNTER2 = 5079; // 16 +const static uint64_t SH_FLD_COUNTER2_LEN = 5080; // 16 +const static uint64_t SH_FLD_COUNTER3 = 5081; // 16 +const static uint64_t SH_FLD_COUNTER3_LEN = 5082; // 16 +const static uint64_t SH_FLD_COUNTERA_0 = 5083; // 2 +const static uint64_t SH_FLD_COUNTERA_0_LEN = 5084; // 2 +const static uint64_t SH_FLD_COUNTERA_1 = 5085; // 2 +const static uint64_t SH_FLD_COUNTERA_1_LEN = 5086; // 2 +const static uint64_t SH_FLD_COUNTERA_2 = 5087; // 2 +const static uint64_t SH_FLD_COUNTERA_2_LEN = 5088; // 2 +const static uint64_t SH_FLD_COUNTERA_3 = 5089; // 2 +const static uint64_t SH_FLD_COUNTERA_3_LEN = 5090; // 2 +const static uint64_t SH_FLD_COUNTERB_0 = 5091; // 2 +const static uint64_t SH_FLD_COUNTERB_0_LEN = 5092; // 2 +const static uint64_t SH_FLD_COUNTERB_1 = 5093; // 2 +const static uint64_t SH_FLD_COUNTERB_1_LEN = 5094; // 2 +const static uint64_t SH_FLD_COUNTERB_2 = 5095; // 2 +const static uint64_t SH_FLD_COUNTERB_2_LEN = 5096; // 2 +const static uint64_t SH_FLD_COUNTERB_3 = 5097; // 2 +const static uint64_t SH_FLD_COUNTERB_3_LEN = 5098; // 2 +const static uint64_t SH_FLD_COUNTER_LEN = 5099; // 43 +const static uint64_t SH_FLD_COUNTER_LOAD_FLAG = 5100; // 2 +const static uint64_t SH_FLD_COUNTER_LOAD_VALUE = 5101; // 2 +const static uint64_t SH_FLD_COUNTER_LOAD_VALUE_LEN = 5102; // 2 +const static uint64_t SH_FLD_COUNTER_VALUE = 5103; // 1 +const static uint64_t SH_FLD_COUNTER_VALUE_LEN = 5104; // 1 +const static uint64_t SH_FLD_COUNT_0_47 = 5105; // 7 +const static uint64_t SH_FLD_COUNT_0_47_LEN = 5106; // 7 +const static uint64_t SH_FLD_COUNT_47 = 5107; // 1 +const static uint64_t SH_FLD_COUNT_47_LEN = 5108; // 1 +const static uint64_t SH_FLD_COUNT_LEN = 5109; // 44 +const static uint64_t SH_FLD_COUNT_STATE_MASK = 5110; // 43 +const static uint64_t SH_FLD_COURSE_DIR_FLUSH_FAILED = 5111; // 2 +const static uint64_t SH_FLD_CO_CRESP_ACK_DEAD = 5112; // 12 +const static uint64_t SH_FLD_CO_MACHINE_HANG = 5113; // 12 +const static uint64_t SH_FLD_CO_PROT_ERR_CHK_DIS = 5114; // 1 +const static uint64_t SH_FLD_CO_PSH_RECEIVED_PB_CRESP_ADR_ERR = 5115; // 12 +const static uint64_t SH_FLD_CO_TIMEOUT_CHK_DIS = 5116; // 1 +const static uint64_t SH_FLD_CO_UNSOLICITED_CRESP = 5117; // 12 +const static uint64_t SH_FLD_CP = 5118; // 2 +const static uint64_t SH_FLD_CPG = 5119; // 8 +const static uint64_t SH_FLD_CPHA = 5120; // 1 +const static uint64_t SH_FLD_CPISEL = 5121; // 20 +const static uint64_t SH_FLD_CPISEL_LEN = 5122; // 20 +const static uint64_t SH_FLD_CPI_TYPE = 5123; // 12 +const static uint64_t SH_FLD_CPI_TYPE_LEN = 5124; // 12 +const static uint64_t SH_FLD_CPLITE = 5125; // 2 +const static uint64_t SH_FLD_CPLITE_LEN = 5126; // 2 +const static uint64_t SH_FLD_CPLTMASK0 = 5127; // 43 +const static uint64_t SH_FLD_CPLTMASK0_LEN = 5128; // 43 +const static uint64_t SH_FLD_CPLT_DCTRL = 5129; // 43 +const static uint64_t SH_FLD_CPLT_RCTRL = 5130; // 43 +const static uint64_t SH_FLD_CPM_CAL_SET = 5131; // 43 +const static uint64_t SH_FLD_CPOL = 5132; // 1 +const static uint64_t SH_FLD_CPS = 5133; // 1 +const static uint64_t SH_FLD_CPS_LEN = 5134; // 1 +const static uint64_t SH_FLD_CP_LEN = 5135; // 2 +const static uint64_t SH_FLD_CP_RETRY_THRESH = 5136; // 4 +const static uint64_t SH_FLD_CP_RETRY_THRESH_LEN = 5137; // 4 +const static uint64_t SH_FLD_CQ_CERR_BIT10 = 5138; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT11 = 5139; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT12 = 5140; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT13 = 5141; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT14 = 5142; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT15 = 5143; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT16 = 5144; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT17 = 5145; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT18 = 5146; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT19 = 5147; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT20 = 5148; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT21 = 5149; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT22 = 5150; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT23 = 5151; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT24 = 5152; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT25 = 5153; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT26 = 5154; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT27 = 5155; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT28 = 5156; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT29 = 5157; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT30 = 5158; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT31 = 5159; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT32 = 5160; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT33 = 5161; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT34 = 5162; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT35 = 5163; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT36 = 5164; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT37 = 5165; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT38 = 5166; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT39 = 5167; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT4 = 5168; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT5 = 5169; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT6 = 5170; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT7 = 5171; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT8 = 5172; // 1 +const static uint64_t SH_FLD_CQ_CERR_BIT9 = 5173; // 1 +const static uint64_t SH_FLD_CQ_CERR_RESET = 5174; // 1 +const static uint64_t SH_FLD_CQ_DRAIN_THRESHOLD = 5175; // 1 +const static uint64_t SH_FLD_CQ_DRAIN_THRESHOLD_LEN = 5176; // 1 +const static uint64_t SH_FLD_CQ_ECC_CE_ERROR = 5177; // 2 +const static uint64_t SH_FLD_CQ_ECC_SUE_ERROR = 5178; // 2 +const static uint64_t SH_FLD_CQ_ECC_UE_ERROR = 5179; // 2 +const static uint64_t SH_FLD_CQ_FILL_THRESHOLD = 5180; // 1 +const static uint64_t SH_FLD_CQ_FILL_THRESHOLD_LEN = 5181; // 1 +const static uint64_t SH_FLD_CQ_LFSR_RESEED_EN = 5182; // 1 +const static uint64_t SH_FLD_CQ_LOGIC_HW_ERROR = 5183; // 2 +const static uint64_t SH_FLD_CQ_PB_LINK_ABORT = 5184; // 2 +const static uint64_t SH_FLD_CQ_PB_MASTER_FSM_HANG = 5185; // 2 +const static uint64_t SH_FLD_CQ_PB_OB_CE_ERROR = 5186; // 2 +const static uint64_t SH_FLD_CQ_PB_OB_UE_ERROR = 5187; // 2 +const static uint64_t SH_FLD_CQ_PB_PARITY_ERROR = 5188; // 2 +const static uint64_t SH_FLD_CQ_PB_RD_ADDR_ERROR = 5189; // 2 +const static uint64_t SH_FLD_CQ_PB_RD_LINK_ERROR = 5190; // 2 +const static uint64_t SH_FLD_CQ_PB_WR_ADDR_ERROR = 5191; // 2 +const static uint64_t SH_FLD_CQ_PB_WR_LINK_ERROR = 5192; // 2 +const static uint64_t SH_FLD_CQ_READ_RTY_RATIO = 5193; // 1 +const static uint64_t SH_FLD_CQ_READ_RTY_RATIO_LEN = 5194; // 1 +const static uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_HI = 5195; // 1 +const static uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_HI_LEN = 5196; // 1 +const static uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_LO = 5197; // 1 +const static uint64_t SH_FLD_CQ_TRACE_GROUP_SEL_LO_LEN = 5198; // 1 +const static uint64_t SH_FLD_CQ_TRACE_INT_DATA_LO = 5199; // 1 +const static uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_01 = 5200; // 1 +const static uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_01_LEN = 5201; // 1 +const static uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_23 = 5202; // 1 +const static uint64_t SH_FLD_CQ_TRACE_TRIGGER_SEL_23_LEN = 5203; // 1 +const static uint64_t SH_FLD_CR0_ATAG_PERR = 5204; // 1 +const static uint64_t SH_FLD_CR0_TTAG_PERR = 5205; // 1 +const static uint64_t SH_FLD_CR1_ATAG_PERR = 5206; // 1 +const static uint64_t SH_FLD_CR1_TTAG_PERR = 5207; // 1 +const static uint64_t SH_FLD_CR2_ATAG_PERR = 5208; // 1 +const static uint64_t SH_FLD_CR2_TTAG_PERR = 5209; // 1 +const static uint64_t SH_FLD_CR3_ATAG_PERR = 5210; // 1 +const static uint64_t SH_FLD_CR3_TTAG_PERR = 5211; // 1 +const static uint64_t SH_FLD_CRB_ECC_SUE = 5212; // 1 +const static uint64_t SH_FLD_CRB_ECC_UE = 5213; // 1 +const static uint64_t SH_FLD_CRB_READS_ENBL = 5214; // 1 +const static uint64_t SH_FLD_CRB_READS_HALTED = 5215; // 1 +const static uint64_t SH_FLD_CRC_MODE = 5216; // 2 +const static uint64_t SH_FLD_CRD_INIT_REQUEST = 5217; // 1 +const static uint64_t SH_FLD_CRD_REQUEST = 5218; // 1 +const static uint64_t SH_FLD_CREDIT_CUR = 5219; // 36 +const static uint64_t SH_FLD_CREDIT_CUR_LEN = 5220; // 36 +const static uint64_t SH_FLD_CREDIT_MAX = 5221; // 36 +const static uint64_t SH_FLD_CREDIT_MAX_LEN = 5222; // 36 +const static uint64_t SH_FLD_CREDIT_RCV_CUR = 5223; // 12 +const static uint64_t SH_FLD_CREDIT_RCV_CUR_LEN = 5224; // 12 +const static uint64_t SH_FLD_CREDIT_RCV_UPD = 5225; // 12 +const static uint64_t SH_FLD_CREDIT_SEND = 5226; // 36 +const static uint64_t SH_FLD_CREDIT_SEND_LEN = 5227; // 36 +const static uint64_t SH_FLD_CREDIT_UPD = 5228; // 36 +const static uint64_t SH_FLD_CREDIT_UPDATE_PENDING = 5229; // 6 +const static uint64_t SH_FLD_CREQ0 = 5230; // 12 +const static uint64_t SH_FLD_CREQ1 = 5231; // 12 +const static uint64_t SH_FLD_CREQ_AE_ALWAYS = 5232; // 6 +const static uint64_t SH_FLD_CREQ_BE_128 = 5233; // 6 +const static uint64_t SH_FLD_CRESP = 5234; // 24 +const static uint64_t SH_FLD_CRESP_0_4 = 5235; // 1 +const static uint64_t SH_FLD_CRESP_0_4_LEN = 5236; // 1 +const static uint64_t SH_FLD_CRESP_ADDR = 5237; // 2 +const static uint64_t SH_FLD_CRESP_ADDR_ERROR = 5238; // 2 +const static uint64_t SH_FLD_CRESP_ERROR = 5239; // 2 +const static uint64_t SH_FLD_CRESP_HANG = 5240; // 1 +const static uint64_t SH_FLD_CRESP_LEN = 5241; // 24 +const static uint64_t SH_FLD_CRITICAL_INTERRUPT = 5242; // 1 +const static uint64_t SH_FLD_CROSS_COUPLE_SELECT_1_B = 5243; // 86 +const static uint64_t SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN = 5244; // 86 +const static uint64_t SH_FLD_CROSS_COUPLE_SELECT_A = 5245; // 172 +const static uint64_t SH_FLD_CROSS_COUPLE_SELECT_A_LEN = 5246; // 172 +const static uint64_t SH_FLD_CROSS_COUPLE_SELECT_B = 5247; // 86 +const static uint64_t SH_FLD_CROSS_COUPLE_SELECT_B_LEN = 5248; // 86 +const static uint64_t SH_FLD_CR_ATAG_PAR = 5249; // 1 +const static uint64_t SH_FLD_CR_TTAG_PAR = 5250; // 1 +const static uint64_t SH_FLD_CS = 5251; // 6 +const static uint64_t SH_FLD_CS0_INIT_CAL_VALUE = 5252; // 8 +const static uint64_t SH_FLD_CS1_INIT_CAL_VALUE = 5253; // 8 +const static uint64_t SH_FLD_CS2_INIT_CAL_VALUE = 5254; // 8 +const static uint64_t SH_FLD_CS3_INIT_CAL_VALUE = 5255; // 8 +const static uint64_t SH_FLD_CS4_INIT_CAL_VALUE = 5256; // 8 +const static uint64_t SH_FLD_CS5_INIT_CAL_VALUE = 5257; // 8 +const static uint64_t SH_FLD_CS6_INIT_CAL_VALUE = 5258; // 8 +const static uint64_t SH_FLD_CS7_INIT_CAL_VALUE = 5259; // 8 +const static uint64_t SH_FLD_CSEL = 5260; // 10 +const static uint64_t SH_FLD_CSEL_LEN = 5261; // 10 +const static uint64_t SH_FLD_CS_LEN = 5262; // 6 +const static uint64_t SH_FLD_CTL = 5263; // 1 +const static uint64_t SH_FLD_CTLE_GAIN_MAX = 5264; // 6 +const static uint64_t SH_FLD_CTLE_GAIN_MAX_LEN = 5265; // 6 +const static uint64_t SH_FLD_CTLE_UPDATE_MODE = 5266; // 6 +const static uint64_t SH_FLD_CTLR_HP_THRESH = 5267; // 3 +const static uint64_t SH_FLD_CTLR_HP_THRESH_LEN = 5268; // 3 +const static uint64_t SH_FLD_CTLW_HP_THRESH = 5269; // 3 +const static uint64_t SH_FLD_CTLW_HP_THRESH_LEN = 5270; // 3 +const static uint64_t SH_FLD_CTL_ARRAY_CE = 5271; // 1 +const static uint64_t SH_FLD_CTL_ARRAY_UE = 5272; // 1 +const static uint64_t SH_FLD_CTL_FWD_PROGRESS_ERR = 5273; // 1 +const static uint64_t SH_FLD_CTL_LEN = 5274; // 1 +const static uint64_t SH_FLD_CTL_LOGIC_ERR = 5275; // 1 +const static uint64_t SH_FLD_CTL_MMIO_ST_DATA_UE = 5276; // 1 +const static uint64_t SH_FLD_CTL_NVL_CFG_ERR = 5277; // 1 +const static uint64_t SH_FLD_CTL_NVL_FATAL_ERR = 5278; // 1 +const static uint64_t SH_FLD_CTL_PBUS_CONFIG_ERR = 5279; // 1 +const static uint64_t SH_FLD_CTL_PBUS_FATAL_ERR = 5280; // 1 +const static uint64_t SH_FLD_CTL_PBUS_PERR = 5281; // 1 +const static uint64_t SH_FLD_CTL_PBUS_RECOV_ERR = 5282; // 1 +const static uint64_t SH_FLD_CTL_PEF = 5283; // 1 +const static uint64_t SH_FLD_CTL_PEST_DIS = 5284; // 1 +const static uint64_t SH_FLD_CTL_RING_ERR = 5285; // 1 +const static uint64_t SH_FLD_CTL_RSVD_15 = 5286; // 1 +const static uint64_t SH_FLD_CTL_SM_0 = 5287; // 6 +const static uint64_t SH_FLD_CTL_SM_1 = 5288; // 6 +const static uint64_t SH_FLD_CTL_SM_2 = 5289; // 6 +const static uint64_t SH_FLD_CTL_SM_3 = 5290; // 6 +const static uint64_t SH_FLD_CTL_SM_4 = 5291; // 6 +const static uint64_t SH_FLD_CTL_SM_5 = 5292; // 6 +const static uint64_t SH_FLD_CTL_SM_6 = 5293; // 6 +const static uint64_t SH_FLD_CTL_SM_7 = 5294; // 6 +const static uint64_t SH_FLD_CTL_TICK = 5295; // 12 +const static uint64_t SH_FLD_CTL_TICK_LEN = 5296; // 12 +const static uint64_t SH_FLD_CTL_TRACE_EN = 5297; // 1 +const static uint64_t SH_FLD_CTL_TRACE_SEL = 5298; // 1 +const static uint64_t SH_FLD_CTRLR_PERR_ESR = 5299; // 1 +const static uint64_t SH_FLD_CTRL_BUSY = 5300; // 1 +const static uint64_t SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC = 5301; // 43 +const static uint64_t SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC = 5302; // 43 +const static uint64_t SH_FLD_CTRL_CC_DCTEST_DC = 5303; // 43 +const static uint64_t SH_FLD_CTRL_CC_FLUSHMODE_INH_DC = 5304; // 43 +const static uint64_t SH_FLD_CTRL_CC_FORCE_ALIGN_DC = 5305; // 43 +const static uint64_t SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC = 5306; // 43 +const static uint64_t SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC = 5307; // 43 +const static uint64_t SH_FLD_CTRL_CC_OTP_PRGMODE_DC = 5308; // 43 +const static uint64_t SH_FLD_CTRL_CC_PIN_LBIST_DC = 5309; // 43 +const static uint64_t SH_FLD_CTRL_CC_SCAN_PROTECT_DC = 5310; // 43 +const static uint64_t SH_FLD_CTRL_CC_SDIS_DC_N = 5311; // 43 +const static uint64_t SH_FLD_CTRL_CC_SSS_CALIBRATE_DC = 5312; // 43 +const static uint64_t SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC = 5313; // 43 +const static uint64_t SH_FLD_CTRL_MISC_CLKDIV_SEL_DC = 5314; // 43 +const static uint64_t SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN = 5315; // 43 +const static uint64_t SH_FLD_CTRL_MISC_PROBE0_SEL_DC = 5316; // 43 +const static uint64_t SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN = 5317; // 43 +const static uint64_t SH_FLD_CTRL_MISC_PROBE1_SEL_DC = 5318; // 43 +const static uint64_t SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN = 5319; // 43 +const static uint64_t SH_FLD_CTRL_MISC_PROBE2_SEL_DC = 5320; // 43 +const static uint64_t SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN = 5321; // 43 +const static uint64_t SH_FLD_CTRL_MISC_PROBE3_SEL_DC = 5322; // 43 +const static uint64_t SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN = 5323; // 43 +const static uint64_t SH_FLD_CTRL_PARITY = 5324; // 43 +const static uint64_t SH_FLD_CT_COMPARE_VECTOR = 5325; // 2 +const static uint64_t SH_FLD_CT_COMPARE_VECTOR_LEN = 5326; // 2 +const static uint64_t SH_FLD_CURRENT_OPCG_MODE = 5327; // 43 +const static uint64_t SH_FLD_CURRENT_OPCG_MODE_LEN = 5328; // 43 +const static uint64_t SH_FLD_CUR_RD_ADDR = 5329; // 6 +const static uint64_t SH_FLD_CUR_RD_ADDR_LEN = 5330; // 6 +const static uint64_t SH_FLD_CUSTOM_INIT_WRITE = 5331; // 8 +const static uint64_t SH_FLD_CUSTOM_RD = 5332; // 8 +const static uint64_t SH_FLD_CUSTOM_WR = 5333; // 8 +const static uint64_t SH_FLD_CW_MIRROR = 5334; // 8 +const static uint64_t SH_FLD_CW_TYPE = 5335; // 12 +const static uint64_t SH_FLD_CW_TYPE_LEN = 5336; // 12 +const static uint64_t SH_FLD_CYCLECNT = 5337; // 3 +const static uint64_t SH_FLD_CYCLECNT_LEN = 5338; // 3 +const static uint64_t SH_FLD_CYCLES = 5339; // 12 +const static uint64_t SH_FLD_CYCLES_LEN = 5340; // 12 +const static uint64_t SH_FLD_CYCLE_COUNT = 5341; // 24 +const static uint64_t SH_FLD_CYCLE_COUNT_LEN = 5342; // 24 +const static uint64_t SH_FLD_C_ERR_RPT_HOLD_DATA = 5343; // 2 +const static uint64_t SH_FLD_C_ERR_RPT_HOLD_DATA_LEN = 5344; // 2 +const static uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT = 5345; // 4 +const static uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_DEC_SELECT_LEN = 5346; // 4 +const static uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT = 5347; // 4 +const static uint64_t SH_FLD_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT_LEN = 5348; // 4 +const static uint64_t SH_FLD_DACTEST_HLMT = 5349; // 6 +const static uint64_t SH_FLD_DACTEST_HLMT_LEN = 5350; // 6 +const static uint64_t SH_FLD_DACTEST_LLMT = 5351; // 6 +const static uint64_t SH_FLD_DACTEST_LLMT_LEN = 5352; // 6 +const static uint64_t SH_FLD_DACTEST_RESET = 5353; // 6 +const static uint64_t SH_FLD_DACTEST_START = 5354; // 6 +const static uint64_t SH_FLD_DAC_BO_CFG = 5355; // 6 +const static uint64_t SH_FLD_DAC_BO_CFG_LEN = 5356; // 6 +const static uint64_t SH_FLD_DARN_ADDR_ERR = 5357; // 12 +const static uint64_t SH_FLD_DARN_DATA_TIMEOUT = 5358; // 12 +const static uint64_t SH_FLD_DARN_EN_ERR = 5359; // 12 +const static uint64_t SH_FLD_DAT0 = 5360; // 1 +const static uint64_t SH_FLD_DAT0_LEN = 5361; // 1 +const static uint64_t SH_FLD_DAT1 = 5362; // 1 +const static uint64_t SH_FLD_DAT1_LEN = 5363; // 1 +const static uint64_t SH_FLD_DATA = 5364; // 382 +const static uint64_t SH_FLD_DATA0 = 5365; // 6 +const static uint64_t SH_FLD_DATA0_LEN = 5366; // 6 +const static uint64_t SH_FLD_DATA1 = 5367; // 6 +const static uint64_t SH_FLD_DATA1_LEN = 5368; // 6 +const static uint64_t SH_FLD_DATA2 = 5369; // 6 +const static uint64_t SH_FLD_DATA2_LEN = 5370; // 6 +const static uint64_t SH_FLD_DATA_0_63 = 5371; // 2 +const static uint64_t SH_FLD_DATA_0_63_LEN = 5372; // 2 +const static uint64_t SH_FLD_DATA_64_79 = 5373; // 2 +const static uint64_t SH_FLD_DATA_64_79_LEN = 5374; // 2 +const static uint64_t SH_FLD_DATA_ARB_LFSR_CONFIG = 5375; // 1 +const static uint64_t SH_FLD_DATA_ARB_LFSR_CONFIG_LEN = 5376; // 1 +const static uint64_t SH_FLD_DATA_BUFFER = 5377; // 43 +const static uint64_t SH_FLD_DATA_COMPARE_BURST_SEL = 5378; // 2 +const static uint64_t SH_FLD_DATA_COMPARE_BURST_SEL_LEN = 5379; // 2 +const static uint64_t SH_FLD_DATA_DLY = 5380; // 1 +const static uint64_t SH_FLD_DATA_DLY_LEN = 5381; // 1 +const static uint64_t SH_FLD_DATA_HANG_DETECTED = 5382; // 2 +const static uint64_t SH_FLD_DATA_HANG_POLL_SCALE = 5383; // 2 +const static uint64_t SH_FLD_DATA_HANG_POLL_SCALE_LEN = 5384; // 2 +const static uint64_t SH_FLD_DATA_LEN = 5385; // 382 +const static uint64_t SH_FLD_DATA_MUX4_1MODE = 5386; // 8 +const static uint64_t SH_FLD_DATA_PARITY_ERR = 5387; // 4 +const static uint64_t SH_FLD_DATA_PIPE_CLR_ON_READ_MODE = 5388; // 6 +const static uint64_t SH_FLD_DATA_POISON_SUE_ENA = 5389; // 6 +const static uint64_t SH_FLD_DATA_POLL_PULSE_DIV = 5390; // 12 +const static uint64_t SH_FLD_DATA_POLL_PULSE_DIV_LEN = 5391; // 12 +const static uint64_t SH_FLD_DATA_REG0 = 5392; // 8 +const static uint64_t SH_FLD_DATA_REG0_LEN = 5393; // 8 +const static uint64_t SH_FLD_DATA_REG1 = 5394; // 8 +const static uint64_t SH_FLD_DATA_REG1_LEN = 5395; // 8 +const static uint64_t SH_FLD_DATA_REG_0_31 = 5396; // 1 +const static uint64_t SH_FLD_DATA_REG_0_31_LEN = 5397; // 1 +const static uint64_t SH_FLD_DATA_REQUEST_0 = 5398; // 4 +const static uint64_t SH_FLD_DATA_REQUEST_1 = 5399; // 2 +const static uint64_t SH_FLD_DATA_REQUEST_2 = 5400; // 2 +const static uint64_t SH_FLD_DATA_REQUEST_3 = 5401; // 2 +const static uint64_t SH_FLD_DATA_ROUTE_ERROR = 5402; // 2 +const static uint64_t SH_FLD_DATA_RTAG_P = 5403; // 12 +const static uint64_t SH_FLD_DATA_V_LT = 5404; // 43 +const static uint64_t SH_FLD_DAT_ARR_ECC_CORR_ENA = 5405; // 6 +const static uint64_t SH_FLD_DAT_ARR_ECC_SUE_ENA = 5406; // 6 +const static uint64_t SH_FLD_DAT_BUFFER_PAR_ERR = 5407; // 4 +const static uint64_t SH_FLD_DAT_CREG_PERR = 5408; // 1 +const static uint64_t SH_FLD_DAT_DATA_BE_CE = 5409; // 1 +const static uint64_t SH_FLD_DAT_DATA_BE_PERR = 5410; // 1 +const static uint64_t SH_FLD_DAT_DATA_BE_SUE = 5411; // 1 +const static uint64_t SH_FLD_DAT_DATA_BE_UE = 5412; // 1 +const static uint64_t SH_FLD_DAT_LOGIC_ERR = 5413; // 1 +const static uint64_t SH_FLD_DAT_PBRX_SUE = 5414; // 1 +const static uint64_t SH_FLD_DAT_RSVD_10 = 5415; // 1 +const static uint64_t SH_FLD_DAT_RSVD_9 = 5416; // 1 +const static uint64_t SH_FLD_DAT_RTAG_PERR = 5417; // 1 +const static uint64_t SH_FLD_DAT_STATE_PERR = 5418; // 1 +const static uint64_t SH_FLD_DBG_BUS0_STG0_SEL = 5419; // 2 +const static uint64_t SH_FLD_DBG_BUS0_STG0_SEL_LEN = 5420; // 2 +const static uint64_t SH_FLD_DBG_BUS1_STG0_SEL = 5421; // 2 +const static uint64_t SH_FLD_DBG_BUS1_STG0_SEL_LEN = 5422; // 2 +const static uint64_t SH_FLD_DBG_BUS_BIT = 5423; // 8 +const static uint64_t SH_FLD_DBG_CC_ERROR = 5424; // 1 +const static uint64_t SH_FLD_DBG_CHIPLET_IS_ALIGNED = 5425; // 1 +const static uint64_t SH_FLD_DBG_CMD = 5426; // 1 +const static uint64_t SH_FLD_DBG_CMD_LEN = 5427; // 1 +const static uint64_t SH_FLD_DBG_CURRENT_OPCG_MODE = 5428; // 1 +const static uint64_t SH_FLD_DBG_CURRENT_OPCG_MODE_LEN = 5429; // 1 +const static uint64_t SH_FLD_DBG_HALT = 5430; // 1 +const static uint64_t SH_FLD_DBG_LAST_OPCG_MODE = 5431; // 1 +const static uint64_t SH_FLD_DBG_LAST_OPCG_MODE_LEN = 5432; // 1 +const static uint64_t SH_FLD_DBG_OPCG_IP = 5433; // 1 +const static uint64_t SH_FLD_DBG_PARANOIA_TEST_ENABLE_CHANGE = 5434; // 1 +const static uint64_t SH_FLD_DBG_PARANOIA_VITL_CLKOFF_CHANGE = 5435; // 1 +const static uint64_t SH_FLD_DBG_PARITY_ERROR = 5436; // 1 +const static uint64_t SH_FLD_DBG_PCB_ERROR = 5437; // 1 +const static uint64_t SH_FLD_DBG_PCB_IDLE = 5438; // 1 +const static uint64_t SH_FLD_DBG_PCB_REQUEST_SINCE_RESET = 5439; // 1 +const static uint64_t SH_FLD_DBG_PROTOCOL_ERROR = 5440; // 1 +const static uint64_t SH_FLD_DBG_REQ = 5441; // 1 +const static uint64_t SH_FLD_DBG_RESET_EP = 5442; // 1 +const static uint64_t SH_FLD_DBG_SECURITY_DEBUG_MODE = 5443; // 1 +const static uint64_t SH_FLD_DBG_SEL_IN = 5444; // 8 +const static uint64_t SH_FLD_DBG_SEL_PWCTL_DEBUG = 5445; // 8 +const static uint64_t SH_FLD_DBG_SEL_PWSEQ0_DEBUG_0 = 5446; // 8 +const static uint64_t SH_FLD_DBG_SEL_PWSEQ0_DEBUG_1 = 5447; // 8 +const static uint64_t SH_FLD_DBG_SEL_PWSEQ1_DEBUG_0 = 5448; // 8 +const static uint64_t SH_FLD_DBG_SEL_PWSEQ1_DEBUG_1 = 5449; // 8 +const static uint64_t SH_FLD_DBG_SEL_PWSEQ2_DEBUG_0 = 5450; // 8 +const static uint64_t SH_FLD_DBG_SEL_PWSEQ2_DEBUG_1 = 5451; // 8 +const static uint64_t SH_FLD_DBG_SEL_PWSEQ3_DEBUG_0 = 5452; // 8 +const static uint64_t SH_FLD_DBG_SEL_PWSEQ3_DEBUG_1 = 5453; // 8 +const static uint64_t SH_FLD_DBG_SEL_PWSEQ4_DEBUG_0 = 5454; // 8 +const static uint64_t SH_FLD_DBG_SEL_PWSEQ4_DEBUG_1 = 5455; // 8 +const static uint64_t SH_FLD_DBG_SEL_PWSEQ5_DEBUG_0 = 5456; // 8 +const static uint64_t SH_FLD_DBG_SEL_PWSEQ5_DEBUG_1 = 5457; // 8 +const static uint64_t SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_0 = 5458; // 8 +const static uint64_t SH_FLD_DBG_SEL_SEC_WDFRD_DEBUG_1 = 5459; // 8 +const static uint64_t SH_FLD_DBG_SEL_WDF = 5460; // 8 +const static uint64_t SH_FLD_DBG_SEL_WDFMGR_DEBUG = 5461; // 8 +const static uint64_t SH_FLD_DBG_SEL_WDFRD_DEBUG_0 = 5462; // 8 +const static uint64_t SH_FLD_DBG_SEL_WDFRD_DEBUG_1 = 5463; // 8 +const static uint64_t SH_FLD_DBG_SEL_WDFWR_DEBUG_0 = 5464; // 8 +const static uint64_t SH_FLD_DBG_SEL_WDFWR_DEBUG_1 = 5465; // 8 +const static uint64_t SH_FLD_DBG_SPARE = 5466; // 8 +const static uint64_t SH_FLD_DBG_SPARE_LEN = 5467; // 8 +const static uint64_t SH_FLD_DBG_SPARE_MCA = 5468; // 8 +const static uint64_t SH_FLD_DBG_SPARE_MCA_LEN = 5469; // 8 +const static uint64_t SH_FLD_DBG_SPARE_NEST = 5470; // 8 +const static uint64_t SH_FLD_DBG_SPARE_NEST_LEN = 5471; // 8 +const static uint64_t SH_FLD_DBG_STATE = 5472; // 1 +const static uint64_t SH_FLD_DBG_STATE_LEN = 5473; // 1 +const static uint64_t SH_FLD_DBG_TEST_ENABLE = 5474; // 1 +const static uint64_t SH_FLD_DBG_TP_TPFSI_ACK = 5475; // 1 +const static uint64_t SH_FLD_DBG_UNCONDITIONAL_EVENT = 5476; // 1 +const static uint64_t SH_FLD_DBG_VITL_CLKOFF = 5477; // 1 +const static uint64_t SH_FLD_DCACHE_ERR = 5478; // 4 +const static uint64_t SH_FLD_DCACHE_TAG_ADDR = 5479; // 4 +const static uint64_t SH_FLD_DCACHE_TAG_ADDR_LEN = 5480; // 4 +const static uint64_t SH_FLD_DCLKSEL = 5481; // 6 +const static uint64_t SH_FLD_DCLKSEL_LEN = 5482; // 6 +const static uint64_t SH_FLD_DCOMP_ENABLE = 5483; // 1 +const static uint64_t SH_FLD_DCOMP_ENGINE_BUSY = 5484; // 1 +const static uint64_t SH_FLD_DCOMP_ERR = 5485; // 1 +const static uint64_t SH_FLD_DCO_DECR = 5486; // 6 +const static uint64_t SH_FLD_DCO_INCR = 5487; // 6 +const static uint64_t SH_FLD_DCO_OVERRIDE = 5488; // 6 +const static uint64_t SH_FLD_DCU_RNW = 5489; // 1 +const static uint64_t SH_FLD_DCU_TIMEOUT_ERROR = 5490; // 1 +const static uint64_t SH_FLD_DC_CALIBRATE_DONE = 5491; // 4 +const static uint64_t SH_FLD_DC_ENABLE_CM_COARSE_CAL = 5492; // 6 +const static uint64_t SH_FLD_DC_ENABLE_CM_FINE_CAL = 5493; // 6 +const static uint64_t SH_FLD_DC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 5494; // 6 +const static uint64_t SH_FLD_DC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 5495; // 6 +const static uint64_t SH_FLD_DC_ENABLE_DAC_H1_CAL = 5496; // 4 +const static uint64_t SH_FLD_DC_ENABLE_DAC_H1_TO_A_CAL = 5497; // 4 +const static uint64_t SH_FLD_DC_ENABLE_INTEG_LATCH_OFFSET_CAL = 5498; // 6 +const static uint64_t SH_FLD_DD2_FIX_DIS = 5499; // 8 +const static uint64_t SH_FLD_DDC_CFG = 5500; // 120 +const static uint64_t SH_FLD_DDC_CFG_LEN = 5501; // 120 +const static uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_SM = 5502; // 72 +const static uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_SM_LEN = 5503; // 72 +const static uint64_t SH_FLD_DDC_DFE_OFFSET_SWITCH_STOP = 5504; // 72 +const static uint64_t SH_FLD_DDR4_CMD_SIG_REDUCTION = 5505; // 8 +const static uint64_t SH_FLD_DDR4_IPW_LOOP_DIS = 5506; // 8 +const static uint64_t SH_FLD_DDR4_LATENCY_SW = 5507; // 8 +const static uint64_t SH_FLD_DDR4_VLEVEL_BANK_GROUP = 5508; // 8 +const static uint64_t SH_FLD_DDR_ACTN = 5509; // 64 +const static uint64_t SH_FLD_DDR_ADDRESS = 5510; // 8 +const static uint64_t SH_FLD_DDR_ADDRESS_0 = 5511; // 2 +const static uint64_t SH_FLD_DDR_ADDRESS_0_13 = 5512; // 62 +const static uint64_t SH_FLD_DDR_ADDRESS_0_13_LEN = 5513; // 62 +const static uint64_t SH_FLD_DDR_ADDRESS_0_LEN = 5514; // 2 +const static uint64_t SH_FLD_DDR_ADDRESS_14 = 5515; // 62 +const static uint64_t SH_FLD_DDR_ADDRESS_15 = 5516; // 62 +const static uint64_t SH_FLD_DDR_ADDRESS_16 = 5517; // 62 +const static uint64_t SH_FLD_DDR_ADDRESS_17 = 5518; // 62 +const static uint64_t SH_FLD_DDR_BANK_0_1 = 5519; // 64 +const static uint64_t SH_FLD_DDR_BANK_0_1_LEN = 5520; // 64 +const static uint64_t SH_FLD_DDR_BANK_2 = 5521; // 64 +const static uint64_t SH_FLD_DDR_BANK_GROUP_0 = 5522; // 64 +const static uint64_t SH_FLD_DDR_BANK_GROUP_1 = 5523; // 64 +const static uint64_t SH_FLD_DDR_CALIBRATION_ENABLE = 5524; // 64 +const static uint64_t SH_FLD_DDR_CAL_RANK = 5525; // 64 +const static uint64_t SH_FLD_DDR_CAL_RANK_LEN = 5526; // 64 +const static uint64_t SH_FLD_DDR_CAL_RESET_TIMEOUT = 5527; // 16 +const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT = 5528; // 2 +const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_LEN = 5529; // 2 +const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT = 5530; // 2 +const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_CNT_MULT_LEN = 5531; // 2 +const static uint64_t SH_FLD_DDR_CAL_TIMEOUT_ERR = 5532; // 16 +const static uint64_t SH_FLD_DDR_CAL_TYPE = 5533; // 64 +const static uint64_t SH_FLD_DDR_CAL_TYPE_LEN = 5534; // 64 +const static uint64_t SH_FLD_DDR_CID_0_1 = 5535; // 64 +const static uint64_t SH_FLD_DDR_CID_0_1_LEN = 5536; // 64 +const static uint64_t SH_FLD_DDR_CID_2 = 5537; // 64 +const static uint64_t SH_FLD_DDR_CKE = 5538; // 64 +const static uint64_t SH_FLD_DDR_CKE_LEN = 5539; // 64 +const static uint64_t SH_FLD_DDR_CSN_0_1 = 5540; // 64 +const static uint64_t SH_FLD_DDR_CSN_0_1_LEN = 5541; // 64 +const static uint64_t SH_FLD_DDR_CSN_2_3 = 5542; // 64 +const static uint64_t SH_FLD_DDR_CSN_2_3_LEN = 5543; // 64 +const static uint64_t SH_FLD_DDR_IF_SM_1HOT = 5544; // 8 +const static uint64_t SH_FLD_DDR_INVALID_ACCESS = 5545; // 8 +const static uint64_t SH_FLD_DDR_MBA_EVENT_N = 5546; // 16 +const static uint64_t SH_FLD_DDR_ODT = 5547; // 64 +const static uint64_t SH_FLD_DDR_ODT_LEN = 5548; // 64 +const static uint64_t SH_FLD_DDR_PARITY = 5549; // 64 +const static uint64_t SH_FLD_DDR_PARITY_ENABLE = 5550; // 2 +const static uint64_t SH_FLD_DDR_RESETN = 5551; // 64 +const static uint64_t SH_FLD_DEAD = 5552; // 43 +const static uint64_t SH_FLD_DEBUG = 5553; // 2 +const static uint64_t SH_FLD_DEBUG0_CONFIG_P = 5554; // 1 +const static uint64_t SH_FLD_DEBUG1_CONFIG_P = 5555; // 1 +const static uint64_t SH_FLD_DEBUGGER = 5556; // 25 +const static uint64_t SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS = 5557; // 1 +const static uint64_t SH_FLD_DEBUG_BOLT_ON_CONTROL_BITS_LEN = 5558; // 1 +const static uint64_t SH_FLD_DEBUG_BUS_SEL = 5559; // 8 +const static uint64_t SH_FLD_DEBUG_BUS_SEL2 = 5560; // 8 +const static uint64_t SH_FLD_DEBUG_BUS_SEL2_LEN = 5561; // 8 +const static uint64_t SH_FLD_DEBUG_BUS_SEL_LEN = 5562; // 8 +const static uint64_t SH_FLD_DEBUG_LEN = 5563; // 2 +const static uint64_t SH_FLD_DEBUG_OCI_MODE = 5564; // 1 +const static uint64_t SH_FLD_DEBUG_OCI_MODE_LEN = 5565; // 1 +const static uint64_t SH_FLD_DEBUG_PB_NOT_OCI = 5566; // 1 +const static uint64_t SH_FLD_DEBUG_TRIGGER = 5567; // 24 +const static uint64_t SH_FLD_DECONFIGURED_INTR = 5568; // 24 +const static uint64_t SH_FLD_DECOUPLE_EDGE_A = 5569; // 48 +const static uint64_t SH_FLD_DECOUPLE_EDGE_B = 5570; // 48 +const static uint64_t SH_FLD_DEC_EXIT_ENABLE = 5571; // 96 +const static uint64_t SH_FLD_DEF_VALUES = 5572; // 8 +const static uint64_t SH_FLD_DEF_VALUES_LEN = 5573; // 8 +const static uint64_t SH_FLD_DEGLITCH_CLK_DLY = 5574; // 1 +const static uint64_t SH_FLD_DEGLITCH_CLK_DLY_LEN = 5575; // 1 +const static uint64_t SH_FLD_DEGLITCH_DATA_DLY = 5576; // 1 +const static uint64_t SH_FLD_DEGLITCH_DATA_DLY_LEN = 5577; // 1 +const static uint64_t SH_FLD_DELAY = 5578; // 1 +const static uint64_t SH_FLD_DELAY1_ID = 5579; // 12 +const static uint64_t SH_FLD_DELAY1_ID_LEN = 5580; // 12 +const static uint64_t SH_FLD_DELAY1_VALID = 5581; // 12 +const static uint64_t SH_FLD_DELAY2_ID = 5582; // 12 +const static uint64_t SH_FLD_DELAY2_ID_LEN = 5583; // 12 +const static uint64_t SH_FLD_DELAY2_VALID = 5584; // 12 +const static uint64_t SH_FLD_DELAY3_ID = 5585; // 12 +const static uint64_t SH_FLD_DELAY3_ID_LEN = 5586; // 12 +const static uint64_t SH_FLD_DELAY3_VALID = 5587; // 12 +const static uint64_t SH_FLD_DELAY4_ID = 5588; // 12 +const static uint64_t SH_FLD_DELAY4_ID_LEN = 5589; // 12 +const static uint64_t SH_FLD_DELAY4_VALID = 5590; // 12 +const static uint64_t SH_FLD_DELAY5_ID = 5591; // 12 +const static uint64_t SH_FLD_DELAY5_ID_LEN = 5592; // 12 +const static uint64_t SH_FLD_DELAY5_VALID = 5593; // 12 +const static uint64_t SH_FLD_DELAY6_ID = 5594; // 12 +const static uint64_t SH_FLD_DELAY6_ID_LEN = 5595; // 12 +const static uint64_t SH_FLD_DELAY6_VALID = 5596; // 12 +const static uint64_t SH_FLD_DELAY7_ID = 5597; // 12 +const static uint64_t SH_FLD_DELAY7_ID_LEN = 5598; // 12 +const static uint64_t SH_FLD_DELAY7_VALID = 5599; // 12 +const static uint64_t SH_FLD_DELAY8_ID = 5600; // 12 +const static uint64_t SH_FLD_DELAY8_ID_LEN = 5601; // 12 +const static uint64_t SH_FLD_DELAY8_VALID = 5602; // 12 +const static uint64_t SH_FLD_DELAYED_PAR = 5603; // 8 +const static uint64_t SH_FLD_DELAYG = 5604; // 32 +const static uint64_t SH_FLD_DELAYG_LEN = 5605; // 32 +const static uint64_t SH_FLD_DELAY_ADJUST_DISABLE = 5606; // 1 +const static uint64_t SH_FLD_DELAY_ADJUST_VALUE = 5607; // 1 +const static uint64_t SH_FLD_DELAY_ADJUST_VALUE_LEN = 5608; // 1 +const static uint64_t SH_FLD_DELAY_AFTER_BLOCK = 5609; // 24 +const static uint64_t SH_FLD_DELAY_DISABLE = 5610; // 1 +const static uint64_t SH_FLD_DELAY_LCLKR = 5611; // 43 +const static uint64_t SH_FLD_DELAY_LEN = 5612; // 1 +const static uint64_t SH_FLD_DELAY_LINE_CTL_OVERRIDE = 5613; // 8 +const static uint64_t SH_FLD_DEQUEUED_EOT_FLAG = 5614; // 1 +const static uint64_t SH_FLD_DESKEW_DONE = 5615; // 4 +const static uint64_t SH_FLD_DESKEW_FAILED = 5616; // 4 +const static uint64_t SH_FLD_DESKEW_MAXSKEW_GRP = 5617; // 4 +const static uint64_t SH_FLD_DESKEW_MAXSKEW_GRP_LEN = 5618; // 4 +const static uint64_t SH_FLD_DESKEW_MAX_LIMIT = 5619; // 4 +const static uint64_t SH_FLD_DESKEW_MAX_LIMIT_LEN = 5620; // 4 +const static uint64_t SH_FLD_DESKEW_MINSKEW_GRP = 5621; // 4 +const static uint64_t SH_FLD_DESKEW_MINSKEW_GRP_LEN = 5622; // 4 +const static uint64_t SH_FLD_DESKEW_PATTCHK_TIMEOUT_SEL = 5623; // 4 +const static uint64_t SH_FLD_DESKEW_PATTCHK_TIMEOUT_SEL_LEN = 5624; // 4 +const static uint64_t SH_FLD_DESKEW_RATE = 5625; // 8 +const static uint64_t SH_FLD_DESKEW_SEQ_GCRMSG = 5626; // 4 +const static uint64_t SH_FLD_DESKEW_SEQ_GCRMSG_LEN = 5627; // 4 +const static uint64_t SH_FLD_DESKEW_SKMAX_GCRMSG = 5628; // 4 +const static uint64_t SH_FLD_DESKEW_SKMAX_GCRMSG_LEN = 5629; // 4 +const static uint64_t SH_FLD_DESKEW_SKMIN_GCRMSG = 5630; // 4 +const static uint64_t SH_FLD_DESKEW_SKMIN_GCRMSG_LEN = 5631; // 4 +const static uint64_t SH_FLD_DEST = 5632; // 1 +const static uint64_t SH_FLD_DEST0 = 5633; // 24 +const static uint64_t SH_FLD_DEST0_LEN = 5634; // 24 +const static uint64_t SH_FLD_DEST1 = 5635; // 24 +const static uint64_t SH_FLD_DEST1_LEN = 5636; // 24 +const static uint64_t SH_FLD_DEST_CHIPID = 5637; // 1 +const static uint64_t SH_FLD_DEST_CHIPID_LEN = 5638; // 1 +const static uint64_t SH_FLD_DEST_GROUPID = 5639; // 1 +const static uint64_t SH_FLD_DEST_GROUPID_LEN = 5640; // 1 +const static uint64_t SH_FLD_DEST_LEN = 5641; // 1 +const static uint64_t SH_FLD_DEVICE = 5642; // 1 +const static uint64_t SH_FLD_DEVICE_ADDRESS_0 = 5643; // 2 +const static uint64_t SH_FLD_DEVICE_ADDRESS_0_LEN = 5644; // 2 +const static uint64_t SH_FLD_DEVICE_ADDRESS_1 = 5645; // 1 +const static uint64_t SH_FLD_DEVICE_ADDRESS_1_LEN = 5646; // 1 +const static uint64_t SH_FLD_DEVICE_ADDRESS_2 = 5647; // 1 +const static uint64_t SH_FLD_DEVICE_ADDRESS_2_LEN = 5648; // 1 +const static uint64_t SH_FLD_DEVICE_ADDRESS_3 = 5649; // 1 +const static uint64_t SH_FLD_DEVICE_ADDRESS_3_LEN = 5650; // 1 +const static uint64_t SH_FLD_DEVICE_ID = 5651; // 4 +const static uint64_t SH_FLD_DEVICE_ID_LEN = 5652; // 4 +const static uint64_t SH_FLD_DFE12_EN = 5653; // 4 +const static uint64_t SH_FLD_DFEHISPD_EN = 5654; // 4 +const static uint64_t SH_FLD_DFE_CA_CFG = 5655; // 6 +const static uint64_t SH_FLD_DFE_CA_CFG_LEN = 5656; // 6 +const static uint64_t SH_FLD_DFE_CONVERGED_CNT_MAX = 5657; // 6 +const static uint64_t SH_FLD_DFE_CONVERGED_CNT_MAX_LEN = 5658; // 6 +const static uint64_t SH_FLD_DFE_FORCE_LOAD_SEED = 5659; // 72 +const static uint64_t SH_FLD_DFE_HTAP_CFG = 5660; // 4 +const static uint64_t SH_FLD_DFE_HTAP_CFG_LEN = 5661; // 4 +const static uint64_t SH_FLD_DFE_INIT_TIMEOUT = 5662; // 4 +const static uint64_t SH_FLD_DFE_INIT_TIMEOUT_LEN = 5663; // 4 +const static uint64_t SH_FLD_DFE_RECAL_TIMEOUT = 5664; // 4 +const static uint64_t SH_FLD_DFE_RECAL_TIMEOUT_LEN = 5665; // 4 +const static uint64_t SH_FLD_DFREEZE = 5666; // 9 +const static uint64_t SH_FLD_DFREEZE_LEN = 5667; // 9 +const static uint64_t SH_FLD_DGD_AE_ALWAYS = 5668; // 6 +const static uint64_t SH_FLD_DGD_BE_128 = 5669; // 6 +const static uint64_t SH_FLD_DGEN_RNDD_DATA_MAPPING = 5670; // 2 +const static uint64_t SH_FLD_DGEN_RNDD_DATA_MAPPING_LEN = 5671; // 2 +const static uint64_t SH_FLD_DGEN_RNDD_SEED0 = 5672; // 2 +const static uint64_t SH_FLD_DGEN_RNDD_SEED0_LEN = 5673; // 2 +const static uint64_t SH_FLD_DGEN_RNDD_SEED1 = 5674; // 2 +const static uint64_t SH_FLD_DGEN_RNDD_SEED1_LEN = 5675; // 2 +const static uint64_t SH_FLD_DGEN_RNDD_SEED2 = 5676; // 2 +const static uint64_t SH_FLD_DGEN_RNDD_SEED2_LEN = 5677; // 2 +const static uint64_t SH_FLD_DIAG_0 = 5678; // 2 +const static uint64_t SH_FLD_DIAG_1 = 5679; // 1 +const static uint64_t SH_FLD_DIAG_2 = 5680; // 1 +const static uint64_t SH_FLD_DIAG_3 = 5681; // 1 +const static uint64_t SH_FLD_DIB01_ERR = 5682; // 2 +const static uint64_t SH_FLD_DIB01_SPARE = 5683; // 1 +const static uint64_t SH_FLD_DIB01_SPARE_LEN = 5684; // 1 +const static uint64_t SH_FLD_DIB23_ERR = 5685; // 2 +const static uint64_t SH_FLD_DIB45_ERR = 5686; // 2 +const static uint64_t SH_FLD_DIB67_ERR = 5687; // 1 +const static uint64_t SH_FLD_DIB67_SPARE = 5688; // 1 +const static uint64_t SH_FLD_DIB67_SPARE_LEN = 5689; // 1 +const static uint64_t SH_FLD_DIGITAL_EYE = 5690; // 8 +const static uint64_t SH_FLD_DIRECT_ATTACH_MODE = 5691; // 4 +const static uint64_t SH_FLD_DIRECT_BRIDGE_SOURCE = 5692; // 1 +const static uint64_t SH_FLD_DIR_CE_DETECTED = 5693; // 12 +const static uint64_t SH_FLD_DIR_PERR_CHK_DIS = 5694; // 2 +const static uint64_t SH_FLD_DIR_SBCE_REPAIR_FAILED = 5695; // 12 +const static uint64_t SH_FLD_DIR_STUCK_BIT_CE = 5696; // 12 +const static uint64_t SH_FLD_DIR_UE_DETECTED = 5697; // 12 +const static uint64_t SH_FLD_DISABLE = 5698; // 2 +const static uint64_t SH_FLD_DISABLE_1 = 5699; // 1 +const static uint64_t SH_FLD_DISABLE_1_LEN = 5700; // 1 +const static uint64_t SH_FLD_DISABLE_2 = 5701; // 1 +const static uint64_t SH_FLD_DISABLE_2K_SPEC_FILTER = 5702; // 4 +const static uint64_t SH_FLD_DISABLE_2N_MODE = 5703; // 2 +const static uint64_t SH_FLD_DISABLE_2TO12_CLEAR = 5704; // 4 +const static uint64_t SH_FLD_DISABLE_2_LEN = 5705; // 1 +const static uint64_t SH_FLD_DISABLE_ALL_SPEC_OPS = 5706; // 4 +const static uint64_t SH_FLD_DISABLE_BANK_PDWN = 5707; // 2 +const static uint64_t SH_FLD_DISABLE_BYPASS_IN_READ_DATAFLOW = 5708; // 4 +const static uint64_t SH_FLD_DISABLE_CENTAUR_BAD_CRESP = 5709; // 4 +const static uint64_t SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH = 5710; // 4 +const static uint64_t SH_FLD_DISABLE_CENTAUR_CMD_PREFETCH_LEN = 5711; // 4 +const static uint64_t SH_FLD_DISABLE_CHARB_BYPASS = 5712; // 4 +const static uint64_t SH_FLD_DISABLE_CHECKIN_HANG_TIMER = 5713; // 1 +const static uint64_t SH_FLD_DISABLE_CHECKOUT_HANG_TIMER = 5714; // 1 +const static uint64_t SH_FLD_DISABLE_CHECKSTOP = 5715; // 1 +const static uint64_t SH_FLD_DISABLE_CI = 5716; // 4 +const static uint64_t SH_FLD_DISABLE_CI_LEN = 5717; // 4 +const static uint64_t SH_FLD_DISABLE_CL_AO_QUEUES = 5718; // 4 +const static uint64_t SH_FLD_DISABLE_COMMAND_BYPASS = 5719; // 4 +const static uint64_t SH_FLD_DISABLE_COMMAND_BYPASS_LEN = 5720; // 4 +const static uint64_t SH_FLD_DISABLE_COMPRESSION = 5721; // 90 +const static uint64_t SH_FLD_DISABLE_CRC_ECC_BYPASS = 5722; // 4 +const static uint64_t SH_FLD_DISABLE_CRC_ECC_BYPASS_LEN = 5723; // 4 +const static uint64_t SH_FLD_DISABLE_CRC_ECC_FP_BYPASS = 5724; // 4 +const static uint64_t SH_FLD_DISABLE_DROPABLE = 5725; // 8 +const static uint64_t SH_FLD_DISABLE_ECC = 5726; // 1 +const static uint64_t SH_FLD_DISABLE_ECC_ARRAY_CHK = 5727; // 2 +const static uint64_t SH_FLD_DISABLE_ECC_ARRAY_CORRECTION = 5728; // 2 +const static uint64_t SH_FLD_DISABLE_ECC_CHK = 5729; // 1 +const static uint64_t SH_FLD_DISABLE_ECC_CORRECTION = 5730; // 1 +const static uint64_t SH_FLD_DISABLE_ECC_COR_GXC_PSI = 5731; // 1 +const static uint64_t SH_FLD_DISABLE_ECC_COR_RXRF_PSI = 5732; // 1 +const static uint64_t SH_FLD_DISABLE_ECC_COR_TXRF_PSI = 5733; // 1 +const static uint64_t SH_FLD_DISABLE_ERR_CMD = 5734; // 1 +const static uint64_t SH_FLD_DISABLE_EXTRA_FIFO_ACCESSES = 5735; // 1 +const static uint64_t SH_FLD_DISABLE_EXTRA_HASH_ACCESSES = 5736; // 1 +const static uint64_t SH_FLD_DISABLE_FAR_HISTORY = 5737; // 1 +const static uint64_t SH_FLD_DISABLE_FASTPATH = 5738; // 4 +const static uint64_t SH_FLD_DISABLE_FENCE_RESET = 5739; // 4 +const static uint64_t SH_FLD_DISABLE_FLOW_SCOPE = 5740; // 1 +const static uint64_t SH_FLD_DISABLE_FP_COMMAND_BYPASS = 5741; // 4 +const static uint64_t SH_FLD_DISABLE_FP_M_BIT = 5742; // 4 +const static uint64_t SH_FLD_DISABLE_G = 5743; // 1 +const static uint64_t SH_FLD_DISABLE_G_RD = 5744; // 1 +const static uint64_t SH_FLD_DISABLE_G_WR = 5745; // 1 +const static uint64_t SH_FLD_DISABLE_H1_CLEAR = 5746; // 6 +const static uint64_t SH_FLD_DISABLE_HIGH_PRIORITY = 5747; // 4 +const static uint64_t SH_FLD_DISABLE_HIGH_PRIORITY_LEN = 5748; // 4 +const static uint64_t SH_FLD_DISABLE_HIT_UNDER_BARRIER = 5749; // 1 +const static uint64_t SH_FLD_DISABLE_HTM_CMD = 5750; // 1 +const static uint64_t SH_FLD_DISABLE_INJECT = 5751; // 1 +const static uint64_t SH_FLD_DISABLE_LFSR = 5752; // 1 +const static uint64_t SH_FLD_DISABLE_LN = 5753; // 1 +const static uint64_t SH_FLD_DISABLE_LN_RD = 5754; // 1 +const static uint64_t SH_FLD_DISABLE_LN_WR = 5755; // 1 +const static uint64_t SH_FLD_DISABLE_LPC_CMDS = 5756; // 3 +const static uint64_t SH_FLD_DISABLE_MDI0 = 5757; // 4 +const static uint64_t SH_FLD_DISABLE_MDI0_LEN = 5758; // 4 +const static uint64_t SH_FLD_DISABLE_MEMCTL_CAL = 5759; // 8 +const static uint64_t SH_FLD_DISABLE_NEAR_HISTORY = 5760; // 1 +const static uint64_t SH_FLD_DISABLE_NN_RD = 5761; // 1 +const static uint64_t SH_FLD_DISABLE_NN_RN = 5762; // 1 +const static uint64_t SH_FLD_DISABLE_NN_WR = 5763; // 1 +const static uint64_t SH_FLD_DISABLE_PARITY_CHECKER = 5764; // 8 +const static uint64_t SH_FLD_DISABLE_PCB_ITR = 5765; // 43 +const static uint64_t SH_FLD_DISABLE_PERFMON_RESET_ON_START = 5766; // 4 +const static uint64_t SH_FLD_DISABLE_PMISC = 5767; // 9 +const static uint64_t SH_FLD_DISABLE_PMU_SNOOPING = 5768; // 1 +const static uint64_t SH_FLD_DISABLE_PROMOTE = 5769; // 1 +const static uint64_t SH_FLD_DISABLE_PTAG_IN_AIBTAG = 5770; // 1 +const static uint64_t SH_FLD_DISABLE_RCMD_CLKGATE = 5771; // 3 +const static uint64_t SH_FLD_DISABLE_RESET_2K_COUNT_IF_HINT_BIT_SET = 5772; // 4 +const static uint64_t SH_FLD_DISABLE_RETRY_LOST_CLAIM = 5773; // 4 +const static uint64_t SH_FLD_DISABLE_SHARD_PRESP_ABORT = 5774; // 4 +const static uint64_t SH_FLD_DISABLE_SPEC_DISABLE_HINT_BIT = 5775; // 4 +const static uint64_t SH_FLD_DISABLE_SPEC_OP = 5776; // 4 +const static uint64_t SH_FLD_DISABLE_SPEC_OP_LEN = 5777; // 4 +const static uint64_t SH_FLD_DISABLE_SPEC_SOURCE_SCOPE = 5778; // 4 +const static uint64_t SH_FLD_DISABLE_SPEC_SOURCE_SCOPE_LEN = 5779; // 4 +const static uint64_t SH_FLD_DISABLE_STICKINESS = 5780; // 43 +const static uint64_t SH_FLD_DISABLE_TIMEOUT = 5781; // 1 +const static uint64_t SH_FLD_DISABLE_TIMEOUT_AND_RETRY = 5782; // 1 +const static uint64_t SH_FLD_DISABLE_TOD_CMD = 5783; // 1 +const static uint64_t SH_FLD_DISABLE_TRACE_CMD = 5784; // 1 +const static uint64_t SH_FLD_DISABLE_VG_NOT_SYS = 5785; // 1 +const static uint64_t SH_FLD_DISABLE_VG_RD = 5786; // 1 +const static uint64_t SH_FLD_DISABLE_VG_WR = 5787; // 1 +const static uint64_t SH_FLD_DISABLE_WRP = 5788; // 1 +const static uint64_t SH_FLD_DISABLE_XSCOM_CMD = 5789; // 1 +const static uint64_t SH_FLD_DISPATCH_SLOT_KILLED_CNT = 5790; // 1 +const static uint64_t SH_FLD_DISPATCH_SLOT_KILLED_CNT_LEN = 5791; // 1 +const static uint64_t SH_FLD_DISTRIBUTION_BROADCAST_MODE_ENABLE = 5792; // 1 +const static uint64_t SH_FLD_DISTR_STEP_SYNC_TX_DISABLE = 5793; // 1 +const static uint64_t SH_FLD_DISTR_STEP_SYNC_TX_SYNC_DISABLE = 5794; // 1 +const static uint64_t SH_FLD_DISTR_STEP_SYNC_TX_TRIGGER = 5795; // 1 +const static uint64_t SH_FLD_DIS_AIB_IN_ECC_CORRECTION = 5796; // 1 +const static uint64_t SH_FLD_DIS_ARX_ECC_CORRECTION = 5797; // 1 +const static uint64_t SH_FLD_DIS_AT_SRAM_ECC_CORRECTION = 5798; // 1 +const static uint64_t SH_FLD_DIS_BAR_SRAM_ECC_CORRECTION = 5799; // 1 +const static uint64_t SH_FLD_DIS_CHGRATE_COUNT = 5800; // 1 +const static uint64_t SH_FLD_DIS_CPM_BUBBLE_CORR = 5801; // 43 +const static uint64_t SH_FLD_DIS_CTRLBUF_ECC_CORRECTION = 5802; // 1 +const static uint64_t SH_FLD_DIS_DATA_ECC_CORRECTION = 5803; // 4 +const static uint64_t SH_FLD_DIS_DATA_ECC_CORRECTION_LEN = 5804; // 4 +const static uint64_t SH_FLD_DIS_DMA_W = 5805; // 1 +const static uint64_t SH_FLD_DIS_ECCCHK = 5806; // 1 +const static uint64_t SH_FLD_DIS_ECCCHK_CLO = 5807; // 1 +const static uint64_t SH_FLD_DIS_ECCCHK_IN = 5808; // 1 +const static uint64_t SH_FLD_DIS_ECCCHK_LDO = 5809; // 1 +const static uint64_t SH_FLD_DIS_ECCCHK_STO = 5810; // 1 +const static uint64_t SH_FLD_DIS_ECCCHK_WRO = 5811; // 1 +const static uint64_t SH_FLD_DIS_GLOB_SCOM = 5812; // 2 +const static uint64_t SH_FLD_DIS_IRQ_ECC_CORRECTION = 5813; // 1 +const static uint64_t SH_FLD_DIS_LD_ECC_CORRECTION = 5814; // 1 +const static uint64_t SH_FLD_DIS_MASTER_RD_PIPE = 5815; // 1 +const static uint64_t SH_FLD_DIS_MASTER_WR_PIPE = 5816; // 1 +const static uint64_t SH_FLD_DIS_MSTID_MATCH_PREF_INV = 5817; // 1 +const static uint64_t SH_FLD_DIS_NCNP = 5818; // 1 +const static uint64_t SH_FLD_DIS_PTAG_ECC_CORRECTION = 5819; // 1 +const static uint64_t SH_FLD_DIS_PTAG_ECC_CORRECTION_LEN = 5820; // 1 +const static uint64_t SH_FLD_DIS_REARB = 5821; // 1 +const static uint64_t SH_FLD_DIS_RECOVERY = 5822; // 24 +const static uint64_t SH_FLD_DIS_REREQUEST_TO = 5823; // 1 +const static uint64_t SH_FLD_DIS_SLAVE_RDPIPE = 5824; // 1 +const static uint64_t SH_FLD_DIS_SLAVE_WRPIPE = 5825; // 1 +const static uint64_t SH_FLD_DIS_STATE_ECC_CORRECTION = 5826; // 4 +const static uint64_t SH_FLD_DIS_STATE_ECC_CORRECTION_LEN = 5827; // 2 +const static uint64_t SH_FLD_DIS_TAG_ECC_CORRECTION = 5828; // 4 +const static uint64_t SH_FLD_DIS_TAG_ECC_CORRECTION_LEN = 5829; // 4 +const static uint64_t SH_FLD_DIS_TAG_SRAM_ECC_CORRECTION = 5830; // 1 +const static uint64_t SH_FLD_DIS_TRACE_EXTRA = 5831; // 17 +const static uint64_t SH_FLD_DIS_TRACE_STALL = 5832; // 17 +const static uint64_t SH_FLD_DIS_WRITE_GATHER = 5833; // 4 +const static uint64_t SH_FLD_DIVIDER_MODE = 5834; // 12 +const static uint64_t SH_FLD_DIVIDER_MODE_LEN = 5835; // 12 +const static uint64_t SH_FLD_DIVSELB = 5836; // 10 +const static uint64_t SH_FLD_DIVSELB_LEN = 5837; // 10 +const static uint64_t SH_FLD_DIVSELFB = 5838; // 10 +const static uint64_t SH_FLD_DIVSELFB_LEN = 5839; // 10 +const static uint64_t SH_FLD_DIV_PARITY = 5840; // 43 +const static uint64_t SH_FLD_DLL = 5841; // 8 +const static uint64_t SH_FLD_DLL_CLOCK_GATE = 5842; // 8 +const static uint64_t SH_FLD_DL_RETURN_P0 = 5843; // 43 +const static uint64_t SH_FLD_DL_RETURN_WDATA_PARITY = 5844; // 43 +const static uint64_t SH_FLD_DMAP_MODE_EN = 5845; // 2 +const static uint64_t SH_FLD_DMA_CH0_IDLE = 5846; // 1 +const static uint64_t SH_FLD_DMA_CH1_IDLE = 5847; // 1 +const static uint64_t SH_FLD_DMA_CH2_IDLE = 5848; // 1 +const static uint64_t SH_FLD_DMA_CH3_IDLE = 5849; // 1 +const static uint64_t SH_FLD_DMA_CH4_IDLE = 5850; // 1 +const static uint64_t SH_FLD_DMA_CRBARRAY_ACTION = 5851; // 1 +const static uint64_t SH_FLD_DMA_CRBARRAY_ENA = 5852; // 1 +const static uint64_t SH_FLD_DMA_CRBARRAY_SELECT = 5853; // 1 +const static uint64_t SH_FLD_DMA_CRBARRAY_TYPE = 5854; // 1 +const static uint64_t SH_FLD_DMA_EGRARRAY_ACTION = 5855; // 1 +const static uint64_t SH_FLD_DMA_EGRARRAY_ENA = 5856; // 1 +const static uint64_t SH_FLD_DMA_EGRARRAY_SELECT = 5857; // 1 +const static uint64_t SH_FLD_DMA_EGRARRAY_SELECT_LEN = 5858; // 1 +const static uint64_t SH_FLD_DMA_EGRARRAY_TYPE = 5859; // 1 +const static uint64_t SH_FLD_DMA_INGARRAY_ACTION = 5860; // 1 +const static uint64_t SH_FLD_DMA_INGARRAY_ENA = 5861; // 1 +const static uint64_t SH_FLD_DMA_INGARRAY_SELECT = 5862; // 1 +const static uint64_t SH_FLD_DMA_INGARRAY_SELECT_LEN = 5863; // 1 +const static uint64_t SH_FLD_DMA_INGARRAY_TYPE = 5864; // 1 +const static uint64_t SH_FLD_DMA_INWR_ACTION = 5865; // 1 +const static uint64_t SH_FLD_DMA_INWR_ENA = 5866; // 1 +const static uint64_t SH_FLD_DMA_INWR_TYPE = 5867; // 1 +const static uint64_t SH_FLD_DMA_MUX_SELECT = 5868; // 1 +const static uint64_t SH_FLD_DMA_MUX_SELECT_LEN = 5869; // 1 +const static uint64_t SH_FLD_DMA_OUTWR_ACTION = 5870; // 1 +const static uint64_t SH_FLD_DMA_OUTWR_ENA = 5871; // 1 +const static uint64_t SH_FLD_DMA_OUTWR_QW0_UEINJ_ENA = 5872; // 1 +const static uint64_t SH_FLD_DMA_OUTWR_QW4_UEINJ_ENA = 5873; // 1 +const static uint64_t SH_FLD_DMA_OUTWR_TYPE = 5874; // 1 +const static uint64_t SH_FLD_DMA_PARTIAL_WRT_NOT_INJECT = 5875; // 1 +const static uint64_t SH_FLD_DMA_PART_WR_NOT_INJ = 5876; // 1 +const static uint64_t SH_FLD_DMA_RD_DISABLE_GROUP = 5877; // 2 +const static uint64_t SH_FLD_DMA_RD_DISABLE_LN = 5878; // 2 +const static uint64_t SH_FLD_DMA_RD_DISABLE_NN_RN = 5879; // 2 +const static uint64_t SH_FLD_DMA_RD_DISABLE_VG_NOT_SYS = 5880; // 2 +const static uint64_t SH_FLD_DMA_RD_VG_RESET_TIMER_MASK = 5881; // 2 +const static uint64_t SH_FLD_DMA_RD_VG_RESET_TIMER_MASK_LEN = 5882; // 2 +const static uint64_t SH_FLD_DMA_RD_VG_RST_TMASK = 5883; // 1 +const static uint64_t SH_FLD_DMA_RD_VG_RST_TMASK_LEN = 5884; // 1 +const static uint64_t SH_FLD_DMA_READ = 5885; // 3 +const static uint64_t SH_FLD_DMA_READ_LEN = 5886; // 3 +const static uint64_t SH_FLD_DMA_STOPPED_STATE = 5887; // 32 +const static uint64_t SH_FLD_DMA_STOPPED_STATE_LEN = 5888; // 16 +const static uint64_t SH_FLD_DMA_TIMER_ENBL = 5889; // 1 +const static uint64_t SH_FLD_DMA_TIMER_REF_DIV = 5890; // 1 +const static uint64_t SH_FLD_DMA_TIMER_REF_DIV_LEN = 5891; // 1 +const static uint64_t SH_FLD_DMA_WRITE = 5892; // 3 +const static uint64_t SH_FLD_DMA_WRITE_LEN = 5893; // 2 +const static uint64_t SH_FLD_DMA_WR_DISABLE_GROUP = 5894; // 2 +const static uint64_t SH_FLD_DMA_WR_DISABLE_LN = 5895; // 2 +const static uint64_t SH_FLD_DMA_WR_DISABLE_NN_RN = 5896; // 2 +const static uint64_t SH_FLD_DMA_WR_DISABLE_VG_NOT_SYS = 5897; // 2 +const static uint64_t SH_FLD_DMA_WR_NOT_INJ = 5898; // 1 +const static uint64_t SH_FLD_DMA_WR_NOT_INJECT = 5899; // 1 +const static uint64_t SH_FLD_DMA_WR_VG_RESET_TIMER_MASK = 5900; // 2 +const static uint64_t SH_FLD_DMA_WR_VG_RESET_TIMER_MASK_LEN = 5901; // 2 +const static uint64_t SH_FLD_DMA_WR_VG_RST_TMASK = 5902; // 1 +const static uint64_t SH_FLD_DMA_WR_VG_RST_TMASK_LEN = 5903; // 1 +const static uint64_t SH_FLD_DNFIFO_DEQUEUED_EOT_FLAG = 5904; // 1 +const static uint64_t SH_FLD_DNFIFO_FIFO_EMPTY = 5905; // 1 +const static uint64_t SH_FLD_DNFIFO_FIFO_ENTRY_COUNT = 5906; // 1 +const static uint64_t SH_FLD_DNFIFO_FIFO_ENTRY_COUNT_LEN = 5907; // 1 +const static uint64_t SH_FLD_DNFIFO_FIFO_EOT_FLAGS = 5908; // 1 +const static uint64_t SH_FLD_DNFIFO_FIFO_EOT_FLAGS_LEN = 5909; // 1 +const static uint64_t SH_FLD_DNFIFO_FIFO_FULL = 5910; // 1 +const static uint64_t SH_FLD_DNFIFO_FIFO_VALID_FLAGS = 5911; // 1 +const static uint64_t SH_FLD_DNFIFO_FIFO_VALID_FLAGS_LEN = 5912; // 1 +const static uint64_t SH_FLD_DNFIFO_REQ_RESET_FR_SBE = 5913; // 1 +const static uint64_t SH_FLD_DNFIFO_REQ_RESET_FR_SP = 5914; // 1 +const static uint64_t SH_FLD_DOB01_CE = 5915; // 4 +const static uint64_t SH_FLD_DOB01_ERR = 5916; // 2 +const static uint64_t SH_FLD_DOB01_SUE = 5917; // 4 +const static uint64_t SH_FLD_DOB01_UE = 5918; // 4 +const static uint64_t SH_FLD_DOB23_CE = 5919; // 4 +const static uint64_t SH_FLD_DOB23_ERR = 5920; // 2 +const static uint64_t SH_FLD_DOB23_SUE = 5921; // 4 +const static uint64_t SH_FLD_DOB23_UE = 5922; // 4 +const static uint64_t SH_FLD_DOB45_CE = 5923; // 4 +const static uint64_t SH_FLD_DOB45_ERR = 5924; // 2 +const static uint64_t SH_FLD_DOB45_SUE = 5925; // 4 +const static uint64_t SH_FLD_DOB45_UE = 5926; // 4 +const static uint64_t SH_FLD_DOB67_CE = 5927; // 2 +const static uint64_t SH_FLD_DOB67_ERR = 5928; // 1 +const static uint64_t SH_FLD_DOB67_SUE = 5929; // 2 +const static uint64_t SH_FLD_DOB67_UE = 5930; // 2 +const static uint64_t SH_FLD_DONE = 5931; // 23 +const static uint64_t SH_FLD_DOORBELL0_C0 = 5932; // 12 +const static uint64_t SH_FLD_DOORBELL0_C1 = 5933; // 12 +const static uint64_t SH_FLD_DOORBELL1_C0 = 5934; // 12 +const static uint64_t SH_FLD_DOORBELL1_C1 = 5935; // 12 +const static uint64_t SH_FLD_DOORBELL2_C0 = 5936; // 12 +const static uint64_t SH_FLD_DOORBELL2_C1 = 5937; // 12 +const static uint64_t SH_FLD_DOORBELL3_C0 = 5938; // 12 +const static uint64_t SH_FLD_DOORBELL3_C1 = 5939; // 12 +const static uint64_t SH_FLD_DOUBLE_EPSILON_LENGTH = 5940; // 4 +const static uint64_t SH_FLD_DO_DR = 5941; // 1 +const static uint64_t SH_FLD_DO_IR = 5942; // 1 +const static uint64_t SH_FLD_DO_TAP_RESET = 5943; // 1 +const static uint64_t SH_FLD_DPLL_DCO_EMPTY = 5944; // 6 +const static uint64_t SH_FLD_DPLL_DCO_FULL = 5945; // 6 +const static uint64_t SH_FLD_DPLL_DYN_FMIN = 5946; // 6 +const static uint64_t SH_FLD_DPLL_INT = 5947; // 6 +const static uint64_t SH_FLD_DPLL_TEST_SEL = 5948; // 43 +const static uint64_t SH_FLD_DPLL_TEST_SEL_LEN = 5949; // 43 +const static uint64_t SH_FLD_DP_ERROR = 5950; // 8 +const static uint64_t SH_FLD_DP_ERROR_FINE = 5951; // 8 +const static uint64_t SH_FLD_DP_GOOD = 5952; // 8 +const static uint64_t SH_FLD_DQS = 5953; // 8 +const static uint64_t SH_FLD_DQS_ALIGN = 5954; // 8 +const static uint64_t SH_FLD_DQ_SEL_LANE = 5955; // 8 +const static uint64_t SH_FLD_DQ_SEL_LANE_LEN = 5956; // 8 +const static uint64_t SH_FLD_DQ_SEL_QUAD = 5957; // 8 +const static uint64_t SH_FLD_DQ_SEL_QUAD_LEN = 5958; // 8 +const static uint64_t SH_FLD_DRAM_ABIST_DONE_DC = 5959; // 43 +const static uint64_t SH_FLD_DROPOUT_DETECT = 5960; // 12 +const static uint64_t SH_FLD_DROP_COUNTER_FULL = 5961; // 4 +const static uint64_t SH_FLD_DROP_MASK_0_5 = 5962; // 1 +const static uint64_t SH_FLD_DROP_MASK_0_5_LEN = 5963; // 1 +const static uint64_t SH_FLD_DROP_PRIORITY_MASK = 5964; // 12 +const static uint64_t SH_FLD_DROP_PRIORITY_MASK_LEN = 5965; // 12 +const static uint64_t SH_FLD_DROP_PRIORITY_MODE = 5966; // 2 +const static uint64_t SH_FLD_DROP_PRI_DMA = 5967; // 1 +const static uint64_t SH_FLD_DROP_PRI_HPC_READ = 5968; // 1 +const static uint64_t SH_FLD_DROP_PRI_INTRP = 5969; // 1 +const static uint64_t SH_FLD_DRTM_REQ = 5970; // 5 +const static uint64_t SH_FLD_DRV_CLK_PATTERN_GCRMSG = 5971; // 4 +const static uint64_t SH_FLD_DRV_CLK_PATTERN_GCRMSG_LEN = 5972; // 4 +const static uint64_t SH_FLD_DRV_DATA_PATTERN_GCRMSG = 5973; // 6 +const static uint64_t SH_FLD_DRV_DATA_PATTERN_GCRMSG_LEN = 5974; // 6 +const static uint64_t SH_FLD_DRV_PATTERN_EN = 5975; // 1 +const static uint64_t SH_FLD_DSC1_ABORT_1 = 5976; // 1 +const static uint64_t SH_FLD_DSC1_DATA_COUNT = 5977; // 1 +const static uint64_t SH_FLD_DSC1_DATA_COUNT_1B = 5978; // 1 +const static uint64_t SH_FLD_DSC1_DATA_COUNT_1B_LEN = 5979; // 1 +const static uint64_t SH_FLD_DSC1_DATA_COUNT_LEN = 5980; // 1 +const static uint64_t SH_FLD_DSC1_HEADER_COUNT = 5981; // 1 +const static uint64_t SH_FLD_DSC1_HEADER_COUNT_1B = 5982; // 1 +const static uint64_t SH_FLD_DSC1_HEADER_COUNT_1B_LEN = 5983; // 1 +const static uint64_t SH_FLD_DSC1_HEADER_COUNT_LEN = 5984; // 1 +const static uint64_t SH_FLD_DSC1_LBUS_SLAVE_1B_PENDING = 5985; // 1 +const static uint64_t SH_FLD_DSC1_PERMISSION_TO_SEND_1 = 5986; // 1 +const static uint64_t SH_FLD_DSC1_PIB_SLAVE_PENDING = 5987; // 1 +const static uint64_t SH_FLD_DSC1_UNUSED_24 = 5988; // 1 +const static uint64_t SH_FLD_DSC1_UNUSED_27 = 5989; // 1 +const static uint64_t SH_FLD_DSC1_XDN_1 = 5990; // 1 +const static uint64_t SH_FLD_DSC1_XUP_1 = 5991; // 1 +const static uint64_t SH_FLD_DSC2_ABORT_2 = 5992; // 1 +const static uint64_t SH_FLD_DSC2_DATA_COUNT = 5993; // 1 +const static uint64_t SH_FLD_DSC2_DATA_COUNT_2B = 5994; // 1 +const static uint64_t SH_FLD_DSC2_DATA_COUNT_2B_LEN = 5995; // 1 +const static uint64_t SH_FLD_DSC2_DATA_COUNT_LEN = 5996; // 1 +const static uint64_t SH_FLD_DSC2_HEADER_COUNT = 5997; // 1 +const static uint64_t SH_FLD_DSC2_HEADER_COUNT_2B = 5998; // 1 +const static uint64_t SH_FLD_DSC2_HEADER_COUNT_2B_LEN = 5999; // 1 +const static uint64_t SH_FLD_DSC2_HEADER_COUNT_LEN = 6000; // 1 +const static uint64_t SH_FLD_DSC2_LBUS_SLAVE_2B_PENDING = 6001; // 1 +const static uint64_t SH_FLD_DSC2_PERMISSION_TO_SEND_2 = 6002; // 1 +const static uint64_t SH_FLD_DSC2_PIB_SLAVE_PENDING = 6003; // 1 +const static uint64_t SH_FLD_DSC2_UNUSED_24 = 6004; // 1 +const static uint64_t SH_FLD_DSC2_UNUSED_27 = 6005; // 1 +const static uint64_t SH_FLD_DSC2_XDN_2 = 6006; // 1 +const static uint64_t SH_FLD_DSC2_XUP_2 = 6007; // 1 +const static uint64_t SH_FLD_DSM_PE = 6008; // 8 +const static uint64_t SH_FLD_DS_SKEW_TIMEOUT_SEL = 6009; // 4 +const static uint64_t SH_FLD_DS_SKEW_TIMEOUT_SEL_LEN = 6010; // 4 +const static uint64_t SH_FLD_DS_TIMEOUT_SEL = 6011; // 4 +const static uint64_t SH_FLD_DS_TIMEOUT_SEL_LEN = 6012; // 4 +const static uint64_t SH_FLD_DTS_ENABLE_L1 = 6013; // 43 +const static uint64_t SH_FLD_DTS_ENABLE_L1_LEN = 6014; // 43 +const static uint64_t SH_FLD_DTS_READ_SEL = 6015; // 43 +const static uint64_t SH_FLD_DTS_READ_SEL_LEN = 6016; // 43 +const static uint64_t SH_FLD_DTS_SAMPLE_ENA = 6017; // 43 +const static uint64_t SH_FLD_DTS_TRIGGER = 6018; // 43 +const static uint64_t SH_FLD_DTS_TRIGGER_SEL = 6019; // 43 +const static uint64_t SH_FLD_DW0_ERR_TYPE = 6020; // 16 +const static uint64_t SH_FLD_DW0_ERR_TYPE_LEN = 6021; // 16 +const static uint64_t SH_FLD_DW0_SYNDROME = 6022; // 16 +const static uint64_t SH_FLD_DW0_SYNDROME_LEN = 6023; // 16 +const static uint64_t SH_FLD_DW1_ERR_TYPE = 6024; // 16 +const static uint64_t SH_FLD_DW1_ERR_TYPE_LEN = 6025; // 16 +const static uint64_t SH_FLD_DW1_SYNDROME = 6026; // 16 +const static uint64_t SH_FLD_DW1_SYNDROME_LEN = 6027; // 16 +const static uint64_t SH_FLD_DW2_ERR_TYPE = 6028; // 16 +const static uint64_t SH_FLD_DW2_ERR_TYPE_LEN = 6029; // 16 +const static uint64_t SH_FLD_DW2_SYNDROME = 6030; // 16 +const static uint64_t SH_FLD_DW2_SYNDROME_LEN = 6031; // 16 +const static uint64_t SH_FLD_DW3_ERR_TYPE = 6032; // 16 +const static uint64_t SH_FLD_DW3_ERR_TYPE_LEN = 6033; // 16 +const static uint64_t SH_FLD_DW3_SYNDROME = 6034; // 16 +const static uint64_t SH_FLD_DW3_SYNDROME_LEN = 6035; // 16 +const static uint64_t SH_FLD_DW_TYPE = 6036; // 12 +const static uint64_t SH_FLD_DW_TYPE_LEN = 6037; // 12 +const static uint64_t SH_FLD_DYNAMIC_MAX_SPARES_EXCEEDED = 6038; // 8 +const static uint64_t SH_FLD_DYNAMIC_REPAIR_ERROR = 6039; // 8 +const static uint64_t SH_FLD_DYNAMIC_SPARE_DEPLOYED = 6040; // 8 +const static uint64_t SH_FLD_DYNAMIC_WINDOW_SELECT = 6041; // 8 +const static uint64_t SH_FLD_DYNAMIC_WINDOW_SELECT_LEN = 6042; // 8 +const static uint64_t SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL = 6043; // 8 +const static uint64_t SH_FLD_DYN_RECAL_INTERVAL_TIMEOUT_SEL_LEN = 6044; // 8 +const static uint64_t SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL = 6045; // 4 +const static uint64_t SH_FLD_DYN_RECAL_OVERALL_TIMEOUT_SEL_LEN = 6046; // 4 +const static uint64_t SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL = 6047; // 8 +const static uint64_t SH_FLD_DYN_RECAL_STATUS_RPT_TIMEOUT_SEL_LEN = 6048; // 8 +const static uint64_t SH_FLD_DYN_RECAL_SUSPEND = 6049; // 4 +const static uint64_t SH_FLD_DYN_RECAL_TSR_IGNORE_GCRMSG = 6050; // 4 +const static uint64_t SH_FLD_DYN_RPR_BAD_BUS_MAX = 6051; // 4 +const static uint64_t SH_FLD_DYN_RPR_BAD_BUS_MAX_LEN = 6052; // 4 +const static uint64_t SH_FLD_DYN_RPR_BAD_LANE_MAX = 6053; // 4 +const static uint64_t SH_FLD_DYN_RPR_BAD_LANE_MAX_LEN = 6054; // 4 +const static uint64_t SH_FLD_DYN_RPR_CLR_ERR_CNTR1 = 6055; // 4 +const static uint64_t SH_FLD_DYN_RPR_CLR_ERR_CNTR2 = 6056; // 4 +const static uint64_t SH_FLD_DYN_RPR_COMPLETE_GCRMSG = 6057; // 4 +const static uint64_t SH_FLD_DYN_RPR_DISABLE = 6058; // 4 +const static uint64_t SH_FLD_DYN_RPR_DISABLE2 = 6059; // 4 +const static uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT = 6060; // 4 +const static uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_SHFT_AMT_LEN = 6061; // 4 +const static uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH = 6062; // 4 +const static uint64_t SH_FLD_DYN_RPR_ENC_BAD_DATA_LANE_WIDTH_LEN = 6063; // 4 +const static uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_DURATION = 6064; // 4 +const static uint64_t SH_FLD_DYN_RPR_ERR_CNTR1_DURATION_LEN = 6065; // 4 +const static uint64_t SH_FLD_DYN_RPR_ERR_CNTR2_DURATION = 6066; // 4 +const static uint64_t SH_FLD_DYN_RPR_ERR_CNTR2_DURATION_LEN = 6067; // 4 +const static uint64_t SH_FLD_DYN_RPR_IP_GCRMSG = 6068; // 4 +const static uint64_t SH_FLD_DYN_RPR_LANE2RPR_GCRMSG = 6069; // 4 +const static uint64_t SH_FLD_DYN_RPR_LANE2RPR_GCRMSG_LEN = 6070; // 4 +const static uint64_t SH_FLD_DYN_RPR_REQ_GCRMSG = 6071; // 4 +const static uint64_t SH_FLD_D_BIT_MAP = 6072; // 8 +const static uint64_t SH_FLD_D_BIT_MAP_LEN = 6073; // 8 +const static uint64_t SH_FLD_EARLY_REQ = 6074; // 8 +const static uint64_t SH_FLD_EARLY_REQ_ERR_MASK = 6075; // 8 +const static uint64_t SH_FLD_EARLY_REQ_SOURCE = 6076; // 8 +const static uint64_t SH_FLD_EARLY_REQ_SOURCE_LEN = 6077; // 8 +const static uint64_t SH_FLD_EBUS_ENABLE_0_15 = 6078; // 1 +const static uint64_t SH_FLD_EBUS_ENABLE_0_15_LEN = 6079; // 1 +const static uint64_t SH_FLD_ECC = 6080; // 3 +const static uint64_t SH_FLD_ECCCHK_DISABLE_0 = 6081; // 1 +const static uint64_t SH_FLD_ECCCHK_DISABLE_1 = 6082; // 1 +const static uint64_t SH_FLD_ECCCHK_DISABLE_2 = 6083; // 1 +const static uint64_t SH_FLD_ECCCHK_DISABLE_3 = 6084; // 1 +const static uint64_t SH_FLD_ECCGEN = 6085; // 8 +const static uint64_t SH_FLD_ECC_CE = 6086; // 3 +const static uint64_t SH_FLD_ECC_CHK_DISABLE = 6087; // 1 +const static uint64_t SH_FLD_ECC_CLEAR = 6088; // 2 +const static uint64_t SH_FLD_ECC_CONFIG_ERROR_0 = 6089; // 1 +const static uint64_t SH_FLD_ECC_CONFIG_ERROR_1 = 6090; // 1 +const static uint64_t SH_FLD_ECC_CONFIG_ERROR_2 = 6091; // 1 +const static uint64_t SH_FLD_ECC_CONFIG_ERROR_3 = 6092; // 1 +const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_0 = 6093; // 1 +const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_1 = 6094; // 1 +const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_2 = 6095; // 1 +const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_3 = 6096; // 1 +const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_FACES = 6097; // 1 +const static uint64_t SH_FLD_ECC_CORRECTED_ERROR_PIB = 6098; // 1 +const static uint64_t SH_FLD_ECC_CORRECTOR_INTERNAL_PARITY_ERROR = 6099; // 8 +const static uint64_t SH_FLD_ECC_CORRECT_DIS = 6100; // 16 +const static uint64_t SH_FLD_ECC_DEBUG_CHUNK_SELECT = 6101; // 8 +const static uint64_t SH_FLD_ECC_DEBUG_CHUNK_SELECT_LEN = 6102; // 8 +const static uint64_t SH_FLD_ECC_DEBUG_ENABLE = 6103; // 8 +const static uint64_t SH_FLD_ECC_DEBUG_PRIMARY_SELECT = 6104; // 8 +const static uint64_t SH_FLD_ECC_DEBUG_PRIMARY_SELECT_LEN = 6105; // 8 +const static uint64_t SH_FLD_ECC_DEBUG_SECONDARY_SELECT = 6106; // 8 +const static uint64_t SH_FLD_ECC_DEBUG_SECONDARY_SELECT_LEN = 6107; // 8 +const static uint64_t SH_FLD_ECC_DETECT_DIS = 6108; // 16 +const static uint64_t SH_FLD_ECC_ENABLE = 6109; // 6 +const static uint64_t SH_FLD_ECC_ENABLE_0 = 6110; // 1 +const static uint64_t SH_FLD_ECC_ENABLE_1 = 6111; // 1 +const static uint64_t SH_FLD_ECC_ENABLE_2 = 6112; // 1 +const static uint64_t SH_FLD_ECC_ENABLE_3 = 6113; // 1 +const static uint64_t SH_FLD_ECC_ERROR_ADDR = 6114; // 2 +const static uint64_t SH_FLD_ECC_ERROR_ADDR_LEN = 6115; // 2 +const static uint64_t SH_FLD_ECC_ERROR_COUNT = 6116; // 2 +const static uint64_t SH_FLD_ECC_ERROR_COUNT_LEN = 6117; // 2 +const static uint64_t SH_FLD_ECC_ERR_INJ_ARRAY_SEL = 6118; // 4 +const static uint64_t SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN = 6119; // 4 +const static uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_ENA = 6120; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_FRQ = 6121; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_TYP = 6122; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED = 6123; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED_LEN = 6124; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_PARTITION_SEL = 6125; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_PARTITION_SEL_LEN = 6126; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_SELECTION = 6127; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_SELECTION_LEN = 6128; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_ENA = 6129; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_FRQ = 6130; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_SEL = 6131; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_EG_TYP = 6132; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_UNUSED = 6133; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_UNUSED_LEN = 6134; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_ENA = 6135; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_FRQ = 6136; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_SEL = 6137; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_SEL_LEN = 6138; // 1 +const static uint64_t SH_FLD_ECC_ERR_INJ_SOUTH_WC_TYP = 6139; // 1 +const static uint64_t SH_FLD_ECC_GENERATOR_INTERNAL_PARITY_ERROR = 6140; // 8 +const static uint64_t SH_FLD_ECC_INJECT_ERR = 6141; // 16 +const static uint64_t SH_FLD_ECC_INJECT_TYPE = 6142; // 16 +const static uint64_t SH_FLD_ECC_LEN = 6143; // 3 +const static uint64_t SH_FLD_ECC_MCBIST_OUT_OF_SYNC_HOLD_OUT = 6144; // 2 +const static uint64_t SH_FLD_ECC_SYNDROME = 6145; // 2 +const static uint64_t SH_FLD_ECC_SYNDROME_LEN = 6146; // 2 +const static uint64_t SH_FLD_ECC_S_BIT_ERROR = 6147; // 1 +const static uint64_t SH_FLD_ECC_UE = 6148; // 3 +const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_0 = 6149; // 1 +const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_1 = 6150; // 1 +const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_2 = 6151; // 1 +const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_3 = 6152; // 1 +const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_FACES = 6153; // 1 +const static uint64_t SH_FLD_ECC_UNCORRECTED_ERROR_PIB = 6154; // 1 +const static uint64_t SH_FLD_ECC_UNCORRECTED_ERR_FACES = 6155; // 1 +const static uint64_t SH_FLD_ECC_UNCORRECTED_ERR_PIB = 6156; // 1 +const static uint64_t SH_FLD_ECC_WAT_ACTION_SELECT = 6157; // 8 +const static uint64_t SH_FLD_ECC_WAT_ENABLE = 6158; // 8 +const static uint64_t SH_FLD_ECC_WAT_SOURCE = 6159; // 8 +const static uint64_t SH_FLD_ECC_WAT_SOURCE_LEN = 6160; // 8 +const static uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE = 6161; // 8 +const static uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_LEN = 6162; // 8 +const static uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT = 6163; // 8 +const static uint64_t SH_FLD_ECC_WDF_HCA_TIMEBASE_SELECT_LEN = 6164; // 8 +const static uint64_t SH_FLD_ECHO_DELAY_CYCLES = 6165; // 2 +const static uint64_t SH_FLD_ECHO_DELAY_CYCLES_LEN = 6166; // 2 +const static uint64_t SH_FLD_ECRESP_HASH_MODE = 6167; // 4 +const static uint64_t SH_FLD_EDGE_TRIGGER_MODE1 = 6168; // 86 +const static uint64_t SH_FLD_EDGE_TRIGGER_MODE2 = 6169; // 86 +const static uint64_t SH_FLD_EDR = 6170; // 21 +const static uint64_t SH_FLD_EDRAM_PGATE = 6171; // 6 +const static uint64_t SH_FLD_EDRAM_SEQUENCE = 6172; // 6 +const static uint64_t SH_FLD_EDR_LEN = 6173; // 21 +const static uint64_t SH_FLD_EFTCOMP_MAX_INRD = 6174; // 1 +const static uint64_t SH_FLD_EFTCOMP_MAX_INRD_LEN = 6175; // 1 +const static uint64_t SH_FLD_EFTDECOMP_MAX_INRD = 6176; // 1 +const static uint64_t SH_FLD_EFTDECOMP_MAX_INRD_LEN = 6177; // 1 +const static uint64_t SH_FLD_EFT_COMP_PREFETCH_ENABLE = 6178; // 1 +const static uint64_t SH_FLD_EFT_DECOMP_PREFETCH_ENABLE = 6179; // 1 +const static uint64_t SH_FLD_EFT_MUX_SELECT = 6180; // 1 +const static uint64_t SH_FLD_EFT_MUX_SELECT_LEN = 6181; // 1 +const static uint64_t SH_FLD_EFT_SPBC_ENABLE = 6182; // 1 +const static uint64_t SH_FLD_EG_CERR_BIT10 = 6183; // 1 +const static uint64_t SH_FLD_EG_CERR_BIT11 = 6184; // 1 +const static uint64_t SH_FLD_EG_CERR_BIT4 = 6185; // 1 +const static uint64_t SH_FLD_EG_CERR_BIT5 = 6186; // 1 +const static uint64_t SH_FLD_EG_CERR_BIT6 = 6187; // 1 +const static uint64_t SH_FLD_EG_CERR_BIT7 = 6188; // 1 +const static uint64_t SH_FLD_EG_CERR_BIT8 = 6189; // 1 +const static uint64_t SH_FLD_EG_CERR_BIT9 = 6190; // 1 +const static uint64_t SH_FLD_EG_CERR_RESET = 6191; // 1 +const static uint64_t SH_FLD_EG_CERR_UNUSEDBITS = 6192; // 1 +const static uint64_t SH_FLD_EG_CERR_UNUSEDBITS_LEN = 6193; // 1 +const static uint64_t SH_FLD_EG_ECC_CE_ERROR = 6194; // 2 +const static uint64_t SH_FLD_EG_ECC_SUE_ERROR = 6195; // 2 +const static uint64_t SH_FLD_EG_ECC_UE_ERROR = 6196; // 2 +const static uint64_t SH_FLD_EG_LOGIC_HW_ERROR = 6197; // 2 +const static uint64_t SH_FLD_EG_TRACE_GROUP_SEL_HI = 6198; // 1 +const static uint64_t SH_FLD_EG_TRACE_GROUP_SEL_HI_LEN = 6199; // 1 +const static uint64_t SH_FLD_EG_TRACE_GROUP_SEL_LO = 6200; // 1 +const static uint64_t SH_FLD_EG_TRACE_GROUP_SEL_LO_LEN = 6201; // 1 +const static uint64_t SH_FLD_EG_TRACE_INT_DATA_HI = 6202; // 1 +const static uint64_t SH_FLD_EG_TRACE_INT_DATA_LO = 6203; // 1 +const static uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_01 = 6204; // 1 +const static uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_01_LEN = 6205; // 1 +const static uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_23 = 6206; // 1 +const static uint64_t SH_FLD_EG_TRACE_TRIGGER_SEL_23_LEN = 6207; // 1 +const static uint64_t SH_FLD_EICR_PE = 6208; // 8 +const static uint64_t SH_FLD_EMERGENCY_M = 6209; // 8 +const static uint64_t SH_FLD_EMERGENCY_M_LEN = 6210; // 8 +const static uint64_t SH_FLD_EMERGENCY_N = 6211; // 8 +const static uint64_t SH_FLD_EMERGENCY_N_LEN = 6212; // 8 +const static uint64_t SH_FLD_EMERGENCY_THROTTLE = 6213; // 16 +const static uint64_t SH_FLD_EMER_THROTTLE_IP = 6214; // 8 +const static uint64_t SH_FLD_EMER_THROTTLE_IP_CLR = 6215; // 8 +const static uint64_t SH_FLD_EN = 6216; // 53 +const static uint64_t SH_FLD_ENABLE = 6217; // 257 +const static uint64_t SH_FLD_ENABLE_0_7 = 6218; // 1 +const static uint64_t SH_FLD_ENABLE_0_7_LEN = 6219; // 1 +const static uint64_t SH_FLD_ENABLE_64_128B_READ = 6220; // 4 +const static uint64_t SH_FLD_ENABLE_AGGRESSIVE_BUSY = 6221; // 8 +const static uint64_t SH_FLD_ENABLE_APO_HANG = 6222; // 4 +const static uint64_t SH_FLD_ENABLE_AUX_PORT_UNUSED = 6223; // 2 +const static uint64_t SH_FLD_ENABLE_BER_TEST = 6224; // 4 +const static uint64_t SH_FLD_ENABLE_BUSY_COUNTERS = 6225; // 8 +const static uint64_t SH_FLD_ENABLE_CENTAUR_CHECKSTOP_COMMAND = 6226; // 4 +const static uint64_t SH_FLD_ENABLE_CENTAUR_PERFMON_START_COMMAND = 6227; // 4 +const static uint64_t SH_FLD_ENABLE_CENTAUR_PERFMON_STOP_COMMAND = 6228; // 4 +const static uint64_t SH_FLD_ENABLE_CENTAUR_SYNC = 6229; // 4 +const static uint64_t SH_FLD_ENABLE_CENTAUR_TRACESTOP_COMMAND = 6230; // 4 +const static uint64_t SH_FLD_ENABLE_CHANNEL_ARB_DISABLE_HP_OP_LFSR = 6231; // 4 +const static uint64_t SH_FLD_ENABLE_CHANNEL_ARB_FORCE_WR_HP_LFSR = 6232; // 4 +const static uint64_t SH_FLD_ENABLE_CLEAN = 6233; // 8 +const static uint64_t SH_FLD_ENABLE_CLIB_HANG = 6234; // 4 +const static uint64_t SH_FLD_ENABLE_CLR_ERR_CMD = 6235; // 1 +const static uint64_t SH_FLD_ENABLE_CM_COARSE_CAL = 6236; // 6 +const static uint64_t SH_FLD_ENABLE_CM_FINE_CAL = 6237; // 6 +const static uint64_t SH_FLD_ENABLE_CQ_PMU_COUNTING = 6238; // 1 +const static uint64_t SH_FLD_ENABLE_CQ_TRACE = 6239; // 1 +const static uint64_t SH_FLD_ENABLE_CRC_BYPASS_ALWAYS = 6240; // 4 +const static uint64_t SH_FLD_ENABLE_CRC_ECC_BPASS_NODAL_ONLY = 6241; // 4 +const static uint64_t SH_FLD_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 6242; // 6 +const static uint64_t SH_FLD_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 6243; // 6 +const static uint64_t SH_FLD_ENABLE_CTLE_COARSE_CAL = 6244; // 6 +const static uint64_t SH_FLD_ENABLE_CTLE_EDGE_OFFSET_CAL = 6245; // 2 +const static uint64_t SH_FLD_ENABLE_CTLE_EDGE_TRACK_ONLY = 6246; // 4 +const static uint64_t SH_FLD_ENABLE_DAC_H1_CAL = 6247; // 6 +const static uint64_t SH_FLD_ENABLE_DAC_H1_TO_A_CAL = 6248; // 4 +const static uint64_t SH_FLD_ENABLE_DDC = 6249; // 6 +const static uint64_t SH_FLD_ENABLE_DEBUG_BUS = 6250; // 1 +const static uint64_t SH_FLD_ENABLE_DFE_H1_CAL = 6251; // 6 +const static uint64_t SH_FLD_ENABLE_DFE_H2_H12_CAL = 6252; // 4 +const static uint64_t SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP = 6253; // 4 +const static uint64_t SH_FLD_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 6254; // 4 +const static uint64_t SH_FLD_ENABLE_DFE_VOLTAGE_MODE = 6255; // 4 +const static uint64_t SH_FLD_ENABLE_DISABLE_PREFETCH_FOR_MIRROR_READS = 6256; // 4 +const static uint64_t SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ = 6257; // 4 +const static uint64_t SH_FLD_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ = 6258; // 4 +const static uint64_t SH_FLD_ENABLE_DONE_SIGNALING = 6259; // 4 +const static uint64_t SH_FLD_ENABLE_DYNAMIC_PF_USAGE = 6260; // 8 +const static uint64_t SH_FLD_ENABLE_DYNAMIC_WR_USAGE = 6261; // 8 +const static uint64_t SH_FLD_ENABLE_EG_PMU_COUNTING = 6262; // 1 +const static uint64_t SH_FLD_ENABLE_EG_TRACE = 6263; // 1 +const static uint64_t SH_FLD_ENABLE_EMER_THROTTLE = 6264; // 4 +const static uint64_t SH_FLD_ENABLE_FINAL_L2U_ADJ = 6265; // 4 +const static uint64_t SH_FLD_ENABLE_FIR_HOST_ATTN = 6266; // 4 +const static uint64_t SH_FLD_ENABLE_FIR_SPEC_ATTN = 6267; // 4 +const static uint64_t SH_FLD_ENABLE_FMAX_TARGET = 6268; // 6 +const static uint64_t SH_FLD_ENABLE_FMIN_TARGET = 6269; // 6 +const static uint64_t SH_FLD_ENABLE_FSAFE_UPON_HEARTBEAT_LOSS = 6270; // 6 +const static uint64_t SH_FLD_ENABLE_GCR_OFL_BUFF = 6271; // 4 +const static uint64_t SH_FLD_ENABLE_GLB_PULSE = 6272; // 1 +const static uint64_t SH_FLD_ENABLE_GLOBAL_RUN = 6273; // 2 +const static uint64_t SH_FLD_ENABLE_H1AP_TWEAK = 6274; // 6 +const static uint64_t SH_FLD_ENABLE_HW_ERROR_RECOVERY = 6275; // 5 +const static uint64_t SH_FLD_ENABLE_INTEG_LATCH_OFFSET_CAL = 6276; // 6 +const static uint64_t SH_FLD_ENABLE_IN_PMU_COUNTING = 6277; // 1 +const static uint64_t SH_FLD_ENABLE_IN_TRACE = 6278; // 1 +const static uint64_t SH_FLD_ENABLE_IPOLL_AND_DMA = 6279; // 3 +const static uint64_t SH_FLD_ENABLE_JUMP_PROTECT = 6280; // 6 +const static uint64_t SH_FLD_ENABLE_JUMP_TARGET_UPDATE = 6281; // 6 +const static uint64_t SH_FLD_ENABLE_LEN = 6282; // 47 +const static uint64_t SH_FLD_ENABLE_MEMORY_BACKING = 6283; // 6 +const static uint64_t SH_FLD_ENABLE_MIRROR_HANG = 6284; // 4 +const static uint64_t SH_FLD_ENABLE_NONMIRROR_HANG = 6285; // 4 +const static uint64_t SH_FLD_ENABLE_PARITY_CHECK = 6286; // 3 +const static uint64_t SH_FLD_ENABLE_PB_SWITCH_AB = 6287; // 1 +const static uint64_t SH_FLD_ENABLE_PB_SWITCH_CD = 6288; // 1 +const static uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_EXTREME_DROOP = 6289; // 6 +const static uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_HEARTBEAT_LOSS = 6290; // 6 +const static uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_IVRM_DROPOUT = 6291; // 6 +const static uint64_t SH_FLD_ENABLE_PCB_INTR_UPON_LARGE_DROOP = 6292; // 6 +const static uint64_t SH_FLD_ENABLE_PECE = 6293; // 24 +const static uint64_t SH_FLD_ENABLE_PF_DROP_CMDLIST = 6294; // 4 +const static uint64_t SH_FLD_ENABLE_PF_DROP_SRQ = 6295; // 4 +const static uint64_t SH_FLD_ENABLE_PREFETCH_PROMOTE = 6296; // 4 +const static uint64_t SH_FLD_ENABLE_PROTECT_UPON_IVRM_DROPOUT = 6297; // 6 +const static uint64_t SH_FLD_ENABLE_READ_DATA_FROM_AMOC = 6298; // 8 +const static uint64_t SH_FLD_ENABLE_READ_DATA_FROM_AMOC_LEN = 6299; // 8 +const static uint64_t SH_FLD_ENABLE_READ_LFSR_DATA = 6300; // 4 +const static uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TOD = 6301; // 1 +const static uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER = 6302; // 1 +const static uint64_t SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER_LEN = 6303; // 1 +const static uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_DISP = 6304; // 8 +const static uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_NSQ = 6305; // 8 +const static uint64_t SH_FLD_ENABLE_REFRESH_BLOCK_SQ = 6306; // 8 +const static uint64_t SH_FLD_ENABLE_RELATIVE_ADDRESS_CMDS = 6307; // 3 +const static uint64_t SH_FLD_ENABLE_REMAP = 6308; // 1 +const static uint64_t SH_FLD_ENABLE_RESULT_CHECK = 6309; // 4 +const static uint64_t SH_FLD_ENABLE_RG_PMU_COUNTING = 6310; // 1 +const static uint64_t SH_FLD_ENABLE_RG_TRACE = 6311; // 1 +const static uint64_t SH_FLD_ENABLE_SCRD_FR_RXRF = 6312; // 1 +const static uint64_t SH_FLD_ENABLE_SCWR_TO_RXRF = 6313; // 1 +const static uint64_t SH_FLD_ENABLE_SCWR_TO_TXRF = 6314; // 1 +const static uint64_t SH_FLD_ENABLE_STREAMING_MODE = 6315; // 2 +const static uint64_t SH_FLD_ENABLE_TRC_GLB_TRIG0 = 6316; // 1 +const static uint64_t SH_FLD_ENABLE_TRC_GLB_TRIG1 = 6317; // 1 +const static uint64_t SH_FLD_ENABLE_TTYPE_DECODE = 6318; // 2 +const static uint64_t SH_FLD_ENABLE_VGA_AMAX_MODE = 6319; // 6 +const static uint64_t SH_FLD_ENABLE_VGA_CAL = 6320; // 6 +const static uint64_t SH_FLD_ENABLE_VGA_EDGE_OFFSET_CAL = 6321; // 2 +const static uint64_t SH_FLD_ENABLE_VITL_ALIGN_CHECK = 6322; // 43 +const static uint64_t SH_FLD_ENABLE_WC_TRACE = 6323; // 1 +const static uint64_t SH_FLD_ENABLE_ZCAL = 6324; // 8 +const static uint64_t SH_FLD_ENA_COARSE_RD = 6325; // 8 +const static uint64_t SH_FLD_ENA_CUSTOM_RD = 6326; // 8 +const static uint64_t SH_FLD_ENA_CUSTOM_WR = 6327; // 8 +const static uint64_t SH_FLD_ENA_DIGITAL_EYE = 6328; // 8 +const static uint64_t SH_FLD_ENA_DQS_ALIGN = 6329; // 16 +const static uint64_t SH_FLD_ENA_INITIAL_COARSE_WR = 6330; // 8 +const static uint64_t SH_FLD_ENA_INITIAL_PAT_WR = 6331; // 8 +const static uint64_t SH_FLD_ENA_RANK = 6332; // 8 +const static uint64_t SH_FLD_ENA_RANK_LEN = 6333; // 8 +const static uint64_t SH_FLD_ENA_RANK_PAIR = 6334; // 16 +const static uint64_t SH_FLD_ENA_RANK_PAIR_LEN = 6335; // 16 +const static uint64_t SH_FLD_ENA_RDCLK_ALIGN = 6336; // 16 +const static uint64_t SH_FLD_ENA_READ_CTR = 6337; // 16 +const static uint64_t SH_FLD_ENA_SYSCLK_ALIGN = 6338; // 8 +const static uint64_t SH_FLD_ENA_WRITE_CTR = 6339; // 8 +const static uint64_t SH_FLD_ENA_WR_LEVEL = 6340; // 8 +const static uint64_t SH_FLD_ENA_ZCAL = 6341; // 8 +const static uint64_t SH_FLD_END = 6342; // 64 +const static uint64_t SH_FLD_ENDABLE_PMU_CNT_RESET = 6343; // 1 +const static uint64_t SH_FLD_ENDPOINTS = 6344; // 1 +const static uint64_t SH_FLD_END_LANE_ID = 6345; // 8 +const static uint64_t SH_FLD_END_LANE_ID_LEN = 6346; // 8 +const static uint64_t SH_FLD_ENH_MODE_0 = 6347; // 1 +const static uint64_t SH_FLD_ENH_MODE_1 = 6348; // 1 +const static uint64_t SH_FLD_ENH_MODE_2 = 6349; // 1 +const static uint64_t SH_FLD_ENH_MODE_3 = 6350; // 1 +const static uint64_t SH_FLD_ENOP = 6351; // 43 +const static uint64_t SH_FLD_ENOP_FORCE_SG = 6352; // 43 +const static uint64_t SH_FLD_ENOP_LEN = 6353; // 43 +const static uint64_t SH_FLD_ENOP_WAIT = 6354; // 43 +const static uint64_t SH_FLD_ENOP_WAIT_LEN = 6355; // 43 +const static uint64_t SH_FLD_ENTRIES = 6356; // 1 +const static uint64_t SH_FLD_ENTRIES_LEN = 6357; // 1 +const static uint64_t SH_FLD_ENTRY = 6358; // 75 +const static uint64_t SH_FLD_ENTRY_LEN = 6359; // 75 +const static uint64_t SH_FLD_ENTRY_SEL_0_5 = 6360; // 1 +const static uint64_t SH_FLD_ENTRY_SEL_0_5_LEN = 6361; // 1 +const static uint64_t SH_FLD_EN_64_128_PB_READ = 6362; // 8 +const static uint64_t SH_FLD_EN_ATTN = 6363; // 24 +const static uint64_t SH_FLD_EN_CHARB_CMD_STALL = 6364; // 8 +const static uint64_t SH_FLD_EN_CHARB_MERGE_STALL = 6365; // 8 +const static uint64_t SH_FLD_EN_CHARB_RRQ_STALL = 6366; // 8 +const static uint64_t SH_FLD_EN_CHARB_STALL = 6367; // 4 +const static uint64_t SH_FLD_EN_CHARB_WRQ_STALL = 6368; // 8 +const static uint64_t SH_FLD_EN_DBG = 6369; // 4 +const static uint64_t SH_FLD_EN_EVENT_COUNT = 6370; // 1 +const static uint64_t SH_FLD_EN_INSTRUC_TRACE = 6371; // 24 +const static uint64_t SH_FLD_EN_MARKER_ACK = 6372; // 1 +const static uint64_t SH_FLD_EN_OR_DIS_WRITE_PROTECTION = 6373; // 1 +const static uint64_t SH_FLD_EN_OR_DIS_WRITE_PROTECTION_LEN = 6374; // 1 +const static uint64_t SH_FLD_EN_POLL_BACKOFF = 6375; // 1 +const static uint64_t SH_FLD_EN_RANDOM_BACKOFF = 6376; // 1 +const static uint64_t SH_FLD_EN_RESET_DD2_FIX_DIS = 6377; // 8 +const static uint64_t SH_FLD_EN_RESET_WR_DELAY_WL = 6378; // 8 +const static uint64_t SH_FLD_EN_RISCTRACE = 6379; // 17 +const static uint64_t SH_FLD_EN_SECOND_WRBUF = 6380; // 1 +const static uint64_t SH_FLD_EN_SLV_FAIRNESS = 6381; // 1 +const static uint64_t SH_FLD_EN_SPEC_CILD_EQD = 6382; // 1 +const static uint64_t SH_FLD_EN_SPEC_CILD_IVE = 6383; // 1 +const static uint64_t SH_FLD_EN_SPEC_CILD_VPC_HW = 6384; // 1 +const static uint64_t SH_FLD_EN_SPEC_CILD_VPC_SW = 6385; // 1 +const static uint64_t SH_FLD_EN_TRACE_FULL_IVA = 6386; // 17 +const static uint64_t SH_FLD_EN_WIDE_TRACE = 6387; // 16 +const static uint64_t SH_FLD_EN_WT4CR_EPS_ON_LCO = 6388; // 12 +const static uint64_t SH_FLD_EN_WT4CR_EXTENDED_MODE = 6389; // 12 +const static uint64_t SH_FLD_EPOCH_TEST_VECTOR = 6390; // 2 +const static uint64_t SH_FLD_EPOCH_TEST_VECTOR_LEN = 6391; // 2 +const static uint64_t SH_FLD_EPOCH_VALUE = 6392; // 2 +const static uint64_t SH_FLD_EPOCH_VALUE_LEN = 6393; // 2 +const static uint64_t SH_FLD_EPS_CNT_USE_DIVIDER_EN = 6394; // 12 +const static uint64_t SH_FLD_EPS_DIVIDER_MODE = 6395; // 12 +const static uint64_t SH_FLD_EPS_DIVIDER_MODE_LEN = 6396; // 12 +const static uint64_t SH_FLD_EPS_MODE_SEL = 6397; // 12 +const static uint64_t SH_FLD_EPS_STEP_MODE = 6398; // 12 +const static uint64_t SH_FLD_EPS_STEP_MODE_LEN = 6399; // 12 +const static uint64_t SH_FLD_EQC_CILOAD = 6400; // 1 +const static uint64_t SH_FLD_EQC_CILOAD_LEN = 6401; // 1 +const static uint64_t SH_FLD_EQC_CISTORE = 6402; // 1 +const static uint64_t SH_FLD_EQC_CISTORE_LEN = 6403; // 1 +const static uint64_t SH_FLD_EQC_DMA = 6404; // 1 +const static uint64_t SH_FLD_EQC_DMA_LEN = 6405; // 1 +const static uint64_t SH_FLD_EQC_EOI_EQP = 6406; // 1 +const static uint64_t SH_FLD_EQC_EOI_EQP_LEN = 6407; // 1 +const static uint64_t SH_FLD_EQC_EOI_ESBE = 6408; // 1 +const static uint64_t SH_FLD_EQC_EOI_ESBE_LEN = 6409; // 1 +const static uint64_t SH_FLD_EQD_BLOCK = 6410; // 1 +const static uint64_t SH_FLD_EQD_BLOCK_LEN = 6411; // 1 +const static uint64_t SH_FLD_EQD_DMA_READ = 6412; // 1 +const static uint64_t SH_FLD_EQD_DMA_READ_LEN = 6413; // 1 +const static uint64_t SH_FLD_EQD_DMA_WRITE = 6414; // 1 +const static uint64_t SH_FLD_EQD_DMA_WRITE_LEN = 6415; // 1 +const static uint64_t SH_FLD_EQD_INDEX = 6416; // 1 +const static uint64_t SH_FLD_EQD_INDEX_LEN = 6417; // 1 +const static uint64_t SH_FLD_EQ_POST = 6418; // 1 +const static uint64_t SH_FLD_EQ_POST_LEN = 6419; // 1 +const static uint64_t SH_FLD_ERAT_ARRAY_CE = 6420; // 1 +const static uint64_t SH_FLD_ERAT_ARRAY_PE = 6421; // 1 +const static uint64_t SH_FLD_ERAT_ARRAY_SUE = 6422; // 1 +const static uint64_t SH_FLD_ERAT_ARRAY_UE = 6423; // 1 +const static uint64_t SH_FLD_ERAT_CICO_HANG = 6424; // 1 +const static uint64_t SH_FLD_ERAT_CNTRL_ERR = 6425; // 1 +const static uint64_t SH_FLD_ERAT_DATA_POLL_SCALE = 6426; // 1 +const static uint64_t SH_FLD_ERAT_DATA_POLL_SCALE_LEN = 6427; // 1 +const static uint64_t SH_FLD_ERAT_LOCAL_CSTOP = 6428; // 1 +const static uint64_t SH_FLD_ERAT_MUX_SELECT = 6429; // 1 +const static uint64_t SH_FLD_ERAT_MUX_SELECT_LEN = 6430; // 1 +const static uint64_t SH_FLD_ERR = 6431; // 24 +const static uint64_t SH_FLD_ERR501 = 6432; // 43 +const static uint64_t SH_FLD_ERROR = 6433; // 123 +const static uint64_t SH_FLD_ERRORS = 6434; // 43 +const static uint64_t SH_FLD_ERRORS_LEN = 6435; // 43 +const static uint64_t SH_FLD_ERROR_0 = 6436; // 1 +const static uint64_t SH_FLD_ERROR_1 = 6437; // 1 +const static uint64_t SH_FLD_ERROR_2 = 6438; // 1 +const static uint64_t SH_FLD_ERROR_3 = 6439; // 1 +const static uint64_t SH_FLD_ERROR_4 = 6440; // 1 +const static uint64_t SH_FLD_ERROR_5 = 6441; // 1 +const static uint64_t SH_FLD_ERROR_ADDR = 6442; // 4 +const static uint64_t SH_FLD_ERROR_ADDRESS = 6443; // 2 +const static uint64_t SH_FLD_ERROR_ADDRESS_LEN = 6444; // 2 +const static uint64_t SH_FLD_ERROR_ADDR_LEN = 6445; // 4 +const static uint64_t SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK = 6446; // 90 +const static uint64_t SH_FLD_ERROR_COARSE_RD = 6447; // 8 +const static uint64_t SH_FLD_ERROR_CONFIG = 6448; // 9 +const static uint64_t SH_FLD_ERROR_CONFIG_LEN = 6449; // 9 +const static uint64_t SH_FLD_ERROR_CUSTOM_RD = 6450; // 8 +const static uint64_t SH_FLD_ERROR_CUSTOM_WR = 6451; // 8 +const static uint64_t SH_FLD_ERROR_DIGITAL_EYE = 6452; // 8 +const static uint64_t SH_FLD_ERROR_DQS_ALIGN = 6453; // 8 +const static uint64_t SH_FLD_ERROR_INITIAL_COARSE_WR = 6454; // 8 +const static uint64_t SH_FLD_ERROR_INITIAL_PAT_WRITE = 6455; // 8 +const static uint64_t SH_FLD_ERROR_INJECT = 6456; // 1 +const static uint64_t SH_FLD_ERROR_INJECT_ENABLE = 6457; // 1 +const static uint64_t SH_FLD_ERROR_INJECT_LEN = 6458; // 1 +const static uint64_t SH_FLD_ERROR_LEN = 6459; // 25 +const static uint64_t SH_FLD_ERROR_MASK = 6460; // 43 +const static uint64_t SH_FLD_ERROR_MASK_LEN = 6461; // 43 +const static uint64_t SH_FLD_ERROR_PULSE_OR_LEVEL = 6462; // 24 +const static uint64_t SH_FLD_ERROR_RDCLK_ALIGN = 6463; // 8 +const static uint64_t SH_FLD_ERROR_READ_CTR = 6464; // 8 +const static uint64_t SH_FLD_ERROR_RECOVERY_COMPLETE = 6465; // 2 +const static uint64_t SH_FLD_ERROR_RECOVERY_INITIATED = 6466; // 2 +const static uint64_t SH_FLD_ERROR_STATE = 6467; // 4 +const static uint64_t SH_FLD_ERROR_WRITE_CTR = 6468; // 8 +const static uint64_t SH_FLD_ERROR_WR_LEVEL = 6469; // 8 +const static uint64_t SH_FLD_ERRS = 6470; // 256 +const static uint64_t SH_FLD_ERRS_INJ = 6471; // 4 +const static uint64_t SH_FLD_ERRS_INJ_LEN = 6472; // 4 +const static uint64_t SH_FLD_ERRS_LEN = 6473; // 140 +const static uint64_t SH_FLD_ERR_ADDR_BEYOND_RANGE = 6474; // 1 +const static uint64_t SH_FLD_ERR_ADDR_OVERLAP = 6475; // 1 +const static uint64_t SH_FLD_ERR_BRK0 = 6476; // 1 +const static uint64_t SH_FLD_ERR_BRK0_LEN = 6477; // 1 +const static uint64_t SH_FLD_ERR_BRK1 = 6478; // 1 +const static uint64_t SH_FLD_ERR_BRK1_LEN = 6479; // 1 +const static uint64_t SH_FLD_ERR_BRK2 = 6480; // 1 +const static uint64_t SH_FLD_ERR_BRK2_LEN = 6481; // 1 +const static uint64_t SH_FLD_ERR_BRK3 = 6482; // 1 +const static uint64_t SH_FLD_ERR_BRK3_LEN = 6483; // 1 +const static uint64_t SH_FLD_ERR_BRK4 = 6484; // 1 +const static uint64_t SH_FLD_ERR_BRK4_LEN = 6485; // 1 +const static uint64_t SH_FLD_ERR_BRK5 = 6486; // 1 +const static uint64_t SH_FLD_ERR_BRK5_LEN = 6487; // 1 +const static uint64_t SH_FLD_ERR_CMD_OVERRUN = 6488; // 1 +const static uint64_t SH_FLD_ERR_CQ = 6489; // 16 +const static uint64_t SH_FLD_ERR_CQ_LEN = 6490; // 16 +const static uint64_t SH_FLD_ERR_DETAIL = 6491; // 16 +const static uint64_t SH_FLD_ERR_DETAIL_LEN = 6492; // 16 +const static uint64_t SH_FLD_ERR_FSM_DP16 = 6493; // 8 +const static uint64_t SH_FLD_ERR_FSM_DP16_LEN = 6494; // 8 +const static uint64_t SH_FLD_ERR_INJ = 6495; // 252 +const static uint64_t SH_FLD_ERR_INJ_ACTION = 6496; // 2 +const static uint64_t SH_FLD_ERR_INJ_ARRAY_SEL = 6497; // 2 +const static uint64_t SH_FLD_ERR_INJ_ARRAY_SEL_LEN = 6498; // 2 +const static uint64_t SH_FLD_ERR_INJ_A_BER_SEL = 6499; // 6 +const static uint64_t SH_FLD_ERR_INJ_A_BER_SEL_LEN = 6500; // 6 +const static uint64_t SH_FLD_ERR_INJ_A_COARSE_SEL = 6501; // 6 +const static uint64_t SH_FLD_ERR_INJ_A_COARSE_SEL_LEN = 6502; // 6 +const static uint64_t SH_FLD_ERR_INJ_A_ENABLE = 6503; // 116 +const static uint64_t SH_FLD_ERR_INJ_A_FINE_SEL = 6504; // 6 +const static uint64_t SH_FLD_ERR_INJ_A_FINE_SEL_LEN = 6505; // 6 +const static uint64_t SH_FLD_ERR_INJ_B_BER_SEL = 6506; // 6 +const static uint64_t SH_FLD_ERR_INJ_B_BER_SEL_LEN = 6507; // 6 +const static uint64_t SH_FLD_ERR_INJ_B_COARSE_SEL = 6508; // 6 +const static uint64_t SH_FLD_ERR_INJ_B_COARSE_SEL_LEN = 6509; // 6 +const static uint64_t SH_FLD_ERR_INJ_B_ENABLE = 6510; // 116 +const static uint64_t SH_FLD_ERR_INJ_B_FINE_SEL = 6511; // 6 +const static uint64_t SH_FLD_ERR_INJ_B_FINE_SEL_LEN = 6512; // 6 +const static uint64_t SH_FLD_ERR_INJ_CLOCK_ENABLE = 6513; // 6 +const static uint64_t SH_FLD_ERR_INJ_ENABLE = 6514; // 8 +const static uint64_t SH_FLD_ERR_INJ_LEN = 6515; // 136 +const static uint64_t SH_FLD_ERR_INJ_SLS_ALL_CMD = 6516; // 4 +const static uint64_t SH_FLD_ERR_INJ_SLS_CMD = 6517; // 4 +const static uint64_t SH_FLD_ERR_INJ_SLS_CMD_LEN = 6518; // 4 +const static uint64_t SH_FLD_ERR_INJ_SLS_MODE = 6519; // 4 +const static uint64_t SH_FLD_ERR_INJ_SLS_RECAL = 6520; // 4 +const static uint64_t SH_FLD_ERR_INJ_STATUS = 6521; // 2 +const static uint64_t SH_FLD_ERR_INJ_TYPE = 6522; // 2 +const static uint64_t SH_FLD_ERR_LVL = 6523; // 16 +const static uint64_t SH_FLD_ERR_LVL_LEN = 6524; // 16 +const static uint64_t SH_FLD_ERR_REG_DP16 = 6525; // 8 +const static uint64_t SH_FLD_ERR_REG_DP16_LEN = 6526; // 8 +const static uint64_t SH_FLD_ERR_RSVD0 = 6527; // 16 +const static uint64_t SH_FLD_ERR_RSVD0_LEN = 6528; // 16 +const static uint64_t SH_FLD_ERR_SET0 = 6529; // 8 +const static uint64_t SH_FLD_ERR_SET1 = 6530; // 8 +const static uint64_t SH_FLD_ERR_SET2 = 6531; // 8 +const static uint64_t SH_FLD_ERR_SET3 = 6532; // 8 +const static uint64_t SH_FLD_ERR_SET4 = 6533; // 8 +const static uint64_t SH_FLD_ERR_SET5 = 6534; // 8 +const static uint64_t SH_FLD_ERR_VLD = 6535; // 16 +const static uint64_t SH_FLD_ESB_OR_LSI_INTERRUPTS = 6536; // 1 +const static uint64_t SH_FLD_ESC1_PRIORITY = 6537; // 1 +const static uint64_t SH_FLD_ESC1_PRIORITY_LEN = 6538; // 1 +const static uint64_t SH_FLD_ESC1_RSD = 6539; // 1 +const static uint64_t SH_FLD_ESC1_RSD_LEN = 6540; // 1 +const static uint64_t SH_FLD_ESC2_PRIORITY = 6541; // 1 +const static uint64_t SH_FLD_ESC2_PRIORITY_LEN = 6542; // 1 +const static uint64_t SH_FLD_ESC2_RSD = 6543; // 1 +const static uint64_t SH_FLD_ESC2_RSD_LEN = 6544; // 1 +const static uint64_t SH_FLD_ESCAPE_ADDRESS = 6545; // 1 +const static uint64_t SH_FLD_ESCAPE_ADDRESS_LEN = 6546; // 1 +const static uint64_t SH_FLD_ESR_RSVD_19 = 6547; // 1 +const static uint64_t SH_FLD_EVENT = 6548; // 6 +const static uint64_t SH_FLD_EVENT0 = 6549; // 21 +const static uint64_t SH_FLD_EVENT0_COUNTER = 6550; // 8 +const static uint64_t SH_FLD_EVENT0_COUNTER_LEN = 6551; // 8 +const static uint64_t SH_FLD_EVENT0_LEN = 6552; // 21 +const static uint64_t SH_FLD_EVENT0_SEL = 6553; // 2 +const static uint64_t SH_FLD_EVENT1 = 6554; // 21 +const static uint64_t SH_FLD_EVENT1_COUNTER = 6555; // 8 +const static uint64_t SH_FLD_EVENT1_COUNTER_LEN = 6556; // 8 +const static uint64_t SH_FLD_EVENT1_LEN = 6557; // 21 +const static uint64_t SH_FLD_EVENT1_SEL = 6558; // 2 +const static uint64_t SH_FLD_EVENT1_SEL_LEN = 6559; // 2 +const static uint64_t SH_FLD_EVENT2 = 6560; // 21 +const static uint64_t SH_FLD_EVENT2HALT_DELAY = 6561; // 1 +const static uint64_t SH_FLD_EVENT2HALT_DELAY_LEN = 6562; // 1 +const static uint64_t SH_FLD_EVENT2HALT_EN = 6563; // 1 +const static uint64_t SH_FLD_EVENT2HALT_EN_LEN = 6564; // 1 +const static uint64_t SH_FLD_EVENT2HALT_GPE0 = 6565; // 1 +const static uint64_t SH_FLD_EVENT2HALT_GPE1 = 6566; // 1 +const static uint64_t SH_FLD_EVENT2HALT_GPE2 = 6567; // 1 +const static uint64_t SH_FLD_EVENT2HALT_GPE3 = 6568; // 1 +const static uint64_t SH_FLD_EVENT2HALT_HALT_STATE = 6569; // 1 +const static uint64_t SH_FLD_EVENT2HALT_MODE = 6570; // 1 +const static uint64_t SH_FLD_EVENT2HALT_MODE_LEN = 6571; // 1 +const static uint64_t SH_FLD_EVENT2HALT_OCC = 6572; // 1 +const static uint64_t SH_FLD_EVENT2_COUNTER = 6573; // 8 +const static uint64_t SH_FLD_EVENT2_COUNTER_LEN = 6574; // 8 +const static uint64_t SH_FLD_EVENT2_LEN = 6575; // 21 +const static uint64_t SH_FLD_EVENT2_SEL = 6576; // 2 +const static uint64_t SH_FLD_EVENT2_SEL_LEN = 6577; // 2 +const static uint64_t SH_FLD_EVENT3 = 6578; // 21 +const static uint64_t SH_FLD_EVENT3_COUNTER = 6579; // 8 +const static uint64_t SH_FLD_EVENT3_COUNTER_LEN = 6580; // 8 +const static uint64_t SH_FLD_EVENT3_LEN = 6581; // 21 +const static uint64_t SH_FLD_EVENT3_SEL = 6582; // 2 +const static uint64_t SH_FLD_EVENT3_SEL_LEN = 6583; // 2 +const static uint64_t SH_FLD_EVENTCNT = 6584; // 3 +const static uint64_t SH_FLD_EVENTCNT_LEN = 6585; // 3 +const static uint64_t SH_FLD_EVENT_BUS_EN = 6586; // 4 +const static uint64_t SH_FLD_EVENT_BUS_ENABLE = 6587; // 4 +const static uint64_t SH_FLD_EVENT_BUS_EN_LEN = 6588; // 4 +const static uint64_t SH_FLD_EVENT_BUS_SELECTS = 6589; // 12 +const static uint64_t SH_FLD_EVENT_BUS_SELECTS_LEN = 6590; // 12 +const static uint64_t SH_FLD_EVENT_LEN = 6591; // 6 +const static uint64_t SH_FLD_EVENT_MUX_SELECTS = 6592; // 24 +const static uint64_t SH_FLD_EVENT_MUX_SELECTS_LEN = 6593; // 24 +const static uint64_t SH_FLD_EXACT_RESET_C3_ON_TO = 6594; // 86 +const static uint64_t SH_FLD_EXACT_TO_MODE = 6595; // 86 +const static uint64_t SH_FLD_EXBIST_MODE = 6596; // 6 +const static uint64_t SH_FLD_EXIT_1 = 6597; // 64 +const static uint64_t SH_FLD_EXIT_CRITERION_A_N = 6598; // 96 +const static uint64_t SH_FLD_EXTADDR = 6599; // 6 +const static uint64_t SH_FLD_EXTADDR_LEN = 6600; // 6 +const static uint64_t SH_FLD_EXTERNAL_TRAP = 6601; // 2 +const static uint64_t SH_FLD_EXTERNAL_TRAP_MASK = 6602; // 1 +const static uint64_t SH_FLD_EXTERNAL_XSTOP = 6603; // 4 +const static uint64_t SH_FLD_EXTRA_CMD_SPACING_0_2 = 6604; // 1 +const static uint64_t SH_FLD_EXTRA_CMD_SPACING_0_2_LEN = 6605; // 1 +const static uint64_t SH_FLD_EXTRA_DAT_SPACING_0_3 = 6606; // 1 +const static uint64_t SH_FLD_EXTRA_DAT_SPACING_0_3_LEN = 6607; // 1 +const static uint64_t SH_FLD_EXT_EBB_EXIT_ENABLE = 6608; // 96 +const static uint64_t SH_FLD_EXT_EXIT_ENABLE = 6609; // 96 +const static uint64_t SH_FLD_EXT_INTERRUPT = 6610; // 1 +const static uint64_t SH_FLD_EXT_RESUME_EXIT_ENABLE = 6611; // 96 +const static uint64_t SH_FLD_EXT_TRIG_ON_FREEZE = 6612; // 43 +const static uint64_t SH_FLD_EXT_TRIG_ON_STOP = 6613; // 43 +const static uint64_t SH_FLD_EYE_OPT_DONE = 6614; // 4 +const static uint64_t SH_FLD_EYE_OPT_FAILED = 6615; // 4 +const static uint64_t SH_FLD_E_BIST_EN = 6616; // 2 +const static uint64_t SH_FLD_E_CONTROLS = 6617; // 48 +const static uint64_t SH_FLD_E_CONTROLS_LEN = 6618; // 48 +const static uint64_t SH_FLD_E_CTLE_COARSE = 6619; // 48 +const static uint64_t SH_FLD_E_CTLE_COARSE_LEN = 6620; // 48 +const static uint64_t SH_FLD_E_CTLE_GAIN = 6621; // 48 +const static uint64_t SH_FLD_E_CTLE_GAIN_LEN = 6622; // 48 +const static uint64_t SH_FLD_E_EVEN_INTEG_FINE_GAIN = 6623; // 48 +const static uint64_t SH_FLD_E_EVEN_INTEG_FINE_GAIN_LEN = 6624; // 48 +const static uint64_t SH_FLD_E_INTEG_COARSE_GAIN = 6625; // 48 +const static uint64_t SH_FLD_E_INTEG_COARSE_GAIN_LEN = 6626; // 48 +const static uint64_t SH_FLD_E_ODD_INTEG_FINE_GAIN = 6627; // 48 +const static uint64_t SH_FLD_E_ODD_INTEG_FINE_GAIN_LEN = 6628; // 48 +const static uint64_t SH_FLD_E_OFFSET = 6629; // 48 +const static uint64_t SH_FLD_E_OFFSET_E = 6630; // 48 +const static uint64_t SH_FLD_E_OFFSET_E_LEN = 6631; // 48 +const static uint64_t SH_FLD_E_OFFSET_LEN = 6632; // 48 +const static uint64_t SH_FLD_E_TARG_MIN = 6633; // 1 +const static uint64_t SH_FLD_E_TARG_MIN_LEN = 6634; // 1 +const static uint64_t SH_FLD_F0_HUT_HISTORY = 6635; // 3 +const static uint64_t SH_FLD_F0_HUT_HISTORY_LEN = 6636; // 3 +const static uint64_t SH_FLD_F0_LUT_HISTORY = 6637; // 3 +const static uint64_t SH_FLD_F0_LUT_HISTORY_LEN = 6638; // 3 +const static uint64_t SH_FLD_F1_HUT_HISTORY = 6639; // 3 +const static uint64_t SH_FLD_F1_HUT_HISTORY_LEN = 6640; // 3 +const static uint64_t SH_FLD_F1_LUT_HISTORY = 6641; // 3 +const static uint64_t SH_FLD_F1_LUT_HISTORY_LEN = 6642; // 3 +const static uint64_t SH_FLD_FACTOR = 6643; // 24 +const static uint64_t SH_FLD_FACTOR_LEN = 6644; // 24 +const static uint64_t SH_FLD_FAIL = 6645; // 4 +const static uint64_t SH_FLD_FAILED_LINK_ON_INTERRUPT = 6646; // 1 +const static uint64_t SH_FLD_FAILING_OPB_MASTER_ACT = 6647; // 3 +const static uint64_t SH_FLD_FAILING_OPB_MASTER_ACT_LEN = 6648; // 3 +const static uint64_t SH_FLD_FAILING_OPB_MASTER_FRST = 6649; // 3 +const static uint64_t SH_FLD_FAILING_OPB_MASTER_FRST_LEN = 6650; // 3 +const static uint64_t SH_FLD_FAIL_RCD = 6651; // 2 +const static uint64_t SH_FLD_FAIL_REG = 6652; // 1 +const static uint64_t SH_FLD_FAIL_REG_LEN = 6653; // 1 +const static uint64_t SH_FLD_FAIL_TYPE = 6654; // 2 +const static uint64_t SH_FLD_FAIL_TYPE_LEN = 6655; // 2 +const static uint64_t SH_FLD_FARB_CAL_RECVFSM_1HOT = 6656; // 8 +const static uint64_t SH_FLD_FARB_PE = 6657; // 8 +const static uint64_t SH_FLD_FARR = 6658; // 43 +const static uint64_t SH_FLD_FASTPATH_LIMIT = 6659; // 8 +const static uint64_t SH_FLD_FASTPATH_LIMIT_LEN = 6660; // 8 +const static uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_0 = 6661; // 1 +const static uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_0_LEN = 6662; // 1 +const static uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_1 = 6663; // 1 +const static uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_1_LEN = 6664; // 1 +const static uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_2 = 6665; // 1 +const static uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_2_LEN = 6666; // 1 +const static uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_3 = 6667; // 1 +const static uint64_t SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_3_LEN = 6668; // 1 +const static uint64_t SH_FLD_FAST_SIM_CNTR = 6669; // 8 +const static uint64_t SH_FLD_FBC = 6670; // 2 +const static uint64_t SH_FLD_FBC_ADDRESS = 6671; // 1 +const static uint64_t SH_FLD_FBC_ADDRESS_ERROR = 6672; // 1 +const static uint64_t SH_FLD_FBC_ADDRESS_LEN = 6673; // 1 +const static uint64_t SH_FLD_FBC_ADDR_DONE = 6674; // 1 +const static uint64_t SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT = 6675; // 1 +const static uint64_t SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN = 6676; // 1 +const static uint64_t SH_FLD_FBC_AUTOINC_ERROR = 6677; // 1 +const static uint64_t SH_FLD_FBC_AUTO_INC = 6678; // 1 +const static uint64_t SH_FLD_FBC_AXTYPE = 6679; // 1 +const static uint64_t SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT = 6680; // 1 +const static uint64_t SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT_LEN = 6681; // 1 +const static uint64_t SH_FLD_FBC_BUS0_STG0_SEL = 6682; // 1 +const static uint64_t SH_FLD_FBC_BUS0_STG0_SEL_LEN = 6683; // 1 +const static uint64_t SH_FLD_FBC_BUS0_STG1_SEL = 6684; // 1 +const static uint64_t SH_FLD_FBC_BUS0_STG2_SEL = 6685; // 1 +const static uint64_t SH_FLD_FBC_BUS1_STG0_SEL = 6686; // 1 +const static uint64_t SH_FLD_FBC_BUS1_STG0_SEL_LEN = 6687; // 1 +const static uint64_t SH_FLD_FBC_BUS1_STG1_SEL = 6688; // 1 +const static uint64_t SH_FLD_FBC_BUS1_STG2_SEL = 6689; // 1 +const static uint64_t SH_FLD_FBC_CLEAR_STATUS = 6690; // 1 +const static uint64_t SH_FLD_FBC_CMD_PROT_ERR_CHK_DIS = 6691; // 1 +const static uint64_t SH_FLD_FBC_COMMAND_ERROR = 6692; // 1 +const static uint64_t SH_FLD_FBC_CRESP_VALUE = 6693; // 1 +const static uint64_t SH_FLD_FBC_CRESP_VALUE_LEN = 6694; // 1 +const static uint64_t SH_FLD_FBC_DATA_DONE = 6695; // 1 +const static uint64_t SH_FLD_FBC_DATA_ONLY = 6696; // 1 +const static uint64_t SH_FLD_FBC_DIN_ECC_CHK_DIS = 6697; // 1 +const static uint64_t SH_FLD_FBC_DISABLE = 6698; // 1 +const static uint64_t SH_FLD_FBC_DISABLE_LOCAL_SHORTCUT = 6699; // 1 +const static uint64_t SH_FLD_FBC_DROP_PRIORITY = 6700; // 1 +const static uint64_t SH_FLD_FBC_DROP_PRIORITY_MAX = 6701; // 1 +const static uint64_t SH_FLD_FBC_ECC_CE = 6702; // 1 +const static uint64_t SH_FLD_FBC_ECC_SUE = 6703; // 1 +const static uint64_t SH_FLD_FBC_ECC_UE = 6704; // 1 +const static uint64_t SH_FLD_FBC_INV_AMORT_DIS = 6705; // 1 +const static uint64_t SH_FLD_FBC_LEN = 6706; // 2 +const static uint64_t SH_FLD_FBC_LFSR_DIS = 6707; // 1 +const static uint64_t SH_FLD_FBC_LOCKED = 6708; // 1 +const static uint64_t SH_FLD_FBC_LOCK_ID = 6709; // 1 +const static uint64_t SH_FLD_FBC_LOCK_ID_LEN = 6710; // 1 +const static uint64_t SH_FLD_FBC_OVERRUN_ERROR = 6711; // 1 +const static uint64_t SH_FLD_FBC_OVERWRITE_PBINIT = 6712; // 1 +const static uint64_t SH_FLD_FBC_PBINIT_MISSING = 6713; // 1 +const static uint64_t SH_FLD_FBC_PB_DATA_HANG_ERR = 6714; // 1 +const static uint64_t SH_FLD_FBC_PB_OP_HANG_ERR = 6715; // 1 +const static uint64_t SH_FLD_FBC_PB_UNEXPECT_CRESP_ERR = 6716; // 1 +const static uint64_t SH_FLD_FBC_PB_UNEXPECT_DATA_ERR = 6717; // 1 +const static uint64_t SH_FLD_FBC_PIB_DIRECT = 6718; // 1 +const static uint64_t SH_FLD_FBC_PIB_DIRECT_DONE = 6719; // 1 +const static uint64_t SH_FLD_FBC_PIB_ERROR = 6720; // 1 +const static uint64_t SH_FLD_FBC_PIB_ERROR_LEN = 6721; // 1 +const static uint64_t SH_FLD_FBC_RESET = 6722; // 1 +const static uint64_t SH_FLD_FBC_RESET_FSM = 6723; // 1 +const static uint64_t SH_FLD_FBC_RNW = 6724; // 1 +const static uint64_t SH_FLD_FBC_SCOPE = 6725; // 1 +const static uint64_t SH_FLD_FBC_SCOPE_LEN = 6726; // 1 +const static uint64_t SH_FLD_FBC_SNP_PROT_ERR_CHK_DIS = 6727; // 1 +const static uint64_t SH_FLD_FBC_SNP_TIMEOUT_CHK_DIS = 6728; // 1 +const static uint64_t SH_FLD_FBC_START_OP = 6729; // 1 +const static uint64_t SH_FLD_FBC_TSIZE = 6730; // 1 +const static uint64_t SH_FLD_FBC_TSIZE_LEN = 6731; // 1 +const static uint64_t SH_FLD_FBC_TTYPE = 6732; // 1 +const static uint64_t SH_FLD_FBC_TTYPE_LEN = 6733; // 1 +const static uint64_t SH_FLD_FBC_WAIT_CMD_ARBIT = 6734; // 1 +const static uint64_t SH_FLD_FBC_WAIT_PIB_DIRECT = 6735; // 1 +const static uint64_t SH_FLD_FBC_WAIT_RESP = 6736; // 1 +const static uint64_t SH_FLD_FBC_WITH_PBINIT_LOW_WAIT = 6737; // 1 +const static uint64_t SH_FLD_FBC_WITH_POST_INIT = 6738; // 1 +const static uint64_t SH_FLD_FBC_WITH_PRE_QUIESCE = 6739; // 1 +const static uint64_t SH_FLD_FBC_WITH_TM_QUIESCE = 6740; // 1 +const static uint64_t SH_FLD_FBC_XLAT_ECC_CHK_DIS = 6741; // 1 +const static uint64_t SH_FLD_FBC_XLAT_PROT_ERR_CHK_DIS = 6742; // 1 +const static uint64_t SH_FLD_FBC_XLAT_TIMEOUT_CHK_DIS = 6743; // 1 +const static uint64_t SH_FLD_FENCE = 6744; // 4 +const static uint64_t SH_FLD_FENCE0 = 6745; // 15 +const static uint64_t SH_FLD_FENCE0_LEN = 6746; // 15 +const static uint64_t SH_FLD_FENCE1 = 6747; // 15 +const static uint64_t SH_FLD_FENCE1_DC = 6748; // 3 +const static uint64_t SH_FLD_FENCE1_LEN = 6749; // 15 +const static uint64_t SH_FLD_FENCE2_DC = 6750; // 3 +const static uint64_t SH_FLD_FENCE3_DC = 6751; // 3 +const static uint64_t SH_FLD_FENCE4_DC = 6752; // 3 +const static uint64_t SH_FLD_FENCE5_DC = 6753; // 3 +const static uint64_t SH_FLD_FENCE6_DC = 6754; // 3 +const static uint64_t SH_FLD_FENCE_EISR = 6755; // 24 +const static uint64_t SH_FLD_FENCE_EN = 6756; // 43 +const static uint64_t SH_FLD_FENCE_GX_INTERFACE = 6757; // 1 +const static uint64_t SH_FLD_FENCE_IO_INTERFACE = 6758; // 1 +const static uint64_t SH_FLD_FENCE_TLBIE = 6759; // 12 +const static uint64_t SH_FLD_FFE_BOOST_EN = 6760; // 6 +const static uint64_t SH_FLD_FF_BYPASS = 6761; // 6 +const static uint64_t SH_FLD_FF_SLEWRATE = 6762; // 6 +const static uint64_t SH_FLD_FF_SLEWRATE_LEN = 6763; // 6 +const static uint64_t SH_FLD_FGAT_0 = 6764; // 2 +const static uint64_t SH_FLD_FGAT_1 = 6765; // 1 +const static uint64_t SH_FLD_FGAT_2 = 6766; // 1 +const static uint64_t SH_FLD_FGAT_3 = 6767; // 1 +const static uint64_t SH_FLD_FIELD = 6768; // 9 +const static uint64_t SH_FLD_FIELD_LEN = 6769; // 9 +const static uint64_t SH_FLD_FIFO_BITS_READ0_0 = 6770; // 3 +const static uint64_t SH_FLD_FIFO_BITS_READ0_0_LEN = 6771; // 3 +const static uint64_t SH_FLD_FIFO_BITS_READ0_1 = 6772; // 2 +const static uint64_t SH_FLD_FIFO_BITS_READ0_1_LEN = 6773; // 2 +const static uint64_t SH_FLD_FIFO_BITS_READ0_2 = 6774; // 2 +const static uint64_t SH_FLD_FIFO_BITS_READ0_2_LEN = 6775; // 2 +const static uint64_t SH_FLD_FIFO_BITS_READ0_3 = 6776; // 2 +const static uint64_t SH_FLD_FIFO_BITS_READ0_3_LEN = 6777; // 2 +const static uint64_t SH_FLD_FIFO_DLY_CFG = 6778; // 120 +const static uint64_t SH_FLD_FIFO_DLY_CFG_LEN = 6779; // 120 +const static uint64_t SH_FLD_FIFO_EMPTY = 6780; // 1 +const static uint64_t SH_FLD_FIFO_ENTRY_COUNT = 6781; // 1 +const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_0 = 6782; // 2 +const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_0_LEN = 6783; // 2 +const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_1 = 6784; // 1 +const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_1_LEN = 6785; // 1 +const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_2 = 6786; // 1 +const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_2_LEN = 6787; // 1 +const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_3 = 6788; // 1 +const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_3_LEN = 6789; // 1 +const static uint64_t SH_FLD_FIFO_ENTRY_COUNT_LEN = 6790; // 1 +const static uint64_t SH_FLD_FIFO_EOT_FLAGS = 6791; // 1 +const static uint64_t SH_FLD_FIFO_EOT_FLAGS_LEN = 6792; // 1 +const static uint64_t SH_FLD_FIFO_FINAL_L2U_DLY = 6793; // 4 +const static uint64_t SH_FLD_FIFO_FINAL_L2U_DLY_LEN = 6794; // 4 +const static uint64_t SH_FLD_FIFO_FULL = 6795; // 7 +const static uint64_t SH_FLD_FIFO_HALF_DEPTH_MODE = 6796; // 72 +const static uint64_t SH_FLD_FIFO_HALF_WIDTH_MODE = 6797; // 140 +const static uint64_t SH_FLD_FIFO_INITIAL_L2U_DLY = 6798; // 4 +const static uint64_t SH_FLD_FIFO_INITIAL_L2U_DLY_LEN = 6799; // 4 +const static uint64_t SH_FLD_FIFO_L2U_DLY = 6800; // 188 +const static uint64_t SH_FLD_FIFO_L2U_DLY_LEN = 6801; // 188 +const static uint64_t SH_FLD_FIFO_VALID_FLAGS = 6802; // 1 +const static uint64_t SH_FLD_FIFO_VALID_FLAGS_LEN = 6803; // 1 +const static uint64_t SH_FLD_FILTDIVSEL = 6804; // 3 +const static uint64_t SH_FLD_FILTDIVSEL_LEN = 6805; // 3 +const static uint64_t SH_FLD_FILTER = 6806; // 2 +const static uint64_t SH_FLD_FILTER_LEN = 6807; // 2 +const static uint64_t SH_FLD_FILTER_MODE = 6808; // 6 +const static uint64_t SH_FLD_FILTER_MODE_LEN = 6809; // 6 +const static uint64_t SH_FLD_FINAL_VDM_DATA = 6810; // 6 +const static uint64_t SH_FLD_FINAL_VDM_DATA01 = 6811; // 12 +const static uint64_t SH_FLD_FINAL_VDM_DATA01_LEN = 6812; // 12 +const static uint64_t SH_FLD_FINAL_VDM_DATA_LEN = 6813; // 6 +const static uint64_t SH_FLD_FINE_CAL_STEP_SIZE = 6814; // 8 +const static uint64_t SH_FLD_FINE_CAL_STEP_SIZE_LEN = 6815; // 8 +const static uint64_t SH_FLD_FIR = 6816; // 48 +const static uint64_t SH_FLD_FIR0_CR0_ATAG_PERR = 6817; // 12 +const static uint64_t SH_FLD_FIR0_CR0_TTAG_PERR = 6818; // 12 +const static uint64_t SH_FLD_FIR0_CR1_ATAG_PERR = 6819; // 12 +const static uint64_t SH_FLD_FIR0_CR1_TTAG_PERR = 6820; // 12 +const static uint64_t SH_FLD_FIR0_CR2_ATAG_PERR = 6821; // 12 +const static uint64_t SH_FLD_FIR0_CR2_TTAG_PERR = 6822; // 12 +const static uint64_t SH_FLD_FIR0_CR3_ATAG_PERR = 6823; // 12 +const static uint64_t SH_FLD_FIR0_CR3_TTAG_PERR = 6824; // 12 +const static uint64_t SH_FLD_FIR0_ILLEGAL_STORE_SIZE = 6825; // 12 +const static uint64_t SH_FLD_FIR0_IMA_FSM_TIMEOUT = 6826; // 12 +const static uint64_t SH_FLD_FIR0_LD_AMO_SEQ = 6827; // 12 +const static uint64_t SH_FLD_FIR0_OVERFLOW = 6828; // 12 +const static uint64_t SH_FLD_FIR0_PBARB_TRASHMODE = 6829; // 12 +const static uint64_t SH_FLD_FIR0_PPE_RD_FSM_TIMEOUT = 6830; // 12 +const static uint64_t SH_FLD_FIR0_PPE_WR_FSM_TIMEOUT = 6831; // 12 +const static uint64_t SH_FLD_FIR0_PURGE_ABORT_LVL_ERR1 = 6832; // 12 +const static uint64_t SH_FLD_FIR0_PURGE_ABORT_LVL_ERR2 = 6833; // 12 +const static uint64_t SH_FLD_FIR0_PURGE_DONE_LVL_ERR1 = 6834; // 12 +const static uint64_t SH_FLD_FIR0_PURGE_LVL_ERR1 = 6835; // 12 +const static uint64_t SH_FLD_FIR0_PURGE_LVL_ERR2 = 6836; // 12 +const static uint64_t SH_FLD_FIR0_SNP0_ADDR_PERR = 6837; // 12 +const static uint64_t SH_FLD_FIR0_SNP0_TTAG_PERR = 6838; // 12 +const static uint64_t SH_FLD_FIR0_SNP1_ADDR_PERR = 6839; // 12 +const static uint64_t SH_FLD_FIR0_SNP1_TTAG_PERR = 6840; // 12 +const static uint64_t SH_FLD_FIR0_TLB_DATA_PAR = 6841; // 12 +const static uint64_t SH_FLD_FIR11_LRU_MEM_INVALID_ABCD = 6842; // 12 +const static uint64_t SH_FLD_FIR11_LRU_MEM_INVALID_EFGH = 6843; // 12 +const static uint64_t SH_FLD_FIR14_B01_BOTH_ACTIVE = 6844; // 12 +const static uint64_t SH_FLD_FIR14_B0_SD_DIR_MULT_HIT = 6845; // 12 +const static uint64_t SH_FLD_FIR14_B1_SD_DIR_MULT_HIT = 6846; // 12 +const static uint64_t SH_FLD_FIR14_B2_SD_DIR_MULT_HIT = 6847; // 12 +const static uint64_t SH_FLD_FIR14_B3_SD_DIR_MULT_HIT = 6848; // 12 +const static uint64_t SH_FLD_FIR14_BAD_FP_MATE = 6849; // 12 +const static uint64_t SH_FLD_FIR14_COX_UNEXP_IDLE_PB_CRESP = 6850; // 12 +const static uint64_t SH_FLD_FIR14_CR0_ATAG_PERR = 6851; // 12 +const static uint64_t SH_FLD_FIR14_CR0_TTAG_PERR = 6852; // 12 +const static uint64_t SH_FLD_FIR14_CR1_ATAG_PERR = 6853; // 12 +const static uint64_t SH_FLD_FIR14_CR1_TTAG_PERR = 6854; // 12 +const static uint64_t SH_FLD_FIR14_CR2_ATAG_PERR = 6855; // 12 +const static uint64_t SH_FLD_FIR14_CR2_TTAG_PERR = 6856; // 12 +const static uint64_t SH_FLD_FIR14_CR3_ATAG_PERR = 6857; // 12 +const static uint64_t SH_FLD_FIR14_CR3_TTAG_PERR = 6858; // 12 +const static uint64_t SH_FLD_FIR14_DW_SET_REF_WITH_FLAG_IDLE = 6859; // 12 +const static uint64_t SH_FLD_FIR14_DW_SET_SI_BY_MACH = 6860; // 12 +const static uint64_t SH_FLD_FIR14_HANG_WAITING_FOR_FP_MATE = 6861; // 12 +const static uint64_t SH_FLD_FIR14_IFU_MULT_REQ = 6862; // 12 +const static uint64_t SH_FLD_FIR14_INVALID_SNP_CPS_STATU_RTN = 6863; // 12 +const static uint64_t SH_FLD_FIR14_KILL_REF_WITH_FLAG_IDLE = 6864; // 12 +const static uint64_t SH_FLD_FIR14_L3PF_MACH_DONE = 6865; // 12 +const static uint64_t SH_FLD_FIR14_L3PF_REQ = 6866; // 12 +const static uint64_t SH_FLD_FIR14_LSU_TAG_REUSE = 6867; // 12 +const static uint64_t SH_FLD_FIR14_NCCTL_RLD_BARRIER = 6868; // 12 +const static uint64_t SH_FLD_FIR14_NCCTL_SNP = 6869; // 12 +const static uint64_t SH_FLD_FIR14_NCCTL_SYNC = 6870; // 12 +const static uint64_t SH_FLD_FIR14_NCCTL_TLBIE_ACK = 6871; // 12 +const static uint64_t SH_FLD_FIR14_NCCTL_VSYNC = 6872; // 12 +const static uint64_t SH_FLD_FIR14_NCU_TID_DONE = 6873; // 12 +const static uint64_t SH_FLD_FIR14_PBARB_FSM_REQ_OVERFLOW = 6874; // 12 +const static uint64_t SH_FLD_FIR14_PBARB_TRASHMODE_PB_REQ = 6875; // 12 +const static uint64_t SH_FLD_FIR14_PD_DIR_MULT_HIT = 6876; // 12 +const static uint64_t SH_FLD_FIR14_PHANTOM_B01_REQ = 6877; // 12 +const static uint64_t SH_FLD_FIR14_RCMD0_ADDR_PERR = 6878; // 12 +const static uint64_t SH_FLD_FIR14_RCMD0_TTAG_PERR = 6879; // 12 +const static uint64_t SH_FLD_FIR14_RCMD1_ADDR_PERR = 6880; // 12 +const static uint64_t SH_FLD_FIR14_RCMD1_TTAG_PERR = 6881; // 12 +const static uint64_t SH_FLD_FIR14_RCMD2_ADDR_PERR = 6882; // 12 +const static uint64_t SH_FLD_FIR14_RCMD2_TTAG_PERR = 6883; // 12 +const static uint64_t SH_FLD_FIR14_RCMD3_ADDR_PERR = 6884; // 12 +const static uint64_t SH_FLD_FIR14_RCMD3_TTAG_PERR = 6885; // 12 +const static uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_CRESP = 6886; // 12 +const static uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_DWDONE = 6887; // 12 +const static uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_PBL3_DATA = 6888; // 12 +const static uint64_t SH_FLD_FIR14_RCX_UNEXP_IDLE_PB_CRESP = 6889; // 12 +const static uint64_t SH_FLD_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK = 6890; // 12 +const static uint64_t SH_FLD_FIR14_RC_PBBUS_SFSTAT = 6891; // 12 +const static uint64_t SH_FLD_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK = 6892; // 12 +const static uint64_t SH_FLD_FIR14_RC_UNEXP_F2_DATA = 6893; // 12 +const static uint64_t SH_FLD_FIR14_RC_UNEXP_PURG_HIT = 6894; // 12 +const static uint64_t SH_FLD_FIR14_RVCTL = 6895; // 12 +const static uint64_t SH_FLD_FIR14_SRCTL0_BAD_HPC = 6896; // 12 +const static uint64_t SH_FLD_FIR14_SRCTL1_BAD_HPC = 6897; // 12 +const static uint64_t SH_FLD_FIR14_SRCTL2_BAD_HPC = 6898; // 12 +const static uint64_t SH_FLD_FIR14_SRCTL3_BAD_HPC = 6899; // 12 +const static uint64_t SH_FLD_FIR14_STQ_COMING = 6900; // 12 +const static uint64_t SH_FLD_FIR14_STQ_OVERFLOW = 6901; // 12 +const static uint64_t SH_FLD_FIR14_TMA_LARXA_VS_FRCMISS_SV = 6902; // 12 +const static uint64_t SH_FLD_FIR14_TMCTL_TIDX_TEND_LDST_SEQ = 6903; // 12 +const static uint64_t SH_FLD_FIR14_XLT_QUEUE_OVRFLW = 6904; // 12 +const static uint64_t SH_FLD_FIR14_XPF_MULT_REQ = 6905; // 12 +const static uint64_t SH_FLD_FIR19_LD_TGT_NODAL_DINC = 6906; // 12 +const static uint64_t SH_FLD_FIR19_ST_TGT_NODAL_DINC = 6907; // 12 +const static uint64_t SH_FLD_FIR1_MASTER_SEQ_ID_PAR = 6908; // 12 +const static uint64_t SH_FLD_FIR1_RSVD_37 = 6909; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_38 = 6910; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_39 = 6911; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_40 = 6912; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_41 = 6913; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_42 = 6914; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_43 = 6915; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_44 = 6916; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_45 = 6917; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_46 = 6918; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_47 = 6919; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_48 = 6920; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_49 = 6921; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_50 = 6922; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_51 = 6923; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_52 = 6924; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_53 = 6925; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_54 = 6926; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_55 = 6927; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_56 = 6928; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_57 = 6929; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_58 = 6930; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_59 = 6931; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_60 = 6932; // 1 +const static uint64_t SH_FLD_FIR1_RSVD_61 = 6933; // 1 +const static uint64_t SH_FLD_FIR1_SNOOP_TLBIE_SEQ_PARITY = 6934; // 12 +const static uint64_t SH_FLD_FIR1_TLBIE_BAD_OP = 6935; // 12 +const static uint64_t SH_FLD_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC = 6936; // 12 +const static uint64_t SH_FLD_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC = 6937; // 12 +const static uint64_t SH_FLD_FIR9_PEC_PHASE3_TIMEOUT = 6938; // 12 +const static uint64_t SH_FLD_FIR9_PEC_PHASE4_RCCO_DISP_FAIL = 6939; // 12 +const static uint64_t SH_FLD_FIR9_PEC_PHASE4_SAME = 6940; // 12 +const static uint64_t SH_FLD_FIR9_PEC_PHASE5_TIMEOUT = 6941; // 12 +const static uint64_t SH_FLD_FIRMWARE_FAULT = 6942; // 1 +const static uint64_t SH_FLD_FIRMWARE_NOTIFY = 6943; // 1 +const static uint64_t SH_FLD_FIRST_ERROR = 6944; // 3 +const static uint64_t SH_FLD_FIRST_ERROR_CAPTURED = 6945; // 1 +const static uint64_t SH_FLD_FIRST_ERROR_DECODE = 6946; // 1 +const static uint64_t SH_FLD_FIRST_ERROR_DECODE_LEN = 6947; // 1 +const static uint64_t SH_FLD_FIRST_ERROR_INFO = 6948; // 1 +const static uint64_t SH_FLD_FIRST_ERROR_INFO_LEN = 6949; // 1 +const static uint64_t SH_FLD_FIRST_ERROR_LEN = 6950; // 3 +const static uint64_t SH_FLD_FIRST_ERROR_SPARE = 6951; // 1 +const static uint64_t SH_FLD_FIRST_ERROR_SPARE_LEN = 6952; // 1 +const static uint64_t SH_FLD_FIR_ACTION0 = 6953; // 16 +const static uint64_t SH_FLD_FIR_ACTION0_LEN = 6954; // 16 +const static uint64_t SH_FLD_FIR_ACTION1 = 6955; // 16 +const static uint64_t SH_FLD_FIR_ACTION1_LEN = 6956; // 16 +const static uint64_t SH_FLD_FIR_LEN = 6957; // 48 +const static uint64_t SH_FLD_FIR_MASK = 6958; // 19 +const static uint64_t SH_FLD_FIR_MASK_LEN = 6959; // 19 +const static uint64_t SH_FLD_FIR_PARITY_ERR = 6960; // 15 +const static uint64_t SH_FLD_FIR_PARITY_ERR2 = 6961; // 1 +const static uint64_t SH_FLD_FIR_PARITY_ERR2_MASK = 6962; // 1 +const static uint64_t SH_FLD_FIR_PARITY_ERR_DUP = 6963; // 13 +const static uint64_t SH_FLD_FIR_PARITY_ERR_DUP_MASK = 6964; // 1 +const static uint64_t SH_FLD_FIR_PARITY_ERR_MASK = 6965; // 2 +const static uint64_t SH_FLD_FIR_RESET = 6966; // 6 +const static uint64_t SH_FLD_FIR_TRIGGER = 6967; // 17 +const static uint64_t SH_FLD_FIT_SEL = 6968; // 17 +const static uint64_t SH_FLD_FIT_SEL_LEN = 6969; // 17 +const static uint64_t SH_FLD_FLUSH_ALIGN_OVR = 6970; // 43 +const static uint64_t SH_FLD_FLUSH_CP_IG_STATE_MAP = 6971; // 2 +const static uint64_t SH_FLD_FLUSH_CP_IG_STATE_MAP_LEN = 6972; // 2 +const static uint64_t SH_FLD_FLUSH_IC = 6973; // 24 +const static uint64_t SH_FLD_FLUSH_SCAN_N = 6974; // 43 +const static uint64_t SH_FLD_FLUSH_SUE_STATE_MAP = 6975; // 2 +const static uint64_t SH_FLD_FLUSH_SUE_STATE_MAP_LEN = 6976; // 2 +const static uint64_t SH_FLD_FMAX = 6977; // 6 +const static uint64_t SH_FLD_FMAX_LEN = 6978; // 6 +const static uint64_t SH_FLD_FMIN = 6979; // 6 +const static uint64_t SH_FLD_FMIN_LEN = 6980; // 6 +const static uint64_t SH_FLD_FMR00_TRAINED = 6981; // 4 +const static uint64_t SH_FLD_FMR01_TRAINED = 6982; // 4 +const static uint64_t SH_FLD_FMR02_TRAINED = 6983; // 4 +const static uint64_t SH_FLD_FMR03_TRAINED = 6984; // 4 +const static uint64_t SH_FLD_FMR04_TRAINED = 6985; // 4 +const static uint64_t SH_FLD_FMR05_TRAINED = 6986; // 4 +const static uint64_t SH_FLD_FMR06_TRAINED = 6987; // 2 +const static uint64_t SH_FLD_FMR07_TRAINED = 6988; // 2 +const static uint64_t SH_FLD_FMULT = 6989; // 6 +const static uint64_t SH_FLD_FMULT_LEN = 6990; // 6 +const static uint64_t SH_FLD_FORCE_ALL_RINGS = 6991; // 43 +const static uint64_t SH_FLD_FORCE_BYPASS = 6992; // 1 +const static uint64_t SH_FLD_FORCE_CL_INJECT = 6993; // 1 +const static uint64_t SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR = 6994; // 5 +const static uint64_t SH_FLD_FORCE_DROOP_DATA = 6995; // 6 +const static uint64_t SH_FLD_FORCE_DROOP_DATA_LEN = 6996; // 6 +const static uint64_t SH_FLD_FORCE_ECC_CE = 6997; // 2 +const static uint64_t SH_FLD_FORCE_ECC_SEL = 6998; // 1 +const static uint64_t SH_FLD_FORCE_ECC_SEL_0_1 = 6999; // 1 +const static uint64_t SH_FLD_FORCE_ECC_SEL_0_1_LEN = 7000; // 1 +const static uint64_t SH_FLD_FORCE_ECC_UE = 7001; // 2 +const static uint64_t SH_FLD_FORCE_FSAFE = 7002; // 6 +const static uint64_t SH_FLD_FORCE_MAX_SCOPE_INTRP = 7003; // 1 +const static uint64_t SH_FLD_FORCE_MPR = 7004; // 8 +const static uint64_t SH_FLD_FORCE_MP_IPL = 7005; // 2 +const static uint64_t SH_FLD_FORCE_ON_CLK_GATE = 7006; // 8 +const static uint64_t SH_FLD_FORCE_PR_INJECT = 7007; // 1 +const static uint64_t SH_FLD_FORCE_QUIESCE = 7008; // 2 +const static uint64_t SH_FLD_FORCE_RESERVED = 7009; // 8 +const static uint64_t SH_FLD_FORCE_RESET = 7010; // 1 +const static uint64_t SH_FLD_FORCE_SFSTAT_ACTIVE = 7011; // 4 +const static uint64_t SH_FLD_FORCE_SINGLE_BIT_ECC_ERR = 7012; // 5 +const static uint64_t SH_FLD_FORCE_TEST = 7013; // 43 +const static uint64_t SH_FLD_FORCE_TEST_MODE = 7014; // 86 +const static uint64_t SH_FLD_FORCE_THRES_ACT = 7015; // 43 +const static uint64_t SH_FLD_FORCE_VG_SYS_INTRP = 7016; // 1 +const static uint64_t SH_FLD_FOREIGN_LINK_HANG_ERROR = 7017; // 4 +const static uint64_t SH_FLD_FP0_CREDIT_PRIORITY_4_NOT_8 = 7018; // 2 +const static uint64_t SH_FLD_FP0_DISABLE_CMD_COMPRESSION = 7019; // 2 +const static uint64_t SH_FLD_FP0_DISABLE_GATHERING = 7020; // 2 +const static uint64_t SH_FLD_FP0_DISABLE_PRSP_COMPRESSION = 7021; // 2 +const static uint64_t SH_FLD_FP0_FMR_DISABLE = 7022; // 2 +const static uint64_t SH_FLD_FP0_FMR_SPARE = 7023; // 2 +const static uint64_t SH_FLD_FP0_LL_CREDIT_HI_LIMIT = 7024; // 2 +const static uint64_t SH_FLD_FP0_LL_CREDIT_HI_LIMIT_LEN = 7025; // 2 +const static uint64_t SH_FLD_FP0_LL_CREDIT_LO_LIMIT = 7026; // 2 +const static uint64_t SH_FLD_FP0_LL_CREDIT_LO_LIMIT_LEN = 7027; // 2 +const static uint64_t SH_FLD_FP0_PRS_DISABLE = 7028; // 2 +const static uint64_t SH_FLD_FP0_PRS_SPARE = 7029; // 2 +const static uint64_t SH_FLD_FP0_PRS_SPARE_LEN = 7030; // 2 +const static uint64_t SH_FLD_FP0_RUN_AFTER_FRAME_ERROR = 7031; // 2 +const static uint64_t SH_FLD_FP1_CREDIT_PRIORITY_4_NOT_8 = 7032; // 2 +const static uint64_t SH_FLD_FP1_DISABLE_CMD_COMPRESSION = 7033; // 2 +const static uint64_t SH_FLD_FP1_DISABLE_GATHERING = 7034; // 2 +const static uint64_t SH_FLD_FP1_DISABLE_PRSP_COMPRESSION = 7035; // 2 +const static uint64_t SH_FLD_FP1_FMR_DISABLE = 7036; // 2 +const static uint64_t SH_FLD_FP1_FMR_SPARE = 7037; // 2 +const static uint64_t SH_FLD_FP1_FMR_SPARE_LEN = 7038; // 2 +const static uint64_t SH_FLD_FP1_LL_CREDIT_HI_LIMIT = 7039; // 2 +const static uint64_t SH_FLD_FP1_LL_CREDIT_HI_LIMIT_LEN = 7040; // 2 +const static uint64_t SH_FLD_FP1_LL_CREDIT_LO_LIMIT = 7041; // 2 +const static uint64_t SH_FLD_FP1_LL_CREDIT_LO_LIMIT_LEN = 7042; // 2 +const static uint64_t SH_FLD_FP1_PRS_DISABLE = 7043; // 2 +const static uint64_t SH_FLD_FP1_PRS_SPARE = 7044; // 2 +const static uint64_t SH_FLD_FP1_PRS_SPARE_LEN = 7045; // 2 +const static uint64_t SH_FLD_FP1_RUN_AFTER_FRAME_ERROR = 7046; // 2 +const static uint64_t SH_FLD_FP2_CREDIT_PRIORITY_4_NOT_8 = 7047; // 2 +const static uint64_t SH_FLD_FP2_DISABLE_CMD_COMPRESSION = 7048; // 2 +const static uint64_t SH_FLD_FP2_DISABLE_GATHERING = 7049; // 2 +const static uint64_t SH_FLD_FP2_DISABLE_PRSP_COMPRESSION = 7050; // 2 +const static uint64_t SH_FLD_FP2_FMR_DISABLE = 7051; // 2 +const static uint64_t SH_FLD_FP2_FMR_SPARE = 7052; // 2 +const static uint64_t SH_FLD_FP2_LL_CREDIT_HI_LIMIT = 7053; // 2 +const static uint64_t SH_FLD_FP2_LL_CREDIT_HI_LIMIT_LEN = 7054; // 2 +const static uint64_t SH_FLD_FP2_LL_CREDIT_LO_LIMIT = 7055; // 2 +const static uint64_t SH_FLD_FP2_LL_CREDIT_LO_LIMIT_LEN = 7056; // 2 +const static uint64_t SH_FLD_FP2_PRS_DISABLE = 7057; // 2 +const static uint64_t SH_FLD_FP2_PRS_SPARE = 7058; // 2 +const static uint64_t SH_FLD_FP2_PRS_SPARE_LEN = 7059; // 2 +const static uint64_t SH_FLD_FP2_RUN_AFTER_FRAME_ERROR = 7060; // 2 +const static uint64_t SH_FLD_FP3_CREDIT_PRIORITY_4_NOT_8 = 7061; // 2 +const static uint64_t SH_FLD_FP3_DISABLE_CMD_COMPRESSION = 7062; // 2 +const static uint64_t SH_FLD_FP3_DISABLE_GATHERING = 7063; // 2 +const static uint64_t SH_FLD_FP3_DISABLE_PRSP_COMPRESSION = 7064; // 2 +const static uint64_t SH_FLD_FP3_FMR_DISABLE = 7065; // 2 +const static uint64_t SH_FLD_FP3_FMR_SPARE = 7066; // 2 +const static uint64_t SH_FLD_FP3_FMR_SPARE_LEN = 7067; // 2 +const static uint64_t SH_FLD_FP3_LL_CREDIT_HI_LIMIT = 7068; // 2 +const static uint64_t SH_FLD_FP3_LL_CREDIT_HI_LIMIT_LEN = 7069; // 2 +const static uint64_t SH_FLD_FP3_LL_CREDIT_LO_LIMIT = 7070; // 2 +const static uint64_t SH_FLD_FP3_LL_CREDIT_LO_LIMIT_LEN = 7071; // 2 +const static uint64_t SH_FLD_FP3_PRS_DISABLE = 7072; // 2 +const static uint64_t SH_FLD_FP3_PRS_SPARE = 7073; // 2 +const static uint64_t SH_FLD_FP3_PRS_SPARE_LEN = 7074; // 2 +const static uint64_t SH_FLD_FP3_RUN_AFTER_FRAME_ERROR = 7075; // 2 +const static uint64_t SH_FLD_FP4_CREDIT_PRIORITY_4_NOT_8 = 7076; // 2 +const static uint64_t SH_FLD_FP4_DISABLE_CMD_COMPRESSION = 7077; // 2 +const static uint64_t SH_FLD_FP4_DISABLE_GATHERING = 7078; // 2 +const static uint64_t SH_FLD_FP4_DISABLE_PRSP_COMPRESSION = 7079; // 2 +const static uint64_t SH_FLD_FP4_FMR_DISABLE = 7080; // 2 +const static uint64_t SH_FLD_FP4_FMR_SPARE = 7081; // 2 +const static uint64_t SH_FLD_FP4_LL_CREDIT_HI_LIMIT = 7082; // 2 +const static uint64_t SH_FLD_FP4_LL_CREDIT_HI_LIMIT_LEN = 7083; // 2 +const static uint64_t SH_FLD_FP4_LL_CREDIT_LO_LIMIT = 7084; // 2 +const static uint64_t SH_FLD_FP4_LL_CREDIT_LO_LIMIT_LEN = 7085; // 2 +const static uint64_t SH_FLD_FP4_PRS_DISABLE = 7086; // 2 +const static uint64_t SH_FLD_FP4_PRS_SPARE = 7087; // 2 +const static uint64_t SH_FLD_FP4_PRS_SPARE_LEN = 7088; // 2 +const static uint64_t SH_FLD_FP4_RUN_AFTER_FRAME_ERROR = 7089; // 2 +const static uint64_t SH_FLD_FP5_CREDIT_PRIORITY_4_NOT_8 = 7090; // 2 +const static uint64_t SH_FLD_FP5_DISABLE_CMD_COMPRESSION = 7091; // 2 +const static uint64_t SH_FLD_FP5_DISABLE_GATHERING = 7092; // 2 +const static uint64_t SH_FLD_FP5_DISABLE_PRSP_COMPRESSION = 7093; // 2 +const static uint64_t SH_FLD_FP5_FMR_DISABLE = 7094; // 2 +const static uint64_t SH_FLD_FP5_FMR_SPARE = 7095; // 2 +const static uint64_t SH_FLD_FP5_FMR_SPARE_LEN = 7096; // 2 +const static uint64_t SH_FLD_FP5_LL_CREDIT_HI_LIMIT = 7097; // 2 +const static uint64_t SH_FLD_FP5_LL_CREDIT_HI_LIMIT_LEN = 7098; // 2 +const static uint64_t SH_FLD_FP5_LL_CREDIT_LO_LIMIT = 7099; // 2 +const static uint64_t SH_FLD_FP5_LL_CREDIT_LO_LIMIT_LEN = 7100; // 2 +const static uint64_t SH_FLD_FP5_PRS_DISABLE = 7101; // 2 +const static uint64_t SH_FLD_FP5_PRS_SPARE = 7102; // 2 +const static uint64_t SH_FLD_FP5_PRS_SPARE_LEN = 7103; // 2 +const static uint64_t SH_FLD_FP5_RUN_AFTER_FRAME_ERROR = 7104; // 2 +const static uint64_t SH_FLD_FP6_CREDIT_PRIORITY_4_NOT_8 = 7105; // 1 +const static uint64_t SH_FLD_FP6_DISABLE_CMD_COMPRESSION = 7106; // 1 +const static uint64_t SH_FLD_FP6_DISABLE_GATHERING = 7107; // 1 +const static uint64_t SH_FLD_FP6_DISABLE_PRSP_COMPRESSION = 7108; // 1 +const static uint64_t SH_FLD_FP6_FMR_DISABLE = 7109; // 1 +const static uint64_t SH_FLD_FP6_FMR_SPARE = 7110; // 1 +const static uint64_t SH_FLD_FP6_LL_CREDIT_HI_LIMIT = 7111; // 1 +const static uint64_t SH_FLD_FP6_LL_CREDIT_HI_LIMIT_LEN = 7112; // 1 +const static uint64_t SH_FLD_FP6_LL_CREDIT_LO_LIMIT = 7113; // 1 +const static uint64_t SH_FLD_FP6_LL_CREDIT_LO_LIMIT_LEN = 7114; // 1 +const static uint64_t SH_FLD_FP6_PRS_DISABLE = 7115; // 1 +const static uint64_t SH_FLD_FP6_PRS_SPARE = 7116; // 1 +const static uint64_t SH_FLD_FP6_PRS_SPARE_LEN = 7117; // 1 +const static uint64_t SH_FLD_FP6_RUN_AFTER_FRAME_ERROR = 7118; // 1 +const static uint64_t SH_FLD_FP7_CREDIT_PRIORITY_4_NOT_8 = 7119; // 1 +const static uint64_t SH_FLD_FP7_DISABLE_CMD_COMPRESSION = 7120; // 1 +const static uint64_t SH_FLD_FP7_DISABLE_GATHERING = 7121; // 1 +const static uint64_t SH_FLD_FP7_DISABLE_PRSP_COMPRESSION = 7122; // 1 +const static uint64_t SH_FLD_FP7_FMR_DISABLE = 7123; // 1 +const static uint64_t SH_FLD_FP7_FMR_SPARE = 7124; // 1 +const static uint64_t SH_FLD_FP7_FMR_SPARE_LEN = 7125; // 1 +const static uint64_t SH_FLD_FP7_LL_CREDIT_HI_LIMIT = 7126; // 1 +const static uint64_t SH_FLD_FP7_LL_CREDIT_HI_LIMIT_LEN = 7127; // 1 +const static uint64_t SH_FLD_FP7_LL_CREDIT_LO_LIMIT = 7128; // 1 +const static uint64_t SH_FLD_FP7_LL_CREDIT_LO_LIMIT_LEN = 7129; // 1 +const static uint64_t SH_FLD_FP7_PRS_DISABLE = 7130; // 1 +const static uint64_t SH_FLD_FP7_PRS_SPARE = 7131; // 1 +const static uint64_t SH_FLD_FP7_PRS_SPARE_LEN = 7132; // 1 +const static uint64_t SH_FLD_FP7_RUN_AFTER_FRAME_ERROR = 7133; // 1 +const static uint64_t SH_FLD_FRAC1 = 7134; // 3 +const static uint64_t SH_FLD_FRAC1_LEN = 7135; // 3 +const static uint64_t SH_FLD_FRAC2 = 7136; // 3 +const static uint64_t SH_FLD_FRAC2_LEN = 7137; // 3 +const static uint64_t SH_FLD_FRAMER00_ATTN = 7138; // 4 +const static uint64_t SH_FLD_FRAMER01_ATTN = 7139; // 4 +const static uint64_t SH_FLD_FRAMER02_ATTN = 7140; // 4 +const static uint64_t SH_FLD_FRAMER03_ATTN = 7141; // 4 +const static uint64_t SH_FLD_FRAMER04_ATTN = 7142; // 4 +const static uint64_t SH_FLD_FRAMER05_ATTN = 7143; // 4 +const static uint64_t SH_FLD_FRAMER06_ATTN = 7144; // 2 +const static uint64_t SH_FLD_FRAMER07_ATTN = 7145; // 2 +const static uint64_t SH_FLD_FRAME_COUNT = 7146; // 8 +const static uint64_t SH_FLD_FRAME_COUNT_LEN = 7147; // 8 +const static uint64_t SH_FLD_FRAME_SIZE = 7148; // 1 +const static uint64_t SH_FLD_FRAME_SIZE_LEN = 7149; // 1 +const static uint64_t SH_FLD_FREE = 7150; // 12 +const static uint64_t SH_FLD_FREEZE = 7151; // 10 +const static uint64_t SH_FLD_FREEZEMODE = 7152; // 9 +const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR1 = 7153; // 1 +const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR2 = 7154; // 1 +const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR3 = 7155; // 1 +const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR4 = 7156; // 1 +const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR5 = 7157; // 1 +const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR6 = 7158; // 1 +const static uint64_t SH_FLD_FREEZE_LOG_ON_ERROR7 = 7159; // 1 +const static uint64_t SH_FLD_FREEZE_ON_OVERFLOW = 7160; // 2 +const static uint64_t SH_FLD_FREEZE_SEL = 7161; // 43 +const static uint64_t SH_FLD_FREE_USAGE_10E = 7162; // 19 +const static uint64_t SH_FLD_FREE_USAGE_11E = 7163; // 19 +const static uint64_t SH_FLD_FREE_USAGE_12D = 7164; // 31 +const static uint64_t SH_FLD_FREE_USAGE_12E = 7165; // 41 +const static uint64_t SH_FLD_FREE_USAGE_13D = 7166; // 32 +const static uint64_t SH_FLD_FREE_USAGE_13E = 7167; // 41 +const static uint64_t SH_FLD_FREE_USAGE_14D = 7168; // 34 +const static uint64_t SH_FLD_FREE_USAGE_14E = 7169; // 41 +const static uint64_t SH_FLD_FREE_USAGE_15D = 7170; // 34 +const static uint64_t SH_FLD_FREE_USAGE_15E = 7171; // 41 +const static uint64_t SH_FLD_FREE_USAGE_16D = 7172; // 38 +const static uint64_t SH_FLD_FREE_USAGE_16E = 7173; // 41 +const static uint64_t SH_FLD_FREE_USAGE_17D = 7174; // 38 +const static uint64_t SH_FLD_FREE_USAGE_17E = 7175; // 41 +const static uint64_t SH_FLD_FREE_USAGE_18D = 7176; // 40 +const static uint64_t SH_FLD_FREE_USAGE_18E = 7177; // 41 +const static uint64_t SH_FLD_FREE_USAGE_19D = 7178; // 41 +const static uint64_t SH_FLD_FREE_USAGE_19E = 7179; // 41 +const static uint64_t SH_FLD_FREE_USAGE_20D = 7180; // 41 +const static uint64_t SH_FLD_FREE_USAGE_20E = 7181; // 43 +const static uint64_t SH_FLD_FREE_USAGE_21D = 7182; // 41 +const static uint64_t SH_FLD_FREE_USAGE_21E = 7183; // 43 +const static uint64_t SH_FLD_FREE_USAGE_22D = 7184; // 41 +const static uint64_t SH_FLD_FREE_USAGE_22E = 7185; // 43 +const static uint64_t SH_FLD_FREE_USAGE_23D = 7186; // 41 +const static uint64_t SH_FLD_FREE_USAGE_23E = 7187; // 43 +const static uint64_t SH_FLD_FREE_USAGE_24D = 7188; // 41 +const static uint64_t SH_FLD_FREE_USAGE_25D = 7189; // 41 +const static uint64_t SH_FLD_FREE_USAGE_26D = 7190; // 42 +const static uint64_t SH_FLD_FREE_USAGE_27D = 7191; // 42 +const static uint64_t SH_FLD_FREE_USAGE_28D = 7192; // 40 +const static uint64_t SH_FLD_FREE_USAGE_29D = 7193; // 40 +const static uint64_t SH_FLD_FREE_USAGE_30D = 7194; // 40 +const static uint64_t SH_FLD_FREE_USAGE_31D = 7195; // 40 +const static uint64_t SH_FLD_FREE_USAGE_44C = 7196; // 43 +const static uint64_t SH_FLD_FREE_USAGE_45C = 7197; // 43 +const static uint64_t SH_FLD_FREE_USAGE_46C = 7198; // 43 +const static uint64_t SH_FLD_FREE_USAGE_47C = 7199; // 43 +const static uint64_t SH_FLD_FREE_USAGE_48A = 7200; // 43 +const static uint64_t SH_FLD_FREE_USAGE_49A = 7201; // 43 +const static uint64_t SH_FLD_FREE_USAGE_50A = 7202; // 43 +const static uint64_t SH_FLD_FREE_USAGE_51A = 7203; // 43 +const static uint64_t SH_FLD_FREE_USAGE_52A = 7204; // 43 +const static uint64_t SH_FLD_FREE_USAGE_53A = 7205; // 43 +const static uint64_t SH_FLD_FREE_USAGE_54A = 7206; // 43 +const static uint64_t SH_FLD_FREE_USAGE_55A = 7207; // 43 +const static uint64_t SH_FLD_FREE_USAGE_56A = 7208; // 43 +const static uint64_t SH_FLD_FREE_USAGE_57A = 7209; // 43 +const static uint64_t SH_FLD_FREE_USAGE_58A = 7210; // 43 +const static uint64_t SH_FLD_FREE_USAGE_59A = 7211; // 43 +const static uint64_t SH_FLD_FREE_USAGE_60A = 7212; // 43 +const static uint64_t SH_FLD_FREE_USAGE_61A = 7213; // 43 +const static uint64_t SH_FLD_FREE_USAGE_62A = 7214; // 43 +const static uint64_t SH_FLD_FREE_USAGE_63A = 7215; // 43 +const static uint64_t SH_FLD_FREE_USAGE_6A = 7216; // 43 +const static uint64_t SH_FLD_FREE_USAGE_7A = 7217; // 43 +const static uint64_t SH_FLD_FREE_USAGE_9A = 7218; // 43 +const static uint64_t SH_FLD_FREQIN_AVG = 7219; // 6 +const static uint64_t SH_FLD_FREQIN_AVG_LEN = 7220; // 6 +const static uint64_t SH_FLD_FREQIN_MAX = 7221; // 6 +const static uint64_t SH_FLD_FREQIN_MAX_LEN = 7222; // 6 +const static uint64_t SH_FLD_FREQIN_MIN = 7223; // 6 +const static uint64_t SH_FLD_FREQIN_MIN_LEN = 7224; // 6 +const static uint64_t SH_FLD_FREQOUT = 7225; // 6 +const static uint64_t SH_FLD_FREQOUT_AVG = 7226; // 6 +const static uint64_t SH_FLD_FREQOUT_AVG_LEN = 7227; // 6 +const static uint64_t SH_FLD_FREQOUT_LEN = 7228; // 6 +const static uint64_t SH_FLD_FREQOUT_MAX = 7229; // 6 +const static uint64_t SH_FLD_FREQOUT_MAX_LEN = 7230; // 6 +const static uint64_t SH_FLD_FREQOUT_MIN = 7231; // 6 +const static uint64_t SH_FLD_FREQOUT_MIN_LEN = 7232; // 6 +const static uint64_t SH_FLD_FREQUENCY_REFERENCE = 7233; // 24 +const static uint64_t SH_FLD_FREQUENCY_REFERENCE_LEN = 7234; // 24 +const static uint64_t SH_FLD_FREQ_CHANGE = 7235; // 6 +const static uint64_t SH_FLD_FREQ_LCL_SAMPLE_EN = 7236; // 12 +const static uint64_t SH_FLD_FREQ_SCALE_A_THRESHOLD = 7237; // 24 +const static uint64_t SH_FLD_FREQ_SCALE_A_THRESHOLD_LEN = 7238; // 24 +const static uint64_t SH_FLD_FREQ_SCALE_B_THRESHOLD = 7239; // 24 +const static uint64_t SH_FLD_FREQ_SCALE_B_THRESHOLD_LEN = 7240; // 24 +const static uint64_t SH_FLD_FRZ_COUNT_ON_FRZ = 7241; // 43 +const static uint64_t SH_FLD_FSAFE = 7242; // 6 +const static uint64_t SH_FLD_FSAFE_ACTIVE = 7243; // 6 +const static uint64_t SH_FLD_FSAFE_LEN = 7244; // 6 +const static uint64_t SH_FLD_FSI_A_MST_0_ACTUAL_ERROR = 7245; // 1 +const static uint64_t SH_FLD_FSI_A_MST_0_ACTUAL_ERROR_LEN = 7246; // 1 +const static uint64_t SH_FLD_FSI_A_MST_0_PORT_0_ENABLE = 7247; // 1 +const static uint64_t SH_FLD_FSI_A_MST_0_PORT_1_ENABLE = 7248; // 1 +const static uint64_t SH_FLD_FSI_A_MST_0_PORT_2_ENABLE = 7249; // 1 +const static uint64_t SH_FLD_FSI_A_MST_0_PORT_3_ENABLE = 7250; // 1 +const static uint64_t SH_FLD_FSI_A_MST_0_PORT_4_ENABLE = 7251; // 1 +const static uint64_t SH_FLD_FSI_A_MST_0_PORT_5_ENABLE = 7252; // 1 +const static uint64_t SH_FLD_FSI_A_MST_0_PORT_6_ENABLE = 7253; // 1 +const static uint64_t SH_FLD_FSI_A_MST_0_PORT_7_ENABLE = 7254; // 1 +const static uint64_t SH_FLD_FSI_A_MST_1_ACTUAL_ERROR = 7255; // 1 +const static uint64_t SH_FLD_FSI_A_MST_1_ACTUAL_ERROR_LEN = 7256; // 1 +const static uint64_t SH_FLD_FSI_A_MST_1_PORT_0_ENABLE = 7257; // 1 +const static uint64_t SH_FLD_FSI_A_MST_1_PORT_1_ENABLE = 7258; // 1 +const static uint64_t SH_FLD_FSI_A_MST_1_PORT_2_ENABLE = 7259; // 1 +const static uint64_t SH_FLD_FSI_A_MST_1_PORT_3_ENABLE = 7260; // 1 +const static uint64_t SH_FLD_FSI_A_MST_1_PORT_4_ENABLE = 7261; // 1 +const static uint64_t SH_FLD_FSI_B_MST_0_ACTUAL_ERROR = 7262; // 1 +const static uint64_t SH_FLD_FSI_B_MST_0_ACTUAL_ERROR_LEN = 7263; // 1 +const static uint64_t SH_FLD_FSI_B_MST_0_PORT_0_ENABLE = 7264; // 1 +const static uint64_t SH_FLD_FSI_B_MST_0_PORT_1_ENABLE = 7265; // 1 +const static uint64_t SH_FLD_FSI_B_MST_0_PORT_2_ENABLE = 7266; // 1 +const static uint64_t SH_FLD_FSI_B_MST_0_PORT_3_ENABLE = 7267; // 1 +const static uint64_t SH_FLD_FSI_B_MST_0_PORT_4_ENABLE = 7268; // 1 +const static uint64_t SH_FLD_FSI_B_MST_0_PORT_5_ENABLE = 7269; // 1 +const static uint64_t SH_FLD_FSI_B_MST_0_PORT_6_ENABLE = 7270; // 1 +const static uint64_t SH_FLD_FSI_B_MST_0_PORT_7_ENABLE = 7271; // 1 +const static uint64_t SH_FLD_FSI_CC_VSB_CBS_CMD = 7272; // 3 +const static uint64_t SH_FLD_FSI_CC_VSB_CBS_CMD_LEN = 7273; // 3 +const static uint64_t SH_FLD_FSI_CC_VSB_CBS_REQ = 7274; // 3 +const static uint64_t SH_FLD_FSI_SCRATCH_PAD1 = 7275; // 1 +const static uint64_t SH_FLD_FSI_SCRATCH_PAD1_LEN = 7276; // 1 +const static uint64_t SH_FLD_FSI_SCRATCH_PAD2 = 7277; // 1 +const static uint64_t SH_FLD_FSI_SCRATCH_PAD2_LEN = 7278; // 1 +const static uint64_t SH_FLD_FSI_SCRATCH_PAD3 = 7279; // 1 +const static uint64_t SH_FLD_FSI_SCRATCH_PAD3_LEN = 7280; // 1 +const static uint64_t SH_FLD_FSMJ_EVENT = 7281; // 2 +const static uint64_t SH_FLD_FSMJ_EVENT_LEN = 7282; // 2 +const static uint64_t SH_FLD_FSMJ_EVENT_SEL = 7283; // 2 +const static uint64_t SH_FLD_FSMJ_EVENT_SEL_LEN = 7284; // 2 +const static uint64_t SH_FLD_FSMJ_FSM = 7285; // 2 +const static uint64_t SH_FLD_FSMJ_FSM_LEN = 7286; // 2 +const static uint64_t SH_FLD_FSMJ_FSM_SEL = 7287; // 2 +const static uint64_t SH_FLD_FSMJ_FSM_SEL_LEN = 7288; // 2 +const static uint64_t SH_FLD_FSM_DATA02 = 7289; // 1 +const static uint64_t SH_FLD_FSM_ERR = 7290; // 5 +const static uint64_t SH_FLD_FSM_ERROR = 7291; // 1 +const static uint64_t SH_FLD_FSM_PARITY_ERROR = 7292; // 3 +const static uint64_t SH_FLD_FSM_PERR = 7293; // 1 +const static uint64_t SH_FLD_FSM_PRESENT_STATE = 7294; // 1 +const static uint64_t SH_FLD_FSM_PRESENT_STATE_LEN = 7295; // 1 +const static uint64_t SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 7296; // 43 +const static uint64_t SH_FLD_FSM_SYNC_ENABLE = 7297; // 1 +const static uint64_t SH_FLD_FSM_TRIGGER = 7298; // 2 +const static uint64_t SH_FLD_FSP_ACCESS_TRUSTED_SPACE = 7299; // 4 +const static uint64_t SH_FLD_FSP_CMD_ENABLE = 7300; // 1 +const static uint64_t SH_FLD_FSP_ECC_ERR_CE = 7301; // 4 +const static uint64_t SH_FLD_FSP_ECC_ERR_UE = 7302; // 4 +const static uint64_t SH_FLD_FSP_ERR_RSP_ENABLE = 7303; // 1 +const static uint64_t SH_FLD_FSP_INBOUND_ACTIVE = 7304; // 1 +const static uint64_t SH_FLD_FSP_INTERRUPT = 7305; // 1 +const static uint64_t SH_FLD_FSP_INT_ENABLE = 7306; // 1 +const static uint64_t SH_FLD_FSP_INV_READ = 7307; // 1 +const static uint64_t SH_FLD_FSP_LINK_ACTIVE = 7308; // 1 +const static uint64_t SH_FLD_FSP_MMIO_ENABLE = 7309; // 1 +const static uint64_t SH_FLD_FSP_MMIO_MASK = 7310; // 1 +const static uint64_t SH_FLD_FSP_MMIO_MASK_LEN = 7311; // 1 +const static uint64_t SH_FLD_FSP_OUTBOUND_ACTIVE = 7312; // 1 +const static uint64_t SH_FLD_FSP_RESET = 7313; // 1 +const static uint64_t SH_FLD_FSP_SPECIAL_WKUP = 7314; // 30 +const static uint64_t SH_FLD_FSP_TCE_ENABLE = 7315; // 1 +const static uint64_t SH_FLD_FULL = 7316; // 2 +const static uint64_t SH_FLD_FULLMASK = 7317; // 1 +const static uint64_t SH_FLD_FULLMASK_LEN = 7318; // 1 +const static uint64_t SH_FLD_FULL_WRITEBACK_ENABLE = 7319; // 6 +const static uint64_t SH_FLD_FUNC = 7320; // 43 +const static uint64_t SH_FLD_FUNCTION = 7321; // 6 +const static uint64_t SH_FLD_FUNCTION_LEN = 7322; // 6 +const static uint64_t SH_FLD_FUNC_MODE_DONE = 7323; // 4 +const static uint64_t SH_FLD_FW0 = 7324; // 1 +const static uint64_t SH_FLD_FW0_MASK = 7325; // 1 +const static uint64_t SH_FLD_FW1 = 7326; // 1 +const static uint64_t SH_FLD_FW1_MASK = 7327; // 1 +const static uint64_t SH_FLD_FWD_PROG_RATE2 = 7328; // 12 +const static uint64_t SH_FLD_FWD_PROG_RATE2_LEN = 7329; // 12 +const static uint64_t SH_FLD_FWMSX_PE = 7330; // 8 +const static uint64_t SH_FLD_FWMSX_PE_LEN = 7331; // 8 +const static uint64_t SH_FLD_FW_RD_WR = 7332; // 8 +const static uint64_t SH_FLD_FW_RD_WR_LEN = 7333; // 8 +const static uint64_t SH_FLD_FW_WR_RD = 7334; // 8 +const static uint64_t SH_FLD_FW_WR_RD_LEN = 7335; // 8 +const static uint64_t SH_FLD_F_READ = 7336; // 43 +const static uint64_t SH_FLD_F_SKITTER_READ_MASK = 7337; // 43 +const static uint64_t SH_FLD_GCR_BUFFER_ENABLED_RO_SIGNAL = 7338; // 4 +const static uint64_t SH_FLD_GCR_HANG_DET_SEL = 7339; // 4 +const static uint64_t SH_FLD_GCR_HANG_DET_SEL_LEN = 7340; // 4 +const static uint64_t SH_FLD_GCR_HANG_ERROR_INJ = 7341; // 4 +const static uint64_t SH_FLD_GCR_HANG_ERROR_MASK = 7342; // 4 +const static uint64_t SH_FLD_GCR_TEST = 7343; // 4 +const static uint64_t SH_FLD_GENERAL_TIMEOUT = 7344; // 43 +const static uint64_t SH_FLD_GENERATE_MPIPL_SEQUENCE = 7345; // 4 +const static uint64_t SH_FLD_GLB_BRCST = 7346; // 43 +const static uint64_t SH_FLD_GLB_BRCST_LEN = 7347; // 43 +const static uint64_t SH_FLD_GLOBAL_EP_RESET_DC = 7348; // 3 +const static uint64_t SH_FLD_GLOBAL_PHY_OFFSET = 7349; // 8 +const static uint64_t SH_FLD_GLOBAL_PHY_OFFSET_LEN = 7350; // 8 +const static uint64_t SH_FLD_GLOBAL_RUN_MODE = 7351; // 2 +const static uint64_t SH_FLD_GO = 7352; // 43 +const static uint64_t SH_FLD_GO2 = 7353; // 43 +const static uint64_t SH_FLD_GOTO_CMD = 7354; // 64 +const static uint64_t SH_FLD_GOTO_CMD_LEN = 7355; // 64 +const static uint64_t SH_FLD_GP = 7356; // 2 +const static uint64_t SH_FLD_GPE0_ERROR = 7357; // 2 +const static uint64_t SH_FLD_GPE0_ERROR_MASK = 7358; // 1 +const static uint64_t SH_FLD_GPE0_HALTED = 7359; // 1 +const static uint64_t SH_FLD_GPE0_HALTED_MASK = 7360; // 1 +const static uint64_t SH_FLD_GPE0_OCISLV_ERR = 7361; // 2 +const static uint64_t SH_FLD_GPE0_OCISLV_ERR_LEN = 7362; // 1 +const static uint64_t SH_FLD_GPE0_OCISLV_ERR_MASK = 7363; // 1 +const static uint64_t SH_FLD_GPE0_WATCHDOG_TIMEOUT = 7364; // 1 +const static uint64_t SH_FLD_GPE0_WATCHDOG_TIMEOUT_MASK = 7365; // 1 +const static uint64_t SH_FLD_GPE1_ERROR = 7366; // 2 +const static uint64_t SH_FLD_GPE1_ERROR_MASK = 7367; // 1 +const static uint64_t SH_FLD_GPE1_HALTED = 7368; // 1 +const static uint64_t SH_FLD_GPE1_HALTED_MASK = 7369; // 1 +const static uint64_t SH_FLD_GPE1_OCISLV_ERR = 7370; // 2 +const static uint64_t SH_FLD_GPE1_OCISLV_ERR_LEN = 7371; // 1 +const static uint64_t SH_FLD_GPE1_OCISLV_ERR_MASK = 7372; // 1 +const static uint64_t SH_FLD_GPE1_WATCHDOG_TIMEOUT = 7373; // 1 +const static uint64_t SH_FLD_GPE1_WATCHDOG_TIMEOUT_MASK = 7374; // 1 +const static uint64_t SH_FLD_GPE2_ERROR = 7375; // 2 +const static uint64_t SH_FLD_GPE2_ERROR_MASK = 7376; // 1 +const static uint64_t SH_FLD_GPE2_HALTED = 7377; // 1 +const static uint64_t SH_FLD_GPE2_HALTED_MASK = 7378; // 1 +const static uint64_t SH_FLD_GPE2_OCISLV_ERR = 7379; // 2 +const static uint64_t SH_FLD_GPE2_OCISLV_ERR_LEN = 7380; // 1 +const static uint64_t SH_FLD_GPE2_OCISLV_ERR_MASK = 7381; // 1 +const static uint64_t SH_FLD_GPE2_WATCHDOG_TIMEOUT = 7382; // 1 +const static uint64_t SH_FLD_GPE2_WATCHDOG_TIMEOUT_MASK = 7383; // 1 +const static uint64_t SH_FLD_GPE3_ERROR = 7384; // 2 +const static uint64_t SH_FLD_GPE3_ERROR_MASK = 7385; // 1 +const static uint64_t SH_FLD_GPE3_HALTED = 7386; // 1 +const static uint64_t SH_FLD_GPE3_HALTED_MASK = 7387; // 1 +const static uint64_t SH_FLD_GPE3_OCISLV_ERR = 7388; // 2 +const static uint64_t SH_FLD_GPE3_OCISLV_ERR_LEN = 7389; // 1 +const static uint64_t SH_FLD_GPE3_OCISLV_ERR_MASK = 7390; // 1 +const static uint64_t SH_FLD_GPE3_WATCHDOG_TIMEOUT = 7391; // 1 +const static uint64_t SH_FLD_GPE3_WATCHDOG_TIMEOUT_MASK = 7392; // 1 +const static uint64_t SH_FLD_GP_TP_GLBCK_VSB_NEST_MESH_SEL_DC = 7393; // 3 +const static uint64_t SH_FLD_GRANTED_PACKET = 7394; // 30 +const static uint64_t SH_FLD_GRANTED_PACKET_LEN = 7395; // 30 +const static uint64_t SH_FLD_GRANTED_SOURCE = 7396; // 30 +const static uint64_t SH_FLD_GRANTED_SOURCE_LEN = 7397; // 30 +const static uint64_t SH_FLD_GROUP = 7398; // 9 +const static uint64_t SH_FLD_GROUPING = 7399; // 8 +const static uint64_t SH_FLD_GROUPING_LEN = 7400; // 8 +const static uint64_t SH_FLD_GROUP_BASE_ADDRESS = 7401; // 8 +const static uint64_t SH_FLD_GROUP_BASE_ADDRESS_LEN = 7402; // 8 +const static uint64_t SH_FLD_GROUP_EPSILON = 7403; // 8 +const static uint64_t SH_FLD_GROUP_EPSILON_LEN = 7404; // 8 +const static uint64_t SH_FLD_GROUP_LEN = 7405; // 9 +const static uint64_t SH_FLD_GROUP_SEL_0_4 = 7406; // 1 +const static uint64_t SH_FLD_GROUP_SEL_0_4_LEN = 7407; // 1 +const static uint64_t SH_FLD_GROUP_SIZE = 7408; // 8 +const static uint64_t SH_FLD_GROUP_SIZE_LEN = 7409; // 8 +const static uint64_t SH_FLD_GRPSEL = 7410; // 2 +const static uint64_t SH_FLD_GRPSEL_LEN = 7411; // 2 +const static uint64_t SH_FLD_GRP_BASE = 7412; // 8 +const static uint64_t SH_FLD_GRP_BASE_LEN = 7413; // 8 +const static uint64_t SH_FLD_GRP_MBR_ID = 7414; // 8 +const static uint64_t SH_FLD_GRP_SIZE = 7415; // 8 +const static uint64_t SH_FLD_GRP_SIZE_LEN = 7416; // 8 +const static uint64_t SH_FLD_GUESS_WAIT_TIME = 7417; // 8 +const static uint64_t SH_FLD_GUESS_WAIT_TIME_LEN = 7418; // 8 +const static uint64_t SH_FLD_GX = 7419; // 2 +const static uint64_t SH_FLD_GXSTP0_TRIG_IN0 = 7420; // 43 +const static uint64_t SH_FLD_GXSTP0_TRIG_IN1 = 7421; // 43 +const static uint64_t SH_FLD_GXSTP0_TRIG_IN10 = 7422; // 43 +const static uint64_t SH_FLD_GXSTP0_TRIG_IN11 = 7423; // 43 +const static uint64_t SH_FLD_GXSTP0_TRIG_IN2 = 7424; // 43 +const static uint64_t SH_FLD_GXSTP0_TRIG_IN3 = 7425; // 43 +const static uint64_t SH_FLD_GXSTP0_TRIG_IN4 = 7426; // 43 +const static uint64_t SH_FLD_GXSTP0_TRIG_IN5 = 7427; // 43 +const static uint64_t SH_FLD_GXSTP0_TRIG_IN6 = 7428; // 43 +const static uint64_t SH_FLD_GXSTP0_TRIG_IN7 = 7429; // 43 +const static uint64_t SH_FLD_GXSTP0_TRIG_IN8 = 7430; // 43 +const static uint64_t SH_FLD_GXSTP0_TRIG_IN9 = 7431; // 43 +const static uint64_t SH_FLD_GXSTP1_TRIG_IN0 = 7432; // 43 +const static uint64_t SH_FLD_GXSTP1_TRIG_IN1 = 7433; // 43 +const static uint64_t SH_FLD_GXSTP1_TRIG_IN10 = 7434; // 43 +const static uint64_t SH_FLD_GXSTP1_TRIG_IN11 = 7435; // 43 +const static uint64_t SH_FLD_GXSTP1_TRIG_IN2 = 7436; // 43 +const static uint64_t SH_FLD_GXSTP1_TRIG_IN3 = 7437; // 43 +const static uint64_t SH_FLD_GXSTP1_TRIG_IN4 = 7438; // 43 +const static uint64_t SH_FLD_GXSTP1_TRIG_IN5 = 7439; // 43 +const static uint64_t SH_FLD_GXSTP1_TRIG_IN6 = 7440; // 43 +const static uint64_t SH_FLD_GXSTP1_TRIG_IN7 = 7441; // 43 +const static uint64_t SH_FLD_GXSTP1_TRIG_IN8 = 7442; // 43 +const static uint64_t SH_FLD_GXSTP1_TRIG_IN9 = 7443; // 43 +const static uint64_t SH_FLD_GXSTP2_TRIG_IN0 = 7444; // 43 +const static uint64_t SH_FLD_GXSTP2_TRIG_IN1 = 7445; // 43 +const static uint64_t SH_FLD_GXSTP2_TRIG_IN10 = 7446; // 43 +const static uint64_t SH_FLD_GXSTP2_TRIG_IN11 = 7447; // 43 +const static uint64_t SH_FLD_GXSTP2_TRIG_IN2 = 7448; // 43 +const static uint64_t SH_FLD_GXSTP2_TRIG_IN3 = 7449; // 43 +const static uint64_t SH_FLD_GXSTP2_TRIG_IN4 = 7450; // 43 +const static uint64_t SH_FLD_GXSTP2_TRIG_IN5 = 7451; // 43 +const static uint64_t SH_FLD_GXSTP2_TRIG_IN6 = 7452; // 43 +const static uint64_t SH_FLD_GXSTP2_TRIG_IN7 = 7453; // 43 +const static uint64_t SH_FLD_GXSTP2_TRIG_IN8 = 7454; // 43 +const static uint64_t SH_FLD_GXSTP2_TRIG_IN9 = 7455; // 43 +const static uint64_t SH_FLD_GXSTP_IN0 = 7456; // 43 +const static uint64_t SH_FLD_GXSTP_IN1 = 7457; // 43 +const static uint64_t SH_FLD_GXSTP_IN10 = 7458; // 43 +const static uint64_t SH_FLD_GXSTP_IN11 = 7459; // 43 +const static uint64_t SH_FLD_GXSTP_IN2 = 7460; // 43 +const static uint64_t SH_FLD_GXSTP_IN3 = 7461; // 43 +const static uint64_t SH_FLD_GXSTP_IN4 = 7462; // 43 +const static uint64_t SH_FLD_GXSTP_IN5 = 7463; // 43 +const static uint64_t SH_FLD_GXSTP_IN6 = 7464; // 43 +const static uint64_t SH_FLD_GXSTP_IN7 = 7465; // 43 +const static uint64_t SH_FLD_GXSTP_IN8 = 7466; // 43 +const static uint64_t SH_FLD_GXSTP_IN9 = 7467; // 43 +const static uint64_t SH_FLD_GX_ENABLE_OVERWRITE = 7468; // 1 +const static uint64_t SH_FLD_GX_LEN = 7469; // 2 +const static uint64_t SH_FLD_GZIPCOMP_MAX_INRD = 7470; // 1 +const static uint64_t SH_FLD_GZIPCOMP_MAX_INRD_LEN = 7471; // 1 +const static uint64_t SH_FLD_GZIPDECOMP_MAX_INRD = 7472; // 1 +const static uint64_t SH_FLD_GZIPDECOMP_MAX_INRD_LEN = 7473; // 1 +const static uint64_t SH_FLD_GZIP_COMP_PREFETCH_ENABLE = 7474; // 1 +const static uint64_t SH_FLD_GZIP_DECOMP_PREFETCH_ENABLE = 7475; // 1 +const static uint64_t SH_FLD_GZIP_FC_SELECT = 7476; // 1 +const static uint64_t SH_FLD_GZIP_FC_SELECT_LEN = 7477; // 1 +const static uint64_t SH_FLD_GZIP_LATENCY_CFG = 7478; // 1 +const static uint64_t SH_FLD_GZIP_MUX_SELECT = 7479; // 1 +const static uint64_t SH_FLD_GZIP_MUX_SELECT_LEN = 7480; // 1 +const static uint64_t SH_FLD_H1AP_CFG = 7481; // 6 +const static uint64_t SH_FLD_H1AP_CFG_LEN = 7482; // 6 +const static uint64_t SH_FLD_HALT_INPUT = 7483; // 13 +const static uint64_t SH_FLD_HALT_ON_TRIG = 7484; // 17 +const static uint64_t SH_FLD_HALT_ON_XSTOP = 7485; // 17 +const static uint64_t SH_FLD_HALT_ROTATION = 7486; // 8 +const static uint64_t SH_FLD_HANG_DATA_SCALE = 7487; // 5 +const static uint64_t SH_FLD_HANG_DATA_SCALE_LEN = 7488; // 5 +const static uint64_t SH_FLD_HANG_ON_ACK_DEAD = 7489; // 1 +const static uint64_t SH_FLD_HANG_ON_ADDR_ERROR = 7490; // 1 +const static uint64_t SH_FLD_HANG_PE_SCALE = 7491; // 3 +const static uint64_t SH_FLD_HANG_PE_SCALE_LEN = 7492; // 3 +const static uint64_t SH_FLD_HANG_PIB_RESET = 7493; // 1 +const static uint64_t SH_FLD_HANG_PLS_MULT = 7494; // 1 +const static uint64_t SH_FLD_HANG_PLS_MULT_LEN = 7495; // 1 +const static uint64_t SH_FLD_HANG_POLL_ENABLE = 7496; // 2 +const static uint64_t SH_FLD_HANG_POLL_PULSE_DIV = 7497; // 24 +const static uint64_t SH_FLD_HANG_POLL_PULSE_DIV_LEN = 7498; // 24 +const static uint64_t SH_FLD_HANG_POLL_SCALE = 7499; // 7 +const static uint64_t SH_FLD_HANG_POLL_SCALE_LEN = 7500; // 7 +const static uint64_t SH_FLD_HANG_RECOVERY_GTE_LEVEL1 = 7501; // 2 +const static uint64_t SH_FLD_HANG_RECOVERY_LIMIT_ERROR = 7502; // 2 +const static uint64_t SH_FLD_HANG_RESET = 7503; // 1 +const static uint64_t SH_FLD_HANG_SHM_SCALE = 7504; // 2 +const static uint64_t SH_FLD_HANG_SHM_SCALE_LEN = 7505; // 2 +const static uint64_t SH_FLD_HANG_SM_ON_ARE = 7506; // 2 +const static uint64_t SH_FLD_HANG_SM_ON_LINK_FAIL = 7507; // 2 +const static uint64_t SH_FLD_HARD_CE_COUNT = 7508; // 2 +const static uint64_t SH_FLD_HARD_CE_COUNT_LEN = 7509; // 2 +const static uint64_t SH_FLD_HARD_MCE_COUNT = 7510; // 2 +const static uint64_t SH_FLD_HARD_MCE_COUNT_LEN = 7511; // 2 +const static uint64_t SH_FLD_HARD_NCE_ETE_ATTN = 7512; // 2 +const static uint64_t SH_FLD_HASH_LPID_DIS = 7513; // 1 +const static uint64_t SH_FLD_HASH_PID_DIS = 7514; // 1 +const static uint64_t SH_FLD_HASH_SIZE_MASK = 7515; // 1 +const static uint64_t SH_FLD_HASH_SIZE_MASK_LEN = 7516; // 1 +const static uint64_t SH_FLD_HA_ILLEGAL_CONSUMER_ACCESS = 7517; // 4 +const static uint64_t SH_FLD_HA_ILLEGAL_PRODUCER_ACCESS = 7518; // 4 +const static uint64_t SH_FLD_HB_ERROR = 7519; // 1 +const static uint64_t SH_FLD_HB_MALF_MASK = 7520; // 1 +const static uint64_t SH_FLD_HDICE = 7521; // 96 +const static uint64_t SH_FLD_HDR_ARR_ECC_CORR_ENA = 7522; // 6 +const static uint64_t SH_FLD_HDR_ARR_ECC_SUE_ENA = 7523; // 6 +const static uint64_t SH_FLD_HI = 7524; // 1 +const static uint64_t SH_FLD_HIGH = 7525; // 1 +const static uint64_t SH_FLD_HIGH_IDLE_COUNT = 7526; // 8 +const static uint64_t SH_FLD_HIGH_IDLE_COUNT_LEN = 7527; // 8 +const static uint64_t SH_FLD_HIGH_IDLE_THRESHOLD = 7528; // 8 +const static uint64_t SH_FLD_HIGH_IDLE_THRESHOLD_LEN = 7529; // 8 +const static uint64_t SH_FLD_HIGH_LEN = 7530; // 1 +const static uint64_t SH_FLD_HILE = 7531; // 24 +const static uint64_t SH_FLD_HIRES_FMAX = 7532; // 6 +const static uint64_t SH_FLD_HIRES_FMAX_LEN = 7533; // 6 +const static uint64_t SH_FLD_HIRES_FMIN = 7534; // 6 +const static uint64_t SH_FLD_HIRES_FMIN_LEN = 7535; // 6 +const static uint64_t SH_FLD_HIRES_FMULT = 7536; // 6 +const static uint64_t SH_FLD_HIRES_FMULT_LEN = 7537; // 6 +const static uint64_t SH_FLD_HIRES_FREQIN_AVG = 7538; // 6 +const static uint64_t SH_FLD_HIRES_FREQIN_AVG_LEN = 7539; // 6 +const static uint64_t SH_FLD_HIRES_FREQIN_MAX = 7540; // 6 +const static uint64_t SH_FLD_HIRES_FREQIN_MAX_LEN = 7541; // 6 +const static uint64_t SH_FLD_HIRES_FREQIN_MIN = 7542; // 6 +const static uint64_t SH_FLD_HIRES_FREQIN_MIN_LEN = 7543; // 6 +const static uint64_t SH_FLD_HIRES_FREQOUT = 7544; // 6 +const static uint64_t SH_FLD_HIRES_FREQOUT_AVG = 7545; // 6 +const static uint64_t SH_FLD_HIRES_FREQOUT_AVG_LEN = 7546; // 6 +const static uint64_t SH_FLD_HIRES_FREQOUT_LEN = 7547; // 6 +const static uint64_t SH_FLD_HIRES_FREQOUT_MAX = 7548; // 6 +const static uint64_t SH_FLD_HIRES_FREQOUT_MAX_LEN = 7549; // 6 +const static uint64_t SH_FLD_HIRES_FREQOUT_MIN = 7550; // 6 +const static uint64_t SH_FLD_HIRES_FREQOUT_MIN_LEN = 7551; // 6 +const static uint64_t SH_FLD_HIST = 7552; // 6 +const static uint64_t SH_FLD_HISTORY_COND2_3_EVENT = 7553; // 43 +const static uint64_t SH_FLD_HISTORY_COND2_TIMEOUT = 7554; // 43 +const static uint64_t SH_FLD_HISTORY_COND4_5_EVENT = 7555; // 43 +const static uint64_t SH_FLD_HISTORY_COND4_TIMEOUT = 7556; // 43 +const static uint64_t SH_FLD_HISTORY_CONDITION0_LT = 7557; // 43 +const static uint64_t SH_FLD_HISTORY_CONDITION1_LT = 7558; // 43 +const static uint64_t SH_FLD_HIST_ADDRESS = 7559; // 1 +const static uint64_t SH_FLD_HIST_ADDRESS_LEN = 7560; // 1 +const static uint64_t SH_FLD_HIST_DONE = 7561; // 1 +const static uint64_t SH_FLD_HIST_FREEZE_HISTORY = 7562; // 1 +const static uint64_t SH_FLD_HIST_LEN = 7563; // 6 +const static uint64_t SH_FLD_HIST_MANUAL_MODE_EN = 7564; // 1 +const static uint64_t SH_FLD_HIST_MASK = 7565; // 1 +const static uint64_t SH_FLD_HIST_MASK_LEN = 7566; // 1 +const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT = 7567; // 6 +const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LANE = 7568; // 6 +const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LANE_LEN = 7569; // 6 +const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_LEN = 7570; // 6 +const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_MODE = 7571; // 6 +const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_MODE_LEN = 7572; // 6 +const static uint64_t SH_FLD_HIST_MIN_EYE_HEIGHT_VALID = 7573; // 6 +const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH = 7574; // 6 +const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LANE = 7575; // 6 +const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LANE_LEN = 7576; // 6 +const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_LEN = 7577; // 6 +const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_MODE = 7578; // 6 +const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_MODE_LEN = 7579; // 6 +const static uint64_t SH_FLD_HIST_MIN_EYE_WIDTH_VALID = 7580; // 6 +const static uint64_t SH_FLD_HIST_RESERVED = 7581; // 1 +const static uint64_t SH_FLD_HIST_RESERVED_LEN = 7582; // 1 +const static uint64_t SH_FLD_HIST_RESET_HISTORY = 7583; // 1 +const static uint64_t SH_FLD_HIST_START_NOT_STOP = 7584; // 1 +const static uint64_t SH_FLD_HIST_STOP_ON_ERROR_GT = 7585; // 1 +const static uint64_t SH_FLD_HIST_STOP_ON_ERROR_GT_LEN = 7586; // 1 +const static uint64_t SH_FLD_HIST_TRACE_TRAFFIC = 7587; // 1 +const static uint64_t SH_FLD_HI_ENABLE = 7588; // 2 +const static uint64_t SH_FLD_HI_FIXED_WINDOW_MODE = 7589; // 2 +const static uint64_t SH_FLD_HI_PRESCALE_MODE = 7590; // 2 +const static uint64_t SH_FLD_HI_SELECT = 7591; // 2 +const static uint64_t SH_FLD_HI_SELECT_LEN = 7592; // 2 +const static uint64_t SH_FLD_HMI_ACTIVE = 7593; // 1 +const static uint64_t SH_FLD_HMI_EXIT_ENABLE = 7594; // 96 +const static uint64_t SH_FLD_HMI_REQUEST_C0 = 7595; // 12 +const static uint64_t SH_FLD_HMI_REQUEST_C1 = 7596; // 12 +const static uint64_t SH_FLD_HOLD = 7597; // 2 +const static uint64_t SH_FLD_HOLD_0 = 7598; // 8 +const static uint64_t SH_FLD_HOLD_0_48 = 7599; // 1 +const static uint64_t SH_FLD_HOLD_0_48_LEN = 7600; // 1 +const static uint64_t SH_FLD_HOLD_1 = 7601; // 8 +const static uint64_t SH_FLD_HOLD_ADDRESS = 7602; // 90 +const static uint64_t SH_FLD_HOLD_ADDRESS_LEN = 7603; // 90 +const static uint64_t SH_FLD_HOLD_DBGTRIG_SEL = 7604; // 43 +const static uint64_t SH_FLD_HOLD_DBGTRIG_SEL_LEN = 7605; // 43 +const static uint64_t SH_FLD_HOLD_LEN = 7606; // 2 +const static uint64_t SH_FLD_HOLD_SAMPLE = 7607; // 43 +const static uint64_t SH_FLD_HOLD_SAMPLE_WITH_TRIGGER = 7608; // 43 +const static uint64_t SH_FLD_HOLE0_LOWER_ADDRESS = 7609; // 8 +const static uint64_t SH_FLD_HOLE0_LOWER_ADDRESS_LEN = 7610; // 8 +const static uint64_t SH_FLD_HOLE0_UPPER_ADDRESS = 7611; // 8 +const static uint64_t SH_FLD_HOLE0_UPPER_ADDRESS_LEN = 7612; // 8 +const static uint64_t SH_FLD_HOLE0_VALID = 7613; // 8 +const static uint64_t SH_FLD_HOLE1_LOWER_ADDRESS = 7614; // 8 +const static uint64_t SH_FLD_HOLE1_LOWER_ADDRESS_LEN = 7615; // 8 +const static uint64_t SH_FLD_HOLE1_UPPER_ADDRESS = 7616; // 8 +const static uint64_t SH_FLD_HOLE1_UPPER_ADDRESS_LEN = 7617; // 8 +const static uint64_t SH_FLD_HOLE1_VALID = 7618; // 8 +const static uint64_t SH_FLD_HRMOR = 7619; // 1 +const static uint64_t SH_FLD_HRMOR_LEN = 7620; // 1 +const static uint64_t SH_FLD_HSSCALERR = 7621; // 6 +const static uint64_t SH_FLD_HSSPLLAERR = 7622; // 6 +const static uint64_t SH_FLD_HSSPLLBERR = 7623; // 6 +const static uint64_t SH_FLD_HSSPLLCAL = 7624; // 3 +const static uint64_t SH_FLD_HSSPLLFASTCAL = 7625; // 6 +const static uint64_t SH_FLD_HSSRECAL = 7626; // 6 +const static uint64_t SH_FLD_HSSRESYNC = 7627; // 6 +const static uint64_t SH_FLD_HTB_EXTEST = 7628; // 43 +const static uint64_t SH_FLD_HTB_INTEST = 7629; // 43 +const static uint64_t SH_FLD_HTMCO_STATUS_ADDR_ERROR = 7630; // 26 +const static uint64_t SH_FLD_HTMCO_STATUS_BUF_WAIT = 7631; // 26 +const static uint64_t SH_FLD_HTMCO_STATUS_COMPLETE = 7632; // 26 +const static uint64_t SH_FLD_HTMCO_STATUS_CRESP_OV = 7633; // 26 +const static uint64_t SH_FLD_HTMCO_STATUS_ENABLE = 7634; // 26 +const static uint64_t SH_FLD_HTMCO_STATUS_FLUSH = 7635; // 26 +const static uint64_t SH_FLD_HTMCO_STATUS_INIT = 7636; // 26 +const static uint64_t SH_FLD_HTMCO_STATUS_PAUSED = 7637; // 26 +const static uint64_t SH_FLD_HTMCO_STATUS_PREREQ = 7638; // 26 +const static uint64_t SH_FLD_HTMCO_STATUS_PURGE_DONE = 7639; // 24 +const static uint64_t SH_FLD_HTMCO_STATUS_PURGE_IN_PROG = 7640; // 24 +const static uint64_t SH_FLD_HTMCO_STATUS_READY = 7641; // 26 +const static uint64_t SH_FLD_HTMCO_STATUS_REPAIR = 7642; // 26 +const static uint64_t SH_FLD_HTMCO_STATUS_SPARE = 7643; // 2 +const static uint64_t SH_FLD_HTMCO_STATUS_SPARE_LEN = 7644; // 2 +const static uint64_t SH_FLD_HTMCO_STATUS_STAMP = 7645; // 26 +const static uint64_t SH_FLD_HTMCO_STATUS_TRACING = 7646; // 26 +const static uint64_t SH_FLD_HTMSC = 7647; // 24 +const static uint64_t SH_FLD_HTMSC_ALLOC = 7648; // 26 +const static uint64_t SH_FLD_HTMSC_BASE = 7649; // 26 +const static uint64_t SH_FLD_HTMSC_BASE_LEN = 7650; // 26 +const static uint64_t SH_FLD_HTMSC_CAPTURE = 7651; // 26 +const static uint64_t SH_FLD_HTMSC_CAPTURE_LEN = 7652; // 26 +const static uint64_t SH_FLD_HTMSC_CHIP0_STOP = 7653; // 24 +const static uint64_t SH_FLD_HTMSC_CHIP1_STOP = 7654; // 24 +const static uint64_t SH_FLD_HTMSC_CONTENT_SEL = 7655; // 26 +const static uint64_t SH_FLD_HTMSC_CONTENT_SEL_LEN = 7656; // 26 +const static uint64_t SH_FLD_HTMSC_COUNT = 7657; // 24 +const static uint64_t SH_FLD_HTMSC_COUNT_LEN = 7658; // 24 +const static uint64_t SH_FLD_HTMSC_CRESPFILT_INVERT = 7659; // 2 +const static uint64_t SH_FLD_HTMSC_CRESP_MASK = 7660; // 2 +const static uint64_t SH_FLD_HTMSC_CRESP_MASK_LEN = 7661; // 2 +const static uint64_t SH_FLD_HTMSC_CRESP_PAT = 7662; // 2 +const static uint64_t SH_FLD_HTMSC_CRESP_PAT_LEN = 7663; // 2 +const static uint64_t SH_FLD_HTMSC_DBG0_STOP = 7664; // 26 +const static uint64_t SH_FLD_HTMSC_DBG1_STOP = 7665; // 26 +const static uint64_t SH_FLD_HTMSC_DD1EQUIV = 7666; // 24 +const static uint64_t SH_FLD_HTMSC_DIS_DRP_PRIORITY_INCR = 7667; // 2 +const static uint64_t SH_FLD_HTMSC_DIS_FORCE_GROUP_SCOPE = 7668; // 2 +const static uint64_t SH_FLD_HTMSC_DIS_GROUP = 7669; // 24 +const static uint64_t SH_FLD_HTMSC_DIS_OPER_HANG = 7670; // 2 +const static uint64_t SH_FLD_HTMSC_DIS_RETRY_BACKOFF = 7671; // 2 +const static uint64_t SH_FLD_HTMSC_DIS_STALL = 7672; // 24 +const static uint64_t SH_FLD_HTMSC_DIS_TSTAMP = 7673; // 26 +const static uint64_t SH_FLD_HTMSC_ENABLE = 7674; // 26 +const static uint64_t SH_FLD_HTMSC_ENABLE_SPLIT_CORE = 7675; // 24 +const static uint64_t SH_FLD_HTMSC_ERROR = 7676; // 24 +const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL0 = 7677; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL0_LEN = 7678; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL1 = 7679; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL1_LEN = 7680; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL2 = 7681; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_CGRPSEL2_LEN = 7682; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL0 = 7683; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL0_LEN = 7684; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL1 = 7685; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL1_LEN = 7686; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL2 = 7687; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL2_LEN = 7688; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL3 = 7689; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL3_LEN = 7690; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL4 = 7691; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL4_LEN = 7692; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL5 = 7693; // 2 +const static uint64_t SH_FLD_HTMSC_FMUX_RGRPSEL5_LEN = 7694; // 2 +const static uint64_t SH_FLD_HTMSC_FSM = 7695; // 24 +const static uint64_t SH_FLD_HTMSC_FSM_LEN = 7696; // 24 +const static uint64_t SH_FLD_HTMSC_INVERT = 7697; // 2 +const static uint64_t SH_FLD_HTMSC_LEN = 7698; // 24 +const static uint64_t SH_FLD_HTMSC_MARK = 7699; // 26 +const static uint64_t SH_FLD_HTMSC_MARKERS_ONLY = 7700; // 26 +const static uint64_t SH_FLD_HTMSC_MARK_LEN = 7701; // 26 +const static uint64_t SH_FLD_HTMSC_MARK_TYPE = 7702; // 26 +const static uint64_t SH_FLD_HTMSC_MARK_TYPE_LEN = 7703; // 26 +const static uint64_t SH_FLD_HTMSC_MARK_VALID = 7704; // 26 +const static uint64_t SH_FLD_HTMSC_MASK = 7705; // 4 +const static uint64_t SH_FLD_HTMSC_MASK_LEN = 7706; // 4 +const static uint64_t SH_FLD_HTMSC_MTSPR_MARK = 7707; // 24 +const static uint64_t SH_FLD_HTMSC_MTSPR_TRIG = 7708; // 24 +const static uint64_t SH_FLD_HTMSC_OPER_HANG_DIV_RATIO = 7709; // 2 +const static uint64_t SH_FLD_HTMSC_OPER_HANG_DIV_RATIO_LEN = 7710; // 2 +const static uint64_t SH_FLD_HTMSC_OTHER_DBG0_STOP = 7711; // 2 +const static uint64_t SH_FLD_HTMSC_PAT = 7712; // 4 +const static uint64_t SH_FLD_HTMSC_PAT_LEN = 7713; // 4 +const static uint64_t SH_FLD_HTMSC_PAUSE = 7714; // 26 +const static uint64_t SH_FLD_HTMSC_PDBAR_ERROR = 7715; // 24 +const static uint64_t SH_FLD_HTMSC_PRIORITY = 7716; // 26 +const static uint64_t SH_FLD_HTMSC_RESERVED = 7717; // 24 +const static uint64_t SH_FLD_HTMSC_RESERVED_LEN = 7718; // 24 +const static uint64_t SH_FLD_HTMSC_RESET = 7719; // 26 +const static uint64_t SH_FLD_HTMSC_RTY_DRP_COUNT = 7720; // 2 +const static uint64_t SH_FLD_HTMSC_RTY_DRP_COUNT_LEN = 7721; // 2 +const static uint64_t SH_FLD_HTMSC_RUN_STOP = 7722; // 26 +const static uint64_t SH_FLD_HTMSC_SCOPE = 7723; // 50 +const static uint64_t SH_FLD_HTMSC_SCOPE_LEN = 7724; // 50 +const static uint64_t SH_FLD_HTMSC_SINGLE_TSTAMP = 7725; // 26 +const static uint64_t SH_FLD_HTMSC_SIZE = 7726; // 26 +const static uint64_t SH_FLD_HTMSC_SIZE_LEN = 7727; // 26 +const static uint64_t SH_FLD_HTMSC_SIZE_SMALL = 7728; // 26 +const static uint64_t SH_FLD_HTMSC_SPARE = 7729; // 24 +const static uint64_t SH_FLD_HTMSC_SPARE0 = 7730; // 24 +const static uint64_t SH_FLD_HTMSC_SPARE1012 = 7731; // 2 +const static uint64_t SH_FLD_HTMSC_SPARE1012_LEN = 7732; // 2 +const static uint64_t SH_FLD_HTMSC_SPARE1112 = 7733; // 24 +const static uint64_t SH_FLD_HTMSC_SPARE1112_LEN = 7734; // 24 +const static uint64_t SH_FLD_HTMSC_SPARE1415 = 7735; // 26 +const static uint64_t SH_FLD_HTMSC_SPARE1415_LEN = 7736; // 26 +const static uint64_t SH_FLD_HTMSC_SPARE16 = 7737; // 2 +const static uint64_t SH_FLD_HTMSC_SPARE23 = 7738; // 2 +const static uint64_t SH_FLD_HTMSC_SPARE2TO4 = 7739; // 24 +const static uint64_t SH_FLD_HTMSC_SPARE2TO4_LEN = 7740; // 24 +const static uint64_t SH_FLD_HTMSC_SPARE3 = 7741; // 2 +const static uint64_t SH_FLD_HTMSC_SPARE4043 = 7742; // 2 +const static uint64_t SH_FLD_HTMSC_SPARE4043_LEN = 7743; // 2 +const static uint64_t SH_FLD_HTMSC_SPARE67 = 7744; // 2 +const static uint64_t SH_FLD_HTMSC_SPARE67_LEN = 7745; // 2 +const static uint64_t SH_FLD_HTMSC_SPARES = 7746; // 24 +const static uint64_t SH_FLD_HTMSC_SPARES_LEN = 7747; // 24 +const static uint64_t SH_FLD_HTMSC_SPARE_1TO2 = 7748; // 24 +const static uint64_t SH_FLD_HTMSC_SPARE_1TO2_LEN = 7749; // 24 +const static uint64_t SH_FLD_HTMSC_SPARE_LEN = 7750; // 24 +const static uint64_t SH_FLD_HTMSC_START = 7751; // 26 +const static uint64_t SH_FLD_HTMSC_STOP = 7752; // 26 +const static uint64_t SH_FLD_HTMSC_STOP_ALT = 7753; // 26 +const static uint64_t SH_FLD_HTMSC_SYNC_STAMP_FORCE = 7754; // 2 +const static uint64_t SH_FLD_HTMSC_SYNC_STAMP_FORCE_LEN = 7755; // 2 +const static uint64_t SH_FLD_HTMSC_TRACE_ACTIVE = 7756; // 24 +const static uint64_t SH_FLD_HTMSC_TRIG = 7757; // 26 +const static uint64_t SH_FLD_HTMSC_TRIG_LEN = 7758; // 26 +const static uint64_t SH_FLD_HTMSC_TSIZEFILT_MASK = 7759; // 2 +const static uint64_t SH_FLD_HTMSC_TSIZEFILT_MASK_LEN = 7760; // 2 +const static uint64_t SH_FLD_HTMSC_TSIZEFILT_PAT = 7761; // 2 +const static uint64_t SH_FLD_HTMSC_TSIZEFILT_PAT_LEN = 7762; // 2 +const static uint64_t SH_FLD_HTMSC_VGTARGET = 7763; // 26 +const static uint64_t SH_FLD_HTMSC_VGTARGET_LEN = 7764; // 26 +const static uint64_t SH_FLD_HTMSC_WRAP = 7765; // 26 +const static uint64_t SH_FLD_HTMSC_WRITETOIO = 7766; // 2 +const static uint64_t SH_FLD_HTMSC_XSTOP_STOP = 7767; // 26 +const static uint64_t SH_FLD_HTM_CMD_OVERRUN = 7768; // 1 +const static uint64_t SH_FLD_HTM_GPE_SRC_SEL = 7769; // 1 +const static uint64_t SH_FLD_HTM_GPE_SRC_SEL_LEN = 7770; // 1 +const static uint64_t SH_FLD_HTM_MARKER_SLAVE_ADRS = 7771; // 1 +const static uint64_t SH_FLD_HTM_MARKER_SLAVE_ADRS_LEN = 7772; // 1 +const static uint64_t SH_FLD_HTM_QUEUE_LIMIT = 7773; // 12 +const static uint64_t SH_FLD_HTM_QUEUE_LIMIT_LEN = 7774; // 12 +const static uint64_t SH_FLD_HTM_SRC_SEL = 7775; // 1 +const static uint64_t SH_FLD_HTM_SRC_SEL_LEN = 7776; // 1 +const static uint64_t SH_FLD_HTM_STOP = 7777; // 1 +const static uint64_t SH_FLD_HTM_TRACE_MODE = 7778; // 1 +const static uint64_t SH_FLD_HUC = 7779; // 1 +const static uint64_t SH_FLD_HUC_LEN = 7780; // 1 +const static uint64_t SH_FLD_HUT = 7781; // 1 +const static uint64_t SH_FLD_HUT_LEN = 7782; // 1 +const static uint64_t SH_FLD_HWCTRL = 7783; // 2 +const static uint64_t SH_FLD_HWCTRL_CLOCK_DIVIDER = 7784; // 1 +const static uint64_t SH_FLD_HWCTRL_CLOCK_DIVIDER_LEN = 7785; // 1 +const static uint64_t SH_FLD_HWCTRL_CPHA = 7786; // 1 +const static uint64_t SH_FLD_HWCTRL_CPOL = 7787; // 1 +const static uint64_t SH_FLD_HWCTRL_DEVICE = 7788; // 1 +const static uint64_t SH_FLD_HWCTRL_FRAME_SIZE = 7789; // 1 +const static uint64_t SH_FLD_HWCTRL_FRAME_SIZE_LEN = 7790; // 1 +const static uint64_t SH_FLD_HWCTRL_FSM_ENABLE = 7791; // 1 +const static uint64_t SH_FLD_HWCTRL_FSM_ERR = 7792; // 1 +const static uint64_t SH_FLD_HWCTRL_INTER_FRAME_DELAY = 7793; // 1 +const static uint64_t SH_FLD_HWCTRL_INTER_FRAME_DELAY_LEN = 7794; // 1 +const static uint64_t SH_FLD_HWCTRL_INVALID_NUMBER_OF_FRAMES = 7795; // 1 +const static uint64_t SH_FLD_HWCTRL_IN_COUNT = 7796; // 1 +const static uint64_t SH_FLD_HWCTRL_IN_COUNT_LEN = 7797; // 1 +const static uint64_t SH_FLD_HWCTRL_IN_DELAY = 7798; // 1 +const static uint64_t SH_FLD_HWCTRL_IN_DELAY_LEN = 7799; // 1 +const static uint64_t SH_FLD_HWCTRL_LEN = 7800; // 2 +const static uint64_t SH_FLD_HWCTRL_NR_OF_FRAMES = 7801; // 1 +const static uint64_t SH_FLD_HWCTRL_NR_OF_FRAMES_LEN = 7802; // 1 +const static uint64_t SH_FLD_HWCTRL_ONGOING = 7803; // 1 +const static uint64_t SH_FLD_HWCTRL_OUT_COUNT = 7804; // 1 +const static uint64_t SH_FLD_HWCTRL_OUT_COUNT_LEN = 7805; // 1 +const static uint64_t SH_FLD_HWCTRL_RDATA0 = 7806; // 1 +const static uint64_t SH_FLD_HWCTRL_RDATA0_LEN = 7807; // 1 +const static uint64_t SH_FLD_HWCTRL_RDATA1 = 7808; // 1 +const static uint64_t SH_FLD_HWCTRL_RDATA1_LEN = 7809; // 1 +const static uint64_t SH_FLD_HWCTRL_RDATA2 = 7810; // 1 +const static uint64_t SH_FLD_HWCTRL_RDATA2_LEN = 7811; // 1 +const static uint64_t SH_FLD_HWCTRL_RDATA3 = 7812; // 1 +const static uint64_t SH_FLD_HWCTRL_RDATA3_LEN = 7813; // 1 +const static uint64_t SH_FLD_HWCTRL_START_SAMPLING = 7814; // 1 +const static uint64_t SH_FLD_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 7815; // 1 +const static uint64_t SH_FLD_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR = 7816; // 1 +const static uint64_t SH_FLD_HWD = 7817; // 1 +const static uint64_t SH_FLD_HWD_0 = 7818; // 1 +const static uint64_t SH_FLD_HWD_0_LEN = 7819; // 1 +const static uint64_t SH_FLD_HWD_10 = 7820; // 1 +const static uint64_t SH_FLD_HWD_10_LEN = 7821; // 1 +const static uint64_t SH_FLD_HWD_11 = 7822; // 1 +const static uint64_t SH_FLD_HWD_11_LEN = 7823; // 1 +const static uint64_t SH_FLD_HWD_12 = 7824; // 1 +const static uint64_t SH_FLD_HWD_12_LEN = 7825; // 1 +const static uint64_t SH_FLD_HWD_13 = 7826; // 1 +const static uint64_t SH_FLD_HWD_13_LEN = 7827; // 1 +const static uint64_t SH_FLD_HWD_14 = 7828; // 1 +const static uint64_t SH_FLD_HWD_14_LEN = 7829; // 1 +const static uint64_t SH_FLD_HWD_15 = 7830; // 1 +const static uint64_t SH_FLD_HWD_15_LEN = 7831; // 1 +const static uint64_t SH_FLD_HWD_2 = 7832; // 1 +const static uint64_t SH_FLD_HWD_2_LEN = 7833; // 1 +const static uint64_t SH_FLD_HWD_3 = 7834; // 1 +const static uint64_t SH_FLD_HWD_3_LEN = 7835; // 1 +const static uint64_t SH_FLD_HWD_4 = 7836; // 1 +const static uint64_t SH_FLD_HWD_4_LEN = 7837; // 1 +const static uint64_t SH_FLD_HWD_5 = 7838; // 1 +const static uint64_t SH_FLD_HWD_5_LEN = 7839; // 1 +const static uint64_t SH_FLD_HWD_6 = 7840; // 1 +const static uint64_t SH_FLD_HWD_6_LEN = 7841; // 1 +const static uint64_t SH_FLD_HWD_7 = 7842; // 1 +const static uint64_t SH_FLD_HWD_7_LEN = 7843; // 1 +const static uint64_t SH_FLD_HWD_8 = 7844; // 1 +const static uint64_t SH_FLD_HWD_8_LEN = 7845; // 1 +const static uint64_t SH_FLD_HWD_9 = 7846; // 1 +const static uint64_t SH_FLD_HWD_9_LEN = 7847; // 1 +const static uint64_t SH_FLD_HWD_LEN = 7848; // 1 +const static uint64_t SH_FLD_HWD_PRIORITY = 7849; // 1 +const static uint64_t SH_FLD_HWD_PRIORITY_LEN = 7850; // 1 +const static uint64_t SH_FLD_HWD_RSD = 7851; // 1 +const static uint64_t SH_FLD_HWD_RSD_LEN = 7852; // 1 +const static uint64_t SH_FLD_HWMSX_PE = 7853; // 8 +const static uint64_t SH_FLD_HWMSX_PE_LEN = 7854; // 8 +const static uint64_t SH_FLD_HW_CONTROL_ERROR = 7855; // 12 +const static uint64_t SH_FLD_HW_DIR_INTIATED_LINE_DELETE_OCCURRED = 7856; // 12 +const static uint64_t SH_FLD_HW_ERRORS = 7857; // 9 +const static uint64_t SH_FLD_HW_ERRORS_MASK = 7858; // 9 +const static uint64_t SH_FLD_HW_PARITY_ERROR = 7859; // 2 +const static uint64_t SH_FLD_HYPERVISOR = 7860; // 4 +const static uint64_t SH_FLD_HYP_BLOCK = 7861; // 24 +const static uint64_t SH_FLD_HYP_BLOCK_LEN = 7862; // 24 +const static uint64_t SH_FLD_HYP_RECOURCE_ERR = 7863; // 96 +const static uint64_t SH_FLD_HYP_SPECIAL_WKUP = 7864; // 30 +const static uint64_t SH_FLD_HYP_VIRT_EXIT_ENABLE = 7865; // 96 +const static uint64_t SH_FLD_I2CM_ECC_ERRORS = 7866; // 1 +const static uint64_t SH_FLD_I2CM_ECC_ERRORS_LEN = 7867; // 1 +const static uint64_t SH_FLD_I2CM_I2C_ERRORS = 7868; // 1 +const static uint64_t SH_FLD_I2CM_I2C_ERRORS_LEN = 7869; // 1 +const static uint64_t SH_FLD_I2CM_INTER = 7870; // 1 +const static uint64_t SH_FLD_I2CM_INTR_STATUS = 7871; // 1 +const static uint64_t SH_FLD_I2CM_INTR_STATUS_LEN = 7872; // 1 +const static uint64_t SH_FLD_I2CM_PIB_ERRORS = 7873; // 1 +const static uint64_t SH_FLD_I2CM_PIB_ERRORS_LEN = 7874; // 1 +const static uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_0 = 7875; // 1 +const static uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_0_LEN = 7876; // 1 +const static uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_1 = 7877; // 1 +const static uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_1_LEN = 7878; // 1 +const static uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_2 = 7879; // 1 +const static uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_2_LEN = 7880; // 1 +const static uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_3 = 7881; // 1 +const static uint64_t SH_FLD_I2CM_STEERED_INTERRUPTS_3_LEN = 7882; // 1 +const static uint64_t SH_FLD_I2C_BUS_HELD_MODE_ENABLE = 7883; // 1 +const static uint64_t SH_FLD_I2C_EXTENDER = 7884; // 1 +const static uint64_t SH_FLD_I2C_SPEED_MUX = 7885; // 1 +const static uint64_t SH_FLD_I2C_SPEED_MUX_LEN = 7886; // 1 +const static uint64_t SH_FLD_I2C_TIMEOUT_VALUE = 7887; // 1 +const static uint64_t SH_FLD_I2C_TIMEOUT_VALUE_LEN = 7888; // 1 +const static uint64_t SH_FLD_IBUF_ABANK = 7889; // 3 +const static uint64_t SH_FLD_IBUF_ABANK_LEN = 7890; // 3 +const static uint64_t SH_FLD_IBUF_AIDX = 7891; // 3 +const static uint64_t SH_FLD_IBUF_AIDX_LEN = 7892; // 3 +const static uint64_t SH_FLD_IBUF_RSRC = 7893; // 3 +const static uint64_t SH_FLD_IBUF_RSRC_LEN = 7894; // 3 +const static uint64_t SH_FLD_IBUF_WSRC = 7895; // 3 +const static uint64_t SH_FLD_IBUF_WSRC_LEN = 7896; // 3 +const static uint64_t SH_FLD_IBWR_MASK = 7897; // 3 +const static uint64_t SH_FLD_IBWR_MASK_LEN = 7898; // 3 +const static uint64_t SH_FLD_ICACHE_ERR = 7899; // 21 +const static uint64_t SH_FLD_ICACHE_TAG_ADDR = 7900; // 21 +const static uint64_t SH_FLD_ICACHE_TAG_ADDR_LEN = 7901; // 21 +const static uint64_t SH_FLD_ICACHE_VALID = 7902; // 21 +const static uint64_t SH_FLD_ICACHE_VALID_LEN = 7903; // 21 +const static uint64_t SH_FLD_ICE_COUNT = 7904; // 2 +const static uint64_t SH_FLD_ICE_COUNT_LEN = 7905; // 2 +const static uint64_t SH_FLD_ICE_ETE_ATTN = 7906; // 2 +const static uint64_t SH_FLD_ICS_INVALID_STATE = 7907; // 1 +const static uint64_t SH_FLD_ICU_RNW = 7908; // 1 +const static uint64_t SH_FLD_ICU_TIMEOUT_ERROR = 7909; // 1 +const static uint64_t SH_FLD_ID = 7910; // 131 +const static uint64_t SH_FLD_IDIAL = 7911; // 34 +const static uint64_t SH_FLD_IDIAL_AMO_ADDR = 7912; // 3 +const static uint64_t SH_FLD_IDIAL_ATS = 7913; // 1 +const static uint64_t SH_FLD_IDIAL_ATS_ESR_MSK = 7914; // 1 +const static uint64_t SH_FLD_IDIAL_ATS_ESR_MSK_LEN = 7915; // 1 +const static uint64_t SH_FLD_IDIAL_ATS_FER_MSK = 7916; // 1 +const static uint64_t SH_FLD_IDIAL_ATS_FER_MSK_LEN = 7917; // 1 +const static uint64_t SH_FLD_IDIAL_ATS_LEN = 7918; // 1 +const static uint64_t SH_FLD_IDIAL_BBRD = 7919; // 3 +const static uint64_t SH_FLD_IDIAL_BBRD_LEN = 7920; // 3 +const static uint64_t SH_FLD_IDIAL_BBUF_RDWR = 7921; // 3 +const static uint64_t SH_FLD_IDIAL_BR_CE = 7922; // 3 +const static uint64_t SH_FLD_IDIAL_BR_CE_LEN = 7923; // 3 +const static uint64_t SH_FLD_IDIAL_BR_SUE = 7924; // 3 +const static uint64_t SH_FLD_IDIAL_BR_SUE_LEN = 7925; // 3 +const static uint64_t SH_FLD_IDIAL_BR_UE = 7926; // 3 +const static uint64_t SH_FLD_IDIAL_BR_UE_LEN = 7927; // 3 +const static uint64_t SH_FLD_IDIAL_CNTL_ERRP = 7928; // 1 +const static uint64_t SH_FLD_IDIAL_CONFIG1 = 7929; // 3 +const static uint64_t SH_FLD_IDIAL_COUNT0 = 7930; // 9 +const static uint64_t SH_FLD_IDIAL_COUNT0_LEN = 7931; // 9 +const static uint64_t SH_FLD_IDIAL_COUNT1 = 7932; // 9 +const static uint64_t SH_FLD_IDIAL_COUNT1_LEN = 7933; // 9 +const static uint64_t SH_FLD_IDIAL_COUNT2 = 7934; // 9 +const static uint64_t SH_FLD_IDIAL_COUNT2_LEN = 7935; // 9 +const static uint64_t SH_FLD_IDIAL_COUNT3 = 7936; // 9 +const static uint64_t SH_FLD_IDIAL_COUNT3_LEN = 7937; // 9 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_0 = 7938; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_1 = 7939; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_2 = 7940; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_3 = 7941; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_4 = 7942; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_5 = 7943; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_6 = 7944; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_ASBE_7 = 7945; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_0 = 7946; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_1 = 7947; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_2 = 7948; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_3 = 7949; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_4 = 7950; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_5 = 7951; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_6 = 7952; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_AUE_7 = 7953; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_0 = 7954; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_1 = 7955; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_2 = 7956; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_DUE_3 = 7957; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_0 = 7958; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_1 = 7959; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_2 = 7960; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_3 = 7961; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_4 = 7962; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_5 = 7963; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_6 = 7964; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_FWD_7 = 7965; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_0 = 7966; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_1 = 7967; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_2 = 7968; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_3 = 7969; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_4 = 7970; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_5 = 7971; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_6 = 7972; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NCF_7 = 7973; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_0 = 7974; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_1 = 7975; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_10 = 7976; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_11 = 7977; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_12 = 7978; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_13 = 7979; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_14 = 7980; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_15 = 7981; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_2 = 7982; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_3 = 7983; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_4 = 7984; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_5 = 7985; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_6 = 7986; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_7 = 7987; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_8 = 7988; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NLG_9 = 7989; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_0 = 7990; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_1 = 7991; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_10 = 7992; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_11 = 7993; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_12 = 7994; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_13 = 7995; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_14 = 7996; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_15 = 7997; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_16 = 7998; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_17 = 7999; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_18 = 8000; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_19 = 8001; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_2 = 8002; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_20 = 8003; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_21 = 8004; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_22 = 8005; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_23 = 8006; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_3 = 8007; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_4 = 8008; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_5 = 8009; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_6 = 8010; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_7 = 8011; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_8 = 8012; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_NVF_9 = 8013; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_0 = 8014; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_1 = 8015; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_2 = 8016; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_3 = 8017; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_4 = 8018; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_5 = 8019; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_6 = 8020; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBC_7 = 8021; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_0 = 8022; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_1 = 8023; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_2 = 8024; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_3 = 8025; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_4 = 8026; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_5 = 8027; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_6 = 8028; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBF_7 = 8029; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_0 = 8030; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_1 = 8031; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_2 = 8032; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_3 = 8033; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_4 = 8034; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_5 = 8035; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_6 = 8036; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBP_7 = 8037; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_0 = 8038; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_1 = 8039; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_2 = 8040; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_3 = 8041; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_4 = 8042; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_5 = 8043; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_6 = 8044; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PBR_7 = 8045; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_0 = 8046; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_1 = 8047; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_2 = 8048; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_PEF_3 = 8049; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_0 = 8050; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_1 = 8051; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_2 = 8052; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_REG_3 = 8053; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_0 = 8054; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_1 = 8055; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_2 = 8056; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV1_3 = 8057; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_0 = 8058; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_1 = 8059; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_2 = 8060; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV2_3 = 8061; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_0 = 8062; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_1 = 8063; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_2 = 8064; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_FIRST_RSV3_3 = 8065; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_0 = 8066; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_1 = 8067; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_2 = 8068; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_3 = 8069; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_4 = 8070; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_5 = 8071; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_6 = 8072; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_ASBE_7 = 8073; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_0 = 8074; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_1 = 8075; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_2 = 8076; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_3 = 8077; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_4 = 8078; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_5 = 8079; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_6 = 8080; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_AUE_7 = 8081; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_0 = 8082; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_1 = 8083; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_2 = 8084; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_DUE_3 = 8085; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_0 = 8086; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_1 = 8087; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_2 = 8088; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_3 = 8089; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_4 = 8090; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_5 = 8091; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_6 = 8092; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_FWD_7 = 8093; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_0 = 8094; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_1 = 8095; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_2 = 8096; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_3 = 8097; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_4 = 8098; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_5 = 8099; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_6 = 8100; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NCF_7 = 8101; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_0 = 8102; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_1 = 8103; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_10 = 8104; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_11 = 8105; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_12 = 8106; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_13 = 8107; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_14 = 8108; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_15 = 8109; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_2 = 8110; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_3 = 8111; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_4 = 8112; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_5 = 8113; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_6 = 8114; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_7 = 8115; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_8 = 8116; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NLG_9 = 8117; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_0 = 8118; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_1 = 8119; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_10 = 8120; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_11 = 8121; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_12 = 8122; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_13 = 8123; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_14 = 8124; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_15 = 8125; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_16 = 8126; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_17 = 8127; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_18 = 8128; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_19 = 8129; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_2 = 8130; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_20 = 8131; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_21 = 8132; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_22 = 8133; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_23 = 8134; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_3 = 8135; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_4 = 8136; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_5 = 8137; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_6 = 8138; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_7 = 8139; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_8 = 8140; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_NVF_9 = 8141; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_0 = 8142; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_1 = 8143; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_2 = 8144; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_3 = 8145; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_4 = 8146; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_5 = 8147; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_6 = 8148; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBC_7 = 8149; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_0 = 8150; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_1 = 8151; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_2 = 8152; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_3 = 8153; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_4 = 8154; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_5 = 8155; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_6 = 8156; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBF_7 = 8157; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_0 = 8158; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_1 = 8159; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_2 = 8160; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_3 = 8161; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_4 = 8162; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_5 = 8163; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_6 = 8164; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBP_7 = 8165; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_0 = 8166; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_1 = 8167; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_2 = 8168; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_3 = 8169; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_4 = 8170; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_5 = 8171; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_6 = 8172; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PBR_7 = 8173; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_0 = 8174; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_1 = 8175; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_2 = 8176; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_PEF_3 = 8177; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_0 = 8178; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_1 = 8179; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_2 = 8180; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_REG_3 = 8181; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_0 = 8182; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_1 = 8183; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_2 = 8184; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV1_3 = 8185; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_0 = 8186; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_1 = 8187; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_2 = 8188; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV2_3 = 8189; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_0 = 8190; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_1 = 8191; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_2 = 8192; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_HOLD_RSV3_3 = 8193; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_0 = 8194; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_1 = 8195; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_2 = 8196; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_3 = 8197; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_4 = 8198; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_5 = 8199; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_6 = 8200; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_ASBE_7 = 8201; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_0 = 8202; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_1 = 8203; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_2 = 8204; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_3 = 8205; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_4 = 8206; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_5 = 8207; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_6 = 8208; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_AUE_7 = 8209; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_0 = 8210; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_1 = 8211; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_2 = 8212; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_DUE_3 = 8213; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_0 = 8214; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_1 = 8215; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_2 = 8216; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_3 = 8217; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_4 = 8218; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_5 = 8219; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_6 = 8220; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_FWD_7 = 8221; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_0 = 8222; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_1 = 8223; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_2 = 8224; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_3 = 8225; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_4 = 8226; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_5 = 8227; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_6 = 8228; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NCF_7 = 8229; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_0 = 8230; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_1 = 8231; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_10 = 8232; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_11 = 8233; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_12 = 8234; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_13 = 8235; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_14 = 8236; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_15 = 8237; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_2 = 8238; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_3 = 8239; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_4 = 8240; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_5 = 8241; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_6 = 8242; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_7 = 8243; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_8 = 8244; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NLG_9 = 8245; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_0 = 8246; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_1 = 8247; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_10 = 8248; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_11 = 8249; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_12 = 8250; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_13 = 8251; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_14 = 8252; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_15 = 8253; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_16 = 8254; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_17 = 8255; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_18 = 8256; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_19 = 8257; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_2 = 8258; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_20 = 8259; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_21 = 8260; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_22 = 8261; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_23 = 8262; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_3 = 8263; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_4 = 8264; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_5 = 8265; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_6 = 8266; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_7 = 8267; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_8 = 8268; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_NVF_9 = 8269; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_0 = 8270; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_1 = 8271; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_2 = 8272; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_3 = 8273; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_4 = 8274; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_5 = 8275; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_6 = 8276; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBC_7 = 8277; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_0 = 8278; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_1 = 8279; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_2 = 8280; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_3 = 8281; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_4 = 8282; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_5 = 8283; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_6 = 8284; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBF_7 = 8285; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_0 = 8286; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_1 = 8287; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_2 = 8288; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_3 = 8289; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_4 = 8290; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_5 = 8291; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_6 = 8292; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBP_7 = 8293; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_0 = 8294; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_1 = 8295; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_2 = 8296; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_3 = 8297; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_4 = 8298; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_5 = 8299; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_6 = 8300; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PBR_7 = 8301; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_0 = 8302; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_1 = 8303; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_2 = 8304; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_PEF_3 = 8305; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_REG_0 = 8306; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_REG_1 = 8307; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_REG_2 = 8308; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_REG_3 = 8309; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_0 = 8310; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_1 = 8311; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_2 = 8312; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV1_3 = 8313; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_0 = 8314; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_1 = 8315; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_2 = 8316; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV2_3 = 8317; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_0 = 8318; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_1 = 8319; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_2 = 8320; // 3 +const static uint64_t SH_FLD_IDIAL_CTL_MASK_RSV3_3 = 8321; // 3 +const static uint64_t SH_FLD_IDIAL_DEBUG0_CONFIG = 8322; // 3 +const static uint64_t SH_FLD_IDIAL_DEBUG1_CONFIG = 8323; // 3 +const static uint64_t SH_FLD_IDIAL_EA = 8324; // 2 +const static uint64_t SH_FLD_IDIAL_EA_LEN = 8325; // 2 +const static uint64_t SH_FLD_IDIAL_ECC_CONFIG = 8326; // 3 +const static uint64_t SH_FLD_IDIAL_ERRINJ = 8327; // 3 +const static uint64_t SH_FLD_IDIAL_IBAR_ERRP = 8328; // 1 +const static uint64_t SH_FLD_IDIAL_IBRD = 8329; // 3 +const static uint64_t SH_FLD_IDIAL_IBRD_LEN = 8330; // 3 +const static uint64_t SH_FLD_IDIAL_IBUF_CTL_PIPE = 8331; // 3 +const static uint64_t SH_FLD_IDIAL_IBUF_RDWR = 8332; // 3 +const static uint64_t SH_FLD_IDIAL_IBUF_STATE = 8333; // 3 +const static uint64_t SH_FLD_IDIAL_IBUF_WARB = 8334; // 3 +const static uint64_t SH_FLD_IDIAL_IBUF_WRITE = 8335; // 3 +const static uint64_t SH_FLD_IDIAL_INHIBIT_CONFIG = 8336; // 3 +const static uint64_t SH_FLD_IDIAL_IR_CE = 8337; // 3 +const static uint64_t SH_FLD_IDIAL_IR_CE_LEN = 8338; // 3 +const static uint64_t SH_FLD_IDIAL_IR_SUE = 8339; // 3 +const static uint64_t SH_FLD_IDIAL_IR_SUE_LEN = 8340; // 3 +const static uint64_t SH_FLD_IDIAL_IR_UE = 8341; // 3 +const static uint64_t SH_FLD_IDIAL_IR_UE_LEN = 8342; // 3 +const static uint64_t SH_FLD_IDIAL_ISSYNC = 8343; // 1 +const static uint64_t SH_FLD_IDIAL_ISSYNC_LEN = 8344; // 1 +const static uint64_t SH_FLD_IDIAL_LEN = 8345; // 34 +const static uint64_t SH_FLD_IDIAL_MISC_STATE = 8346; // 3 +const static uint64_t SH_FLD_IDIAL_MM_LOCAL_XSTOP = 8347; // 1 +const static uint64_t SH_FLD_IDIAL_MRG_IR_PIPE = 8348; // 3 +const static uint64_t SH_FLD_IDIAL_MRG_OR_PIPE = 8349; // 3 +const static uint64_t SH_FLD_IDIAL_MRG_STATE = 8350; // 3 +const static uint64_t SH_FLD_IDIAL_NDL0_NOSTALL = 8351; // 1 +const static uint64_t SH_FLD_IDIAL_NDL0_STALL = 8352; // 1 +const static uint64_t SH_FLD_IDIAL_NDL1_NOSTALL = 8353; // 1 +const static uint64_t SH_FLD_IDIAL_NDL1_STALL = 8354; // 1 +const static uint64_t SH_FLD_IDIAL_NDL2_NOSTALL = 8355; // 1 +const static uint64_t SH_FLD_IDIAL_NDL2_STALL = 8356; // 1 +const static uint64_t SH_FLD_IDIAL_NDL3_NOSTALL = 8357; // 1 +const static uint64_t SH_FLD_IDIAL_NDL3_STALL = 8358; // 1 +const static uint64_t SH_FLD_IDIAL_NDL4_NOSTALL = 8359; // 1 +const static uint64_t SH_FLD_IDIAL_NDL4_STALL = 8360; // 1 +const static uint64_t SH_FLD_IDIAL_NDL5_NOSTALL = 8361; // 1 +const static uint64_t SH_FLD_IDIAL_NDL5_STALL = 8362; // 1 +const static uint64_t SH_FLD_IDIAL_OBRD = 8363; // 3 +const static uint64_t SH_FLD_IDIAL_OBRD_LEN = 8364; // 3 +const static uint64_t SH_FLD_IDIAL_OBUF_RDWR = 8365; // 3 +const static uint64_t SH_FLD_IDIAL_OBUF_STATE = 8366; // 3 +const static uint64_t SH_FLD_IDIAL_OR_CE = 8367; // 3 +const static uint64_t SH_FLD_IDIAL_OR_CE_LEN = 8368; // 3 +const static uint64_t SH_FLD_IDIAL_OR_SUE = 8369; // 3 +const static uint64_t SH_FLD_IDIAL_OR_SUE_LEN = 8370; // 3 +const static uint64_t SH_FLD_IDIAL_OR_UE = 8371; // 3 +const static uint64_t SH_FLD_IDIAL_OR_UE_LEN = 8372; // 3 +const static uint64_t SH_FLD_IDIAL_PAR = 8373; // 1 +const static uint64_t SH_FLD_IDIAL_PAR_LEN = 8374; // 1 +const static uint64_t SH_FLD_IDIAL_PBRX_RTAG = 8375; // 6 +const static uint64_t SH_FLD_IDIAL_PBTX_AMO = 8376; // 3 +const static uint64_t SH_FLD_IDIAL_PBTX_AMO_LEN = 8377; // 3 +const static uint64_t SH_FLD_IDIAL_PBTX_PIPE = 8378; // 3 +const static uint64_t SH_FLD_IDIAL_PBTX_STATE = 8379; // 3 +const static uint64_t SH_FLD_IDIAL_PC = 8380; // 2 +const static uint64_t SH_FLD_IDIAL_PC_LEN = 8381; // 2 +const static uint64_t SH_FLD_IDIAL_PE = 8382; // 2 +const static uint64_t SH_FLD_IDIAL_PE_LEN = 8383; // 2 +const static uint64_t SH_FLD_IDIAL_PR_CE = 8384; // 3 +const static uint64_t SH_FLD_IDIAL_PR_CE_LEN = 8385; // 3 +const static uint64_t SH_FLD_IDIAL_PR_SUE = 8386; // 3 +const static uint64_t SH_FLD_IDIAL_PR_SUE_LEN = 8387; // 3 +const static uint64_t SH_FLD_IDIAL_PR_UE = 8388; // 3 +const static uint64_t SH_FLD_IDIAL_PR_UE_LEN = 8389; // 3 +const static uint64_t SH_FLD_IDIAL_PT_CE = 8390; // 3 +const static uint64_t SH_FLD_IDIAL_PT_CE_LEN = 8391; // 3 +const static uint64_t SH_FLD_IDIAL_PT_SUE = 8392; // 3 +const static uint64_t SH_FLD_IDIAL_PT_SUE_LEN = 8393; // 3 +const static uint64_t SH_FLD_IDIAL_PT_UE = 8394; // 3 +const static uint64_t SH_FLD_IDIAL_PT_UE_LEN = 8395; // 3 +const static uint64_t SH_FLD_IDIAL_RA = 8396; // 2 +const static uint64_t SH_FLD_IDIAL_RA_LEN = 8397; // 2 +const static uint64_t SH_FLD_IDIAL_RING_ERRP = 8398; // 1 +const static uint64_t SH_FLD_IDIAL_RNW = 8399; // 1 +const static uint64_t SH_FLD_IDIAL_RQIN_OVF = 8400; // 3 +const static uint64_t SH_FLD_IDIAL_RQIN_OVF_LEN = 8401; // 3 +const static uint64_t SH_FLD_IDIAL_RQIN_STATE = 8402; // 3 +const static uint64_t SH_FLD_IDIAL_RSVD0 = 8403; // 4 +const static uint64_t SH_FLD_IDIAL_RSVD0_LEN = 8404; // 4 +const static uint64_t SH_FLD_IDIAL_RSVD1 = 8405; // 2 +const static uint64_t SH_FLD_IDIAL_RSVD1_LEN = 8406; // 2 +const static uint64_t SH_FLD_IDIAL_SCOMDAA_ERRP = 8407; // 1 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_0 = 8408; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_1 = 8409; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_2 = 8410; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_ASBE_3 = 8411; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_0 = 8412; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_1 = 8413; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_2 = 8414; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_AUE_3 = 8415; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_0 = 8416; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_1 = 8417; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_2 = 8418; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_FWD_3 = 8419; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_0 = 8420; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_1 = 8421; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_2 = 8422; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_3 = 8423; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_4 = 8424; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_5 = 8425; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_6 = 8426; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NCF_7 = 8427; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_0 = 8428; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_1 = 8429; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_10 = 8430; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_11 = 8431; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_12 = 8432; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_13 = 8433; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_14 = 8434; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_15 = 8435; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_2 = 8436; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_3 = 8437; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_4 = 8438; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_5 = 8439; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_6 = 8440; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_7 = 8441; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_8 = 8442; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLGX_9 = 8443; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_0 = 8444; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_1 = 8445; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_10 = 8446; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_11 = 8447; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_12 = 8448; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_13 = 8449; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_14 = 8450; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_15 = 8451; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_16 = 8452; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_17 = 8453; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_18 = 8454; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_19 = 8455; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_2 = 8456; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_20 = 8457; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_21 = 8458; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_22 = 8459; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_23 = 8460; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_24 = 8461; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_25 = 8462; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_26 = 8463; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_27 = 8464; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_28 = 8465; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_29 = 8466; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_3 = 8467; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_30 = 8468; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_31 = 8469; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_32 = 8470; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_33 = 8471; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_34 = 8472; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_35 = 8473; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_36 = 8474; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_37 = 8475; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_38 = 8476; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_39 = 8477; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_4 = 8478; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_40 = 8479; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_41 = 8480; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_42 = 8481; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_43 = 8482; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_44 = 8483; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_45 = 8484; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_46 = 8485; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_47 = 8486; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_48 = 8487; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_49 = 8488; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_5 = 8489; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_50 = 8490; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_51 = 8491; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_52 = 8492; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_53 = 8493; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_54 = 8494; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_55 = 8495; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_56 = 8496; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_57 = 8497; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_58 = 8498; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_59 = 8499; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_6 = 8500; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_60 = 8501; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_61 = 8502; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_62 = 8503; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_63 = 8504; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_7 = 8505; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_8 = 8506; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NLG_9 = 8507; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_0 = 8508; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_1 = 8509; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_10 = 8510; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_11 = 8511; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_12 = 8512; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_13 = 8513; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_14 = 8514; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_15 = 8515; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_16 = 8516; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_17 = 8517; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_18 = 8518; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_19 = 8519; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_2 = 8520; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_20 = 8521; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_21 = 8522; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_22 = 8523; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_23 = 8524; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_24 = 8525; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_25 = 8526; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_26 = 8527; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_27 = 8528; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_28 = 8529; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_29 = 8530; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_3 = 8531; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_30 = 8532; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_31 = 8533; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_4 = 8534; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_5 = 8535; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_6 = 8536; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_7 = 8537; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_8 = 8538; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_NVF_9 = 8539; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_0 = 8540; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_1 = 8541; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_10 = 8542; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_11 = 8543; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_2 = 8544; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_3 = 8545; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_4 = 8546; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_5 = 8547; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_6 = 8548; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_7 = 8549; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_8 = 8550; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBC_9 = 8551; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_0 = 8552; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_1 = 8553; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_10 = 8554; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_11 = 8555; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_2 = 8556; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_3 = 8557; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_4 = 8558; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_5 = 8559; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_6 = 8560; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_7 = 8561; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_8 = 8562; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBF_9 = 8563; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_0 = 8564; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_1 = 8565; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_2 = 8566; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_3 = 8567; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_4 = 8568; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_5 = 8569; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_6 = 8570; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBP_7 = 8571; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_0 = 8572; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_1 = 8573; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_2 = 8574; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_3 = 8575; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_4 = 8576; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_5 = 8577; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_6 = 8578; // 12 +const static uint64_t SH_FLD_IDIAL_SM_FIRST_PBR_7 = 8579; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_0 = 8580; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_1 = 8581; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_2 = 8582; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_ASBE_3 = 8583; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_0 = 8584; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_1 = 8585; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_2 = 8586; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_AUE_3 = 8587; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_0 = 8588; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_1 = 8589; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_2 = 8590; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_FWD_3 = 8591; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_0 = 8592; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_1 = 8593; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_2 = 8594; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_3 = 8595; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_4 = 8596; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_5 = 8597; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_6 = 8598; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NCF_7 = 8599; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_0 = 8600; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_1 = 8601; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_10 = 8602; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_11 = 8603; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_12 = 8604; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_13 = 8605; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_14 = 8606; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_15 = 8607; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_2 = 8608; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_3 = 8609; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_4 = 8610; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_5 = 8611; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_6 = 8612; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_7 = 8613; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_8 = 8614; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLGX_9 = 8615; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_0 = 8616; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_1 = 8617; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_10 = 8618; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_11 = 8619; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_12 = 8620; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_13 = 8621; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_14 = 8622; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_15 = 8623; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_16 = 8624; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_17 = 8625; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_18 = 8626; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_19 = 8627; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_2 = 8628; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_20 = 8629; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_21 = 8630; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_22 = 8631; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_23 = 8632; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_24 = 8633; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_25 = 8634; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_26 = 8635; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_27 = 8636; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_28 = 8637; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_29 = 8638; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_3 = 8639; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_30 = 8640; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_31 = 8641; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_32 = 8642; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_33 = 8643; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_34 = 8644; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_35 = 8645; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_36 = 8646; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_37 = 8647; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_38 = 8648; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_39 = 8649; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_4 = 8650; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_40 = 8651; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_41 = 8652; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_42 = 8653; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_43 = 8654; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_44 = 8655; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_45 = 8656; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_46 = 8657; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_47 = 8658; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_48 = 8659; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_49 = 8660; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_5 = 8661; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_50 = 8662; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_51 = 8663; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_52 = 8664; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_53 = 8665; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_54 = 8666; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_55 = 8667; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_56 = 8668; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_57 = 8669; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_58 = 8670; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_59 = 8671; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_6 = 8672; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_60 = 8673; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_61 = 8674; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_62 = 8675; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_63 = 8676; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_7 = 8677; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_8 = 8678; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NLG_9 = 8679; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_0 = 8680; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_1 = 8681; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_10 = 8682; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_11 = 8683; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_12 = 8684; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_13 = 8685; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_14 = 8686; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_15 = 8687; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_16 = 8688; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_17 = 8689; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_18 = 8690; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_19 = 8691; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_2 = 8692; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_20 = 8693; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_21 = 8694; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_22 = 8695; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_23 = 8696; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_24 = 8697; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_25 = 8698; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_26 = 8699; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_27 = 8700; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_28 = 8701; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_29 = 8702; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_3 = 8703; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_30 = 8704; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_31 = 8705; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_4 = 8706; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_5 = 8707; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_6 = 8708; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_7 = 8709; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_8 = 8710; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_NVF_9 = 8711; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_0 = 8712; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_1 = 8713; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_10 = 8714; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_11 = 8715; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_2 = 8716; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_3 = 8717; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_4 = 8718; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_5 = 8719; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_6 = 8720; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_7 = 8721; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_8 = 8722; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBC_9 = 8723; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_0 = 8724; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_1 = 8725; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_10 = 8726; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_11 = 8727; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_2 = 8728; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_3 = 8729; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_4 = 8730; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_5 = 8731; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_6 = 8732; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_7 = 8733; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_8 = 8734; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBF_9 = 8735; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_0 = 8736; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_1 = 8737; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_2 = 8738; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_3 = 8739; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_4 = 8740; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_5 = 8741; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_6 = 8742; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBP_7 = 8743; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_0 = 8744; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_1 = 8745; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_2 = 8746; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_3 = 8747; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_4 = 8748; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_5 = 8749; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_6 = 8750; // 12 +const static uint64_t SH_FLD_IDIAL_SM_HOLD_PBR_7 = 8751; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_0 = 8752; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_1 = 8753; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_2 = 8754; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_ASBE_3 = 8755; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_AUE_0 = 8756; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_AUE_1 = 8757; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_AUE_2 = 8758; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_AUE_3 = 8759; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_FWD_0 = 8760; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_FWD_1 = 8761; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_FWD_2 = 8762; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_FWD_3 = 8763; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NCF_0 = 8764; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NCF_1 = 8765; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NCF_2 = 8766; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NCF_3 = 8767; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NCF_4 = 8768; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NCF_5 = 8769; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NCF_6 = 8770; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NCF_7 = 8771; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_0 = 8772; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_1 = 8773; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_10 = 8774; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_11 = 8775; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_12 = 8776; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_13 = 8777; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_14 = 8778; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_15 = 8779; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_2 = 8780; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_3 = 8781; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_4 = 8782; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_5 = 8783; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_6 = 8784; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_7 = 8785; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_8 = 8786; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLGX_9 = 8787; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_0 = 8788; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_1 = 8789; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_10 = 8790; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_11 = 8791; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_12 = 8792; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_13 = 8793; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_14 = 8794; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_15 = 8795; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_16 = 8796; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_17 = 8797; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_18 = 8798; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_19 = 8799; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_2 = 8800; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_20 = 8801; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_21 = 8802; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_22 = 8803; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_23 = 8804; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_24 = 8805; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_25 = 8806; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_26 = 8807; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_27 = 8808; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_28 = 8809; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_29 = 8810; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_3 = 8811; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_30 = 8812; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_31 = 8813; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_32 = 8814; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_33 = 8815; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_34 = 8816; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_35 = 8817; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_36 = 8818; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_37 = 8819; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_38 = 8820; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_39 = 8821; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_4 = 8822; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_40 = 8823; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_41 = 8824; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_42 = 8825; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_43 = 8826; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_44 = 8827; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_45 = 8828; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_46 = 8829; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_47 = 8830; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_48 = 8831; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_49 = 8832; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_5 = 8833; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_50 = 8834; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_51 = 8835; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_52 = 8836; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_53 = 8837; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_54 = 8838; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_55 = 8839; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_56 = 8840; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_57 = 8841; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_58 = 8842; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_59 = 8843; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_6 = 8844; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_60 = 8845; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_61 = 8846; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_62 = 8847; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_63 = 8848; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_7 = 8849; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_8 = 8850; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NLG_9 = 8851; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_0 = 8852; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_1 = 8853; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_10 = 8854; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_11 = 8855; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_12 = 8856; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_13 = 8857; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_14 = 8858; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_15 = 8859; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_16 = 8860; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_17 = 8861; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_18 = 8862; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_19 = 8863; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_2 = 8864; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_20 = 8865; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_21 = 8866; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_22 = 8867; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_23 = 8868; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_24 = 8869; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_25 = 8870; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_26 = 8871; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_27 = 8872; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_28 = 8873; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_29 = 8874; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_3 = 8875; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_30 = 8876; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_31 = 8877; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_4 = 8878; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_5 = 8879; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_6 = 8880; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_7 = 8881; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_8 = 8882; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_NVF_9 = 8883; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_0 = 8884; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_1 = 8885; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_10 = 8886; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_11 = 8887; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_2 = 8888; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_3 = 8889; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_4 = 8890; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_5 = 8891; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_6 = 8892; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_7 = 8893; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_8 = 8894; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBC_9 = 8895; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_0 = 8896; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_1 = 8897; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_10 = 8898; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_11 = 8899; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_2 = 8900; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_3 = 8901; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_4 = 8902; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_5 = 8903; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_6 = 8904; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_7 = 8905; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_8 = 8906; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBF_9 = 8907; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_0 = 8908; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_1 = 8909; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_2 = 8910; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_3 = 8911; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_4 = 8912; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_5 = 8913; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_6 = 8914; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBP_7 = 8915; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBR_0 = 8916; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBR_1 = 8917; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBR_2 = 8918; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBR_3 = 8919; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBR_4 = 8920; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBR_5 = 8921; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBR_6 = 8922; // 12 +const static uint64_t SH_FLD_IDIAL_SM_MASK_PBR_7 = 8923; // 12 +const static uint64_t SH_FLD_IDIAL_TAG = 8924; // 1 +const static uint64_t SH_FLD_IDIAL_TAG_LEN = 8925; // 1 +const static uint64_t SH_FLD_IDIAL_VLD = 8926; // 1 +const static uint64_t SH_FLD_IDLE = 8927; // 2 +const static uint64_t SH_FLD_IDLES = 8928; // 64 +const static uint64_t SH_FLD_IDLES_LEN = 8929; // 64 +const static uint64_t SH_FLD_IDLE_INDICATION = 8930; // 1 +const static uint64_t SH_FLD_IDLE_PAT_ACTN = 8931; // 2 +const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_0_13 = 8932; // 2 +const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_0_13_LEN = 8933; // 2 +const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_14 = 8934; // 2 +const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_15 = 8935; // 2 +const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_16 = 8936; // 2 +const static uint64_t SH_FLD_IDLE_PAT_ADDRESS_17 = 8937; // 2 +const static uint64_t SH_FLD_IDLE_PAT_BANK_0_1 = 8938; // 2 +const static uint64_t SH_FLD_IDLE_PAT_BANK_0_1_LEN = 8939; // 2 +const static uint64_t SH_FLD_IDLE_PAT_BANK_2 = 8940; // 2 +const static uint64_t SH_FLD_IDLE_PAT_BANK_GROUP_0 = 8941; // 2 +const static uint64_t SH_FLD_IDLE_PAT_BANK_GROUP_1 = 8942; // 2 +const static uint64_t SH_FLD_IDLE_PAT_PARITY = 8943; // 2 +const static uint64_t SH_FLD_ID_LEN = 8944; // 129 +const static uint64_t SH_FLD_IFC_REG_CERR0 = 8945; // 1 +const static uint64_t SH_FLD_IFC_REG_CERR1 = 8946; // 1 +const static uint64_t SH_FLD_IFC_REG_CERR2 = 8947; // 1 +const static uint64_t SH_FLD_IFC_REG_ERR0 = 8948; // 1 +const static uint64_t SH_FLD_IFC_REG_ERR1 = 8949; // 1 +const static uint64_t SH_FLD_IFC_REG_ERR2 = 8950; // 1 +const static uint64_t SH_FLD_IFC_REG_ERR3 = 8951; // 1 +const static uint64_t SH_FLD_IFC_REG_ERR4 = 8952; // 1 +const static uint64_t SH_FLD_IFC_REG_ERR5 = 8953; // 1 +const static uint64_t SH_FLD_IFC_REG_ERR6 = 8954; // 1 +const static uint64_t SH_FLD_IFC_REG_ERR7 = 8955; // 1 +const static uint64_t SH_FLD_IFC_REG_ERR8 = 8956; // 1 +const static uint64_t SH_FLD_IFREQ = 8957; // 1 +const static uint64_t SH_FLD_IGNORE_PECE = 8958; // 12 +const static uint64_t SH_FLD_ILLEGAL_CACHE_OP = 8959; // 1 +const static uint64_t SH_FLD_ILLEGAL_CACHE_OP_MASK = 8960; // 1 +const static uint64_t SH_FLD_ILLEGAL_LPC_BAR_ACCESS = 8961; // 4 +const static uint64_t SH_FLD_ILL_CRESP = 8962; // 1 +const static uint64_t SH_FLD_IMA_ACK_DEAD = 8963; // 12 +const static uint64_t SH_FLD_IMA_CRESP_ADDR_ERR = 8964; // 12 +const static uint64_t SH_FLD_IMM_FREEZE = 8965; // 43 +const static uint64_t SH_FLD_IN = 8966; // 264 +const static uint64_t SH_FLD_IN0 = 8967; // 339 +const static uint64_t SH_FLD_IN1 = 8968; // 296 +const static uint64_t SH_FLD_IN10 = 8969; // 208 +const static uint64_t SH_FLD_IN11 = 8970; // 208 +const static uint64_t SH_FLD_IN11_LEN = 8971; // 3 +const static uint64_t SH_FLD_IN12 = 8972; // 162 +const static uint64_t SH_FLD_IN12_LEN = 8973; // 6 +const static uint64_t SH_FLD_IN13 = 8974; // 156 +const static uint64_t SH_FLD_IN13_LEN = 8975; // 12 +const static uint64_t SH_FLD_IN14 = 8976; // 144 +const static uint64_t SH_FLD_IN14_LEN = 8977; // 3 +const static uint64_t SH_FLD_IN15 = 8978; // 141 +const static uint64_t SH_FLD_IN16 = 8979; // 141 +const static uint64_t SH_FLD_IN17 = 8980; // 141 +const static uint64_t SH_FLD_IN17_LEN = 8981; // 6 +const static uint64_t SH_FLD_IN18 = 8982; // 135 +const static uint64_t SH_FLD_IN18_LEN = 8983; // 3 +const static uint64_t SH_FLD_IN19 = 8984; // 132 +const static uint64_t SH_FLD_IN2 = 8985; // 296 +const static uint64_t SH_FLD_IN20 = 8986; // 132 +const static uint64_t SH_FLD_IN21 = 8987; // 132 +const static uint64_t SH_FLD_IN21_LEN = 8988; // 3 +const static uint64_t SH_FLD_IN22 = 8989; // 86 +const static uint64_t SH_FLD_IN23 = 8990; // 43 +const static uint64_t SH_FLD_IN24 = 8991; // 43 +const static uint64_t SH_FLD_IN25 = 8992; // 43 +const static uint64_t SH_FLD_IN26 = 8993; // 129 +const static uint64_t SH_FLD_IN27 = 8994; // 43 +const static uint64_t SH_FLD_IN28 = 8995; // 43 +const static uint64_t SH_FLD_IN29 = 8996; // 43 +const static uint64_t SH_FLD_IN3 = 8997; // 296 +const static uint64_t SH_FLD_IN30 = 8998; // 43 +const static uint64_t SH_FLD_IN31 = 8999; // 43 +const static uint64_t SH_FLD_IN32 = 9000; // 43 +const static uint64_t SH_FLD_IN33 = 9001; // 43 +const static uint64_t SH_FLD_IN34 = 9002; // 43 +const static uint64_t SH_FLD_IN35 = 9003; // 43 +const static uint64_t SH_FLD_IN36 = 9004; // 43 +const static uint64_t SH_FLD_IN37 = 9005; // 43 +const static uint64_t SH_FLD_IN38 = 9006; // 43 +const static uint64_t SH_FLD_IN39 = 9007; // 43 +const static uint64_t SH_FLD_IN3_LEN = 9008; // 1 +const static uint64_t SH_FLD_IN4 = 9009; // 338 +const static uint64_t SH_FLD_IN40 = 9010; // 43 +const static uint64_t SH_FLD_IN4_LEN = 9011; // 1 +const static uint64_t SH_FLD_IN5 = 9012; // 337 +const static uint64_t SH_FLD_IN5_LEN = 9013; // 78 +const static uint64_t SH_FLD_IN6 = 9014; // 260 +const static uint64_t SH_FLD_IN6_LEN = 9015; // 3 +const static uint64_t SH_FLD_IN7 = 9016; // 257 +const static uint64_t SH_FLD_IN7_LEN = 9017; // 9 +const static uint64_t SH_FLD_IN8 = 9018; // 248 +const static uint64_t SH_FLD_IN8_LEN = 9019; // 3 +const static uint64_t SH_FLD_IN9 = 9020; // 245 +const static uint64_t SH_FLD_INBAND_BAR_HIT_WITH_INCORRECT_TTYPE = 9021; // 4 +const static uint64_t SH_FLD_INBD_ARRAY_ECC_CE = 9022; // 2 +const static uint64_t SH_FLD_INBD_ARRAY_ECC_UE = 9023; // 2 +const static uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_CE = 9024; // 1 +const static uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_SUE = 9025; // 1 +const static uint64_t SH_FLD_INBD_LCO_ARRAY_ECC_UE = 9026; // 1 +const static uint64_t SH_FLD_INCLUDE_TRAFFIC = 9027; // 1 +const static uint64_t SH_FLD_INCOMING_PB_PARITY_ERR = 9028; // 2 +const static uint64_t SH_FLD_INDEX = 9029; // 1 +const static uint64_t SH_FLD_INDEX_LEN = 9030; // 1 +const static uint64_t SH_FLD_INDIRECT_BRIDGE_0_SOURCE = 9031; // 1 +const static uint64_t SH_FLD_INDIRECT_BRIDGE_1_SOURCE = 9032; // 1 +const static uint64_t SH_FLD_INDIRECT_BRIDGE_2_SOURCE = 9033; // 1 +const static uint64_t SH_FLD_INDIRECT_BRIDGE_3_SOURCE = 9034; // 1 +const static uint64_t SH_FLD_INDIRECT_MODE = 9035; // 2 +const static uint64_t SH_FLD_INDIR_THRDID = 9036; // 4 +const static uint64_t SH_FLD_INDIR_THRDID_LEN = 9037; // 4 +const static uint64_t SH_FLD_INDIR_VLD = 9038; // 4 +const static uint64_t SH_FLD_INEX = 9039; // 43 +const static uint64_t SH_FLD_INFINITE_MODE = 9040; // 43 +const static uint64_t SH_FLD_INFO = 9041; // 43 +const static uint64_t SH_FLD_INFORMATION = 9042; // 8 +const static uint64_t SH_FLD_INFORMATION_LEN = 9043; // 8 +const static uint64_t SH_FLD_INFO_CAPTURED = 9044; // 4 +const static uint64_t SH_FLD_INH0_TICK = 9045; // 12 +const static uint64_t SH_FLD_INH0_TICK_LEN = 9046; // 12 +const static uint64_t SH_FLD_INH1_TICK = 9047; // 12 +const static uint64_t SH_FLD_INH1_TICK_LEN = 9048; // 12 +const static uint64_t SH_FLD_INIT = 9049; // 1 +const static uint64_t SH_FLD_INITIAL_COARSE_WR = 9050; // 8 +const static uint64_t SH_FLD_INITIAL_PAT_WRITE = 9051; // 8 +const static uint64_t SH_FLD_INIT_DONE_DL_MASK = 9052; // 2 +const static uint64_t SH_FLD_INIT_REQUEST = 9053; // 1 +const static uint64_t SH_FLD_INIT_TIMER = 9054; // 1 +const static uint64_t SH_FLD_INIT_TIMER_LEN = 9055; // 1 +const static uint64_t SH_FLD_INIT_TMR_CFG = 9056; // 72 +const static uint64_t SH_FLD_INIT_TMR_CFG_LEN = 9057; // 72 +const static uint64_t SH_FLD_INJ = 9058; // 1 +const static uint64_t SH_FLD_INJECT_1HOT_SM_ERROR = 9059; // 8 +const static uint64_t SH_FLD_INJECT_ENABLE = 9060; // 1 +const static uint64_t SH_FLD_INJECT_ERR = 9061; // 12 +const static uint64_t SH_FLD_INJECT_FIR_ERR0 = 9062; // 8 +const static uint64_t SH_FLD_INJECT_FIR_ERR1 = 9063; // 8 +const static uint64_t SH_FLD_INJECT_FIR_ERR2 = 9064; // 8 +const static uint64_t SH_FLD_INJECT_FIR_ERR3 = 9065; // 8 +const static uint64_t SH_FLD_INJECT_FIR_ERR4 = 9066; // 8 +const static uint64_t SH_FLD_INJECT_MODE = 9067; // 2 +const static uint64_t SH_FLD_INJECT_MODE_LEN = 9068; // 2 +const static uint64_t SH_FLD_INJECT_TYPE = 9069; // 2 +const static uint64_t SH_FLD_INJECT_TYPE_LEN = 9070; // 2 +const static uint64_t SH_FLD_INJ_LEN = 9071; // 1 +const static uint64_t SH_FLD_INOP = 9072; // 43 +const static uint64_t SH_FLD_INOP_FORCE_SG = 9073; // 43 +const static uint64_t SH_FLD_INOP_LEN = 9074; // 43 +const static uint64_t SH_FLD_INOP_WAIT = 9075; // 43 +const static uint64_t SH_FLD_INOP_WAIT_LEN = 9076; // 43 +const static uint64_t SH_FLD_INPROG_WR_ERR = 9077; // 1 +const static uint64_t SH_FLD_INRD_DONE_ERR = 9078; // 1 +const static uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK = 9079; // 43 +const static uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_DO = 9080; // 43 +const static uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN = 9081; // 43 +const static uint64_t SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN = 9082; // 43 +const static uint64_t SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL = 9083; // 43 +const static uint64_t SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN = 9084; // 43 +const static uint64_t SH_FLD_INST1_CHECKSTOP_MODE_LT = 9085; // 43 +const static uint64_t SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN = 9086; // 43 +const static uint64_t SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR = 9087; // 43 +const static uint64_t SH_FLD_INST1_COND3_ENABLE = 9088; // 43 +const static uint64_t SH_FLD_INST1_CONDITION1_ACTION_BANK = 9089; // 43 +const static uint64_t SH_FLD_INST1_CONDITION1_ACTION_DO = 9090; // 43 +const static uint64_t SH_FLD_INST1_CONDITION1_ACTION_DO_LEN = 9091; // 43 +const static uint64_t SH_FLD_INST1_CONDITION1_ACTION_WAITN = 9092; // 43 +const static uint64_t SH_FLD_INST1_CONDITION1_TRIG_SEL = 9093; // 43 +const static uint64_t SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN = 9094; // 43 +const static uint64_t SH_FLD_INST1_CONDITION2_ACTION_BANK = 9095; // 43 +const static uint64_t SH_FLD_INST1_CONDITION2_ACTION_DO = 9096; // 43 +const static uint64_t SH_FLD_INST1_CONDITION2_ACTION_DO_LEN = 9097; // 43 +const static uint64_t SH_FLD_INST1_CONDITION2_ACTION_WAITN = 9098; // 43 +const static uint64_t SH_FLD_INST1_CONDITION2_TRIG_SEL = 9099; // 43 +const static uint64_t SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN = 9100; // 43 +const static uint64_t SH_FLD_INST1_SLOW_LFSR_MODE = 9101; // 43 +const static uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK = 9102; // 43 +const static uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_DO = 9103; // 43 +const static uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN = 9104; // 43 +const static uint64_t SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN = 9105; // 43 +const static uint64_t SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL = 9106; // 43 +const static uint64_t SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 9107; // 43 +const static uint64_t SH_FLD_INST2_CHECKSTOP_MODE_LT = 9108; // 43 +const static uint64_t SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN = 9109; // 43 +const static uint64_t SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR = 9110; // 43 +const static uint64_t SH_FLD_INST2_COND3_ENABLE = 9111; // 43 +const static uint64_t SH_FLD_INST2_CONDITION1_ACTION_BANK = 9112; // 43 +const static uint64_t SH_FLD_INST2_CONDITION1_ACTION_DO = 9113; // 43 +const static uint64_t SH_FLD_INST2_CONDITION1_ACTION_DO_LEN = 9114; // 43 +const static uint64_t SH_FLD_INST2_CONDITION1_ACTION_WAITN = 9115; // 43 +const static uint64_t SH_FLD_INST2_CONDITION1_TRIG_SEL = 9116; // 43 +const static uint64_t SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN = 9117; // 43 +const static uint64_t SH_FLD_INST2_CONDITION2_ACTION_BANK = 9118; // 43 +const static uint64_t SH_FLD_INST2_CONDITION2_ACTION_DO = 9119; // 43 +const static uint64_t SH_FLD_INST2_CONDITION2_ACTION_DO_LEN = 9120; // 43 +const static uint64_t SH_FLD_INST2_CONDITION2_ACTION_WAITN = 9121; // 43 +const static uint64_t SH_FLD_INST2_CONDITION2_TRIG_SEL = 9122; // 43 +const static uint64_t SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN = 9123; // 43 +const static uint64_t SH_FLD_INST2_SLOW_LFSR_MODE = 9124; // 43 +const static uint64_t SH_FLD_INST3_COND3_ENABLE = 9125; // 43 +const static uint64_t SH_FLD_INST3_SLOW_LFSR_MODE = 9126; // 43 +const static uint64_t SH_FLD_INST4_COND3_ENABLE = 9127; // 43 +const static uint64_t SH_FLD_INST4_SLOW_LFSR_MODE = 9128; // 43 +const static uint64_t SH_FLD_INSTANT_CACHE_VDM_DATA = 9129; // 12 +const static uint64_t SH_FLD_INSTANT_CACHE_VDM_DATA_LEN = 9130; // 12 +const static uint64_t SH_FLD_INSTANT_CORE0_VDM_DATA = 9131; // 12 +const static uint64_t SH_FLD_INSTANT_CORE0_VDM_DATA_LEN = 9132; // 12 +const static uint64_t SH_FLD_INSTANT_CORE1_VDM_DATA = 9133; // 12 +const static uint64_t SH_FLD_INSTANT_CORE1_VDM_DATA_LEN = 9134; // 12 +const static uint64_t SH_FLD_INSTANT_CORE2_VDM_DATA = 9135; // 12 +const static uint64_t SH_FLD_INSTANT_CORE2_VDM_DATA_LEN = 9136; // 12 +const static uint64_t SH_FLD_INSTANT_CORE3_VDM_DATA = 9137; // 12 +const static uint64_t SH_FLD_INSTANT_CORE3_VDM_DATA_LEN = 9138; // 12 +const static uint64_t SH_FLD_INSTANT_VDM_CONTROL_SUMMARY = 9139; // 12 +const static uint64_t SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN = 9140; // 12 +const static uint64_t SH_FLD_INSTR0_BUSYCNT_RUNNING = 9141; // 1 +const static uint64_t SH_FLD_INSTR0_CYCLECNT_RUNNING = 9142; // 1 +const static uint64_t SH_FLD_INSTR0_MODE = 9143; // 1 +const static uint64_t SH_FLD_INSTR0_MODE_LEN = 9144; // 1 +const static uint64_t SH_FLD_INSTR0_RESET = 9145; // 1 +const static uint64_t SH_FLD_INSTR0_START = 9146; // 1 +const static uint64_t SH_FLD_INSTR0_STOP = 9147; // 1 +const static uint64_t SH_FLD_INSTR0_STOPPED_ON_ERROR = 9148; // 1 +const static uint64_t SH_FLD_INSTR0_STOP_ON_ERROR_GT = 9149; // 1 +const static uint64_t SH_FLD_INSTR0_STOP_ON_ERROR_GT_LEN = 9150; // 1 +const static uint64_t SH_FLD_INSTR0_STOP_TIMER_EN = 9151; // 1 +const static uint64_t SH_FLD_INSTR1_BUSYCNT_RUNNING = 9152; // 1 +const static uint64_t SH_FLD_INSTR1_CYCLECNT_RUNNING = 9153; // 1 +const static uint64_t SH_FLD_INSTR1_MODE = 9154; // 1 +const static uint64_t SH_FLD_INSTR1_MODE_LEN = 9155; // 1 +const static uint64_t SH_FLD_INSTR1_RESET = 9156; // 1 +const static uint64_t SH_FLD_INSTR1_START = 9157; // 1 +const static uint64_t SH_FLD_INSTR1_STOP = 9158; // 1 +const static uint64_t SH_FLD_INSTR1_STOPPED_ON_ERROR = 9159; // 1 +const static uint64_t SH_FLD_INSTR1_STOP_ON_ERROR_GT = 9160; // 1 +const static uint64_t SH_FLD_INSTR1_STOP_ON_ERROR_GT_LEN = 9161; // 1 +const static uint64_t SH_FLD_INSTR1_STOP_TIMER_EN = 9162; // 1 +const static uint64_t SH_FLD_INSTR2_BUSYCNT_RUNNING = 9163; // 1 +const static uint64_t SH_FLD_INSTR2_CYCLECNT_RUNNING = 9164; // 1 +const static uint64_t SH_FLD_INSTR2_MODE = 9165; // 1 +const static uint64_t SH_FLD_INSTR2_MODE_LEN = 9166; // 1 +const static uint64_t SH_FLD_INSTR2_RESET = 9167; // 1 +const static uint64_t SH_FLD_INSTR2_START = 9168; // 1 +const static uint64_t SH_FLD_INSTR2_STOP = 9169; // 1 +const static uint64_t SH_FLD_INSTR2_STOPPED_ON_ERROR = 9170; // 1 +const static uint64_t SH_FLD_INSTR2_STOP_ON_ERROR_GT = 9171; // 1 +const static uint64_t SH_FLD_INSTR2_STOP_ON_ERROR_GT_LEN = 9172; // 1 +const static uint64_t SH_FLD_INSTR2_STOP_TIMER_EN = 9173; // 1 +const static uint64_t SH_FLD_INST_CYCLE_SAMPLE = 9174; // 12 +const static uint64_t SH_FLD_INST_CYCLE_SAMPLE_LEN = 9175; // 12 +const static uint64_t SH_FLD_INTERMITTENT_CE_COUNT = 9176; // 2 +const static uint64_t SH_FLD_INTERMITTENT_CE_COUNT_LEN = 9177; // 2 +const static uint64_t SH_FLD_INTERMITTENT_MCE_COUNT = 9178; // 2 +const static uint64_t SH_FLD_INTERMITTENT_MCE_COUNT_LEN = 9179; // 2 +const static uint64_t SH_FLD_INTERNAL_ERR = 9180; // 1 +const static uint64_t SH_FLD_INTERNAL_ERROR = 9181; // 4 +const static uint64_t SH_FLD_INTERNAL_ERR_MASK = 9182; // 1 +const static uint64_t SH_FLD_INTERNAL_FSM_ERROR = 9183; // 2 +const static uint64_t SH_FLD_INTERNAL_PARITY_ERROR = 9184; // 6 +const static uint64_t SH_FLD_INTERNAL_SCOM_ERROR = 9185; // 32 +const static uint64_t SH_FLD_INTERNAL_SCOM_ERROR_CLONE = 9186; // 8 +const static uint64_t SH_FLD_INTERNAL_SCOM_ERROR_COPY = 9187; // 24 +const static uint64_t SH_FLD_INTERNAL_STATE_VECTOR = 9188; // 1 +const static uint64_t SH_FLD_INTERNAL_STATE_VECTOR_LEN = 9189; // 1 +const static uint64_t SH_FLD_INTERRUPT = 9190; // 3 +const static uint64_t SH_FLD_INTERRUPT0_ADDRESS_ERROR = 9191; // 4 +const static uint64_t SH_FLD_INTERRUPT1 = 9192; // 1 +const static uint64_t SH_FLD_INTERRUPT1_ADDRESS_ERROR = 9193; // 4 +const static uint64_t SH_FLD_INTERRUPT1_LEN = 9194; // 1 +const static uint64_t SH_FLD_INTERRUPT2 = 9195; // 1 +const static uint64_t SH_FLD_INTERRUPT2_ADDRESS_ERROR = 9196; // 4 +const static uint64_t SH_FLD_INTERRUPT2_LEN = 9197; // 1 +const static uint64_t SH_FLD_INTERRUPT3 = 9198; // 1 +const static uint64_t SH_FLD_INTERRUPT3_ADDRESS_ERROR = 9199; // 4 +const static uint64_t SH_FLD_INTERRUPT3_LEN = 9200; // 1 +const static uint64_t SH_FLD_INTERRUPT4 = 9201; // 1 +const static uint64_t SH_FLD_INTERRUPT4_ADDRESS_ERROR = 9202; // 4 +const static uint64_t SH_FLD_INTERRUPT4_LEN = 9203; // 1 +const static uint64_t SH_FLD_INTERRUPT5_ADDRESS_ERROR = 9204; // 4 +const static uint64_t SH_FLD_INTERRUPT_00 = 9205; // 1 +const static uint64_t SH_FLD_INTERRUPT_01 = 9206; // 1 +const static uint64_t SH_FLD_INTERRUPT_02 = 9207; // 1 +const static uint64_t SH_FLD_INTERRUPT_03 = 9208; // 1 +const static uint64_t SH_FLD_INTERRUPT_04 = 9209; // 1 +const static uint64_t SH_FLD_INTERRUPT_05 = 9210; // 1 +const static uint64_t SH_FLD_INTERRUPT_06 = 9211; // 1 +const static uint64_t SH_FLD_INTERRUPT_07 = 9212; // 1 +const static uint64_t SH_FLD_INTERRUPT_08 = 9213; // 1 +const static uint64_t SH_FLD_INTERRUPT_09 = 9214; // 1 +const static uint64_t SH_FLD_INTERRUPT_10 = 9215; // 1 +const static uint64_t SH_FLD_INTERRUPT_11 = 9216; // 1 +const static uint64_t SH_FLD_INTERRUPT_12 = 9217; // 1 +const static uint64_t SH_FLD_INTERRUPT_13 = 9218; // 1 +const static uint64_t SH_FLD_INTERRUPT_14 = 9219; // 1 +const static uint64_t SH_FLD_INTERRUPT_15 = 9220; // 1 +const static uint64_t SH_FLD_INTERRUPT_16 = 9221; // 1 +const static uint64_t SH_FLD_INTERRUPT_17 = 9222; // 1 +const static uint64_t SH_FLD_INTERRUPT_18 = 9223; // 1 +const static uint64_t SH_FLD_INTERRUPT_19 = 9224; // 1 +const static uint64_t SH_FLD_INTERRUPT_20 = 9225; // 1 +const static uint64_t SH_FLD_INTERRUPT_21 = 9226; // 1 +const static uint64_t SH_FLD_INTERRUPT_22 = 9227; // 1 +const static uint64_t SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE = 9228; // 4 +const static uint64_t SH_FLD_INTERRUPT_CONDITION_PENDING = 9229; // 1 +const static uint64_t SH_FLD_INTERRUPT_DISABLE = 9230; // 1 +const static uint64_t SH_FLD_INTERRUPT_DISABLE_LEN = 9231; // 1 +const static uint64_t SH_FLD_INTERRUPT_EDGE_POL_N = 9232; // 2 +const static uint64_t SH_FLD_INTERRUPT_EDGE_POL_N_LEN = 9233; // 2 +const static uint64_t SH_FLD_INTERRUPT_ENABLED = 9234; // 1 +const static uint64_t SH_FLD_INTERRUPT_FROM_ERROR = 9235; // 4 +const static uint64_t SH_FLD_INTERRUPT_FROM_FSP = 9236; // 4 +const static uint64_t SH_FLD_INTERRUPT_INPUT = 9237; // 12 +const static uint64_t SH_FLD_INTERRUPT_INPUT_LEN = 9238; // 12 +const static uint64_t SH_FLD_INTERRUPT_MASK = 9239; // 12 +const static uint64_t SH_FLD_INTERRUPT_MASK_LEN = 9240; // 12 +const static uint64_t SH_FLD_INTERRUPT_MASK_N = 9241; // 2 +const static uint64_t SH_FLD_INTERRUPT_MASK_N_LEN = 9242; // 2 +const static uint64_t SH_FLD_INTERRUPT_POLARITY = 9243; // 12 +const static uint64_t SH_FLD_INTERRUPT_POLARITY_LEN = 9244; // 12 +const static uint64_t SH_FLD_INTERRUPT_ROUTE_A_N = 9245; // 6 +const static uint64_t SH_FLD_INTERRUPT_ROUTE_A_N_LEN = 9246; // 6 +const static uint64_t SH_FLD_INTERRUPT_S0 = 9247; // 1 +const static uint64_t SH_FLD_INTERRUPT_S1 = 9248; // 1 +const static uint64_t SH_FLD_INTERRUPT_SENT = 9249; // 1 +const static uint64_t SH_FLD_INTERRUPT_TYPE = 9250; // 12 +const static uint64_t SH_FLD_INTERRUPT_TYPE_LEN = 9251; // 12 +const static uint64_t SH_FLD_INTERRUPT_TYPE_N = 9252; // 2 +const static uint64_t SH_FLD_INTERRUPT_TYPE_N_LEN = 9253; // 2 +const static uint64_t SH_FLD_INTER_FRAME_DELAY = 9254; // 1 +const static uint64_t SH_FLD_INTER_FRAME_DELAY_LEN = 9255; // 1 +const static uint64_t SH_FLD_INTQ_BAD_CRESP = 9256; // 1 +const static uint64_t SH_FLD_INTQ_FSM_PERR = 9257; // 1 +const static uint64_t SH_FLD_INTQ_OP_HANG = 9258; // 1 +const static uint64_t SH_FLD_INTQ_OVERFLOW = 9259; // 1 +const static uint64_t SH_FLD_INTR0 = 9260; // 5 +const static uint64_t SH_FLD_INTR1 = 9261; // 5 +const static uint64_t SH_FLD_INTR_GRANTED = 9262; // 30 +const static uint64_t SH_FLD_INT_0 = 9263; // 4 +const static uint64_t SH_FLD_INT_0_LEN = 9264; // 4 +const static uint64_t SH_FLD_INT_1 = 9265; // 2 +const static uint64_t SH_FLD_INT_1_LEN = 9266; // 2 +const static uint64_t SH_FLD_INT_2 = 9267; // 2 +const static uint64_t SH_FLD_INT_2_LEN = 9268; // 2 +const static uint64_t SH_FLD_INT_3 = 9269; // 2 +const static uint64_t SH_FLD_INT_3_LEN = 9270; // 2 +const static uint64_t SH_FLD_INT_CNTR_REF = 9271; // 1 +const static uint64_t SH_FLD_INT_CNTR_REF_LEN = 9272; // 1 +const static uint64_t SH_FLD_INT_CURRENT_STATE = 9273; // 6 +const static uint64_t SH_FLD_INT_CURRENT_STATE_LEN = 9274; // 6 +const static uint64_t SH_FLD_INT_ENA = 9275; // 1 +const static uint64_t SH_FLD_INT_ENABLE_ENC = 9276; // 6 +const static uint64_t SH_FLD_INT_ENABLE_ENC_LEN = 9277; // 6 +const static uint64_t SH_FLD_INT_GOTO_STATE = 9278; // 6 +const static uint64_t SH_FLD_INT_GOTO_STATE_LEN = 9279; // 6 +const static uint64_t SH_FLD_INT_MODE = 9280; // 6 +const static uint64_t SH_FLD_INT_MODE_LEN = 9281; // 6 +const static uint64_t SH_FLD_INT_NCE_ETE_ATTN = 9282; // 2 +const static uint64_t SH_FLD_INT_NEXT_STATE = 9283; // 6 +const static uint64_t SH_FLD_INT_NEXT_STATE_LEN = 9284; // 6 +const static uint64_t SH_FLD_INT_RETURN_STATE = 9285; // 6 +const static uint64_t SH_FLD_INT_RETURN_STATE_LEN = 9286; // 6 +const static uint64_t SH_FLD_INT_RX_FSM = 9287; // 43 +const static uint64_t SH_FLD_INT_STATE_ERR = 9288; // 1 +const static uint64_t SH_FLD_INT_TX_FSM = 9289; // 43 +const static uint64_t SH_FLD_INT_TYPE = 9290; // 43 +const static uint64_t SH_FLD_INVALIDATE_ADDRESS = 9291; // 1 +const static uint64_t SH_FLD_INVALIDATE_ADDRESS_LEN = 9292; // 1 +const static uint64_t SH_FLD_INVALIDATE_ALL = 9293; // 1 +const static uint64_t SH_FLD_INVALIDATE_ONE = 9294; // 1 +const static uint64_t SH_FLD_INVALIDATE_PE_NUMBER = 9295; // 1 +const static uint64_t SH_FLD_INVALIDATE_PE_NUMBER_LEN = 9296; // 1 +const static uint64_t SH_FLD_INVALIDCRESP = 9297; // 9 +const static uint64_t SH_FLD_INVALIDCRESP_MASK = 9298; // 9 +const static uint64_t SH_FLD_INVALID_ADDRESS = 9299; // 12 +const static uint64_t SH_FLD_INVALID_ADDRESS_ALIGNMENT = 9300; // 4 +const static uint64_t SH_FLD_INVALID_ADDRESS_MASK = 9301; // 8 +const static uint64_t SH_FLD_INVALID_CMD_0 = 9302; // 4 +const static uint64_t SH_FLD_INVALID_CMD_1 = 9303; // 2 +const static uint64_t SH_FLD_INVALID_CMD_2 = 9304; // 2 +const static uint64_t SH_FLD_INVALID_CMD_3 = 9305; // 2 +const static uint64_t SH_FLD_INVALID_COMMAND = 9306; // 4 +const static uint64_t SH_FLD_INVALID_CRESP = 9307; // 4 +const static uint64_t SH_FLD_INVALID_CRESP_ERR = 9308; // 1 +const static uint64_t SH_FLD_INVALID_CRESP_ERROR = 9309; // 2 +const static uint64_t SH_FLD_INVALID_MAINT_ADDRESS = 9310; // 4 +const static uint64_t SH_FLD_INVALID_MAINT_ADDRESS_LEN = 9311; // 2 +const static uint64_t SH_FLD_INVALID_REQTYPE = 9312; // 16 +const static uint64_t SH_FLD_INVALID_REQTYPE_ERR_MASK = 9313; // 8 +const static uint64_t SH_FLD_INVALID_REQTYPE_LEN = 9314; // 8 +const static uint64_t SH_FLD_INVALID_REQ_SOURCE = 9315; // 8 +const static uint64_t SH_FLD_INVALID_REQ_SOURCE_LEN = 9316; // 8 +const static uint64_t SH_FLD_INVALID_STATE_RECOV = 9317; // 1 +const static uint64_t SH_FLD_INVALID_STATE_UNRECOV = 9318; // 1 +const static uint64_t SH_FLD_INVALID_TRANSFER_SIZE = 9319; // 4 +const static uint64_t SH_FLD_INVALID_TTYPE = 9320; // 4 +const static uint64_t SH_FLD_INVAL_IODA_TBL_SEL_ESR = 9321; // 1 +const static uint64_t SH_FLD_INVLD_CMD_ERR = 9322; // 1 +const static uint64_t SH_FLD_INVLD_PRGM_ERR = 9323; // 1 +const static uint64_t SH_FLD_INV_PROT_ERR_CHK_DIS = 9324; // 1 +const static uint64_t SH_FLD_INV_SINGLE_THREAD_EN = 9325; // 1 +const static uint64_t SH_FLD_INV_TIMEOUT_CHK_DIS = 9326; // 1 +const static uint64_t SH_FLD_IN_BAD_OP_ERR = 9327; // 2 +const static uint64_t SH_FLD_IN_CERR_BIT10 = 9328; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT11 = 9329; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT12 = 9330; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT13 = 9331; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT14 = 9332; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT15 = 9333; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT16 = 9334; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT17 = 9335; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT18 = 9336; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT19 = 9337; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT20 = 9338; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT21 = 9339; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT22 = 9340; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT23 = 9341; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT24 = 9342; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT25 = 9343; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT26 = 9344; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT27 = 9345; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT28 = 9346; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT29 = 9347; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT4 = 9348; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT5 = 9349; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT6 = 9350; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT7 = 9351; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT8 = 9352; // 1 +const static uint64_t SH_FLD_IN_CERR_BIT9 = 9353; // 1 +const static uint64_t SH_FLD_IN_CERR_RESET = 9354; // 1 +const static uint64_t SH_FLD_IN_CERR_UNUSED_BITS = 9355; // 1 +const static uint64_t SH_FLD_IN_CERR_UNUSED_BITS_LEN = 9356; // 1 +const static uint64_t SH_FLD_IN_COUNT1 = 9357; // 1 +const static uint64_t SH_FLD_IN_COUNT1_LEN = 9358; // 1 +const static uint64_t SH_FLD_IN_COUNT2 = 9359; // 1 +const static uint64_t SH_FLD_IN_COUNT2_LEN = 9360; // 1 +const static uint64_t SH_FLD_IN_DELAY1 = 9361; // 1 +const static uint64_t SH_FLD_IN_DELAY1_LEN = 9362; // 1 +const static uint64_t SH_FLD_IN_DELAY2 = 9363; // 1 +const static uint64_t SH_FLD_IN_DELAY2_LEN = 9364; // 1 +const static uint64_t SH_FLD_IN_ECC_CE_ERROR = 9365; // 2 +const static uint64_t SH_FLD_IN_ECC_SUE_ERROR = 9366; // 2 +const static uint64_t SH_FLD_IN_ECC_UE_ERROR = 9367; // 2 +const static uint64_t SH_FLD_IN_LEN = 9368; // 264 +const static uint64_t SH_FLD_IN_LOGIC_HW_ERROR = 9369; // 2 +const static uint64_t SH_FLD_IN_MASTER_MODE = 9370; // 43 +const static uint64_t SH_FLD_IN_PARITY_ERROR = 9371; // 2 +const static uint64_t SH_FLD_IN_PROG = 9372; // 1 +const static uint64_t SH_FLD_IN_PROG_LEN = 9373; // 1 +const static uint64_t SH_FLD_IN_SEQ_ERR = 9374; // 2 +const static uint64_t SH_FLD_IN_SEQ_PERR = 9375; // 2 +const static uint64_t SH_FLD_IN_SLAVE_MODE = 9376; // 43 +const static uint64_t SH_FLD_IN_SNP_ADDR_PERR = 9377; // 2 +const static uint64_t SH_FLD_IN_SNP_TTAG_PERR = 9378; // 2 +const static uint64_t SH_FLD_IN_SW_CAST_ERROR = 9379; // 2 +const static uint64_t SH_FLD_IN_TIMEOUT = 9380; // 2 +const static uint64_t SH_FLD_IN_TRACE_GROUP_SEL_HI = 9381; // 1 +const static uint64_t SH_FLD_IN_TRACE_GROUP_SEL_HI_LEN = 9382; // 1 +const static uint64_t SH_FLD_IN_TRACE_GROUP_SEL_LO = 9383; // 1 +const static uint64_t SH_FLD_IN_TRACE_GROUP_SEL_LO_LEN = 9384; // 1 +const static uint64_t SH_FLD_IN_TRACE_INT_DATA_HI = 9385; // 1 +const static uint64_t SH_FLD_IN_TRACE_INT_DATA_LO = 9386; // 1 +const static uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_01 = 9387; // 1 +const static uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_01_LEN = 9388; // 1 +const static uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_23 = 9389; // 1 +const static uint64_t SH_FLD_IN_TRACE_TRIGGER_SEL_23_LEN = 9390; // 1 +const static uint64_t SH_FLD_IOCLK_SLIP = 9391; // 72 +const static uint64_t SH_FLD_IOCLK_SLIP_LEN = 9392; // 72 +const static uint64_t SH_FLD_IOCLK_SLIP_STROBE = 9393; // 72 +const static uint64_t SH_FLD_IODA_ADDR_PERR_ESR = 9394; // 1 +const static uint64_t SH_FLD_IOE01_IS_LOGICAL_PAIR = 9395; // 1 +const static uint64_t SH_FLD_IOE23_IS_LOGICAL_PAIR = 9396; // 1 +const static uint64_t SH_FLD_IOE45_IS_LOGICAL_PAIR = 9397; // 1 +const static uint64_t SH_FLD_IOO01_IS_LOGICAL_PAIR = 9398; // 1 +const static uint64_t SH_FLD_IOO23_IS_LOGICAL_PAIR = 9399; // 1 +const static uint64_t SH_FLD_IOO45_IS_LOGICAL_PAIR = 9400; // 1 +const static uint64_t SH_FLD_IOO67_IS_LOGICAL_PAIR = 9401; // 1 +const static uint64_t SH_FLD_IORESET = 9402; // 107 +const static uint64_t SH_FLD_IORESET_HARD_BUS0 = 9403; // 4 +const static uint64_t SH_FLD_IORESET_HARD_BUS0_LEN = 9404; // 4 +const static uint64_t SH_FLD_IOVALID = 9405; // 1 +const static uint64_t SH_FLD_IOVALID_10D = 9406; // 35 +const static uint64_t SH_FLD_IOVALID_11D = 9407; // 35 +const static uint64_t SH_FLD_IOVALID_4D = 9408; // 31 +const static uint64_t SH_FLD_IOVALID_5D = 9409; // 32 +const static uint64_t SH_FLD_IOVALID_6D = 9410; // 35 +const static uint64_t SH_FLD_IOVALID_7D = 9411; // 35 +const static uint64_t SH_FLD_IOVALID_8D = 9412; // 35 +const static uint64_t SH_FLD_IOVALID_9D = 9413; // 35 +const static uint64_t SH_FLD_IP = 9414; // 4 +const static uint64_t SH_FLD_IPB = 9415; // 1 +const static uint64_t SH_FLD_IPB_LEN = 9416; // 1 +const static uint64_t SH_FLD_IPI = 9417; // 1 +const static uint64_t SH_FLD_IPI0_HI_PRIORITY = 9418; // 1 +const static uint64_t SH_FLD_IPI0_LO_PRIORITY = 9419; // 1 +const static uint64_t SH_FLD_IPI1_HI_PRIORITY = 9420; // 1 +const static uint64_t SH_FLD_IPI1_LO_PRIORITY = 9421; // 1 +const static uint64_t SH_FLD_IPI2_HI_PRIORITY = 9422; // 1 +const static uint64_t SH_FLD_IPI2_LO_PRIORITY = 9423; // 1 +const static uint64_t SH_FLD_IPI3_HI_PRIORITY = 9424; // 1 +const static uint64_t SH_FLD_IPI3_LO_PRIORITY = 9425; // 1 +const static uint64_t SH_FLD_IPI4_HI_PRIORITY = 9426; // 1 +const static uint64_t SH_FLD_IPI4_LO_PRIORITY = 9427; // 1 +const static uint64_t SH_FLD_IPI_LEN = 9428; // 1 +const static uint64_t SH_FLD_IPI_PRIORITY = 9429; // 1 +const static uint64_t SH_FLD_IPI_PRIORITY_LEN = 9430; // 1 +const static uint64_t SH_FLD_IPI_RSD = 9431; // 1 +const static uint64_t SH_FLD_IPI_RSD_LEN = 9432; // 1 +const static uint64_t SH_FLD_IPOLL_0 = 9433; // 1 +const static uint64_t SH_FLD_IPOLL_1 = 9434; // 1 +const static uint64_t SH_FLD_IPOLL_2 = 9435; // 1 +const static uint64_t SH_FLD_IPOLL_3 = 9436; // 1 +const static uint64_t SH_FLD_IPOLL_4 = 9437; // 1 +const static uint64_t SH_FLD_IPOLL_5 = 9438; // 1 +const static uint64_t SH_FLD_IPW_SIDEAB_SEL = 9439; // 8 +const static uint64_t SH_FLD_IPW_WR_WR = 9440; // 8 +const static uint64_t SH_FLD_IPW_WR_WR_LEN = 9441; // 8 +const static uint64_t SH_FLD_IQSPD_CFG = 9442; // 4 +const static uint64_t SH_FLD_IQSPD_CFG_LEN = 9443; // 4 +const static uint64_t SH_FLD_IR = 9444; // 21 +const static uint64_t SH_FLD_IREF_BYPASS = 9445; // 2 +const static uint64_t SH_FLD_IREF_PDWN_B = 9446; // 2 +const static uint64_t SH_FLD_IREF_RES_DAC = 9447; // 2 +const static uint64_t SH_FLD_IREF_RES_DAC_LEN = 9448; // 2 +const static uint64_t SH_FLD_IRQ = 9449; // 1 +const static uint64_t SH_FLD_IRQ_LEN = 9450; // 1 +const static uint64_t SH_FLD_IRQ_TRACE_ENABLE = 9451; // 1 +const static uint64_t SH_FLD_IR_DR_EQ0_ERR = 9452; // 1 +const static uint64_t SH_FLD_IR_LEN = 9453; // 21 +const static uint64_t SH_FLD_IS = 9454; // 8 +const static uint64_t SH_FLD_IS_ACTIVE_MASTER = 9455; // 1 +const static uint64_t SH_FLD_IS_BACKUP_MASTER = 9456; // 1 +const static uint64_t SH_FLD_IS_LEN = 9457; // 8 +const static uint64_t SH_FLD_IS_PRIMARY = 9458; // 1 +const static uint64_t SH_FLD_IS_RUNNING = 9459; // 2 +const static uint64_t SH_FLD_IS_SECONDARY = 9460; // 1 +const static uint64_t SH_FLD_IS_SLAVE = 9461; // 1 +const static uint64_t SH_FLD_IS_SPECIAL = 9462; // 1 +const static uint64_t SH_FLD_ITUNE = 9463; // 4 +const static uint64_t SH_FLD_ITUNE_LEN = 9464; // 4 +const static uint64_t SH_FLD_IVC = 9465; // 1 +const static uint64_t SH_FLD_IVC_INTF_DISABLE = 9466; // 6 +const static uint64_t SH_FLD_IVC_LEN = 9467; // 1 +const static uint64_t SH_FLD_IVE_BLOCK = 9468; // 1 +const static uint64_t SH_FLD_IVE_BLOCK_LEN = 9469; // 1 +const static uint64_t SH_FLD_IVE_INDEX = 9470; // 1 +const static uint64_t SH_FLD_IVE_INDEX_LEN = 9471; // 1 +const static uint64_t SH_FLD_IVPR = 9472; // 5 +const static uint64_t SH_FLD_IVPR_LEN = 9473; // 5 +const static uint64_t SH_FLD_IVRM_BYPASS_B = 9474; // 30 +const static uint64_t SH_FLD_IVRM_ENABLED_HISTORY = 9475; // 6 +const static uint64_t SH_FLD_IVRM_IVID = 9476; // 30 +const static uint64_t SH_FLD_IVRM_IVID_LEN = 9477; // 30 +const static uint64_t SH_FLD_IVRM_LOCAL_CONTROL = 9478; // 24 +const static uint64_t SH_FLD_IVRM_PFET_STRENGTH_CACHE = 9479; // 30 +const static uint64_t SH_FLD_IVRM_PFET_STRENGTH_CACHE_LEN = 9480; // 30 +const static uint64_t SH_FLD_IVRM_PFET_STRENGTH_CORE = 9481; // 30 +const static uint64_t SH_FLD_IVRM_PFET_STRENGTH_CORE_LEN = 9482; // 30 +const static uint64_t SH_FLD_IVRM_POWERON = 9483; // 30 +const static uint64_t SH_FLD_IVRM_PVREF_ERROR = 9484; // 1 +const static uint64_t SH_FLD_IVRM_UREG_TEST_EN = 9485; // 24 +const static uint64_t SH_FLD_IVRM_UREG_TEST_ID = 9486; // 24 +const static uint64_t SH_FLD_IVRM_UREG_TEST_ID_LEN = 9487; // 24 +const static uint64_t SH_FLD_IVRM_VID_DONE = 9488; // 30 +const static uint64_t SH_FLD_IVRM_VID_VALID = 9489; // 30 +const static uint64_t SH_FLD_IVRM_VREG_SLOW_DC = 9490; // 30 +const static uint64_t SH_FLD_I_DELAY_ADJUST_RATIO = 9491; // 1 +const static uint64_t SH_FLD_I_DELAY_ADJUST_RATIO_LEN = 9492; // 1 +const static uint64_t SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT = 9493; // 1 +const static uint64_t SH_FLD_I_PATH_CORE_SYNC_PERIOD_SELECT_LEN = 9494; // 1 +const static uint64_t SH_FLD_I_PATH_DELAY_ADJUST = 9495; // 1 +const static uint64_t SH_FLD_I_PATH_DELAY_STEP_CHECK_PARITY = 9496; // 4 +const static uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD = 9497; // 1 +const static uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE = 9498; // 1 +const static uint64_t SH_FLD_I_PATH_DELAY_TWOS_COMPL_LOAD_VALUE_LEN = 9499; // 1 +const static uint64_t SH_FLD_I_PATH_DELAY_VALUE = 9500; // 2 +const static uint64_t SH_FLD_I_PATH_DELAY_VALUE_LEN = 9501; // 2 +const static uint64_t SH_FLD_I_PATH_FSM_STATE_PARITY = 9502; // 4 +const static uint64_t SH_FLD_I_PATH_STATE = 9503; // 1 +const static uint64_t SH_FLD_I_PATH_STATE_LEN = 9504; // 1 +const static uint64_t SH_FLD_I_PATH_STEP_CHECK = 9505; // 4 +const static uint64_t SH_FLD_I_PATH_STEP_CHECK_CPS_DEVIATION_X_DISABLE = 9506; // 1 +const static uint64_t SH_FLD_I_PATH_STEP_CHECK_VALID = 9507; // 1 +const static uint64_t SH_FLD_I_PATH_SYNC_CHECK = 9508; // 4 +const static uint64_t SH_FLD_I_PATH_SYNC_CHECK_DISABLE = 9509; // 1 +const static uint64_t SH_FLD_I_PATH_TIME_OVERFLOW = 9510; // 3 +const static uint64_t SH_FLD_I_PATH_TIME_OVERFLOW_CORE_INTERRUPT = 9511; // 1 +const static uint64_t SH_FLD_I_PATH_TIME_PARITY = 9512; // 4 +const static uint64_t SH_FLD_JITTER_EPSILON = 9513; // 8 +const static uint64_t SH_FLD_JITTER_EPSILON_LEN = 9514; // 8 +const static uint64_t SH_FLD_JTAGACC_CERRPT = 9515; // 1 +const static uint64_t SH_FLD_JTAGACC_CERRPT_LEN = 9516; // 1 +const static uint64_t SH_FLD_JTAGACC_ERR = 9517; // 1 +const static uint64_t SH_FLD_JTAGACC_ERR_MASK = 9518; // 1 +const static uint64_t SH_FLD_JTAG_INPROG = 9519; // 1 +const static uint64_t SH_FLD_JTAG_INSTR = 9520; // 1 +const static uint64_t SH_FLD_JTAG_INSTR_LEN = 9521; // 1 +const static uint64_t SH_FLD_JTAG_SRC_SEL = 9522; // 1 +const static uint64_t SH_FLD_JTAG_TDI = 9523; // 1 +const static uint64_t SH_FLD_JTAG_TDI_LEN = 9524; // 1 +const static uint64_t SH_FLD_JTAG_TDO = 9525; // 1 +const static uint64_t SH_FLD_JTAG_TDO_LEN = 9526; // 1 +const static uint64_t SH_FLD_JTAG_TRST_B = 9527; // 1 +const static uint64_t SH_FLD_KEEP_EDRAM_ENABLED_ON = 9528; // 129 +const static uint64_t SH_FLD_KEEP_MS_MODE = 9529; // 43 +const static uint64_t SH_FLD_KPRIME = 9530; // 8 +const static uint64_t SH_FLD_L = 9531; // 8 +const static uint64_t SH_FLD_L2 = 9532; // 12 +const static uint64_t SH_FLD_L2_CORE_INTF_QUIESCE_C0 = 9533; // 12 +const static uint64_t SH_FLD_L2_CORE_INTF_QUIESCE_C1 = 9534; // 12 +const static uint64_t SH_FLD_L2_EX0_CLKGLM_ASYNC_RESET = 9535; // 6 +const static uint64_t SH_FLD_L2_EX0_CLKGLM_SEL = 9536; // 6 +const static uint64_t SH_FLD_L2_EX0_CLK_SB_OVERRIDE = 9537; // 6 +const static uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE = 9538; // 6 +const static uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_EN = 9539; // 6 +const static uint64_t SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_LEN = 9540; // 6 +const static uint64_t SH_FLD_L2_EX0_CLK_SB_SPARE0 = 9541; // 6 +const static uint64_t SH_FLD_L2_EX0_CLK_SB_STRENGTH = 9542; // 6 +const static uint64_t SH_FLD_L2_EX0_CLK_SB_STRENGTH_LEN = 9543; // 6 +const static uint64_t SH_FLD_L2_EX0_CLK_SW_OVERRIDE = 9544; // 6 +const static uint64_t SH_FLD_L2_EX0_CLK_SW_RESCLK = 9545; // 6 +const static uint64_t SH_FLD_L2_EX0_CLK_SW_RESCLK_LEN = 9546; // 6 +const static uint64_t SH_FLD_L2_EX0_CLK_SW_SPARE1 = 9547; // 6 +const static uint64_t SH_FLD_L2_EX0_CLK_SYNC = 9548; // 6 +const static uint64_t SH_FLD_L2_EX0_CLK_SYNC_DONE = 9549; // 6 +const static uint64_t SH_FLD_L2_EX0_CLK_SYNC_ENABLE = 9550; // 6 +const static uint64_t SH_FLD_L2_EX1_CLKGLM_ASYNC_RESET = 9551; // 6 +const static uint64_t SH_FLD_L2_EX1_CLKGLM_SEL = 9552; // 6 +const static uint64_t SH_FLD_L2_EX1_CLK_SB_OVERRIDE = 9553; // 6 +const static uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE = 9554; // 6 +const static uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_EN = 9555; // 6 +const static uint64_t SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_LEN = 9556; // 6 +const static uint64_t SH_FLD_L2_EX1_CLK_SB_SPARE0 = 9557; // 6 +const static uint64_t SH_FLD_L2_EX1_CLK_SB_STRENGTH = 9558; // 6 +const static uint64_t SH_FLD_L2_EX1_CLK_SB_STRENGTH_LEN = 9559; // 6 +const static uint64_t SH_FLD_L2_EX1_CLK_SW_OVERRIDE = 9560; // 6 +const static uint64_t SH_FLD_L2_EX1_CLK_SW_RESCLK = 9561; // 6 +const static uint64_t SH_FLD_L2_EX1_CLK_SW_RESCLK_LEN = 9562; // 6 +const static uint64_t SH_FLD_L2_EX1_CLK_SW_SPARE1 = 9563; // 6 +const static uint64_t SH_FLD_L2_EX1_CLK_SYNC = 9564; // 6 +const static uint64_t SH_FLD_L2_EX1_CLK_SYNC_DONE = 9565; // 6 +const static uint64_t SH_FLD_L2_EX1_CLK_SYNC_ENABLE = 9566; // 6 +const static uint64_t SH_FLD_L2_LEN = 9567; // 12 +const static uint64_t SH_FLD_L2_PURGE = 9568; // 12 +const static uint64_t SH_FLD_L2_PURGE_ABORT = 9569; // 12 +const static uint64_t SH_FLD_L2_PURGE_DONE = 9570; // 24 +const static uint64_t SH_FLD_L2_STEP_MODE = 9571; // 12 +const static uint64_t SH_FLD_L2_STEP_MODE_LEN = 9572; // 12 +const static uint64_t SH_FLD_L2_STOPPED = 9573; // 1 +const static uint64_t SH_FLD_L2_STOPPED_LEN = 9574; // 1 +const static uint64_t SH_FLD_L3 = 9575; // 24 +const static uint64_t SH_FLD_L3CERRS_CFG_DCACHE_CAPP = 9576; // 12 +const static uint64_t SH_FLD_L3CERRS_LCO_RETRY_THROTL_DIS = 9577; // 12 +const static uint64_t SH_FLD_L3CICTL_CI_OVERRUN_CK = 9578; // 12 +const static uint64_t SH_FLD_L3CORTR_NO_LCO_TGTS = 9579; // 12 +const static uint64_t SH_FLD_L3L2CTL_PF_OVERRUN_CK = 9580; // 12 +const static uint64_t SH_FLD_L3L2CTL_RD_OVERRUN_CK = 9581; // 12 +const static uint64_t SH_FLD_L3PBEXCA0_OVERFLOW = 9582; // 12 +const static uint64_t SH_FLD_L3PBEXCA0_UNDERFLOW = 9583; // 12 +const static uint64_t SH_FLD_L3PBEXCA1_OVERFLOW = 9584; // 12 +const static uint64_t SH_FLD_L3PBEXCA1_UNDERFLOW = 9585; // 12 +const static uint64_t SH_FLD_L3SDRTL0_BAD_HPC = 9586; // 12 +const static uint64_t SH_FLD_L3SDRTL0_CACHE_INHIBIT = 9587; // 12 +const static uint64_t SH_FLD_L3SDRTL1_BAD_HPC = 9588; // 12 +const static uint64_t SH_FLD_L3SDRTL1_CACHE_INHIBIT = 9589; // 12 +const static uint64_t SH_FLD_L3SDRTL2_BAD_HPC = 9590; // 12 +const static uint64_t SH_FLD_L3SDRTL2_CACHE_INHIBIT = 9591; // 12 +const static uint64_t SH_FLD_L3SDRTL3_BAD_HPC = 9592; // 12 +const static uint64_t SH_FLD_L3SDRTL3_CACHE_INHIBIT = 9593; // 12 +const static uint64_t SH_FLD_L3XMEMA0_CRW_DIR_HIT = 9594; // 12 +const static uint64_t SH_FLD_L3XMEMA0_DW_DIR_HIT = 9595; // 12 +const static uint64_t SH_FLD_L3XMEMA1_CRW_DIR_HIT = 9596; // 12 +const static uint64_t SH_FLD_L3XMEMA1_DW_DIR_HIT = 9597; // 12 +const static uint64_t SH_FLD_L3_1ST_BEAT_SYNDROME = 9598; // 12 +const static uint64_t SH_FLD_L3_1ST_BEAT_SYNDROME_LEN = 9599; // 12 +const static uint64_t SH_FLD_L3_1ST_BEAT_UE = 9600; // 12 +const static uint64_t SH_FLD_L3_2ND_BEAT_SYNDROME = 9601; // 12 +const static uint64_t SH_FLD_L3_2ND_BEAT_SYNDROME_LEN = 9602; // 12 +const static uint64_t SH_FLD_L3_2ND_BEAT_UE = 9603; // 12 +const static uint64_t SH_FLD_L3_ABORT = 9604; // 12 +const static uint64_t SH_FLD_L3_ADDR_HANG_DETECTED = 9605; // 12 +const static uint64_t SH_FLD_L3_ADDR_HASH_EN_CFG = 9606; // 12 +const static uint64_t SH_FLD_L3_ALL_MEMBERS_DELETED_ERROR = 9607; // 12 +const static uint64_t SH_FLD_L3_BANK = 9608; // 12 +const static uint64_t SH_FLD_L3_BANK_LEN = 9609; // 12 +const static uint64_t SH_FLD_L3_BUSY_ERR = 9610; // 36 +const static uint64_t SH_FLD_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ = 9611; // 12 +const static uint64_t SH_FLD_L3_CAC_RD_SUE_DET = 9612; // 12 +const static uint64_t SH_FLD_L3_CAC_RD_UE_DET = 9613; // 12 +const static uint64_t SH_FLD_L3_CAC_TYPE = 9614; // 12 +const static uint64_t SH_FLD_L3_CAC_TYPE_LEN = 9615; // 12 +const static uint64_t SH_FLD_L3_CAC_WR_DATA_CE_FROM_L2 = 9616; // 12 +const static uint64_t SH_FLD_L3_CAC_WR_DATA_CE_FROM_PB = 9617; // 12 +const static uint64_t SH_FLD_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC = 9618; // 12 +const static uint64_t SH_FLD_L3_CAC_WR_DATA_SUE_FROM_PB = 9619; // 12 +const static uint64_t SH_FLD_L3_CAC_WR_DATA_UE_FROM_L2 = 9620; // 12 +const static uint64_t SH_FLD_L3_CAC_WR_DATA_UE_FROM_PB = 9621; // 12 +const static uint64_t SH_FLD_L3_CFG = 9622; // 36 +const static uint64_t SH_FLD_L3_CFG_LEN = 9623; // 12 +const static uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE = 9624; // 6 +const static uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE_EN = 9625; // 6 +const static uint64_t SH_FLD_L3_CLK_SB_PULSE_MODE_LEN = 9626; // 6 +const static uint64_t SH_FLD_L3_CLK_SB_SPARE0 = 9627; // 6 +const static uint64_t SH_FLD_L3_CLK_SB_STRENGTH = 9628; // 6 +const static uint64_t SH_FLD_L3_CLK_SB_STRENGTH_LEN = 9629; // 6 +const static uint64_t SH_FLD_L3_COLUMN_MD_CFG = 9630; // 12 +const static uint64_t SH_FLD_L3_COLUMN_MD_CFG_LEN = 9631; // 12 +const static uint64_t SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG = 9632; // 12 +const static uint64_t SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG_LEN = 9633; // 12 +const static uint64_t SH_FLD_L3_CP_UTIL_EN_DC = 9634; // 12 +const static uint64_t SH_FLD_L3_CP_UTIL_EXT_SEL = 9635; // 12 +const static uint64_t SH_FLD_L3_CP_UTIL_EXT_SEL_LEN = 9636; // 12 +const static uint64_t SH_FLD_L3_CP_UTIL_SEL_DC = 9637; // 12 +const static uint64_t SH_FLD_L3_CP_UTIL_SEL_DC_LEN = 9638; // 12 +const static uint64_t SH_FLD_L3_DATA_POLL_PULSE_DIV = 9639; // 12 +const static uint64_t SH_FLD_L3_DATA_POLL_PULSE_DIV_LEN = 9640; // 12 +const static uint64_t SH_FLD_L3_DIR_ADDR = 9641; // 24 +const static uint64_t SH_FLD_L3_DIR_ADDR_LEN = 9642; // 24 +const static uint64_t SH_FLD_L3_DIR_RD_CE_DET = 9643; // 12 +const static uint64_t SH_FLD_L3_DIR_RD_PHANTOM_ERROR = 9644; // 12 +const static uint64_t SH_FLD_L3_DIR_RD_UE_DET = 9645; // 12 +const static uint64_t SH_FLD_L3_DIR_TYPE = 9646; // 12 +const static uint64_t SH_FLD_L3_DISABLED_CFG = 9647; // 12 +const static uint64_t SH_FLD_L3_DMAP_CI_EN_CFG = 9648; // 12 +const static uint64_t SH_FLD_L3_DRAM_ERROR = 9649; // 12 +const static uint64_t SH_FLD_L3_DRAM_POS_WORDLINE_FAIL = 9650; // 12 +const static uint64_t SH_FLD_L3_DW = 9651; // 12 +const static uint64_t SH_FLD_L3_DW_LEN = 9652; // 12 +const static uint64_t SH_FLD_L3_DYN_LCO_BLK_DIS_CFG = 9653; // 12 +const static uint64_t SH_FLD_L3_EDRAM_ENABLE0 = 9654; // 43 +const static uint64_t SH_FLD_L3_EDRAM_ENABLE1 = 9655; // 43 +const static uint64_t SH_FLD_L3_EDRAM_PGATE_ERR = 9656; // 6 +const static uint64_t SH_FLD_L3_EDRAM_SEQ_ERR = 9657; // 6 +const static uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ACTUAL = 9658; // 6 +const static uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ACTUAL_LEN = 9659; // 6 +const static uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ENCODE = 9660; // 6 +const static uint64_t SH_FLD_L3_EX0_EDRAM_ENABLE_ENCODE_LEN = 9661; // 6 +const static uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ACTUAL = 9662; // 6 +const static uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ACTUAL_LEN = 9663; // 6 +const static uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ENCODE = 9664; // 6 +const static uint64_t SH_FLD_L3_EX1_EDRAM_ENABLE_ENCODE_LEN = 9665; // 6 +const static uint64_t SH_FLD_L3_HANG_POLL_PULSE_DIV = 9666; // 12 +const static uint64_t SH_FLD_L3_HANG_POLL_PULSE_DIV_LEN = 9667; // 12 +const static uint64_t SH_FLD_L3_HW_CONTROL_ERR = 9668; // 12 +const static uint64_t SH_FLD_L3_IS_ECO_CFG = 9669; // 12 +const static uint64_t SH_FLD_L3_LCO_ADDR_TGT_ENABLE = 9670; // 12 +const static uint64_t SH_FLD_L3_LCO_ENABLE_CFG = 9671; // 12 +const static uint64_t SH_FLD_L3_LCO_RTY_LIMIT_DISABLE = 9672; // 12 +const static uint64_t SH_FLD_L3_LCO_TARGET_GROUP = 9673; // 12 +const static uint64_t SH_FLD_L3_LCO_TARGET_ID = 9674; // 12 +const static uint64_t SH_FLD_L3_LCO_TARGET_ID_LEN = 9675; // 12 +const static uint64_t SH_FLD_L3_LCO_TARGET_VICTIMS = 9676; // 12 +const static uint64_t SH_FLD_L3_LCO_TARGET_VICTIMS_LEN = 9677; // 12 +const static uint64_t SH_FLD_L3_LEN = 9678; // 24 +const static uint64_t SH_FLD_L3_LINE_DEL_CE_DONE = 9679; // 12 +const static uint64_t SH_FLD_L3_LINE_DEL_ON_ALL_CE = 9680; // 24 +const static uint64_t SH_FLD_L3_LINE_DEL_ON_NEXT_CE = 9681; // 24 +const static uint64_t SH_FLD_L3_LRU_ERROR = 9682; // 12 +const static uint64_t SH_FLD_L3_LRU_INVAL_CNT = 9683; // 12 +const static uint64_t SH_FLD_L3_MACH_HANG_DETECTED = 9684; // 12 +const static uint64_t SH_FLD_L3_MEMBER = 9685; // 24 +const static uint64_t SH_FLD_L3_MEMBER_LEN = 9686; // 24 +const static uint64_t SH_FLD_L3_NO_ALLOCATE_ACTIVE = 9687; // 12 +const static uint64_t SH_FLD_L3_NO_ALLOCATE_EN = 9688; // 12 +const static uint64_t SH_FLD_L3_PB_MAST_RD_ACK_DEAD = 9689; // 12 +const static uint64_t SH_FLD_L3_PB_MAST_RD_ADDR_ERR = 9690; // 12 +const static uint64_t SH_FLD_L3_PB_MAST_WR_ACK_DEAD = 9691; // 12 +const static uint64_t SH_FLD_L3_PB_MAST_WR_ADDR_ERR = 9692; // 12 +const static uint64_t SH_FLD_L3_PPE_RD_CE_DET = 9693; // 12 +const static uint64_t SH_FLD_L3_PPE_RD_SUE_DET = 9694; // 12 +const static uint64_t SH_FLD_L3_PPE_RD_UE_DET = 9695; // 12 +const static uint64_t SH_FLD_L3_RA = 9696; // 12 +const static uint64_t SH_FLD_L3_RA_LEN = 9697; // 12 +const static uint64_t SH_FLD_L3_RDSN_LINEDEL_UE_EN = 9698; // 12 +const static uint64_t SH_FLD_L3_REFRESH_TIMER_ERROR = 9699; // 12 +const static uint64_t SH_FLD_L3_REQ = 9700; // 36 +const static uint64_t SH_FLD_L3_SCOM_CINJ_LCO_DIS = 9701; // 12 +const static uint64_t SH_FLD_L3_SCOM_INIT = 9702; // 12 +const static uint64_t SH_FLD_L3_SCOM_QUIESCE_CACHE = 9703; // 12 +const static uint64_t SH_FLD_L3_SCOM_QUIESCE_CACHE_LFSR = 9704; // 12 +const static uint64_t SH_FLD_L3_SCOM_QUIESCE_REFRESH = 9705; // 12 +const static uint64_t SH_FLD_L3_SINGLE_CAC = 9706; // 12 +const static uint64_t SH_FLD_L3_SINGLE_DIR = 9707; // 12 +const static uint64_t SH_FLD_L3_SINGLE_LRU = 9708; // 12 +const static uint64_t SH_FLD_L3_SNP_CACHE_INHIBIT_ERR = 9709; // 12 +const static uint64_t SH_FLD_L3_SOLID_CAC = 9710; // 12 +const static uint64_t SH_FLD_L3_SOLID_DIR = 9711; // 12 +const static uint64_t SH_FLD_L3_SOLID_LRU = 9712; // 12 +const static uint64_t SH_FLD_L3_SPARE3 = 9713; // 12 +const static uint64_t SH_FLD_L3_SPARE5 = 9714; // 12 +const static uint64_t SH_FLD_L3_SPARE7 = 9715; // 12 +const static uint64_t SH_FLD_L3_STOPPED = 9716; // 1 +const static uint64_t SH_FLD_L3_STOPPED_LEN = 9717; // 1 +const static uint64_t SH_FLD_L3_SYSMAP_SM_NOT_LG_SEL = 9718; // 12 +const static uint64_t SH_FLD_L3_TIMER_DIVIDE_MAJOR = 9719; // 12 +const static uint64_t SH_FLD_L3_TIMER_DIVIDE_MAJOR_LEN = 9720; // 12 +const static uint64_t SH_FLD_L3_TIMER_DIVIDE_MINOR = 9721; // 12 +const static uint64_t SH_FLD_L3_TIMER_DIVIDE_MINOR_LEN = 9722; // 12 +const static uint64_t SH_FLD_L3_TTYPE = 9723; // 24 +const static uint64_t SH_FLD_L3_TTYPE_LEN = 9724; // 24 +const static uint64_t SH_FLD_L3_UTIL_MON_BITS = 9725; // 12 +const static uint64_t SH_FLD_L3_UTIL_MON_BITS_LEN = 9726; // 12 +const static uint64_t SH_FLD_L3_VAL = 9727; // 12 +const static uint64_t SH_FLD_LANE_ANA_PDWN = 9728; // 120 +const static uint64_t SH_FLD_LANE_BAD_VEC_0_15 = 9729; // 4 +const static uint64_t SH_FLD_LANE_BAD_VEC_0_15_LEN = 9730; // 4 +const static uint64_t SH_FLD_LANE_BAD_VEC_16_23 = 9731; // 4 +const static uint64_t SH_FLD_LANE_BAD_VEC_16_23_LEN = 9732; // 4 +const static uint64_t SH_FLD_LANE_BIST_ACTVITY_DET = 9733; // 116 +const static uint64_t SH_FLD_LANE_BIST_ERR = 9734; // 116 +const static uint64_t SH_FLD_LANE_DIG_PDWN = 9735; // 120 +const static uint64_t SH_FLD_LANE_DISABLED = 9736; // 48 +const static uint64_t SH_FLD_LANE_DISABLED_VEC_0_15 = 9737; // 8 +const static uint64_t SH_FLD_LANE_DISABLED_VEC_0_15_LEN = 9738; // 8 +const static uint64_t SH_FLD_LANE_DISABLED_VEC_16_23 = 9739; // 8 +const static uint64_t SH_FLD_LANE_DISABLED_VEC_16_23_LEN = 9740; // 8 +const static uint64_t SH_FLD_LANE_INVALID = 9741; // 72 +const static uint64_t SH_FLD_LANE_INVERT = 9742; // 190 +const static uint64_t SH_FLD_LANE_PDWN = 9743; // 116 +const static uint64_t SH_FLD_LANE_QUIESCE = 9744; // 117 +const static uint64_t SH_FLD_LANE_QUIESCE_LEN = 9745; // 117 +const static uint64_t SH_FLD_LANE_SCRAMBLE_DISABLE = 9746; // 140 +const static uint64_t SH_FLD_LAST_BANK = 9747; // 90 +const static uint64_t SH_FLD_LAST_BANK_LEN = 9748; // 90 +const static uint64_t SH_FLD_LAST_BANK_VALID = 9749; // 90 +const static uint64_t SH_FLD_LAST_OPCG_MODE = 9750; // 43 +const static uint64_t SH_FLD_LAST_OPCG_MODE_LEN = 9751; // 43 +const static uint64_t SH_FLD_LATCANCEL = 9752; // 15 +const static uint64_t SH_FLD_LATCANCEL_LEN = 9753; // 15 +const static uint64_t SH_FLD_LATENCY = 9754; // 6 +const static uint64_t SH_FLD_LATENCY_LEN = 9755; // 6 +const static uint64_t SH_FLD_LATE_LAUNCH_PRIMARY = 9756; // 1 +const static uint64_t SH_FLD_LATE_LAUNCH_SECONDARY = 9757; // 1 +const static uint64_t SH_FLD_LATFINISH = 9758; // 15 +const static uint64_t SH_FLD_LATFINISH_LEN = 9759; // 15 +const static uint64_t SH_FLD_LATSTART = 9760; // 15 +const static uint64_t SH_FLD_LATSTART_LEN = 9761; // 15 +const static uint64_t SH_FLD_LAT_THRESHA = 9762; // 8 +const static uint64_t SH_FLD_LAT_THRESHA_LEN = 9763; // 8 +const static uint64_t SH_FLD_LAT_THRESHB = 9764; // 8 +const static uint64_t SH_FLD_LAT_THRESHB_LEN = 9765; // 8 +const static uint64_t SH_FLD_LAT_THRESHC = 9766; // 8 +const static uint64_t SH_FLD_LAT_THRESHC_LEN = 9767; // 8 +const static uint64_t SH_FLD_LBIST = 9768; // 43 +const static uint64_t SH_FLD_LBIST_SKITTER_CTL = 9769; // 43 +const static uint64_t SH_FLD_LBIST_SKITTER_CTL_LEN = 9770; // 43 +const static uint64_t SH_FLD_LBUS_CLOCK_DIVIDER = 9771; // 2 +const static uint64_t SH_FLD_LBUS_CLOCK_DIVIDER_LEN = 9772; // 2 +const static uint64_t SH_FLD_LBUS_PARITY_ERR1_0 = 9773; // 12 +const static uint64_t SH_FLD_LBUS_PARITY_ERR1_1 = 9774; // 12 +const static uint64_t SH_FLD_LBUS_PARITY_ERR1_2 = 9775; // 12 +const static uint64_t SH_FLD_LBUS_PARITY_ERR1_3 = 9776; // 12 +const static uint64_t SH_FLD_LBUS_PARITY_ERROR_0 = 9777; // 4 +const static uint64_t SH_FLD_LBUS_PARITY_ERROR_1 = 9778; // 2 +const static uint64_t SH_FLD_LBUS_PARITY_ERROR_2 = 9779; // 2 +const static uint64_t SH_FLD_LBUS_PARITY_ERROR_3 = 9780; // 2 +const static uint64_t SH_FLD_LCK_STATUS_PARITY_ERROR = 9781; // 3 +const static uint64_t SH_FLD_LCL_FIRST_GRPSCAN_ENA = 9782; // 1 +const static uint64_t SH_FLD_LCL_FIRST_GRPSCAN_RMT_ENA = 9783; // 1 +const static uint64_t SH_FLD_LCO_CRED_MASK = 9784; // 1 +const static uint64_t SH_FLD_LCO_CRED_MASK_LEN = 9785; // 1 +const static uint64_t SH_FLD_LCO_TARG_CONFIG = 9786; // 1 +const static uint64_t SH_FLD_LCO_TARG_CONFIG_LEN = 9787; // 1 +const static uint64_t SH_FLD_LCO_TARG_MIN = 9788; // 1 +const static uint64_t SH_FLD_LCO_TARG_MIN_LEN = 9789; // 1 +const static uint64_t SH_FLD_LD = 9790; // 96 +const static uint64_t SH_FLD_LDQ_DATA_HANG = 9791; // 1 +const static uint64_t SH_FLD_LDQ_EQD_MAX_0_4 = 9792; // 1 +const static uint64_t SH_FLD_LDQ_EQD_MAX_0_4_LEN = 9793; // 1 +const static uint64_t SH_FLD_LDQ_EQD_MIN_0_4 = 9794; // 1 +const static uint64_t SH_FLD_LDQ_EQD_MIN_0_4_LEN = 9795; // 1 +const static uint64_t SH_FLD_LDQ_FSM_PERR = 9796; // 1 +const static uint64_t SH_FLD_LDQ_IVE_MAX_0_4 = 9797; // 1 +const static uint64_t SH_FLD_LDQ_IVE_MAX_0_4_LEN = 9798; // 1 +const static uint64_t SH_FLD_LDQ_IVE_MIN_0_4 = 9799; // 1 +const static uint64_t SH_FLD_LDQ_IVE_MIN_0_4_LEN = 9800; // 1 +const static uint64_t SH_FLD_LDQ_REG_MAX_0_4 = 9801; // 1 +const static uint64_t SH_FLD_LDQ_REG_MAX_0_4_LEN = 9802; // 1 +const static uint64_t SH_FLD_LDQ_REG_MIN_0_4 = 9803; // 1 +const static uint64_t SH_FLD_LDQ_REG_MIN_0_4_LEN = 9804; // 1 +const static uint64_t SH_FLD_LDQ_REG_ORDER_ALL = 9805; // 1 +const static uint64_t SH_FLD_LDQ_THR_MAX_0_4 = 9806; // 1 +const static uint64_t SH_FLD_LDQ_THR_MAX_0_4_LEN = 9807; // 1 +const static uint64_t SH_FLD_LDQ_THR_MIN_0_4 = 9808; // 1 +const static uint64_t SH_FLD_LDQ_THR_MIN_0_4_LEN = 9809; // 1 +const static uint64_t SH_FLD_LDQ_VPC_MAX_0_4 = 9810; // 1 +const static uint64_t SH_FLD_LDQ_VPC_MAX_0_4_LEN = 9811; // 1 +const static uint64_t SH_FLD_LDQ_VPC_MIN_0_4 = 9812; // 1 +const static uint64_t SH_FLD_LDQ_VPC_MIN_0_4_LEN = 9813; // 1 +const static uint64_t SH_FLD_LD_ACK_DEAD = 9814; // 12 +const static uint64_t SH_FLD_LD_ADDR_ERR = 9815; // 12 +const static uint64_t SH_FLD_LD_CLASS_CMD_ADDR_ERR = 9816; // 4 +const static uint64_t SH_FLD_LD_CLASS_CMD_FOREIGN_LINK_FAIL = 9817; // 4 +const static uint64_t SH_FLD_LD_ECC_CE = 9818; // 1 +const static uint64_t SH_FLD_LD_ECC_UE = 9819; // 1 +const static uint64_t SH_FLD_LD_UNLD_DLY = 9820; // 1 +const static uint64_t SH_FLD_LD_UNLD_DLY_LEN = 9821; // 1 +const static uint64_t SH_FLD_LENGTH_IN_BYTES_0 = 9822; // 2 +const static uint64_t SH_FLD_LENGTH_IN_BYTES_0_LEN = 9823; // 2 +const static uint64_t SH_FLD_LENGTH_IN_BYTES_1 = 9824; // 1 +const static uint64_t SH_FLD_LENGTH_IN_BYTES_1_LEN = 9825; // 1 +const static uint64_t SH_FLD_LENGTH_IN_BYTES_2 = 9826; // 1 +const static uint64_t SH_FLD_LENGTH_IN_BYTES_2_LEN = 9827; // 1 +const static uint64_t SH_FLD_LENGTH_IN_BYTES_3 = 9828; // 1 +const static uint64_t SH_FLD_LENGTH_IN_BYTES_3_LEN = 9829; // 1 +const static uint64_t SH_FLD_LEVEL_TRANSITION_RATE_A_N = 9830; // 96 +const static uint64_t SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN = 9831; // 96 +const static uint64_t SH_FLD_LFIR_IN = 9832; // 43 +const static uint64_t SH_FLD_LFIR_IN_LEN = 9833; // 43 +const static uint64_t SH_FLD_LFIR_RECOV_ERR = 9834; // 43 +const static uint64_t SH_FLD_LFREQ = 9835; // 1 +const static uint64_t SH_FLD_LFREQ0 = 9836; // 24 +const static uint64_t SH_FLD_LFREQ0_LEN = 9837; // 24 +const static uint64_t SH_FLD_LFREQ1 = 9838; // 24 +const static uint64_t SH_FLD_LFREQ1_LEN = 9839; // 24 +const static uint64_t SH_FLD_LFREQ_LEN = 9840; // 1 +const static uint64_t SH_FLD_LFSR_ARB_MODE = 9841; // 3 +const static uint64_t SH_FLD_LFSR_DIS = 9842; // 1 +const static uint64_t SH_FLD_LFSR_FAIRNESS_MASK = 9843; // 1 +const static uint64_t SH_FLD_LFSR_FAIRNESS_MASK_LEN = 9844; // 1 +const static uint64_t SH_FLD_LIMIT = 9845; // 2 +const static uint64_t SH_FLD_LIMIT_LEN = 9846; // 2 +const static uint64_t SH_FLD_LIM_PS = 9847; // 1 +const static uint64_t SH_FLD_LINEAR_WINDOW_BAR = 9848; // 4 +const static uint64_t SH_FLD_LINEAR_WINDOW_BAR_LEN = 9849; // 4 +const static uint64_t SH_FLD_LINEAR_WINDOW_BASE = 9850; // 4 +const static uint64_t SH_FLD_LINEAR_WINDOW_BASE_LEN = 9851; // 4 +const static uint64_t SH_FLD_LINEAR_WINDOW_ENABLE = 9852; // 4 +const static uint64_t SH_FLD_LINEAR_WINDOW_MASK = 9853; // 4 +const static uint64_t SH_FLD_LINEAR_WINDOW_MASK_LEN = 9854; // 4 +const static uint64_t SH_FLD_LINEAR_WINDOW_REGION = 9855; // 4 +const static uint64_t SH_FLD_LINEAR_WINDOW_REGION_LEN = 9856; // 4 +const static uint64_t SH_FLD_LINEAR_WINDOW_SCRESP = 9857; // 4 +const static uint64_t SH_FLD_LINEAR_WINDOW_SCRESP_LEN = 9858; // 4 +const static uint64_t SH_FLD_LINK00_HI = 9859; // 2 +const static uint64_t SH_FLD_LINK00_HI_LEN = 9860; // 2 +const static uint64_t SH_FLD_LINK00_LO = 9861; // 2 +const static uint64_t SH_FLD_LINK00_LO_LEN = 9862; // 2 +const static uint64_t SH_FLD_LINK01_CAPP_MODE = 9863; // 1 +const static uint64_t SH_FLD_LINK01_DIB_VC_LIMIT = 9864; // 2 +const static uint64_t SH_FLD_LINK01_DIB_VC_LIMIT_LEN = 9865; // 2 +const static uint64_t SH_FLD_LINK01_HI = 9866; // 2 +const static uint64_t SH_FLD_LINK01_HI_LEN = 9867; // 2 +const static uint64_t SH_FLD_LINK01_HRB_INIT_STATE = 9868; // 1 +const static uint64_t SH_FLD_LINK01_LO = 9869; // 2 +const static uint64_t SH_FLD_LINK01_LO_LEN = 9870; // 2 +const static uint64_t SH_FLD_LINK02_HI = 9871; // 2 +const static uint64_t SH_FLD_LINK02_HI_LEN = 9872; // 2 +const static uint64_t SH_FLD_LINK02_LO = 9873; // 2 +const static uint64_t SH_FLD_LINK02_LO_LEN = 9874; // 2 +const static uint64_t SH_FLD_LINK03_HI = 9875; // 2 +const static uint64_t SH_FLD_LINK03_HI_LEN = 9876; // 2 +const static uint64_t SH_FLD_LINK03_LO = 9877; // 2 +const static uint64_t SH_FLD_LINK03_LO_LEN = 9878; // 2 +const static uint64_t SH_FLD_LINK04_HI = 9879; // 2 +const static uint64_t SH_FLD_LINK04_HI_LEN = 9880; // 2 +const static uint64_t SH_FLD_LINK04_LO = 9881; // 2 +const static uint64_t SH_FLD_LINK04_LO_LEN = 9882; // 2 +const static uint64_t SH_FLD_LINK05_HI = 9883; // 2 +const static uint64_t SH_FLD_LINK05_HI_LEN = 9884; // 2 +const static uint64_t SH_FLD_LINK05_LO = 9885; // 2 +const static uint64_t SH_FLD_LINK05_LO_LEN = 9886; // 2 +const static uint64_t SH_FLD_LINK06_HI = 9887; // 1 +const static uint64_t SH_FLD_LINK06_HI_LEN = 9888; // 1 +const static uint64_t SH_FLD_LINK06_LO = 9889; // 1 +const static uint64_t SH_FLD_LINK06_LO_LEN = 9890; // 1 +const static uint64_t SH_FLD_LINK07_HI = 9891; // 1 +const static uint64_t SH_FLD_LINK07_HI_LEN = 9892; // 1 +const static uint64_t SH_FLD_LINK07_LO = 9893; // 1 +const static uint64_t SH_FLD_LINK07_LO_LEN = 9894; // 1 +const static uint64_t SH_FLD_LINK0_DOB_LIMIT = 9895; // 1 +const static uint64_t SH_FLD_LINK0_DOB_LIMIT_LEN = 9896; // 1 +const static uint64_t SH_FLD_LINK0_DOB_VC0_LIMIT = 9897; // 2 +const static uint64_t SH_FLD_LINK0_DOB_VC0_LIMIT_LEN = 9898; // 2 +const static uint64_t SH_FLD_LINK0_DOB_VC1_LIMIT = 9899; // 2 +const static uint64_t SH_FLD_LINK0_DOB_VC1_LIMIT_LEN = 9900; // 2 +const static uint64_t SH_FLD_LINK0_SPARE = 9901; // 1 +const static uint64_t SH_FLD_LINK0_SPARE_LEN = 9902; // 1 +const static uint64_t SH_FLD_LINK1_DOB_LIMIT = 9903; // 1 +const static uint64_t SH_FLD_LINK1_DOB_LIMIT_LEN = 9904; // 1 +const static uint64_t SH_FLD_LINK1_DOB_VC0_LIMIT = 9905; // 2 +const static uint64_t SH_FLD_LINK1_DOB_VC0_LIMIT_LEN = 9906; // 2 +const static uint64_t SH_FLD_LINK1_DOB_VC1_LIMIT = 9907; // 2 +const static uint64_t SH_FLD_LINK1_DOB_VC1_LIMIT_LEN = 9908; // 2 +const static uint64_t SH_FLD_LINK1_SPARE = 9909; // 1 +const static uint64_t SH_FLD_LINK1_SPARE_LEN = 9910; // 1 +const static uint64_t SH_FLD_LINK23_DIB_VC_LIMIT = 9911; // 2 +const static uint64_t SH_FLD_LINK23_DIB_VC_LIMIT_LEN = 9912; // 2 +const static uint64_t SH_FLD_LINK2_DOB_LIMIT = 9913; // 2 +const static uint64_t SH_FLD_LINK2_DOB_LIMIT_LEN = 9914; // 2 +const static uint64_t SH_FLD_LINK2_DOB_VC0_LIMIT = 9915; // 2 +const static uint64_t SH_FLD_LINK2_DOB_VC0_LIMIT_LEN = 9916; // 2 +const static uint64_t SH_FLD_LINK2_DOB_VC1_LIMIT = 9917; // 2 +const static uint64_t SH_FLD_LINK2_DOB_VC1_LIMIT_LEN = 9918; // 2 +const static uint64_t SH_FLD_LINK3_DOB_LIMIT = 9919; // 2 +const static uint64_t SH_FLD_LINK3_DOB_LIMIT_LEN = 9920; // 2 +const static uint64_t SH_FLD_LINK3_DOB_VC0_LIMIT = 9921; // 2 +const static uint64_t SH_FLD_LINK3_DOB_VC0_LIMIT_LEN = 9922; // 2 +const static uint64_t SH_FLD_LINK3_DOB_VC1_LIMIT = 9923; // 2 +const static uint64_t SH_FLD_LINK3_DOB_VC1_LIMIT_LEN = 9924; // 2 +const static uint64_t SH_FLD_LINK45_DIB_VC_LIMIT = 9925; // 2 +const static uint64_t SH_FLD_LINK45_DIB_VC_LIMIT_LEN = 9926; // 2 +const static uint64_t SH_FLD_LINK4_DOB_LIMIT = 9927; // 2 +const static uint64_t SH_FLD_LINK4_DOB_LIMIT_LEN = 9928; // 2 +const static uint64_t SH_FLD_LINK4_DOB_VC0_LIMIT = 9929; // 2 +const static uint64_t SH_FLD_LINK4_DOB_VC0_LIMIT_LEN = 9930; // 2 +const static uint64_t SH_FLD_LINK4_DOB_VC1_LIMIT = 9931; // 2 +const static uint64_t SH_FLD_LINK4_DOB_VC1_LIMIT_LEN = 9932; // 2 +const static uint64_t SH_FLD_LINK5_DOB_LIMIT = 9933; // 2 +const static uint64_t SH_FLD_LINK5_DOB_LIMIT_LEN = 9934; // 2 +const static uint64_t SH_FLD_LINK5_DOB_VC0_LIMIT = 9935; // 2 +const static uint64_t SH_FLD_LINK5_DOB_VC0_LIMIT_LEN = 9936; // 2 +const static uint64_t SH_FLD_LINK5_DOB_VC1_LIMIT = 9937; // 2 +const static uint64_t SH_FLD_LINK5_DOB_VC1_LIMIT_LEN = 9938; // 2 +const static uint64_t SH_FLD_LINK67_CAPP_MODE = 9939; // 1 +const static uint64_t SH_FLD_LINK67_DIB_VC_LIMIT = 9940; // 1 +const static uint64_t SH_FLD_LINK67_DIB_VC_LIMIT_LEN = 9941; // 1 +const static uint64_t SH_FLD_LINK67_HRB_INIT_STATE = 9942; // 1 +const static uint64_t SH_FLD_LINK6_DOB_VC0_LIMIT = 9943; // 1 +const static uint64_t SH_FLD_LINK6_DOB_VC0_LIMIT_LEN = 9944; // 1 +const static uint64_t SH_FLD_LINK6_DOB_VC1_LIMIT = 9945; // 1 +const static uint64_t SH_FLD_LINK6_DOB_VC1_LIMIT_LEN = 9946; // 1 +const static uint64_t SH_FLD_LINK6_SPARE = 9947; // 1 +const static uint64_t SH_FLD_LINK6_SPARE_LEN = 9948; // 1 +const static uint64_t SH_FLD_LINK7_DOB_VC0_LIMIT = 9949; // 1 +const static uint64_t SH_FLD_LINK7_DOB_VC0_LIMIT_LEN = 9950; // 1 +const static uint64_t SH_FLD_LINK7_DOB_VC1_LIMIT = 9951; // 1 +const static uint64_t SH_FLD_LINK7_DOB_VC1_LIMIT_LEN = 9952; // 1 +const static uint64_t SH_FLD_LINK7_SPARE = 9953; // 1 +const static uint64_t SH_FLD_LINK7_SPARE_LEN = 9954; // 1 +const static uint64_t SH_FLD_LINKS01_TOD_ENABLE = 9955; // 1 +const static uint64_t SH_FLD_LINKS23_TOD_ENABLE = 9956; // 1 +const static uint64_t SH_FLD_LINKS45_TOD_ENABLE = 9957; // 1 +const static uint64_t SH_FLD_LINKS67_TOD_ENABLE = 9958; // 1 +const static uint64_t SH_FLD_LINK_AVP_MODE = 9959; // 2 +const static uint64_t SH_FLD_LINUX_TRIG_MODE = 9960; // 1 +const static uint64_t SH_FLD_LISTEN_TO_PULSE_DIS = 9961; // 43 +const static uint64_t SH_FLD_LO = 9962; // 1 +const static uint64_t SH_FLD_LOAD_CI_BUFF = 9963; // 2 +const static uint64_t SH_FLD_LOAD_RSVD_VALUES = 9964; // 8 +const static uint64_t SH_FLD_LOCALITY_4_ACCESS = 9965; // 1 +const static uint64_t SH_FLD_LOCAL_HANG_COMP = 9966; // 4 +const static uint64_t SH_FLD_LOCAL_HANG_COMP_LEN = 9967; // 4 +const static uint64_t SH_FLD_LOCAL_HIGH_PRIORITY = 9968; // 4 +const static uint64_t SH_FLD_LOCAL_HIGH_PRIORITY_LEN = 9969; // 4 +const static uint64_t SH_FLD_LOCAL_LOW_PRIORITY = 9970; // 4 +const static uint64_t SH_FLD_LOCAL_LOW_PRIORITY_LEN = 9971; // 4 +const static uint64_t SH_FLD_LOCAL_NODE_EPSILON = 9972; // 8 +const static uint64_t SH_FLD_LOCAL_NODE_EPSILON_LEN = 9973; // 8 +const static uint64_t SH_FLD_LOCAL_QUIESCE_ACHIEVED = 9974; // 1 +const static uint64_t SH_FLD_LOCAL_TRACE_RUN_IN = 9975; // 43 +const static uint64_t SH_FLD_LOCK = 9976; // 16 +const static uint64_t SH_FLD_LOCKED_FSM_RESET_ONGOING = 9977; // 1 +const static uint64_t SH_FLD_LOCKED_FSM_STATE = 9978; // 1 +const static uint64_t SH_FLD_LOCKED_FSM_STATE_LEN = 9979; // 1 +const static uint64_t SH_FLD_LOCKED_PIBM_ADDR = 9980; // 1 +const static uint64_t SH_FLD_LOCKED_PIBM_ADDR_LEN = 9981; // 1 +const static uint64_t SH_FLD_LOCKED_SEEPROM_ADDRESS = 9982; // 1 +const static uint64_t SH_FLD_LOCKED_SEEPROM_ADDRESS_LEN = 9983; // 1 +const static uint64_t SH_FLD_LOCK_PCB_ON_ERR = 9984; // 12 +const static uint64_t SH_FLD_LOCK_SEL = 9985; // 6 +const static uint64_t SH_FLD_LOFF_AMP_EN = 9986; // 6 +const static uint64_t SH_FLD_LOG = 9987; // 1 +const static uint64_t SH_FLD_LOG_FULL = 9988; // 8 +const static uint64_t SH_FLD_LOG_LEN = 9989; // 1 +const static uint64_t SH_FLD_LOG_POINTER = 9990; // 8 +const static uint64_t SH_FLD_LOG_POINTER_LEN = 9991; // 8 +const static uint64_t SH_FLD_LOOP_BREAK_MODE = 9992; // 64 +const static uint64_t SH_FLD_LOOP_BREAK_MODE_LEN = 9993; // 64 +const static uint64_t SH_FLD_LOOP_COUNT = 9994; // 43 +const static uint64_t SH_FLD_LOOP_COUNT_LEN = 9995; // 43 +const static uint64_t SH_FLD_LOW = 9996; // 1 +const static uint64_t SH_FLD_LOW_IDLE_COUNT = 9997; // 8 +const static uint64_t SH_FLD_LOW_IDLE_COUNT_LEN = 9998; // 8 +const static uint64_t SH_FLD_LOW_IDLE_THRESHOLD = 9999; // 8 +const static uint64_t SH_FLD_LOW_IDLE_THRESHOLD_LEN = 10000; // 8 +const static uint64_t SH_FLD_LOW_LATENCY = 10001; // 8 +const static uint64_t SH_FLD_LOW_LEN = 10002; // 1 +const static uint64_t SH_FLD_LOW_ORDER_STEP_VALUE = 10003; // 1 +const static uint64_t SH_FLD_LOW_ORDER_STEP_VALUE_LEN = 10004; // 1 +const static uint64_t SH_FLD_LOW_PROBE_TRACE_GATE = 10005; // 8 +const static uint64_t SH_FLD_LO_ENABLE = 10006; // 2 +const static uint64_t SH_FLD_LO_FIXED_WINDOW_MODE = 10007; // 2 +const static uint64_t SH_FLD_LO_PRESCALE_MODE = 10008; // 2 +const static uint64_t SH_FLD_LO_SELECT = 10009; // 2 +const static uint64_t SH_FLD_LO_SELECT_LEN = 10010; // 2 +const static uint64_t SH_FLD_LP = 10011; // 8 +const static uint64_t SH_FLD_LPARID = 10012; // 24 +const static uint64_t SH_FLD_LPARID_LEN = 10013; // 24 +const static uint64_t SH_FLD_LPARSHORT = 10014; // 272 +const static uint64_t SH_FLD_LPARSHORT_LEN = 10015; // 272 +const static uint64_t SH_FLD_LPCR_BOT = 10016; // 16 +const static uint64_t SH_FLD_LPCR_ISL = 10017; // 16 +const static uint64_t SH_FLD_LPCR_PS = 10018; // 16 +const static uint64_t SH_FLD_LPCR_PS_LEN = 10019; // 16 +const static uint64_t SH_FLD_LPCR_SC = 10020; // 16 +const static uint64_t SH_FLD_LPCR_TC = 10021; // 16 +const static uint64_t SH_FLD_LPCTH = 10022; // 3 +const static uint64_t SH_FLD_LPCTH_LEN = 10023; // 3 +const static uint64_t SH_FLD_LPC_MODE = 10024; // 2 +const static uint64_t SH_FLD_LPC_MODE_LEN = 10025; // 2 +const static uint64_t SH_FLD_LPID = 10026; // 9 +const static uint64_t SH_FLD_LPID_LEN = 10027; // 9 +const static uint64_t SH_FLD_LPID_MASK = 10028; // 1 +const static uint64_t SH_FLD_LPID_MASK_LEN = 10029; // 1 +const static uint64_t SH_FLD_LP_CNT_THRESH = 10030; // 6 +const static uint64_t SH_FLD_LP_CNT_THRESH_LEN = 10031; // 6 +const static uint64_t SH_FLD_LP_LEN = 10032; // 8 +const static uint64_t SH_FLD_LP_MAX_CRED_THRESH = 10033; // 6 +const static uint64_t SH_FLD_LP_MAX_CRED_THRESH_LEN = 10034; // 6 +const static uint64_t SH_FLD_LP_MIN_CRED_THRESH = 10035; // 6 +const static uint64_t SH_FLD_LP_MIN_CRED_THRESH_LEN = 10036; // 6 +const static uint64_t SH_FLD_LP_MODE_ENABLE = 10037; // 6 +const static uint64_t SH_FLD_LP_ONLY_MODE = 10038; // 6 +const static uint64_t SH_FLD_LP_TIMER_TICK_CONFIG = 10039; // 6 +const static uint64_t SH_FLD_LP_TIMER_TICK_CONFIG_LEN = 10040; // 6 +const static uint64_t SH_FLD_LRDIMM = 10041; // 2 +const static uint64_t SH_FLD_LRDIMM_CONTEXT = 10042; // 8 +const static uint64_t SH_FLD_LRDIMM_LEN = 10043; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD1 = 10044; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD10 = 10045; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD10_LEN = 10046; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD11 = 10047; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD11_LEN = 10048; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD12 = 10049; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD12_LEN = 10050; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD13 = 10051; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD13_LEN = 10052; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD14 = 10053; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD14_LEN = 10054; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD15 = 10055; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD15_LEN = 10056; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD1_LEN = 10057; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD2 = 10058; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD2_LEN = 10059; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD3 = 10060; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD3_LEN = 10061; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD4 = 10062; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD4_LEN = 10063; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD5 = 10064; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD5_LEN = 10065; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD6 = 10066; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD6_LEN = 10067; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD7 = 10068; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD7_LEN = 10069; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD8 = 10070; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD8_LEN = 10071; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD9 = 10072; // 2 +const static uint64_t SH_FLD_LRDIMM_WORD9_LEN = 10073; // 2 +const static uint64_t SH_FLD_LRU_ALL_MEMBERS_IN_CGC_ARE_LINE_DELETED = 10074; // 12 +const static uint64_t SH_FLD_LRU_PERR_CHK_DIS = 10075; // 2 +const static uint64_t SH_FLD_LRU_READ_ERROR_DETECTED = 10076; // 12 +const static uint64_t SH_FLD_LSMFB_SCAN_ALL_PRIO_ENA = 10077; // 1 +const static uint64_t SH_FLD_LTE_EN = 10078; // 4 +const static uint64_t SH_FLD_LUC = 10079; // 1 +const static uint64_t SH_FLD_LUC_LEN = 10080; // 1 +const static uint64_t SH_FLD_LUT = 10081; // 1 +const static uint64_t SH_FLD_LUT_LEN = 10082; // 1 +const static uint64_t SH_FLD_LVDIR_EN = 10083; // 12 +const static uint64_t SH_FLD_LVDIR_PERR = 10084; // 12 +const static uint64_t SH_FLD_LVLTRANS_FENCE = 10085; // 43 +const static uint64_t SH_FLD_M = 10086; // 1 +const static uint64_t SH_FLD_M0_BIT_MAP = 10087; // 8 +const static uint64_t SH_FLD_M0_BIT_MAP_LEN = 10088; // 8 +const static uint64_t SH_FLD_M0_PRIORITY = 10089; // 1 +const static uint64_t SH_FLD_M0_PRIORITY_LEN = 10090; // 1 +const static uint64_t SH_FLD_M0_PRIORITY_SEL = 10091; // 1 +const static uint64_t SH_FLD_M1HC0A = 10092; // 1 +const static uint64_t SH_FLD_M1HC0A_LEN = 10093; // 1 +const static uint64_t SH_FLD_M1HC0B = 10094; // 1 +const static uint64_t SH_FLD_M1HC0B_LEN = 10095; // 1 +const static uint64_t SH_FLD_M1HC1A = 10096; // 1 +const static uint64_t SH_FLD_M1HC1A_LEN = 10097; // 1 +const static uint64_t SH_FLD_M1HC1B = 10098; // 1 +const static uint64_t SH_FLD_M1HC1B_LEN = 10099; // 1 +const static uint64_t SH_FLD_M1HC2A = 10100; // 1 +const static uint64_t SH_FLD_M1HC2A_LEN = 10101; // 1 +const static uint64_t SH_FLD_M1HC2B = 10102; // 1 +const static uint64_t SH_FLD_M1HC2B_LEN = 10103; // 1 +const static uint64_t SH_FLD_M1SASIM1_ENABLE_PIB_ERROR = 10104; // 1 +const static uint64_t SH_FLD_M1SASIM1_ENABLE_PIB_PENDING = 10105; // 1 +const static uint64_t SH_FLD_M1SASIM1_ENABLE_XUP = 10106; // 1 +const static uint64_t SH_FLD_M1_BIT_MAP = 10107; // 8 +const static uint64_t SH_FLD_M1_BIT_MAP_LEN = 10108; // 8 +const static uint64_t SH_FLD_M1_PRIORITY = 10109; // 1 +const static uint64_t SH_FLD_M1_PRIORITY_LEN = 10110; // 1 +const static uint64_t SH_FLD_M1_PRIORITY_SEL = 10111; // 1 +const static uint64_t SH_FLD_M2HC0A = 10112; // 1 +const static uint64_t SH_FLD_M2HC0A_LEN = 10113; // 1 +const static uint64_t SH_FLD_M2HC0B = 10114; // 1 +const static uint64_t SH_FLD_M2HC0B_LEN = 10115; // 1 +const static uint64_t SH_FLD_M2HC1A = 10116; // 1 +const static uint64_t SH_FLD_M2HC1A_LEN = 10117; // 1 +const static uint64_t SH_FLD_M2HC1B = 10118; // 1 +const static uint64_t SH_FLD_M2HC1B_LEN = 10119; // 1 +const static uint64_t SH_FLD_M2HC2A = 10120; // 1 +const static uint64_t SH_FLD_M2HC2A_LEN = 10121; // 1 +const static uint64_t SH_FLD_M2HC2B = 10122; // 1 +const static uint64_t SH_FLD_M2HC2B_LEN = 10123; // 1 +const static uint64_t SH_FLD_M2_PRIORITY = 10124; // 1 +const static uint64_t SH_FLD_M2_PRIORITY_LEN = 10125; // 1 +const static uint64_t SH_FLD_M2_PRIORITY_SEL = 10126; // 1 +const static uint64_t SH_FLD_M3_PRIORITY = 10127; // 1 +const static uint64_t SH_FLD_M3_PRIORITY_LEN = 10128; // 1 +const static uint64_t SH_FLD_M3_PRIORITY_SEL = 10129; // 1 +const static uint64_t SH_FLD_M4_PRIORITY = 10130; // 1 +const static uint64_t SH_FLD_M4_PRIORITY_LEN = 10131; // 1 +const static uint64_t SH_FLD_M5_PRIORITY = 10132; // 1 +const static uint64_t SH_FLD_M5_PRIORITY_LEN = 10133; // 1 +const static uint64_t SH_FLD_M5_PRIORITY_SEL = 10134; // 1 +const static uint64_t SH_FLD_M6_PRIORITY = 10135; // 1 +const static uint64_t SH_FLD_M6_PRIORITY_LEN = 10136; // 1 +const static uint64_t SH_FLD_M7_PRIORITY = 10137; // 1 +const static uint64_t SH_FLD_M7_PRIORITY_LEN = 10138; // 1 +const static uint64_t SH_FLD_M7_PRIORITY_SEL = 10139; // 1 +const static uint64_t SH_FLD_MAGIC_COOKIE = 10140; // 1 +const static uint64_t SH_FLD_MAGIC_COOKIE_LEN = 10141; // 1 +const static uint64_t SH_FLD_MAINLINE_AUE = 10142; // 8 +const static uint64_t SH_FLD_MAINLINE_IAUE = 10143; // 8 +const static uint64_t SH_FLD_MAINLINE_IMPE = 10144; // 8 +const static uint64_t SH_FLD_MAINLINE_IRCD = 10145; // 8 +const static uint64_t SH_FLD_MAINLINE_IUE = 10146; // 8 +const static uint64_t SH_FLD_MAINLINE_MCE = 10147; // 8 +const static uint64_t SH_FLD_MAINLINE_MPE_RANK_0_TO_7 = 10148; // 8 +const static uint64_t SH_FLD_MAINLINE_MPE_RANK_0_TO_7_LEN = 10149; // 8 +const static uint64_t SH_FLD_MAINLINE_NCE = 10150; // 8 +const static uint64_t SH_FLD_MAINLINE_RCD = 10151; // 8 +const static uint64_t SH_FLD_MAINLINE_SCE = 10152; // 8 +const static uint64_t SH_FLD_MAINLINE_SUE = 10153; // 8 +const static uint64_t SH_FLD_MAINLINE_TCE = 10154; // 8 +const static uint64_t SH_FLD_MAINLINE_UE = 10155; // 8 +const static uint64_t SH_FLD_MAINTENANCE_AUE = 10156; // 8 +const static uint64_t SH_FLD_MAINTENANCE_IAUE = 10157; // 8 +const static uint64_t SH_FLD_MAINTENANCE_IMPE = 10158; // 8 +const static uint64_t SH_FLD_MAINTENANCE_IRCD = 10159; // 8 +const static uint64_t SH_FLD_MAINTENANCE_IUE = 10160; // 8 +const static uint64_t SH_FLD_MAINTENANCE_MCE = 10161; // 8 +const static uint64_t SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7 = 10162; // 8 +const static uint64_t SH_FLD_MAINTENANCE_MPE_RANK_0_TO_7_LEN = 10163; // 8 +const static uint64_t SH_FLD_MAINTENANCE_NCE = 10164; // 8 +const static uint64_t SH_FLD_MAINTENANCE_RCD = 10165; // 8 +const static uint64_t SH_FLD_MAINTENANCE_SCE = 10166; // 8 +const static uint64_t SH_FLD_MAINTENANCE_SUE = 10167; // 8 +const static uint64_t SH_FLD_MAINTENANCE_TCE = 10168; // 8 +const static uint64_t SH_FLD_MAINTENANCE_UE = 10169; // 8 +const static uint64_t SH_FLD_MAINT_CCS_PE_HOLD_OUT = 10170; // 2 +const static uint64_t SH_FLD_MAIN_SLICE_EN_ENC = 10171; // 1 +const static uint64_t SH_FLD_MAIN_SLICE_EN_ENC_LEN = 10172; // 1 +const static uint64_t SH_FLD_MAJOR = 10173; // 1 +const static uint64_t SH_FLD_MAJOR_LEN = 10174; // 1 +const static uint64_t SH_FLD_MALFUNCTION_ALERT = 10175; // 96 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP0 = 10176; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP0_LEN = 10177; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP1 = 10178; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP10 = 10179; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP10_LEN = 10180; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP11 = 10181; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP11_LEN = 10182; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP12 = 10183; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP12_LEN = 10184; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP13 = 10185; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP13_LEN = 10186; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP14 = 10187; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP14_LEN = 10188; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP15 = 10189; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP15_LEN = 10190; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP1_LEN = 10191; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP2 = 10192; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP2_LEN = 10193; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP3 = 10194; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP3_LEN = 10195; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP4 = 10196; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP4_LEN = 10197; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP5 = 10198; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP5_LEN = 10199; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP6 = 10200; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP6_LEN = 10201; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP7 = 10202; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP7_LEN = 10203; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP8 = 10204; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP8_LEN = 10205; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP9 = 10206; // 1 +const static uint64_t SH_FLD_MALF_ERR_FROM_GROUP9_LEN = 10207; // 1 +const static uint64_t SH_FLD_MANUAL_CLR_PB_STOP = 10208; // 1 +const static uint64_t SH_FLD_MANUAL_PB_SWITCH_ABCD = 10209; // 1 +const static uint64_t SH_FLD_MANUAL_SET_PB_STOP = 10210; // 1 +const static uint64_t SH_FLD_MAP_ERR_INJ_PEND = 10211; // 1 +const static uint64_t SH_FLD_MAP_REG_CERR0 = 10212; // 1 +const static uint64_t SH_FLD_MAP_REG_CERR1 = 10213; // 1 +const static uint64_t SH_FLD_MAP_REG_ERR0 = 10214; // 1 +const static uint64_t SH_FLD_MAP_REG_ERR1 = 10215; // 1 +const static uint64_t SH_FLD_MAP_REG_ERR2 = 10216; // 1 +const static uint64_t SH_FLD_MAP_REG_ERR3 = 10217; // 1 +const static uint64_t SH_FLD_MAP_REG_ERR4 = 10218; // 1 +const static uint64_t SH_FLD_MARGINPD_SEL = 10219; // 6 +const static uint64_t SH_FLD_MARGINPD_SEL_LEN = 10220; // 6 +const static uint64_t SH_FLD_MARGINPU_SEL = 10221; // 6 +const static uint64_t SH_FLD_MARGINPU_SEL_LEN = 10222; // 6 +const static uint64_t SH_FLD_MARK = 10223; // 64 +const static uint64_t SH_FLD_MARK_LEN = 10224; // 64 +const static uint64_t SH_FLD_MASK = 10225; // 68 +const static uint64_t SH_FLD_MASKA = 10226; // 90 +const static uint64_t SH_FLD_MASKA_LEN = 10227; // 90 +const static uint64_t SH_FLD_MASKB = 10228; // 90 +const static uint64_t SH_FLD_MASKB_LEN = 10229; // 90 +const static uint64_t SH_FLD_MASKC = 10230; // 90 +const static uint64_t SH_FLD_MASKC_LEN = 10231; // 90 +const static uint64_t SH_FLD_MASKD = 10232; // 90 +const static uint64_t SH_FLD_MASKD_LEN = 10233; // 90 +const static uint64_t SH_FLD_MASK_AGV_DISABLE_MODE = 10234; // 2 +const static uint64_t SH_FLD_MASK_B = 10235; // 129 +const static uint64_t SH_FLD_MASK_LEN = 10236; // 60 +const static uint64_t SH_FLD_MASK_PURGE_INTERFACE = 10237; // 12 +const static uint64_t SH_FLD_MASK_TOGGLE_ENABLE = 10238; // 1 +const static uint64_t SH_FLD_MASTER = 10239; // 8 +const static uint64_t SH_FLD_MASTERID = 10240; // 6 +const static uint64_t SH_FLD_MASTERID_LEN = 10241; // 6 +const static uint64_t SH_FLD_MASTERS = 10242; // 43 +const static uint64_t SH_FLD_MASTERS_LEN = 10243; // 43 +const static uint64_t SH_FLD_MASTER_ARRAY_CE = 10244; // 4 +const static uint64_t SH_FLD_MASTER_ARRAY_UE = 10245; // 4 +const static uint64_t SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV = 10246; // 12 +const static uint64_t SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV_LEN = 10247; // 12 +const static uint64_t SH_FLD_MASTER_ERROR_CODE = 10248; // 1 +const static uint64_t SH_FLD_MASTER_ERROR_CODE_LEN = 10249; // 1 +const static uint64_t SH_FLD_MASTER_IDLE = 10250; // 1 +const static uint64_t SH_FLD_MASTER_MODE = 10251; // 47 +const static uint64_t SH_FLD_MASTER_RECOVERABLE_ERROR = 10252; // 4 +const static uint64_t SH_FLD_MASTER_RESPONSE_BIT = 10253; // 1 +const static uint64_t SH_FLD_MASTER_SYS_XSTOP_ERROR = 10254; // 4 +const static uint64_t SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV = 10255; // 12 +const static uint64_t SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN = 10256; // 12 +const static uint64_t SH_FLD_MATCH = 10257; // 12 +const static uint64_t SH_FLD_MATCHA_MUXSEL = 10258; // 90 +const static uint64_t SH_FLD_MATCHA_MUXSEL_LEN = 10259; // 90 +const static uint64_t SH_FLD_MATCHB_MUXSEL = 10260; // 90 +const static uint64_t SH_FLD_MATCHB_MUXSEL_LEN = 10261; // 90 +const static uint64_t SH_FLD_MATCHC_MUXSEL = 10262; // 90 +const static uint64_t SH_FLD_MATCHC_MUXSEL_LEN = 10263; // 90 +const static uint64_t SH_FLD_MATCHD_MUXSEL = 10264; // 90 +const static uint64_t SH_FLD_MATCHD_MUXSEL_LEN = 10265; // 90 +const static uint64_t SH_FLD_MATCH_LEN = 10266; // 12 +const static uint64_t SH_FLD_MATCH_NOT_MODE = 10267; // 90 +const static uint64_t SH_FLD_MATCH_NOT_MODE_LEN = 10268; // 90 +const static uint64_t SH_FLD_MAXCYCLECNT = 10269; // 3 +const static uint64_t SH_FLD_MAXCYCLECNT_LEN = 10270; // 3 +const static uint64_t SH_FLD_MAX_BAD_LANES = 10271; // 4 +const static uint64_t SH_FLD_MAX_BAD_LANES_LEN = 10272; // 4 +const static uint64_t SH_FLD_MAX_BER_CHECK_COUNT = 10273; // 4 +const static uint64_t SH_FLD_MAX_BER_CHECK_COUNT_LEN = 10274; // 4 +const static uint64_t SH_FLD_MAX_CRD_TO_CQ = 10275; // 6 +const static uint64_t SH_FLD_MAX_CRD_TO_CQ_LEN = 10276; // 6 +const static uint64_t SH_FLD_MAX_CRD_TO_PC = 10277; // 6 +const static uint64_t SH_FLD_MAX_CRD_TO_PC_LEN = 10278; // 6 +const static uint64_t SH_FLD_MAX_CYCLE_SAMPLE = 10279; // 12 +const static uint64_t SH_FLD_MAX_CYCLE_SAMPLE_LEN = 10280; // 12 +const static uint64_t SH_FLD_MAX_ENTRIES_IN_MODIFIED = 10281; // 3 +const static uint64_t SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN = 10282; // 3 +const static uint64_t SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS = 10283; // 2 +const static uint64_t SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS_LEN = 10284; // 2 +const static uint64_t SH_FLD_MAX_OUTSTANDING = 10285; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_CI_LOAD = 10286; // 2 +const static uint64_t SH_FLD_MAX_OUTSTANDING_CI_LOAD_LEN = 10287; // 2 +const static uint64_t SH_FLD_MAX_OUTSTANDING_CI_STORE = 10288; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_CI_STORE_LEN = 10289; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_EOI = 10290; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_EOI_LEN = 10291; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_EQD_FETCH = 10292; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_EQD_FETCH_LEN = 10293; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_EQD_WRITE = 10294; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_EQD_WRITE_LEN = 10295; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_EQP = 10296; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_EQP_LEN = 10297; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_ISB_FETCH = 10298; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_ISB_FETCH_LEN = 10299; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_ISB_WRITE = 10300; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_ISB_WRITE_LEN = 10301; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_IVE_FETCH = 10302; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_IVE_FETCH_LEN = 10303; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_LEN = 10304; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP = 10305; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP_LEN = 10306; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_SOFT_EOI = 10307; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_SOFT_EOI_LEN = 10308; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT = 10309; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT_LEN = 10310; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT_VC = 10311; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_ST_RMT_VC_LEN = 10312; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_VPD_FETCH = 10313; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_VPD_FETCH_LEN = 10314; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_WB = 10315; // 1 +const static uint64_t SH_FLD_MAX_OUTSTANDING_WB_LEN = 10316; // 1 +const static uint64_t SH_FLD_MAX_POLL_BCAST_1_0_4 = 10317; // 1 +const static uint64_t SH_FLD_MAX_POLL_BCAST_1_0_4_LEN = 10318; // 1 +const static uint64_t SH_FLD_MAX_POLL_BCAST_2_0_4 = 10319; // 1 +const static uint64_t SH_FLD_MAX_POLL_BCAST_2_0_4_LEN = 10320; // 1 +const static uint64_t SH_FLD_MAX_POLL_BCAST_3_0_4 = 10321; // 1 +const static uint64_t SH_FLD_MAX_POLL_BCAST_3_0_4_LEN = 10322; // 1 +const static uint64_t SH_FLD_MAX_PROMOTE_LEVEL_A_N = 10323; // 96 +const static uint64_t SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN = 10324; // 96 +const static uint64_t SH_FLD_MAX_PTAG_IN_USE = 10325; // 4 +const static uint64_t SH_FLD_MAX_PTAG_IN_USE_LEN = 10326; // 4 +const static uint64_t SH_FLD_MAX_UNLOCK_IN_FIFO = 10327; // 4 +const static uint64_t SH_FLD_MAX_UNLOCK_IN_FIFO_LEN = 10328; // 4 +const static uint64_t SH_FLD_MB00_SPATTN = 10329; // 4 +const static uint64_t SH_FLD_MB01_SPATTN = 10330; // 4 +const static uint64_t SH_FLD_MB10_SPATTN = 10331; // 4 +const static uint64_t SH_FLD_MB11_SPATTN = 10332; // 4 +const static uint64_t SH_FLD_MB20_SPATTN = 10333; // 4 +const static uint64_t SH_FLD_MB21_SPATTN = 10334; // 4 +const static uint64_t SH_FLD_MB30_SPATTN = 10335; // 4 +const static uint64_t SH_FLD_MB31_SPATTN = 10336; // 4 +const static uint64_t SH_FLD_MB40_SPATTN = 10337; // 4 +const static uint64_t SH_FLD_MB41_SPATTN = 10338; // 4 +const static uint64_t SH_FLD_MB50_SPATTN = 10339; // 4 +const static uint64_t SH_FLD_MB51_SPATTN = 10340; // 4 +const static uint64_t SH_FLD_MB60_SPATTN = 10341; // 2 +const static uint64_t SH_FLD_MB61_SPATTN = 10342; // 2 +const static uint64_t SH_FLD_MB70_SPATTN = 10343; // 2 +const static uint64_t SH_FLD_MB71_SPATTN = 10344; // 2 +const static uint64_t SH_FLD_MBASE = 10345; // 12 +const static uint64_t SH_FLD_MBASE_LEN = 10346; // 12 +const static uint64_t SH_FLD_MBA_NONRECOVERABLE_ERROR = 10347; // 16 +const static uint64_t SH_FLD_MBA_RECOVERABLE_ERROR = 10348; // 16 +const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_CAW2_CE_UE_ERR_DETECT_EN = 10349; // 8 +const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_EN = 10350; // 8 +const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_CRC_MODE_X8 = 10351; // 8 +const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_CHK_DISABLE = 10352; // 8 +const static uint64_t SH_FLD_MBA_WRD_MODE_CFG_WRD_ECC_COR_DISABLE = 10353; // 8 +const static uint64_t SH_FLD_MBA_WRD_MODE_RESERVED_4 = 10354; // 8 +const static uint64_t SH_FLD_MBOX0 = 10355; // 1 +const static uint64_t SH_FLD_MBOX0_LEN = 10356; // 1 +const static uint64_t SH_FLD_MBOX1 = 10357; // 1 +const static uint64_t SH_FLD_MBOX1_LEN = 10358; // 1 +const static uint64_t SH_FLD_MBOX2 = 10359; // 1 +const static uint64_t SH_FLD_MBOX2_LEN = 10360; // 1 +const static uint64_t SH_FLD_MBOX3 = 10361; // 1 +const static uint64_t SH_FLD_MBOX3_LEN = 10362; // 1 +const static uint64_t SH_FLD_MBOX4 = 10363; // 1 +const static uint64_t SH_FLD_MBOX4_LEN = 10364; // 1 +const static uint64_t SH_FLD_MBOX5 = 10365; // 1 +const static uint64_t SH_FLD_MBOX5_LEN = 10366; // 1 +const static uint64_t SH_FLD_MBOX6 = 10367; // 1 +const static uint64_t SH_FLD_MBOX6_LEN = 10368; // 1 +const static uint64_t SH_FLD_MBOX7 = 10369; // 1 +const static uint64_t SH_FLD_MBOX7_LEN = 10370; // 1 +const static uint64_t SH_FLD_MBR_DIS = 10371; // 2 +const static uint64_t SH_FLD_MBR_DIS_LEN = 10372; // 2 +const static uint64_t SH_FLD_MBSECCQ_DATA_GENERATOR_OVERRIDE = 10373; // 8 +const static uint64_t SH_FLD_MBSECCQ_DATA_INVERSION = 10374; // 8 +const static uint64_t SH_FLD_MBSECCQ_DATA_INVERSION_LEN = 10375; // 8 +const static uint64_t SH_FLD_MBSECCQ_DELAY_NONBYPASS = 10376; // 8 +const static uint64_t SH_FLD_MBSECCQ_DELAY_VALID_1X = 10377; // 8 +const static uint64_t SH_FLD_MBSECCQ_DISABLE_MARK_STORE_WRITE = 10378; // 8 +const static uint64_t SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT = 10379; // 8 +const static uint64_t SH_FLD_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT = 10380; // 8 +const static uint64_t SH_FLD_MBSECCQ_DISABLE_MPE_CONFIRM = 10381; // 8 +const static uint64_t SH_FLD_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING = 10382; // 8 +const static uint64_t SH_FLD_MBSECCQ_DISABLE_UE_RETRY = 10383; // 8 +const static uint64_t SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY = 10384; // 8 +const static uint64_t SH_FLD_MBSECCQ_ECC_SCHEDULER_DELAY_LEN = 10385; // 8 +const static uint64_t SH_FLD_MBSECCQ_ENABLE_CHIPMARKED_SCE_NCE = 10386; // 8 +const static uint64_t SH_FLD_MBSECCQ_ENABLE_HOST_ATTENTION = 10387; // 8 +const static uint64_t SH_FLD_MBSECCQ_ENABLE_SPECIAL_ATTENTION = 10388; // 8 +const static uint64_t SH_FLD_MBSECCQ_ENABLE_TCE_CORRECTION = 10389; // 8 +const static uint64_t SH_FLD_MBSECCQ_ENABLE_UE_NOISE_WINDOW = 10390; // 8 +const static uint64_t SH_FLD_MBSECCQ_EXIT_OVERRIDE = 10391; // 8 +const static uint64_t SH_FLD_MBSECCQ_EXIT_OVERRIDE_LEN = 10392; // 8 +const static uint64_t SH_FLD_MBSECCQ_HWMARK_EXIT1 = 10393; // 8 +const static uint64_t SH_FLD_MBSECCQ_INT_RESET_KEEPER = 10394; // 8 +const static uint64_t SH_FLD_MBSECCQ_ITAG_METADATA_ENABLE = 10395; // 8 +const static uint64_t SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY = 10396; // 8 +const static uint64_t SH_FLD_MBSECCQ_NEST_VAL_TO_DATA_DELAY_LEN = 10397; // 8 +const static uint64_t SH_FLD_MBSECCQ_READ_POINTER_DELAY = 10398; // 8 +const static uint64_t SH_FLD_MBSECCQ_READ_POINTER_DELAY_LEN = 10399; // 8 +const static uint64_t SH_FLD_MBSECCQ_RESERVED_33_39 = 10400; // 8 +const static uint64_t SH_FLD_MBSECCQ_RESERVED_33_39_LEN = 10401; // 8 +const static uint64_t SH_FLD_MBSECCQ_USE_ADDRESS_HASH = 10402; // 8 +const static uint64_t SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY = 10403; // 8 +const static uint64_t SH_FLD_MBSECCQ_VAL_TO_DATA_DELAY_LEN = 10404; // 8 +const static uint64_t SH_FLD_MB_BAD_ADDR = 10405; // 2 +const static uint64_t SH_FLD_MB_BAD_WRITE = 10406; // 2 +const static uint64_t SH_FLD_MB_CORRUPT = 10407; // 2 +const static uint64_t SH_FLD_MB_LINK_DOWN = 10408; // 2 +const static uint64_t SH_FLD_MB_LINK_ID = 10409; // 2 +const static uint64_t SH_FLD_MB_LINK_ID_LEN = 10410; // 2 +const static uint64_t SH_FLD_MB_RESET = 10411; // 2 +const static uint64_t SH_FLD_MB_SENT = 10412; // 2 +const static uint64_t SH_FLD_MB_SPARE = 10413; // 2 +const static uint64_t SH_FLD_MB_SPARE_LEN = 10414; // 2 +const static uint64_t SH_FLD_MB_VALID = 10415; // 2 +const static uint64_t SH_FLD_MB_WR_NOT_RD = 10416; // 2 +const static uint64_t SH_FLD_MCA_DBG_SEL_IN = 10417; // 8 +const static uint64_t SH_FLD_MCA_DBG_SEL_WRT = 10418; // 8 +const static uint64_t SH_FLD_MCBAGEN_PE_HOLD_OUT = 10419; // 2 +const static uint64_t SH_FLD_MCBCM_PE = 10420; // 8 +const static uint64_t SH_FLD_MCBCNTL_PE_HOLD_OUT = 10421; // 2 +const static uint64_t SH_FLD_MCBCNTL_PORT_SEL = 10422; // 2 +const static uint64_t SH_FLD_MCBCNTL_PORT_SEL_LEN = 10423; // 2 +const static uint64_t SH_FLD_MCBDGEN_PE_HOLD_OUT = 10424; // 2 +const static uint64_t SH_FLD_MCBERR_SCOM_PE_HOLD_OUT = 10425; // 2 +const static uint64_t SH_FLD_MCBIST_BRODCAST_OUT_OF_SYNC = 10426; // 2 +const static uint64_t SH_FLD_MCBIST_CCS_SUBTEST_DONE = 10427; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR = 10428; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST = 10429; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST = 10430; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_REF_WAIT_TIME = 10431; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_REF_WAIT_TIME_LEN = 10432; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_RAND_MODE = 10433; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_REV_MODE = 10434; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL = 10435; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ADDR_SEL_LEN = 10436; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_1ST_CMD = 10437; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_2ND_CMD = 10438; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST00_COMPL_3RD_CMD = 10439; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST00_DATA_MODE = 10440; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST00_DATA_MODE_LEN = 10441; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST00_DONE = 10442; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST00_ECC_MODE = 10443; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST00_OP_TYPE = 10444; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST00_OP_TYPE_LEN = 10445; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_RAND_MODE = 10446; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_REV_MODE = 10447; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL = 10448; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ADDR_SEL_LEN = 10449; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_1ST_CMD = 10450; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_2ND_CMD = 10451; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST01_COMPL_3RD_CMD = 10452; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST01_DATA_MODE = 10453; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST01_DATA_MODE_LEN = 10454; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST01_DONE = 10455; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST01_ECC_MODE = 10456; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST01_OP_TYPE = 10457; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST01_OP_TYPE_LEN = 10458; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_RAND_MODE = 10459; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_REV_MODE = 10460; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL = 10461; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ADDR_SEL_LEN = 10462; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_1ST_CMD = 10463; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_2ND_CMD = 10464; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST02_COMPL_3RD_CMD = 10465; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST02_DATA_MODE = 10466; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST02_DATA_MODE_LEN = 10467; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST02_DONE = 10468; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST02_ECC_MODE = 10469; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST02_OP_TYPE = 10470; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST02_OP_TYPE_LEN = 10471; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_RAND_MODE = 10472; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_REV_MODE = 10473; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL = 10474; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ADDR_SEL_LEN = 10475; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_1ST_CMD = 10476; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_2ND_CMD = 10477; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST03_COMPL_3RD_CMD = 10478; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST03_DATA_MODE = 10479; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST03_DATA_MODE_LEN = 10480; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST03_DONE = 10481; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST03_ECC_MODE = 10482; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST03_OP_TYPE = 10483; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST03_OP_TYPE_LEN = 10484; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_RAND_MODE = 10485; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_REV_MODE = 10486; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL = 10487; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ADDR_SEL_LEN = 10488; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_1ST_CMD = 10489; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_2ND_CMD = 10490; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST04_COMPL_3RD_CMD = 10491; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST04_DATA_MODE = 10492; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST04_DATA_MODE_LEN = 10493; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST04_DONE = 10494; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST04_ECC_MODE = 10495; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST04_OP_TYPE = 10496; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST04_OP_TYPE_LEN = 10497; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_RAND_MODE = 10498; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_REV_MODE = 10499; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL = 10500; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ADDR_SEL_LEN = 10501; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_1ST_CMD = 10502; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_2ND_CMD = 10503; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST05_COMPL_3RD_CMD = 10504; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST05_DATA_MODE = 10505; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST05_DATA_MODE_LEN = 10506; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST05_DONE = 10507; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST05_ECC_MODE = 10508; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST05_OP_TYPE = 10509; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST05_OP_TYPE_LEN = 10510; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_RAND_MODE = 10511; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_REV_MODE = 10512; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL = 10513; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ADDR_SEL_LEN = 10514; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_1ST_CMD = 10515; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_2ND_CMD = 10516; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST06_COMPL_3RD_CMD = 10517; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST06_DATA_MODE = 10518; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST06_DATA_MODE_LEN = 10519; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST06_DONE = 10520; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST06_ECC_MODE = 10521; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST06_OP_TYPE = 10522; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST06_OP_TYPE_LEN = 10523; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_RAND_MODE = 10524; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_REV_MODE = 10525; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL = 10526; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ADDR_SEL_LEN = 10527; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_1ST_CMD = 10528; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_2ND_CMD = 10529; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST07_COMPL_3RD_CMD = 10530; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST07_DATA_MODE = 10531; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST07_DATA_MODE_LEN = 10532; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST07_DONE = 10533; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST07_ECC_MODE = 10534; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST07_OP_TYPE = 10535; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST07_OP_TYPE_LEN = 10536; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_RAND_MODE = 10537; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_REV_MODE = 10538; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL = 10539; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ADDR_SEL_LEN = 10540; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_1ST_CMD = 10541; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_2ND_CMD = 10542; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST08_COMPL_3RD_CMD = 10543; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST08_DATA_MODE = 10544; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST08_DATA_MODE_LEN = 10545; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST08_DONE = 10546; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST08_ECC_MODE = 10547; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST08_OP_TYPE = 10548; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST08_OP_TYPE_LEN = 10549; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_RAND_MODE = 10550; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_REV_MODE = 10551; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL = 10552; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ADDR_SEL_LEN = 10553; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_1ST_CMD = 10554; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_2ND_CMD = 10555; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST09_COMPL_3RD_CMD = 10556; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST09_DATA_MODE = 10557; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST09_DATA_MODE_LEN = 10558; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST09_DONE = 10559; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST09_ECC_MODE = 10560; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST09_OP_TYPE = 10561; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST09_OP_TYPE_LEN = 10562; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_RAND_MODE = 10563; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_REV_MODE = 10564; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL = 10565; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ADDR_SEL_LEN = 10566; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_1ST_CMD = 10567; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_2ND_CMD = 10568; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST10_COMPL_3RD_CMD = 10569; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST10_DATA_MODE = 10570; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST10_DATA_MODE_LEN = 10571; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST10_DONE = 10572; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST10_ECC_MODE = 10573; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST10_OP_TYPE = 10574; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST10_OP_TYPE_LEN = 10575; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_RAND_MODE = 10576; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_REV_MODE = 10577; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL = 10578; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ADDR_SEL_LEN = 10579; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_1ST_CMD = 10580; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_2ND_CMD = 10581; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST11_COMPL_3RD_CMD = 10582; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST11_DATA_MODE = 10583; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST11_DATA_MODE_LEN = 10584; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST11_DONE = 10585; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST11_ECC_MODE = 10586; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST11_OP_TYPE = 10587; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST11_OP_TYPE_LEN = 10588; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_RAND_MODE = 10589; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_REV_MODE = 10590; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL = 10591; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ADDR_SEL_LEN = 10592; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_1ST_CMD = 10593; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_2ND_CMD = 10594; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST12_COMPL_3RD_CMD = 10595; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST12_DATA_MODE = 10596; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST12_DATA_MODE_LEN = 10597; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST12_DONE = 10598; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST12_ECC_MODE = 10599; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST12_OP_TYPE = 10600; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST12_OP_TYPE_LEN = 10601; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_RAND_MODE = 10602; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_REV_MODE = 10603; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL = 10604; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ADDR_SEL_LEN = 10605; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_1ST_CMD = 10606; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_2ND_CMD = 10607; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST13_COMPL_3RD_CMD = 10608; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST13_DATA_MODE = 10609; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST13_DATA_MODE_LEN = 10610; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST13_DONE = 10611; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST13_ECC_MODE = 10612; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST13_OP_TYPE = 10613; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST13_OP_TYPE_LEN = 10614; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_RAND_MODE = 10615; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_REV_MODE = 10616; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL = 10617; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ADDR_SEL_LEN = 10618; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_1ST_CMD = 10619; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_2ND_CMD = 10620; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST14_COMPL_3RD_CMD = 10621; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST14_DATA_MODE = 10622; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST14_DATA_MODE_LEN = 10623; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST14_DONE = 10624; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST14_ECC_MODE = 10625; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST14_OP_TYPE = 10626; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST14_OP_TYPE_LEN = 10627; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_RAND_MODE = 10628; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_REV_MODE = 10629; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL = 10630; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ADDR_SEL_LEN = 10631; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_1ST_CMD = 10632; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_2ND_CMD = 10633; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST15_COMPL_3RD_CMD = 10634; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST15_DATA_MODE = 10635; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST15_DATA_MODE_LEN = 10636; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST15_DONE = 10637; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST15_ECC_MODE = 10638; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST15_OP_TYPE = 10639; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST15_OP_TYPE_LEN = 10640; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_RAND_MODE = 10641; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_REV_MODE = 10642; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL = 10643; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ADDR_SEL_LEN = 10644; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_1ST_CMD = 10645; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_2ND_CMD = 10646; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST16_COMPL_3RD_CMD = 10647; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST16_DATA_MODE = 10648; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST16_DATA_MODE_LEN = 10649; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST16_DONE = 10650; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST16_ECC_MODE = 10651; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST16_OP_TYPE = 10652; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST16_OP_TYPE_LEN = 10653; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_RAND_MODE = 10654; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_REV_MODE = 10655; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL = 10656; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ADDR_SEL_LEN = 10657; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_1ST_CMD = 10658; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_2ND_CMD = 10659; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST17_COMPL_3RD_CMD = 10660; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST17_DATA_MODE = 10661; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST17_DATA_MODE_LEN = 10662; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST17_DONE = 10663; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST17_ECC_MODE = 10664; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST17_OP_TYPE = 10665; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST17_OP_TYPE_LEN = 10666; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_RAND_MODE = 10667; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_REV_MODE = 10668; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL = 10669; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ADDR_SEL_LEN = 10670; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_1ST_CMD = 10671; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_2ND_CMD = 10672; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST18_COMPL_3RD_CMD = 10673; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST18_DATA_MODE = 10674; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST18_DATA_MODE_LEN = 10675; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST18_DONE = 10676; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST18_ECC_MODE = 10677; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST18_OP_TYPE = 10678; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST18_OP_TYPE_LEN = 10679; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_RAND_MODE = 10680; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_REV_MODE = 10681; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL = 10682; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ADDR_SEL_LEN = 10683; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_1ST_CMD = 10684; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_2ND_CMD = 10685; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST19_COMPL_3RD_CMD = 10686; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST19_DATA_MODE = 10687; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST19_DATA_MODE_LEN = 10688; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST19_DONE = 10689; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST19_ECC_MODE = 10690; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST19_OP_TYPE = 10691; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST19_OP_TYPE_LEN = 10692; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_RAND_MODE = 10693; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_REV_MODE = 10694; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL = 10695; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ADDR_SEL_LEN = 10696; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_1ST_CMD = 10697; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_2ND_CMD = 10698; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST20_COMPL_3RD_CMD = 10699; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST20_DATA_MODE = 10700; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST20_DATA_MODE_LEN = 10701; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST20_DONE = 10702; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST20_ECC_MODE = 10703; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST20_OP_TYPE = 10704; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST20_OP_TYPE_LEN = 10705; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_RAND_MODE = 10706; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_REV_MODE = 10707; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL = 10708; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ADDR_SEL_LEN = 10709; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_1ST_CMD = 10710; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_2ND_CMD = 10711; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST21_COMPL_3RD_CMD = 10712; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST21_DATA_MODE = 10713; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST21_DATA_MODE_LEN = 10714; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST21_DONE = 10715; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST21_ECC_MODE = 10716; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST21_OP_TYPE = 10717; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST21_OP_TYPE_LEN = 10718; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_RAND_MODE = 10719; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_REV_MODE = 10720; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL = 10721; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ADDR_SEL_LEN = 10722; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_1ST_CMD = 10723; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_2ND_CMD = 10724; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST22_COMPL_3RD_CMD = 10725; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST22_DATA_MODE = 10726; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST22_DATA_MODE_LEN = 10727; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST22_DONE = 10728; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST22_ECC_MODE = 10729; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST22_OP_TYPE = 10730; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST22_OP_TYPE_LEN = 10731; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_RAND_MODE = 10732; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_REV_MODE = 10733; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL = 10734; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ADDR_SEL_LEN = 10735; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_1ST_CMD = 10736; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_2ND_CMD = 10737; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST23_COMPL_3RD_CMD = 10738; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST23_DATA_MODE = 10739; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST23_DATA_MODE_LEN = 10740; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST23_DONE = 10741; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST23_ECC_MODE = 10742; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST23_OP_TYPE = 10743; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST23_OP_TYPE_LEN = 10744; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_RAND_MODE = 10745; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_REV_MODE = 10746; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL = 10747; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ADDR_SEL_LEN = 10748; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_1ST_CMD = 10749; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_2ND_CMD = 10750; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST24_COMPL_3RD_CMD = 10751; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST24_DATA_MODE = 10752; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST24_DATA_MODE_LEN = 10753; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST24_DONE = 10754; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST24_ECC_MODE = 10755; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST24_OP_TYPE = 10756; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST24_OP_TYPE_LEN = 10757; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_RAND_MODE = 10758; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_REV_MODE = 10759; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL = 10760; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ADDR_SEL_LEN = 10761; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_1ST_CMD = 10762; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_2ND_CMD = 10763; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST25_COMPL_3RD_CMD = 10764; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST25_DATA_MODE = 10765; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST25_DATA_MODE_LEN = 10766; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST25_DONE = 10767; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST25_ECC_MODE = 10768; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST25_OP_TYPE = 10769; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST25_OP_TYPE_LEN = 10770; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_RAND_MODE = 10771; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_REV_MODE = 10772; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL = 10773; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ADDR_SEL_LEN = 10774; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_1ST_CMD = 10775; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_2ND_CMD = 10776; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST26_COMPL_3RD_CMD = 10777; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST26_DATA_MODE = 10778; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST26_DATA_MODE_LEN = 10779; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST26_DONE = 10780; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST26_ECC_MODE = 10781; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST26_OP_TYPE = 10782; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST26_OP_TYPE_LEN = 10783; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_RAND_MODE = 10784; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_REV_MODE = 10785; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL = 10786; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ADDR_SEL_LEN = 10787; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_1ST_CMD = 10788; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_2ND_CMD = 10789; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST27_COMPL_3RD_CMD = 10790; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST27_DATA_MODE = 10791; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST27_DATA_MODE_LEN = 10792; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST27_DONE = 10793; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST27_ECC_MODE = 10794; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST27_OP_TYPE = 10795; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST27_OP_TYPE_LEN = 10796; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_RAND_MODE = 10797; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_REV_MODE = 10798; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL = 10799; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ADDR_SEL_LEN = 10800; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_1ST_CMD = 10801; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_2ND_CMD = 10802; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST28_COMPL_3RD_CMD = 10803; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST28_DATA_MODE = 10804; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST28_DATA_MODE_LEN = 10805; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST28_DONE = 10806; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST28_ECC_MODE = 10807; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST28_OP_TYPE = 10808; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST28_OP_TYPE_LEN = 10809; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_RAND_MODE = 10810; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_REV_MODE = 10811; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL = 10812; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ADDR_SEL_LEN = 10813; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_1ST_CMD = 10814; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_2ND_CMD = 10815; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST29_COMPL_3RD_CMD = 10816; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST29_DATA_MODE = 10817; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST29_DATA_MODE_LEN = 10818; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST29_DONE = 10819; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST29_ECC_MODE = 10820; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST29_OP_TYPE = 10821; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST29_OP_TYPE_LEN = 10822; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_RAND_MODE = 10823; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_REV_MODE = 10824; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL = 10825; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ADDR_SEL_LEN = 10826; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_1ST_CMD = 10827; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_2ND_CMD = 10828; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST30_COMPL_3RD_CMD = 10829; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST30_DATA_MODE = 10830; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST30_DATA_MODE_LEN = 10831; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST30_DONE = 10832; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST30_ECC_MODE = 10833; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST30_OP_TYPE = 10834; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST30_OP_TYPE_LEN = 10835; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_RAND_MODE = 10836; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_REV_MODE = 10837; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL = 10838; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ADDR_SEL_LEN = 10839; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_1ST_CMD = 10840; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_2ND_CMD = 10841; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST31_COMPL_3RD_CMD = 10842; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST31_DATA_MODE = 10843; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST31_DATA_MODE_LEN = 10844; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST31_DONE = 10845; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST31_ECC_MODE = 10846; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST31_OP_TYPE = 10847; // 2 +const static uint64_t SH_FLD_MCBIST_CFG_TEST31_OP_TYPE_LEN = 10848; // 2 +const static uint64_t SH_FLD_MCBIST_DATA_ERROR = 10849; // 2 +const static uint64_t SH_FLD_MCBIST_FSM_INJ_MODE = 10850; // 2 +const static uint64_t SH_FLD_MCBIST_FSM_INJ_REG = 10851; // 2 +const static uint64_t SH_FLD_MCBIST_HALF_COMPARE_MASK = 10852; // 8 +const static uint64_t SH_FLD_MCBIST_HALF_COMPARE_MASK_LEN = 10853; // 8 +const static uint64_t SH_FLD_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR = 10854; // 2 +const static uint64_t SH_FLD_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR_LEN = 10855; // 2 +const static uint64_t SH_FLD_MCBIST_MASK_COVERAGE_SELECTOR = 10856; // 8 +const static uint64_t SH_FLD_MCBIST_PROGRAM_COMPLETE = 10857; // 2 +const static uint64_t SH_FLD_MCBIST_SUBTEST_IP = 10858; // 2 +const static uint64_t SH_FLD_MCBIST_SUBTEST_NUM_INDICATOR = 10859; // 2 +const static uint64_t SH_FLD_MCBIST_SUBTEST_NUM_INDICATOR_LEN = 10860; // 2 +const static uint64_t SH_FLD_MCBIST_TRAP_CE_ENABLE = 10861; // 8 +const static uint64_t SH_FLD_MCBIST_TRAP_MPE_ENABLE = 10862; // 8 +const static uint64_t SH_FLD_MCBIST_TRAP_NONSTOP = 10863; // 8 +const static uint64_t SH_FLD_MCBIST_TRAP_UE_ENABLE = 10864; // 8 +const static uint64_t SH_FLD_MCB_CNTLQ_PE_HOLD_OUT = 10865; // 2 +const static uint64_t SH_FLD_MCB_FIR_CCS_ERR_HOLD_OUT = 10866; // 2 +const static uint64_t SH_FLD_MCB_FIR_MCBFSM_ERR_HOLD_OUT = 10867; // 2 +const static uint64_t SH_FLD_MCD_ARRAY_ECC_CE_ERR = 10868; // 2 +const static uint64_t SH_FLD_MCD_ARRAY_ECC_UE_ERR = 10869; // 2 +const static uint64_t SH_FLD_MCD_CHICKEN_SWITCH = 10870; // 2 +const static uint64_t SH_FLD_MCD_CL_PROBE_PB_HANG_ERR = 10871; // 2 +const static uint64_t SH_FLD_MCD_CRESP_ADDR_ERR = 10872; // 2 +const static uint64_t SH_FLD_MCD_PB_ADDR_PARITY_ERR = 10873; // 2 +const static uint64_t SH_FLD_MCD_SCOM_ERR = 10874; // 2 +const static uint64_t SH_FLD_MCD_SCOM_ERR_DUP = 10875; // 2 +const static uint64_t SH_FLD_MCD_SM_OR_CASE_ERR = 10876; // 2 +const static uint64_t SH_FLD_MCD_TTAG_PARITY_ERR = 10877; // 2 +const static uint64_t SH_FLD_MCD_UNSOLICITED_CRESP_ERR = 10878; // 2 +const static uint64_t SH_FLD_MCD_UPDATE_ERR = 10879; // 2 +const static uint64_t SH_FLD_MCE_SYMBOL0_COUNT = 10880; // 2 +const static uint64_t SH_FLD_MCE_SYMBOL0_COUNT_LEN = 10881; // 2 +const static uint64_t SH_FLD_MCE_SYMBOL1_COUNT = 10882; // 2 +const static uint64_t SH_FLD_MCE_SYMBOL1_COUNT_LEN = 10883; // 2 +const static uint64_t SH_FLD_MCE_SYMBOL2_COUNT = 10884; // 2 +const static uint64_t SH_FLD_MCE_SYMBOL2_COUNT_LEN = 10885; // 2 +const static uint64_t SH_FLD_MCE_SYMBOL3_COUNT = 10886; // 2 +const static uint64_t SH_FLD_MCE_SYMBOL3_COUNT_LEN = 10887; // 2 +const static uint64_t SH_FLD_MCMD = 10888; // 24 +const static uint64_t SH_FLD_MCMD_LEN = 10889; // 24 +const static uint64_t SH_FLD_MCMODE0_64B_WR_IS_PWRT = 10890; // 4 +const static uint64_t SH_FLD_MCPERF1_DISABLE_FASTPATH_QOS = 10891; // 4 +const static uint64_t SH_FLD_MCS_RESET_KEEPER = 10892; // 4 +const static uint64_t SH_FLD_MCS_WAT0 = 10893; // 4 +const static uint64_t SH_FLD_MCS_WAT1 = 10894; // 4 +const static uint64_t SH_FLD_MCS_WAT2 = 10895; // 4 +const static uint64_t SH_FLD_MCS_WAT3 = 10896; // 4 +const static uint64_t SH_FLD_MC_CHANNELS_PER_GROUP = 10897; // 4 +const static uint64_t SH_FLD_MC_CHANNELS_PER_GROUP_LEN = 10898; // 4 +const static uint64_t SH_FLD_MC_FP_MATE_CMD_ERR0 = 10899; // 12 +const static uint64_t SH_FLD_MC_FP_MATE_CMD_ERR1 = 10900; // 12 +const static uint64_t SH_FLD_MC_INTERNAL_NONRECOVERABLE_ERROR = 10901; // 4 +const static uint64_t SH_FLD_MC_INTERNAL_RECOVERABLE_ERROR = 10902; // 4 +const static uint64_t SH_FLD_MC_TC_0_FIR_HOST_ATTN = 10903; // 2 +const static uint64_t SH_FLD_MC_TC_1_FIR_HOST_ATTN = 10904; // 2 +const static uint64_t SH_FLD_MC_TC_2_FIR_HOST_ATTN = 10905; // 2 +const static uint64_t SH_FLD_MC_TC_3_FIR_HOST_ATTN = 10906; // 2 +const static uint64_t SH_FLD_MC_TC_4_FIR_HOST_ATTN = 10907; // 2 +const static uint64_t SH_FLD_MC_TC_5_FIR_HOST_ATTN = 10908; // 2 +const static uint64_t SH_FLD_MC_TC_6_FIR_HOST_ATTN = 10909; // 2 +const static uint64_t SH_FLD_MC_TC_7_FIR_HOST_ATTN = 10910; // 2 +const static uint64_t SH_FLD_MD5_LATENCY_CFG = 10911; // 1 +const static uint64_t SH_FLD_MDI_0 = 10912; // 8 +const static uint64_t SH_FLD_MDI_1 = 10913; // 8 +const static uint64_t SH_FLD_MED_IDLE_COUNT = 10914; // 8 +const static uint64_t SH_FLD_MED_IDLE_COUNT_LEN = 10915; // 8 +const static uint64_t SH_FLD_MED_IDLE_THRESHOLD = 10916; // 8 +const static uint64_t SH_FLD_MED_IDLE_THRESHOLD_LEN = 10917; // 8 +const static uint64_t SH_FLD_MEGAMOUTH = 10918; // 24 +const static uint64_t SH_FLD_MEM = 10919; // 26 +const static uint64_t SH_FLD_MEMCTL_CIC_FAST = 10920; // 8 +const static uint64_t SH_FLD_MEMCTL_CTRN_IGNORE = 10921; // 8 +const static uint64_t SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP = 10922; // 4 +const static uint64_t SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN = 10923; // 4 +const static uint64_t SH_FLD_MEMORY_TYPE = 10924; // 8 +const static uint64_t SH_FLD_MEMORY_TYPE_LEN = 10925; // 8 +const static uint64_t SH_FLD_MEM_ADDR = 10926; // 21 +const static uint64_t SH_FLD_MEM_ADDR_LEN = 10927; // 21 +const static uint64_t SH_FLD_MEM_BUSY = 10928; // 21 +const static uint64_t SH_FLD_MEM_BYTE_ENABLE = 10929; // 21 +const static uint64_t SH_FLD_MEM_BYTE_ENABLE_LEN = 10930; // 21 +const static uint64_t SH_FLD_MEM_DATAOP_PENDING = 10931; // 21 +const static uint64_t SH_FLD_MEM_ERROR = 10932; // 21 +const static uint64_t SH_FLD_MEM_ERROR_LEN = 10933; // 21 +const static uint64_t SH_FLD_MEM_HIGH_PRIORITY = 10934; // 4 +const static uint64_t SH_FLD_MEM_HIGH_PRIORITY_LEN = 10935; // 4 +const static uint64_t SH_FLD_MEM_IFETCH_PENDING = 10936; // 21 +const static uint64_t SH_FLD_MEM_IMPRECISE_ERROR_PENDING = 10937; // 21 +const static uint64_t SH_FLD_MEM_LEN = 10938; // 26 +const static uint64_t SH_FLD_MEM_LINE_MODE = 10939; // 21 +const static uint64_t SH_FLD_MEM_LOW_PRIORITY = 10940; // 4 +const static uint64_t SH_FLD_MEM_LOW_PRIORITY_LEN = 10941; // 4 +const static uint64_t SH_FLD_MEM_R_NW = 10942; // 21 +const static uint64_t SH_FLD_MEM_SIZE = 10943; // 6 +const static uint64_t SH_FLD_MEM_SIZE_LEN = 10944; // 6 +const static uint64_t SH_FLD_MERGE_CAPACITY_LIMIT = 10945; // 12 +const static uint64_t SH_FLD_MERGE_CAPACITY_LIMIT_LEN = 10946; // 12 +const static uint64_t SH_FLD_MESSAGE_BITS0 = 10947; // 15 +const static uint64_t SH_FLD_MESSAGE_BITS0_LEN = 10948; // 15 +const static uint64_t SH_FLD_MESSAGE_BITS1 = 10949; // 15 +const static uint64_t SH_FLD_MESSAGE_BITS1_LEN = 10950; // 15 +const static uint64_t SH_FLD_MESSAGE_BITS2 = 10951; // 12 +const static uint64_t SH_FLD_MESSAGE_BITS2_LEN = 10952; // 12 +const static uint64_t SH_FLD_MESSAGE_BITS3 = 10953; // 12 +const static uint64_t SH_FLD_MESSAGE_BITS3_LEN = 10954; // 12 +const static uint64_t SH_FLD_MESSAGE_BITS4 = 10955; // 12 +const static uint64_t SH_FLD_MESSAGE_BITS4_LEN = 10956; // 12 +const static uint64_t SH_FLD_MGR_CREDIT = 10957; // 3 +const static uint64_t SH_FLD_MGR_CREDIT_LEN = 10958; // 3 +const static uint64_t SH_FLD_MIB_GPIO = 10959; // 13 +const static uint64_t SH_FLD_MIB_GPIO_LEN = 10960; // 13 +const static uint64_t SH_FLD_MID_CARE_MASK = 10961; // 4 +const static uint64_t SH_FLD_MID_CARE_MASK_LEN = 10962; // 4 +const static uint64_t SH_FLD_MID_MATCH_VALUE = 10963; // 4 +const static uint64_t SH_FLD_MID_MATCH_VALUE_LEN = 10964; // 4 +const static uint64_t SH_FLD_MIG_REG = 10965; // 1 +const static uint64_t SH_FLD_MIG_REG_LEN = 10966; // 1 +const static uint64_t SH_FLD_MINCYCLECNT = 10967; // 3 +const static uint64_t SH_FLD_MINCYCLECNT_LEN = 10968; // 3 +const static uint64_t SH_FLD_MINIKERF = 10969; // 2 +const static uint64_t SH_FLD_MINIKERF_LEN = 10970; // 2 +const static uint64_t SH_FLD_MINOR = 10971; // 1 +const static uint64_t SH_FLD_MINOR_LEN = 10972; // 1 +const static uint64_t SH_FLD_MIN_CYCLE_SAMPLE = 10973; // 12 +const static uint64_t SH_FLD_MIN_CYCLE_SAMPLE_LEN = 10974; // 12 +const static uint64_t SH_FLD_MIN_EYE_HEIGHT = 10975; // 6 +const static uint64_t SH_FLD_MIN_EYE_HEIGHT_LEN = 10976; // 6 +const static uint64_t SH_FLD_MIN_EYE_WIDTH = 10977; // 6 +const static uint64_t SH_FLD_MIN_EYE_WIDTH_LEN = 10978; // 6 +const static uint64_t SH_FLD_MIRROR_ACTION_OCCURRED = 10979; // 4 +const static uint64_t SH_FLD_MISC = 10980; // 10 +const static uint64_t SH_FLD_MISC_BUS0BYTE0 = 10981; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE0_LEN = 10982; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE1 = 10983; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE10 = 10984; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE10_LEN = 10985; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE1_LEN = 10986; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE2 = 10987; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE2_LEN = 10988; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE3 = 10989; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE3_LEN = 10990; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE4 = 10991; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE4_LEN = 10992; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE5 = 10993; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE5_LEN = 10994; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE6 = 10995; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE6_LEN = 10996; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE7 = 10997; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE7_LEN = 10998; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE8 = 10999; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE8_LEN = 11000; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE9 = 11001; // 1 +const static uint64_t SH_FLD_MISC_BUS0BYTE9_LEN = 11002; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE0 = 11003; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE0_LEN = 11004; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE1 = 11005; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE10 = 11006; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE10_LEN = 11007; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE1_LEN = 11008; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE2 = 11009; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE2_LEN = 11010; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE3 = 11011; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE3_LEN = 11012; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE4 = 11013; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE4_LEN = 11014; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE5 = 11015; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE5_LEN = 11016; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE6 = 11017; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE6_LEN = 11018; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE7 = 11019; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE7_LEN = 11020; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE8 = 11021; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE8_LEN = 11022; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE9 = 11023; // 1 +const static uint64_t SH_FLD_MISC_BUS1BYTE9_LEN = 11024; // 1 +const static uint64_t SH_FLD_MISC_CFG = 11025; // 6 +const static uint64_t SH_FLD_MISC_CFG_LEN = 11026; // 6 +const static uint64_t SH_FLD_MISC_CTL_4VS64 = 11027; // 1 +const static uint64_t SH_FLD_MISC_CTL_ACCEPT_PASTE = 11028; // 1 +const static uint64_t SH_FLD_MISC_CTL_CAM_INVAL_DONE = 11029; // 1 +const static uint64_t SH_FLD_MISC_CTL_CAM_LOCATION = 11030; // 1 +const static uint64_t SH_FLD_MISC_CTL_CAM_LOCATION_LEN = 11031; // 1 +const static uint64_t SH_FLD_MISC_CTL_DISABLE_PUSH2MEM_LIMIT = 11032; // 1 +const static uint64_t SH_FLD_MISC_CTL_ENABLE_WRMON = 11033; // 1 +const static uint64_t SH_FLD_MISC_CTL_HMI_ACTIVE = 11034; // 1 +const static uint64_t SH_FLD_MISC_CTL_INVALIDATE_CAM_ALL = 11035; // 1 +const static uint64_t SH_FLD_MISC_CTL_INVALIDATE_CAM_LOC = 11036; // 1 +const static uint64_t SH_FLD_MISC_CTL_QUIESCE_REQUEST = 11037; // 1 +const static uint64_t SH_FLD_MISC_CTL_RG_IS_IDLE = 11038; // 1 +const static uint64_t SH_FLD_MISC_CTL_UNUSED_BITS = 11039; // 1 +const static uint64_t SH_FLD_MISC_CTL_UNUSED_BITS2 = 11040; // 1 +const static uint64_t SH_FLD_MISC_CTL_UNUSED_BITS_LEN = 11041; // 1 +const static uint64_t SH_FLD_MISC_CTRL_PERR = 11042; // 1 +const static uint64_t SH_FLD_MISC_DA_ADDR_PERR = 11043; // 1 +const static uint64_t SH_FLD_MISC_DA_OP = 11044; // 1 +const static uint64_t SH_FLD_MISC_INT_RA_PERR = 11045; // 1 +const static uint64_t SH_FLD_MISC_LEN = 11046; // 10 +const static uint64_t SH_FLD_MISC_LENGTH = 11047; // 1 +const static uint64_t SH_FLD_MISC_LENGTH_LEN = 11048; // 1 +const static uint64_t SH_FLD_MISC_LENR = 11049; // 1 +const static uint64_t SH_FLD_MISC_LENR_LEN = 11050; // 1 +const static uint64_t SH_FLD_MISC_NMMU_ERR = 11051; // 1 +const static uint64_t SH_FLD_MISC_RESYNC_OSC_FROM = 11052; // 1 +const static uint64_t SH_FLD_MISC_RING_ERR = 11053; // 1 +const static uint64_t SH_FLD_MISC_RNW = 11054; // 1 +const static uint64_t SH_FLD_MISC_RSVD = 11055; // 1 +const static uint64_t SH_FLD_MISC_RSVD_LEN = 11056; // 1 +const static uint64_t SH_FLD_MISR_A_VAL = 11057; // 43 +const static uint64_t SH_FLD_MISR_A_VAL_LEN = 11058; // 43 +const static uint64_t SH_FLD_MISR_B_VAL = 11059; // 43 +const static uint64_t SH_FLD_MISR_B_VAL_LEN = 11060; // 43 +const static uint64_t SH_FLD_MISR_INIT_WAIT = 11061; // 43 +const static uint64_t SH_FLD_MISR_INIT_WAIT_LEN = 11062; // 43 +const static uint64_t SH_FLD_MISR_MODE = 11063; // 43 +const static uint64_t SH_FLD_MLC_ACCESS_ERR_ESR = 11064; // 1 +const static uint64_t SH_FLD_MMIO = 11065; // 15 +const static uint64_t SH_FLD_MMIOSD = 11066; // 1 +const static uint64_t SH_FLD_MMIO_BAR_PE = 11067; // 1 +const static uint64_t SH_FLD_MMIO_CTL_ACTYPE = 11068; // 1 +const static uint64_t SH_FLD_MMIO_CTL_COMP = 11069; // 1 +const static uint64_t SH_FLD_MMIO_CTL_INIT = 11070; // 1 +const static uint64_t SH_FLD_MMIO_CTL_OFFSET = 11071; // 1 +const static uint64_t SH_FLD_MMIO_CTL_OFFSET_LEN = 11072; // 1 +const static uint64_t SH_FLD_MMIO_CTL_OPTYPE = 11073; // 1 +const static uint64_t SH_FLD_MMIO_CTL_OP_ERR = 11074; // 1 +const static uint64_t SH_FLD_MMIO_CTL_UNUSED = 11075; // 1 +const static uint64_t SH_FLD_MMIO_CTL_UNUSED_LEN = 11076; // 1 +const static uint64_t SH_FLD_MMIO_CTL_WINID = 11077; // 1 +const static uint64_t SH_FLD_MMIO_CTL_WINID_LEN = 11078; // 1 +const static uint64_t SH_FLD_MMIO_DATA = 11079; // 1 +const static uint64_t SH_FLD_MMIO_DATA_LEN = 11080; // 1 +const static uint64_t SH_FLD_MMIO_ECC = 11081; // 1 +const static uint64_t SH_FLD_MMIO_ECC_LEN = 11082; // 1 +const static uint64_t SH_FLD_MMIO_HYP_RD_ADDR_ERR = 11083; // 2 +const static uint64_t SH_FLD_MMIO_HYP_WR_ADDR_ERR = 11084; // 2 +const static uint64_t SH_FLD_MMIO_NON8B_HYP_ERR = 11085; // 2 +const static uint64_t SH_FLD_MMIO_NON8B_OS_ERR = 11086; // 2 +const static uint64_t SH_FLD_MMIO_OS_RD_ADDR_ERR = 11087; // 2 +const static uint64_t SH_FLD_MMIO_OS_WR_ADDR_ERR = 11088; // 2 +const static uint64_t SH_FLD_MMIO_REQUEST_TIMEOUT = 11089; // 6 +const static uint64_t SH_FLD_MMR = 11090; // 1 +const static uint64_t SH_FLD_MMR_LEN = 11091; // 1 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_00 = 11092; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_00_LEN = 11093; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_01 = 11094; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_01_LEN = 11095; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_02 = 11096; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_02_LEN = 11097; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_03 = 11098; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_03_LEN = 11099; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_04 = 11100; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_04_LEN = 11101; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_05 = 11102; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_05_LEN = 11103; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_06 = 11104; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_06_LEN = 11105; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_07 = 11106; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_07_LEN = 11107; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_08 = 11108; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_08_LEN = 11109; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_09 = 11110; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_09_LEN = 11111; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_10 = 11112; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_10_LEN = 11113; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_11 = 11114; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_11_LEN = 11115; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_12 = 11116; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_12_LEN = 11117; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_13 = 11118; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_13_LEN = 11119; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_14 = 11120; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_14_LEN = 11121; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_15 = 11122; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_15_LEN = 11123; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_16 = 11124; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_16_LEN = 11125; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_17 = 11126; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_17_LEN = 11127; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_18 = 11128; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_18_LEN = 11129; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_19 = 11130; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_19_LEN = 11131; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_20 = 11132; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_20_LEN = 11133; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_21 = 11134; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_21_LEN = 11135; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_22 = 11136; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_22_LEN = 11137; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_23 = 11138; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_23_LEN = 11139; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_24 = 11140; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_24_LEN = 11141; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_25 = 11142; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_25_LEN = 11143; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_26 = 11144; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_26_LEN = 11145; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_27 = 11146; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_27_LEN = 11147; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_28 = 11148; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_28_LEN = 11149; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_29 = 11150; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_29_LEN = 11151; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_30 = 11152; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_30_LEN = 11153; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_31 = 11154; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_31_LEN = 11155; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_32 = 11156; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_32_LEN = 11157; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_33 = 11158; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_33_LEN = 11159; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_34 = 11160; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_34_LEN = 11161; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_35 = 11162; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_35_LEN = 11163; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_36 = 11164; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_36_LEN = 11165; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_37 = 11166; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_37_LEN = 11167; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_38 = 11168; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_38_LEN = 11169; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_39 = 11170; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_39_LEN = 11171; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_40 = 11172; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_40_LEN = 11173; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_41 = 11174; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_41_LEN = 11175; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_42 = 11176; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_42_LEN = 11177; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_43 = 11178; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_43_LEN = 11179; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_44 = 11180; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_44_LEN = 11181; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_45 = 11182; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_45_LEN = 11183; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_46 = 11184; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_46_LEN = 11185; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_47 = 11186; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_47_LEN = 11187; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_48 = 11188; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_48_LEN = 11189; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_49 = 11190; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_49_LEN = 11191; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_50 = 11192; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_50_LEN = 11193; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_51 = 11194; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_51_LEN = 11195; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_52 = 11196; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_52_LEN = 11197; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_53 = 11198; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_53_LEN = 11199; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_54 = 11200; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_54_LEN = 11201; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_55 = 11202; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_55_LEN = 11203; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_56 = 11204; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_56_LEN = 11205; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_57 = 11206; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_57_LEN = 11207; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_58 = 11208; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_58_LEN = 11209; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_59 = 11210; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_59_LEN = 11211; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_60 = 11212; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_60_LEN = 11213; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_61 = 11214; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_61_LEN = 11215; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_62 = 11216; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_62_LEN = 11217; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_63 = 11218; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_63_LEN = 11219; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_64 = 11220; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_64_LEN = 11221; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_65 = 11222; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_65_LEN = 11223; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_66 = 11224; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_66_LEN = 11225; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_67 = 11226; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_67_LEN = 11227; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_68 = 11228; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_68_LEN = 11229; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_69 = 11230; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_69_LEN = 11231; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_70 = 11232; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_70_LEN = 11233; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_71 = 11234; // 2 +const static uint64_t SH_FLD_MODAL_SYMBOL_COUNTER_71_LEN = 11235; // 2 +const static uint64_t SH_FLD_MODE = 11236; // 153 +const static uint64_t SH_FLD_MODEREG_SPRC_LT0_SEL = 11237; // 24 +const static uint64_t SH_FLD_MODEREG_SPRC_LT1_SEL = 11238; // 24 +const static uint64_t SH_FLD_MODEREG_SPRC_LT2_SEL = 11239; // 24 +const static uint64_t SH_FLD_MODEREG_SPRC_LT3_SEL = 11240; // 24 +const static uint64_t SH_FLD_MODEREG_SPRC_LT4_SEL = 11241; // 24 +const static uint64_t SH_FLD_MODEREG_SPRC_LT5_SEL = 11242; // 24 +const static uint64_t SH_FLD_MODEREG_SPRC_LT6_SEL = 11243; // 24 +const static uint64_t SH_FLD_MODEREG_SPRC_LT7_SEL = 11244; // 24 +const static uint64_t SH_FLD_MODEREG_TFAC_ERR_INJ = 11245; // 24 +const static uint64_t SH_FLD_MODEREG_TFAC_ERR_INJ_LEN = 11246; // 24 +const static uint64_t SH_FLD_MODE_128K_VP = 11247; // 1 +const static uint64_t SH_FLD_MODE_LEN = 11248; // 151 +const static uint64_t SH_FLD_MODE_REGISTER_0_VALUE = 11249; // 64 +const static uint64_t SH_FLD_MODE_REGISTER_0_VALUE_LEN = 11250; // 64 +const static uint64_t SH_FLD_MODE_REGISTER_1_VALUE = 11251; // 64 +const static uint64_t SH_FLD_MODE_REGISTER_1_VALUE_LEN = 11252; // 64 +const static uint64_t SH_FLD_MODE_REGISTER_2_VALUE = 11253; // 64 +const static uint64_t SH_FLD_MODE_REGISTER_2_VALUE_LEN = 11254; // 64 +const static uint64_t SH_FLD_MODE_REGISTER_3_VALUE = 11255; // 64 +const static uint64_t SH_FLD_MODE_REGISTER_3_VALUE_LEN = 11256; // 64 +const static uint64_t SH_FLD_MODE_SEL = 11257; // 12 +const static uint64_t SH_FLD_MON = 11258; // 12 +const static uint64_t SH_FLD_MON_LEN = 11259; // 12 +const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS = 11260; // 1 +const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS_ENABLE = 11261; // 1 +const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ADDRESS_LEN = 11262; // 1 +const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ID = 11263; // 1 +const static uint64_t SH_FLD_MOVE_TO_TB_CORE_ID_LEN = 11264; // 1 +const static uint64_t SH_FLD_MOVE_TO_TB_ON_2X_SYNC_ENABLE = 11265; // 1 +const static uint64_t SH_FLD_MPR_PAGE = 11266; // 8 +const static uint64_t SH_FLD_MPR_PAGE_LEN = 11267; // 8 +const static uint64_t SH_FLD_MPR_PATTERN_BIT = 11268; // 8 +const static uint64_t SH_FLD_MPSS_DIS = 11269; // 1 +const static uint64_t SH_FLD_MPW1 = 11270; // 43 +const static uint64_t SH_FLD_MPW2 = 11271; // 43 +const static uint64_t SH_FLD_MPW3 = 11272; // 43 +const static uint64_t SH_FLD_MRBGP = 11273; // 15 +const static uint64_t SH_FLD_MRBGP_LEN = 11274; // 15 +const static uint64_t SH_FLD_MRBSP = 11275; // 15 +const static uint64_t SH_FLD_MRBSP_LEN = 11276; // 15 +const static uint64_t SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR = 11277; // 6 +const static uint64_t SH_FLD_MRG_BBRD_NBUF = 11278; // 3 +const static uint64_t SH_FLD_MRG_BBRD_NBUF_LEN = 11279; // 3 +const static uint64_t SH_FLD_MRG_COMMON_FATAL_ERROR = 11280; // 6 +const static uint64_t SH_FLD_MRG_CR_DIS = 11281; // 3 +const static uint64_t SH_FLD_MRG_CTLW_CR_DIS = 11282; // 3 +const static uint64_t SH_FLD_MRG_ECC_CORRECTABLE_ERROR = 11283; // 6 +const static uint64_t SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR = 11284; // 6 +const static uint64_t SH_FLD_MRG_IBRD_NBUF = 11285; // 3 +const static uint64_t SH_FLD_MRG_IBRD_NBUF_LEN = 11286; // 3 +const static uint64_t SH_FLD_MRG_IBWR_NBUF = 11287; // 3 +const static uint64_t SH_FLD_MRG_IBWR_NBUF_LEN = 11288; // 3 +const static uint64_t SH_FLD_MRG_MRT_ERROR = 11289; // 6 +const static uint64_t SH_FLD_MRG_OBRD_NBUF = 11290; // 3 +const static uint64_t SH_FLD_MRG_OBRD_NBUF_LEN = 11291; // 3 +const static uint64_t SH_FLD_MRG_PBTX_NBUF = 11292; // 3 +const static uint64_t SH_FLD_MRG_PBTX_NBUF_LEN = 11293; // 3 +const static uint64_t SH_FLD_MRG_RDBF_NBUF = 11294; // 3 +const static uint64_t SH_FLD_MRG_RDBF_NBUF_LEN = 11295; // 3 +const static uint64_t SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR = 11296; // 6 +const static uint64_t SH_FLD_MRS_CMD_DQ_OFF = 11297; // 8 +const static uint64_t SH_FLD_MRS_CMD_DQ_OFF_LEN = 11298; // 8 +const static uint64_t SH_FLD_MRS_CMD_DQ_ON = 11299; // 8 +const static uint64_t SH_FLD_MRS_CMD_DQ_ON_LEN = 11300; // 8 +const static uint64_t SH_FLD_MRT_ERR_NOT_VALID = 11301; // 1 +const static uint64_t SH_FLD_MRT_ERR_PSIZE = 11302; // 1 +const static uint64_t SH_FLD_MR_MASK_EN = 11303; // 8 +const static uint64_t SH_FLD_MR_MASK_EN_LEN = 11304; // 8 +const static uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1 = 11305; // 1 +const static uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_1_LEN = 11306; // 1 +const static uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2 = 11307; // 1 +const static uint64_t SH_FLD_MSADES_ADDRESS_OF_LBUS_PARITY_2_LEN = 11308; // 1 +const static uint64_t SH_FLD_MSADES_CLEAR_1 = 11309; // 1 +const static uint64_t SH_FLD_MSADES_CLEAR_2 = 11310; // 1 +const static uint64_t SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_1 = 11311; // 1 +const static uint64_t SH_FLD_MSADES_ILLEGAL_OPERATION_ATTEMPTED_2 = 11312; // 1 +const static uint64_t SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_1 = 11313; // 1 +const static uint64_t SH_FLD_MSADES_LBUS_B_RAM_PARITY_DETECTED_2 = 11314; // 1 +const static uint64_t SH_FLD_MSADES_READ_EMPTY_PIB_1 = 11315; // 1 +const static uint64_t SH_FLD_MSADES_READ_EMPTY_PIB_2 = 11316; // 1 +const static uint64_t SH_FLD_MSADES_UNUSED_15_12 = 11317; // 1 +const static uint64_t SH_FLD_MSADES_UNUSED_15_12_LEN = 11318; // 1 +const static uint64_t SH_FLD_MSADES_UNUSED_31_28 = 11319; // 1 +const static uint64_t SH_FLD_MSADES_UNUSED_31_28_LEN = 11320; // 1 +const static uint64_t SH_FLD_MSADES_WRITE_FULL_PIB_1 = 11321; // 1 +const static uint64_t SH_FLD_MSADES_WRITE_FULL_PIB_2 = 11322; // 1 +const static uint64_t SH_FLD_MSADI_PIB_ERROR_1 = 11323; // 1 +const static uint64_t SH_FLD_MSADI_PIB_ERROR_2 = 11324; // 1 +const static uint64_t SH_FLD_MSADI_PIB_PENDING_1 = 11325; // 1 +const static uint64_t SH_FLD_MSADI_PIB_PENDING_2 = 11326; // 1 +const static uint64_t SH_FLD_MSADI_UNUSED_31_11 = 11327; // 4 +const static uint64_t SH_FLD_MSADI_UNUSED_31_11_LEN = 11328; // 4 +const static uint64_t SH_FLD_MSADI_UNUSED_7_3 = 11329; // 1 +const static uint64_t SH_FLD_MSADI_UNUSED_7_3_LEN = 11330; // 1 +const static uint64_t SH_FLD_MSADI_XUP_1 = 11331; // 1 +const static uint64_t SH_FLD_MSADI_XUP_2 = 11332; // 1 +const static uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1 = 11333; // 1 +const static uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_1_LEN = 11334; // 1 +const static uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2 = 11335; // 1 +const static uint64_t SH_FLD_MSBDES_ADDRESS_OF_PIB_PARITY_2_LEN = 11336; // 1 +const static uint64_t SH_FLD_MSBDES_CLEAR_1 = 11337; // 1 +const static uint64_t SH_FLD_MSBDES_CLEAR_2 = 11338; // 1 +const static uint64_t SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_1 = 11339; // 1 +const static uint64_t SH_FLD_MSBDES_ILLEGAL_OPERATION_ATTEMPTED_2 = 11340; // 1 +const static uint64_t SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_1 = 11341; // 1 +const static uint64_t SH_FLD_MSBDES_PIB_A_RAM_PARITY_DETECTED_2 = 11342; // 1 +const static uint64_t SH_FLD_MSBDES_READ_EMPTY_PIB_A_1 = 11343; // 1 +const static uint64_t SH_FLD_MSBDES_READ_EMPTY_PIB_A_2 = 11344; // 1 +const static uint64_t SH_FLD_MSBDES_UNUSED_15_12 = 11345; // 1 +const static uint64_t SH_FLD_MSBDES_UNUSED_15_12_LEN = 11346; // 1 +const static uint64_t SH_FLD_MSBDES_UNUSED_31_28 = 11347; // 1 +const static uint64_t SH_FLD_MSBDES_UNUSED_31_28_LEN = 11348; // 1 +const static uint64_t SH_FLD_MSBDES_WRITE_FULL_PIB_A_1 = 11349; // 1 +const static uint64_t SH_FLD_MSBDES_WRITE_FULL_PIB_A_2 = 11350; // 1 +const static uint64_t SH_FLD_MSBDIM1_ENABLE_ABORT = 11351; // 1 +const static uint64_t SH_FLD_MSBDIM1_ENABLE_ABORT_2 = 11352; // 1 +const static uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR = 11353; // 1 +const static uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_ERROR_2 = 11354; // 1 +const static uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING = 11355; // 1 +const static uint64_t SH_FLD_MSBDIM1_ENABLE_LBUS_PENDING_2 = 11356; // 1 +const static uint64_t SH_FLD_MSBDIM1_ENABLE_XDN = 11357; // 1 +const static uint64_t SH_FLD_MSBDIM1_ENABLE_XDN_2 = 11358; // 1 +const static uint64_t SH_FLD_MSBDI_LBUS_ERROR_1 = 11359; // 1 +const static uint64_t SH_FLD_MSBDI_LBUS_ERROR_2 = 11360; // 1 +const static uint64_t SH_FLD_MSBDI_LBUS_PENDING_1 = 11361; // 1 +const static uint64_t SH_FLD_MSBDI_LBUS_PENDING_2 = 11362; // 1 +const static uint64_t SH_FLD_MSBDI_XDN_1 = 11363; // 1 +const static uint64_t SH_FLD_MSBDI_XDN_2 = 11364; // 1 +const static uint64_t SH_FLD_MSBSWAP = 11365; // 4 +const static uint64_t SH_FLD_MSC_BUS0_STG0_SEL = 11366; // 1 +const static uint64_t SH_FLD_MSC_BUS0_STG0_SEL_LEN = 11367; // 1 +const static uint64_t SH_FLD_MSC_BUS0_STG1_SEL = 11368; // 1 +const static uint64_t SH_FLD_MSC_BUS0_STG2_SEL = 11369; // 1 +const static uint64_t SH_FLD_MSC_BUS1_STG0_SEL = 11370; // 1 +const static uint64_t SH_FLD_MSC_BUS1_STG0_SEL_LEN = 11371; // 1 +const static uint64_t SH_FLD_MSC_BUS1_STG1_SEL = 11372; // 1 +const static uint64_t SH_FLD_MSC_BUS1_STG2_SEL = 11373; // 1 +const static uint64_t SH_FLD_MSG_ADDR_ERR = 11374; // 12 +const static uint64_t SH_FLD_MSK = 11375; // 5 +const static uint64_t SH_FLD_MSK_LEN = 11376; // 5 +const static uint64_t SH_FLD_MSM_CURR_STATE_0 = 11377; // 2 +const static uint64_t SH_FLD_MSM_CURR_STATE_0_LEN = 11378; // 2 +const static uint64_t SH_FLD_MSM_CURR_STATE_1 = 11379; // 1 +const static uint64_t SH_FLD_MSM_CURR_STATE_1_LEN = 11380; // 1 +const static uint64_t SH_FLD_MSM_CURR_STATE_2 = 11381; // 1 +const static uint64_t SH_FLD_MSM_CURR_STATE_2_LEN = 11382; // 1 +const static uint64_t SH_FLD_MSM_CURR_STATE_3 = 11383; // 1 +const static uint64_t SH_FLD_MSM_CURR_STATE_3_LEN = 11384; // 1 +const static uint64_t SH_FLD_MSR_DR = 11385; // 256 +const static uint64_t SH_FLD_MSR_HV = 11386; // 256 +const static uint64_t SH_FLD_MSR_PE = 11387; // 8 +const static uint64_t SH_FLD_MSR_PR = 11388; // 256 +const static uint64_t SH_FLD_MSR_SF = 11389; // 256 +const static uint64_t SH_FLD_MSR_TA = 11390; // 256 +const static uint64_t SH_FLD_MSR_US = 11391; // 256 +const static uint64_t SH_FLD_MSR_UV = 11392; // 256 +const static uint64_t SH_FLD_MST_DIS_ABUSPAREN = 11393; // 1 +const static uint64_t SH_FLD_MST_DIS_BEPAREN = 11394; // 1 +const static uint64_t SH_FLD_MST_DIS_RDDBUSPAR = 11395; // 1 +const static uint64_t SH_FLD_MST_DIS_WRDBUSPAREN = 11396; // 1 +const static uint64_t SH_FLD_MST_SPARE = 11397; // 1 +const static uint64_t SH_FLD_MS_GROUP_CHIP = 11398; // 2 +const static uint64_t SH_FLD_MS_GROUP_CHIP_LEN = 11399; // 2 +const static uint64_t SH_FLD_MS_WAT_DEBUG_CONFIG_REG_ERROR = 11400; // 4 +const static uint64_t SH_FLD_MULTICAST1 = 11401; // 43 +const static uint64_t SH_FLD_MULTICAST1_LEN = 11402; // 43 +const static uint64_t SH_FLD_MULTICAST2 = 11403; // 43 +const static uint64_t SH_FLD_MULTICAST2_LEN = 11404; // 43 +const static uint64_t SH_FLD_MULTICAST3 = 11405; // 43 +const static uint64_t SH_FLD_MULTICAST3_LEN = 11406; // 43 +const static uint64_t SH_FLD_MULTICAST4 = 11407; // 43 +const static uint64_t SH_FLD_MULTICAST4_LEN = 11408; // 43 +const static uint64_t SH_FLD_MULTICAST_COMPARE_REGISTER = 11409; // 2 +const static uint64_t SH_FLD_MULTICAST_COMPARE_REGISTER_LEN = 11410; // 2 +const static uint64_t SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER = 11411; // 1 +const static uint64_t SH_FLD_MULTICAST_COMPARE_VALUE_REGISTER_LEN = 11412; // 1 +const static uint64_t SH_FLD_MULTIPLE_BAR = 11413; // 4 +const static uint64_t SH_FLD_MULTIPLE_DIR_ERRORS_DETECTED = 11414; // 12 +const static uint64_t SH_FLD_MULTIPLE_REQ = 11415; // 8 +const static uint64_t SH_FLD_MULTIPLE_REQ_SOURCE = 11416; // 8 +const static uint64_t SH_FLD_MULTIPLE_REQ_SOURCE_LEN = 11417; // 8 +const static uint64_t SH_FLD_MULT_REQ_ERR_MASK = 11418; // 8 +const static uint64_t SH_FLD_MUOP_ERROR_1 = 11419; // 4 +const static uint64_t SH_FLD_MUOP_ERROR_2 = 11420; // 4 +const static uint64_t SH_FLD_MUOP_ERROR_3 = 11421; // 4 +const static uint64_t SH_FLD_MUXEN = 11422; // 4 +const static uint64_t SH_FLD_MUXSEL = 11423; // 4 +const static uint64_t SH_FLD_MUXSEL_LEN = 11424; // 4 +const static uint64_t SH_FLD_M_0_STEP_ALIGN_FSM_STATE = 11425; // 1 +const static uint64_t SH_FLD_M_0_STEP_ALIGN_FSM_STATE_LEN = 11426; // 1 +const static uint64_t SH_FLD_M_1_STEP_ALIGN_FSM_STATE = 11427; // 1 +const static uint64_t SH_FLD_M_1_STEP_ALIGN_FSM_STATE_LEN = 11428; // 1 +const static uint64_t SH_FLD_M_CPS_ENABLE = 11429; // 1 +const static uint64_t SH_FLD_M_PATH_0_OSC_NOT_VALID = 11430; // 1 +const static uint64_t SH_FLD_M_PATH_0_PARITY = 11431; // 4 +const static uint64_t SH_FLD_M_PATH_0_STEP_ALIGN_THRESHOLD_ENABLE = 11432; // 1 +const static uint64_t SH_FLD_M_PATH_0_STEP_ALIGN_VALID_SWITCH = 11433; // 1 +const static uint64_t SH_FLD_M_PATH_0_STEP_CHECK = 11434; // 4 +const static uint64_t SH_FLD_M_PATH_0_STEP_CHECK_VALID = 11435; // 1 +const static uint64_t SH_FLD_M_PATH_0_STEP_CREATE_THRESHOLD_ENABLE = 11436; // 1 +const static uint64_t SH_FLD_M_PATH_0_SYNC_CREATE_COUNTER_ENABLE = 11437; // 1 +const static uint64_t SH_FLD_M_PATH_1_OSC_NOT_VALID = 11438; // 1 +const static uint64_t SH_FLD_M_PATH_1_PARITY = 11439; // 4 +const static uint64_t SH_FLD_M_PATH_1_STEP_ALIGN_THRESHOLD_ENABLE = 11440; // 1 +const static uint64_t SH_FLD_M_PATH_1_STEP_ALIGN_VALID_SWITCH = 11441; // 1 +const static uint64_t SH_FLD_M_PATH_1_STEP_CHECK = 11442; // 4 +const static uint64_t SH_FLD_M_PATH_1_STEP_CHECK_VALID = 11443; // 1 +const static uint64_t SH_FLD_M_PATH_1_STEP_CREATE_THRESHOLD_ENABLE = 11444; // 1 +const static uint64_t SH_FLD_M_PATH_1_SYNC_CREATE_COUNTER_ENABLE = 11445; // 1 +const static uint64_t SH_FLD_M_PATH_CLOCK_OFF_ENABLE = 11446; // 1 +const static uint64_t SH_FLD_M_PATH_SELECT = 11447; // 1 +const static uint64_t SH_FLD_M_PATH_SWITCH_TRIGGER = 11448; // 1 +const static uint64_t SH_FLD_N0DGD = 11449; // 12 +const static uint64_t SH_FLD_N0REQ = 11450; // 12 +const static uint64_t SH_FLD_N0RSP = 11451; // 12 +const static uint64_t SH_FLD_N1DGD = 11452; // 12 +const static uint64_t SH_FLD_N1REQ = 11453; // 12 +const static uint64_t SH_FLD_N1RSP = 11454; // 12 +const static uint64_t SH_FLD_NACK_RECEIVED_ERROR_0 = 11455; // 4 +const static uint64_t SH_FLD_NACK_RECEIVED_ERROR_1 = 11456; // 2 +const static uint64_t SH_FLD_NACK_RECEIVED_ERROR_2 = 11457; // 2 +const static uint64_t SH_FLD_NACK_RECEIVED_ERROR_3 = 11458; // 2 +const static uint64_t SH_FLD_NB_CLEAN_SLOT = 11459; // 6 +const static uint64_t SH_FLD_NB_CLEAN_SLOT_LEN = 11460; // 6 +const static uint64_t SH_FLD_NB_WRITE_SLOT = 11461; // 6 +const static uint64_t SH_FLD_NB_WRITE_SLOT_LEN = 11462; // 6 +const static uint64_t SH_FLD_NCU_POWERBUS_DATA_TIMEOUT = 11463; // 12 +const static uint64_t SH_FLD_NCU_PURGE = 11464; // 12 +const static uint64_t SH_FLD_NCU_PURGE_ABORT = 11465; // 12 +const static uint64_t SH_FLD_NCU_PURGE_DONE = 11466; // 24 +const static uint64_t SH_FLD_NCU_SNP_TLBIE_CNT_THRESH = 11467; // 1 +const static uint64_t SH_FLD_NCU_SNP_TLBIE_CNT_THRESH_LEN = 11468; // 1 +const static uint64_t SH_FLD_NCU_SNP_TLBIE_DEC_RATE = 11469; // 1 +const static uint64_t SH_FLD_NCU_SNP_TLBIE_DEC_RATE_LEN = 11470; // 1 +const static uint64_t SH_FLD_NCU_SNP_TLBIE_INC_RATE = 11471; // 1 +const static uint64_t SH_FLD_NCU_SNP_TLBIE_INC_RATE_LEN = 11472; // 1 +const static uint64_t SH_FLD_NCU_SNP_TLBIE_PACING_CNT_EN = 11473; // 1 +const static uint64_t SH_FLD_NCU_TLBIE_QUIESCE = 11474; // 12 +const static uint64_t SH_FLD_NDLMUX_BRK0TO2 = 11475; // 1 +const static uint64_t SH_FLD_NDLMUX_BRK0TO2_LEN = 11476; // 1 +const static uint64_t SH_FLD_NDL_BRK0_NOSTALL = 11477; // 1 +const static uint64_t SH_FLD_NDL_BRK0_STALL = 11478; // 1 +const static uint64_t SH_FLD_NDL_BRK1_NOSTALL = 11479; // 1 +const static uint64_t SH_FLD_NDL_BRK1_STALL = 11480; // 1 +const static uint64_t SH_FLD_NDL_BRK2_NOSTALL = 11481; // 1 +const static uint64_t SH_FLD_NDL_BRK2_STALL = 11482; // 1 +const static uint64_t SH_FLD_NDL_BRK3_NOSTALL = 11483; // 1 +const static uint64_t SH_FLD_NDL_BRK3_STALL = 11484; // 1 +const static uint64_t SH_FLD_NDL_BRK4_NOSTALL = 11485; // 1 +const static uint64_t SH_FLD_NDL_BRK4_STALL = 11486; // 1 +const static uint64_t SH_FLD_NDL_BRK5_NOSTALL = 11487; // 1 +const static uint64_t SH_FLD_NDL_BRK5_STALL = 11488; // 1 +const static uint64_t SH_FLD_NDL_PRI_PARITY_ENA = 11489; // 6 +const static uint64_t SH_FLD_NDL_RX_PARITY_ENA = 11490; // 6 +const static uint64_t SH_FLD_NDL_TX_PARITY_ENA = 11491; // 6 +const static uint64_t SH_FLD_NDT0_RESERVED1 = 11492; // 12 +const static uint64_t SH_FLD_NDT0_RESERVED2 = 11493; // 12 +const static uint64_t SH_FLD_NDT0_RESERVED2_LEN = 11494; // 12 +const static uint64_t SH_FLD_NDT1_RESERVED1 = 11495; // 12 +const static uint64_t SH_FLD_NDT1_RESERVED2 = 11496; // 12 +const static uint64_t SH_FLD_NDT1_RESERVED2_LEN = 11497; // 12 +const static uint64_t SH_FLD_NEAR_NODAL_EPSILON = 11498; // 8 +const static uint64_t SH_FLD_NEAR_NODAL_EPSILON_LEN = 11499; // 8 +const static uint64_t SH_FLD_NEST_DBG_SEL_IN = 11500; // 8 +const static uint64_t SH_FLD_NEST_DBG_SEL_WRT = 11501; // 8 +const static uint64_t SH_FLD_NEST_LIMIT = 11502; // 24 +const static uint64_t SH_FLD_NEST_LIMIT_LEN = 11503; // 24 +const static uint64_t SH_FLD_NETWORK_RESET_OCCURRED = 11504; // 30 +const static uint64_t SH_FLD_NEXT_RANK = 11505; // 8 +const static uint64_t SH_FLD_NEXT_RANK_LEN = 11506; // 8 +const static uint64_t SH_FLD_NEXT_RANK_PAIR = 11507; // 8 +const static uint64_t SH_FLD_NEXT_RANK_PAIR_LEN = 11508; // 8 +const static uint64_t SH_FLD_NFIRACTION0 = 11509; // 9 +const static uint64_t SH_FLD_NFIRACTION0_LEN = 11510; // 9 +const static uint64_t SH_FLD_NFIRACTION1 = 11511; // 9 +const static uint64_t SH_FLD_NFIRACTION1_LEN = 11512; // 9 +const static uint64_t SH_FLD_NMCMD = 11513; // 6 +const static uint64_t SH_FLD_NMCMD_LEN = 11514; // 6 +const static uint64_t SH_FLD_NMEXCMD = 11515; // 6 +const static uint64_t SH_FLD_NMEXCMD_LEN = 11516; // 6 +const static uint64_t SH_FLD_NMMU = 11517; // 3 +const static uint64_t SH_FLD_NMMU_LOCAL_XSTOP = 11518; // 1 +const static uint64_t SH_FLD_NONBAR_PE = 11519; // 9 +const static uint64_t SH_FLD_NONBAR_PE_MASK = 11520; // 9 +const static uint64_t SH_FLD_NONRD_ARE_ERRORS = 11521; // 9 +const static uint64_t SH_FLD_NONRD_ARE_ERRORS_MASK = 11522; // 9 +const static uint64_t SH_FLD_NONSLS_CNTR_TAP_PTS = 11523; // 4 +const static uint64_t SH_FLD_NONSLS_CNTR_TAP_PTS_LEN = 11524; // 4 +const static uint64_t SH_FLD_NONZERO_CSB_CC = 11525; // 1 +const static uint64_t SH_FLD_NOTIFY_FAILED_ERR = 11526; // 2 +const static uint64_t SH_FLD_NOT_TRIGGER_MODE1 = 11527; // 86 +const static uint64_t SH_FLD_NOT_TRIGGER_MODE2 = 11528; // 86 +const static uint64_t SH_FLD_NOT_USED_0 = 11529; // 2 +const static uint64_t SH_FLD_NOT_USED_0_LEN = 11530; // 2 +const static uint64_t SH_FLD_NOT_USED_1 = 11531; // 1 +const static uint64_t SH_FLD_NOT_USED_1_LEN = 11532; // 1 +const static uint64_t SH_FLD_NOT_USED_2 = 11533; // 1 +const static uint64_t SH_FLD_NOT_USED_2_LEN = 11534; // 1 +const static uint64_t SH_FLD_NOT_USED_3 = 11535; // 1 +const static uint64_t SH_FLD_NOT_USED_3_LEN = 11536; // 1 +const static uint64_t SH_FLD_NO_WAIT_ON_CLK_CMD = 11537; // 43 +const static uint64_t SH_FLD_NRE_ERR_REG_DP16 = 11538; // 8 +const static uint64_t SH_FLD_NRE_ERR_REG_DP16_LEN = 11539; // 8 +const static uint64_t SH_FLD_NR_OF_FRAMES = 11540; // 1 +const static uint64_t SH_FLD_NSEG_MAIN_EN = 11541; // 6 +const static uint64_t SH_FLD_NSEG_MAIN_EN_LEN = 11542; // 6 +const static uint64_t SH_FLD_NSEG_MARGINPD_EN = 11543; // 6 +const static uint64_t SH_FLD_NSEG_MARGINPD_EN_LEN = 11544; // 6 +const static uint64_t SH_FLD_NSEG_MARGINPU_EN = 11545; // 6 +const static uint64_t SH_FLD_NSEG_MARGINPU_EN_LEN = 11546; // 6 +const static uint64_t SH_FLD_NSEG_POST_EN = 11547; // 2 +const static uint64_t SH_FLD_NSEG_POST_EN_LEN = 11548; // 2 +const static uint64_t SH_FLD_NSEG_POST_SEL = 11549; // 2 +const static uint64_t SH_FLD_NSEG_POST_SEL_LEN = 11550; // 2 +const static uint64_t SH_FLD_NSEG_PRE_EN = 11551; // 6 +const static uint64_t SH_FLD_NSEG_PRE_EN_LEN = 11552; // 6 +const static uint64_t SH_FLD_NSEG_PRE_SEL = 11553; // 6 +const static uint64_t SH_FLD_NSEG_PRE_SEL_LEN = 11554; // 6 +const static uint64_t SH_FLD_NSL_FILL_COUNT = 11555; // 43 +const static uint64_t SH_FLD_NSL_FILL_COUNT_LEN = 11556; // 43 +const static uint64_t SH_FLD_NSQ_LFSR_CNTL = 11557; // 8 +const static uint64_t SH_FLD_NSQ_LFSR_CNTL_LEN = 11558; // 8 +const static uint64_t SH_FLD_NTLR_PAUSE_THRESH = 11559; // 3 +const static uint64_t SH_FLD_NTLR_PAUSE_THRESH_LEN = 11560; // 3 +const static uint64_t SH_FLD_NTLW_PAUSE_THRESH = 11561; // 3 +const static uint64_t SH_FLD_NTLW_PAUSE_THRESH_LEN = 11562; // 3 +const static uint64_t SH_FLD_NTL_0 = 11563; // 36 +const static uint64_t SH_FLD_NTL_1 = 11564; // 36 +const static uint64_t SH_FLD_NTL_10 = 11565; // 36 +const static uint64_t SH_FLD_NTL_11 = 11566; // 36 +const static uint64_t SH_FLD_NTL_12 = 11567; // 36 +const static uint64_t SH_FLD_NTL_13 = 11568; // 36 +const static uint64_t SH_FLD_NTL_14 = 11569; // 36 +const static uint64_t SH_FLD_NTL_15 = 11570; // 36 +const static uint64_t SH_FLD_NTL_16 = 11571; // 36 +const static uint64_t SH_FLD_NTL_17 = 11572; // 36 +const static uint64_t SH_FLD_NTL_18 = 11573; // 36 +const static uint64_t SH_FLD_NTL_19 = 11574; // 36 +const static uint64_t SH_FLD_NTL_2 = 11575; // 36 +const static uint64_t SH_FLD_NTL_20 = 11576; // 36 +const static uint64_t SH_FLD_NTL_21 = 11577; // 36 +const static uint64_t SH_FLD_NTL_22 = 11578; // 36 +const static uint64_t SH_FLD_NTL_23 = 11579; // 36 +const static uint64_t SH_FLD_NTL_24 = 11580; // 36 +const static uint64_t SH_FLD_NTL_25 = 11581; // 36 +const static uint64_t SH_FLD_NTL_26 = 11582; // 36 +const static uint64_t SH_FLD_NTL_27 = 11583; // 36 +const static uint64_t SH_FLD_NTL_28 = 11584; // 36 +const static uint64_t SH_FLD_NTL_29 = 11585; // 36 +const static uint64_t SH_FLD_NTL_3 = 11586; // 36 +const static uint64_t SH_FLD_NTL_30 = 11587; // 36 +const static uint64_t SH_FLD_NTL_31 = 11588; // 36 +const static uint64_t SH_FLD_NTL_32 = 11589; // 36 +const static uint64_t SH_FLD_NTL_33 = 11590; // 36 +const static uint64_t SH_FLD_NTL_34 = 11591; // 36 +const static uint64_t SH_FLD_NTL_35 = 11592; // 36 +const static uint64_t SH_FLD_NTL_36 = 11593; // 36 +const static uint64_t SH_FLD_NTL_37 = 11594; // 36 +const static uint64_t SH_FLD_NTL_38 = 11595; // 36 +const static uint64_t SH_FLD_NTL_39 = 11596; // 36 +const static uint64_t SH_FLD_NTL_4 = 11597; // 36 +const static uint64_t SH_FLD_NTL_40 = 11598; // 36 +const static uint64_t SH_FLD_NTL_41 = 11599; // 36 +const static uint64_t SH_FLD_NTL_42 = 11600; // 36 +const static uint64_t SH_FLD_NTL_43 = 11601; // 36 +const static uint64_t SH_FLD_NTL_44 = 11602; // 36 +const static uint64_t SH_FLD_NTL_45 = 11603; // 36 +const static uint64_t SH_FLD_NTL_46 = 11604; // 36 +const static uint64_t SH_FLD_NTL_47 = 11605; // 36 +const static uint64_t SH_FLD_NTL_48 = 11606; // 36 +const static uint64_t SH_FLD_NTL_49 = 11607; // 36 +const static uint64_t SH_FLD_NTL_5 = 11608; // 36 +const static uint64_t SH_FLD_NTL_50 = 11609; // 36 +const static uint64_t SH_FLD_NTL_51 = 11610; // 36 +const static uint64_t SH_FLD_NTL_52 = 11611; // 36 +const static uint64_t SH_FLD_NTL_53 = 11612; // 36 +const static uint64_t SH_FLD_NTL_54 = 11613; // 36 +const static uint64_t SH_FLD_NTL_55 = 11614; // 36 +const static uint64_t SH_FLD_NTL_56 = 11615; // 36 +const static uint64_t SH_FLD_NTL_57 = 11616; // 36 +const static uint64_t SH_FLD_NTL_58 = 11617; // 36 +const static uint64_t SH_FLD_NTL_59 = 11618; // 36 +const static uint64_t SH_FLD_NTL_6 = 11619; // 36 +const static uint64_t SH_FLD_NTL_60 = 11620; // 36 +const static uint64_t SH_FLD_NTL_61 = 11621; // 36 +const static uint64_t SH_FLD_NTL_62 = 11622; // 36 +const static uint64_t SH_FLD_NTL_63 = 11623; // 36 +const static uint64_t SH_FLD_NTL_7 = 11624; // 36 +const static uint64_t SH_FLD_NTL_8 = 11625; // 36 +const static uint64_t SH_FLD_NTL_9 = 11626; // 36 +const static uint64_t SH_FLD_NTL_ARRAY_CE = 11627; // 1 +const static uint64_t SH_FLD_NTL_ARRAY_DATA_SUE = 11628; // 1 +const static uint64_t SH_FLD_NTL_ARRAY_DATA_UE = 11629; // 1 +const static uint64_t SH_FLD_NTL_ARRAY_HDR_UE = 11630; // 1 +const static uint64_t SH_FLD_NTL_LMD_POISON = 11631; // 1 +const static uint64_t SH_FLD_NTL_LOGIC_ERR = 11632; // 1 +const static uint64_t SH_FLD_NTL_NVL_CONFIG_ERR = 11633; // 1 +const static uint64_t SH_FLD_NTL_NVL_CRC_ERR = 11634; // 1 +const static uint64_t SH_FLD_NTL_NVL_DATA_PERR = 11635; // 1 +const static uint64_t SH_FLD_NTL_NVL_FLIT_PERR = 11636; // 1 +const static uint64_t SH_FLD_NTL_NVL_PKT_MALFOR = 11637; // 1 +const static uint64_t SH_FLD_NTL_NVL_PKT_UNSUPPORTED = 11638; // 1 +const static uint64_t SH_FLD_NTL_PRI_ERR = 11639; // 1 +const static uint64_t SH_FLD_NTL_RESET = 11640; // 6 +const static uint64_t SH_FLD_NTL_RESET_LEN = 11641; // 6 +const static uint64_t SH_FLD_NTTM_MODE = 11642; // 2 +const static uint64_t SH_FLD_NTTM_RW_DATA_DLY = 11643; // 2 +const static uint64_t SH_FLD_NTTM_RW_DATA_DLY_LEN = 11644; // 2 +const static uint64_t SH_FLD_NULL_MSR_LP = 11645; // 46 +const static uint64_t SH_FLD_NULL_MSR_SIBRC = 11646; // 46 +const static uint64_t SH_FLD_NULL_MSR_SIBRC_LEN = 11647; // 46 +const static uint64_t SH_FLD_NULL_MSR_WE = 11648; // 46 +const static uint64_t SH_FLD_NUM_BLOCKS = 11649; // 12 +const static uint64_t SH_FLD_NUM_BLOCKS_LEN = 11650; // 12 +const static uint64_t SH_FLD_NUM_CLEAN = 11651; // 8 +const static uint64_t SH_FLD_NUM_CLEAN_LEN = 11652; // 8 +const static uint64_t SH_FLD_NUM_CL_ACTIVE = 11653; // 8 +const static uint64_t SH_FLD_NUM_CL_ACTIVE_LEN = 11654; // 8 +const static uint64_t SH_FLD_NUM_HA_RSVD = 11655; // 8 +const static uint64_t SH_FLD_NUM_HA_RSVD_LEN = 11656; // 8 +const static uint64_t SH_FLD_NUM_HA_RSVD_SEL = 11657; // 8 +const static uint64_t SH_FLD_NUM_HA_RSVD_SEL_LEN = 11658; // 8 +const static uint64_t SH_FLD_NUM_HPC_RD_RSVD = 11659; // 8 +const static uint64_t SH_FLD_NUM_HPC_RD_RSVD_LEN = 11660; // 8 +const static uint64_t SH_FLD_NUM_HTM_RSVD = 11661; // 8 +const static uint64_t SH_FLD_NUM_HTM_RSVD_LEN = 11662; // 8 +const static uint64_t SH_FLD_NUM_HTM_RSVD_SEL = 11663; // 8 +const static uint64_t SH_FLD_NUM_HTM_RSVD_SEL_LEN = 11664; // 8 +const static uint64_t SH_FLD_NUM_RMW_BUF = 11665; // 8 +const static uint64_t SH_FLD_NUM_RMW_BUF_LEN = 11666; // 8 +const static uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD = 11667; // 8 +const static uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_LEN = 11668; // 8 +const static uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_SEL = 11669; // 8 +const static uint64_t SH_FLD_NUM_SEC_MIRROR_RSVD_SEL_LEN = 11670; // 8 +const static uint64_t SH_FLD_NUM_VALID_SAMPLES = 11671; // 8 +const static uint64_t SH_FLD_NUM_VALID_SAMPLES_LEN = 11672; // 8 +const static uint64_t SH_FLD_NVBE = 11673; // 24 +const static uint64_t SH_FLD_NVDGD0 = 11674; // 3 +const static uint64_t SH_FLD_NVDGD1 = 11675; // 3 +const static uint64_t SH_FLD_NVREQ0 = 11676; // 3 +const static uint64_t SH_FLD_NVREQ1 = 11677; // 3 +const static uint64_t SH_FLD_NVRS0 = 11678; // 3 +const static uint64_t SH_FLD_NVRS1 = 11679; // 3 +const static uint64_t SH_FLD_NV_RESP_RATE1 = 11680; // 12 +const static uint64_t SH_FLD_NV_RESP_RATE1_LEN = 11681; // 12 +const static uint64_t SH_FLD_NV_RESP_RATE2 = 11682; // 12 +const static uint64_t SH_FLD_NV_RESP_RATE2_LEN = 11683; // 12 +const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_ACTION = 11684; // 1 +const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_ENABLE = 11685; // 1 +const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_SELECT = 11686; // 1 +const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_SELECT_LEN = 11687; // 1 +const static uint64_t SH_FLD_NXCQ_ERAT_ARRAY_TYPE = 11688; // 1 +const static uint64_t SH_FLD_NXCQ_HANG_SM_ON_ARE = 11689; // 1 +const static uint64_t SH_FLD_NXCQ_HANG_SM_ON_LINK_FAIL = 11690; // 1 +const static uint64_t SH_FLD_NXCQ_INJECT_MODE = 11691; // 2 +const static uint64_t SH_FLD_NXCQ_INJECT_MODE_LEN = 11692; // 2 +const static uint64_t SH_FLD_NXCQ_INJECT_TYPE = 11693; // 2 +const static uint64_t SH_FLD_NXCQ_INJECT_TYPE_LEN = 11694; // 2 +const static uint64_t SH_FLD_NXCQ_PBCQ_ARRAY = 11695; // 2 +const static uint64_t SH_FLD_NXCQ_PBCQ_ARRAY_LEN = 11696; // 2 +const static uint64_t SH_FLD_NXCQ_PBCQ_INJECT_ENABLE = 11697; // 2 +const static uint64_t SH_FLD_NXCQ_RNG_INJECT_ACTION = 11698; // 1 +const static uint64_t SH_FLD_NXCQ_RNG_INJECT_ENABLE = 11699; // 1 +const static uint64_t SH_FLD_NXCQ_TRACE_CNTL = 11700; // 2 +const static uint64_t SH_FLD_NXCQ_TRACE_CNTL_LEN = 11701; // 2 +const static uint64_t SH_FLD_NX_FREEZE_MODES = 11702; // 2 +const static uint64_t SH_FLD_NX_FREEZE_MODES_LEN = 11703; // 2 +const static uint64_t SH_FLD_NX_LOCAL_XSTOP = 11704; // 2 +const static uint64_t SH_FLD_O = 11705; // 1 +const static uint64_t SH_FLD_O2SCMD_A_N_RESERVED_0 = 11706; // 4 +const static uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_1 = 11707; // 4 +const static uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 = 11708; // 4 +const static uint64_t SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN = 11709; // 4 +const static uint64_t SH_FLD_O2SST_A_N_RESERVED_1_4 = 11710; // 4 +const static uint64_t SH_FLD_O2SST_A_N_RESERVED_1_4_LEN = 11711; // 4 +const static uint64_t SH_FLD_O2SST_A_N_RESERVED_6 = 11712; // 4 +const static uint64_t SH_FLD_O2S_BRIDGE_ENABLE_A_N = 11713; // 4 +const static uint64_t SH_FLD_O2S_CLEAR_STICKY_BITS_A_N = 11714; // 4 +const static uint64_t SH_FLD_O2S_CLOCK_DIVIDER_A_N = 11715; // 4 +const static uint64_t SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN = 11716; // 4 +const static uint64_t SH_FLD_O2S_CPHA_A_N = 11717; // 4 +const static uint64_t SH_FLD_O2S_CPOL_A_N = 11718; // 4 +const static uint64_t SH_FLD_O2S_FRAME_SIZE_A_N = 11719; // 4 +const static uint64_t SH_FLD_O2S_FRAME_SIZE_A_N_LEN = 11720; // 4 +const static uint64_t SH_FLD_O2S_FSM_ERR_A_N = 11721; // 4 +const static uint64_t SH_FLD_O2S_INTER_FRAME_DELAY_A_N = 11722; // 4 +const static uint64_t SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN = 11723; // 4 +const static uint64_t SH_FLD_O2S_IN_COUNT1_A_N = 11724; // 4 +const static uint64_t SH_FLD_O2S_IN_COUNT1_A_N_LEN = 11725; // 4 +const static uint64_t SH_FLD_O2S_IN_COUNT2_A_N = 11726; // 4 +const static uint64_t SH_FLD_O2S_IN_COUNT2_A_N_LEN = 11727; // 4 +const static uint64_t SH_FLD_O2S_IN_DELAY1_A_N = 11728; // 4 +const static uint64_t SH_FLD_O2S_IN_DELAY1_A_N_LEN = 11729; // 4 +const static uint64_t SH_FLD_O2S_IN_DELAY2_A_N = 11730; // 4 +const static uint64_t SH_FLD_O2S_IN_DELAY2_A_N_LEN = 11731; // 4 +const static uint64_t SH_FLD_O2S_NR_OF_FRAMES_A_N = 11732; // 4 +const static uint64_t SH_FLD_O2S_ONGOING_A_N = 11733; // 4 +const static uint64_t SH_FLD_O2S_OUT_COUNT1_A_N = 11734; // 4 +const static uint64_t SH_FLD_O2S_OUT_COUNT1_A_N_LEN = 11735; // 4 +const static uint64_t SH_FLD_O2S_OUT_COUNT2_A_N = 11736; // 4 +const static uint64_t SH_FLD_O2S_OUT_COUNT2_A_N_LEN = 11737; // 4 +const static uint64_t SH_FLD_O2S_RDATA_A_N = 11738; // 4 +const static uint64_t SH_FLD_O2S_RDATA_A_N_LEN = 11739; // 4 +const static uint64_t SH_FLD_O2S_WDATA_A_N = 11740; // 4 +const static uint64_t SH_FLD_O2S_WDATA_A_N_LEN = 11741; // 4 +const static uint64_t SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N = 11742; // 4 +const static uint64_t SH_FLD_OBUF_ABANK = 11743; // 3 +const static uint64_t SH_FLD_OBUF_ABANK_LEN = 11744; // 3 +const static uint64_t SH_FLD_OBUF_AIDX = 11745; // 3 +const static uint64_t SH_FLD_OBUF_AIDX_LEN = 11746; // 3 +const static uint64_t SH_FLD_OBUF_RSRC = 11747; // 3 +const static uint64_t SH_FLD_OBUF_RSRC_LEN = 11748; // 3 +const static uint64_t SH_FLD_OBUF_WSRC = 11749; // 3 +const static uint64_t SH_FLD_OBUF_WSRC_LEN = 11750; // 3 +const static uint64_t SH_FLD_OBWR_MASK = 11751; // 3 +const static uint64_t SH_FLD_OBWR_MASK_LEN = 11752; // 3 +const static uint64_t SH_FLD_OCB_DB_OCI_READ_DATA_PARITY = 11753; // 1 +const static uint64_t SH_FLD_OCB_DB_OCI_READ_DATA_PARITY_MASK = 11754; // 1 +const static uint64_t SH_FLD_OCB_DB_OCI_SLAVE_ERROR = 11755; // 1 +const static uint64_t SH_FLD_OCB_DB_OCI_SLAVE_ERROR_MASK = 11756; // 1 +const static uint64_t SH_FLD_OCB_DB_OCI_TIMEOUT = 11757; // 1 +const static uint64_t SH_FLD_OCB_DB_OCI_TIMEOUT_MASK = 11758; // 1 +const static uint64_t SH_FLD_OCB_DB_PIB_DATA_PARITY_ERR = 11759; // 1 +const static uint64_t SH_FLD_OCB_DB_PIB_DATA_PARITY_ERR_MASK = 11760; // 1 +const static uint64_t SH_FLD_OCB_ERROR = 11761; // 1 +const static uint64_t SH_FLD_OCB_ERROR_MASK = 11762; // 1 +const static uint64_t SH_FLD_OCB_IDC0_ERROR = 11763; // 1 +const static uint64_t SH_FLD_OCB_IDC0_ERROR_MASK = 11764; // 1 +const static uint64_t SH_FLD_OCB_IDC1_ERROR = 11765; // 1 +const static uint64_t SH_FLD_OCB_IDC1_ERROR_MASK = 11766; // 1 +const static uint64_t SH_FLD_OCB_IDC2_ERROR = 11767; // 1 +const static uint64_t SH_FLD_OCB_IDC2_ERROR_MASK = 11768; // 1 +const static uint64_t SH_FLD_OCB_IDC3_ERROR = 11769; // 1 +const static uint64_t SH_FLD_OCB_IDC3_ERROR_MASK = 11770; // 1 +const static uint64_t SH_FLD_OCB_OCISLV_ERR = 11771; // 1 +const static uint64_t SH_FLD_OCB_OCISLV_ERR_LEN = 11772; // 1 +const static uint64_t SH_FLD_OCB_PIB_ADDR_PARITY_ERR = 11773; // 1 +const static uint64_t SH_FLD_OCB_PIB_ADDR_PARITY_ERR_MASK = 11774; // 1 +const static uint64_t SH_FLD_OCC_ACTION_SET = 11775; // 1 +const static uint64_t SH_FLD_OCC_ACTION_SET_LEN = 11776; // 1 +const static uint64_t SH_FLD_OCC_ERROR = 11777; // 1 +const static uint64_t SH_FLD_OCC_FLAGS = 11778; // 1 +const static uint64_t SH_FLD_OCC_FLAGS_LEN = 11779; // 1 +const static uint64_t SH_FLD_OCC_HEARTBEAT_COUNT = 11780; // 7 +const static uint64_t SH_FLD_OCC_HEARTBEAT_COUNT_LEN = 11781; // 7 +const static uint64_t SH_FLD_OCC_HEARTBEAT_EN = 11782; // 1 +const static uint64_t SH_FLD_OCC_HEARTBEAT_ENABLE = 11783; // 6 +const static uint64_t SH_FLD_OCC_HEARTBEAT_LOSS = 11784; // 6 +const static uint64_t SH_FLD_OCC_HEARTBEAT_LOST = 11785; // 12 +const static uint64_t SH_FLD_OCC_MALF_ALERT = 11786; // 1 +const static uint64_t SH_FLD_OCC_SCRATCH_N = 11787; // 3 +const static uint64_t SH_FLD_OCC_SCRATCH_N_LEN = 11788; // 3 +const static uint64_t SH_FLD_OCC_SPCL_TIMEOUT_ADDR = 11789; // 1 +const static uint64_t SH_FLD_OCC_SPCL_TIMEOUT_ADDR_LEN = 11790; // 1 +const static uint64_t SH_FLD_OCC_SPECIAL_WKUP = 11791; // 30 +const static uint64_t SH_FLD_OCC_STRM0_PULL = 11792; // 1 +const static uint64_t SH_FLD_OCC_STRM0_PUSH = 11793; // 1 +const static uint64_t SH_FLD_OCC_STRM1_PULL = 11794; // 1 +const static uint64_t SH_FLD_OCC_STRM1_PUSH = 11795; // 1 +const static uint64_t SH_FLD_OCC_STRM2_PULL = 11796; // 1 +const static uint64_t SH_FLD_OCC_STRM2_PUSH = 11797; // 1 +const static uint64_t SH_FLD_OCC_STRM3_PULL = 11798; // 1 +const static uint64_t SH_FLD_OCC_STRM3_PUSH = 11799; // 1 +const static uint64_t SH_FLD_OCC_TIMER0 = 11800; // 1 +const static uint64_t SH_FLD_OCC_TIMER1 = 11801; // 1 +const static uint64_t SH_FLD_OCC_TRACE_MUX_SEL = 11802; // 1 +const static uint64_t SH_FLD_OCC_TRACE_MUX_SEL_LEN = 11803; // 1 +const static uint64_t SH_FLD_OCICFG_RESERVED_20 = 11804; // 1 +const static uint64_t SH_FLD_OCICFG_RESERVED_23 = 11805; // 1 +const static uint64_t SH_FLD_OCISLV_FAIRNESS_MASK = 11806; // 1 +const static uint64_t SH_FLD_OCISLV_FAIRNESS_MASK_LEN = 11807; // 1 +const static uint64_t SH_FLD_OCISLV_REREQ_HANG_DIV = 11808; // 1 +const static uint64_t SH_FLD_OCISLV_REREQ_HANG_DIV_LEN = 11809; // 1 +const static uint64_t SH_FLD_OCI_APAR_ERR = 11810; // 1 +const static uint64_t SH_FLD_OCI_APAR_ERR_MASK = 11811; // 1 +const static uint64_t SH_FLD_OCI_ARB_RESET = 11812; // 1 +const static uint64_t SH_FLD_OCI_BAD_REG_ADDR = 11813; // 1 +const static uint64_t SH_FLD_OCI_BAD_REG_ADDR_MASK = 11814; // 1 +const static uint64_t SH_FLD_OCI_ERR_INJ_CE_UE = 11815; // 1 +const static uint64_t SH_FLD_OCI_ERR_INJ_DCU = 11816; // 1 +const static uint64_t SH_FLD_OCI_ERR_INJ_ICU = 11817; // 1 +const static uint64_t SH_FLD_OCI_ERR_INJ_SINGL_CONT = 11818; // 1 +const static uint64_t SH_FLD_OCI_HI_BUS_MODE = 11819; // 1 +const static uint64_t SH_FLD_OCI_M0_FLCK = 11820; // 1 +const static uint64_t SH_FLD_OCI_M0_OEAR_LOCK = 11821; // 1 +const static uint64_t SH_FLD_OCI_M0_RW_STATUS = 11822; // 1 +const static uint64_t SH_FLD_OCI_M0_TIMEOUT_ERROR = 11823; // 1 +const static uint64_t SH_FLD_OCI_M1_FLCK = 11824; // 1 +const static uint64_t SH_FLD_OCI_M1_OEAR_LOCK = 11825; // 1 +const static uint64_t SH_FLD_OCI_M1_RW_STATUS = 11826; // 1 +const static uint64_t SH_FLD_OCI_M1_TIMEOUT_ERROR = 11827; // 1 +const static uint64_t SH_FLD_OCI_M2_FLCK = 11828; // 1 +const static uint64_t SH_FLD_OCI_M2_OEAR_LOCK = 11829; // 1 +const static uint64_t SH_FLD_OCI_M2_RW_STATUS = 11830; // 1 +const static uint64_t SH_FLD_OCI_M2_TIMEOUT_ERROR = 11831; // 1 +const static uint64_t SH_FLD_OCI_M3_FLCK = 11832; // 1 +const static uint64_t SH_FLD_OCI_M3_OEAR_LOCK = 11833; // 1 +const static uint64_t SH_FLD_OCI_M3_RW_STATUS = 11834; // 1 +const static uint64_t SH_FLD_OCI_M3_TIMEOUT_ERROR = 11835; // 1 +const static uint64_t SH_FLD_OCI_M4_FLCK = 11836; // 1 +const static uint64_t SH_FLD_OCI_M4_OEAR_LOCK = 11837; // 1 +const static uint64_t SH_FLD_OCI_M4_RW_STATUS = 11838; // 1 +const static uint64_t SH_FLD_OCI_M4_TIMEOUT_ERROR = 11839; // 1 +const static uint64_t SH_FLD_OCI_M5_FLCK = 11840; // 1 +const static uint64_t SH_FLD_OCI_M5_OEAR_LOCK = 11841; // 1 +const static uint64_t SH_FLD_OCI_M5_RW_STATUS = 11842; // 1 +const static uint64_t SH_FLD_OCI_M5_TIMEOUT_ERROR = 11843; // 1 +const static uint64_t SH_FLD_OCI_M6_FLCK = 11844; // 1 +const static uint64_t SH_FLD_OCI_M6_OEAR_LOCK = 11845; // 1 +const static uint64_t SH_FLD_OCI_M6_RW_STATUS = 11846; // 1 +const static uint64_t SH_FLD_OCI_M6_TIMEOUT_ERROR = 11847; // 1 +const static uint64_t SH_FLD_OCI_M7_FLCK = 11848; // 1 +const static uint64_t SH_FLD_OCI_M7_OEAR_LOCK = 11849; // 1 +const static uint64_t SH_FLD_OCI_M7_RW_STATUS = 11850; // 1 +const static uint64_t SH_FLD_OCI_M7_TIMEOUT_ERROR = 11851; // 1 +const static uint64_t SH_FLD_OCI_MARKER_SPACE = 11852; // 1 +const static uint64_t SH_FLD_OCI_MARKER_SPACE_LEN = 11853; // 1 +const static uint64_t SH_FLD_OCI_PRIORITY_MODE = 11854; // 1 +const static uint64_t SH_FLD_OCI_PRIORITY_ORDER = 11855; // 1 +const static uint64_t SH_FLD_OCI_PRIORITY_ORDER_LEN = 11856; // 1 +const static uint64_t SH_FLD_OCI_READ_DATA_PARITY = 11857; // 4 +const static uint64_t SH_FLD_OCI_READ_PIPELINE_CONTROL = 11858; // 1 +const static uint64_t SH_FLD_OCI_READ_PIPELINE_CONTROL_LEN = 11859; // 1 +const static uint64_t SH_FLD_OCI_REGION = 11860; // 4 +const static uint64_t SH_FLD_OCI_REGION_LEN = 11861; // 4 +const static uint64_t SH_FLD_OCI_SLAVE_ERROR = 11862; // 4 +const static uint64_t SH_FLD_OCI_SLAVE_INIT = 11863; // 1 +const static uint64_t SH_FLD_OCI_SLAVE_INIT_MASK = 11864; // 1 +const static uint64_t SH_FLD_OCI_TIMEOUT = 11865; // 4 +const static uint64_t SH_FLD_OCI_TIMEOUT_ADDR = 11866; // 1 +const static uint64_t SH_FLD_OCI_TIMEOUT_ADDR_LEN = 11867; // 1 +const static uint64_t SH_FLD_OCI_TRACE_MUX_SEL = 11868; // 1 +const static uint64_t SH_FLD_OCI_TRACE_MUX_SEL_LEN = 11869; // 1 +const static uint64_t SH_FLD_OCI_WRITE_PIPELINE_CONTROL = 11870; // 1 +const static uint64_t SH_FLD_OCI_WRPAR_ERR = 11871; // 1 +const static uint64_t SH_FLD_OCI_WRPAR_ERR_MASK = 11872; // 1 +const static uint64_t SH_FLD_OCR_DBG_HALT = 11873; // 1 +const static uint64_t SH_FLD_OFFSET = 11874; // 15 +const static uint64_t SH_FLD_OFFSET_LEN = 11875; // 15 +const static uint64_t SH_FLD_OFF_INIT_CFG = 11876; // 6 +const static uint64_t SH_FLD_OFF_INIT_CFG_LEN = 11877; // 6 +const static uint64_t SH_FLD_OFF_INIT_TIMEOUT = 11878; // 6 +const static uint64_t SH_FLD_OFF_INIT_TIMEOUT_LEN = 11879; // 6 +const static uint64_t SH_FLD_OFF_RECAL_CFG = 11880; // 6 +const static uint64_t SH_FLD_OFF_RECAL_CFG_LEN = 11881; // 6 +const static uint64_t SH_FLD_OFF_RECAL_TIMEOUT = 11882; // 6 +const static uint64_t SH_FLD_OFF_RECAL_TIMEOUT_LEN = 11883; // 6 +const static uint64_t SH_FLD_OJCFG_DBG_HALT = 11884; // 1 +const static uint64_t SH_FLD_OJCFG_JTAG_SRC_SEL = 11885; // 1 +const static uint64_t SH_FLD_OJCFG_JTAG_TRST_B = 11886; // 1 +const static uint64_t SH_FLD_OJCFG_RUN_TCK = 11887; // 1 +const static uint64_t SH_FLD_OJCFG_TCK_WIDTH = 11888; // 1 +const static uint64_t SH_FLD_OJCFG_TCK_WIDTH_LEN = 11889; // 1 +const static uint64_t SH_FLD_OJIC_DO_DR = 11890; // 1 +const static uint64_t SH_FLD_OJIC_DO_IR = 11891; // 1 +const static uint64_t SH_FLD_OJIC_DO_TAP_RESET = 11892; // 1 +const static uint64_t SH_FLD_OJIC_JTAG_INSTR = 11893; // 1 +const static uint64_t SH_FLD_OJIC_JTAG_INSTR_LEN = 11894; // 1 +const static uint64_t SH_FLD_OJIC_WR_VALID = 11895; // 1 +const static uint64_t SH_FLD_OJSTAT_FSM_ERROR = 11896; // 1 +const static uint64_t SH_FLD_OJSTAT_INPROG_WR_ERR = 11897; // 1 +const static uint64_t SH_FLD_OJSTAT_IR_DR_EQ0_ERR = 11898; // 1 +const static uint64_t SH_FLD_OJSTAT_JTAG_INPROG = 11899; // 1 +const static uint64_t SH_FLD_OJSTAT_RUN_TCK_EQ0_ERR = 11900; // 1 +const static uint64_t SH_FLD_OJSTAT_SRC_SEL_EQ1_ERR = 11901; // 1 +const static uint64_t SH_FLD_OJSTAT_TRST_B_EQ0_ERR = 11902; // 1 +const static uint64_t SH_FLD_ONESHOT0 = 11903; // 24 +const static uint64_t SH_FLD_ONESHOT1 = 11904; // 24 +const static uint64_t SH_FLD_ONE_PPC = 11905; // 24 +const static uint64_t SH_FLD_ONGOING = 11906; // 1 +const static uint64_t SH_FLD_ONL = 11907; // 96 +const static uint64_t SH_FLD_OOB_MUX = 11908; // 3 +const static uint64_t SH_FLD_OPB_ERROR = 11909; // 4 +const static uint64_t SH_FLD_OPB_MASTER_HANG_TIMEOUT = 11910; // 4 +const static uint64_t SH_FLD_OPB_PARITY_ERROR = 11911; // 3 +const static uint64_t SH_FLD_OPB_TIMEOUT = 11912; // 4 +const static uint64_t SH_FLD_OPCG_IP = 11913; // 43 +const static uint64_t SH_FLD_OPCODE = 11914; // 1 +const static uint64_t SH_FLD_OPCODE_LEN = 11915; // 1 +const static uint64_t SH_FLD_OPER = 11916; // 1 +const static uint64_t SH_FLD_OPER_LEN = 11917; // 1 +const static uint64_t SH_FLD_OPTION_PIB_RESET = 11918; // 1 +const static uint64_t SH_FLD_OSCILLATOR = 11919; // 1 +const static uint64_t SH_FLD_OSCILLATOR_LEN = 11920; // 1 +const static uint64_t SH_FLD_OSCSWITCH_CNTL0_DC = 11921; // 3 +const static uint64_t SH_FLD_OSCSWITCH_CNTL0_DC_LEN = 11922; // 3 +const static uint64_t SH_FLD_OSCSWITCH_CNTL1_DC = 11923; // 3 +const static uint64_t SH_FLD_OSCSWITCH_CNTL1_DC_LEN = 11924; // 3 +const static uint64_t SH_FLD_OSCSWITCH_INTERRUPT = 11925; // 4 +const static uint64_t SH_FLD_OS_STATUS_DISABLE_A_N = 11926; // 96 +const static uint64_t SH_FLD_OTHER_SCOM_SAT = 11927; // 1 +const static uint64_t SH_FLD_OTP = 11928; // 1 +const static uint64_t SH_FLD_OTP_LEN = 11929; // 1 +const static uint64_t SH_FLD_OTR_SPECIAL_WKUP = 11930; // 30 +const static uint64_t SH_FLD_OUT = 11931; // 1 +const static uint64_t SH_FLD_OUTER_LOOP_CNT = 11932; // 8 +const static uint64_t SH_FLD_OUTER_LOOP_CNT_LEN = 11933; // 8 +const static uint64_t SH_FLD_OUTWR_INRD_ECC_CE = 11934; // 1 +const static uint64_t SH_FLD_OUTWR_INRD_ECC_SUE = 11935; // 1 +const static uint64_t SH_FLD_OUTWR_INRD_ECC_UE = 11936; // 1 +const static uint64_t SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR = 11937; // 6 +const static uint64_t SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR = 11938; // 6 +const static uint64_t SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR = 11939; // 6 +const static uint64_t SH_FLD_OUT_COUNT1 = 11940; // 1 +const static uint64_t SH_FLD_OUT_COUNT1_LEN = 11941; // 1 +const static uint64_t SH_FLD_OUT_COUNT2 = 11942; // 1 +const static uint64_t SH_FLD_OUT_COUNT2_LEN = 11943; // 1 +const static uint64_t SH_FLD_OUT_LEN = 11944; // 1 +const static uint64_t SH_FLD_OUT_RRB_SOURCED_ERROR = 11945; // 6 +const static uint64_t SH_FLD_OVERFLOW_CHECKSTOP = 11946; // 2 +const static uint64_t SH_FLD_OVERFLOW_ERR = 11947; // 43 +const static uint64_t SH_FLD_OVERFLOW_ERROR = 11948; // 2 +const static uint64_t SH_FLD_OVERFLOW_MASK = 11949; // 43 +const static uint64_t SH_FLD_OVERRIDE = 11950; // 8 +const static uint64_t SH_FLD_OVERRIDE_EN = 11951; // 24 +const static uint64_t SH_FLD_OVERRIDE_PBINIT_ERR_CMD = 11952; // 1 +const static uint64_t SH_FLD_OVERRIDE_PBINIT_HTM_CMD = 11953; // 1 +const static uint64_t SH_FLD_OVERRIDE_PBINIT_TOD_CMD = 11954; // 1 +const static uint64_t SH_FLD_OVERRIDE_PBINIT_TRACE_CMD = 11955; // 1 +const static uint64_t SH_FLD_OVERRIDE_PBINIT_XSCOM_CMD = 11956; // 1 +const static uint64_t SH_FLD_OVERRUN = 11957; // 8 +const static uint64_t SH_FLD_OVER_OR_UNDERRUN_ERR = 11958; // 1 +const static uint64_t SH_FLD_OVR_PM = 11959; // 1 +const static uint64_t SH_FLD_OWN_ID_THIS_SLAVE = 11960; // 2 +const static uint64_t SH_FLD_OWN_ID_THIS_SLAVE_LEN = 11961; // 2 +const static uint64_t SH_FLD_P0_IS_IDLE = 11962; // 4 +const static uint64_t SH_FLD_P1_IS_IDLE = 11963; // 4 +const static uint64_t SH_FLD_P9_TO_P9_MODE = 11964; // 6 +const static uint64_t SH_FLD_PACE = 11965; // 2 +const static uint64_t SH_FLD_PACE_LEN = 11966; // 2 +const static uint64_t SH_FLD_PACE_RATE = 11967; // 1 +const static uint64_t SH_FLD_PACE_RATE_LEN = 11968; // 1 +const static uint64_t SH_FLD_PACING_ALLOW_0 = 11969; // 2 +const static uint64_t SH_FLD_PACING_ALLOW_1 = 11970; // 1 +const static uint64_t SH_FLD_PACING_ALLOW_2 = 11971; // 1 +const static uint64_t SH_FLD_PACING_ALLOW_3 = 11972; // 1 +const static uint64_t SH_FLD_PAGE_OFFSET_CFG = 11973; // 1 +const static uint64_t SH_FLD_PAGE_OFFSET_CFG_LEN = 11974; // 1 +const static uint64_t SH_FLD_PAGE_SIZE_64K = 11975; // 4 +const static uint64_t SH_FLD_PAGE_SIZE_64K_PC = 11976; // 1 +const static uint64_t SH_FLD_PAGE_SIZE_64K_VC = 11977; // 1 +const static uint64_t SH_FLD_PAIR0_QUA = 11978; // 8 +const static uint64_t SH_FLD_PAIR0_QUA_LEN = 11979; // 8 +const static uint64_t SH_FLD_PAIR0_QUA_V = 11980; // 8 +const static uint64_t SH_FLD_PAIR0_TER = 11981; // 8 +const static uint64_t SH_FLD_PAIR0_TER_LEN = 11982; // 8 +const static uint64_t SH_FLD_PAIR0_TER_V = 11983; // 8 +const static uint64_t SH_FLD_PAIR1_PRI = 11984; // 8 +const static uint64_t SH_FLD_PAIR1_PRI_LEN = 11985; // 8 +const static uint64_t SH_FLD_PAIR1_PRI_V = 11986; // 8 +const static uint64_t SH_FLD_PAIR1_QUA = 11987; // 8 +const static uint64_t SH_FLD_PAIR1_QUA_LEN = 11988; // 8 +const static uint64_t SH_FLD_PAIR1_QUA_V = 11989; // 8 +const static uint64_t SH_FLD_PAIR1_SEC = 11990; // 8 +const static uint64_t SH_FLD_PAIR1_SEC_LEN = 11991; // 8 +const static uint64_t SH_FLD_PAIR1_SEC_V = 11992; // 8 +const static uint64_t SH_FLD_PAIR1_TER = 11993; // 8 +const static uint64_t SH_FLD_PAIR1_TER_LEN = 11994; // 8 +const static uint64_t SH_FLD_PAIR1_TER_V = 11995; // 8 +const static uint64_t SH_FLD_PAIR2_PRI = 11996; // 8 +const static uint64_t SH_FLD_PAIR2_PRI_LEN = 11997; // 8 +const static uint64_t SH_FLD_PAIR2_PRI_V = 11998; // 8 +const static uint64_t SH_FLD_PAIR2_QUA = 11999; // 8 +const static uint64_t SH_FLD_PAIR2_QUA_LEN = 12000; // 8 +const static uint64_t SH_FLD_PAIR2_QUA_V = 12001; // 8 +const static uint64_t SH_FLD_PAIR2_SEC = 12002; // 8 +const static uint64_t SH_FLD_PAIR2_SEC_LEN = 12003; // 8 +const static uint64_t SH_FLD_PAIR2_SEC_V = 12004; // 8 +const static uint64_t SH_FLD_PAIR2_TER = 12005; // 8 +const static uint64_t SH_FLD_PAIR2_TER_LEN = 12006; // 8 +const static uint64_t SH_FLD_PAIR2_TER_V = 12007; // 8 +const static uint64_t SH_FLD_PAIR3_PRI = 12008; // 8 +const static uint64_t SH_FLD_PAIR3_PRI_LEN = 12009; // 8 +const static uint64_t SH_FLD_PAIR3_PRI_V = 12010; // 8 +const static uint64_t SH_FLD_PAIR3_SEC = 12011; // 8 +const static uint64_t SH_FLD_PAIR3_SEC_LEN = 12012; // 8 +const static uint64_t SH_FLD_PAIR3_SEC_V = 12013; // 8 +const static uint64_t SH_FLD_PAPR_INBOUND_INJECT_ERROR = 12014; // 6 +const static uint64_t SH_FLD_PAPR_OUTBOUND_INJECT_ERROR = 12015; // 6 +const static uint64_t SH_FLD_PARALLEL_ADDR_INVALID = 12016; // 43 +const static uint64_t SH_FLD_PARALLEL_READ_NVLD = 12017; // 43 +const static uint64_t SH_FLD_PARALLEL_WRITE_NVLD = 12018; // 43 +const static uint64_t SH_FLD_PARANOIA_TEST_ENABLE_CHANGE = 12019; // 43 +const static uint64_t SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE = 12020; // 43 +const static uint64_t SH_FLD_PARITY = 12021; // 45 +const static uint64_t SH_FLD_PARITY_CHECK = 12022; // 1 +const static uint64_t SH_FLD_PARITY_ERR = 12023; // 4 +const static uint64_t SH_FLD_PARITY_ERR2 = 12024; // 3 +const static uint64_t SH_FLD_PARITY_ERROR = 12025; // 51 +const static uint64_t SH_FLD_PARITY_ERROR_SUE_ENA = 12026; // 6 +const static uint64_t SH_FLD_PARITY_ON_INTERFACE_MACHINE = 12027; // 43 +const static uint64_t SH_FLD_PARITY_ON_P2S_MACHINE = 12028; // 43 +const static uint64_t SH_FLD_PARSER00_ATTN = 12029; // 4 +const static uint64_t SH_FLD_PARSER01_ATTN = 12030; // 4 +const static uint64_t SH_FLD_PARSER02_ATTN = 12031; // 4 +const static uint64_t SH_FLD_PARSER03_ATTN = 12032; // 4 +const static uint64_t SH_FLD_PARSER04_ATTN = 12033; // 4 +const static uint64_t SH_FLD_PARSER05_ATTN = 12034; // 4 +const static uint64_t SH_FLD_PARSER06_ATTN = 12035; // 2 +const static uint64_t SH_FLD_PARSER07_ATTN = 12036; // 2 +const static uint64_t SH_FLD_PART_0 = 12037; // 2 +const static uint64_t SH_FLD_PART_0_LEN = 12038; // 2 +const static uint64_t SH_FLD_PART_1 = 12039; // 2 +const static uint64_t SH_FLD_PART_10 = 12040; // 2 +const static uint64_t SH_FLD_PART_10_LEN = 12041; // 2 +const static uint64_t SH_FLD_PART_11 = 12042; // 2 +const static uint64_t SH_FLD_PART_11_LEN = 12043; // 2 +const static uint64_t SH_FLD_PART_12 = 12044; // 2 +const static uint64_t SH_FLD_PART_12_LEN = 12045; // 2 +const static uint64_t SH_FLD_PART_13 = 12046; // 2 +const static uint64_t SH_FLD_PART_13_LEN = 12047; // 2 +const static uint64_t SH_FLD_PART_14 = 12048; // 2 +const static uint64_t SH_FLD_PART_14_LEN = 12049; // 2 +const static uint64_t SH_FLD_PART_15 = 12050; // 2 +const static uint64_t SH_FLD_PART_15_LEN = 12051; // 2 +const static uint64_t SH_FLD_PART_16 = 12052; // 2 +const static uint64_t SH_FLD_PART_16_LEN = 12053; // 2 +const static uint64_t SH_FLD_PART_17 = 12054; // 2 +const static uint64_t SH_FLD_PART_17_LEN = 12055; // 2 +const static uint64_t SH_FLD_PART_18 = 12056; // 2 +const static uint64_t SH_FLD_PART_18_LEN = 12057; // 2 +const static uint64_t SH_FLD_PART_19 = 12058; // 2 +const static uint64_t SH_FLD_PART_19_LEN = 12059; // 2 +const static uint64_t SH_FLD_PART_1_LEN = 12060; // 2 +const static uint64_t SH_FLD_PART_2 = 12061; // 2 +const static uint64_t SH_FLD_PART_20 = 12062; // 2 +const static uint64_t SH_FLD_PART_20_LEN = 12063; // 2 +const static uint64_t SH_FLD_PART_21 = 12064; // 2 +const static uint64_t SH_FLD_PART_21_LEN = 12065; // 2 +const static uint64_t SH_FLD_PART_22 = 12066; // 2 +const static uint64_t SH_FLD_PART_22_LEN = 12067; // 2 +const static uint64_t SH_FLD_PART_23 = 12068; // 2 +const static uint64_t SH_FLD_PART_23_LEN = 12069; // 2 +const static uint64_t SH_FLD_PART_24 = 12070; // 2 +const static uint64_t SH_FLD_PART_24_LEN = 12071; // 2 +const static uint64_t SH_FLD_PART_25 = 12072; // 2 +const static uint64_t SH_FLD_PART_25_LEN = 12073; // 2 +const static uint64_t SH_FLD_PART_26 = 12074; // 2 +const static uint64_t SH_FLD_PART_26_LEN = 12075; // 2 +const static uint64_t SH_FLD_PART_27 = 12076; // 2 +const static uint64_t SH_FLD_PART_27_LEN = 12077; // 2 +const static uint64_t SH_FLD_PART_28 = 12078; // 2 +const static uint64_t SH_FLD_PART_28_LEN = 12079; // 2 +const static uint64_t SH_FLD_PART_29 = 12080; // 2 +const static uint64_t SH_FLD_PART_29_LEN = 12081; // 2 +const static uint64_t SH_FLD_PART_2_LEN = 12082; // 2 +const static uint64_t SH_FLD_PART_3 = 12083; // 2 +const static uint64_t SH_FLD_PART_30 = 12084; // 2 +const static uint64_t SH_FLD_PART_30_LEN = 12085; // 2 +const static uint64_t SH_FLD_PART_31 = 12086; // 2 +const static uint64_t SH_FLD_PART_31_LEN = 12087; // 2 +const static uint64_t SH_FLD_PART_32 = 12088; // 2 +const static uint64_t SH_FLD_PART_32_LEN = 12089; // 2 +const static uint64_t SH_FLD_PART_33 = 12090; // 2 +const static uint64_t SH_FLD_PART_33_LEN = 12091; // 2 +const static uint64_t SH_FLD_PART_34 = 12092; // 2 +const static uint64_t SH_FLD_PART_34_LEN = 12093; // 2 +const static uint64_t SH_FLD_PART_35 = 12094; // 2 +const static uint64_t SH_FLD_PART_35_LEN = 12095; // 2 +const static uint64_t SH_FLD_PART_36 = 12096; // 2 +const static uint64_t SH_FLD_PART_36_LEN = 12097; // 2 +const static uint64_t SH_FLD_PART_37 = 12098; // 2 +const static uint64_t SH_FLD_PART_37_LEN = 12099; // 2 +const static uint64_t SH_FLD_PART_38 = 12100; // 2 +const static uint64_t SH_FLD_PART_38_LEN = 12101; // 2 +const static uint64_t SH_FLD_PART_39 = 12102; // 2 +const static uint64_t SH_FLD_PART_39_LEN = 12103; // 2 +const static uint64_t SH_FLD_PART_3_LEN = 12104; // 2 +const static uint64_t SH_FLD_PART_4 = 12105; // 2 +const static uint64_t SH_FLD_PART_40 = 12106; // 2 +const static uint64_t SH_FLD_PART_40_LEN = 12107; // 2 +const static uint64_t SH_FLD_PART_41 = 12108; // 2 +const static uint64_t SH_FLD_PART_41_LEN = 12109; // 2 +const static uint64_t SH_FLD_PART_42 = 12110; // 2 +const static uint64_t SH_FLD_PART_42_LEN = 12111; // 2 +const static uint64_t SH_FLD_PART_43 = 12112; // 2 +const static uint64_t SH_FLD_PART_43_LEN = 12113; // 2 +const static uint64_t SH_FLD_PART_44 = 12114; // 2 +const static uint64_t SH_FLD_PART_44_LEN = 12115; // 2 +const static uint64_t SH_FLD_PART_45 = 12116; // 2 +const static uint64_t SH_FLD_PART_45_LEN = 12117; // 2 +const static uint64_t SH_FLD_PART_46 = 12118; // 2 +const static uint64_t SH_FLD_PART_46_LEN = 12119; // 2 +const static uint64_t SH_FLD_PART_47 = 12120; // 2 +const static uint64_t SH_FLD_PART_47_LEN = 12121; // 2 +const static uint64_t SH_FLD_PART_48 = 12122; // 2 +const static uint64_t SH_FLD_PART_48_LEN = 12123; // 2 +const static uint64_t SH_FLD_PART_49 = 12124; // 2 +const static uint64_t SH_FLD_PART_49_LEN = 12125; // 2 +const static uint64_t SH_FLD_PART_4_LEN = 12126; // 2 +const static uint64_t SH_FLD_PART_5 = 12127; // 2 +const static uint64_t SH_FLD_PART_50 = 12128; // 2 +const static uint64_t SH_FLD_PART_50_LEN = 12129; // 2 +const static uint64_t SH_FLD_PART_51 = 12130; // 2 +const static uint64_t SH_FLD_PART_51_LEN = 12131; // 2 +const static uint64_t SH_FLD_PART_52 = 12132; // 2 +const static uint64_t SH_FLD_PART_52_LEN = 12133; // 2 +const static uint64_t SH_FLD_PART_53 = 12134; // 2 +const static uint64_t SH_FLD_PART_53_LEN = 12135; // 2 +const static uint64_t SH_FLD_PART_54 = 12136; // 2 +const static uint64_t SH_FLD_PART_54_LEN = 12137; // 2 +const static uint64_t SH_FLD_PART_55 = 12138; // 2 +const static uint64_t SH_FLD_PART_55_LEN = 12139; // 2 +const static uint64_t SH_FLD_PART_56 = 12140; // 2 +const static uint64_t SH_FLD_PART_56_LEN = 12141; // 2 +const static uint64_t SH_FLD_PART_57 = 12142; // 2 +const static uint64_t SH_FLD_PART_57_LEN = 12143; // 2 +const static uint64_t SH_FLD_PART_58 = 12144; // 2 +const static uint64_t SH_FLD_PART_58_LEN = 12145; // 2 +const static uint64_t SH_FLD_PART_59 = 12146; // 2 +const static uint64_t SH_FLD_PART_59_LEN = 12147; // 2 +const static uint64_t SH_FLD_PART_5_LEN = 12148; // 2 +const static uint64_t SH_FLD_PART_6 = 12149; // 2 +const static uint64_t SH_FLD_PART_60 = 12150; // 2 +const static uint64_t SH_FLD_PART_60_LEN = 12151; // 2 +const static uint64_t SH_FLD_PART_61 = 12152; // 2 +const static uint64_t SH_FLD_PART_61_LEN = 12153; // 2 +const static uint64_t SH_FLD_PART_62 = 12154; // 2 +const static uint64_t SH_FLD_PART_62_LEN = 12155; // 2 +const static uint64_t SH_FLD_PART_63 = 12156; // 2 +const static uint64_t SH_FLD_PART_63_LEN = 12157; // 2 +const static uint64_t SH_FLD_PART_6_LEN = 12158; // 2 +const static uint64_t SH_FLD_PART_7 = 12159; // 2 +const static uint64_t SH_FLD_PART_7_LEN = 12160; // 2 +const static uint64_t SH_FLD_PART_8 = 12161; // 2 +const static uint64_t SH_FLD_PART_8_LEN = 12162; // 2 +const static uint64_t SH_FLD_PART_9 = 12163; // 2 +const static uint64_t SH_FLD_PART_9_LEN = 12164; // 2 +const static uint64_t SH_FLD_PAR_17_MASK = 12165; // 8 +const static uint64_t SH_FLD_PAR_ERR_ONLY = 12166; // 8 +const static uint64_t SH_FLD_PAR_INVERT = 12167; // 8 +const static uint64_t SH_FLD_PASS_CQ_INT_PMU_DATA_HI = 12168; // 1 +const static uint64_t SH_FLD_PASS_CQ_INT_PMU_DATA_LO = 12169; // 1 +const static uint64_t SH_FLD_PASS_CQ_INT_TRACE_DATA_HI = 12170; // 1 +const static uint64_t SH_FLD_PASS_CQ_INT_TRACE_DATA_LO = 12171; // 1 +const static uint64_t SH_FLD_PASS_CQ_INT_TRACE_TRIG_01 = 12172; // 1 +const static uint64_t SH_FLD_PASS_CQ_INT_TRACE_TRIG_23 = 12173; // 1 +const static uint64_t SH_FLD_PASS_WC_INT_TRACE_DATA_HI = 12174; // 1 +const static uint64_t SH_FLD_PASS_WC_INT_TRACE_DATA_LO = 12175; // 1 +const static uint64_t SH_FLD_PASS_WC_INT_TRACE_TRIG_01 = 12176; // 1 +const static uint64_t SH_FLD_PASS_WC_INT_TRACE_TRIG_23 = 12177; // 1 +const static uint64_t SH_FLD_PASTE_ADDR_ALIGN = 12178; // 1 +const static uint64_t SH_FLD_PASTE_REJECT = 12179; // 1 +const static uint64_t SH_FLD_PATTERNA = 12180; // 90 +const static uint64_t SH_FLD_PATTERNA_LEN = 12181; // 90 +const static uint64_t SH_FLD_PATTERNB = 12182; // 90 +const static uint64_t SH_FLD_PATTERNB_LEN = 12183; // 90 +const static uint64_t SH_FLD_PATTERNC = 12184; // 90 +const static uint64_t SH_FLD_PATTERNC_LEN = 12185; // 90 +const static uint64_t SH_FLD_PATTERND = 12186; // 90 +const static uint64_t SH_FLD_PATTERND_LEN = 12187; // 90 +const static uint64_t SH_FLD_PATTERN_CHECK_EN = 12188; // 1 +const static uint64_t SH_FLD_PATTERN_SEL = 12189; // 2 +const static uint64_t SH_FLD_PATTERN_SEL_LEN = 12190; // 2 +const static uint64_t SH_FLD_PAYLOAD = 12191; // 1 +const static uint64_t SH_FLD_PAYLOAD_LEN = 12192; // 1 +const static uint64_t SH_FLD_PBASE = 12193; // 4 +const static uint64_t SH_FLD_PBASE_LEN = 12194; // 4 +const static uint64_t SH_FLD_PBAX_EN = 12195; // 1 +const static uint64_t SH_FLD_PBAX_OCC_PUSH0 = 12196; // 1 +const static uint64_t SH_FLD_PBAX_OCC_PUSH1 = 12197; // 1 +const static uint64_t SH_FLD_PBAX_OCC_SEND_ATTN = 12198; // 1 +const static uint64_t SH_FLD_PBA_BCDE_ATTN = 12199; // 1 +const static uint64_t SH_FLD_PBA_BCUE_ATTN = 12200; // 1 +const static uint64_t SH_FLD_PBA_ERROR = 12201; // 1 +const static uint64_t SH_FLD_PBA_REGION = 12202; // 1 +const static uint64_t SH_FLD_PBA_REGION_LEN = 12203; // 1 +const static uint64_t SH_FLD_PBCFG_0_DISABLE_WR_RD_PUSH = 12204; // 1 +const static uint64_t SH_FLD_PBCFG_0_EPSILON = 12205; // 1 +const static uint64_t SH_FLD_PBCFG_0_EPSILON_LEN = 12206; // 1 +const static uint64_t SH_FLD_PBCFG_0_HANG_NX_MAX_CNT = 12207; // 1 +const static uint64_t SH_FLD_PBCFG_0_HANG_NX_MAX_CNT_LEN = 12208; // 1 +const static uint64_t SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT = 12209; // 1 +const static uint64_t SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT_LEN = 12210; // 1 +const static uint64_t SH_FLD_PBCFG_0_INJ_ARRAY_SEL = 12211; // 1 +const static uint64_t SH_FLD_PBCFG_0_INJ_CE = 12212; // 1 +const static uint64_t SH_FLD_PBCFG_0_INJ_FREQ = 12213; // 1 +const static uint64_t SH_FLD_PBCFG_0_INJ_SUE = 12214; // 1 +const static uint64_t SH_FLD_PBCFG_0_INJ_UE = 12215; // 1 +const static uint64_t SH_FLD_PBCFG_0_UNUSED1 = 12216; // 1 +const static uint64_t SH_FLD_PBCFG_0_UNUSED1_LEN = 12217; // 1 +const static uint64_t SH_FLD_PBCFG_0_UNUSED2 = 12218; // 1 +const static uint64_t SH_FLD_PBCFG_0_UNUSED2_LEN = 12219; // 1 +const static uint64_t SH_FLD_PBCFG_1_UNUSED1 = 12220; // 1 +const static uint64_t SH_FLD_PBCFG_1_UNUSED1_LEN = 12221; // 1 +const static uint64_t SH_FLD_PBCFG_1_UNUSED2 = 12222; // 1 +const static uint64_t SH_FLD_PBCFG_1_UNUSED2_LEN = 12223; // 1 +const static uint64_t SH_FLD_PBCQ_CNTRL_LOGIC_ERR = 12224; // 1 +const static uint64_t SH_FLD_PBDATA_HANG = 12225; // 1 +const static uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR0 = 12226; // 12 +const static uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR1 = 12227; // 12 +const static uint64_t SH_FLD_PBEXCA0_CMD_REQ_ERR2 = 12228; // 12 +const static uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR0 = 12229; // 12 +const static uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR1 = 12230; // 12 +const static uint64_t SH_FLD_PBEXCA1_CMD_REQ_ERR2 = 12231; // 12 +const static uint64_t SH_FLD_PBIEQ00_PBH_HW1_ERROR = 12232; // 2 +const static uint64_t SH_FLD_PBIEQ00_PBH_HW2_ERROR = 12233; // 2 +const static uint64_t SH_FLD_PBIEQ00_PBH_OVERFLOW_ERROR = 12234; // 2 +const static uint64_t SH_FLD_PBIEQ00_PBH_PROTOCOL_ERROR = 12235; // 2 +const static uint64_t SH_FLD_PBIEQ01_PBH_HW1_ERROR = 12236; // 2 +const static uint64_t SH_FLD_PBIEQ01_PBH_HW2_ERROR = 12237; // 2 +const static uint64_t SH_FLD_PBIEQ01_PBH_OVERFLOW_ERROR = 12238; // 2 +const static uint64_t SH_FLD_PBIEQ01_PBH_PROTOCOL_ERROR = 12239; // 2 +const static uint64_t SH_FLD_PBIEQ02_PBH_HW1_ERROR = 12240; // 2 +const static uint64_t SH_FLD_PBIEQ02_PBH_HW2_ERROR = 12241; // 2 +const static uint64_t SH_FLD_PBIEQ02_PBH_OVERFLOW_ERROR = 12242; // 2 +const static uint64_t SH_FLD_PBIEQ02_PBH_PROTOCOL_ERROR = 12243; // 2 +const static uint64_t SH_FLD_PBIEQ03_PBH_HW1_ERROR = 12244; // 2 +const static uint64_t SH_FLD_PBIEQ03_PBH_HW2_ERROR = 12245; // 2 +const static uint64_t SH_FLD_PBIEQ03_PBH_OVERFLOW_ERROR = 12246; // 2 +const static uint64_t SH_FLD_PBIEQ03_PBH_PROTOCOL_ERROR = 12247; // 2 +const static uint64_t SH_FLD_PBIEQ04_PBH_HW1_ERROR = 12248; // 2 +const static uint64_t SH_FLD_PBIEQ04_PBH_HW2_ERROR = 12249; // 2 +const static uint64_t SH_FLD_PBIEQ04_PBH_OVERFLOW_ERROR = 12250; // 2 +const static uint64_t SH_FLD_PBIEQ04_PBH_PROTOCOL_ERROR = 12251; // 2 +const static uint64_t SH_FLD_PBIEQ05_PBH_HW1_ERROR = 12252; // 2 +const static uint64_t SH_FLD_PBIEQ05_PBH_HW2_ERROR = 12253; // 2 +const static uint64_t SH_FLD_PBIEQ05_PBH_OVERFLOW_ERROR = 12254; // 2 +const static uint64_t SH_FLD_PBIEQ05_PBH_PROTOCOL_ERROR = 12255; // 2 +const static uint64_t SH_FLD_PBI_IDLE = 12256; // 1 +const static uint64_t SH_FLD_PBI_INTERNAL_HANG = 12257; // 1 +const static uint64_t SH_FLD_PBI_MUX_SELECT = 12258; // 1 +const static uint64_t SH_FLD_PBI_MUX_SELECT_LEN = 12259; // 1 +const static uint64_t SH_FLD_PBI_PE = 12260; // 2 +const static uint64_t SH_FLD_PBI_WRITE_IDLE = 12261; // 2 +const static uint64_t SH_FLD_PBLN = 12262; // 15 +const static uint64_t SH_FLD_PBM_STATE = 12263; // 3 +const static uint64_t SH_FLD_PBM_STATE_LEN = 12264; // 3 +const static uint64_t SH_FLD_PBNNG = 12265; // 15 +const static uint64_t SH_FLD_PBREQ_BCE_MAX_PRIORITY = 12266; // 1 +const static uint64_t SH_FLD_PBREQ_DATA_HANG_DIV = 12267; // 1 +const static uint64_t SH_FLD_PBREQ_DATA_HANG_DIV_LEN = 12268; // 1 +const static uint64_t SH_FLD_PBREQ_DROP_PRIORITY_MASK = 12269; // 1 +const static uint64_t SH_FLD_PBREQ_DROP_PRIORITY_MASK_LEN = 12270; // 1 +const static uint64_t SH_FLD_PBREQ_EVENT_MUX = 12271; // 1 +const static uint64_t SH_FLD_PBREQ_EVENT_MUX_LEN = 12272; // 1 +const static uint64_t SH_FLD_PBREQ_EXIT_HANG_DIV = 12273; // 1 +const static uint64_t SH_FLD_PBREQ_EXIT_HANG_DIV_LEN = 12274; // 1 +const static uint64_t SH_FLD_PBREQ_EXIT_ON_HANG = 12275; // 1 +const static uint64_t SH_FLD_PBREQ_EXIT_ON_HANG_PBAX = 12276; // 1 +const static uint64_t SH_FLD_PBREQ_OPER_HANG_DIV = 12277; // 1 +const static uint64_t SH_FLD_PBREQ_OPER_HANG_DIV_LEN = 12278; // 1 +const static uint64_t SH_FLD_PBREQ_SLVFW_MAX_PRIORITY = 12279; // 1 +const static uint64_t SH_FLD_PBRNVG = 12280; // 15 +const static uint64_t SH_FLD_PBRS = 12281; // 3 +const static uint64_t SH_FLD_PBRSP = 12282; // 12 +const static uint64_t SH_FLD_PBRX_MASK = 12283; // 3 +const static uint64_t SH_FLD_PBRX_MASK_LEN = 12284; // 3 +const static uint64_t SH_FLD_PBRX_RTAG = 12285; // 3 +const static uint64_t SH_FLD_PBRX_RTAG_LEN = 12286; // 3 +const static uint64_t SH_FLD_PBTX_AMO_IGNORE_XUE = 12287; // 3 +const static uint64_t SH_FLD_PBTX_DELAY_BDONE = 12288; // 3 +const static uint64_t SH_FLD_PBTX_EARLY_AFTAG = 12289; // 3 +const static uint64_t SH_FLD_PBTX_FLIP_IMIN_BIG = 12290; // 3 +const static uint64_t SH_FLD_PBTX_FLIP_IMIN_LITTLE = 12291; // 3 +const static uint64_t SH_FLD_PBTX_REDUCE_RTAG = 12292; // 3 +const static uint64_t SH_FLD_PBUNSUPPORTEDCMD = 12293; // 9 +const static uint64_t SH_FLD_PBUNSUPPORTEDCMD_MASK = 12294; // 9 +const static uint64_t SH_FLD_PBUNSUPPORTEDSIZE = 12295; // 9 +const static uint64_t SH_FLD_PBUNSUPPORTEDSIZE_MASK = 12296; // 9 +const static uint64_t SH_FLD_PBUS_CMD_HANG = 12297; // 2 +const static uint64_t SH_FLD_PBUS_ECC_CE = 12298; // 2 +const static uint64_t SH_FLD_PBUS_ECC_SUE = 12299; // 2 +const static uint64_t SH_FLD_PBUS_ECC_UE = 12300; // 2 +const static uint64_t SH_FLD_PBUS_LINK_ABORT = 12301; // 2 +const static uint64_t SH_FLD_PBUS_LOAD_LINK_ERR = 12302; // 2 +const static uint64_t SH_FLD_PBUS_MISC_HW = 12303; // 2 +const static uint64_t SH_FLD_PBUS_READ_ARE = 12304; // 2 +const static uint64_t SH_FLD_PBUS_STORE_LINK_ERR = 12305; // 2 +const static uint64_t SH_FLD_PBUS_WRITE_ARE = 12306; // 2 +const static uint64_t SH_FLD_PBUS_XLAT_ECC_SUE = 12307; // 1 +const static uint64_t SH_FLD_PBUS_XLAT_ECC_UE = 12308; // 1 +const static uint64_t SH_FLD_PB_ACKDEAD_FW_RD = 12309; // 1 +const static uint64_t SH_FLD_PB_ACKDEAD_FW_RD_MASK = 12310; // 1 +const static uint64_t SH_FLD_PB_ACKDEAD_FW_WR = 12311; // 1 +const static uint64_t SH_FLD_PB_ACKDEAD_FW_WR_MASK = 12312; // 1 +const static uint64_t SH_FLD_PB_ADDR_PARITY = 12313; // 2 +const static uint64_t SH_FLD_PB_BADCRESP = 12314; // 1 +const static uint64_t SH_FLD_PB_BADCRESP_MASK = 12315; // 1 +const static uint64_t SH_FLD_PB_BAR_RESET = 12316; // 1 +const static uint64_t SH_FLD_PB_CE_FW = 12317; // 1 +const static uint64_t SH_FLD_PB_CE_FW_MASK = 12318; // 1 +const static uint64_t SH_FLD_PB_CMD_ERR = 12319; // 12 +const static uint64_t SH_FLD_PB_DATA_ERR = 12320; // 12 +const static uint64_t SH_FLD_PB_DATA_HANG_ERRORS = 12321; // 9 +const static uint64_t SH_FLD_PB_DATA_HANG_ERRORS_MASK = 12322; // 9 +const static uint64_t SH_FLD_PB_DATA_TIME_OUT = 12323; // 4 +const static uint64_t SH_FLD_PB_ECC_CE = 12324; // 1 +const static uint64_t SH_FLD_PB_ECC_ERR_CE = 12325; // 4 +const static uint64_t SH_FLD_PB_ECC_ERR_SUE = 12326; // 4 +const static uint64_t SH_FLD_PB_ECC_ERR_UE = 12327; // 4 +const static uint64_t SH_FLD_PB_ECC_SUE = 12328; // 1 +const static uint64_t SH_FLD_PB_ECC_UE = 12329; // 1 +const static uint64_t SH_FLD_PB_HANG_ERRORS = 12330; // 9 +const static uint64_t SH_FLD_PB_HANG_ERRORS_MASK = 12331; // 9 +const static uint64_t SH_FLD_PB_INTERFACE_PE = 12332; // 9 +const static uint64_t SH_FLD_PB_INTERFACE_PE_MASK = 12333; // 9 +const static uint64_t SH_FLD_PB_NOCI_EVENT_SEL = 12334; // 1 +const static uint64_t SH_FLD_PB_OFFSET = 12335; // 2 +const static uint64_t SH_FLD_PB_OFFSET_LEN = 12336; // 2 +const static uint64_t SH_FLD_PB_OPERTO = 12337; // 1 +const static uint64_t SH_FLD_PB_OPERTO_MASK = 12338; // 1 +const static uint64_t SH_FLD_PB_OP_HANG_ERR = 12339; // 1 +const static uint64_t SH_FLD_PB_PARITY_ERR = 12340; // 1 +const static uint64_t SH_FLD_PB_PARITY_ERROR = 12341; // 5 +const static uint64_t SH_FLD_PB_PARITY_ERR_MASK = 12342; // 1 +const static uint64_t SH_FLD_PB_PURGE_DONE_LVL = 12343; // 6 +const static uint64_t SH_FLD_PB_PURGE_PLS = 12344; // 6 +const static uint64_t SH_FLD_PB_RCMDX_CI_ERR1 = 12345; // 1 +const static uint64_t SH_FLD_PB_RCMDX_CI_ERR2 = 12346; // 1 +const static uint64_t SH_FLD_PB_RCMDX_CI_ERR3 = 12347; // 1 +const static uint64_t SH_FLD_PB_RDADRERR_FW = 12348; // 1 +const static uint64_t SH_FLD_PB_RDADRERR_FW_MASK = 12349; // 1 +const static uint64_t SH_FLD_PB_RDDATATO_FW = 12350; // 1 +const static uint64_t SH_FLD_PB_RDDATATO_FW_MASK = 12351; // 1 +const static uint64_t SH_FLD_PB_STOP = 12352; // 1 +const static uint64_t SH_FLD_PB_SUE_FW = 12353; // 1 +const static uint64_t SH_FLD_PB_SUE_FW_MASK = 12354; // 1 +const static uint64_t SH_FLD_PB_TO_PEC_CE = 12355; // 9 +const static uint64_t SH_FLD_PB_TO_PEC_CE_MASK = 12356; // 9 +const static uint64_t SH_FLD_PB_TO_PEC_SUE = 12357; // 9 +const static uint64_t SH_FLD_PB_TO_PEC_SUE_MASK = 12358; // 9 +const static uint64_t SH_FLD_PB_TO_PEC_UE = 12359; // 9 +const static uint64_t SH_FLD_PB_TO_PEC_UE_MASK = 12360; // 9 +const static uint64_t SH_FLD_PB_UE_FW = 12361; // 1 +const static uint64_t SH_FLD_PB_UE_FW_MASK = 12362; // 1 +const static uint64_t SH_FLD_PB_UNEXPCRESP = 12363; // 1 +const static uint64_t SH_FLD_PB_UNEXPCRESP_MASK = 12364; // 1 +const static uint64_t SH_FLD_PB_UNEXPDATA = 12365; // 1 +const static uint64_t SH_FLD_PB_UNEXPDATA_MASK = 12366; // 1 +const static uint64_t SH_FLD_PB_WRADRERR_FW = 12367; // 1 +const static uint64_t SH_FLD_PB_WRADRERR_FW_MASK = 12368; // 1 +const static uint64_t SH_FLD_PB_XLAT_DATA_SUE = 12369; // 1 +const static uint64_t SH_FLD_PB_XLAT_DATA_UE = 12370; // 1 +const static uint64_t SH_FLD_PCB = 12371; // 3 +const static uint64_t SH_FLD_PCBMUX_GRANT_C0 = 12372; // 12 +const static uint64_t SH_FLD_PCBMUX_GRANT_C1 = 12373; // 12 +const static uint64_t SH_FLD_PCBMUX_REQ_C0 = 12374; // 12 +const static uint64_t SH_FLD_PCBMUX_REQ_C1 = 12375; // 12 +const static uint64_t SH_FLD_PCBQ_N_INFO = 12376; // 24 +const static uint64_t SH_FLD_PCBQ_N_INFO_LEN = 12377; // 24 +const static uint64_t SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 12378; // 43 +const static uint64_t SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 12379; // 43 +const static uint64_t SH_FLD_PCB_ADDRESS_PARITY = 12380; // 43 +const static uint64_t SH_FLD_PCB_COMMAND_PARITY = 12381; // 43 +const static uint64_t SH_FLD_PCB_EP_RESET = 12382; // 43 +const static uint64_t SH_FLD_PCB_ERROR = 12383; // 43 +const static uint64_t SH_FLD_PCB_FSM = 12384; // 43 +const static uint64_t SH_FLD_PCB_IDLE = 12385; // 43 +const static uint64_t SH_FLD_PCB_INTERFACE = 12386; // 43 +const static uint64_t SH_FLD_PCB_INTERRUPT_PROTOCOL = 12387; // 30 +const static uint64_t SH_FLD_PCB_INTR_TYPE_A_CORE_N = 12388; // 144 +const static uint64_t SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN = 12389; // 144 +const static uint64_t SH_FLD_PCB_INTR_TYPE_A_QUAD_N = 12390; // 12 +const static uint64_t SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN = 12391; // 12 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_0 = 12392; // 8 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_1 = 12393; // 8 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_10 = 12394; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_11 = 12395; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_12 = 12396; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_13 = 12397; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_14 = 12398; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_15 = 12399; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_16 = 12400; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_17 = 12401; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_18 = 12402; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_19 = 12403; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_2 = 12404; // 8 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_20 = 12405; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_21 = 12406; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_22 = 12407; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_23 = 12408; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_3 = 12409; // 8 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_4 = 12410; // 8 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_5 = 12411; // 8 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_6 = 12412; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_7 = 12413; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_8 = 12414; // 6 +const static uint64_t SH_FLD_PCB_INTR_TYPE_N_PENDING_9 = 12415; // 6 +const static uint64_t SH_FLD_PCB_LEN = 12416; // 2 +const static uint64_t SH_FLD_PCB_MASK = 12417; // 43 +const static uint64_t SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 12418; // 43 +const static uint64_t SH_FLD_PCB_REQUEST_SINCE_RESET = 12419; // 43 +const static uint64_t SH_FLD_PCB_RESET_DC = 12420; // 3 +const static uint64_t SH_FLD_PCB_TMP = 12421; // 1 +const static uint64_t SH_FLD_PCB_TMP_LEN = 12422; // 1 +const static uint64_t SH_FLD_PCB_WDATA_PARITY = 12423; // 43 +const static uint64_t SH_FLD_PCC_CORE_INTF_QUIESCE_C0 = 12424; // 12 +const static uint64_t SH_FLD_PCC_CORE_INTF_QUIESCE_C1 = 12425; // 12 +const static uint64_t SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS = 12426; // 6 +const static uint64_t SH_FLD_PCIE_REQUEST_ACCESS_ERROR = 12427; // 6 +const static uint64_t SH_FLD_PCI_CLOCK_ERROR = 12428; // 9 +const static uint64_t SH_FLD_PCI_CLOCK_ERROR_MASK = 12429; // 9 +const static uint64_t SH_FLD_PCI_HANG_ERROR = 12430; // 9 +const static uint64_t SH_FLD_PCI_HANG_ERROR_MASK = 12431; // 9 +const static uint64_t SH_FLD_PCLKDIFSEL = 12432; // 10 +const static uint64_t SH_FLD_PCLKOUTEN = 12433; // 3 +const static uint64_t SH_FLD_PCLKSEL = 12434; // 14 +const static uint64_t SH_FLD_PCLKSEL_LEN = 12435; // 14 +const static uint64_t SH_FLD_PC_CAL_PCFSM_1HOT = 12436; // 8 +const static uint64_t SH_FLD_PC_CAL_REFFSM_1HOT = 12437; // 8 +const static uint64_t SH_FLD_PC_CRD_AVAIL_PERR = 12438; // 1 +const static uint64_t SH_FLD_PC_CRD_PERR = 12439; // 1 +const static uint64_t SH_FLD_PC_DISABLE_DROOP = 12440; // 24 +const static uint64_t SH_FLD_PC_ERR_STATUS0 = 12441; // 8 +const static uint64_t SH_FLD_PC_ERR_STATUS0_LEN = 12442; // 8 +const static uint64_t SH_FLD_PC_FATAL_ERROR_0_2 = 12443; // 1 +const static uint64_t SH_FLD_PC_FATAL_ERROR_0_2_LEN = 12444; // 1 +const static uint64_t SH_FLD_PC_FUSED_CORE_MODE = 12445; // 24 +const static uint64_t SH_FLD_PC_INFO_ERROR_0_2 = 12446; // 1 +const static uint64_t SH_FLD_PC_INFO_ERROR_0_2_LEN = 12447; // 1 +const static uint64_t SH_FLD_PC_INIT_CAL_ERR = 12448; // 8 +const static uint64_t SH_FLD_PC_INIT_CAL_ERR_LEN = 12449; // 8 +const static uint64_t SH_FLD_PC_INSTR_RUNNING_C0 = 12450; // 12 +const static uint64_t SH_FLD_PC_INSTR_RUNNING_C1 = 12451; // 12 +const static uint64_t SH_FLD_PC_INTR_PENDING_C0 = 12452; // 24 +const static uint64_t SH_FLD_PC_INTR_PENDING_C1 = 12453; // 24 +const static uint64_t SH_FLD_PC_NON_HV_RUNNING_C0 = 12454; // 12 +const static uint64_t SH_FLD_PC_NON_HV_RUNNING_C0_LEN = 12455; // 12 +const static uint64_t SH_FLD_PC_NON_HV_RUNNING_C1 = 12456; // 12 +const static uint64_t SH_FLD_PC_NON_HV_RUNNING_C1_LEN = 12457; // 12 +const static uint64_t SH_FLD_PC_PE = 12458; // 8 +const static uint64_t SH_FLD_PC_PM_STATE_ACTIVE_C0 = 12459; // 24 +const static uint64_t SH_FLD_PC_PM_STATE_ACTIVE_C1 = 12460; // 24 +const static uint64_t SH_FLD_PC_PRIORITY_LIMIT_0_3 = 12461; // 1 +const static uint64_t SH_FLD_PC_PRIORITY_LIMIT_0_3_LEN = 12462; // 1 +const static uint64_t SH_FLD_PC_RECOV_ERROR_0_2 = 12463; // 1 +const static uint64_t SH_FLD_PC_RECOV_ERROR_0_2_LEN = 12464; // 1 +const static uint64_t SH_FLD_PC_SLICE_EN_ENC = 12465; // 1 +const static uint64_t SH_FLD_PC_SLICE_EN_ENC_LEN = 12466; // 1 +const static uint64_t SH_FLD_PC_TC_AVP_OUT = 12467; // 24 +const static uint64_t SH_FLD_PC_TC_VALID_NOT_HV_MODE = 12468; // 24 +const static uint64_t SH_FLD_PC_TEST = 12469; // 1 +const static uint64_t SH_FLD_PC_TP_TRIG_SEL = 12470; // 43 +const static uint64_t SH_FLD_PC_TP_TRIG_SEL_LEN = 12471; // 43 +const static uint64_t SH_FLD_PC_UNMASKED_ATTN_C0 = 12472; // 12 +const static uint64_t SH_FLD_PC_UNMASKED_ATTN_C1 = 12473; // 12 +const static uint64_t SH_FLD_PDWN = 12474; // 5 +const static uint64_t SH_FLD_PDWNPLL = 12475; // 6 +const static uint64_t SH_FLD_PDWNT = 12476; // 3 +const static uint64_t SH_FLD_PDWN_LITE = 12477; // 140 +const static uint64_t SH_FLD_PDWN_LITE_DISABLE = 12478; // 8 +const static uint64_t SH_FLD_PE = 12479; // 45 +const static uint64_t SH_FLD_PEAK_ENABLE_DAC_CFG = 12480; // 4 +const static uint64_t SH_FLD_PEAK_INIT_CFG = 12481; // 6 +const static uint64_t SH_FLD_PEAK_INIT_CFG_LEN = 12482; // 6 +const static uint64_t SH_FLD_PEAK_INIT_TIMEOUT = 12483; // 6 +const static uint64_t SH_FLD_PEAK_INIT_TIMEOUT_LEN = 12484; // 6 +const static uint64_t SH_FLD_PEAK_RECAL_CFG = 12485; // 6 +const static uint64_t SH_FLD_PEAK_RECAL_CFG_LEN = 12486; // 6 +const static uint64_t SH_FLD_PEAK_RECAL_TIMEOUT = 12487; // 6 +const static uint64_t SH_FLD_PEAK_RECAL_TIMEOUT_LEN = 12488; // 6 +const static uint64_t SH_FLD_PEAK_TUNE = 12489; // 4 +const static uint64_t SH_FLD_PECE_C_N_T0 = 12490; // 24 +const static uint64_t SH_FLD_PECE_C_N_T0_LEN = 12491; // 24 +const static uint64_t SH_FLD_PECE_C_N_T1 = 12492; // 24 +const static uint64_t SH_FLD_PECE_C_N_T1_LEN = 12493; // 24 +const static uint64_t SH_FLD_PECE_C_N_T2 = 12494; // 24 +const static uint64_t SH_FLD_PECE_C_N_T2_LEN = 12495; // 24 +const static uint64_t SH_FLD_PECE_C_N_T3 = 12496; // 24 +const static uint64_t SH_FLD_PECE_C_N_T3_LEN = 12497; // 24 +const static uint64_t SH_FLD_PECE_DECR = 12498; // 96 +const static uint64_t SH_FLD_PECE_DHDES = 12499; // 96 +const static uint64_t SH_FLD_PECE_DPDES = 12500; // 96 +const static uint64_t SH_FLD_PECE_HMAINT = 12501; // 96 +const static uint64_t SH_FLD_PECE_HYPV = 12502; // 96 +const static uint64_t SH_FLD_PECE_INTR_DISABLED = 12503; // 24 +const static uint64_t SH_FLD_PECE_OS_EXT = 12504; // 96 +const static uint64_t SH_FLD_PEC_SCOM_ERR = 12505; // 9 +const static uint64_t SH_FLD_PEC_SCOM_ERR_MASK = 12506; // 9 +const static uint64_t SH_FLD_PEEK_DATA1_0 = 12507; // 12 +const static uint64_t SH_FLD_PEEK_DATA1_0_LEN = 12508; // 12 +const static uint64_t SH_FLD_PEEK_DATA1_1 = 12509; // 12 +const static uint64_t SH_FLD_PEEK_DATA1_1_LEN = 12510; // 12 +const static uint64_t SH_FLD_PEEK_DATA1_2 = 12511; // 12 +const static uint64_t SH_FLD_PEEK_DATA1_2_LEN = 12512; // 12 +const static uint64_t SH_FLD_PEEK_DATA1_3 = 12513; // 12 +const static uint64_t SH_FLD_PEEK_DATA1_3_LEN = 12514; // 12 +const static uint64_t SH_FLD_PEND = 12515; // 8 +const static uint64_t SH_FLD_PENDING_SOURCE = 12516; // 30 +const static uint64_t SH_FLD_PENDING_SOURCE_LEN = 12517; // 30 +const static uint64_t SH_FLD_PERFORM_RDCLK_ALIGN = 12518; // 8 +const static uint64_t SH_FLD_PERF_CASCADE = 12519; // 1 +const static uint64_t SH_FLD_PERF_CASCADE_LEN = 12520; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_CASCADE = 12521; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_CASCADE_LEN = 12522; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_DISABLE_PMISC = 12523; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_ENABLE = 12524; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_EVENTS = 12525; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_EVENTS_LEN = 12526; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_FREEZEMODE = 12527; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_OPERATION_C0 = 12528; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_OPERATION_C0_LEN = 12529; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_OPERATION_C1 = 12530; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_OPERATION_C1_LEN = 12531; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_OPERATION_C2 = 12532; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_OPERATION_C2_LEN = 12533; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_OPERATION_C3 = 12534; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_OPERATION_C3_LEN = 12535; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_PMISC_MODE = 12536; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C0 = 12537; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C0_LEN = 12538; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C1 = 12539; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C1_LEN = 12540; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C2 = 12541; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C2_LEN = 12542; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C3 = 12543; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_PRESCALE_C3_LEN = 12544; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_RESETMODE = 12545; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_SPARE = 12546; // 1 +const static uint64_t SH_FLD_PERF_CONFIG_SPARE_LEN = 12547; // 1 +const static uint64_t SH_FLD_PERF_DISABLE_PMISC = 12548; // 1 +const static uint64_t SH_FLD_PERF_ENABLE = 12549; // 2 +const static uint64_t SH_FLD_PERF_EVENT0 = 12550; // 1 +const static uint64_t SH_FLD_PERF_EVENT0_LEN = 12551; // 1 +const static uint64_t SH_FLD_PERF_EVENT1 = 12552; // 1 +const static uint64_t SH_FLD_PERF_EVENT1_LEN = 12553; // 1 +const static uint64_t SH_FLD_PERF_EVENT2 = 12554; // 1 +const static uint64_t SH_FLD_PERF_EVENT2_LEN = 12555; // 1 +const static uint64_t SH_FLD_PERF_EVENT3 = 12556; // 1 +const static uint64_t SH_FLD_PERF_EVENT3_LEN = 12557; // 1 +const static uint64_t SH_FLD_PERF_FREEZEMODE = 12558; // 1 +const static uint64_t SH_FLD_PERF_PE_MASK = 12559; // 1 +const static uint64_t SH_FLD_PERF_PE_MATCH = 12560; // 1 +const static uint64_t SH_FLD_PERF_PE_MATCH_LEN = 12561; // 1 +const static uint64_t SH_FLD_PERF_PMISC_MODE = 12562; // 1 +const static uint64_t SH_FLD_PERF_PRESCALE_C0 = 12563; // 1 +const static uint64_t SH_FLD_PERF_PRESCALE_C0_LEN = 12564; // 1 +const static uint64_t SH_FLD_PERF_PRESCALE_C1 = 12565; // 1 +const static uint64_t SH_FLD_PERF_PRESCALE_C1_LEN = 12566; // 1 +const static uint64_t SH_FLD_PERF_PRESCALE_C2 = 12567; // 1 +const static uint64_t SH_FLD_PERF_PRESCALE_C2_LEN = 12568; // 1 +const static uint64_t SH_FLD_PERF_PRESCALE_C3 = 12569; // 1 +const static uint64_t SH_FLD_PERF_PRESCALE_C3_LEN = 12570; // 1 +const static uint64_t SH_FLD_PERF_RESETMODE = 12571; // 1 +const static uint64_t SH_FLD_PERF_THRESH = 12572; // 8 +const static uint64_t SH_FLD_PERF_THRESH_LEN = 12573; // 8 +const static uint64_t SH_FLD_PERIODIC = 12574; // 56 +const static uint64_t SH_FLD_PERIODIC_CAL_REQ_EN = 12575; // 8 +const static uint64_t SH_FLD_PERIODIC_LEN = 12576; // 56 +const static uint64_t SH_FLD_PERSIST = 12577; // 8 +const static uint64_t SH_FLD_PERSIST_LEN = 12578; // 8 +const static uint64_t SH_FLD_PERV = 12579; // 215 +const static uint64_t SH_FLD_PERVASIVE_CAPT = 12580; // 6 +const static uint64_t SH_FLD_PER_ABORT = 12581; // 8 +const static uint64_t SH_FLD_PER_DUTY_CYCLE_SW = 12582; // 8 +const static uint64_t SH_FLD_PER_REPEAT_COUNT = 12583; // 8 +const static uint64_t SH_FLD_PER_REPEAT_COUNT_LEN = 12584; // 8 +const static uint64_t SH_FLD_PE_ADR_BAR_MODE = 12585; // 3 +const static uint64_t SH_FLD_PE_BLOCK_CQPB_PB_INIT = 12586; // 3 +const static uint64_t SH_FLD_PE_CAPP = 12587; // 3 +const static uint64_t SH_FLD_PE_CAPP_APC_ENG = 12588; // 3 +const static uint64_t SH_FLD_PE_CAPP_APC_ENG_LEN = 12589; // 3 +const static uint64_t SH_FLD_PE_CAPP_EN = 12590; // 3 +const static uint64_t SH_FLD_PE_CAPP_LEN = 12591; // 3 +const static uint64_t SH_FLD_PE_CAPP_NUM_MSG_ENG = 12592; // 3 +const static uint64_t SH_FLD_PE_CAPP_NUM_MSG_ENG_LEN = 12593; // 3 +const static uint64_t SH_FLD_PE_CAPP_P8_MODE = 12594; // 3 +const static uint64_t SH_FLD_PE_CHANNEL_STREAMING_EN = 12595; // 3 +const static uint64_t SH_FLD_PE_CQ_ECC_INJECT_ENABLE = 12596; // 3 +const static uint64_t SH_FLD_PE_CQ_PAR_INJECT_ENABLE = 12597; // 3 +const static uint64_t SH_FLD_PE_CQ_REGISTER_ARRAY = 12598; // 3 +const static uint64_t SH_FLD_PE_CQ_REGISTER_ARRAY_LEN = 12599; // 3 +const static uint64_t SH_FLD_PE_CQ_SRAM_ARRAY = 12600; // 3 +const static uint64_t SH_FLD_PE_CQ_SRAM_ARRAY_LEN = 12601; // 3 +const static uint64_t SH_FLD_PE_DISABLE_CQ_TCE_ARBITRATION = 12602; // 3 +const static uint64_t SH_FLD_PE_DISABLE_INJ_ON_RESEND = 12603; // 3 +const static uint64_t SH_FLD_PE_DISABLE_INTWR_SCOPE_GROUP = 12604; // 3 +const static uint64_t SH_FLD_PE_DISABLE_INTWR_SCOPE_NODE = 12605; // 3 +const static uint64_t SH_FLD_PE_DISABLE_INTWR_VG = 12606; // 3 +const static uint64_t SH_FLD_PE_DISABLE_MC_PREFETCH = 12607; // 3 +const static uint64_t SH_FLD_PE_DISABLE_OOO_MODE = 12608; // 3 +const static uint64_t SH_FLD_PE_DISABLE_PCI_CLK_CHECK = 12609; // 3 +const static uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_GROUP = 12610; // 3 +const static uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_NODAL = 12611; // 3 +const static uint64_t SH_FLD_PE_DISABLE_RD_SCOPE_RNNN = 12612; // 3 +const static uint64_t SH_FLD_PE_DISABLE_RD_VG = 12613; // 3 +const static uint64_t SH_FLD_PE_DISABLE_TCE_ARBITRATION = 12614; // 3 +const static uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_GROUP = 12615; // 3 +const static uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_NODAL = 12616; // 3 +const static uint64_t SH_FLD_PE_DISABLE_TCE_SCOPE_RNNN = 12617; // 3 +const static uint64_t SH_FLD_PE_DISABLE_TCE_VG = 12618; // 3 +const static uint64_t SH_FLD_PE_DISABLE_WR_SCOPE_GROUP = 12619; // 3 +const static uint64_t SH_FLD_PE_DISABLE_WR_VG = 12620; // 3 +const static uint64_t SH_FLD_PE_DROPPACECOUNT = 12621; // 3 +const static uint64_t SH_FLD_PE_DROPPACECOUNT_LEN = 12622; // 3 +const static uint64_t SH_FLD_PE_DROPPACEINC = 12623; // 3 +const static uint64_t SH_FLD_PE_DROPPACEINC_LEN = 12624; // 3 +const static uint64_t SH_FLD_PE_DROPPRIORITYMASK = 12625; // 3 +const static uint64_t SH_FLD_PE_DROPPRIORITYMASK_LEN = 12626; // 3 +const static uint64_t SH_FLD_PE_ECC_INJECT_TYPE = 12627; // 3 +const static uint64_t SH_FLD_PE_ECC_INJECT_TYPE_LEN = 12628; // 3 +const static uint64_t SH_FLD_PE_EINJ_STACK = 12629; // 3 +const static uint64_t SH_FLD_PE_EINJ_STACK_LEN = 12630; // 3 +const static uint64_t SH_FLD_PE_ENABLE_CTAG_DROP_PRIORITY = 12631; // 3 +const static uint64_t SH_FLD_PE_ENABLE_DMAR_IOPACING = 12632; // 3 +const static uint64_t SH_FLD_PE_ENABLE_DMAW_IOPACING = 12633; // 3 +const static uint64_t SH_FLD_PE_ENABLE_ENH_FLOW = 12634; // 3 +const static uint64_t SH_FLD_PE_ENABLE_IO_CMD_PACING = 12635; // 3 +const static uint64_t SH_FLD_PE_ENABLE_NEW_FLOW_CACHE_INJECT = 12636; // 3 +const static uint64_t SH_FLD_PE_ENABLE_RD_SKIP_GROUP = 12637; // 3 +const static uint64_t SH_FLD_PE_ENABLE_TCE_SKIP_GROUP = 12638; // 3 +const static uint64_t SH_FLD_PE_ENHANCED_PEER2PEER_MODDE = 12639; // 9 +const static uint64_t SH_FLD_PE_ETU_RESET = 12640; // 9 +const static uint64_t SH_FLD_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW = 12641; // 3 +const static uint64_t SH_FLD_PE_HANG_SM_ON_ARE = 12642; // 3 +const static uint64_t SH_FLD_PE_IGNORE_SFSTAT = 12643; // 3 +const static uint64_t SH_FLD_PE_INBOUND_ACTIVE = 12644; // 9 +const static uint64_t SH_FLD_PE_INT_BAR = 12645; // 9 +const static uint64_t SH_FLD_PE_INT_BAR_EN = 12646; // 9 +const static uint64_t SH_FLD_PE_INT_BAR_LEN = 12647; // 9 +const static uint64_t SH_FLD_PE_ISMB_ERROR_INJECT = 12648; // 3 +const static uint64_t SH_FLD_PE_ISMB_ERROR_INJECT_LEN = 12649; // 3 +const static uint64_t SH_FLD_PE_LEN = 12650; // 45 +const static uint64_t SH_FLD_PE_MMIO_BAR0 = 12651; // 9 +const static uint64_t SH_FLD_PE_MMIO_BAR0_EN = 12652; // 9 +const static uint64_t SH_FLD_PE_MMIO_BAR0_LEN = 12653; // 9 +const static uint64_t SH_FLD_PE_MMIO_BAR1 = 12654; // 9 +const static uint64_t SH_FLD_PE_MMIO_BAR1_EN = 12655; // 9 +const static uint64_t SH_FLD_PE_MMIO_BAR1_LEN = 12656; // 9 +const static uint64_t SH_FLD_PE_MMIO_MASK0 = 12657; // 9 +const static uint64_t SH_FLD_PE_MMIO_MASK0_LEN = 12658; // 9 +const static uint64_t SH_FLD_PE_MMIO_MASK1 = 12659; // 9 +const static uint64_t SH_FLD_PE_MMIO_MASK1_LEN = 12660; // 9 +const static uint64_t SH_FLD_PE_OSMB_DATASTART_MODE = 12661; // 3 +const static uint64_t SH_FLD_PE_OSMB_DATASTART_MODE_LEN = 12662; // 3 +const static uint64_t SH_FLD_PE_OSMB_EARLYEMPTY_MODE = 12663; // 3 +const static uint64_t SH_FLD_PE_OSMB_EARLYEMPTY_MODE_LEN = 12664; // 3 +const static uint64_t SH_FLD_PE_OSMB_EARLY_START = 12665; // 3 +const static uint64_t SH_FLD_PE_OSMB_EARLY_START_LEN = 12666; // 3 +const static uint64_t SH_FLD_PE_OSMB_HOL_BLK_CNT = 12667; // 3 +const static uint64_t SH_FLD_PE_OSMB_HOL_BLK_CNT_LEN = 12668; // 3 +const static uint64_t SH_FLD_PE_OUTBOUND_ACTIVE = 12669; // 9 +const static uint64_t SH_FLD_PE_PCIE_CLK_TRACE_EN = 12670; // 3 +const static uint64_t SH_FLD_PE_PCI_CLK_TRACE_SEL = 12671; // 3 +const static uint64_t SH_FLD_PE_PCI_CLK_TRACE_SEL_LEN = 12672; // 3 +const static uint64_t SH_FLD_PE_PEER2PEER_MODDE = 12673; // 9 +const static uint64_t SH_FLD_PE_PERFMON_EN = 12674; // 3 +const static uint64_t SH_FLD_PE_PERFMON_EN_LEN = 12675; // 3 +const static uint64_t SH_FLD_PE_PERFMON_READ_TYPE = 12676; // 3 +const static uint64_t SH_FLD_PE_PERFMON_READ_TYPE_LEN = 12677; // 3 +const static uint64_t SH_FLD_PE_PHB_BAR = 12678; // 9 +const static uint64_t SH_FLD_PE_PHB_BAR_EN = 12679; // 9 +const static uint64_t SH_FLD_PE_PHB_BAR_LEN = 12680; // 9 +const static uint64_t SH_FLD_PE_PMON_MUX_BYTE0 = 12681; // 3 +const static uint64_t SH_FLD_PE_PMON_MUX_BYTE0_LEN = 12682; // 3 +const static uint64_t SH_FLD_PE_PMON_MUX_BYTE1 = 12683; // 3 +const static uint64_t SH_FLD_PE_PMON_MUX_BYTE1_LEN = 12684; // 3 +const static uint64_t SH_FLD_PE_PMON_MUX_BYTE2 = 12685; // 3 +const static uint64_t SH_FLD_PE_PMON_MUX_BYTE2_LEN = 12686; // 3 +const static uint64_t SH_FLD_PE_PMON_MUX_BYTE3 = 12687; // 3 +const static uint64_t SH_FLD_PE_PMON_MUX_BYTE3_LEN = 12688; // 3 +const static uint64_t SH_FLD_PE_QFIFO_HOLD_MODE = 12689; // 3 +const static uint64_t SH_FLD_PE_QFIFO_HOLD_MODE_LEN = 12690; // 3 +const static uint64_t SH_FLD_PE_RD_TIMEOUT_MASK = 12691; // 3 +const static uint64_t SH_FLD_PE_RD_TIMEOUT_MASK_LEN = 12692; // 3 +const static uint64_t SH_FLD_PE_RD_WRITE_ORDERING = 12693; // 3 +const static uint64_t SH_FLD_PE_RD_WRITE_ORDERING_LEN = 12694; // 3 +const static uint64_t SH_FLD_PE_RTYDROPDIVIDER = 12695; // 3 +const static uint64_t SH_FLD_PE_RTYDROPDIVIDER_LEN = 12696; // 3 +const static uint64_t SH_FLD_PE_SELECT_ETU_TRACE = 12697; // 3 +const static uint64_t SH_FLD_PE_STOP_STATE_SIGNALED = 12698; // 6 +const static uint64_t SH_FLD_PE_STQ_ALLOCATION = 12699; // 3 +const static uint64_t SH_FLD_PE_TX_RESP_HWM = 12700; // 3 +const static uint64_t SH_FLD_PE_TX_RESP_HWM_LEN = 12701; // 3 +const static uint64_t SH_FLD_PE_TX_RESP_LWM = 12702; // 3 +const static uint64_t SH_FLD_PE_TX_RESP_LWM_LEN = 12703; // 3 +const static uint64_t SH_FLD_PE_WR_CACHE_INJECT_MODE = 12704; // 3 +const static uint64_t SH_FLD_PE_WR_CACHE_INJECT_MODE_LEN = 12705; // 3 +const static uint64_t SH_FLD_PE_WR_STRICT_ORDER_MODE = 12706; // 3 +const static uint64_t SH_FLD_PE_WR_TIMEOUT_MASK = 12707; // 3 +const static uint64_t SH_FLD_PE_WR_TIMEOUT_MASK_LEN = 12708; // 3 +const static uint64_t SH_FLD_PFD360SEL = 12709; // 4 +const static uint64_t SH_FLD_PFET_SEQ_PROGRAM = 12710; // 30 +const static uint64_t SH_FLD_PFREQ0 = 12711; // 24 +const static uint64_t SH_FLD_PFREQ0_LEN = 12712; // 24 +const static uint64_t SH_FLD_PFREQ1 = 12713; // 24 +const static uint64_t SH_FLD_PFREQ1_LEN = 12714; // 24 +const static uint64_t SH_FLD_PF_DROP_CNT_THRESH = 12715; // 4 +const static uint64_t SH_FLD_PF_DROP_CNT_THRESH_LEN = 12716; // 4 +const static uint64_t SH_FLD_PF_DROP_VALUE0 = 12717; // 8 +const static uint64_t SH_FLD_PF_DROP_VALUE0_LEN = 12718; // 8 +const static uint64_t SH_FLD_PF_DROP_VALUE1 = 12719; // 8 +const static uint64_t SH_FLD_PF_DROP_VALUE1_LEN = 12720; // 8 +const static uint64_t SH_FLD_PF_DROP_VALUE2 = 12721; // 8 +const static uint64_t SH_FLD_PF_DROP_VALUE2_LEN = 12722; // 8 +const static uint64_t SH_FLD_PF_DROP_VALUE3 = 12723; // 8 +const static uint64_t SH_FLD_PF_DROP_VALUE3_LEN = 12724; // 8 +const static uint64_t SH_FLD_PF_MACHINE_HANG = 12725; // 12 +const static uint64_t SH_FLD_PF_MACHINE_W4DT_HANG = 12726; // 12 +const static uint64_t SH_FLD_PF_PROMOTE_ERR_INJ = 12727; // 8 +const static uint64_t SH_FLD_PF_UNSOLICITED_CRESP = 12728; // 12 +const static uint64_t SH_FLD_PF_UNSOLICITED_DATA = 12729; // 12 +const static uint64_t SH_FLD_PGMIGR1_BAR = 12730; // 1 +const static uint64_t SH_FLD_PGMIGR1_BAR_LEN = 12731; // 1 +const static uint64_t SH_FLD_PGMIGR1_PGSZ = 12732; // 1 +const static uint64_t SH_FLD_PGMIGR1_PGSZ_LEN = 12733; // 1 +const static uint64_t SH_FLD_PGMIGR1_VAL = 12734; // 1 +const static uint64_t SH_FLD_PGMIGR2_BAR = 12735; // 1 +const static uint64_t SH_FLD_PGMIGR2_BAR_LEN = 12736; // 1 +const static uint64_t SH_FLD_PGMIGR2_PGSZ = 12737; // 1 +const static uint64_t SH_FLD_PGMIGR2_PGSZ_LEN = 12738; // 1 +const static uint64_t SH_FLD_PGMIGR2_VAL = 12739; // 1 +const static uint64_t SH_FLD_PGMIGR3_BAR = 12740; // 1 +const static uint64_t SH_FLD_PGMIGR3_BAR_LEN = 12741; // 1 +const static uint64_t SH_FLD_PGMIGR3_PGSZ = 12742; // 1 +const static uint64_t SH_FLD_PGMIGR3_PGSZ_LEN = 12743; // 1 +const static uint64_t SH_FLD_PGMIGR3_VAL = 12744; // 1 +const static uint64_t SH_FLD_PGMIGR4_BAR = 12745; // 1 +const static uint64_t SH_FLD_PGMIGR4_BAR_LEN = 12746; // 1 +const static uint64_t SH_FLD_PGMIGR4_PGSZ = 12747; // 1 +const static uint64_t SH_FLD_PGMIGR4_PGSZ_LEN = 12748; // 1 +const static uint64_t SH_FLD_PGMIGR4_VAL = 12749; // 1 +const static uint64_t SH_FLD_PGMIGR5_BAR = 12750; // 1 +const static uint64_t SH_FLD_PGMIGR5_BAR_LEN = 12751; // 1 +const static uint64_t SH_FLD_PGMIGR5_PGSZ = 12752; // 1 +const static uint64_t SH_FLD_PGMIGR5_PGSZ_LEN = 12753; // 1 +const static uint64_t SH_FLD_PGMIGR5_VAL = 12754; // 1 +const static uint64_t SH_FLD_PGMIGR6_BAR = 12755; // 1 +const static uint64_t SH_FLD_PGMIGR6_BAR_LEN = 12756; // 1 +const static uint64_t SH_FLD_PGMIGR6_PGSZ = 12757; // 1 +const static uint64_t SH_FLD_PGMIGR6_PGSZ_LEN = 12758; // 1 +const static uint64_t SH_FLD_PGMIGR6_VAL = 12759; // 1 +const static uint64_t SH_FLD_PGMIGR7_BAR = 12760; // 1 +const static uint64_t SH_FLD_PGMIGR7_BAR_LEN = 12761; // 1 +const static uint64_t SH_FLD_PGMIGR7_PGSZ = 12762; // 1 +const static uint64_t SH_FLD_PGMIGR7_PGSZ_LEN = 12763; // 1 +const static uint64_t SH_FLD_PGMIGR7_VAL = 12764; // 1 +const static uint64_t SH_FLD_PGOFFIRSTLS = 12765; // 1 +const static uint64_t SH_FLD_PGOFFIRSTLS_LEN = 12766; // 1 +const static uint64_t SH_FLD_PGOFNEXTLS = 12767; // 1 +const static uint64_t SH_FLD_PGOFNEXTLS_LEN = 12768; // 1 +const static uint64_t SH_FLD_PGOOD_TIMEOUT_SEL = 12769; // 4 +const static uint64_t SH_FLD_PGOOD_TIMEOUT_SEL_LEN = 12770; // 4 +const static uint64_t SH_FLD_PG_MIG_DISABLED_ERR = 12771; // 2 +const static uint64_t SH_FLD_PG_MIG_SIZE_MISMATCH_ERR = 12772; // 2 +const static uint64_t SH_FLD_PHASEFB = 12773; // 4 +const static uint64_t SH_FLD_PHASEFB_LEN = 12774; // 4 +const static uint64_t SH_FLD_PHBCSR_SPARE = 12775; // 1 +const static uint64_t SH_FLD_PHB_FILTER_CNTL = 12776; // 2 +const static uint64_t SH_FLD_PHB_FILTER_CNTL_LEN = 12777; // 2 +const static uint64_t SH_FLD_PHB_LINK_DOWN = 12778; // 4 +const static uint64_t SH_FLD_PHYP_SCOPE = 12779; // 1 +const static uint64_t SH_FLD_PHY_PARITY_HOLD_OUT = 12780; // 8 +const static uint64_t SH_FLD_PIB2PCB_DC = 12781; // 3 +const static uint64_t SH_FLD_PIBI2CM_PIB_SLAVE_ID = 12782; // 1 +const static uint64_t SH_FLD_PIBI2CM_PIB_SLAVE_ID_LEN = 12783; // 1 +const static uint64_t SH_FLD_PIB_0 = 12784; // 2 +const static uint64_t SH_FLD_PIB_0_LEN = 12785; // 2 +const static uint64_t SH_FLD_PIB_1 = 12786; // 2 +const static uint64_t SH_FLD_PIB_1_LEN = 12787; // 2 +const static uint64_t SH_FLD_PIB_2 = 12788; // 2 +const static uint64_t SH_FLD_PIB_2_LEN = 12789; // 2 +const static uint64_t SH_FLD_PIB_3 = 12790; // 2 +const static uint64_t SH_FLD_PIB_3_LEN = 12791; // 2 +const static uint64_t SH_FLD_PIB_ABORT = 12792; // 2 +const static uint64_t SH_FLD_PIB_ADDR = 12793; // 1 +const static uint64_t SH_FLD_PIB_ADDR_LEN = 12794; // 1 +const static uint64_t SH_FLD_PIB_ADDR_P = 12795; // 1 +const static uint64_t SH_FLD_PIB_ADDR_P_ERR = 12796; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_0 = 12797; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_0_LEN = 12798; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_1 = 12799; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_1_LEN = 12800; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_2 = 12801; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_2_LEN = 12802; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_3 = 12803; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_ADDR_3_LEN = 12804; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_0 = 12805; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_1 = 12806; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_2 = 12807; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_READCONT_3 = 12808; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_0 = 12809; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_1 = 12810; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_2 = 12811; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_RNW_3 = 12812; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_0 = 12813; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_1 = 12814; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_2 = 12815; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_3 = 12816; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_0 = 12817; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_1 = 12818; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_2 = 12819; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_3 = 12820; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_0 = 12821; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_1 = 12822; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_2 = 12823; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_3 = 12824; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_0 = 12825; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_0_LEN = 12826; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_1 = 12827; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_1_LEN = 12828; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_2 = 12829; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_2_LEN = 12830; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_3 = 12831; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_1_3_LEN = 12832; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_0 = 12833; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_0_LEN = 12834; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_1 = 12835; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_1_LEN = 12836; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_2 = 12837; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_2_LEN = 12838; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_3 = 12839; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_2_3_LEN = 12840; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_0 = 12841; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_0_LEN = 12842; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_1 = 12843; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_1_LEN = 12844; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_2 = 12845; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_2_LEN = 12846; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_3 = 12847; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_3_3_LEN = 12848; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_0 = 12849; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_0_LEN = 12850; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_1 = 12851; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_1_LEN = 12852; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_2 = 12853; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_2_LEN = 12854; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_3 = 12855; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_DATA_4_3_LEN = 12856; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_0 = 12857; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_0_LEN = 12858; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_1 = 12859; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_1_LEN = 12860; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_2 = 12861; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_2_LEN = 12862; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_3 = 12863; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_LENGTH_3_LEN = 12864; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0 = 12865; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0_LEN = 12866; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1 = 12867; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1_LEN = 12868; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2 = 12869; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2_LEN = 12870; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3 = 12871; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3_LEN = 12872; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_0 = 12873; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_0_LEN = 12874; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_1 = 12875; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_1_LEN = 12876; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_2 = 12877; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_2_LEN = 12878; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_3 = 12879; // 1 +const static uint64_t SH_FLD_PIB_CNTR_REG_SPEED_3_LEN = 12880; // 1 +const static uint64_t SH_FLD_PIB_COMPONENT_BUSY = 12881; // 1 +const static uint64_t SH_FLD_PIB_DATA0TO7_0 = 12882; // 1 +const static uint64_t SH_FLD_PIB_DATA0TO7_0_LEN = 12883; // 1 +const static uint64_t SH_FLD_PIB_DATA0TO7_1 = 12884; // 1 +const static uint64_t SH_FLD_PIB_DATA0TO7_1_LEN = 12885; // 1 +const static uint64_t SH_FLD_PIB_DATA0TO7_2 = 12886; // 1 +const static uint64_t SH_FLD_PIB_DATA0TO7_2_LEN = 12887; // 1 +const static uint64_t SH_FLD_PIB_DATA0TO7_3 = 12888; // 1 +const static uint64_t SH_FLD_PIB_DATA0TO7_3_LEN = 12889; // 1 +const static uint64_t SH_FLD_PIB_DATA_P = 12890; // 1 +const static uint64_t SH_FLD_PIB_DATA_P_ERR = 12891; // 1 +const static uint64_t SH_FLD_PIB_ERROR_CODE = 12892; // 1 +const static uint64_t SH_FLD_PIB_ERROR_CODE_LEN = 12893; // 1 +const static uint64_t SH_FLD_PIB_FSM_STATE = 12894; // 1 +const static uint64_t SH_FLD_PIB_FSM_STATE_LEN = 12895; // 1 +const static uint64_t SH_FLD_PIB_HANG = 12896; // 1 +const static uint64_t SH_FLD_PIB_MASTER_REQUEST = 12897; // 4 +const static uint64_t SH_FLD_PIB_MASTER_RSP_INFO = 12898; // 4 +const static uint64_t SH_FLD_PIB_MASTER_RSP_INFO_LEN = 12899; // 4 +const static uint64_t SH_FLD_PIB_RESET_DURING_PIB_ACCESS = 12900; // 4 +const static uint64_t SH_FLD_PIB_RESPONSE_INFO = 12901; // 1 +const static uint64_t SH_FLD_PIB_RESPONSE_INFO_LEN = 12902; // 1 +const static uint64_t SH_FLD_PIB_SLAVE_ADDR_INVALID = 12903; // 4 +const static uint64_t SH_FLD_PIB_SLAVE_ADDR_PARITY = 12904; // 4 +const static uint64_t SH_FLD_PIB_SLAVE_DATA_PARITY = 12905; // 4 +const static uint64_t SH_FLD_PIB_SLAVE_READ_INVALID = 12906; // 4 +const static uint64_t SH_FLD_PIB_SLAVE_WRITE_INVALID = 12907; // 4 +const static uint64_t SH_FLD_PID = 12908; // 273 +const static uint64_t SH_FLD_PID_LEN = 12909; // 273 +const static uint64_t SH_FLD_PID_MASK = 12910; // 1 +const static uint64_t SH_FLD_PID_MASK_LEN = 12911; // 1 +const static uint64_t SH_FLD_PIPELINE_ENABLE = 12912; // 1 +const static uint64_t SH_FLD_PIPE_COUNTER = 12913; // 1 +const static uint64_t SH_FLD_PIPE_COUNTER_LEN = 12914; // 1 +const static uint64_t SH_FLD_PIPE_MARGIN = 12915; // 48 +const static uint64_t SH_FLD_PIPE_SEL = 12916; // 120 +const static uint64_t SH_FLD_PIPE_SEL_LEN = 12917; // 48 +const static uint64_t SH_FLD_PI_ECC_CE = 12918; // 1 +const static uint64_t SH_FLD_PI_ECC_SUE = 12919; // 1 +const static uint64_t SH_FLD_PI_ECC_UE = 12920; // 1 +const static uint64_t SH_FLD_PLBARB_LOCKERR = 12921; // 1 +const static uint64_t SH_FLD_PLLCVHOLD = 12922; // 6 +const static uint64_t SH_FLD_PLLFMAX = 12923; // 6 +const static uint64_t SH_FLD_PLLFMIN = 12924; // 6 +const static uint64_t SH_FLD_PLLLOCK = 12925; // 4 +const static uint64_t SH_FLD_PLLLOCK_0_FILTER_PLL_NEST = 12926; // 1 +const static uint64_t SH_FLD_PLLLOCK_1_FILTER_PLL_MC = 12927; // 1 +const static uint64_t SH_FLD_PLLLOCK_2_XBUS = 12928; // 1 +const static uint64_t SH_FLD_PLLLOCK_3_NEST = 12929; // 1 +const static uint64_t SH_FLD_PLLREFSEL = 12930; // 3 +const static uint64_t SH_FLD_PLLREFSEL_LEN = 12931; // 3 +const static uint64_t SH_FLD_PLLRESET = 12932; // 6 +const static uint64_t SH_FLD_PLL_BNDY_BYPASS_EN = 12933; // 43 +const static uint64_t SH_FLD_PLL_BYPASS = 12934; // 43 +const static uint64_t SH_FLD_PLL_CLKIN_SEL = 12935; // 43 +const static uint64_t SH_FLD_PLL_DESTOUT = 12936; // 43 +const static uint64_t SH_FLD_PLL_LOCK_TIMEOUT_SEL = 12937; // 4 +const static uint64_t SH_FLD_PLL_LOCK_TIMEOUT_SEL_LEN = 12938; // 4 +const static uint64_t SH_FLD_PLL_REFCLKSEL_SCOM_EN = 12939; // 4 +const static uint64_t SH_FLD_PLL_RESET = 12940; // 43 +const static uint64_t SH_FLD_PLL_TEST_EN = 12941; // 43 +const static uint64_t SH_FLD_PLL_UNLOCK = 12942; // 43 +const static uint64_t SH_FLD_PLL_UNLOCK_LEN = 12943; // 43 +const static uint64_t SH_FLD_PL_ERR = 12944; // 6 +const static uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_EN = 12945; // 12 +const static uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_NUM = 12946; // 12 +const static uint64_t SH_FLD_PM03_L23_EVENT_TID_SEL_NUM_LEN = 12947; // 12 +const static uint64_t SH_FLD_PM03_SMT_ROTATION_DIS = 12948; // 12 +const static uint64_t SH_FLD_PM07_TID_ROTATE_PLSS_RATE = 12949; // 12 +const static uint64_t SH_FLD_PM07_TID_ROTATE_PLSS_RATE_LEN = 12950; // 12 +const static uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_EN = 12951; // 12 +const static uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_NUM = 12952; // 12 +const static uint64_t SH_FLD_PM47_L23_EVENT_TID_SEL_NUM_LEN = 12953; // 12 +const static uint64_t SH_FLD_PM47_SMT_ROTATION_DIS = 12954; // 12 +const static uint64_t SH_FLD_PMCM_THRESHOLD = 12955; // 24 +const static uint64_t SH_FLD_PMCM_THRESHOLD_LEN = 12956; // 24 +const static uint64_t SH_FLD_PMCR_OVERRIDE_EN = 12957; // 12 +const static uint64_t SH_FLD_PMCR_UPDATE_C0 = 12958; // 12 +const static uint64_t SH_FLD_PMCR_UPDATE_C1 = 12959; // 12 +const static uint64_t SH_FLD_PMC_ENABLE = 12960; // 1 +const static uint64_t SH_FLD_PMC_O2S_0A_ONGOING = 12961; // 1 +const static uint64_t SH_FLD_PMC_O2S_0B_ONGOING = 12962; // 1 +const static uint64_t SH_FLD_PMC_O2S_1A_ONGOING = 12963; // 1 +const static uint64_t SH_FLD_PMC_O2S_1B_ONGOING = 12964; // 1 +const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE0_PENDING = 12965; // 1 +const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE1_PENDING = 12966; // 1 +const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE2_PENDING = 12967; // 1 +const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE3_PENDING = 12968; // 1 +const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE4_PENDING = 12969; // 1 +const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE5_PENDING = 12970; // 1 +const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE6_PENDING = 12971; // 1 +const static uint64_t SH_FLD_PMC_PCB_INTR_TYPE7_PENDING = 12972; // 1 +const static uint64_t SH_FLD_PMISC_CRESP_ADDR_ERR = 12973; // 12 +const static uint64_t SH_FLD_PMISC_MODE = 12974; // 9 +const static uint64_t SH_FLD_PMON_GROUP_SELECT = 12975; // 2 +const static uint64_t SH_FLD_PMON_GROUP_SELECT_LEN = 12976; // 2 +const static uint64_t SH_FLD_PMON_MUX_BYTE0_0_2 = 12977; // 1 +const static uint64_t SH_FLD_PMON_MUX_BYTE0_0_2_LEN = 12978; // 1 +const static uint64_t SH_FLD_PMON_MUX_BYTE1_0_2 = 12979; // 1 +const static uint64_t SH_FLD_PMON_MUX_BYTE1_0_2_LEN = 12980; // 1 +const static uint64_t SH_FLD_PMON_MUX_BYTE2_0_2 = 12981; // 1 +const static uint64_t SH_FLD_PMON_MUX_BYTE2_0_2_LEN = 12982; // 1 +const static uint64_t SH_FLD_PMON_MUX_BYTE3_0_2 = 12983; // 1 +const static uint64_t SH_FLD_PMON_MUX_BYTE3_0_2_LEN = 12984; // 1 +const static uint64_t SH_FLD_PMSR_OVERRIDE_EN = 12985; // 12 +const static uint64_t SH_FLD_PMU0145_EVENT0_MODE = 12986; // 2 +const static uint64_t SH_FLD_PMU0145_EVENT0_MODE_LEN = 12987; // 2 +const static uint64_t SH_FLD_PMU0145_EVENT1_MODE = 12988; // 2 +const static uint64_t SH_FLD_PMU0145_EVENT1_MODE_LEN = 12989; // 2 +const static uint64_t SH_FLD_PMU0145_EVENT2_MODE = 12990; // 2 +const static uint64_t SH_FLD_PMU0145_EVENT2_MODE_LEN = 12991; // 2 +const static uint64_t SH_FLD_PMU0145_EVENT3_MODE = 12992; // 2 +const static uint64_t SH_FLD_PMU0145_EVENT3_MODE_LEN = 12993; // 2 +const static uint64_t SH_FLD_PMU01_LINK_SELECT = 12994; // 2 +const static uint64_t SH_FLD_PMU0_ENABLE = 12995; // 2 +const static uint64_t SH_FLD_PMU0_SIZE = 12996; // 2 +const static uint64_t SH_FLD_PMU0_SIZE_LEN = 12997; // 2 +const static uint64_t SH_FLD_PMU1_ENABLE = 12998; // 2 +const static uint64_t SH_FLD_PMU1_SIZE = 12999; // 2 +const static uint64_t SH_FLD_PMU1_SIZE_LEN = 13000; // 2 +const static uint64_t SH_FLD_PMU2367_EVENT0_MODE = 13001; // 2 +const static uint64_t SH_FLD_PMU2367_EVENT0_MODE_LEN = 13002; // 2 +const static uint64_t SH_FLD_PMU2367_EVENT1_MODE = 13003; // 2 +const static uint64_t SH_FLD_PMU2367_EVENT1_MODE_LEN = 13004; // 2 +const static uint64_t SH_FLD_PMU2367_EVENT2_MODE = 13005; // 2 +const static uint64_t SH_FLD_PMU2367_EVENT2_MODE_LEN = 13006; // 2 +const static uint64_t SH_FLD_PMU2367_EVENT3_MODE = 13007; // 2 +const static uint64_t SH_FLD_PMU2367_EVENT3_MODE_LEN = 13008; // 2 +const static uint64_t SH_FLD_PMU23_LINK_SELECT = 13009; // 2 +const static uint64_t SH_FLD_PMU2_ENABLE = 13010; // 2 +const static uint64_t SH_FLD_PMU2_SIZE = 13011; // 2 +const static uint64_t SH_FLD_PMU2_SIZE_LEN = 13012; // 2 +const static uint64_t SH_FLD_PMU3_ENABLE = 13013; // 2 +const static uint64_t SH_FLD_PMU3_SIZE = 13014; // 2 +const static uint64_t SH_FLD_PMU3_SIZE_LEN = 13015; // 2 +const static uint64_t SH_FLD_PMU45_LINK_SELECT = 13016; // 2 +const static uint64_t SH_FLD_PMU4_ENABLE = 13017; // 2 +const static uint64_t SH_FLD_PMU5_ENABLE = 13018; // 2 +const static uint64_t SH_FLD_PMU67_LINK_SELECT = 13019; // 2 +const static uint64_t SH_FLD_PMU6_ENABLE = 13020; // 2 +const static uint64_t SH_FLD_PMU7_ENABLE = 13021; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT = 13022; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT_LEN = 13023; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER0_ENABLE = 13024; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER0_EVENT_SELECT = 13025; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER0_EVENT_SELECT_LEN = 13026; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER0_POSEDGE_SELECT = 13027; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT = 13028; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT_LEN = 13029; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER1_ENABLE = 13030; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER1_EVENT_SELECT = 13031; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER1_EVENT_SELECT_LEN = 13032; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER1_POSEDGE_SELECT = 13033; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT = 13034; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT_LEN = 13035; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER2_ENABLE = 13036; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER2_EVENT_SELECT = 13037; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER2_EVENT_SELECT_LEN = 13038; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER2_POSEDGE_SELECT = 13039; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT = 13040; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT_LEN = 13041; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER3_ENABLE = 13042; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER3_EVENT_SELECT = 13043; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER3_EVENT_SELECT_LEN = 13044; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER3_POSEDGE_SELECT = 13045; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER_FREEZE_MODE = 13046; // 2 +const static uint64_t SH_FLD_PMUA_COUNTER_RESET_MODE = 13047; // 2 +const static uint64_t SH_FLD_PMUA_PORT_SELECT = 13048; // 2 +const static uint64_t SH_FLD_PMUA_PORT_SELECT_LEN = 13049; // 2 +const static uint64_t SH_FLD_PMUA_PRESCALER_SELECT = 13050; // 2 +const static uint64_t SH_FLD_PMUA_PRESCALER_SELECT_LEN = 13051; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT = 13052; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT_LEN = 13053; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER0_ENABLE = 13054; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER0_EVENT_SELECT = 13055; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER0_EVENT_SELECT_LEN = 13056; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER0_POSEDGE_SELECT = 13057; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT = 13058; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT_LEN = 13059; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER1_ENABLE = 13060; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER1_EVENT_SELECT = 13061; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER1_EVENT_SELECT_LEN = 13062; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER1_POSEDGE_SELECT = 13063; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT = 13064; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT_LEN = 13065; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER2_ENABLE = 13066; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER2_EVENT_SELECT = 13067; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER2_EVENT_SELECT_LEN = 13068; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER2_POSEDGE_SELECT = 13069; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT = 13070; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT_LEN = 13071; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER3_ENABLE = 13072; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER3_EVENT_SELECT = 13073; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER3_EVENT_SELECT_LEN = 13074; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER3_POSEDGE_SELECT = 13075; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER_FREEZE_MODE = 13076; // 2 +const static uint64_t SH_FLD_PMUB_COUNTER_RESET_MODE = 13077; // 2 +const static uint64_t SH_FLD_PMUB_PORT_SELECT = 13078; // 2 +const static uint64_t SH_FLD_PMUB_PORT_SELECT_LEN = 13079; // 2 +const static uint64_t SH_FLD_PMUB_PRESCALER_SELECT = 13080; // 2 +const static uint64_t SH_FLD_PMUB_PRESCALER_SELECT_LEN = 13081; // 2 +const static uint64_t SH_FLD_PMULET_FREEZE_MODE = 13082; // 2 +const static uint64_t SH_FLD_PMULET_RESET_MODE = 13083; // 2 +const static uint64_t SH_FLD_PMU_BUS_ENABLE = 13084; // 2 +const static uint64_t SH_FLD_PMU_BUS_ENABLE_LEN = 13085; // 2 +const static uint64_t SH_FLD_PMU_ENABLE = 13086; // 2 +const static uint64_t SH_FLD_PMU_SELECT_HIGH = 13087; // 2 +const static uint64_t SH_FLD_PMU_SELECT_HIGH_LEN = 13088; // 2 +const static uint64_t SH_FLD_PMU_SELECT_LOW = 13089; // 2 +const static uint64_t SH_FLD_PMU_SELECT_LOW_LEN = 13090; // 2 +const static uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C0 = 13091; // 12 +const static uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL = 13092; // 12 +const static uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C1 = 13093; // 12 +const static uint64_t SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL = 13094; // 12 +const static uint64_t SH_FLD_PM_ENTRY_ACK_C0 = 13095; // 12 +const static uint64_t SH_FLD_PM_ENTRY_ACK_C0_ACTUAL = 13096; // 12 +const static uint64_t SH_FLD_PM_ENTRY_ACK_C1 = 13097; // 12 +const static uint64_t SH_FLD_PM_ENTRY_ACK_C1_ACTUAL = 13098; // 12 +const static uint64_t SH_FLD_PM_ERROR = 13099; // 6 +const static uint64_t SH_FLD_PM_EXIT_C0 = 13100; // 12 +const static uint64_t SH_FLD_PM_EXIT_C0_ACTUAL = 13101; // 12 +const static uint64_t SH_FLD_PM_EXIT_C1 = 13102; // 12 +const static uint64_t SH_FLD_PM_EXIT_C1_ACTUAL = 13103; // 12 +const static uint64_t SH_FLD_PM_STATE_ACTIVE_C0 = 13104; // 12 +const static uint64_t SH_FLD_PM_STATE_ACTIVE_C1 = 13105; // 12 +const static uint64_t SH_FLD_PM_STATE_ALL_HV_C0 = 13106; // 12 +const static uint64_t SH_FLD_PM_STATE_ALL_HV_C1 = 13107; // 12 +const static uint64_t SH_FLD_PM_STATE_C0 = 13108; // 12 +const static uint64_t SH_FLD_PM_STATE_C0_LEN = 13109; // 12 +const static uint64_t SH_FLD_PM_STATE_C1 = 13110; // 12 +const static uint64_t SH_FLD_PM_STATE_C1_LEN = 13111; // 12 +const static uint64_t SH_FLD_POCKET_ND_RATE1 = 13112; // 12 +const static uint64_t SH_FLD_POCKET_ND_RATE1_LEN = 13113; // 12 +const static uint64_t SH_FLD_POCKET_RATE1 = 13114; // 12 +const static uint64_t SH_FLD_POCKET_RATE1_LEN = 13115; // 12 +const static uint64_t SH_FLD_POCKET_RATE2 = 13116; // 12 +const static uint64_t SH_FLD_POCKET_RATE2_LEN = 13117; // 12 +const static uint64_t SH_FLD_POCKET_RATE3 = 13118; // 12 +const static uint64_t SH_FLD_POCKET_RATE3_LEN = 13119; // 12 +const static uint64_t SH_FLD_POD0 = 13120; // 38 +const static uint64_t SH_FLD_POD0_LEN = 13121; // 38 +const static uint64_t SH_FLD_POD1 = 13122; // 38 +const static uint64_t SH_FLD_POD10 = 13123; // 38 +const static uint64_t SH_FLD_POD10_LEN = 13124; // 38 +const static uint64_t SH_FLD_POD1_LEN = 13125; // 38 +const static uint64_t SH_FLD_POD2 = 13126; // 38 +const static uint64_t SH_FLD_POD2_LEN = 13127; // 38 +const static uint64_t SH_FLD_POD3 = 13128; // 38 +const static uint64_t SH_FLD_POD3_LEN = 13129; // 38 +const static uint64_t SH_FLD_POD4 = 13130; // 38 +const static uint64_t SH_FLD_POD4_LEN = 13131; // 38 +const static uint64_t SH_FLD_POD5 = 13132; // 38 +const static uint64_t SH_FLD_POD5_LEN = 13133; // 38 +const static uint64_t SH_FLD_POD6 = 13134; // 38 +const static uint64_t SH_FLD_POD6_LEN = 13135; // 38 +const static uint64_t SH_FLD_POD7 = 13136; // 38 +const static uint64_t SH_FLD_POD7_LEN = 13137; // 38 +const static uint64_t SH_FLD_POD8 = 13138; // 38 +const static uint64_t SH_FLD_POD8_LEN = 13139; // 38 +const static uint64_t SH_FLD_POD9 = 13140; // 38 +const static uint64_t SH_FLD_POD9_LEN = 13141; // 38 +const static uint64_t SH_FLD_POINTER = 13142; // 2 +const static uint64_t SH_FLD_POINTER_LEN = 13143; // 2 +const static uint64_t SH_FLD_POLLING_TIMEOUT_SEL = 13144; // 6 +const static uint64_t SH_FLD_POLLING_TIMEOUT_SEL_LEN = 13145; // 6 +const static uint64_t SH_FLD_POLL_BCST_RTY_MON = 13146; // 1 +const static uint64_t SH_FLD_POLL_DONE = 13147; // 1 +const static uint64_t SH_FLD_POOL = 13148; // 1 +const static uint64_t SH_FLD_POOL_LEN = 13149; // 1 +const static uint64_t SH_FLD_PORT0_ERROR_CODE = 13150; // 3 +const static uint64_t SH_FLD_PORT0_ERROR_CODE_0 = 13151; // 1 +const static uint64_t SH_FLD_PORT0_ERROR_CODE_0_LEN = 13152; // 1 +const static uint64_t SH_FLD_PORT0_ERROR_CODE_1 = 13153; // 2 +const static uint64_t SH_FLD_PORT0_ERROR_CODE_1_LEN = 13154; // 2 +const static uint64_t SH_FLD_PORT0_ERROR_CODE_2 = 13155; // 3 +const static uint64_t SH_FLD_PORT0_ERROR_CODE_2_LEN = 13156; // 3 +const static uint64_t SH_FLD_PORT0_ERROR_CODE_LEN = 13157; // 3 +const static uint64_t SH_FLD_PORT1_ERROR_CODE = 13158; // 3 +const static uint64_t SH_FLD_PORT1_ERROR_CODE_0 = 13159; // 1 +const static uint64_t SH_FLD_PORT1_ERROR_CODE_0_LEN = 13160; // 1 +const static uint64_t SH_FLD_PORT1_ERROR_CODE_1 = 13161; // 2 +const static uint64_t SH_FLD_PORT1_ERROR_CODE_1_LEN = 13162; // 2 +const static uint64_t SH_FLD_PORT1_ERROR_CODE_2 = 13163; // 3 +const static uint64_t SH_FLD_PORT1_ERROR_CODE_2_LEN = 13164; // 3 +const static uint64_t SH_FLD_PORT1_ERROR_CODE_LEN = 13165; // 3 +const static uint64_t SH_FLD_PORT2_ERROR_CODE = 13166; // 3 +const static uint64_t SH_FLD_PORT2_ERROR_CODE_0 = 13167; // 1 +const static uint64_t SH_FLD_PORT2_ERROR_CODE_0_LEN = 13168; // 1 +const static uint64_t SH_FLD_PORT2_ERROR_CODE_1 = 13169; // 2 +const static uint64_t SH_FLD_PORT2_ERROR_CODE_1_LEN = 13170; // 2 +const static uint64_t SH_FLD_PORT2_ERROR_CODE_2 = 13171; // 3 +const static uint64_t SH_FLD_PORT2_ERROR_CODE_2_LEN = 13172; // 3 +const static uint64_t SH_FLD_PORT2_ERROR_CODE_LEN = 13173; // 3 +const static uint64_t SH_FLD_PORT3_ERROR_CODE = 13174; // 3 +const static uint64_t SH_FLD_PORT3_ERROR_CODE_0 = 13175; // 1 +const static uint64_t SH_FLD_PORT3_ERROR_CODE_0_LEN = 13176; // 1 +const static uint64_t SH_FLD_PORT3_ERROR_CODE_1 = 13177; // 2 +const static uint64_t SH_FLD_PORT3_ERROR_CODE_1_LEN = 13178; // 2 +const static uint64_t SH_FLD_PORT3_ERROR_CODE_2 = 13179; // 3 +const static uint64_t SH_FLD_PORT3_ERROR_CODE_2_LEN = 13180; // 3 +const static uint64_t SH_FLD_PORT3_ERROR_CODE_LEN = 13181; // 3 +const static uint64_t SH_FLD_PORT4_ERROR_CODE = 13182; // 3 +const static uint64_t SH_FLD_PORT4_ERROR_CODE_0 = 13183; // 1 +const static uint64_t SH_FLD_PORT4_ERROR_CODE_0_LEN = 13184; // 1 +const static uint64_t SH_FLD_PORT4_ERROR_CODE_1 = 13185; // 2 +const static uint64_t SH_FLD_PORT4_ERROR_CODE_1_LEN = 13186; // 2 +const static uint64_t SH_FLD_PORT4_ERROR_CODE_2 = 13187; // 3 +const static uint64_t SH_FLD_PORT4_ERROR_CODE_2_LEN = 13188; // 3 +const static uint64_t SH_FLD_PORT4_ERROR_CODE_LEN = 13189; // 3 +const static uint64_t SH_FLD_PORT5_ERROR_CODE = 13190; // 3 +const static uint64_t SH_FLD_PORT5_ERROR_CODE_0 = 13191; // 1 +const static uint64_t SH_FLD_PORT5_ERROR_CODE_0_LEN = 13192; // 1 +const static uint64_t SH_FLD_PORT5_ERROR_CODE_1 = 13193; // 2 +const static uint64_t SH_FLD_PORT5_ERROR_CODE_1_LEN = 13194; // 2 +const static uint64_t SH_FLD_PORT5_ERROR_CODE_2 = 13195; // 3 +const static uint64_t SH_FLD_PORT5_ERROR_CODE_2_LEN = 13196; // 3 +const static uint64_t SH_FLD_PORT5_ERROR_CODE_LEN = 13197; // 3 +const static uint64_t SH_FLD_PORT6_ERROR_CODE = 13198; // 3 +const static uint64_t SH_FLD_PORT6_ERROR_CODE_0 = 13199; // 1 +const static uint64_t SH_FLD_PORT6_ERROR_CODE_0_LEN = 13200; // 1 +const static uint64_t SH_FLD_PORT6_ERROR_CODE_1 = 13201; // 2 +const static uint64_t SH_FLD_PORT6_ERROR_CODE_1_LEN = 13202; // 2 +const static uint64_t SH_FLD_PORT6_ERROR_CODE_2 = 13203; // 3 +const static uint64_t SH_FLD_PORT6_ERROR_CODE_2_LEN = 13204; // 3 +const static uint64_t SH_FLD_PORT6_ERROR_CODE_LEN = 13205; // 3 +const static uint64_t SH_FLD_PORT7_ERROR_CODE = 13206; // 3 +const static uint64_t SH_FLD_PORT7_ERROR_CODE_0 = 13207; // 1 +const static uint64_t SH_FLD_PORT7_ERROR_CODE_0_LEN = 13208; // 1 +const static uint64_t SH_FLD_PORT7_ERROR_CODE_1 = 13209; // 2 +const static uint64_t SH_FLD_PORT7_ERROR_CODE_1_LEN = 13210; // 2 +const static uint64_t SH_FLD_PORT7_ERROR_CODE_2 = 13211; // 3 +const static uint64_t SH_FLD_PORT7_ERROR_CODE_2_LEN = 13212; // 3 +const static uint64_t SH_FLD_PORT7_ERROR_CODE_LEN = 13213; // 3 +const static uint64_t SH_FLD_PORTPOWERDOWN = 13214; // 8 +const static uint64_t SH_FLD_PORT_0_ENABLE = 13215; // 1 +const static uint64_t SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP = 13216; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN = 13217; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP = 13218; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN = 13219; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_MPE_ON_RCE = 13220; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP = 13221; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN = 13222; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD = 13223; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN = 13224; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_IS_TCE = 13225; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD = 13226; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 13227; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_NCE_ON_RCE = 13228; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP = 13229; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN = 13230; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD = 13231; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN = 13232; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD = 13233; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 13234; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP = 13235; // 2 +const static uint64_t SH_FLD_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN = 13236; // 2 +const static uint64_t SH_FLD_PORT_1_ENABLE = 13237; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP = 13238; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_AUE_ADDR_TRAP_LEN = 13239; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP = 13240; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ADDR_TRAP_LEN = 13241; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_MPE_ON_RCE = 13242; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP = 13243; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ADDR_TRAP_LEN = 13244; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD = 13245; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN = 13246; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_IS_TCE = 13247; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD = 13248; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 13249; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_NCE_ON_RCE = 13250; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP = 13251; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_RCE_ADDR_TRAP_LEN = 13252; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD = 13253; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN = 13254; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD = 13255; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 13256; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP = 13257; // 2 +const static uint64_t SH_FLD_PORT_1_MAINLINE_UE_ADDR_TRAP_LEN = 13258; // 2 +const static uint64_t SH_FLD_PORT_2_ENABLE = 13259; // 3 +const static uint64_t SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP = 13260; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_AUE_ADDR_TRAP_LEN = 13261; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP = 13262; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ADDR_TRAP_LEN = 13263; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_MPE_ON_RCE = 13264; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP = 13265; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ADDR_TRAP_LEN = 13266; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD = 13267; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_GALOIS_FIELD_LEN = 13268; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_IS_TCE = 13269; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD = 13270; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 13271; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_NCE_ON_RCE = 13272; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP = 13273; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_RCE_ADDR_TRAP_LEN = 13274; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD = 13275; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_TCE_GALOIS_FIELD_LEN = 13276; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD = 13277; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 13278; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP = 13279; // 2 +const static uint64_t SH_FLD_PORT_2_MAINLINE_UE_ADDR_TRAP_LEN = 13280; // 2 +const static uint64_t SH_FLD_PORT_3_ENABLE = 13281; // 3 +const static uint64_t SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP = 13282; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_AUE_ADDR_TRAP_LEN = 13283; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP = 13284; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ADDR_TRAP_LEN = 13285; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_MPE_ON_RCE = 13286; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP = 13287; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ADDR_TRAP_LEN = 13288; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD = 13289; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_GALOIS_FIELD_LEN = 13290; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_IS_TCE = 13291; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD = 13292; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 13293; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_NCE_ON_RCE = 13294; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP = 13295; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_RCE_ADDR_TRAP_LEN = 13296; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD = 13297; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_TCE_GALOIS_FIELD_LEN = 13298; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD = 13299; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 13300; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP = 13301; // 2 +const static uint64_t SH_FLD_PORT_3_MAINLINE_UE_ADDR_TRAP_LEN = 13302; // 2 +const static uint64_t SH_FLD_PORT_4_ENABLE = 13303; // 3 +const static uint64_t SH_FLD_PORT_5_ENABLE = 13304; // 3 +const static uint64_t SH_FLD_PORT_6_ENABLE = 13305; // 3 +const static uint64_t SH_FLD_PORT_7_ENABLE = 13306; // 3 +const static uint64_t SH_FLD_PORT_ENABLE = 13307; // 3 +const static uint64_t SH_FLD_PORT_ERROR_RESET = 13308; // 1 +const static uint64_t SH_FLD_PORT_ERROR_RESET_1 = 13309; // 2 +const static uint64_t SH_FLD_PORT_ERROR_RESET_2 = 13310; // 3 +const static uint64_t SH_FLD_PORT_ERROR_RESET_3 = 13311; // 3 +const static uint64_t SH_FLD_PORT_ERROR_RESET_4 = 13312; // 3 +const static uint64_t SH_FLD_PORT_ERROR_RESET_5 = 13313; // 3 +const static uint64_t SH_FLD_PORT_ERROR_RESET_6 = 13314; // 3 +const static uint64_t SH_FLD_PORT_ERROR_RESET_7 = 13315; // 3 +const static uint64_t SH_FLD_PORT_FAIL = 13316; // 8 +const static uint64_t SH_FLD_PORT_GENERAL_RESET = 13317; // 1 +const static uint64_t SH_FLD_PORT_GENERAL_RESET_1 = 13318; // 2 +const static uint64_t SH_FLD_PORT_GENERAL_RESET_2 = 13319; // 3 +const static uint64_t SH_FLD_PORT_GENERAL_RESET_3 = 13320; // 3 +const static uint64_t SH_FLD_PORT_GENERAL_RESET_4 = 13321; // 3 +const static uint64_t SH_FLD_PORT_GENERAL_RESET_5 = 13322; // 3 +const static uint64_t SH_FLD_PORT_GENERAL_RESET_6 = 13323; // 3 +const static uint64_t SH_FLD_PORT_GENERAL_RESET_7 = 13324; // 3 +const static uint64_t SH_FLD_PORT_NUMBER_0 = 13325; // 2 +const static uint64_t SH_FLD_PORT_NUMBER_0_LEN = 13326; // 2 +const static uint64_t SH_FLD_PORT_NUMBER_1 = 13327; // 1 +const static uint64_t SH_FLD_PORT_NUMBER_1_LEN = 13328; // 1 +const static uint64_t SH_FLD_PORT_NUMBER_2 = 13329; // 1 +const static uint64_t SH_FLD_PORT_NUMBER_2_LEN = 13330; // 1 +const static uint64_t SH_FLD_PORT_NUMBER_3 = 13331; // 1 +const static uint64_t SH_FLD_PORT_NUMBER_3_LEN = 13332; // 1 +const static uint64_t SH_FLD_PORT_SEL = 13333; // 1 +const static uint64_t SH_FLD_PORT_SEL_LEN = 13334; // 1 +const static uint64_t SH_FLD_POWDN_DLY = 13335; // 30 +const static uint64_t SH_FLD_POWDN_DLY_LEN = 13336; // 30 +const static uint64_t SH_FLD_POWERBUS_DATA_HANG_ERROR = 13337; // 4 +const static uint64_t SH_FLD_POWERBUS_HANG_ERROR = 13338; // 4 +const static uint64_t SH_FLD_POWERBUS_INTERFACE_PE = 13339; // 4 +const static uint64_t SH_FLD_POWERBUS_MISC_ERROR = 13340; // 4 +const static uint64_t SH_FLD_POWERBUS_PROTOCOL_ERROR = 13341; // 4 +const static uint64_t SH_FLD_POWER_MANAGEMENT_INTERRUPT = 13342; // 1 +const static uint64_t SH_FLD_POWER_SAVING_LIMIT_A_N = 13343; // 96 +const static uint64_t SH_FLD_POWER_SAVING_LIMIT_A_N_LEN = 13344; // 96 +const static uint64_t SH_FLD_POWER_UP_CNTR_REF = 13345; // 1 +const static uint64_t SH_FLD_POWER_UP_CNTR_REF_LEN = 13346; // 1 +const static uint64_t SH_FLD_POWUP_DLY = 13347; // 30 +const static uint64_t SH_FLD_POWUP_DLY_LEN = 13348; // 30 +const static uint64_t SH_FLD_PPC405_CHIP_RESET = 13349; // 1 +const static uint64_t SH_FLD_PPC405_CHIP_RESET_MASK = 13350; // 1 +const static uint64_t SH_FLD_PPC405_CORE_RESET = 13351; // 1 +const static uint64_t SH_FLD_PPC405_CORE_RESET_MASK = 13352; // 1 +const static uint64_t SH_FLD_PPC405_DBGMSRWE = 13353; // 1 +const static uint64_t SH_FLD_PPC405_DBGMSRWE_MASK = 13354; // 1 +const static uint64_t SH_FLD_PPC405_DBGSTOPACK = 13355; // 1 +const static uint64_t SH_FLD_PPC405_DBGSTOPACK_MASK = 13356; // 1 +const static uint64_t SH_FLD_PPC405_HALT = 13357; // 1 +const static uint64_t SH_FLD_PPC405_SYSTEM_RESET = 13358; // 1 +const static uint64_t SH_FLD_PPC405_SYSTEM_RESET_MASK = 13359; // 1 +const static uint64_t SH_FLD_PPE_BREAKPOINT_ERROR = 13360; // 12 +const static uint64_t SH_FLD_PPE_DEBUG_TRIGGER = 13361; // 12 +const static uint64_t SH_FLD_PPE_EXTERNAL_ERROR = 13362; // 12 +const static uint64_t SH_FLD_PPE_HALTED = 13363; // 12 +const static uint64_t SH_FLD_PPE_INTERNAL_ERROR = 13364; // 12 +const static uint64_t SH_FLD_PPE_PROGRESS_ERROR = 13365; // 12 +const static uint64_t SH_FLD_PPE_RD_ACK_DEAD = 13366; // 12 +const static uint64_t SH_FLD_PPE_RD_CRESP_ADDR_ERR = 13367; // 12 +const static uint64_t SH_FLD_PPE_WATCHDOG = 13368; // 12 +const static uint64_t SH_FLD_PPE_WR_ACK_DEAD = 13369; // 12 +const static uint64_t SH_FLD_PPE_WR_CRESP_ADDR_ERR = 13370; // 12 +const static uint64_t SH_FLD_PPE_XIRAMEDR_EDR = 13371; // 4 +const static uint64_t SH_FLD_PPE_XIRAMEDR_EDR_LEN = 13372; // 4 +const static uint64_t SH_FLD_PPE_XIRAMGA_IR = 13373; // 4 +const static uint64_t SH_FLD_PPE_XIRAMGA_IR_LEN = 13374; // 4 +const static uint64_t SH_FLD_PPE_XIRAMRA_SPRG0 = 13375; // 4 +const static uint64_t SH_FLD_PPE_XIRAMRA_SPRG0_LEN = 13376; // 4 +const static uint64_t SH_FLD_PPE_XIXCR_XCR = 13377; // 4 +const static uint64_t SH_FLD_PPE_XIXCR_XCR_LEN = 13378; // 4 +const static uint64_t SH_FLD_PPM_SPARE_OUT_C0 = 13379; // 12 +const static uint64_t SH_FLD_PPM_SPARE_OUT_C1 = 13380; // 12 +const static uint64_t SH_FLD_PPM_WRITE_DISABLE = 13381; // 24 +const static uint64_t SH_FLD_PPM_WRITE_OVERRIDE = 13382; // 24 +const static uint64_t SH_FLD_PQ_STATE = 13383; // 1 +const static uint64_t SH_FLD_PQ_STATE_LEN = 13384; // 1 +const static uint64_t SH_FLD_PRB0 = 13385; // 12 +const static uint64_t SH_FLD_PRB1 = 13386; // 12 +const static uint64_t SH_FLD_PRBS_CHECK_SYNC = 13387; // 72 +const static uint64_t SH_FLD_PRBS_RXBIST_MODE = 13388; // 72 +const static uint64_t SH_FLD_PRBS_SCRAMBLE_MODE = 13389; // 144 +const static uint64_t SH_FLD_PRBS_SCRAMBLE_MODE_LEN = 13390; // 144 +const static uint64_t SH_FLD_PRBS_SEED_DDC = 13391; // 72 +const static uint64_t SH_FLD_PRBS_SEED_DFE = 13392; // 72 +const static uint64_t SH_FLD_PRBS_SEED_MODE = 13393; // 4 +const static uint64_t SH_FLD_PRBS_SEED_VALUE_0_15 = 13394; // 140 +const static uint64_t SH_FLD_PRBS_SEED_VALUE_0_15_LEN = 13395; // 140 +const static uint64_t SH_FLD_PRBS_SEED_VALUE_16_22 = 13396; // 140 +const static uint64_t SH_FLD_PRBS_SEED_VALUE_16_22_LEN = 13397; // 140 +const static uint64_t SH_FLD_PRBS_SLS_EXPECT = 13398; // 4 +const static uint64_t SH_FLD_PRBS_SLS_EXPECT_LEN = 13399; // 4 +const static uint64_t SH_FLD_PRBS_SYNC_MODE = 13400; // 72 +const static uint64_t SH_FLD_PRBS_TEST_DATA = 13401; // 120 +const static uint64_t SH_FLD_PRBS_TEST_DATA_LEN = 13402; // 120 +const static uint64_t SH_FLD_PRECISE_DIR_FLUSH_FAILED = 13403; // 2 +const static uint64_t SH_FLD_PRECISE_DIR_SIZE = 13404; // 2 +const static uint64_t SH_FLD_PRECISE_DIR_SIZE_LEN = 13405; // 2 +const static uint64_t SH_FLD_PRECLUDE = 13406; // 1 +const static uint64_t SH_FLD_PREF2DMD = 13407; // 1 +const static uint64_t SH_FLD_PREFETCH = 13408; // 6 +const static uint64_t SH_FLD_PREFETCH_CHANNEL_CNT = 13409; // 1 +const static uint64_t SH_FLD_PREFETCH_CHANNEL_CNT_LEN = 13410; // 1 +const static uint64_t SH_FLD_PREFETCH_DISABLE = 13411; // 6 +const static uint64_t SH_FLD_PREFETCH_DISTANCE = 13412; // 6 +const static uint64_t SH_FLD_PREFETCH_DISTANCE_LEN = 13413; // 6 +const static uint64_t SH_FLD_PREFETCH_LIMIT = 13414; // 8 +const static uint64_t SH_FLD_PREFETCH_LIMIT_LEN = 13415; // 8 +const static uint64_t SH_FLD_PREFEVOD = 13416; // 1 +const static uint64_t SH_FLD_PREF_DEPTH = 13417; // 1 +const static uint64_t SH_FLD_PREF_DEPTH_LEN = 13418; // 1 +const static uint64_t SH_FLD_PREF_THRSH0 = 13419; // 1 +const static uint64_t SH_FLD_PREF_THRSH0_LEN = 13420; // 1 +const static uint64_t SH_FLD_PREF_THRSH1 = 13421; // 1 +const static uint64_t SH_FLD_PREF_THRSH1_LEN = 13422; // 1 +const static uint64_t SH_FLD_PREF_THRSH2 = 13423; // 1 +const static uint64_t SH_FLD_PREF_THRSH2_LEN = 13424; // 1 +const static uint64_t SH_FLD_PREF_THRSH3 = 13425; // 1 +const static uint64_t SH_FLD_PREF_THRSH3_LEN = 13426; // 1 +const static uint64_t SH_FLD_PREF_TIMEOUT = 13427; // 1 +const static uint64_t SH_FLD_PREF_TIMEOUT_LEN = 13428; // 1 +const static uint64_t SH_FLD_PRESCALAR_SEL0 = 13429; // 2 +const static uint64_t SH_FLD_PRESCALAR_SEL0_LEN = 13430; // 2 +const static uint64_t SH_FLD_PRESCALAR_SEL1 = 13431; // 2 +const static uint64_t SH_FLD_PRESCALAR_SEL1_LEN = 13432; // 2 +const static uint64_t SH_FLD_PRESCALAR_SEL2 = 13433; // 2 +const static uint64_t SH_FLD_PRESCALAR_SEL2_LEN = 13434; // 2 +const static uint64_t SH_FLD_PRESCALAR_SEL3 = 13435; // 2 +const static uint64_t SH_FLD_PRESCALAR_SEL3_LEN = 13436; // 2 +const static uint64_t SH_FLD_PRESCALER_SEL = 13437; // 1 +const static uint64_t SH_FLD_PRESCALER_SEL_LEN = 13438; // 1 +const static uint64_t SH_FLD_PRESCALE_C0 = 13439; // 9 +const static uint64_t SH_FLD_PRESCALE_C0_LEN = 13440; // 9 +const static uint64_t SH_FLD_PRESCALE_C1 = 13441; // 9 +const static uint64_t SH_FLD_PRESCALE_C1_LEN = 13442; // 9 +const static uint64_t SH_FLD_PRESCALE_C2 = 13443; // 9 +const static uint64_t SH_FLD_PRESCALE_C2_LEN = 13444; // 9 +const static uint64_t SH_FLD_PRESCALE_C3 = 13445; // 9 +const static uint64_t SH_FLD_PRESCALE_C3_LEN = 13446; // 9 +const static uint64_t SH_FLD_PRESP_RTY_OTHER = 13447; // 2 +const static uint64_t SH_FLD_PREVENT_SBE_START = 13448; // 1 +const static uint64_t SH_FLD_PRGM_ADDR = 13449; // 1 +const static uint64_t SH_FLD_PRGM_ADDR_LEN = 13450; // 1 +const static uint64_t SH_FLD_PRGSM_BUSY = 13451; // 24 +const static uint64_t SH_FLD_PRGSM_BUSY_ON_THIS = 13452; // 24 +const static uint64_t SH_FLD_PRG_BIT_LOCATION = 13453; // 1 +const static uint64_t SH_FLD_PRG_BIT_LOCATION_LEN = 13454; // 1 +const static uint64_t SH_FLD_PRI = 13455; // 8 +const static uint64_t SH_FLD_PRIORITY = 13456; // 18 +const static uint64_t SH_FLD_PRIORITY_ENABLE = 13457; // 6 +const static uint64_t SH_FLD_PRIORITY_LEN = 13458; // 6 +const static uint64_t SH_FLD_PRIORITY_LIMIT_0_3 = 13459; // 1 +const static uint64_t SH_FLD_PRIORITY_LIMIT_0_3_LEN = 13460; // 1 +const static uint64_t SH_FLD_PRIORITY_LPID = 13461; // 6 +const static uint64_t SH_FLD_PRIORITY_LPID_LEN = 13462; // 6 +const static uint64_t SH_FLD_PRIORITY_PID = 13463; // 6 +const static uint64_t SH_FLD_PRIORITY_PID_LEN = 13464; // 6 +const static uint64_t SH_FLD_PRIORITY_PRIMAX = 13465; // 3 +const static uint64_t SH_FLD_PRIORITY_PRIMAX_LEN = 13466; // 3 +const static uint64_t SH_FLD_PRIORITY_QUEUED = 13467; // 6 +const static uint64_t SH_FLD_PRIORITY_QUEUED_LEN = 13468; // 6 +const static uint64_t SH_FLD_PRIORITY_READ_OFFSET = 13469; // 6 +const static uint64_t SH_FLD_PRIORITY_READ_OFFSET_LEN = 13470; // 6 +const static uint64_t SH_FLD_PRIORITY_SIZE = 13471; // 6 +const static uint64_t SH_FLD_PRIORITY_SIZE_LEN = 13472; // 6 +const static uint64_t SH_FLD_PRIORITY_TID = 13473; // 6 +const static uint64_t SH_FLD_PRIORITY_TID_LEN = 13474; // 6 +const static uint64_t SH_FLD_PRI_I_PATH_STEP_CHECK_ENABLE = 13475; // 1 +const static uint64_t SH_FLD_PRI_LEN = 13476; // 8 +const static uint64_t SH_FLD_PRI_M_PATH_0_STEP_CHECK_ENABLE = 13477; // 1 +const static uint64_t SH_FLD_PRI_M_PATH_1_STEP_CHECK_ENABLE = 13478; // 1 +const static uint64_t SH_FLD_PRI_M_PATH_SELECT = 13479; // 2 +const static uint64_t SH_FLD_PRI_M_S_DRAWER_SELECT = 13480; // 2 +const static uint64_t SH_FLD_PRI_M_S_SELECT = 13481; // 2 +const static uint64_t SH_FLD_PRI_SEC_SELECT = 13482; // 1 +const static uint64_t SH_FLD_PRI_SEC_SELECT_LEN = 13483; // 1 +const static uint64_t SH_FLD_PRI_SELECT = 13484; // 1 +const static uint64_t SH_FLD_PRI_STATE_MACHINE_RESET = 13485; // 6 +const static uint64_t SH_FLD_PRI_S_PATH_0_STEP_CHECK_ENABLE = 13486; // 1 +const static uint64_t SH_FLD_PRI_S_PATH_1_STEP_CHECK_ENABLE = 13487; // 1 +const static uint64_t SH_FLD_PRI_S_PATH_SELECT = 13488; // 1 +const static uint64_t SH_FLD_PRI_V = 13489; // 8 +const static uint64_t SH_FLD_PROBE_0_TOGGLE_ENABLE = 13490; // 1 +const static uint64_t SH_FLD_PROBE_1_TOGGLE_ENABLE = 13491; // 1 +const static uint64_t SH_FLD_PROBE_2_TOGGLE_ENABLE = 13492; // 1 +const static uint64_t SH_FLD_PROBE_3_TOGGLE_ENABLE = 13493; // 1 +const static uint64_t SH_FLD_PROC_RCVY_AGAIN = 13494; // 96 +const static uint64_t SH_FLD_PROC_RCVY_DONE = 13495; // 96 +const static uint64_t SH_FLD_PROGRAM_ENABLE = 13496; // 1 +const static uint64_t SH_FLD_PROG_REQ_DELAY = 13497; // 1 +const static uint64_t SH_FLD_PROG_REQ_DELAY_LEN = 13498; // 1 +const static uint64_t SH_FLD_PROTECTION_CHECK = 13499; // 1 +const static uint64_t SH_FLD_PROTOCOL = 13500; // 8 +const static uint64_t SH_FLD_PROTOCOL_CHECKSTOP = 13501; // 2 +const static uint64_t SH_FLD_PROTOCOL_ERROR = 13502; // 45 +const static uint64_t SH_FLD_PROTOCOL_LEN = 13503; // 8 +const static uint64_t SH_FLD_PROT_EX_SPARE0 = 13504; // 1 +const static uint64_t SH_FLD_PROT_EX_SPARE1 = 13505; // 1 +const static uint64_t SH_FLD_PROT_TP_SPARE0 = 13506; // 1 +const static uint64_t SH_FLD_PROT_TP_SPARE1 = 13507; // 1 +const static uint64_t SH_FLD_PROT_TP_SPARE2 = 13508; // 1 +const static uint64_t SH_FLD_PRPG_A_VAL = 13509; // 43 +const static uint64_t SH_FLD_PRPG_A_VAL_LEN = 13510; // 43 +const static uint64_t SH_FLD_PRPG_B_VAL = 13511; // 43 +const static uint64_t SH_FLD_PRPG_B_VAL_LEN = 13512; // 43 +const static uint64_t SH_FLD_PRPG_MODE = 13513; // 43 +const static uint64_t SH_FLD_PRPG_VALUE = 13514; // 43 +const static uint64_t SH_FLD_PRPG_VALUE_LEN = 13515; // 43 +const static uint64_t SH_FLD_PRPG_WEIGHTING = 13516; // 43 +const static uint64_t SH_FLD_PRPG_WEIGHTING_LEN = 13517; // 43 +const static uint64_t SH_FLD_PRS = 13518; // 8 +const static uint64_t SH_FLD_PRV_BUS0_STG2_SEL = 13519; // 1 +const static uint64_t SH_FLD_PRV_BUS1_STG2_SEL = 13520; // 1 +const static uint64_t SH_FLD_PR_BUMP_SL_1UI = 13521; // 120 +const static uint64_t SH_FLD_PR_BUMP_SR_1UI = 13522; // 120 +const static uint64_t SH_FLD_PR_BUMP_TO_CENTER = 13523; // 72 +const static uint64_t SH_FLD_PR_BUMP_TO_EDGE_A = 13524; // 120 +const static uint64_t SH_FLD_PR_BUMP_TO_EDGE_B = 13525; // 48 +const static uint64_t SH_FLD_PR_DATA_A_OFFSET = 13526; // 120 +const static uint64_t SH_FLD_PR_DATA_A_OFFSET_LEN = 13527; // 120 +const static uint64_t SH_FLD_PR_DATA_B_OFFSET = 13528; // 120 +const static uint64_t SH_FLD_PR_DATA_B_OFFSET_LEN = 13529; // 120 +const static uint64_t SH_FLD_PR_DDC_A = 13530; // 120 +const static uint64_t SH_FLD_PR_DDC_B = 13531; // 48 +const static uint64_t SH_FLD_PR_EDGE_TRACK_CNTL = 13532; // 120 +const static uint64_t SH_FLD_PR_EDGE_TRACK_CNTL_LEN = 13533; // 120 +const static uint64_t SH_FLD_PR_FW_INERTIA_AMT = 13534; // 48 +const static uint64_t SH_FLD_PR_FW_INERTIA_AMT_LEN = 13535; // 48 +const static uint64_t SH_FLD_PR_FW_OFF = 13536; // 48 +const static uint64_t SH_FLD_PR_HALFRATE_MODE = 13537; // 120 +const static uint64_t SH_FLD_PR_INVALID_LOCK_BUMP_SIZE = 13538; // 120 +const static uint64_t SH_FLD_PR_INVALID_LOCK_BUMP_SIZE_LEN = 13539; // 120 +const static uint64_t SH_FLD_PR_INVALID_LOCK_FILTER_EN = 13540; // 120 +const static uint64_t SH_FLD_PR_IQ_RES_SEL = 13541; // 120 +const static uint64_t SH_FLD_PR_IQ_RES_SEL_LEN = 13542; // 120 +const static uint64_t SH_FLD_PR_LOCK_DONE = 13543; // 120 +const static uint64_t SH_FLD_PR_PHASE_STEP = 13544; // 120 +const static uint64_t SH_FLD_PR_PHASE_STEP_LEN = 13545; // 120 +const static uint64_t SH_FLD_PR_RESET = 13546; // 48 +const static uint64_t SH_FLD_PR_TRACE_DDC_SM = 13547; // 120 +const static uint64_t SH_FLD_PR_TRACE_DDC_SM_LEN = 13548; // 120 +const static uint64_t SH_FLD_PR_TRACE_DDC_STOP = 13549; // 120 +const static uint64_t SH_FLD_PR_TRACE_WOBBLE_SM = 13550; // 120 +const static uint64_t SH_FLD_PR_TRACE_WOBBLE_SM_LEN = 13551; // 120 +const static uint64_t SH_FLD_PR_TRACE_WOBBLE_STOP = 13552; // 120 +const static uint64_t SH_FLD_PR_USE_DFE_CLOCK_A = 13553; // 120 +const static uint64_t SH_FLD_PR_USE_DFE_CLOCK_B = 13554; // 48 +const static uint64_t SH_FLD_PR_WOBBLE_A = 13555; // 120 +const static uint64_t SH_FLD_PR_WOBBLE_B = 13556; // 48 +const static uint64_t SH_FLD_PR_WOBBLE_EDGE = 13557; // 48 +const static uint64_t SH_FLD_PSAVE_ANA_REQ_DIS = 13558; // 48 +const static uint64_t SH_FLD_PSAVE_DIG_REQ_DIS = 13559; // 48 +const static uint64_t SH_FLD_PSAVE_MODE_DISABLE = 13560; // 140 +const static uint64_t SH_FLD_PSAVE_MODE_TIMEOUT_SEL = 13561; // 4 +const static uint64_t SH_FLD_PSAVE_MODE_TIMEOUT_SEL_LEN = 13562; // 4 +const static uint64_t SH_FLD_PSAVE_REQ_DIS = 13563; // 48 +const static uint64_t SH_FLD_PSAVE_TIMER_WAKEUP_MODE = 13564; // 4 +const static uint64_t SH_FLD_PSAVE_WAKEUP_LANE0_ENABLE = 13565; // 4 +const static uint64_t SH_FLD_PSCR_OVERRIDE_EN = 13566; // 12 +const static uint64_t SH_FLD_PSEG_MAIN_EN = 13567; // 6 +const static uint64_t SH_FLD_PSEG_MAIN_EN_LEN = 13568; // 6 +const static uint64_t SH_FLD_PSEG_MARGINPD_EN = 13569; // 6 +const static uint64_t SH_FLD_PSEG_MARGINPD_EN_LEN = 13570; // 6 +const static uint64_t SH_FLD_PSEG_MARGINPU_EN = 13571; // 6 +const static uint64_t SH_FLD_PSEG_MARGINPU_EN_LEN = 13572; // 6 +const static uint64_t SH_FLD_PSEG_POST_EN = 13573; // 2 +const static uint64_t SH_FLD_PSEG_POST_EN_LEN = 13574; // 2 +const static uint64_t SH_FLD_PSEG_POST_SEL = 13575; // 2 +const static uint64_t SH_FLD_PSEG_POST_SEL_LEN = 13576; // 2 +const static uint64_t SH_FLD_PSEG_PRE_EN = 13577; // 6 +const static uint64_t SH_FLD_PSEG_PRE_EN_LEN = 13578; // 6 +const static uint64_t SH_FLD_PSEG_PRE_SEL = 13579; // 6 +const static uint64_t SH_FLD_PSEG_PRE_SEL_LEN = 13580; // 6 +const static uint64_t SH_FLD_PSIFSP_ACK_TIMEOUT = 13581; // 1 +const static uint64_t SH_FLD_PSIFSP_DMAR_OUTSTANDING = 13582; // 1 +const static uint64_t SH_FLD_PSIFSP_DMA_ADDR_ERR = 13583; // 1 +const static uint64_t SH_FLD_PSIFSP_DMA_ERR = 13584; // 1 +const static uint64_t SH_FLD_PSIFSP_INT_BUSY = 13585; // 1 +const static uint64_t SH_FLD_PSIFSP_INV_OP = 13586; // 1 +const static uint64_t SH_FLD_PSIFSP_LOAD_OUTSTANDING = 13587; // 1 +const static uint64_t SH_FLD_PSIFSP_MMIO_ADDR_ERR = 13588; // 1 +const static uint64_t SH_FLD_PSIFSP_MMIO_LENGTH_ERR = 13589; // 1 +const static uint64_t SH_FLD_PSIFSP_MMIO_LOAD_TIMEOUT = 13590; // 1 +const static uint64_t SH_FLD_PSIFSP_MMIO_TYPE_ERR = 13591; // 1 +const static uint64_t SH_FLD_PSIFSP_PAGE_FAULT = 13592; // 1 +const static uint64_t SH_FLD_PSIFSP_PERR = 13593; // 1 +const static uint64_t SH_FLD_PSIFSP_TCE_EXTENT_ERR = 13594; // 1 +const static uint64_t SH_FLD_PSIHB2FSP_INJ_CONST = 13595; // 1 +const static uint64_t SH_FLD_PSIHB2FSP_INJ_ERR_BITS = 13596; // 1 +const static uint64_t SH_FLD_PSIHB2FSP_INJ_ERR_BITS_LEN = 13597; // 1 +const static uint64_t SH_FLD_PSIHB2FSP_INJ_ONCE = 13598; // 1 +const static uint64_t SH_FLD_PSIHB2PB_INJ_CONST = 13599; // 1 +const static uint64_t SH_FLD_PSIHB2PB_INJ_ERR_BITS = 13600; // 1 +const static uint64_t SH_FLD_PSIHB2PB_INJ_ERR_BITS_LEN = 13601; // 1 +const static uint64_t SH_FLD_PSIHB2PB_INJ_ONCE = 13602; // 1 +const static uint64_t SH_FLD_PSIHBC_RESET = 13603; // 1 +const static uint64_t SH_FLD_PSIRFACC_C_RXDATA_RDY_ERR = 13604; // 1 +const static uint64_t SH_FLD_PSIRFACC_RADDR_PCK = 13605; // 1 +const static uint64_t SH_FLD_PSIRFACC_RCTRL_PCK = 13606; // 1 +const static uint64_t SH_FLD_PSIRFACC_RDL_FSM_PCK = 13607; // 1 +const static uint64_t SH_FLD_PSIRFACC_RFSM_PCK = 13608; // 1 +const static uint64_t SH_FLD_PSIRFACC_RLINK_STATE_LT_02 = 13609; // 1 +const static uint64_t SH_FLD_PSIRFACC_RXSC_PCK = 13610; // 1 +const static uint64_t SH_FLD_PSIRFACC_TADDR_PCK = 13611; // 1 +const static uint64_t SH_FLD_PSIRFACC_TCTRL_PCK = 13612; // 1 +const static uint64_t SH_FLD_PSIRFACC_TDL_CMD_CTRL_PCK = 13613; // 1 +const static uint64_t SH_FLD_PSIRFACC_TDL_FSM_PCK = 13614; // 1 +const static uint64_t SH_FLD_PSIRFACC_TDL_RETRY_ERR = 13615; // 1 +const static uint64_t SH_FLD_PSIRFACC_TDL_RSP_CTRL_PCK = 13616; // 1 +const static uint64_t SH_FLD_PSIRFACC_TFSM_PCK = 13617; // 1 +const static uint64_t SH_FLD_PSIRFACC_TXSC_PCK = 13618; // 1 +const static uint64_t SH_FLD_PSIRXBFF_DATAO_PCK = 13619; // 1 +const static uint64_t SH_FLD_PSIRXBFF_DATA_PCK = 13620; // 1 +const static uint64_t SH_FLD_PSIRXBFF_RFC_PCK = 13621; // 1 +const static uint64_t SH_FLD_PSIRXEI_SHIFT_PCK = 13622; // 1 +const static uint64_t SH_FLD_PSIRXEI_TRANSMIT_PCK = 13623; // 1 +const static uint64_t SH_FLD_PSIRXINS_DATA_PCK = 13624; // 1 +const static uint64_t SH_FLD_PSIRXINS_OVERRUN = 13625; // 1 +const static uint64_t SH_FLD_PSIRXINS_RFGSHIFT_PCK = 13626; // 1 +const static uint64_t SH_FLD_PSIRXINS_RZRTMP_PCK = 13627; // 1 +const static uint64_t SH_FLD_PSIRXLC_CE_RF = 13628; // 1 +const static uint64_t SH_FLD_PSIRXLC_DATA_BUFF_PCK = 13629; // 1 +const static uint64_t SH_FLD_PSIRXLC_DATA_GXST1_PCK_2N = 13630; // 1 +const static uint64_t SH_FLD_PSIRXLC_DATA_PCK = 13631; // 1 +const static uint64_t SH_FLD_PSIRXLC_FSM_PCK = 13632; // 1 +const static uint64_t SH_FLD_PSIRXLC_RADDR_PCK = 13633; // 1 +const static uint64_t SH_FLD_PSIRXLC_RCTRL_PCK = 13634; // 1 +const static uint64_t SH_FLD_PSIRXLC_UE_RF = 13635; // 1 +const static uint64_t SH_FLD_PSITXBFF_DATA_PCK = 13636; // 1 +const static uint64_t SH_FLD_PSITXBFF_TDO_PCK = 13637; // 1 +const static uint64_t SH_FLD_PSITXBFF_TFC_PCK = 13638; // 1 +const static uint64_t SH_FLD_PSITXEI_SHIFT_PCK = 13639; // 1 +const static uint64_t SH_FLD_PSITXEI_TRANSMIT_PCK = 13640; // 1 +const static uint64_t SH_FLD_PSITXINS_DATA_PCK = 13641; // 1 +const static uint64_t SH_FLD_PSITXINS_PARITY = 13642; // 1 +const static uint64_t SH_FLD_PSITXINS_TZRTMP_PCK = 13643; // 1 +const static uint64_t SH_FLD_PSITXINS_UNDERRUN = 13644; // 1 +const static uint64_t SH_FLD_PSITXLC_CE_GX_2N = 13645; // 1 +const static uint64_t SH_FLD_PSITXLC_CE_RF = 13646; // 1 +const static uint64_t SH_FLD_PSITXLC_DATA_BUFF_PCK = 13647; // 1 +const static uint64_t SH_FLD_PSITXLC_DATA_GXST2_PCK_2N = 13648; // 1 +const static uint64_t SH_FLD_PSITXLC_DATA_GXST3_PCK_2N = 13649; // 1 +const static uint64_t SH_FLD_PSITXLC_FSM_PCK = 13650; // 1 +const static uint64_t SH_FLD_PSITXLC_TADDR_PCK = 13651; // 1 +const static uint64_t SH_FLD_PSITXLC_TCTRL_PCK = 13652; // 1 +const static uint64_t SH_FLD_PSITXLC_TDO_PCK = 13653; // 1 +const static uint64_t SH_FLD_PSITXLC_UE_GX_2N = 13654; // 1 +const static uint64_t SH_FLD_PSITXLC_UE_RF = 13655; // 1 +const static uint64_t SH_FLD_PSI_ALERT1 = 13656; // 1 +const static uint64_t SH_FLD_PSI_ALERT2 = 13657; // 1 +const static uint64_t SH_FLD_PSI_LINK_ENABLE = 13658; // 1 +const static uint64_t SH_FLD_PSI_LINK_INACTIVE_TRANS = 13659; // 1 +const static uint64_t SH_FLD_PSI_RESERVED0 = 13660; // 2 +const static uint64_t SH_FLD_PSI_RESERVED1 = 13661; // 2 +const static uint64_t SH_FLD_PSI_RESERVED2 = 13662; // 2 +const static uint64_t SH_FLD_PSI_RESERVED3 = 13663; // 2 +const static uint64_t SH_FLD_PSI_RESERVED4 = 13664; // 2 +const static uint64_t SH_FLD_PSI_UE = 13665; // 1 +const static uint64_t SH_FLD_PSI_XMIT_ERROR = 13666; // 1 +const static uint64_t SH_FLD_PSL_CMD_SUE = 13667; // 4 +const static uint64_t SH_FLD_PSL_CMD_UE = 13668; // 4 +const static uint64_t SH_FLD_PSL_CREDIT_TIMEOUT_ERR = 13669; // 4 +const static uint64_t SH_FLD_PSSBRIDGE_ONGOING = 13670; // 1 +const static uint64_t SH_FLD_PSS_HAM = 13671; // 3 +const static uint64_t SH_FLD_PSS_HAM_CORE_INTERRUPT_MASK = 13672; // 1 +const static uint64_t SH_FLD_PSTATE_A_THRESHOLD = 13673; // 24 +const static uint64_t SH_FLD_PSTATE_A_THRESHOLD_LEN = 13674; // 24 +const static uint64_t SH_FLD_PSTATE_B_THRESHOLD = 13675; // 24 +const static uint64_t SH_FLD_PSTATE_B_THRESHOLD_LEN = 13676; // 24 +const static uint64_t SH_FLD_PS_SPARE1 = 13677; // 1 +const static uint64_t SH_FLD_PTCR = 13678; // 1 +const static uint64_t SH_FLD_PTCR_LEN = 13679; // 1 +const static uint64_t SH_FLD_PTSPARE6 = 13680; // 2 +const static uint64_t SH_FLD_PTSPARE7 = 13681; // 2 +const static uint64_t SH_FLD_PULL_EMPTY = 13682; // 4 +const static uint64_t SH_FLD_PULL_ENABLE = 13683; // 4 +const static uint64_t SH_FLD_PULL_FULL = 13684; // 4 +const static uint64_t SH_FLD_PULL_INTR_ACTION_0_1 = 13685; // 4 +const static uint64_t SH_FLD_PULL_INTR_ACTION_0_1_LEN = 13686; // 4 +const static uint64_t SH_FLD_PULL_LENGTH = 13687; // 4 +const static uint64_t SH_FLD_PULL_LENGTH_LEN = 13688; // 4 +const static uint64_t SH_FLD_PULL_READ_PTR = 13689; // 4 +const static uint64_t SH_FLD_PULL_READ_PTR_LEN = 13690; // 4 +const static uint64_t SH_FLD_PULL_READ_UNDERFLOW = 13691; // 4 +const static uint64_t SH_FLD_PULL_READ_UNDERFLOW_EN = 13692; // 4 +const static uint64_t SH_FLD_PULL_REGION = 13693; // 4 +const static uint64_t SH_FLD_PULL_REGION_LEN = 13694; // 4 +const static uint64_t SH_FLD_PULL_START = 13695; // 4 +const static uint64_t SH_FLD_PULL_START_LEN = 13696; // 4 +const static uint64_t SH_FLD_PULL_WRITE_OVERFLOW = 13697; // 4 +const static uint64_t SH_FLD_PULL_WRITE_PTR = 13698; // 4 +const static uint64_t SH_FLD_PULL_WRITE_PTR_LEN = 13699; // 4 +const static uint64_t SH_FLD_PULSE1_CNTR = 13700; // 1 +const static uint64_t SH_FLD_PULSE1_CNTR_LEN = 13701; // 1 +const static uint64_t SH_FLD_PULSE2_CNTR = 13702; // 1 +const static uint64_t SH_FLD_PULSE2_CNTR_LEN = 13703; // 1 +const static uint64_t SH_FLD_PULSE_DELAY = 13704; // 43 +const static uint64_t SH_FLD_PULSE_DELAY_LEN = 13705; // 43 +const static uint64_t SH_FLD_PULSE_DROOP_DATA = 13706; // 6 +const static uint64_t SH_FLD_PULSE_DROOP_DATA_LEN = 13707; // 6 +const static uint64_t SH_FLD_PULSE_DROOP_ENABLE = 13708; // 6 +const static uint64_t SH_FLD_PULSE_INPUT_SEL = 13709; // 43 +const static uint64_t SH_FLD_PUMP_MODE = 13710; // 1 +const static uint64_t SH_FLD_PUP_LITE_WAIT_SEL = 13711; // 4 +const static uint64_t SH_FLD_PUP_LITE_WAIT_SEL_LEN = 13712; // 4 +const static uint64_t SH_FLD_PUSH_EMPTY = 13713; // 6 +const static uint64_t SH_FLD_PUSH_ENABLE = 13714; // 6 +const static uint64_t SH_FLD_PUSH_FULL = 13715; // 6 +const static uint64_t SH_FLD_PUSH_INTR_ACTION_0_1 = 13716; // 6 +const static uint64_t SH_FLD_PUSH_INTR_ACTION_0_1_LEN = 13717; // 6 +const static uint64_t SH_FLD_PUSH_LENGTH = 13718; // 6 +const static uint64_t SH_FLD_PUSH_LENGTH_LEN = 13719; // 6 +const static uint64_t SH_FLD_PUSH_READ_PTR = 13720; // 6 +const static uint64_t SH_FLD_PUSH_READ_PTR_LEN = 13721; // 6 +const static uint64_t SH_FLD_PUSH_READ_UNDERFLOW = 13722; // 4 +const static uint64_t SH_FLD_PUSH_REGION = 13723; // 4 +const static uint64_t SH_FLD_PUSH_REGION_LEN = 13724; // 4 +const static uint64_t SH_FLD_PUSH_START = 13725; // 6 +const static uint64_t SH_FLD_PUSH_START_LEN = 13726; // 6 +const static uint64_t SH_FLD_PUSH_WRITE_OVERFLOW = 13727; // 4 +const static uint64_t SH_FLD_PUSH_WRITE_OVERFLOW_EN = 13728; // 4 +const static uint64_t SH_FLD_PUSH_WRITE_PTR = 13729; // 6 +const static uint64_t SH_FLD_PUSH_WRITE_PTR_LEN = 13730; // 6 +const static uint64_t SH_FLD_PU_BIT_ENABLES = 13731; // 1 +const static uint64_t SH_FLD_PU_BIT_ENABLES_LEN = 13732; // 1 +const static uint64_t SH_FLD_PU_CNTL_UNUSED = 13733; // 1 +const static uint64_t SH_FLD_PU_CNTL_UNUSED_LEN = 13734; // 1 +const static uint64_t SH_FLD_PU_COUNTS = 13735; // 8 +const static uint64_t SH_FLD_PU_COUNTS_LEN = 13736; // 8 +const static uint64_t SH_FLD_PVREF_ERROR_EN = 13737; // 1 +const static uint64_t SH_FLD_PVREF_ERROR_EN_LEN = 13738; // 1 +const static uint64_t SH_FLD_PVREF_ERROR_FINE = 13739; // 1 +const static uint64_t SH_FLD_PVREF_ERROR_GROSS = 13740; // 1 +const static uint64_t SH_FLD_PVREF_FAIL = 13741; // 12 +const static uint64_t SH_FLD_PVTN = 13742; // 16 +const static uint64_t SH_FLD_PVTNL_ENC = 13743; // 1 +const static uint64_t SH_FLD_PVTNL_ENC_LEN = 13744; // 1 +const static uint64_t SH_FLD_PVTN_LEN = 13745; // 16 +const static uint64_t SH_FLD_PVTP = 13746; // 16 +const static uint64_t SH_FLD_PVTPL_ENC = 13747; // 1 +const static uint64_t SH_FLD_PVTPL_ENC_LEN = 13748; // 1 +const static uint64_t SH_FLD_PVTP_LEN = 13749; // 16 +const static uint64_t SH_FLD_PWR0 = 13750; // 12 +const static uint64_t SH_FLD_PWR1 = 13751; // 12 +const static uint64_t SH_FLD_QPPM_ONGOING = 13752; // 24 +const static uint64_t SH_FLD_QPPM_RDATA = 13753; // 24 +const static uint64_t SH_FLD_QPPM_RDATA_LEN = 13754; // 24 +const static uint64_t SH_FLD_QPPM_REG = 13755; // 24 +const static uint64_t SH_FLD_QPPM_REG_LEN = 13756; // 24 +const static uint64_t SH_FLD_QPPM_RNW = 13757; // 24 +const static uint64_t SH_FLD_QPPM_STATUS = 13758; // 24 +const static uint64_t SH_FLD_QPPM_STATUS_LEN = 13759; // 24 +const static uint64_t SH_FLD_QPPM_WDATA = 13760; // 24 +const static uint64_t SH_FLD_QPPM_WDATA_LEN = 13761; // 24 +const static uint64_t SH_FLD_QUA = 13762; // 8 +const static uint64_t SH_FLD_QUAD_CHECKSTOP = 13763; // 12 +const static uint64_t SH_FLD_QUAD_CLK_SB_OVERRIDE = 13764; // 24 +const static uint64_t SH_FLD_QUAD_CLK_SW_OVERRIDE = 13765; // 24 +const static uint64_t SH_FLD_QUAD_SEL = 13766; // 6 +const static uint64_t SH_FLD_QUAD_SEL_LEN = 13767; // 6 +const static uint64_t SH_FLD_QUAD_STOPPED = 13768; // 1 +const static uint64_t SH_FLD_QUAD_STOPPED_LEN = 13769; // 1 +const static uint64_t SH_FLD_QUA_LEN = 13770; // 8 +const static uint64_t SH_FLD_QUA_V = 13771; // 8 +const static uint64_t SH_FLD_QUEUED_RD_EN = 13772; // 12 +const static uint64_t SH_FLD_QUEUED_WR_EN = 13773; // 12 +const static uint64_t SH_FLD_QUEUE_DISABLE = 13774; // 6 +const static uint64_t SH_FLD_QUEUE_NOT_EMPTY = 13775; // 6 +const static uint64_t SH_FLD_QUIESCE = 13776; // 1 +const static uint64_t SH_FLD_QUIESCED = 13777; // 1 +const static uint64_t SH_FLD_QUIESCE_ACHEIVED = 13778; // 1 +const static uint64_t SH_FLD_QUIESCE_AUTO_RESET = 13779; // 1 +const static uint64_t SH_FLD_QUIESCE_DONE = 13780; // 2 +const static uint64_t SH_FLD_QUIESCE_FAILED = 13781; // 1 +const static uint64_t SH_FLD_QUIESCE_PB = 13782; // 1 +const static uint64_t SH_FLD_QUIESCE_REQUEST = 13783; // 1 +const static uint64_t SH_FLD_R = 13784; // 8 +const static uint64_t SH_FLD_R0_COUNT = 13785; // 12 +const static uint64_t SH_FLD_R0_COUNT_LEN = 13786; // 12 +const static uint64_t SH_FLD_R15_BIT_MAP = 13787; // 8 +const static uint64_t SH_FLD_R15_BIT_MAP_LEN = 13788; // 8 +const static uint64_t SH_FLD_R16_BIT_MAP = 13789; // 8 +const static uint64_t SH_FLD_R16_BIT_MAP_LEN = 13790; // 8 +const static uint64_t SH_FLD_R17_BIT_MAP = 13791; // 8 +const static uint64_t SH_FLD_R17_BIT_MAP_LEN = 13792; // 8 +const static uint64_t SH_FLD_R1_COUNT = 13793; // 12 +const static uint64_t SH_FLD_R1_COUNT_LEN = 13794; // 12 +const static uint64_t SH_FLD_R2_COUNT = 13795; // 12 +const static uint64_t SH_FLD_R2_COUNT_LEN = 13796; // 12 +const static uint64_t SH_FLD_RAND_ADDR_ALL_ADDR_MODE_EN = 13797; // 2 +const static uint64_t SH_FLD_RAND_EVENT = 13798; // 1 +const static uint64_t SH_FLD_RAND_EVENT_LEN = 13799; // 1 +const static uint64_t SH_FLD_RANGE = 13800; // 1 +const static uint64_t SH_FLD_RANGE_LEN = 13801; // 1 +const static uint64_t SH_FLD_RANK = 13802; // 8 +const static uint64_t SH_FLD_RANK_LEN = 13803; // 8 +const static uint64_t SH_FLD_RANK_OVERRIDE = 13804; // 8 +const static uint64_t SH_FLD_RANK_OVERRIDE_VALUE = 13805; // 8 +const static uint64_t SH_FLD_RANK_OVERRIDE_VALUE_LEN = 13806; // 8 +const static uint64_t SH_FLD_RANK_PAIR = 13807; // 8 +const static uint64_t SH_FLD_RANK_PAIR_LEN = 13808; // 8 +const static uint64_t SH_FLD_RANK_SM_1HOT = 13809; // 8 +const static uint64_t SH_FLD_RATE = 13810; // 14 +const static uint64_t SH_FLD_RATE_LEN = 13811; // 14 +const static uint64_t SH_FLD_RATIO = 13812; // 2 +const static uint64_t SH_FLD_RATIO_LEN = 13813; // 2 +const static uint64_t SH_FLD_RC = 13814; // 8 +const static uint64_t SH_FLD_RCDAT_RD_PARITY_ERR = 13815; // 12 +const static uint64_t SH_FLD_RCD_PARITY_ERROR = 13816; // 16 +const static uint64_t SH_FLD_RCE_COUNT = 13817; // 2 +const static uint64_t SH_FLD_RCE_COUNT_LEN = 13818; // 2 +const static uint64_t SH_FLD_RCE_ETE_ATTN = 13819; // 2 +const static uint64_t SH_FLD_RCMD0_ADDR_PARITY_ERROR = 13820; // 2 +const static uint64_t SH_FLD_RCMD0_ADDR_PERR = 13821; // 1 +const static uint64_t SH_FLD_RCMD0_TTAG_PERR = 13822; // 1 +const static uint64_t SH_FLD_RCMD1_ADDR_PARITY_ERROR = 13823; // 2 +const static uint64_t SH_FLD_RCMD1_ADDR_PERR = 13824; // 1 +const static uint64_t SH_FLD_RCMD1_TTAG_PERR = 13825; // 1 +const static uint64_t SH_FLD_RCMD2_ADDR_PARITY_ERROR = 13826; // 2 +const static uint64_t SH_FLD_RCMD2_ADDR_PERR = 13827; // 1 +const static uint64_t SH_FLD_RCMD2_TTAG_PERR = 13828; // 1 +const static uint64_t SH_FLD_RCMD3_ADDR_PARITY_ERROR = 13829; // 2 +const static uint64_t SH_FLD_RCMD3_ADDR_PERR = 13830; // 1 +const static uint64_t SH_FLD_RCMD3_TTAG_PERR = 13831; // 1 +const static uint64_t SH_FLD_RCMD_ERR_INJ = 13832; // 8 +const static uint64_t SH_FLD_RCTRL_CONFIG = 13833; // 8 +const static uint64_t SH_FLD_RCTRL_CONFIG_LEN = 13834; // 8 +const static uint64_t SH_FLD_RCVD_POISONED_CIST_DATA = 13835; // 1 +const static uint64_t SH_FLD_RCV_BRDCST_GROUP = 13836; // 1 +const static uint64_t SH_FLD_RCV_BRDCST_GROUP_LEN = 13837; // 1 +const static uint64_t SH_FLD_RCV_CAPTURE = 13838; // 1 +const static uint64_t SH_FLD_RCV_CAPTURE_LEN = 13839; // 1 +const static uint64_t SH_FLD_RCV_CHIPID = 13840; // 1 +const static uint64_t SH_FLD_RCV_CHIPID_LEN = 13841; // 1 +const static uint64_t SH_FLD_RCV_CREDIT_OVERFLOW_ENA = 13842; // 6 +const static uint64_t SH_FLD_RCV_DATATO_DIV = 13843; // 1 +const static uint64_t SH_FLD_RCV_DATATO_DIV_LEN = 13844; // 1 +const static uint64_t SH_FLD_RCV_ERROR = 13845; // 1 +const static uint64_t SH_FLD_RCV_GROUPID = 13846; // 1 +const static uint64_t SH_FLD_RCV_GROUPID_LEN = 13847; // 1 +const static uint64_t SH_FLD_RCV_IN_PROGRESS = 13848; // 1 +const static uint64_t SH_FLD_RCV_PB_OP_HANG_ERR = 13849; // 1 +const static uint64_t SH_FLD_RCV_RESERVATION_SET = 13850; // 1 +const static uint64_t SH_FLD_RCV_RESET = 13851; // 1 +const static uint64_t SH_FLD_RCV_TOD_STATE = 13852; // 1 +const static uint64_t SH_FLD_RCV_TOD_STATE_LEN = 13853; // 1 +const static uint64_t SH_FLD_RCV_TTAG_PARITY_ERR = 13854; // 1 +const static uint64_t SH_FLD_RCV_WRITE_IN_PROGRESS = 13855; // 1 +const static uint64_t SH_FLD_RC_ADDR_PAR = 13856; // 1 +const static uint64_t SH_FLD_RC_ENABLE_AUTO_RECAL = 13857; // 2 +const static uint64_t SH_FLD_RC_ENABLE_BER_TEST = 13858; // 4 +const static uint64_t SH_FLD_RC_ENABLE_CM_COARSE_CAL = 13859; // 6 +const static uint64_t SH_FLD_RC_ENABLE_CM_FINE_CAL = 13860; // 6 +const static uint64_t SH_FLD_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL = 13861; // 6 +const static uint64_t SH_FLD_RC_ENABLE_CTLE_2ND_LATCH_OFFSET_CAL = 13862; // 6 +const static uint64_t SH_FLD_RC_ENABLE_CTLE_COARSE_CAL = 13863; // 6 +const static uint64_t SH_FLD_RC_ENABLE_CTLE_EDGE_OFFSET_CAL = 13864; // 2 +const static uint64_t SH_FLD_RC_ENABLE_CTLE_EDGE_TRACK_ONLY = 13865; // 4 +const static uint64_t SH_FLD_RC_ENABLE_DAC_H1_CAL = 13866; // 6 +const static uint64_t SH_FLD_RC_ENABLE_DAC_H1_TO_A_CAL = 13867; // 4 +const static uint64_t SH_FLD_RC_ENABLE_DDC = 13868; // 6 +const static uint64_t SH_FLD_RC_ENABLE_DFE_H1_CAL = 13869; // 6 +const static uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_CAL = 13870; // 4 +const static uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP = 13871; // 4 +const static uint64_t SH_FLD_RC_ENABLE_DFE_H2_H12_SUBSTEP_LEN = 13872; // 4 +const static uint64_t SH_FLD_RC_ENABLE_DFE_VOLTAGE_MODE = 13873; // 4 +const static uint64_t SH_FLD_RC_ENABLE_H1AP_TWEAK = 13874; // 6 +const static uint64_t SH_FLD_RC_ENABLE_INTEG_LATCH_OFFSET_CAL = 13875; // 6 +const static uint64_t SH_FLD_RC_ENABLE_RESULT_CHECK = 13876; // 4 +const static uint64_t SH_FLD_RC_ENABLE_VGA_AMAX_MODE = 13877; // 6 +const static uint64_t SH_FLD_RC_ENABLE_VGA_CAL = 13878; // 6 +const static uint64_t SH_FLD_RC_ENABLE_VGA_EDGE_OFFSET_CAL = 13879; // 2 +const static uint64_t SH_FLD_RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV = 13880; // 12 +const static uint64_t SH_FLD_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR = 13881; // 12 +const static uint64_t SH_FLD_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR_FOR_HYP = 13882; // 12 +const static uint64_t SH_FLD_RC_MASK = 13883; // 8 +const static uint64_t SH_FLD_RC_POWBUS_DATA_CE_ERR_FROM_F2CHK = 13884; // 12 +const static uint64_t SH_FLD_RC_POWBUS_DATA_SUE_ERR_FROM_F2CHK = 13885; // 12 +const static uint64_t SH_FLD_RC_POWBUS_DATA_UE_ERR_FROM_F2CHK = 13886; // 12 +const static uint64_t SH_FLD_RC_POWERBUS_DATA_TIMEOUT = 13887; // 12 +const static uint64_t SH_FLD_RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV = 13888; // 12 +const static uint64_t SH_FLD_RC_STORE_RECEIVED_PB_CRESP_ADR_ERR = 13889; // 12 +const static uint64_t SH_FLD_RC_TTAG_PAR = 13890; // 1 +const static uint64_t SH_FLD_RDADDR_ARB_BAD_HAND = 13891; // 2 +const static uint64_t SH_FLD_RDATA = 13892; // 1 +const static uint64_t SH_FLD_RDATA_LEN = 13893; // 1 +const static uint64_t SH_FLD_RDCLK_ALIGN = 13894; // 8 +const static uint64_t SH_FLD_RDCMP = 13895; // 2 +const static uint64_t SH_FLD_RDCMP_LEN = 13896; // 2 +const static uint64_t SH_FLD_RDIV = 13897; // 14 +const static uint64_t SH_FLD_RDIV_LEN = 13898; // 10 +const static uint64_t SH_FLD_RDQ_ABORT_OP = 13899; // 1 +const static uint64_t SH_FLD_RDQ_ABORT_TRM = 13900; // 1 +const static uint64_t SH_FLD_RDQ_BAD_CRESP = 13901; // 1 +const static uint64_t SH_FLD_RDQ_DATA_HANG = 13902; // 1 +const static uint64_t SH_FLD_RDQ_FSM_PERR = 13903; // 1 +const static uint64_t SH_FLD_RDQ_OP_HANG = 13904; // 1 +const static uint64_t SH_FLD_RDQ_OVERFLOW = 13905; // 1 +const static uint64_t SH_FLD_RDWR_ACCESS_EN = 13906; // 2 +const static uint64_t SH_FLD_RDWR_ADDR = 13907; // 2 +const static uint64_t SH_FLD_RDWR_ADDR_LEN = 13908; // 2 +const static uint64_t SH_FLD_RDWR_OP_BUSY = 13909; // 1 +const static uint64_t SH_FLD_RDWR_RDWR_DATA = 13910; // 2 +const static uint64_t SH_FLD_RDWR_RDWR_DATA_LEN = 13911; // 2 +const static uint64_t SH_FLD_RDWR_READ_STATUS = 13912; // 2 +const static uint64_t SH_FLD_RDWR_REQ_PEND = 13913; // 2 +const static uint64_t SH_FLD_RDWR_UPDATE_ERROR = 13914; // 2 +const static uint64_t SH_FLD_RDWR_WRITE_MODE = 13915; // 2 +const static uint64_t SH_FLD_RDWR_WRITE_STATUS = 13916; // 2 +const static uint64_t SH_FLD_RDWR_WR_ENABLE = 13917; // 2 +const static uint64_t SH_FLD_RDX_BUS0_STG0_SEL = 13918; // 1 +const static uint64_t SH_FLD_RDX_BUS0_STG0_SEL_LEN = 13919; // 1 +const static uint64_t SH_FLD_RDX_BUS0_STG1_SEL = 13920; // 1 +const static uint64_t SH_FLD_RDX_BUS0_STG2_SEL = 13921; // 1 +const static uint64_t SH_FLD_RDX_BUS1_STG0_SEL = 13922; // 1 +const static uint64_t SH_FLD_RDX_BUS1_STG0_SEL_LEN = 13923; // 1 +const static uint64_t SH_FLD_RDX_BUS1_STG1_SEL = 13924; // 1 +const static uint64_t SH_FLD_RDX_BUS1_STG2_SEL = 13925; // 1 +const static uint64_t SH_FLD_RD_ADDR_0_7 = 13926; // 1 +const static uint64_t SH_FLD_RD_ADDR_0_7_LEN = 13927; // 1 +const static uint64_t SH_FLD_RD_ARE_ERRORS = 13928; // 9 +const static uint64_t SH_FLD_RD_ARE_ERRORS_MASK = 13929; // 9 +const static uint64_t SH_FLD_RD_CNTL = 13930; // 8 +const static uint64_t SH_FLD_RD_CNTL_MASK = 13931; // 8 +const static uint64_t SH_FLD_RD_DATA_COUNT = 13932; // 1 +const static uint64_t SH_FLD_RD_DATA_COUNT_LEN = 13933; // 1 +const static uint64_t SH_FLD_RD_DATA_PARITY_ERROR = 13934; // 3 +const static uint64_t SH_FLD_RD_ECC_CE = 13935; // 1 +const static uint64_t SH_FLD_RD_ECC_UE = 13936; // 1 +const static uint64_t SH_FLD_RD_GO_M_QOS = 13937; // 2 +const static uint64_t SH_FLD_RD_MACHINE_HANG = 13938; // 12 +const static uint64_t SH_FLD_RD_RST_INTRPT_FACES = 13939; // 1 +const static uint64_t SH_FLD_RD_RST_INTRPT_PIB = 13940; // 1 +const static uint64_t SH_FLD_RD_SCOPE = 13941; // 24 +const static uint64_t SH_FLD_RD_SCOPE_LEN = 13942; // 24 +const static uint64_t SH_FLD_RD_SLVNUM = 13943; // 6 +const static uint64_t SH_FLD_RD_SLVNUM_LEN = 13944; // 6 +const static uint64_t SH_FLD_READ_ASYNC_INTERFACE_PARITY_ERROR = 13945; // 8 +const static uint64_t SH_FLD_READ_ASYNC_INTERFACE_SEQUENCE_ERROR = 13946; // 8 +const static uint64_t SH_FLD_READ_BUFFER_OVERFLOW_ERROR = 13947; // 8 +const static uint64_t SH_FLD_READ_COMPARE_REQUIRED = 13948; // 64 +const static uint64_t SH_FLD_READ_COMPLETE = 13949; // 1 +const static uint64_t SH_FLD_READ_CONTINUE_0 = 13950; // 2 +const static uint64_t SH_FLD_READ_CONTINUE_1 = 13951; // 1 +const static uint64_t SH_FLD_READ_CONTINUE_2 = 13952; // 1 +const static uint64_t SH_FLD_READ_CONTINUE_3 = 13953; // 1 +const static uint64_t SH_FLD_READ_CONTROL_OVERFLOW_ERROR = 13954; // 8 +const static uint64_t SH_FLD_READ_COUNT = 13955; // 8 +const static uint64_t SH_FLD_READ_COUNT_LEN = 13956; // 8 +const static uint64_t SH_FLD_READ_CRD_POOL = 13957; // 1 +const static uint64_t SH_FLD_READ_CRD_POOL_LEN = 13958; // 1 +const static uint64_t SH_FLD_READ_CTR = 13959; // 8 +const static uint64_t SH_FLD_READ_DEBUG_SELECT = 13960; // 8 +const static uint64_t SH_FLD_READ_DEBUG_SELECT_LEN = 13961; // 8 +const static uint64_t SH_FLD_READ_ECC_CONTROL_PARITY_ERROR = 13962; // 8 +const static uint64_t SH_FLD_READ_ECC_DATAPATH_PARITY_ERROR = 13963; // 8 +const static uint64_t SH_FLD_READ_ECC_ECCPIPE_PARITY_ERROR = 13964; // 8 +const static uint64_t SH_FLD_READ_ENABLE = 13965; // 129 +const static uint64_t SH_FLD_READ_EPSILON_MODE = 13966; // 2 +const static uint64_t SH_FLD_READ_EPSILON_TIER0 = 13967; // 2 +const static uint64_t SH_FLD_READ_EPSILON_TIER0_LEN = 13968; // 2 +const static uint64_t SH_FLD_READ_EPSILON_TIER1 = 13969; // 2 +const static uint64_t SH_FLD_READ_EPSILON_TIER1_LEN = 13970; // 2 +const static uint64_t SH_FLD_READ_EPSILON_TIER2 = 13971; // 2 +const static uint64_t SH_FLD_READ_EPSILON_TIER2_LEN = 13972; // 2 +const static uint64_t SH_FLD_READ_ERR_INJECT0 = 13973; // 8 +const static uint64_t SH_FLD_READ_ERR_INJECT0_LEN = 13974; // 8 +const static uint64_t SH_FLD_READ_INVALID_FACES = 13975; // 1 +const static uint64_t SH_FLD_READ_INVALID_PIB = 13976; // 1 +const static uint64_t SH_FLD_READ_LATENCY_OFFSET = 13977; // 8 +const static uint64_t SH_FLD_READ_LATENCY_OFFSET_LEN = 13978; // 8 +const static uint64_t SH_FLD_READ_NOT_WRITE_0 = 13979; // 2 +const static uint64_t SH_FLD_READ_NOT_WRITE_1 = 13980; // 1 +const static uint64_t SH_FLD_READ_NOT_WRITE_2 = 13981; // 1 +const static uint64_t SH_FLD_READ_NOT_WRITE_3 = 13982; // 1 +const static uint64_t SH_FLD_READ_NVLD = 13983; // 1 +const static uint64_t SH_FLD_READ_OR_WRITE_DATA = 13984; // 64 +const static uint64_t SH_FLD_READ_OR_WRITE_DATA_LEN = 13985; // 64 +const static uint64_t SH_FLD_READ_PAR_NOT_SEQ = 13986; // 8 +const static uint64_t SH_FLD_READ_POOL = 13987; // 1 +const static uint64_t SH_FLD_READ_POOL_LEN = 13988; // 1 +const static uint64_t SH_FLD_READ_PREFETCH_CTL = 13989; // 4 +const static uint64_t SH_FLD_READ_PREFETCH_CTL_LEN = 13990; // 4 +const static uint64_t SH_FLD_READ_RAMP_PERF_TRESHOLD = 13991; // 4 +const static uint64_t SH_FLD_READ_RAMP_PERF_TRESHOLD_LEN = 13992; // 4 +const static uint64_t SH_FLD_READ_RESPONSE_DELAY_ENABLE = 13993; // 2 +const static uint64_t SH_FLD_READ_RST_INTERRUPT_FACES = 13994; // 1 +const static uint64_t SH_FLD_READ_RST_INTERRUPT_PIB = 13995; // 1 +const static uint64_t SH_FLD_READ_SPECULATION_DISABLE_THRESHOLD = 13996; // 4 +const static uint64_t SH_FLD_READ_SPECULATION_DISABLE_THRESHOLD_LEN = 13997; // 4 +const static uint64_t SH_FLD_READ_TTYPE = 13998; // 4 +const static uint64_t SH_FLD_RECAL_ABORT = 13999; // 48 +const static uint64_t SH_FLD_RECAL_ABORT_DL_MASK = 14000; // 2 +const static uint64_t SH_FLD_RECAL_DONE_DL_MASK = 14001; // 2 +const static uint64_t SH_FLD_RECAL_ERROR = 14002; // 8 +const static uint64_t SH_FLD_RECAL_MAX_SPARES_EXCEEDED = 14003; // 8 +const static uint64_t SH_FLD_RECAL_REQ = 14004; // 48 +const static uint64_t SH_FLD_RECAL_REQ_DL_MASK = 14005; // 2 +const static uint64_t SH_FLD_RECAL_SPARE_DEPLOYED = 14006; // 8 +const static uint64_t SH_FLD_RECEIVED = 14007; // 1 +const static uint64_t SH_FLD_RECEIVED_ERROR = 14008; // 1 +const static uint64_t SH_FLD_RECEIVER_MODE = 14009; // 3 +const static uint64_t SH_FLD_RECEIVER_MODE_LEN = 14010; // 3 +const static uint64_t SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER = 14011; // 1 +const static uint64_t SH_FLD_RECEIVE_ACKNOWLEDGE_REGISTER_LEN = 14012; // 1 +const static uint64_t SH_FLD_RECOVERABLE_ERROR = 14013; // 2 +const static uint64_t SH_FLD_RECOVERY_BLK = 14014; // 24 +const static uint64_t SH_FLD_RECOVERY_BLK_EXTEND = 14015; // 24 +const static uint64_t SH_FLD_RECOVERY_FAILED = 14016; // 6 +const static uint64_t SH_FLD_RECOVERY_HANG_DETECTED = 14017; // 2 +const static uint64_t SH_FLD_RECR_PE = 14018; // 8 +const static uint64_t SH_FLD_REC_LIMIT = 14019; // 24 +const static uint64_t SH_FLD_REC_LIMIT_LEN = 14020; // 24 +const static uint64_t SH_FLD_REC_PB_SM_ERROR_ERR = 14021; // 2 +const static uint64_t SH_FLD_REC_SM_ERROR_ERR = 14022; // 2 +const static uint64_t SH_FLD_REC_UPDATE_ERROR = 14023; // 2 +const static uint64_t SH_FLD_REDIS_PRIORITY = 14024; // 1 +const static uint64_t SH_FLD_REDIS_PRIORITY_LEN = 14025; // 1 +const static uint64_t SH_FLD_REDIS_RSD = 14026; // 1 +const static uint64_t SH_FLD_REDIS_RSD_LEN = 14027; // 1 +const static uint64_t SH_FLD_REFCLKSEL = 14028; // 4 +const static uint64_t SH_FLD_REFCLK_0_TERM_DIS_DC = 14029; // 3 +const static uint64_t SH_FLD_REFCLK_1_TERM_DIS_DC = 14030; // 3 +const static uint64_t SH_FLD_REFCLK_CLKMUX0_SEL = 14031; // 43 +const static uint64_t SH_FLD_REFCLK_CLKMUX1_SEL = 14032; // 43 +const static uint64_t SH_FLD_REFISINK = 14033; // 3 +const static uint64_t SH_FLD_REFISINK_LEN = 14034; // 3 +const static uint64_t SH_FLD_REFISRC = 14035; // 3 +const static uint64_t SH_FLD_REFISRC_LEN = 14036; // 3 +const static uint64_t SH_FLD_REFRESH_ALL_RANKS = 14037; // 8 +const static uint64_t SH_FLD_REFRESH_BLOCK_CONFIG = 14038; // 8 +const static uint64_t SH_FLD_REFRESH_BLOCK_CONFIG_LEN = 14039; // 8 +const static uint64_t SH_FLD_REFRESH_CONTROL = 14040; // 8 +const static uint64_t SH_FLD_REFRESH_CONTROL_LEN = 14041; // 8 +const static uint64_t SH_FLD_REFRESH_COUNT = 14042; // 8 +const static uint64_t SH_FLD_REFRESH_COUNT_LEN = 14043; // 8 +const static uint64_t SH_FLD_REFRESH_INTERVAL = 14044; // 8 +const static uint64_t SH_FLD_REFRESH_INTERVAL_LEN = 14045; // 8 +const static uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_EN = 14046; // 2 +const static uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL = 14047; // 2 +const static uint64_t SH_FLD_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN = 14048; // 2 +const static uint64_t SH_FLD_REFRESH_OVERRUN = 14049; // 16 +const static uint64_t SH_FLD_REFVREG = 14050; // 3 +const static uint64_t SH_FLD_REFVREG_LEN = 14051; // 3 +const static uint64_t SH_FLD_REG = 14052; // 19 +const static uint64_t SH_FLD_REGF = 14053; // 43 +const static uint64_t SH_FLD_REGION = 14054; // 72 +const static uint64_t SH_FLD_REGION_LEN = 14055; // 72 +const static uint64_t SH_FLD_REGISTER = 14056; // 3 +const static uint64_t SH_FLD_REGISTER_ARRAY_PE = 14057; // 9 +const static uint64_t SH_FLD_REGISTER_ARRAY_PE_MASK = 14058; // 9 +const static uint64_t SH_FLD_REGISTER_LEN = 14059; // 3 +const static uint64_t SH_FLD_REGISTER_PE = 14060; // 4 +const static uint64_t SH_FLD_REGISTER_VALID = 14061; // 4 +const static uint64_t SH_FLD_REGS = 14062; // 1 +const static uint64_t SH_FLD_REGSEL = 14063; // 4 +const static uint64_t SH_FLD_REGSEL_LEN = 14064; // 4 +const static uint64_t SH_FLD_REGS_LEN = 14065; // 1 +const static uint64_t SH_FLD_REGS_ORDERING_TAG = 14066; // 1 +const static uint64_t SH_FLD_REGS_ORDERING_TAG_LEN = 14067; // 1 +const static uint64_t SH_FLD_REG_ADDR_LENGTH = 14068; // 1 +const static uint64_t SH_FLD_REG_ADDR_LENGTH_LEN = 14069; // 1 +const static uint64_t SH_FLD_REG_ADDR_LEN_0 = 14070; // 1 +const static uint64_t SH_FLD_REG_ADDR_LEN_0_LEN = 14071; // 1 +const static uint64_t SH_FLD_REG_ADDR_LEN_1 = 14072; // 1 +const static uint64_t SH_FLD_REG_ADDR_LEN_1_LEN = 14073; // 1 +const static uint64_t SH_FLD_REG_ADDR_LEN_2 = 14074; // 1 +const static uint64_t SH_FLD_REG_ADDR_LEN_2_LEN = 14075; // 1 +const static uint64_t SH_FLD_REG_ADDR_LEN_3 = 14076; // 1 +const static uint64_t SH_FLD_REG_ADDR_LEN_3_LEN = 14077; // 1 +const static uint64_t SH_FLD_REG_ENABLE = 14078; // 1 +const static uint64_t SH_FLD_REG_FIFO_SIZE_EQ_1 = 14079; // 1 +const static uint64_t SH_FLD_REG_LEN = 14080; // 19 +const static uint64_t SH_FLD_REG_UNUSED = 14081; // 1 +const static uint64_t SH_FLD_REG_UNUSED_LEN = 14082; // 1 +const static uint64_t SH_FLD_REG_WAKEUP_C0 = 14083; // 24 +const static uint64_t SH_FLD_REG_WAKEUP_C1 = 14084; // 24 +const static uint64_t SH_FLD_REINIT_CREDITS = 14085; // 1 +const static uint64_t SH_FLD_REJECTED_PASTE_CMD = 14086; // 2 +const static uint64_t SH_FLD_RELAXED_CMD_ARMWF_ADD = 14087; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMWF_AND = 14088; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_E = 14089; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S = 14090; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U = 14091; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S = 14092; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U = 14093; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMWF_CAS_U = 14094; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMWF_OR = 14095; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMWF_XOR = 14096; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMW_ADD = 14097; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMW_AND = 14098; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S = 14099; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U = 14100; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S = 14101; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U = 14102; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMW_OR = 14103; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_ARMW_XOR = 14104; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_CL_DMA_INJ = 14105; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_CL_DMA_W = 14106; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_CL_DMA_W_HP = 14107; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_CL_RD_NC_F0 = 14108; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_DMA_PR_W = 14109; // 12 +const static uint64_t SH_FLD_RELAXED_CMD_PR_DMA_INJ = 14110; // 12 +const static uint64_t SH_FLD_RELAXED_RESERVED0 = 14111; // 12 +const static uint64_t SH_FLD_RELAXED_RESERVED0_LEN = 14112; // 12 +const static uint64_t SH_FLD_RELAXED_RESERVED1 = 14113; // 12 +const static uint64_t SH_FLD_RELAXED_RESERVED1_LEN = 14114; // 12 +const static uint64_t SH_FLD_RELAXED_RESERVED2 = 14115; // 12 +const static uint64_t SH_FLD_RELAXED_RESERVED2_LEN = 14116; // 12 +const static uint64_t SH_FLD_RELAXED_RESERVED3 = 14117; // 12 +const static uint64_t SH_FLD_RELAXED_RESERVED3_LEN = 14118; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE0_MASK = 14119; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE0_MASK_LEN = 14120; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE0_MATCH = 14121; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE0_MATCH_LEN = 14122; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE0_RDENA = 14123; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE0_WRENA = 14124; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE1_MASK = 14125; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE1_MASK_LEN = 14126; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE1_MATCH = 14127; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE1_MATCH_LEN = 14128; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE1_RDENA = 14129; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE1_WRENA = 14130; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE2_MASK = 14131; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE2_MASK_LEN = 14132; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE2_MATCH = 14133; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE2_MATCH_LEN = 14134; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE2_RDENA = 14135; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE2_WRENA = 14136; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE3_MASK = 14137; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE3_MASK_LEN = 14138; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE3_MATCH = 14139; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE3_MATCH_LEN = 14140; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE3_RDENA = 14141; // 12 +const static uint64_t SH_FLD_RELAXED_SOURCE3_WRENA = 14142; // 12 +const static uint64_t SH_FLD_RELAXED_WR = 14143; // 1 +const static uint64_t SH_FLD_REL_ASYNC_PARITY_ERROR = 14144; // 8 +const static uint64_t SH_FLD_REL_ASYNC_SEQUENCE_ERROR = 14145; // 8 +const static uint64_t SH_FLD_REL_MERGE_ASYNC_PARITY_ERROR = 14146; // 8 +const static uint64_t SH_FLD_REL_MERGE_ASYNC_SEQUENCE_ERROR = 14147; // 8 +const static uint64_t SH_FLD_REMAINING_WORDS = 14148; // 1 +const static uint64_t SH_FLD_REMAINING_WORDS_LEN = 14149; // 1 +const static uint64_t SH_FLD_REMAP_DEST = 14150; // 1 +const static uint64_t SH_FLD_REMAP_DEST_LEN = 14151; // 1 +const static uint64_t SH_FLD_REMAP_SOURCE = 14152; // 1 +const static uint64_t SH_FLD_REMAP_SOURCE_LEN = 14153; // 1 +const static uint64_t SH_FLD_REMOTE_NODAL_EPSILON = 14154; // 8 +const static uint64_t SH_FLD_REMOTE_NODAL_EPSILON_LEN = 14155; // 8 +const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION = 14156; // 1 +const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR = 14157; // 1 +const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_FACTOR_LEN = 14158; // 1 +const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_CPS_DEVIATION_LEN = 14159; // 1 +const static uint64_t SH_FLD_REMOTE_SYNC_CHECK_M_CPS_DISABLE = 14160; // 1 +const static uint64_t SH_FLD_REMOTE_SYNC_DISABLE = 14161; // 1 +const static uint64_t SH_FLD_REMOTE_SYNC_ERROR_DISABLE = 14162; // 1 +const static uint64_t SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX = 14163; // 1 +const static uint64_t SH_FLD_REMOTE_SYNC_MISS_COUNT_MAX_LEN = 14164; // 1 +const static uint64_t SH_FLD_REM_0 = 14165; // 6 +const static uint64_t SH_FLD_REM_0_LEN = 14166; // 6 +const static uint64_t SH_FLD_REM_1 = 14167; // 6 +const static uint64_t SH_FLD_REM_1_LEN = 14168; // 6 +const static uint64_t SH_FLD_REM_2 = 14169; // 6 +const static uint64_t SH_FLD_REM_2_LEN = 14170; // 6 +const static uint64_t SH_FLD_REM_3 = 14171; // 6 +const static uint64_t SH_FLD_REM_3_LEN = 14172; // 6 +const static uint64_t SH_FLD_REPAIR_DONE = 14173; // 4 +const static uint64_t SH_FLD_REPAIR_FAILED = 14174; // 4 +const static uint64_t SH_FLD_REPEAT_CMD_CNT = 14175; // 64 +const static uint64_t SH_FLD_REPEAT_CMD_CNT_LEN = 14176; // 64 +const static uint64_t SH_FLD_REPR = 14177; // 43 +const static uint64_t SH_FLD_REPTEST_ENABLE = 14178; // 1 +const static uint64_t SH_FLD_REPTEST_MATCH_TH = 14179; // 1 +const static uint64_t SH_FLD_REPTEST_MATCH_TH_LEN = 14180; // 1 +const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0 = 14181; // 1 +const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0_LEN = 14182; // 1 +const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1 = 14183; // 1 +const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN = 14184; // 1 +const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_TH = 14185; // 1 +const static uint64_t SH_FLD_REPTEST_SOFT_FAIL_TH_LEN = 14186; // 1 +const static uint64_t SH_FLD_REQ = 14187; // 43 +const static uint64_t SH_FLD_REQUEST = 14188; // 1 +const static uint64_t SH_FLD_REQUEST_LEN = 14189; // 1 +const static uint64_t SH_FLD_REQ_INTR_PAYLOAD = 14190; // 30 +const static uint64_t SH_FLD_REQ_INTR_PAYLOAD_LEN = 14191; // 30 +const static uint64_t SH_FLD_REQ_INTR_TYPE = 14192; // 30 +const static uint64_t SH_FLD_REQ_INTR_TYPE_LEN = 14193; // 30 +const static uint64_t SH_FLD_REQ_RESET_FR_SBE = 14194; // 1 +const static uint64_t SH_FLD_REQ_RESET_FR_SP = 14195; // 1 +const static uint64_t SH_FLD_RESERVATION_EN = 14196; // 1 +const static uint64_t SH_FLD_RESERVED = 14197; // 134 +const static uint64_t SH_FLD_RESERVED0 = 14198; // 9 +const static uint64_t SH_FLD_RESERVED0_LEN = 14199; // 9 +const static uint64_t SH_FLD_RESERVED1 = 14200; // 215 +const static uint64_t SH_FLD_RESERVED17 = 14201; // 4 +const static uint64_t SH_FLD_RESERVED18 = 14202; // 8 +const static uint64_t SH_FLD_RESERVED19 = 14203; // 4 +const static uint64_t SH_FLD_RESERVED19_23 = 14204; // 4 +const static uint64_t SH_FLD_RESERVED19_23_LEN = 14205; // 4 +const static uint64_t SH_FLD_RESERVED1_2 = 14206; // 4 +const static uint64_t SH_FLD_RESERVED1_2_LEN = 14207; // 4 +const static uint64_t SH_FLD_RESERVED1_LEN = 14208; // 176 +const static uint64_t SH_FLD_RESERVED2 = 14209; // 66 +const static uint64_t SH_FLD_RESERVED20 = 14210; // 16 +const static uint64_t SH_FLD_RESERVED21 = 14211; // 4 +const static uint64_t SH_FLD_RESERVED22 = 14212; // 4 +const static uint64_t SH_FLD_RESERVED23 = 14213; // 4 +const static uint64_t SH_FLD_RESERVED24 = 14214; // 4 +const static uint64_t SH_FLD_RESERVED25 = 14215; // 8 +const static uint64_t SH_FLD_RESERVED27 = 14216; // 4 +const static uint64_t SH_FLD_RESERVED28 = 14217; // 4 +const static uint64_t SH_FLD_RESERVED28_31 = 14218; // 6 +const static uint64_t SH_FLD_RESERVED28_31_LEN = 14219; // 6 +const static uint64_t SH_FLD_RESERVED2_LEN = 14220; // 42 +const static uint64_t SH_FLD_RESERVED3 = 14221; // 24 +const static uint64_t SH_FLD_RESERVED3_LEN = 14222; // 24 +const static uint64_t SH_FLD_RESERVED4 = 14223; // 10 +const static uint64_t SH_FLD_RESERVED4_LEN = 14224; // 6 +const static uint64_t SH_FLD_RESERVED515 = 14225; // 4 +const static uint64_t SH_FLD_RESERVED515_LEN = 14226; // 4 +const static uint64_t SH_FLD_RESERVED52_55 = 14227; // 4 +const static uint64_t SH_FLD_RESERVED52_55_LEN = 14228; // 4 +const static uint64_t SH_FLD_RESERVED57_63 = 14229; // 4 +const static uint64_t SH_FLD_RESERVED57_63_LEN = 14230; // 4 +const static uint64_t SH_FLD_RESERVED6 = 14231; // 1 +const static uint64_t SH_FLD_RESERVED63 = 14232; // 4 +const static uint64_t SH_FLD_RESERVED_0 = 14233; // 6 +const static uint64_t SH_FLD_RESERVED_00 = 14234; // 1 +const static uint64_t SH_FLD_RESERVED_02 = 14235; // 1 +const static uint64_t SH_FLD_RESERVED_03 = 14236; // 1 +const static uint64_t SH_FLD_RESERVED_0_1 = 14237; // 24 +const static uint64_t SH_FLD_RESERVED_0_17 = 14238; // 2 +const static uint64_t SH_FLD_RESERVED_0_17_LEN = 14239; // 2 +const static uint64_t SH_FLD_RESERVED_0_19 = 14240; // 6 +const static uint64_t SH_FLD_RESERVED_0_19_LEN = 14241; // 6 +const static uint64_t SH_FLD_RESERVED_0_1_LEN = 14242; // 24 +const static uint64_t SH_FLD_RESERVED_0_20 = 14243; // 5 +const static uint64_t SH_FLD_RESERVED_0_20_LEN = 14244; // 5 +const static uint64_t SH_FLD_RESERVED_0_25 = 14245; // 1 +const static uint64_t SH_FLD_RESERVED_0_25_LEN = 14246; // 1 +const static uint64_t SH_FLD_RESERVED_0_29 = 14247; // 1 +const static uint64_t SH_FLD_RESERVED_0_29_LEN = 14248; // 1 +const static uint64_t SH_FLD_RESERVED_0_3 = 14249; // 1 +const static uint64_t SH_FLD_RESERVED_0_31 = 14250; // 2 +const static uint64_t SH_FLD_RESERVED_0_31_LEN = 14251; // 2 +const static uint64_t SH_FLD_RESERVED_0_32 = 14252; // 1 +const static uint64_t SH_FLD_RESERVED_0_32_LEN = 14253; // 1 +const static uint64_t SH_FLD_RESERVED_0_3_LEN = 14254; // 1 +const static uint64_t SH_FLD_RESERVED_0_7 = 14255; // 24 +const static uint64_t SH_FLD_RESERVED_0_7_LEN = 14256; // 24 +const static uint64_t SH_FLD_RESERVED_1 = 14257; // 12 +const static uint64_t SH_FLD_RESERVED_10 = 14258; // 1 +const static uint64_t SH_FLD_RESERVED_10_11 = 14259; // 31 +const static uint64_t SH_FLD_RESERVED_10_11_LEN = 14260; // 31 +const static uint64_t SH_FLD_RESERVED_10_LEN = 14261; // 1 +const static uint64_t SH_FLD_RESERVED_11 = 14262; // 2 +const static uint64_t SH_FLD_RESERVED_11A = 14263; // 43 +const static uint64_t SH_FLD_RESERVED_11_12 = 14264; // 4 +const static uint64_t SH_FLD_RESERVED_11_12_LEN = 14265; // 4 +const static uint64_t SH_FLD_RESERVED_11_14 = 14266; // 4 +const static uint64_t SH_FLD_RESERVED_11_14_LEN = 14267; // 4 +const static uint64_t SH_FLD_RESERVED_11_LEN = 14268; // 1 +const static uint64_t SH_FLD_RESERVED_12 = 14269; // 3 +const static uint64_t SH_FLD_RESERVED_12_13 = 14270; // 8 +const static uint64_t SH_FLD_RESERVED_12_13_LEN = 14271; // 8 +const static uint64_t SH_FLD_RESERVED_12_15 = 14272; // 25 +const static uint64_t SH_FLD_RESERVED_12_15_LEN = 14273; // 25 +const static uint64_t SH_FLD_RESERVED_12_16 = 14274; // 1 +const static uint64_t SH_FLD_RESERVED_12_16_LEN = 14275; // 1 +const static uint64_t SH_FLD_RESERVED_12_23 = 14276; // 1 +const static uint64_t SH_FLD_RESERVED_12_23_LEN = 14277; // 1 +const static uint64_t SH_FLD_RESERVED_13 = 14278; // 10 +const static uint64_t SH_FLD_RESERVED_13_15 = 14279; // 12 +const static uint64_t SH_FLD_RESERVED_13_15_LEN = 14280; // 12 +const static uint64_t SH_FLD_RESERVED_13_31 = 14281; // 2 +const static uint64_t SH_FLD_RESERVED_13_31_LEN = 14282; // 2 +const static uint64_t SH_FLD_RESERVED_13_34 = 14283; // 2 +const static uint64_t SH_FLD_RESERVED_13_34_LEN = 14284; // 2 +const static uint64_t SH_FLD_RESERVED_13_LEN = 14285; // 1 +const static uint64_t SH_FLD_RESERVED_14 = 14286; // 1 +const static uint64_t SH_FLD_RESERVED_14C = 14287; // 43 +const static uint64_t SH_FLD_RESERVED_14_LEN = 14288; // 1 +const static uint64_t SH_FLD_RESERVED_15 = 14289; // 1 +const static uint64_t SH_FLD_RESERVED_15C = 14290; // 43 +const static uint64_t SH_FLD_RESERVED_16 = 14291; // 8 +const static uint64_t SH_FLD_RESERVED_16_17 = 14292; // 4 +const static uint64_t SH_FLD_RESERVED_16_17_LEN = 14293; // 4 +const static uint64_t SH_FLD_RESERVED_16_18 = 14294; // 30 +const static uint64_t SH_FLD_RESERVED_16_18_LEN = 14295; // 30 +const static uint64_t SH_FLD_RESERVED_16_26 = 14296; // 1 +const static uint64_t SH_FLD_RESERVED_16_26_LEN = 14297; // 1 +const static uint64_t SH_FLD_RESERVED_16_27 = 14298; // 1 +const static uint64_t SH_FLD_RESERVED_16_27_LEN = 14299; // 1 +const static uint64_t SH_FLD_RESERVED_16_LEN = 14300; // 1 +const static uint64_t SH_FLD_RESERVED_17 = 14301; // 3 +const static uint64_t SH_FLD_RESERVED_17_19 = 14302; // 6 +const static uint64_t SH_FLD_RESERVED_17_19_LEN = 14303; // 6 +const static uint64_t SH_FLD_RESERVED_17_LEN = 14304; // 1 +const static uint64_t SH_FLD_RESERVED_18 = 14305; // 1 +const static uint64_t SH_FLD_RESERVED_18A = 14306; // 43 +const static uint64_t SH_FLD_RESERVED_18_19 = 14307; // 1 +const static uint64_t SH_FLD_RESERVED_18_19_LEN = 14308; // 1 +const static uint64_t SH_FLD_RESERVED_18_23 = 14309; // 10 +const static uint64_t SH_FLD_RESERVED_18_23_LEN = 14310; // 10 +const static uint64_t SH_FLD_RESERVED_18_31 = 14311; // 14 +const static uint64_t SH_FLD_RESERVED_18_31_LEN = 14312; // 14 +const static uint64_t SH_FLD_RESERVED_19 = 14313; // 1 +const static uint64_t SH_FLD_RESERVED_19A = 14314; // 43 +const static uint64_t SH_FLD_RESERVED_1_12 = 14315; // 4 +const static uint64_t SH_FLD_RESERVED_1_12_LEN = 14316; // 4 +const static uint64_t SH_FLD_RESERVED_1_2 = 14317; // 55 +const static uint64_t SH_FLD_RESERVED_1_2_LEN = 14318; // 55 +const static uint64_t SH_FLD_RESERVED_1_3 = 14319; // 1 +const static uint64_t SH_FLD_RESERVED_1_3_LEN = 14320; // 1 +const static uint64_t SH_FLD_RESERVED_1_5 = 14321; // 1 +const static uint64_t SH_FLD_RESERVED_1_5_LEN = 14322; // 1 +const static uint64_t SH_FLD_RESERVED_1_7 = 14323; // 3 +const static uint64_t SH_FLD_RESERVED_1_7_LEN = 14324; // 3 +const static uint64_t SH_FLD_RESERVED_2 = 14325; // 3 +const static uint64_t SH_FLD_RESERVED_20 = 14326; // 3 +const static uint64_t SH_FLD_RESERVED_20_21 = 14327; // 1 +const static uint64_t SH_FLD_RESERVED_20_21_LEN = 14328; // 1 +const static uint64_t SH_FLD_RESERVED_20_31 = 14329; // 1 +const static uint64_t SH_FLD_RESERVED_20_31_LEN = 14330; // 1 +const static uint64_t SH_FLD_RESERVED_20_LEN = 14331; // 1 +const static uint64_t SH_FLD_RESERVED_21 = 14332; // 8 +const static uint64_t SH_FLD_RESERVED_21_31 = 14333; // 1 +const static uint64_t SH_FLD_RESERVED_21_31_LEN = 14334; // 1 +const static uint64_t SH_FLD_RESERVED_22C = 14335; // 43 +const static uint64_t SH_FLD_RESERVED_22_31 = 14336; // 1 +const static uint64_t SH_FLD_RESERVED_22_31_LEN = 14337; // 1 +const static uint64_t SH_FLD_RESERVED_23 = 14338; // 4 +const static uint64_t SH_FLD_RESERVED_23C = 14339; // 43 +const static uint64_t SH_FLD_RESERVED_23_26 = 14340; // 8 +const static uint64_t SH_FLD_RESERVED_23_26_LEN = 14341; // 8 +const static uint64_t SH_FLD_RESERVED_23_63 = 14342; // 2 +const static uint64_t SH_FLD_RESERVED_23_63_LEN = 14343; // 2 +const static uint64_t SH_FLD_RESERVED_24 = 14344; // 5 +const static uint64_t SH_FLD_RESERVED_24_25 = 14345; // 6 +const static uint64_t SH_FLD_RESERVED_24_25_LEN = 14346; // 6 +const static uint64_t SH_FLD_RESERVED_24_26 = 14347; // 3 +const static uint64_t SH_FLD_RESERVED_24_26_LEN = 14348; // 3 +const static uint64_t SH_FLD_RESERVED_24_29 = 14349; // 1 +const static uint64_t SH_FLD_RESERVED_24_29_LEN = 14350; // 1 +const static uint64_t SH_FLD_RESERVED_24_31 = 14351; // 1 +const static uint64_t SH_FLD_RESERVED_24_31_LEN = 14352; // 1 +const static uint64_t SH_FLD_RESERVED_24_LEN = 14353; // 1 +const static uint64_t SH_FLD_RESERVED_25 = 14354; // 12 +const static uint64_t SH_FLD_RESERVED_25_26 = 14355; // 3 +const static uint64_t SH_FLD_RESERVED_25_26_LEN = 14356; // 3 +const static uint64_t SH_FLD_RESERVED_25_33 = 14357; // 8 +const static uint64_t SH_FLD_RESERVED_25_33_LEN = 14358; // 8 +const static uint64_t SH_FLD_RESERVED_26_49 = 14359; // 2 +const static uint64_t SH_FLD_RESERVED_26_49_LEN = 14360; // 2 +const static uint64_t SH_FLD_RESERVED_28 = 14361; // 5 +const static uint64_t SH_FLD_RESERVED_28_31 = 14362; // 68 +const static uint64_t SH_FLD_RESERVED_28_31_LEN = 14363; // 68 +const static uint64_t SH_FLD_RESERVED_28_LEN = 14364; // 2 +const static uint64_t SH_FLD_RESERVED_29_31 = 14365; // 6 +const static uint64_t SH_FLD_RESERVED_29_31_LEN = 14366; // 6 +const static uint64_t SH_FLD_RESERVED_2E = 14367; // 43 +const static uint64_t SH_FLD_RESERVED_2_10 = 14368; // 24 +const static uint64_t SH_FLD_RESERVED_2_10_LEN = 14369; // 24 +const static uint64_t SH_FLD_RESERVED_2_3 = 14370; // 4 +const static uint64_t SH_FLD_RESERVED_2_3_LEN = 14371; // 4 +const static uint64_t SH_FLD_RESERVED_2_9 = 14372; // 1 +const static uint64_t SH_FLD_RESERVED_2_9_LEN = 14373; // 1 +const static uint64_t SH_FLD_RESERVED_3 = 14374; // 9 +const static uint64_t SH_FLD_RESERVED_30 = 14375; // 1 +const static uint64_t SH_FLD_RESERVED_30C = 14376; // 43 +const static uint64_t SH_FLD_RESERVED_30_31 = 14377; // 12 +const static uint64_t SH_FLD_RESERVED_30_31_LEN = 14378; // 12 +const static uint64_t SH_FLD_RESERVED_31 = 14379; // 3 +const static uint64_t SH_FLD_RESERVED_31C = 14380; // 43 +const static uint64_t SH_FLD_RESERVED_31_LEN = 14381; // 2 +const static uint64_t SH_FLD_RESERVED_32 = 14382; // 27 +const static uint64_t SH_FLD_RESERVED_32_33 = 14383; // 7 +const static uint64_t SH_FLD_RESERVED_32_33_LEN = 14384; // 7 +const static uint64_t SH_FLD_RESERVED_32_34 = 14385; // 8 +const static uint64_t SH_FLD_RESERVED_32_34_LEN = 14386; // 8 +const static uint64_t SH_FLD_RESERVED_32_35 = 14387; // 3 +const static uint64_t SH_FLD_RESERVED_32_35_LEN = 14388; // 3 +const static uint64_t SH_FLD_RESERVED_32_39 = 14389; // 3 +const static uint64_t SH_FLD_RESERVED_32_39_LEN = 14390; // 3 +const static uint64_t SH_FLD_RESERVED_32_40 = 14391; // 10 +const static uint64_t SH_FLD_RESERVED_32_40_LEN = 14392; // 10 +const static uint64_t SH_FLD_RESERVED_32_43 = 14393; // 1 +const static uint64_t SH_FLD_RESERVED_32_43_LEN = 14394; // 1 +const static uint64_t SH_FLD_RESERVED_32_44 = 14395; // 3 +const static uint64_t SH_FLD_RESERVED_32_44_LEN = 14396; // 3 +const static uint64_t SH_FLD_RESERVED_32_63 = 14397; // 8 +const static uint64_t SH_FLD_RESERVED_32_63_LEN = 14398; // 8 +const static uint64_t SH_FLD_RESERVED_33A = 14399; // 43 +const static uint64_t SH_FLD_RESERVED_33_39 = 14400; // 1 +const static uint64_t SH_FLD_RESERVED_33_39_LEN = 14401; // 1 +const static uint64_t SH_FLD_RESERVED_33_63 = 14402; // 1 +const static uint64_t SH_FLD_RESERVED_33_63_LEN = 14403; // 1 +const static uint64_t SH_FLD_RESERVED_34 = 14404; // 1 +const static uint64_t SH_FLD_RESERVED_34A = 14405; // 43 +const static uint64_t SH_FLD_RESERVED_35 = 14406; // 1 +const static uint64_t SH_FLD_RESERVED_35A = 14407; // 43 +const static uint64_t SH_FLD_RESERVED_36_37 = 14408; // 8 +const static uint64_t SH_FLD_RESERVED_36_37_LEN = 14409; // 8 +const static uint64_t SH_FLD_RESERVED_36_39 = 14410; // 1 +const static uint64_t SH_FLD_RESERVED_36_39_LEN = 14411; // 1 +const static uint64_t SH_FLD_RESERVED_37 = 14412; // 1 +const static uint64_t SH_FLD_RESERVED_37_51 = 14413; // 1 +const static uint64_t SH_FLD_RESERVED_37_51_LEN = 14414; // 1 +const static uint64_t SH_FLD_RESERVED_37_56 = 14415; // 8 +const static uint64_t SH_FLD_RESERVED_37_56_LEN = 14416; // 8 +const static uint64_t SH_FLD_RESERVED_38 = 14417; // 1 +const static uint64_t SH_FLD_RESERVED_38A = 14418; // 43 +const static uint64_t SH_FLD_RESERVED_38_39 = 14419; // 24 +const static uint64_t SH_FLD_RESERVED_38_39_LEN = 14420; // 24 +const static uint64_t SH_FLD_RESERVED_38_41 = 14421; // 2 +const static uint64_t SH_FLD_RESERVED_38_41_LEN = 14422; // 2 +const static uint64_t SH_FLD_RESERVED_38_63 = 14423; // 2 +const static uint64_t SH_FLD_RESERVED_38_63_LEN = 14424; // 2 +const static uint64_t SH_FLD_RESERVED_39 = 14425; // 12 +const static uint64_t SH_FLD_RESERVED_39A = 14426; // 43 +const static uint64_t SH_FLD_RESERVED_39_47 = 14427; // 64 +const static uint64_t SH_FLD_RESERVED_39_47_LEN = 14428; // 64 +const static uint64_t SH_FLD_RESERVED_3E = 14429; // 43 +const static uint64_t SH_FLD_RESERVED_3_9 = 14430; // 1 +const static uint64_t SH_FLD_RESERVED_3_9_LEN = 14431; // 1 +const static uint64_t SH_FLD_RESERVED_4 = 14432; // 18 +const static uint64_t SH_FLD_RESERVED_40 = 14433; // 35 +const static uint64_t SH_FLD_RESERVED_40_41 = 14434; // 9 +const static uint64_t SH_FLD_RESERVED_40_41_LEN = 14435; // 9 +const static uint64_t SH_FLD_RESERVED_40_42 = 14436; // 1 +const static uint64_t SH_FLD_RESERVED_40_42_LEN = 14437; // 1 +const static uint64_t SH_FLD_RESERVED_40_43 = 14438; // 1 +const static uint64_t SH_FLD_RESERVED_40_43_LEN = 14439; // 1 +const static uint64_t SH_FLD_RESERVED_40_47 = 14440; // 2 +const static uint64_t SH_FLD_RESERVED_40_47_LEN = 14441; // 2 +const static uint64_t SH_FLD_RESERVED_41 = 14442; // 2 +const static uint64_t SH_FLD_RESERVED_41_42 = 14443; // 10 +const static uint64_t SH_FLD_RESERVED_41_42_LEN = 14444; // 10 +const static uint64_t SH_FLD_RESERVED_41_43 = 14445; // 1 +const static uint64_t SH_FLD_RESERVED_41_43_LEN = 14446; // 1 +const static uint64_t SH_FLD_RESERVED_41_63 = 14447; // 8 +const static uint64_t SH_FLD_RESERVED_41_63_LEN = 14448; // 8 +const static uint64_t SH_FLD_RESERVED_42 = 14449; // 2 +const static uint64_t SH_FLD_RESERVED_42A = 14450; // 43 +const static uint64_t SH_FLD_RESERVED_42_43 = 14451; // 12 +const static uint64_t SH_FLD_RESERVED_42_43_LEN = 14452; // 12 +const static uint64_t SH_FLD_RESERVED_42_47 = 14453; // 8 +const static uint64_t SH_FLD_RESERVED_42_47_LEN = 14454; // 8 +const static uint64_t SH_FLD_RESERVED_43 = 14455; // 2 +const static uint64_t SH_FLD_RESERVED_43A = 14456; // 43 +const static uint64_t SH_FLD_RESERVED_43C = 14457; // 43 +const static uint64_t SH_FLD_RESERVED_43_44 = 14458; // 2 +const static uint64_t SH_FLD_RESERVED_43_44_LEN = 14459; // 2 +const static uint64_t SH_FLD_RESERVED_44 = 14460; // 1 +const static uint64_t SH_FLD_RESERVED_44_47 = 14461; // 1 +const static uint64_t SH_FLD_RESERVED_44_47_LEN = 14462; // 1 +const static uint64_t SH_FLD_RESERVED_44_51 = 14463; // 1 +const static uint64_t SH_FLD_RESERVED_44_51_LEN = 14464; // 1 +const static uint64_t SH_FLD_RESERVED_45 = 14465; // 1 +const static uint64_t SH_FLD_RESERVED_45_47 = 14466; // 2 +const static uint64_t SH_FLD_RESERVED_45_47_LEN = 14467; // 2 +const static uint64_t SH_FLD_RESERVED_46 = 14468; // 1 +const static uint64_t SH_FLD_RESERVED_47 = 14469; // 2 +const static uint64_t SH_FLD_RESERVED_47_48 = 14470; // 2 +const static uint64_t SH_FLD_RESERVED_47_48_LEN = 14471; // 2 +const static uint64_t SH_FLD_RESERVED_48 = 14472; // 27 +const static uint64_t SH_FLD_RESERVED_48_49 = 14473; // 3 +const static uint64_t SH_FLD_RESERVED_48_49_LEN = 14474; // 3 +const static uint64_t SH_FLD_RESERVED_48_50 = 14475; // 2 +const static uint64_t SH_FLD_RESERVED_48_50_LEN = 14476; // 2 +const static uint64_t SH_FLD_RESERVED_48_63 = 14477; // 10 +const static uint64_t SH_FLD_RESERVED_48_63_LEN = 14478; // 10 +const static uint64_t SH_FLD_RESERVED_49_63 = 14479; // 8 +const static uint64_t SH_FLD_RESERVED_49_63_LEN = 14480; // 8 +const static uint64_t SH_FLD_RESERVED_4_5 = 14481; // 1 +const static uint64_t SH_FLD_RESERVED_4_5_LEN = 14482; // 1 +const static uint64_t SH_FLD_RESERVED_4_7 = 14483; // 32 +const static uint64_t SH_FLD_RESERVED_4_7_LEN = 14484; // 32 +const static uint64_t SH_FLD_RESERVED_4_LEN = 14485; // 1 +const static uint64_t SH_FLD_RESERVED_5 = 14486; // 2 +const static uint64_t SH_FLD_RESERVED_50 = 14487; // 4 +const static uint64_t SH_FLD_RESERVED_50_51 = 14488; // 3 +const static uint64_t SH_FLD_RESERVED_50_51_LEN = 14489; // 3 +const static uint64_t SH_FLD_RESERVED_50_63 = 14490; // 1 +const static uint64_t SH_FLD_RESERVED_50_63_LEN = 14491; // 1 +const static uint64_t SH_FLD_RESERVED_51 = 14492; // 16 +const static uint64_t SH_FLD_RESERVED_51_63 = 14493; // 9 +const static uint64_t SH_FLD_RESERVED_51_63_LEN = 14494; // 9 +const static uint64_t SH_FLD_RESERVED_52 = 14495; // 38 +const static uint64_t SH_FLD_RESERVED_52_55 = 14496; // 64 +const static uint64_t SH_FLD_RESERVED_52_55_LEN = 14497; // 64 +const static uint64_t SH_FLD_RESERVED_52_56 = 14498; // 8 +const static uint64_t SH_FLD_RESERVED_52_56_LEN = 14499; // 8 +const static uint64_t SH_FLD_RESERVED_53_54 = 14500; // 8 +const static uint64_t SH_FLD_RESERVED_53_54_LEN = 14501; // 8 +const static uint64_t SH_FLD_RESERVED_53_58 = 14502; // 2 +const static uint64_t SH_FLD_RESERVED_53_58_LEN = 14503; // 2 +const static uint64_t SH_FLD_RESERVED_53_63 = 14504; // 1 +const static uint64_t SH_FLD_RESERVED_53_63_LEN = 14505; // 1 +const static uint64_t SH_FLD_RESERVED_54_63 = 14506; // 8 +const static uint64_t SH_FLD_RESERVED_54_63_LEN = 14507; // 8 +const static uint64_t SH_FLD_RESERVED_55_62 = 14508; // 8 +const static uint64_t SH_FLD_RESERVED_55_62_LEN = 14509; // 8 +const static uint64_t SH_FLD_RESERVED_55_63 = 14510; // 8 +const static uint64_t SH_FLD_RESERVED_55_63_LEN = 14511; // 8 +const static uint64_t SH_FLD_RESERVED_56 = 14512; // 32 +const static uint64_t SH_FLD_RESERVED_56_57 = 14513; // 2 +const static uint64_t SH_FLD_RESERVED_56_57_LEN = 14514; // 2 +const static uint64_t SH_FLD_RESERVED_56_58 = 14515; // 5 +const static uint64_t SH_FLD_RESERVED_56_58_LEN = 14516; // 5 +const static uint64_t SH_FLD_RESERVED_56_59 = 14517; // 1 +const static uint64_t SH_FLD_RESERVED_56_59_LEN = 14518; // 1 +const static uint64_t SH_FLD_RESERVED_56_63 = 14519; // 18 +const static uint64_t SH_FLD_RESERVED_56_63_LEN = 14520; // 18 +const static uint64_t SH_FLD_RESERVED_57 = 14521; // 24 +const static uint64_t SH_FLD_RESERVED_57_58 = 14522; // 1 +const static uint64_t SH_FLD_RESERVED_57_58_LEN = 14523; // 1 +const static uint64_t SH_FLD_RESERVED_57_59 = 14524; // 8 +const static uint64_t SH_FLD_RESERVED_57_59_LEN = 14525; // 8 +const static uint64_t SH_FLD_RESERVED_57_63 = 14526; // 8 +const static uint64_t SH_FLD_RESERVED_57_63_LEN = 14527; // 8 +const static uint64_t SH_FLD_RESERVED_58 = 14528; // 1 +const static uint64_t SH_FLD_RESERVED_58_59 = 14529; // 1 +const static uint64_t SH_FLD_RESERVED_58_59_LEN = 14530; // 1 +const static uint64_t SH_FLD_RESERVED_58_63 = 14531; // 8 +const static uint64_t SH_FLD_RESERVED_58_63_LEN = 14532; // 8 +const static uint64_t SH_FLD_RESERVED_59 = 14533; // 1 +const static uint64_t SH_FLD_RESERVED_5_15 = 14534; // 1 +const static uint64_t SH_FLD_RESERVED_5_15_LEN = 14535; // 1 +const static uint64_t SH_FLD_RESERVED_5_7 = 14536; // 1 +const static uint64_t SH_FLD_RESERVED_5_7_LEN = 14537; // 1 +const static uint64_t SH_FLD_RESERVED_5_LEN = 14538; // 1 +const static uint64_t SH_FLD_RESERVED_6 = 14539; // 2 +const static uint64_t SH_FLD_RESERVED_60 = 14540; // 24 +const static uint64_t SH_FLD_RESERVED_60_61 = 14541; // 8 +const static uint64_t SH_FLD_RESERVED_60_61_LEN = 14542; // 8 +const static uint64_t SH_FLD_RESERVED_60_63 = 14543; // 17 +const static uint64_t SH_FLD_RESERVED_60_63_LEN = 14544; // 17 +const static uint64_t SH_FLD_RESERVED_61 = 14545; // 24 +const static uint64_t SH_FLD_RESERVED_61_63 = 14546; // 26 +const static uint64_t SH_FLD_RESERVED_61_63_LEN = 14547; // 26 +const static uint64_t SH_FLD_RESERVED_62 = 14548; // 1 +const static uint64_t SH_FLD_RESERVED_62_63 = 14549; // 8 +const static uint64_t SH_FLD_RESERVED_62_63_LEN = 14550; // 8 +const static uint64_t SH_FLD_RESERVED_63 = 14551; // 12 +const static uint64_t SH_FLD_RESERVED_6C = 14552; // 43 +const static uint64_t SH_FLD_RESERVED_6E = 14553; // 43 +const static uint64_t SH_FLD_RESERVED_6_14 = 14554; // 2 +const static uint64_t SH_FLD_RESERVED_6_14_LEN = 14555; // 2 +const static uint64_t SH_FLD_RESERVED_6_7 = 14556; // 27 +const static uint64_t SH_FLD_RESERVED_6_7_LEN = 14557; // 27 +const static uint64_t SH_FLD_RESERVED_6_9 = 14558; // 12 +const static uint64_t SH_FLD_RESERVED_6_9_LEN = 14559; // 12 +const static uint64_t SH_FLD_RESERVED_7 = 14560; // 2 +const static uint64_t SH_FLD_RESERVED_7C = 14561; // 43 +const static uint64_t SH_FLD_RESERVED_7_9 = 14562; // 8 +const static uint64_t SH_FLD_RESERVED_7_9_LEN = 14563; // 8 +const static uint64_t SH_FLD_RESERVED_7_LEN = 14564; // 1 +const static uint64_t SH_FLD_RESERVED_8 = 14565; // 6 +const static uint64_t SH_FLD_RESERVED_8_10 = 14566; // 39 +const static uint64_t SH_FLD_RESERVED_8_10_LEN = 14567; // 39 +const static uint64_t SH_FLD_RESERVED_8_9 = 14568; // 5 +const static uint64_t SH_FLD_RESERVED_8_9_LEN = 14569; // 5 +const static uint64_t SH_FLD_RESERVED_8_LEN = 14570; // 1 +const static uint64_t SH_FLD_RESERVED_9 = 14571; // 27 +const static uint64_t SH_FLD_RESERVED_9_15 = 14572; // 2 +const static uint64_t SH_FLD_RESERVED_9_15_LEN = 14573; // 2 +const static uint64_t SH_FLD_RESERVED_9_26 = 14574; // 1 +const static uint64_t SH_FLD_RESERVED_9_26_LEN = 14575; // 1 +const static uint64_t SH_FLD_RESERVED_9_27 = 14576; // 1 +const static uint64_t SH_FLD_RESERVED_9_27_LEN = 14577; // 1 +const static uint64_t SH_FLD_RESERVED_CERR_24 = 14578; // 8 +const static uint64_t SH_FLD_RESERVED_CERR_25 = 14579; // 8 +const static uint64_t SH_FLD_RESERVED_FOR_ADDRESS = 14580; // 1 +const static uint64_t SH_FLD_RESERVED_FOR_ADDRESS_LEN = 14581; // 1 +const static uint64_t SH_FLD_RESERVED_FOR_CONFIGS = 14582; // 1 +const static uint64_t SH_FLD_RESERVED_FOR_CONFIGS_LEN = 14583; // 1 +const static uint64_t SH_FLD_RESERVED_FOR_ERRS = 14584; // 1 +const static uint64_t SH_FLD_RESERVED_FOR_ERRS_LEN = 14585; // 1 +const static uint64_t SH_FLD_RESERVED_ID_55C = 14586; // 43 +const static uint64_t SH_FLD_RESERVED_ID_61C = 14587; // 43 +const static uint64_t SH_FLD_RESERVED_ID_62C = 14588; // 43 +const static uint64_t SH_FLD_RESERVED_ID_63C = 14589; // 43 +const static uint64_t SH_FLD_RESERVED_LAST_LT = 14590; // 43 +const static uint64_t SH_FLD_RESERVED_LEN = 14591; // 76 +const static uint64_t SH_FLD_RESERVED_LT = 14592; // 43 +const static uint64_t SH_FLD_RESERVED_LT_LEN = 14593; // 43 +const static uint64_t SH_FLD_RESERVED_RING_LOCKING = 14594; // 43 +const static uint64_t SH_FLD_RESERVED_TCDBG_LT = 14595; // 43 +const static uint64_t SH_FLD_RESERVED_TCDBG_LT_LEN = 14596; // 43 +const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_35C = 14597; // 43 +const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_36C = 14598; // 43 +const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_37C = 14599; // 43 +const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_38C = 14600; // 43 +const static uint64_t SH_FLD_RESERVED_TEST_CONTROL_39C = 14601; // 43 +const static uint64_t SH_FLD_RESERVE_11 = 14602; // 2 +const static uint64_t SH_FLD_RESERVE_39_52 = 14603; // 2 +const static uint64_t SH_FLD_RESERVE_39_52_LEN = 14604; // 2 +const static uint64_t SH_FLD_RESERVE_5_15 = 14605; // 2 +const static uint64_t SH_FLD_RESERVE_5_15_LEN = 14606; // 2 +const static uint64_t SH_FLD_RESET = 14607; // 27 +const static uint64_t SH_FLD_RESETMODE = 14608; // 9 +const static uint64_t SH_FLD_RESET_0 = 14609; // 8 +const static uint64_t SH_FLD_RESET_0_7 = 14610; // 1 +const static uint64_t SH_FLD_RESET_0_7_LEN = 14611; // 1 +const static uint64_t SH_FLD_RESET_1 = 14612; // 8 +const static uint64_t SH_FLD_RESET_C2TIMER_ON_C1 = 14613; // 86 +const static uint64_t SH_FLD_RESET_C3_ON_C0 = 14614; // 86 +const static uint64_t SH_FLD_RESET_C3_SELECT = 14615; // 86 +const static uint64_t SH_FLD_RESET_C3_SELECT_LEN = 14616; // 86 +const static uint64_t SH_FLD_RESET_EP = 14617; // 43 +const static uint64_t SH_FLD_RESET_ERROR_LOGS = 14618; // 2 +const static uint64_t SH_FLD_RESET_ERR_RPT = 14619; // 8 +const static uint64_t SH_FLD_RESET_IMPRECISE_QERR = 14620; // 12 +const static uint64_t SH_FLD_RESET_KEEPER = 14621; // 26 +const static uint64_t SH_FLD_RESET_LEN = 14622; // 2 +const static uint64_t SH_FLD_RESET_ON_PARITY = 14623; // 1 +const static uint64_t SH_FLD_RESET_PIB = 14624; // 1 +const static uint64_t SH_FLD_RESET_RECOVER = 14625; // 8 +const static uint64_t SH_FLD_RESET_TOD_STATE = 14626; // 1 +const static uint64_t SH_FLD_RESET_TRAP_CNFG = 14627; // 2 +const static uint64_t SH_FLD_RESET_TRIG_SEL = 14628; // 43 +const static uint64_t SH_FLD_RESET_TRIG_SEL_LEN = 14629; // 43 +const static uint64_t SH_FLD_RESET_ZCAL = 14630; // 8 +const static uint64_t SH_FLD_RESID_FE_LEN_0 = 14631; // 2 +const static uint64_t SH_FLD_RESID_FE_LEN_0_LEN = 14632; // 2 +const static uint64_t SH_FLD_RESID_FE_LEN_1 = 14633; // 1 +const static uint64_t SH_FLD_RESID_FE_LEN_1_LEN = 14634; // 1 +const static uint64_t SH_FLD_RESID_FE_LEN_2 = 14635; // 1 +const static uint64_t SH_FLD_RESID_FE_LEN_2_LEN = 14636; // 1 +const static uint64_t SH_FLD_RESID_FE_LEN_3 = 14637; // 1 +const static uint64_t SH_FLD_RESID_FE_LEN_3_LEN = 14638; // 1 +const static uint64_t SH_FLD_RESPONSE = 14639; // 1 +const static uint64_t SH_FLD_RESP_PKT_RCV = 14640; // 2 +const static uint64_t SH_FLD_RESSEL = 14641; // 4 +const static uint64_t SH_FLD_RESULT = 14642; // 1 +const static uint64_t SH_FLD_RESULT_AVAILABLE = 14643; // 2 +const static uint64_t SH_FLD_RESULT_LEN = 14644; // 1 +const static uint64_t SH_FLD_RESUME_FROM_PAUSE = 14645; // 2 +const static uint64_t SH_FLD_RETRAIN_PERCAL_SW = 14646; // 8 +const static uint64_t SH_FLD_RETRY_LPC_LFSR_SELECT = 14647; // 4 +const static uint64_t SH_FLD_RETRY_LPC_LFSR_SELECT_LEN = 14648; // 4 +const static uint64_t SH_FLD_RETRY_VALUE = 14649; // 1 +const static uint64_t SH_FLD_RETRY_VALUE_LEN = 14650; // 1 +const static uint64_t SH_FLD_RETURNQ_ERR = 14651; // 4 +const static uint64_t SH_FLD_RETURN_GOOD_ON_COMP = 14652; // 24 +const static uint64_t SH_FLD_RG_CERR_BIT10 = 14653; // 1 +const static uint64_t SH_FLD_RG_CERR_BIT11 = 14654; // 1 +const static uint64_t SH_FLD_RG_CERR_BIT4 = 14655; // 1 +const static uint64_t SH_FLD_RG_CERR_BIT5 = 14656; // 1 +const static uint64_t SH_FLD_RG_CERR_BIT6 = 14657; // 1 +const static uint64_t SH_FLD_RG_CERR_BIT7 = 14658; // 1 +const static uint64_t SH_FLD_RG_CERR_BIT8 = 14659; // 1 +const static uint64_t SH_FLD_RG_CERR_BIT9 = 14660; // 1 +const static uint64_t SH_FLD_RG_CERR_RESET = 14661; // 1 +const static uint64_t SH_FLD_RG_CERR_UNUSED_BITS = 14662; // 1 +const static uint64_t SH_FLD_RG_CERR_UNUSED_BITS_LEN = 14663; // 1 +const static uint64_t SH_FLD_RG_ECC_CE_ERROR = 14664; // 2 +const static uint64_t SH_FLD_RG_ECC_SUE_ERROR = 14665; // 2 +const static uint64_t SH_FLD_RG_ECC_UE_ERROR = 14666; // 2 +const static uint64_t SH_FLD_RG_LOGIC_HW_ERROR = 14667; // 2 +const static uint64_t SH_FLD_RG_TRACE_GROUP_SEL_HI = 14668; // 1 +const static uint64_t SH_FLD_RG_TRACE_GROUP_SEL_HI_LEN = 14669; // 1 +const static uint64_t SH_FLD_RG_TRACE_GROUP_SEL_LO = 14670; // 1 +const static uint64_t SH_FLD_RG_TRACE_GROUP_SEL_LO_LEN = 14671; // 1 +const static uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_01 = 14672; // 1 +const static uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_01_LEN = 14673; // 1 +const static uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_23 = 14674; // 1 +const static uint64_t SH_FLD_RG_TRACE_TRIGGER_SEL_23_LEN = 14675; // 1 +const static uint64_t SH_FLD_RIC = 14676; // 8 +const static uint64_t SH_FLD_RIC_LEN = 14677; // 8 +const static uint64_t SH_FLD_RINGS = 14678; // 43 +const static uint64_t SH_FLD_RINGS_LEN = 14679; // 43 +const static uint64_t SH_FLD_RING_LOCKING = 14680; // 43 +const static uint64_t SH_FLD_RMA_BAR = 14681; // 1 +const static uint64_t SH_FLD_RMA_BAR_LEN = 14682; // 1 +const static uint64_t SH_FLD_RMA_BAR_MASK = 14683; // 1 +const static uint64_t SH_FLD_RMA_BAR_MASK_LEN = 14684; // 1 +const static uint64_t SH_FLD_RMT_FIRST_GRPSCAN_ENA = 14685; // 1 +const static uint64_t SH_FLD_RND_BACKOFF_ENABLE = 14686; // 2 +const static uint64_t SH_FLD_RNG0_BIST_FAIL = 14687; // 1 +const static uint64_t SH_FLD_RNG0_FAIL = 14688; // 1 +const static uint64_t SH_FLD_RNG0_INJ_CONTINOUS_ERROR = 14689; // 1 +const static uint64_t SH_FLD_RNG1_BIST_FAIL = 14690; // 1 +const static uint64_t SH_FLD_RNG1_FAIL = 14691; // 1 +const static uint64_t SH_FLD_RNG1_INJ_CONTINOUS_ERROR = 14692; // 1 +const static uint64_t SH_FLD_RNG_CNTRL_LOGIC_ERR = 14693; // 1 +const static uint64_t SH_FLD_RNG_FIRST_FAIL = 14694; // 1 +const static uint64_t SH_FLD_RNG_SECOND_FAIL = 14695; // 1 +const static uint64_t SH_FLD_RNW = 14696; // 15 +const static uint64_t SH_FLD_ROUTE_CHECKSTOP = 14697; // 2 +const static uint64_t SH_FLD_RPT = 14698; // 2 +const static uint64_t SH_FLD_RPT1 = 14699; // 1 +const static uint64_t SH_FLD_RPT1_LEN = 14700; // 1 +const static uint64_t SH_FLD_RPTHANG_SELECT = 14701; // 4 +const static uint64_t SH_FLD_RPTHANG_SELECT_LEN = 14702; // 4 +const static uint64_t SH_FLD_RPT_LEN = 14703; // 2 +const static uint64_t SH_FLD_RRDM_DLY = 14704; // 8 +const static uint64_t SH_FLD_RRDM_DLY_LEN = 14705; // 8 +const static uint64_t SH_FLD_RRN_BYPASS_ENABLE = 14706; // 1 +const static uint64_t SH_FLD_RRN_DATA = 14707; // 1 +const static uint64_t SH_FLD_RRN_DATA_LEN = 14708; // 1 +const static uint64_t SH_FLD_RROP_DLY = 14709; // 8 +const static uint64_t SH_FLD_RROP_DLY_LEN = 14710; // 8 +const static uint64_t SH_FLD_RRQ_CAPACITY_LIMIT = 14711; // 4 +const static uint64_t SH_FLD_RRQ_CAPACITY_LIMIT_LEN = 14712; // 4 +const static uint64_t SH_FLD_RRQ_HANG = 14713; // 8 +const static uint64_t SH_FLD_RRQ_PE = 14714; // 8 +const static uint64_t SH_FLD_RRSBG_DLY = 14715; // 8 +const static uint64_t SH_FLD_RRSBG_DLY_LEN = 14716; // 8 +const static uint64_t SH_FLD_RRSMDR_DLY = 14717; // 8 +const static uint64_t SH_FLD_RRSMDR_DLY_LEN = 14718; // 8 +const static uint64_t SH_FLD_RRSMSR_DLY = 14719; // 8 +const static uint64_t SH_FLD_RRSMSR_DLY_LEN = 14720; // 8 +const static uint64_t SH_FLD_RSB_BUS_LOGIC_ERROR = 14721; // 6 +const static uint64_t SH_FLD_RSB_DBG_FATAL_ERROR = 14722; // 6 +const static uint64_t SH_FLD_RSB_DBG_INF_ERROR = 14723; // 6 +const static uint64_t SH_FLD_RSB_ERR_FATAL_ERROR = 14724; // 6 +const static uint64_t SH_FLD_RSB_ERR_INF_ERROR = 14725; // 6 +const static uint64_t SH_FLD_RSB_FDA_FATAL_ERROR = 14726; // 6 +const static uint64_t SH_FLD_RSB_FDA_INF_ERROR = 14727; // 6 +const static uint64_t SH_FLD_RSB_FDB_FATAL_ERROR = 14728; // 6 +const static uint64_t SH_FLD_RSB_FDB_INF_ERROR = 14729; // 6 +const static uint64_t SH_FLD_RSB_REQUEST_ADDRESS_ERROR = 14730; // 6 +const static uint64_t SH_FLD_RSB_UVI_FATAL_ERROR = 14731; // 6 +const static uint64_t SH_FLD_RSB_UVI_INF_ERROR = 14732; // 6 +const static uint64_t SH_FLD_RSD_AT_MACRO = 14733; // 1 +const static uint64_t SH_FLD_RSD_AT_MACRO_LEN = 14734; // 1 +const static uint64_t SH_FLD_RSD_CRD_AT_MACRO = 14735; // 1 +const static uint64_t SH_FLD_RSD_CRD_AT_MACRO_LEN = 14736; // 1 +const static uint64_t SH_FLD_RSD_CRD_DMA_READ = 14737; // 1 +const static uint64_t SH_FLD_RSD_CRD_DMA_READ_LEN = 14738; // 1 +const static uint64_t SH_FLD_RSD_CRD_DMA_WRITE = 14739; // 1 +const static uint64_t SH_FLD_RSD_CRD_DMA_WRITE_LEN = 14740; // 1 +const static uint64_t SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD = 14741; // 1 +const static uint64_t SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD_LEN = 14742; // 1 +const static uint64_t SH_FLD_RSD_CRD_EQ_POST = 14743; // 1 +const static uint64_t SH_FLD_RSD_CRD_EQ_POST_LEN = 14744; // 1 +const static uint64_t SH_FLD_RSD_CRD_TRIG_FWD_1 = 14745; // 1 +const static uint64_t SH_FLD_RSD_CRD_TRIG_FWD_1_LEN = 14746; // 1 +const static uint64_t SH_FLD_RSD_CRD_TRIG_FWD_2 = 14747; // 1 +const static uint64_t SH_FLD_RSD_CRD_TRIG_FWD_2_LEN = 14748; // 1 +const static uint64_t SH_FLD_RSD_DMA_READ = 14749; // 1 +const static uint64_t SH_FLD_RSD_DMA_READ_LEN = 14750; // 1 +const static uint64_t SH_FLD_RSD_DMA_WRITE = 14751; // 1 +const static uint64_t SH_FLD_RSD_DMA_WRITE_LEN = 14752; // 1 +const static uint64_t SH_FLD_RSD_TCTXT_WRITE = 14753; // 1 +const static uint64_t SH_FLD_RSD_TCTXT_WRITE_LEN = 14754; // 1 +const static uint64_t SH_FLD_RSD_VPC_LD_RMT = 14755; // 1 +const static uint64_t SH_FLD_RSD_VPC_LD_RMT_LEN = 14756; // 1 +const static uint64_t SH_FLD_RSD_VPC_ST_RMT = 14757; // 1 +const static uint64_t SH_FLD_RSD_VPC_ST_RMT_LEN = 14758; // 1 +const static uint64_t SH_FLD_RSD_VPC_ST_RMT_VC = 14759; // 1 +const static uint64_t SH_FLD_RSD_VPC_ST_RMT_VC_LEN = 14760; // 1 +const static uint64_t SH_FLD_RSEL = 14761; // 10 +const static uint64_t SH_FLD_RSEL_LEN = 14762; // 10 +const static uint64_t SH_FLD_RSPOUT_CE_ESR = 14763; // 1 +const static uint64_t SH_FLD_RSPOUT_UE_ESR = 14764; // 1 +const static uint64_t SH_FLD_RSP_AE_ALWAYS = 14765; // 6 +const static uint64_t SH_FLD_RSP_CTL_CRED_SINGLE_ENA = 14766; // 6 +const static uint64_t SH_FLD_RSV17 = 14767; // 2 +const static uint64_t SH_FLD_RSV18 = 14768; // 2 +const static uint64_t SH_FLD_RSV19 = 14769; // 2 +const static uint64_t SH_FLD_RSV26 = 14770; // 2 +const static uint64_t SH_FLD_RSV27 = 14771; // 2 +const static uint64_t SH_FLD_RSV34 = 14772; // 2 +const static uint64_t SH_FLD_RSV35 = 14773; // 2 +const static uint64_t SH_FLD_RSV6 = 14774; // 2 +const static uint64_t SH_FLD_RSV7 = 14775; // 2 +const static uint64_t SH_FLD_RSVD = 14776; // 2 +const static uint64_t SH_FLD_RSVD0 = 14777; // 1 +const static uint64_t SH_FLD_RSVD0_LEN = 14778; // 1 +const static uint64_t SH_FLD_RSVD1 = 14779; // 1 +const static uint64_t SH_FLD_RSVD1_LEN = 14780; // 1 +const static uint64_t SH_FLD_RSVD_35_43 = 14781; // 8 +const static uint64_t SH_FLD_RSVD_35_43_LEN = 14782; // 8 +const static uint64_t SH_FLD_RSVD_LEN = 14783; // 1 +const static uint64_t SH_FLD_RTAGFLUSH_FAILED = 14784; // 2 +const static uint64_t SH_FLD_RTAG_PARITY = 14785; // 1 +const static uint64_t SH_FLD_RTAG_PERR = 14786; // 1 +const static uint64_t SH_FLD_RTIM_THOLD_FORCE = 14787; // 43 +const static uint64_t SH_FLD_RTY_COUNT = 14788; // 2 +const static uint64_t SH_FLD_RTY_COUNT_LEN = 14789; // 2 +const static uint64_t SH_FLD_RUNNING = 14790; // 92 +const static uint64_t SH_FLD_RUNN_COUNT_COMPARE_VALUE = 14791; // 43 +const static uint64_t SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN = 14792; // 43 +const static uint64_t SH_FLD_RUNN_MODE = 14793; // 43 +const static uint64_t SH_FLD_RUN_CHIPLET_SCAN0 = 14794; // 43 +const static uint64_t SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL = 14795; // 43 +const static uint64_t SH_FLD_RUN_DCCAL = 14796; // 48 +const static uint64_t SH_FLD_RUN_DYN_RECAL_TIMER = 14797; // 4 +const static uint64_t SH_FLD_RUN_LANE = 14798; // 48 +const static uint64_t SH_FLD_RUN_LANE_DL_MASK = 14799; // 2 +const static uint64_t SH_FLD_RUN_ON_CAPTURE_DR = 14800; // 43 +const static uint64_t SH_FLD_RUN_ON_UPDATE_DR = 14801; // 43 +const static uint64_t SH_FLD_RUN_SCAN0 = 14802; // 43 +const static uint64_t SH_FLD_RUN_STATE_MASK = 14803; // 43 +const static uint64_t SH_FLD_RUN_TCK = 14804; // 1 +const static uint64_t SH_FLD_RUN_TCK_EQ0_ERR = 14805; // 1 +const static uint64_t SH_FLD_RWDM_DLY = 14806; // 8 +const static uint64_t SH_FLD_RWDM_DLY_LEN = 14807; // 8 +const static uint64_t SH_FLD_RWSMDR_DLY = 14808; // 8 +const static uint64_t SH_FLD_RWSMDR_DLY_LEN = 14809; // 8 +const static uint64_t SH_FLD_RWSMSR_DLY = 14810; // 8 +const static uint64_t SH_FLD_RWSMSR_DLY_LEN = 14811; // 8 +const static uint64_t SH_FLD_RX = 14812; // 8 +const static uint64_t SH_FLD_RXAERR = 14813; // 6 +const static uint64_t SH_FLD_RXBERR = 14814; // 6 +const static uint64_t SH_FLD_RXCAL = 14815; // 116 +const static uint64_t SH_FLD_RXCERR = 14816; // 6 +const static uint64_t SH_FLD_RXDERR = 14817; // 6 +const static uint64_t SH_FLD_RXEERR = 14818; // 6 +const static uint64_t SH_FLD_RXFERR = 14819; // 6 +const static uint64_t SH_FLD_RXGERR = 14820; // 6 +const static uint64_t SH_FLD_RXHERR = 14821; // 6 +const static uint64_t SH_FLD_RXIERR = 14822; // 6 +const static uint64_t SH_FLD_RXJERR = 14823; // 6 +const static uint64_t SH_FLD_RXKERR = 14824; // 6 +const static uint64_t SH_FLD_RXLERR = 14825; // 6 +const static uint64_t SH_FLD_RXMERR = 14826; // 6 +const static uint64_t SH_FLD_RXNERR = 14827; // 6 +const static uint64_t SH_FLD_RXOERR = 14828; // 6 +const static uint64_t SH_FLD_RXPERR = 14829; // 6 +const static uint64_t SH_FLD_RX_BUS_WIDTH = 14830; // 4 +const static uint64_t SH_FLD_RX_BUS_WIDTH_LEN = 14831; // 4 +const static uint64_t SH_FLD_RX_PCB_DATA_P = 14832; // 1 +const static uint64_t SH_FLD_RX_PCB_DATA_P_ERR = 14833; // 1 +const static uint64_t SH_FLD_RX_SELECT = 14834; // 4 +const static uint64_t SH_FLD_RX_SELECT_LEN = 14835; // 4 +const static uint64_t SH_FLD_RX_TTYPE_0 = 14836; // 4 +const static uint64_t SH_FLD_RX_TTYPE_1 = 14837; // 4 +const static uint64_t SH_FLD_RX_TTYPE_1_ON_STEP_ENABLE = 14838; // 1 +const static uint64_t SH_FLD_RX_TTYPE_2 = 14839; // 4 +const static uint64_t SH_FLD_RX_TTYPE_3 = 14840; // 4 +const static uint64_t SH_FLD_RX_TTYPE_4 = 14841; // 4 +const static uint64_t SH_FLD_RX_TTYPE_4_DATA_PARITY = 14842; // 4 +const static uint64_t SH_FLD_RX_TTYPE_5 = 14843; // 4 +const static uint64_t SH_FLD_RX_TTYPE_INVALID = 14844; // 4 +const static uint64_t SH_FLD_S0_BIT_MAP = 14845; // 8 +const static uint64_t SH_FLD_S0_BIT_MAP_LEN = 14846; // 8 +const static uint64_t SH_FLD_S1_BIT_MAP = 14847; // 8 +const static uint64_t SH_FLD_S1_BIT_MAP_LEN = 14848; // 8 +const static uint64_t SH_FLD_S2_BIT_MAP = 14849; // 8 +const static uint64_t SH_FLD_S2_BIT_MAP_LEN = 14850; // 8 +const static uint64_t SH_FLD_SACOLL = 14851; // 12 +const static uint64_t SH_FLD_SAFE_REFRESH_MODE = 14852; // 8 +const static uint64_t SH_FLD_SAFE_REFRESH_MODE_CLR = 14853; // 8 +const static uint64_t SH_FLD_SAMPLED_SMD_PIN = 14854; // 1 +const static uint64_t SH_FLD_SAMPLE_GUTS = 14855; // 43 +const static uint64_t SH_FLD_SAMPLE_GUTS_LEN = 14856; // 43 +const static uint64_t SH_FLD_SAMPLE_PULSE_CNT = 14857; // 43 +const static uint64_t SH_FLD_SAMPLE_PULSE_CNT_LEN = 14858; // 43 +const static uint64_t SH_FLD_SAMPLE_VALID = 14859; // 12 +const static uint64_t SH_FLD_SAMPTEST_ENABLE = 14860; // 1 +const static uint64_t SH_FLD_SAMPTEST_MATCH_TH_MAX = 14861; // 1 +const static uint64_t SH_FLD_SAMPTEST_MATCH_TH_MAX_LEN = 14862; // 1 +const static uint64_t SH_FLD_SAMPTEST_MATCH_TH_MIN = 14863; // 1 +const static uint64_t SH_FLD_SAMPTEST_MATCH_TH_MIN_LEN = 14864; // 1 +const static uint64_t SH_FLD_SAMPTEST_RRN_ENABLE = 14865; // 1 +const static uint64_t SH_FLD_SAMPTEST_WINDOW_SIZE = 14866; // 1 +const static uint64_t SH_FLD_SAMPTEST_WINDOW_SIZE_LEN = 14867; // 1 +const static uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 14868; // 43 +const static uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 14869; // 43 +const static uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 14870; // 43 +const static uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 14871; // 43 +const static uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR = 14872; // 43 +const static uint64_t SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 14873; // 43 +const static uint64_t SH_FLD_SBASE = 14874; // 12 +const static uint64_t SH_FLD_SBASE_LEN = 14875; // 12 +const static uint64_t SH_FLD_SBC_DMA = 14876; // 1 +const static uint64_t SH_FLD_SBC_DMA_LEN = 14877; // 1 +const static uint64_t SH_FLD_SBC_EOI = 14878; // 1 +const static uint64_t SH_FLD_SBC_EOI_LEN = 14879; // 1 +const static uint64_t SH_FLD_SBC_LOOKUP = 14880; // 1 +const static uint64_t SH_FLD_SBC_LOOKUP_LEN = 14881; // 1 +const static uint64_t SH_FLD_SBEFIFO_DATA = 14882; // 5 +const static uint64_t SH_FLD_SBEFIFO_RESET = 14883; // 5 +const static uint64_t SH_FLD_SBE_EXTERNAL_FIRS = 14884; // 1 +const static uint64_t SH_FLD_SBE_EXTERNAL_FIRS_LEN = 14885; // 1 +const static uint64_t SH_FLD_SB_STRENGTH = 14886; // 43 +const static uint64_t SH_FLD_SB_STRENGTH_LEN = 14887; // 43 +const static uint64_t SH_FLD_SCAN0_MODE = 14888; // 43 +const static uint64_t SH_FLD_SCAN_CLK_USE_EVEN = 14889; // 43 +const static uint64_t SH_FLD_SCAN_COUNT = 14890; // 43 +const static uint64_t SH_FLD_SCAN_COUNT_LEN = 14891; // 43 +const static uint64_t SH_FLD_SCAN_INIT_VERSION_PARITY_MASK = 14892; // 43 +const static uint64_t SH_FLD_SCAN_RATIO = 14893; // 43 +const static uint64_t SH_FLD_SCAN_RATIO_LEN = 14894; // 43 +const static uint64_t SH_FLD_SCOM1_SAT_ERR = 14895; // 2 +const static uint64_t SH_FLD_SCOMSAT00_ERR = 14896; // 1 +const static uint64_t SH_FLD_SCOMSAT01_ERR = 14897; // 1 +const static uint64_t SH_FLD_SCOM_CMD_REG_INJ = 14898; // 2 +const static uint64_t SH_FLD_SCOM_CMD_REG_INJ_MODE = 14899; // 2 +const static uint64_t SH_FLD_SCOM_ERR = 14900; // 14 +const static uint64_t SH_FLD_SCOM_ERR1 = 14901; // 36 +const static uint64_t SH_FLD_SCOM_ERR2 = 14902; // 40 +const static uint64_t SH_FLD_SCOM_ERROR = 14903; // 8 +const static uint64_t SH_FLD_SCOM_ERR_DUP = 14904; // 10 +const static uint64_t SH_FLD_SCOM_FATAL_ERROR = 14905; // 6 +const static uint64_t SH_FLD_SCOM_FATAL_REG_PE = 14906; // 2 +const static uint64_t SH_FLD_SCOM_FIR_HMI = 14907; // 96 +const static uint64_t SH_FLD_SCOM_HANG_LIMIT = 14908; // 43 +const static uint64_t SH_FLD_SCOM_HANG_LIMIT_LEN = 14909; // 43 +const static uint64_t SH_FLD_SCOM_INF_ERROR = 14910; // 6 +const static uint64_t SH_FLD_SCOM_LINK01_RESET_KEEPER = 14911; // 2 +const static uint64_t SH_FLD_SCOM_LINK23_RESET_KEEPER = 14912; // 2 +const static uint64_t SH_FLD_SCOM_LINK45_RESET_KEEPER = 14913; // 2 +const static uint64_t SH_FLD_SCOM_LINK67_RESET_KEEPER = 14914; // 1 +const static uint64_t SH_FLD_SCOM_MMIO_ADDR_ERR = 14915; // 2 +const static uint64_t SH_FLD_SCOM_PARITY_CLASS_RECOVERABLE = 14916; // 8 +const static uint64_t SH_FLD_SCOM_PARITY_CLASS_STATUS = 14917; // 8 +const static uint64_t SH_FLD_SCOM_PARITY_CLASS_UNRECOVERABLE = 14918; // 8 +const static uint64_t SH_FLD_SCOM_PARITY_ERR = 14919; // 3 +const static uint64_t SH_FLD_SCOM_PARITY_ERR2 = 14920; // 3 +const static uint64_t SH_FLD_SCOM_PE = 14921; // 3 +const static uint64_t SH_FLD_SCOM_PERFMON_START_COMMAND = 14922; // 4 +const static uint64_t SH_FLD_SCOM_PERFMON_STOP_COMMAND = 14923; // 4 +const static uint64_t SH_FLD_SCOM_PERR0 = 14924; // 6 +const static uint64_t SH_FLD_SCOM_PERR1 = 14925; // 6 +const static uint64_t SH_FLD_SCOM_PE_DUP = 14926; // 3 +const static uint64_t SH_FLD_SCOM_RECOVERABLE_REG_PE = 14927; // 2 +const static uint64_t SH_FLD_SCOM_SET_WAT_EXT_ARM = 14928; // 2 +const static uint64_t SH_FLD_SCOM_SET_WAT_EXT_RESET = 14929; // 2 +const static uint64_t SH_FLD_SCOM_SET_WAT_EXT_TRIGGER = 14930; // 2 +const static uint64_t SH_FLD_SCOM_S_ERR = 14931; // 1 +const static uint64_t SH_FLD_SCOM_WRITE = 14932; // 24 +const static uint64_t SH_FLD_SCOPE = 14933; // 24 +const static uint64_t SH_FLD_SCOPE_ATTN_BAR = 14934; // 1 +const static uint64_t SH_FLD_SCOPE_ATTN_BAR_LEN = 14935; // 1 +const static uint64_t SH_FLD_SCOPE_CONTROL = 14936; // 6 +const static uint64_t SH_FLD_SCOPE_CONTROL_LEN = 14937; // 6 +const static uint64_t SH_FLD_SCOPE_LEN = 14938; // 24 +const static uint64_t SH_FLD_SCOPE_MODE = 14939; // 48 +const static uint64_t SH_FLD_SCOPE_MODE_LEN = 14940; // 48 +const static uint64_t SH_FLD_SCPTGT_LFSR_MODE = 14941; // 2 +const static uint64_t SH_FLD_SCPTGT_LFSR_MODE_LEN = 14942; // 2 +const static uint64_t SH_FLD_SCRATCH_ATOMIC_DATA = 14943; // 24 +const static uint64_t SH_FLD_SCRATCH_ATOMIC_DATA_LEN = 14944; // 24 +const static uint64_t SH_FLD_SCRATCH_N = 14945; // 4 +const static uint64_t SH_FLD_SCRATCH_N_LEN = 14946; // 4 +const static uint64_t SH_FLD_SEC = 14947; // 8 +const static uint64_t SH_FLD_SECURE = 14948; // 1 +const static uint64_t SH_FLD_SECURE_ACCESS = 14949; // 1 +const static uint64_t SH_FLD_SECURE_ACCESS_BIT = 14950; // 1 +const static uint64_t SH_FLD_SECURE_DEBUG = 14951; // 1 +const static uint64_t SH_FLD_SECURE_DEBUG_MODE = 14952; // 1 +const static uint64_t SH_FLD_SECURE_ERR = 14953; // 2 +const static uint64_t SH_FLD_SECURE_MODE = 14954; // 1 +const static uint64_t SH_FLD_SECURE_SCOM_ERROR = 14955; // 4 +const static uint64_t SH_FLD_SECURITY_DEBUG_MODE = 14956; // 43 +const static uint64_t SH_FLD_SEC_I_PATH_STEP_CHECK_ENABLE = 14957; // 1 +const static uint64_t SH_FLD_SEC_LEN = 14958; // 8 +const static uint64_t SH_FLD_SEC_M_PATH_0_STEP_CHECK_ENABLE = 14959; // 1 +const static uint64_t SH_FLD_SEC_M_PATH_1_STEP_CHECK_ENABLE = 14960; // 1 +const static uint64_t SH_FLD_SEC_M_PATH_SELECT = 14961; // 2 +const static uint64_t SH_FLD_SEC_M_S_DRAWER_SELECT = 14962; // 2 +const static uint64_t SH_FLD_SEC_M_S_SELECT = 14963; // 2 +const static uint64_t SH_FLD_SEC_SELECT = 14964; // 1 +const static uint64_t SH_FLD_SEC_S_PATH_0_STEP_CHECK_ENABLE = 14965; // 1 +const static uint64_t SH_FLD_SEC_S_PATH_1_STEP_CHECK_ENABLE = 14966; // 1 +const static uint64_t SH_FLD_SEC_S_PATH_SELECT = 14967; // 1 +const static uint64_t SH_FLD_SEC_V = 14968; // 8 +const static uint64_t SH_FLD_SEC_WBRD_DEBUG_0_SELECT = 14969; // 8 +const static uint64_t SH_FLD_SEC_WBRD_DEBUG_1_SELECT = 14970; // 8 +const static uint64_t SH_FLD_SEEPROM_UPDATE_LOCK = 14971; // 1 +const static uint64_t SH_FLD_SEG_TEST_CLK_STATUS = 14972; // 4 +const static uint64_t SH_FLD_SEG_TEST_CLK_STATUS_LEN = 14973; // 4 +const static uint64_t SH_FLD_SEG_TEST_LEAKAGE_CTRL = 14974; // 6 +const static uint64_t SH_FLD_SEG_TEST_MODE = 14975; // 6 +const static uint64_t SH_FLD_SEG_TEST_MODE_LEN = 14976; // 6 +const static uint64_t SH_FLD_SEG_TEST_STATUS = 14977; // 116 +const static uint64_t SH_FLD_SEG_TEST_STATUS_LEN = 14978; // 116 +const static uint64_t SH_FLD_SEIDBAR = 14979; // 1 +const static uint64_t SH_FLD_SEIDBAR_LEN = 14980; // 1 +const static uint64_t SH_FLD_SEIDR = 14981; // 256 +const static uint64_t SH_FLD_SEIDR_LEN = 14982; // 256 +const static uint64_t SH_FLD_SEL = 14983; // 10 +const static uint64_t SH_FLD_SEL0 = 14984; // 1 +const static uint64_t SH_FLD_SEL0_LEN = 14985; // 1 +const static uint64_t SH_FLD_SEL1 = 14986; // 1 +const static uint64_t SH_FLD_SEL1_LEN = 14987; // 1 +const static uint64_t SH_FLD_SELD2SPR = 14988; // 10 +const static uint64_t SH_FLD_SELECT = 14989; // 14 +const static uint64_t SH_FLD_SELECT_LEN = 14990; // 14 +const static uint64_t SH_FLD_SELECT_LOCAL_HANG_PULSE = 14991; // 4 +const static uint64_t SH_FLD_SELECT_PB_HANG_PULSE = 14992; // 4 +const static uint64_t SH_FLD_SELECT_REGISTER_FSP2PIB = 14993; // 1 +const static uint64_t SH_FLD_SELECT_REGISTER_FSP2PIB_LEN = 14994; // 1 +const static uint64_t SH_FLD_SELECT_SECONDARY_SEEPROM = 14995; // 1 +const static uint64_t SH_FLD_SELFBOOT_DONE = 14996; // 1 +const static uint64_t SH_FLD_SELFBOOT_ENGINE_ATTENTION = 14997; // 1 +const static uint64_t SH_FLD_SELF_BUSY_0 = 14998; // 4 +const static uint64_t SH_FLD_SELF_BUSY_1 = 14999; // 2 +const static uint64_t SH_FLD_SELF_BUSY_2 = 15000; // 2 +const static uint64_t SH_FLD_SELF_BUSY_3 = 15001; // 2 +const static uint64_t SH_FLD_SELPFDPW = 15002; // 10 +const static uint64_t SH_FLD_SELPREFB = 15003; // 10 +const static uint64_t SH_FLD_SELPRESPE = 15004; // 10 +const static uint64_t SH_FLD_SEL_03_NPU_NOT = 15005; // 1 +const static uint64_t SH_FLD_SEL_04_NPU_NOT = 15006; // 1 +const static uint64_t SH_FLD_SEL_05_NPU_NOT = 15007; // 1 +const static uint64_t SH_FLD_SEL_0_2 = 15008; // 16 +const static uint64_t SH_FLD_SEL_0_2_LEN = 15009; // 16 +const static uint64_t SH_FLD_SEL_1_3 = 15010; // 16 +const static uint64_t SH_FLD_SEL_1_3_LEN = 15011; // 16 +const static uint64_t SH_FLD_SEL_LEN = 15012; // 10 +const static uint64_t SH_FLD_SEL_RG_PMU_DATA = 15013; // 1 +const static uint64_t SH_FLD_SEL_RG_TRACE_DATA_HI = 15014; // 1 +const static uint64_t SH_FLD_SEL_RG_TRACE_DATA_HI_LEN = 15015; // 1 +const static uint64_t SH_FLD_SEL_RG_TRACE_DATA_LO = 15016; // 1 +const static uint64_t SH_FLD_SEL_RG_TRACE_DATA_LO_LEN = 15017; // 1 +const static uint64_t SH_FLD_SEL_RG_TRIGGERS_01 = 15018; // 1 +const static uint64_t SH_FLD_SEL_RG_TRIGGERS_01_LEN = 15019; // 1 +const static uint64_t SH_FLD_SEL_RG_TRIGGERS_23 = 15020; // 1 +const static uint64_t SH_FLD_SEL_RG_TRIGGERS_23_LEN = 15021; // 1 +const static uint64_t SH_FLD_SEL_THOLD_ARY = 15022; // 43 +const static uint64_t SH_FLD_SEL_THOLD_NSL = 15023; // 43 +const static uint64_t SH_FLD_SEL_THOLD_SL = 15024; // 43 +const static uint64_t SH_FLD_SEL_TYPE_0_2 = 15025; // 16 +const static uint64_t SH_FLD_SEL_TYPE_1_3 = 15026; // 16 +const static uint64_t SH_FLD_SEND_DELAY_CYCLES = 15027; // 2 +const static uint64_t SH_FLD_SEND_DELAY_CYCLES_LEN = 15028; // 2 +const static uint64_t SH_FLD_SEND_PACKET_TIMER_VALUE = 15029; // 2 +const static uint64_t SH_FLD_SEND_PACKET_TIMER_VALUE_LEN = 15030; // 2 +const static uint64_t SH_FLD_SEQ = 15031; // 8 +const static uint64_t SH_FLD_SEQ_01 = 15032; // 43 +const static uint64_t SH_FLD_SEQ_01_LEN = 15033; // 43 +const static uint64_t SH_FLD_SEQ_02 = 15034; // 43 +const static uint64_t SH_FLD_SEQ_02_LEN = 15035; // 43 +const static uint64_t SH_FLD_SEQ_03 = 15036; // 43 +const static uint64_t SH_FLD_SEQ_03_LEN = 15037; // 43 +const static uint64_t SH_FLD_SEQ_04 = 15038; // 43 +const static uint64_t SH_FLD_SEQ_04_LEN = 15039; // 43 +const static uint64_t SH_FLD_SEQ_05 = 15040; // 43 +const static uint64_t SH_FLD_SEQ_05_LEN = 15041; // 43 +const static uint64_t SH_FLD_SEQ_06 = 15042; // 43 +const static uint64_t SH_FLD_SEQ_06_LEN = 15043; // 43 +const static uint64_t SH_FLD_SEQ_07 = 15044; // 43 +const static uint64_t SH_FLD_SEQ_07EVEN = 15045; // 43 +const static uint64_t SH_FLD_SEQ_07EVEN_LEN = 15046; // 43 +const static uint64_t SH_FLD_SEQ_07ODD = 15047; // 43 +const static uint64_t SH_FLD_SEQ_07ODD_LEN = 15048; // 43 +const static uint64_t SH_FLD_SEQ_07_LEN = 15049; // 43 +const static uint64_t SH_FLD_SEQ_08 = 15050; // 43 +const static uint64_t SH_FLD_SEQ_08EVEN = 15051; // 43 +const static uint64_t SH_FLD_SEQ_08EVEN_LEN = 15052; // 43 +const static uint64_t SH_FLD_SEQ_08ODD = 15053; // 43 +const static uint64_t SH_FLD_SEQ_08ODD_LEN = 15054; // 43 +const static uint64_t SH_FLD_SEQ_08_LEN = 15055; // 43 +const static uint64_t SH_FLD_SEQ_09 = 15056; // 43 +const static uint64_t SH_FLD_SEQ_09EVEN = 15057; // 43 +const static uint64_t SH_FLD_SEQ_09EVEN_LEN = 15058; // 43 +const static uint64_t SH_FLD_SEQ_09ODD = 15059; // 43 +const static uint64_t SH_FLD_SEQ_09ODD_LEN = 15060; // 43 +const static uint64_t SH_FLD_SEQ_09_LEN = 15061; // 43 +const static uint64_t SH_FLD_SEQ_10 = 15062; // 43 +const static uint64_t SH_FLD_SEQ_10EVEN = 15063; // 43 +const static uint64_t SH_FLD_SEQ_10EVEN_LEN = 15064; // 43 +const static uint64_t SH_FLD_SEQ_10ODD = 15065; // 43 +const static uint64_t SH_FLD_SEQ_10ODD_LEN = 15066; // 43 +const static uint64_t SH_FLD_SEQ_10_LEN = 15067; // 43 +const static uint64_t SH_FLD_SEQ_11 = 15068; // 43 +const static uint64_t SH_FLD_SEQ_11EVEN = 15069; // 43 +const static uint64_t SH_FLD_SEQ_11EVEN_LEN = 15070; // 43 +const static uint64_t SH_FLD_SEQ_11ODD = 15071; // 43 +const static uint64_t SH_FLD_SEQ_11ODD_LEN = 15072; // 43 +const static uint64_t SH_FLD_SEQ_11_LEN = 15073; // 43 +const static uint64_t SH_FLD_SEQ_12 = 15074; // 43 +const static uint64_t SH_FLD_SEQ_12EVEN = 15075; // 43 +const static uint64_t SH_FLD_SEQ_12EVEN_LEN = 15076; // 43 +const static uint64_t SH_FLD_SEQ_12ODD = 15077; // 43 +const static uint64_t SH_FLD_SEQ_12ODD_LEN = 15078; // 43 +const static uint64_t SH_FLD_SEQ_12_LEN = 15079; // 43 +const static uint64_t SH_FLD_SEQ_13_01EVEN = 15080; // 43 +const static uint64_t SH_FLD_SEQ_13_01EVEN_LEN = 15081; // 43 +const static uint64_t SH_FLD_SEQ_14_01ODD = 15082; // 43 +const static uint64_t SH_FLD_SEQ_14_01ODD_LEN = 15083; // 43 +const static uint64_t SH_FLD_SEQ_15_02EVEN = 15084; // 43 +const static uint64_t SH_FLD_SEQ_15_02EVEN_LEN = 15085; // 43 +const static uint64_t SH_FLD_SEQ_16_02ODD = 15086; // 43 +const static uint64_t SH_FLD_SEQ_16_02ODD_LEN = 15087; // 43 +const static uint64_t SH_FLD_SEQ_17_03EVEN = 15088; // 43 +const static uint64_t SH_FLD_SEQ_17_03EVEN_LEN = 15089; // 43 +const static uint64_t SH_FLD_SEQ_18_03ODD = 15090; // 43 +const static uint64_t SH_FLD_SEQ_18_03ODD_LEN = 15091; // 43 +const static uint64_t SH_FLD_SEQ_19_04EVEN = 15092; // 43 +const static uint64_t SH_FLD_SEQ_19_04EVEN_LEN = 15093; // 43 +const static uint64_t SH_FLD_SEQ_20_04ODD = 15094; // 43 +const static uint64_t SH_FLD_SEQ_20_04ODD_LEN = 15095; // 43 +const static uint64_t SH_FLD_SEQ_21_05EVEN = 15096; // 43 +const static uint64_t SH_FLD_SEQ_21_05EVEN_LEN = 15097; // 43 +const static uint64_t SH_FLD_SEQ_22_05ODD = 15098; // 43 +const static uint64_t SH_FLD_SEQ_22_05ODD_LEN = 15099; // 43 +const static uint64_t SH_FLD_SEQ_23_06EVEN = 15100; // 43 +const static uint64_t SH_FLD_SEQ_23_06EVEN_LEN = 15101; // 43 +const static uint64_t SH_FLD_SEQ_24_06ODD = 15102; // 43 +const static uint64_t SH_FLD_SEQ_24_06ODD_LEN = 15103; // 43 +const static uint64_t SH_FLD_SEQ_MASK = 15104; // 8 +const static uint64_t SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 15105; // 43 +const static uint64_t SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 15106; // 43 +const static uint64_t SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK = 15107; // 43 +const static uint64_t SH_FLD_SERVO_CHG_CFG = 15108; // 6 +const static uint64_t SH_FLD_SERVO_CHG_CFG_LEN = 15109; // 6 +const static uint64_t SH_FLD_SERVO_DONE = 15110; // 6 +const static uint64_t SH_FLD_SERVO_OP = 15111; // 6 +const static uint64_t SH_FLD_SERVO_OP_LEN = 15112; // 6 +const static uint64_t SH_FLD_SERVO_RECAL_IP = 15113; // 4 +const static uint64_t SH_FLD_SERVO_RESULT = 15114; // 6 +const static uint64_t SH_FLD_SERVO_RESULT_LEN = 15115; // 6 +const static uint64_t SH_FLD_SERVO_THRESH1 = 15116; // 6 +const static uint64_t SH_FLD_SERVO_THRESH1_LEN = 15117; // 6 +const static uint64_t SH_FLD_SERVO_THRESH2 = 15118; // 6 +const static uint64_t SH_FLD_SERVO_THRESH2_LEN = 15119; // 6 +const static uint64_t SH_FLD_SERVO_THRESH3 = 15120; // 4 +const static uint64_t SH_FLD_SERVO_THRESH3_LEN = 15121; // 4 +const static uint64_t SH_FLD_SET = 15122; // 6 +const static uint64_t SH_FLD_SET_CMDS = 15123; // 2 +const static uint64_t SH_FLD_SET_CMDS_EN = 15124; // 2 +const static uint64_t SH_FLD_SET_CMDS_LEN = 15125; // 2 +const static uint64_t SH_FLD_SET_ECC_INJECT_ERR = 15126; // 12 +const static uint64_t SH_FLD_SET_INDEX = 15127; // 2 +const static uint64_t SH_FLD_SET_INDEX_LEN = 15128; // 2 +const static uint64_t SH_FLD_SET_LEN = 15129; // 6 +const static uint64_t SH_FLD_SGB_BYTE_VALID = 15130; // 21 +const static uint64_t SH_FLD_SGB_BYTE_VALID_LEN = 15131; // 21 +const static uint64_t SH_FLD_SGB_FLUSH_PENDING = 15132; // 21 +const static uint64_t SH_FLD_SG_HIGH_DURING_FILL = 15133; // 43 +const static uint64_t SH_FLD_SHADOW_ANALOGTUNE = 15134; // 14 +const static uint64_t SH_FLD_SHADOW_ANALOGTUNE_LEN = 15135; // 14 +const static uint64_t SH_FLD_SHADOW_ATSTSEL = 15136; // 14 +const static uint64_t SH_FLD_SHADOW_ATSTSEL_LEN = 15137; // 14 +const static uint64_t SH_FLD_SHADOW_BANDSEL = 15138; // 14 +const static uint64_t SH_FLD_SHADOW_BANDSEL_LEN = 15139; // 14 +const static uint64_t SH_FLD_SHADOW_BGOFFSET = 15140; // 14 +const static uint64_t SH_FLD_SHADOW_BGOFFSET_LEN = 15141; // 14 +const static uint64_t SH_FLD_SHADOW_BYPASSN = 15142; // 10 +const static uint64_t SH_FLD_SHADOW_CALRECAL = 15143; // 10 +const static uint64_t SH_FLD_SHADOW_CALREQ = 15144; // 10 +const static uint64_t SH_FLD_SHADOW_CAPSEL = 15145; // 4 +const static uint64_t SH_FLD_SHADOW_CCALBANDSEL = 15146; // 10 +const static uint64_t SH_FLD_SHADOW_CCALBANDSEL_LEN = 15147; // 10 +const static uint64_t SH_FLD_SHADOW_CCALCOMP = 15148; // 10 +const static uint64_t SH_FLD_SHADOW_CCALCVHOLD = 15149; // 10 +const static uint64_t SH_FLD_SHADOW_CCALERR = 15150; // 10 +const static uint64_t SH_FLD_SHADOW_CCALFMAX = 15151; // 10 +const static uint64_t SH_FLD_SHADOW_CCALFMIN = 15152; // 10 +const static uint64_t SH_FLD_SHADOW_CCALLOAD = 15153; // 10 +const static uint64_t SH_FLD_SHADOW_CCALMETH = 15154; // 10 +const static uint64_t SH_FLD_SHADOW_CMLEN = 15155; // 10 +const static uint64_t SH_FLD_SHADOW_CPISEL = 15156; // 14 +const static uint64_t SH_FLD_SHADOW_CPISEL_LEN = 15157; // 14 +const static uint64_t SH_FLD_SHADOW_CSEL = 15158; // 10 +const static uint64_t SH_FLD_SHADOW_CSEL_LEN = 15159; // 10 +const static uint64_t SH_FLD_SHADOW_DIVSELB = 15160; // 10 +const static uint64_t SH_FLD_SHADOW_DIVSELB_LEN = 15161; // 10 +const static uint64_t SH_FLD_SHADOW_DIVSELFB = 15162; // 4 +const static uint64_t SH_FLD_SHADOW_DIVSELFB_LEN = 15163; // 4 +const static uint64_t SH_FLD_SHADOW_EN = 15164; // 10 +const static uint64_t SH_FLD_SHADOW_ENABLE = 15165; // 10 +const static uint64_t SH_FLD_SHADOW_FILTDIVSEL = 15166; // 3 +const static uint64_t SH_FLD_SHADOW_FILTDIVSEL_LEN = 15167; // 3 +const static uint64_t SH_FLD_SHADOW_FRAC1 = 15168; // 3 +const static uint64_t SH_FLD_SHADOW_FRAC1_LEN = 15169; // 3 +const static uint64_t SH_FLD_SHADOW_FRAC2 = 15170; // 3 +const static uint64_t SH_FLD_SHADOW_FRAC2_LEN = 15171; // 3 +const static uint64_t SH_FLD_SHADOW_ITUNE = 15172; // 4 +const static uint64_t SH_FLD_SHADOW_ITUNE_LEN = 15173; // 4 +const static uint64_t SH_FLD_SHADOW_LOCK = 15174; // 10 +const static uint64_t SH_FLD_SHADOW_MUXEN = 15175; // 4 +const static uint64_t SH_FLD_SHADOW_MUXSEL = 15176; // 4 +const static uint64_t SH_FLD_SHADOW_MUXSEL_LEN = 15177; // 4 +const static uint64_t SH_FLD_SHADOW_PCLKDIFSEL = 15178; // 10 +const static uint64_t SH_FLD_SHADOW_PCLKSEL = 15179; // 14 +const static uint64_t SH_FLD_SHADOW_PCLKSEL_LEN = 15180; // 14 +const static uint64_t SH_FLD_SHADOW_PFD360SEL = 15181; // 4 +const static uint64_t SH_FLD_SHADOW_PHASEFB = 15182; // 4 +const static uint64_t SH_FLD_SHADOW_PHASEFB_LEN = 15183; // 4 +const static uint64_t SH_FLD_SHADOW_PLLLOCK = 15184; // 4 +const static uint64_t SH_FLD_SHADOW_RDIV = 15185; // 14 +const static uint64_t SH_FLD_SHADOW_RDIV_LEN = 15186; // 10 +const static uint64_t SH_FLD_SHADOW_REFCLKSEL = 15187; // 4 +const static uint64_t SH_FLD_SHADOW_RESET = 15188; // 10 +const static uint64_t SH_FLD_SHADOW_RESSEL = 15189; // 4 +const static uint64_t SH_FLD_SHADOW_RSEL = 15190; // 10 +const static uint64_t SH_FLD_SHADOW_RSEL_LEN = 15191; // 10 +const static uint64_t SH_FLD_SHADOW_SEL = 15192; // 10 +const static uint64_t SH_FLD_SHADOW_SELD2SPR = 15193; // 10 +const static uint64_t SH_FLD_SHADOW_SELPFDPW = 15194; // 10 +const static uint64_t SH_FLD_SHADOW_SELPREFB = 15195; // 10 +const static uint64_t SH_FLD_SHADOW_SELPRESPE = 15196; // 10 +const static uint64_t SH_FLD_SHADOW_SEL_LEN = 15197; // 10 +const static uint64_t SH_FLD_SHADOW_SPARE = 15198; // 7 +const static uint64_t SH_FLD_SHADOW_SPARE_LEN = 15199; // 3 +const static uint64_t SH_FLD_SHADOW_SPEDIV = 15200; // 10 +const static uint64_t SH_FLD_SHADOW_SPEDIV_LEN = 15201; // 10 +const static uint64_t SH_FLD_SHADOW_SSCGEN = 15202; // 3 +const static uint64_t SH_FLD_SHADOW_SYNCEN = 15203; // 7 +const static uint64_t SH_FLD_SHADOW_THREEPHAS = 15204; // 3 +const static uint64_t SH_FLD_SHADOW_UNUSED23_31 = 15205; // 7 +const static uint64_t SH_FLD_SHADOW_UNUSED23_31_LEN = 15206; // 7 +const static uint64_t SH_FLD_SHADOW_UNUSED4 = 15207; // 7 +const static uint64_t SH_FLD_SHADOW_UNUSED5 = 15208; // 7 +const static uint64_t SH_FLD_SHADOW_UNUSED63 = 15209; // 3 +const static uint64_t SH_FLD_SHADOW_UNUSED88 = 15210; // 3 +const static uint64_t SH_FLD_SHADOW_UNUSED88_LEN = 15211; // 3 +const static uint64_t SH_FLD_SHADOW_VCORANGE = 15212; // 10 +const static uint64_t SH_FLD_SHADOW_VCORANGE_LEN = 15213; // 10 +const static uint64_t SH_FLD_SHADOW_VCOSEL = 15214; // 10 +const static uint64_t SH_FLD_SHADOW_VREGBYPASS = 15215; // 4 +const static uint64_t SH_FLD_SHADOW_VREGENABLE_N = 15216; // 4 +const static uint64_t SH_FLD_SHADOW_VSEL = 15217; // 10 +const static uint64_t SH_FLD_SHADOW_VSEL_LEN = 15218; // 10 +const static uint64_t SH_FLD_SHA_LATENCY_CFG = 15219; // 1 +const static uint64_t SH_FLD_SHIFTER_PARITY_MASK = 15220; // 43 +const static uint64_t SH_FLD_SHIFTER_VALID_MASK = 15221; // 43 +const static uint64_t SH_FLD_SIGNATURE = 15222; // 1 +const static uint64_t SH_FLD_SIGNATURE_LEN = 15223; // 1 +const static uint64_t SH_FLD_SINGLE_BIT_MPR_RP0 = 15224; // 8 +const static uint64_t SH_FLD_SINGLE_BIT_MPR_RP1 = 15225; // 8 +const static uint64_t SH_FLD_SINGLE_BIT_MPR_RP2 = 15226; // 8 +const static uint64_t SH_FLD_SINGLE_BIT_MPR_RP3 = 15227; // 8 +const static uint64_t SH_FLD_SINGLE_OUTSTANDING_CMD = 15228; // 1 +const static uint64_t SH_FLD_SIR_CERR = 15229; // 8 +const static uint64_t SH_FLD_SIZE = 15230; // 45 +const static uint64_t SH_FLD_SIZE_LEN = 15231; // 45 +const static uint64_t SH_FLD_SKIP_G = 15232; // 4 +const static uint64_t SH_FLD_SKIP_INVALID_ADDR_DIMM_DIS = 15233; // 2 +const static uint64_t SH_FLD_SKIP_RDCENTERING = 15234; // 8 +const static uint64_t SH_FLD_SKITTER0 = 15235; // 43 +const static uint64_t SH_FLD_SKITTER0_LEN = 15236; // 43 +const static uint64_t SH_FLD_SKITTER_FORCEREG_PARITY_MASK = 15237; // 43 +const static uint64_t SH_FLD_SKITTER_MODEREG_PARITY_MASK = 15238; // 43 +const static uint64_t SH_FLD_SLAVE10_ERROR_CODE = 15239; // 1 +const static uint64_t SH_FLD_SLAVE10_ERROR_CODE_LEN = 15240; // 1 +const static uint64_t SH_FLD_SLAVE10_RESPONSE_BIT = 15241; // 1 +const static uint64_t SH_FLD_SLAVE11_ERROR_CODE = 15242; // 1 +const static uint64_t SH_FLD_SLAVE11_ERROR_CODE_LEN = 15243; // 1 +const static uint64_t SH_FLD_SLAVE11_RESPONSE_BIT = 15244; // 1 +const static uint64_t SH_FLD_SLAVE12_ERROR_CODE = 15245; // 1 +const static uint64_t SH_FLD_SLAVE12_ERROR_CODE_LEN = 15246; // 1 +const static uint64_t SH_FLD_SLAVE12_RESPONSE_BIT = 15247; // 1 +const static uint64_t SH_FLD_SLAVE13_ERROR_CODE = 15248; // 1 +const static uint64_t SH_FLD_SLAVE13_ERROR_CODE_LEN = 15249; // 1 +const static uint64_t SH_FLD_SLAVE13_RESPONSE_BIT = 15250; // 1 +const static uint64_t SH_FLD_SLAVE14_ERROR_CODE = 15251; // 1 +const static uint64_t SH_FLD_SLAVE14_ERROR_CODE_LEN = 15252; // 1 +const static uint64_t SH_FLD_SLAVE14_RESPONSE_BIT = 15253; // 1 +const static uint64_t SH_FLD_SLAVE15_ERROR_CODE = 15254; // 1 +const static uint64_t SH_FLD_SLAVE15_ERROR_CODE_LEN = 15255; // 1 +const static uint64_t SH_FLD_SLAVE15_RESPONSE_BIT = 15256; // 1 +const static uint64_t SH_FLD_SLAVE16_ERROR_CODE = 15257; // 1 +const static uint64_t SH_FLD_SLAVE16_ERROR_CODE_LEN = 15258; // 1 +const static uint64_t SH_FLD_SLAVE16_RESPONSE_BIT = 15259; // 1 +const static uint64_t SH_FLD_SLAVE17_ERROR_CODE = 15260; // 1 +const static uint64_t SH_FLD_SLAVE17_ERROR_CODE_LEN = 15261; // 1 +const static uint64_t SH_FLD_SLAVE17_RESPONSE_BIT = 15262; // 1 +const static uint64_t SH_FLD_SLAVE18_ERROR_CODE = 15263; // 1 +const static uint64_t SH_FLD_SLAVE18_ERROR_CODE_LEN = 15264; // 1 +const static uint64_t SH_FLD_SLAVE18_RESPONSE_BIT = 15265; // 1 +const static uint64_t SH_FLD_SLAVE19_ERROR_CODE = 15266; // 1 +const static uint64_t SH_FLD_SLAVE19_ERROR_CODE_LEN = 15267; // 1 +const static uint64_t SH_FLD_SLAVE19_RESPONSE_BIT = 15268; // 1 +const static uint64_t SH_FLD_SLAVE1_ERROR_CODE = 15269; // 1 +const static uint64_t SH_FLD_SLAVE1_ERROR_CODE_LEN = 15270; // 1 +const static uint64_t SH_FLD_SLAVE1_RESPONSE_BIT = 15271; // 1 +const static uint64_t SH_FLD_SLAVE20_ERROR_CODE = 15272; // 1 +const static uint64_t SH_FLD_SLAVE20_ERROR_CODE_LEN = 15273; // 1 +const static uint64_t SH_FLD_SLAVE20_RESPONSE_BIT = 15274; // 1 +const static uint64_t SH_FLD_SLAVE21_ERROR_CODE = 15275; // 1 +const static uint64_t SH_FLD_SLAVE21_ERROR_CODE_LEN = 15276; // 1 +const static uint64_t SH_FLD_SLAVE21_RESPONSE_BIT = 15277; // 1 +const static uint64_t SH_FLD_SLAVE22_ERROR_CODE = 15278; // 1 +const static uint64_t SH_FLD_SLAVE22_ERROR_CODE_LEN = 15279; // 1 +const static uint64_t SH_FLD_SLAVE22_RESPONSE_BIT = 15280; // 1 +const static uint64_t SH_FLD_SLAVE23_ERROR_CODE = 15281; // 1 +const static uint64_t SH_FLD_SLAVE23_ERROR_CODE_LEN = 15282; // 1 +const static uint64_t SH_FLD_SLAVE23_RESPONSE_BIT = 15283; // 1 +const static uint64_t SH_FLD_SLAVE24_ERROR_CODE = 15284; // 1 +const static uint64_t SH_FLD_SLAVE24_ERROR_CODE_LEN = 15285; // 1 +const static uint64_t SH_FLD_SLAVE24_RESPONSE_BIT = 15286; // 1 +const static uint64_t SH_FLD_SLAVE25_ERROR_CODE = 15287; // 1 +const static uint64_t SH_FLD_SLAVE25_ERROR_CODE_LEN = 15288; // 1 +const static uint64_t SH_FLD_SLAVE25_RESPONSE_BIT = 15289; // 1 +const static uint64_t SH_FLD_SLAVE26_ERROR_CODE = 15290; // 1 +const static uint64_t SH_FLD_SLAVE26_ERROR_CODE_LEN = 15291; // 1 +const static uint64_t SH_FLD_SLAVE26_RESPONSE_BIT = 15292; // 1 +const static uint64_t SH_FLD_SLAVE27_ERROR_CODE = 15293; // 1 +const static uint64_t SH_FLD_SLAVE27_ERROR_CODE_LEN = 15294; // 1 +const static uint64_t SH_FLD_SLAVE27_RESPONSE_BIT = 15295; // 1 +const static uint64_t SH_FLD_SLAVE28_ERROR_CODE = 15296; // 1 +const static uint64_t SH_FLD_SLAVE28_ERROR_CODE_LEN = 15297; // 1 +const static uint64_t SH_FLD_SLAVE28_RESPONSE_BIT = 15298; // 1 +const static uint64_t SH_FLD_SLAVE29_ERROR_CODE = 15299; // 1 +const static uint64_t SH_FLD_SLAVE29_ERROR_CODE_LEN = 15300; // 1 +const static uint64_t SH_FLD_SLAVE29_RESPONSE_BIT = 15301; // 1 +const static uint64_t SH_FLD_SLAVE2_ERROR_CODE = 15302; // 1 +const static uint64_t SH_FLD_SLAVE2_ERROR_CODE_LEN = 15303; // 1 +const static uint64_t SH_FLD_SLAVE2_RESPONSE_BIT = 15304; // 1 +const static uint64_t SH_FLD_SLAVE30_ERROR_CODE = 15305; // 1 +const static uint64_t SH_FLD_SLAVE30_ERROR_CODE_LEN = 15306; // 1 +const static uint64_t SH_FLD_SLAVE30_RESPONSE_BIT = 15307; // 1 +const static uint64_t SH_FLD_SLAVE31_ERROR_CODE = 15308; // 1 +const static uint64_t SH_FLD_SLAVE31_ERROR_CODE_LEN = 15309; // 1 +const static uint64_t SH_FLD_SLAVE31_RESPONSE_BIT = 15310; // 1 +const static uint64_t SH_FLD_SLAVE32_ERROR_CODE = 15311; // 1 +const static uint64_t SH_FLD_SLAVE32_ERROR_CODE_LEN = 15312; // 1 +const static uint64_t SH_FLD_SLAVE32_RESPONSE_BIT = 15313; // 1 +const static uint64_t SH_FLD_SLAVE33_ERROR_CODE = 15314; // 1 +const static uint64_t SH_FLD_SLAVE33_ERROR_CODE_LEN = 15315; // 1 +const static uint64_t SH_FLD_SLAVE33_RESPONSE_BIT = 15316; // 1 +const static uint64_t SH_FLD_SLAVE34_ERROR_CODE = 15317; // 1 +const static uint64_t SH_FLD_SLAVE34_ERROR_CODE_LEN = 15318; // 1 +const static uint64_t SH_FLD_SLAVE34_RESPONSE_BIT = 15319; // 1 +const static uint64_t SH_FLD_SLAVE35_ERROR_CODE = 15320; // 1 +const static uint64_t SH_FLD_SLAVE35_ERROR_CODE_LEN = 15321; // 1 +const static uint64_t SH_FLD_SLAVE35_RESPONSE_BIT = 15322; // 1 +const static uint64_t SH_FLD_SLAVE36_ERROR_CODE = 15323; // 1 +const static uint64_t SH_FLD_SLAVE36_ERROR_CODE_LEN = 15324; // 1 +const static uint64_t SH_FLD_SLAVE36_RESPONSE_BIT = 15325; // 1 +const static uint64_t SH_FLD_SLAVE37_ERROR_CODE = 15326; // 1 +const static uint64_t SH_FLD_SLAVE37_ERROR_CODE_LEN = 15327; // 1 +const static uint64_t SH_FLD_SLAVE37_RESPONSE_BIT = 15328; // 1 +const static uint64_t SH_FLD_SLAVE38_ERROR_CODE = 15329; // 1 +const static uint64_t SH_FLD_SLAVE38_ERROR_CODE_LEN = 15330; // 1 +const static uint64_t SH_FLD_SLAVE38_RESPONSE_BIT = 15331; // 1 +const static uint64_t SH_FLD_SLAVE39_ERROR_CODE = 15332; // 1 +const static uint64_t SH_FLD_SLAVE39_ERROR_CODE_LEN = 15333; // 1 +const static uint64_t SH_FLD_SLAVE39_RESPONSE_BIT = 15334; // 1 +const static uint64_t SH_FLD_SLAVE3_ERROR_CODE = 15335; // 1 +const static uint64_t SH_FLD_SLAVE3_ERROR_CODE_LEN = 15336; // 1 +const static uint64_t SH_FLD_SLAVE3_RESPONSE_BIT = 15337; // 1 +const static uint64_t SH_FLD_SLAVE40_ERROR_CODE = 15338; // 1 +const static uint64_t SH_FLD_SLAVE40_ERROR_CODE_LEN = 15339; // 1 +const static uint64_t SH_FLD_SLAVE40_RESPONSE_BIT = 15340; // 1 +const static uint64_t SH_FLD_SLAVE41_ERROR_CODE = 15341; // 1 +const static uint64_t SH_FLD_SLAVE41_ERROR_CODE_LEN = 15342; // 1 +const static uint64_t SH_FLD_SLAVE41_RESPONSE_BIT = 15343; // 1 +const static uint64_t SH_FLD_SLAVE42_ERROR_CODE = 15344; // 1 +const static uint64_t SH_FLD_SLAVE42_ERROR_CODE_LEN = 15345; // 1 +const static uint64_t SH_FLD_SLAVE42_RESPONSE_BIT = 15346; // 1 +const static uint64_t SH_FLD_SLAVE43_ERROR_CODE = 15347; // 1 +const static uint64_t SH_FLD_SLAVE43_ERROR_CODE_LEN = 15348; // 1 +const static uint64_t SH_FLD_SLAVE43_RESPONSE_BIT = 15349; // 1 +const static uint64_t SH_FLD_SLAVE44_ERROR_CODE = 15350; // 1 +const static uint64_t SH_FLD_SLAVE44_ERROR_CODE_LEN = 15351; // 1 +const static uint64_t SH_FLD_SLAVE44_RESPONSE_BIT = 15352; // 1 +const static uint64_t SH_FLD_SLAVE45_ERROR_CODE = 15353; // 1 +const static uint64_t SH_FLD_SLAVE45_ERROR_CODE_LEN = 15354; // 1 +const static uint64_t SH_FLD_SLAVE45_RESPONSE_BIT = 15355; // 1 +const static uint64_t SH_FLD_SLAVE46_ERROR_CODE = 15356; // 1 +const static uint64_t SH_FLD_SLAVE46_ERROR_CODE_LEN = 15357; // 1 +const static uint64_t SH_FLD_SLAVE46_RESPONSE_BIT = 15358; // 1 +const static uint64_t SH_FLD_SLAVE47_ERROR_CODE = 15359; // 1 +const static uint64_t SH_FLD_SLAVE47_ERROR_CODE_LEN = 15360; // 1 +const static uint64_t SH_FLD_SLAVE47_RESPONSE_BIT = 15361; // 1 +const static uint64_t SH_FLD_SLAVE48_ERROR_CODE = 15362; // 1 +const static uint64_t SH_FLD_SLAVE48_ERROR_CODE_LEN = 15363; // 1 +const static uint64_t SH_FLD_SLAVE48_RESPONSE_BIT = 15364; // 1 +const static uint64_t SH_FLD_SLAVE49_ERROR_CODE = 15365; // 1 +const static uint64_t SH_FLD_SLAVE49_ERROR_CODE_LEN = 15366; // 1 +const static uint64_t SH_FLD_SLAVE49_RESPONSE_BIT = 15367; // 1 +const static uint64_t SH_FLD_SLAVE4_ERROR_CODE = 15368; // 1 +const static uint64_t SH_FLD_SLAVE4_ERROR_CODE_LEN = 15369; // 1 +const static uint64_t SH_FLD_SLAVE4_RESPONSE_BIT = 15370; // 1 +const static uint64_t SH_FLD_SLAVE50_ERROR_CODE = 15371; // 1 +const static uint64_t SH_FLD_SLAVE50_ERROR_CODE_LEN = 15372; // 1 +const static uint64_t SH_FLD_SLAVE50_RESPONSE_BIT = 15373; // 1 +const static uint64_t SH_FLD_SLAVE51_ERROR_CODE = 15374; // 1 +const static uint64_t SH_FLD_SLAVE51_ERROR_CODE_LEN = 15375; // 1 +const static uint64_t SH_FLD_SLAVE51_RESPONSE_BIT = 15376; // 1 +const static uint64_t SH_FLD_SLAVE52_ERROR_CODE = 15377; // 1 +const static uint64_t SH_FLD_SLAVE52_ERROR_CODE_LEN = 15378; // 1 +const static uint64_t SH_FLD_SLAVE52_RESPONSE_BIT = 15379; // 1 +const static uint64_t SH_FLD_SLAVE53_ERROR_CODE = 15380; // 1 +const static uint64_t SH_FLD_SLAVE53_ERROR_CODE_LEN = 15381; // 1 +const static uint64_t SH_FLD_SLAVE53_RESPONSE_BIT = 15382; // 1 +const static uint64_t SH_FLD_SLAVE54_ERROR_CODE = 15383; // 1 +const static uint64_t SH_FLD_SLAVE54_ERROR_CODE_LEN = 15384; // 1 +const static uint64_t SH_FLD_SLAVE54_RESPONSE_BIT = 15385; // 1 +const static uint64_t SH_FLD_SLAVE55_ERROR_CODE = 15386; // 1 +const static uint64_t SH_FLD_SLAVE55_ERROR_CODE_LEN = 15387; // 1 +const static uint64_t SH_FLD_SLAVE55_RESPONSE_BIT = 15388; // 1 +const static uint64_t SH_FLD_SLAVE56_ERROR_CODE = 15389; // 1 +const static uint64_t SH_FLD_SLAVE56_ERROR_CODE_LEN = 15390; // 1 +const static uint64_t SH_FLD_SLAVE56_RESPONSE_BIT = 15391; // 1 +const static uint64_t SH_FLD_SLAVE57_ERROR_CODE = 15392; // 1 +const static uint64_t SH_FLD_SLAVE57_ERROR_CODE_LEN = 15393; // 1 +const static uint64_t SH_FLD_SLAVE57_RESPONSE_BIT = 15394; // 1 +const static uint64_t SH_FLD_SLAVE58_ERROR_CODE = 15395; // 1 +const static uint64_t SH_FLD_SLAVE58_ERROR_CODE_LEN = 15396; // 1 +const static uint64_t SH_FLD_SLAVE58_RESPONSE_BIT = 15397; // 1 +const static uint64_t SH_FLD_SLAVE59_ERROR_CODE = 15398; // 1 +const static uint64_t SH_FLD_SLAVE59_ERROR_CODE_LEN = 15399; // 1 +const static uint64_t SH_FLD_SLAVE59_RESPONSE_BIT = 15400; // 1 +const static uint64_t SH_FLD_SLAVE5_ERROR_CODE = 15401; // 1 +const static uint64_t SH_FLD_SLAVE5_ERROR_CODE_LEN = 15402; // 1 +const static uint64_t SH_FLD_SLAVE5_RESPONSE_BIT = 15403; // 1 +const static uint64_t SH_FLD_SLAVE60_ERROR_CODE = 15404; // 1 +const static uint64_t SH_FLD_SLAVE60_ERROR_CODE_LEN = 15405; // 1 +const static uint64_t SH_FLD_SLAVE60_RESPONSE_BIT = 15406; // 1 +const static uint64_t SH_FLD_SLAVE61_ERROR_CODE = 15407; // 1 +const static uint64_t SH_FLD_SLAVE61_ERROR_CODE_LEN = 15408; // 1 +const static uint64_t SH_FLD_SLAVE61_RESPONSE_BIT = 15409; // 1 +const static uint64_t SH_FLD_SLAVE62_ERROR_CODE = 15410; // 1 +const static uint64_t SH_FLD_SLAVE62_ERROR_CODE_LEN = 15411; // 1 +const static uint64_t SH_FLD_SLAVE62_RESPONSE_BIT = 15412; // 1 +const static uint64_t SH_FLD_SLAVE63_ERROR_CODE = 15413; // 1 +const static uint64_t SH_FLD_SLAVE63_ERROR_CODE_LEN = 15414; // 1 +const static uint64_t SH_FLD_SLAVE63_RESPONSE_BIT = 15415; // 1 +const static uint64_t SH_FLD_SLAVE6_ERROR_CODE = 15416; // 1 +const static uint64_t SH_FLD_SLAVE6_ERROR_CODE_LEN = 15417; // 1 +const static uint64_t SH_FLD_SLAVE6_RESPONSE_BIT = 15418; // 1 +const static uint64_t SH_FLD_SLAVE7_ERROR_CODE = 15419; // 1 +const static uint64_t SH_FLD_SLAVE7_ERROR_CODE_LEN = 15420; // 1 +const static uint64_t SH_FLD_SLAVE7_RESPONSE_BIT = 15421; // 1 +const static uint64_t SH_FLD_SLAVE8_ERROR_CODE = 15422; // 1 +const static uint64_t SH_FLD_SLAVE8_ERROR_CODE_LEN = 15423; // 1 +const static uint64_t SH_FLD_SLAVE8_RESPONSE_BIT = 15424; // 1 +const static uint64_t SH_FLD_SLAVE9_ERROR_CODE = 15425; // 1 +const static uint64_t SH_FLD_SLAVE9_ERROR_CODE_LEN = 15426; // 1 +const static uint64_t SH_FLD_SLAVE9_RESPONSE_BIT = 15427; // 1 +const static uint64_t SH_FLD_SLAVE_IDLE = 15428; // 1 +const static uint64_t SH_FLD_SLAVE_MODE = 15429; // 43 +const static uint64_t SH_FLD_SLAVE_RESET_TO_405_ENABLE = 15430; // 1 +const static uint64_t SH_FLD_SLBI_GROUP_PUMP_EN = 15431; // 12 +const static uint64_t SH_FLD_SLB_BUS0_STG1_SEL = 15432; // 1 +const static uint64_t SH_FLD_SLB_BUS0_STG2_SEL = 15433; // 1 +const static uint64_t SH_FLD_SLB_BUS1_STG1_SEL = 15434; // 1 +const static uint64_t SH_FLD_SLB_BUS1_STG2_SEL = 15435; // 1 +const static uint64_t SH_FLD_SLEWCTL = 15436; // 1 +const static uint64_t SH_FLD_SLEWCTL_LEN = 15437; // 1 +const static uint64_t SH_FLD_SLEW_DN_SEL = 15438; // 6 +const static uint64_t SH_FLD_SLICE = 15439; // 3 +const static uint64_t SH_FLD_SLICE0_CFG_ECC_CE_ERR = 15440; // 2 +const static uint64_t SH_FLD_SLICE0_CFG_ECC_UE_ERR = 15441; // 2 +const static uint64_t SH_FLD_SLICE1_CFG_ECC_CE_ERR = 15442; // 2 +const static uint64_t SH_FLD_SLICE1_CFG_ECC_UE_ERR = 15443; // 2 +const static uint64_t SH_FLD_SLICE2_CFG_ECC_CE_ERR = 15444; // 2 +const static uint64_t SH_FLD_SLICE2_CFG_ECC_UE_ERR = 15445; // 2 +const static uint64_t SH_FLD_SLICE3_CFG_ECC_CE_ERR = 15446; // 2 +const static uint64_t SH_FLD_SLICE3_CFG_ECC_UE_ERR = 15447; // 2 +const static uint64_t SH_FLD_SLICE_LEN = 15448; // 3 +const static uint64_t SH_FLD_SLOT0_B2_VALID = 15449; // 8 +const static uint64_t SH_FLD_SLOT0_D_VALUE = 15450; // 8 +const static uint64_t SH_FLD_SLOT0_M0_VALID = 15451; // 8 +const static uint64_t SH_FLD_SLOT0_M1_VALID = 15452; // 8 +const static uint64_t SH_FLD_SLOT0_ROW15_VALID = 15453; // 8 +const static uint64_t SH_FLD_SLOT0_ROW16_VALID = 15454; // 8 +const static uint64_t SH_FLD_SLOT0_ROW17_VALID = 15455; // 8 +const static uint64_t SH_FLD_SLOT0_S0_VALID = 15456; // 8 +const static uint64_t SH_FLD_SLOT0_S1_VALID = 15457; // 8 +const static uint64_t SH_FLD_SLOT0_S2_VALID = 15458; // 8 +const static uint64_t SH_FLD_SLOT0_VALID = 15459; // 8 +const static uint64_t SH_FLD_SLOT1_B2_VALID = 15460; // 8 +const static uint64_t SH_FLD_SLOT1_D_VALUE = 15461; // 8 +const static uint64_t SH_FLD_SLOT1_M0_VALID = 15462; // 8 +const static uint64_t SH_FLD_SLOT1_M1_VALID = 15463; // 8 +const static uint64_t SH_FLD_SLOT1_ROW15_VALID = 15464; // 8 +const static uint64_t SH_FLD_SLOT1_ROW16_VALID = 15465; // 8 +const static uint64_t SH_FLD_SLOT1_ROW17_VALID = 15466; // 8 +const static uint64_t SH_FLD_SLOT1_S0_VALID = 15467; // 8 +const static uint64_t SH_FLD_SLOT1_S1_VALID = 15468; // 8 +const static uint64_t SH_FLD_SLOT1_S2_VALID = 15469; // 8 +const static uint64_t SH_FLD_SLOT1_VALID = 15470; // 8 +const static uint64_t SH_FLD_SLOW_CMD_RATE = 15471; // 1 +const static uint64_t SH_FLD_SLOW_TO_MODE = 15472; // 86 +const static uint64_t SH_FLD_SLS_CMD_GCRMSG = 15473; // 4 +const static uint64_t SH_FLD_SLS_CMD_GCRMSG_LEN = 15474; // 4 +const static uint64_t SH_FLD_SLS_CNTR_TAP_PTS = 15475; // 4 +const static uint64_t SH_FLD_SLS_CNTR_TAP_PTS_LEN = 15476; // 4 +const static uint64_t SH_FLD_SLS_DISABLE = 15477; // 4 +const static uint64_t SH_FLD_SLS_EXCEPTION2_CS = 15478; // 4 +const static uint64_t SH_FLD_SLS_EXTEND_SEL = 15479; // 4 +const static uint64_t SH_FLD_SLS_EXTEND_SEL_LEN = 15480; // 4 +const static uint64_t SH_FLD_SLS_LANE_GCRMSG = 15481; // 4 +const static uint64_t SH_FLD_SLS_LANE_GCRMSG_LEN = 15482; // 4 +const static uint64_t SH_FLD_SLS_LANE_SEL_LG_GCRMSG = 15483; // 4 +const static uint64_t SH_FLD_SLS_LANE_SHDW_GCRMSG = 15484; // 4 +const static uint64_t SH_FLD_SLS_LANE_UNSEL_LG_GCRMSG = 15485; // 4 +const static uint64_t SH_FLD_SLS_LANE_VAL_GCRMSG = 15486; // 4 +const static uint64_t SH_FLD_SLS_SCRAMBLE_MODE = 15487; // 4 +const static uint64_t SH_FLD_SLS_SCRAMBLE_MODE_LEN = 15488; // 4 +const static uint64_t SH_FLD_SLS_TIMEOUT_SEL = 15489; // 4 +const static uint64_t SH_FLD_SLS_TIMEOUT_SEL_LEN = 15490; // 4 +const static uint64_t SH_FLD_SLV_DIS_ABUSPAR = 15491; // 1 +const static uint64_t SH_FLD_SLV_DIS_BE = 15492; // 1 +const static uint64_t SH_FLD_SLV_DIS_BEPAR = 15493; // 1 +const static uint64_t SH_FLD_SLV_DIS_RDDBUSPAREN = 15494; // 1 +const static uint64_t SH_FLD_SLV_DIS_SACK = 15495; // 1 +const static uint64_t SH_FLD_SLV_DIS_WRDBUSPAR = 15496; // 1 +const static uint64_t SH_FLD_SLV_EVENT_MUX = 15497; // 1 +const static uint64_t SH_FLD_SLV_EVENT_MUX_LEN = 15498; // 1 +const static uint64_t SH_FLD_SLV_LGL_RPR_REQ_GCRMSG = 15499; // 4 +const static uint64_t SH_FLD_SLV_MV_SLS_RPR_REQ_GCRMSG = 15500; // 4 +const static uint64_t SH_FLD_SLV_MV_SLS_SHDW_REQ_GCRMSG = 15501; // 4 +const static uint64_t SH_FLD_SLV_MV_SLS_SHDW_RPR_REQ_GCRMSG = 15502; // 4 +const static uint64_t SH_FLD_SLV_MV_SLS_UNSHDW_REQ_GCRMSG = 15503; // 4 +const static uint64_t SH_FLD_SLV_MV_SLS_UNSHDW_RPR_REQ_GCRMSG = 15504; // 4 +const static uint64_t SH_FLD_SLV_RECAL_ABORT_ACK_FIN_GCRMSG = 15505; // 4 +const static uint64_t SH_FLD_SLV_RECAL_ABORT_MNOP_FIN_GCRMSG = 15506; // 4 +const static uint64_t SH_FLD_SLV_RECAL_ABORT_SNOP_FIN_GCRMSG = 15507; // 4 +const static uint64_t SH_FLD_SLV_RECAL_DONE_NOP_FIN_GCRMSG = 15508; // 4 +const static uint64_t SH_FLD_SLV_RECAL_FAIL_NOP_FIN_GCRMSG = 15509; // 4 +const static uint64_t SH_FLD_SLV_RECAL_FRESULTS_FIN_GCRMSG = 15510; // 4 +const static uint64_t SH_FLD_SLV_SHDW_DONE_FIN_GCRMSG = 15511; // 4 +const static uint64_t SH_FLD_SLV_SHDW_NOP_FIN_GCRMSG = 15512; // 4 +const static uint64_t SH_FLD_SLV_SHDW_RPR_DONE_FIN_GCRMSG = 15513; // 4 +const static uint64_t SH_FLD_SLV_SHDW_RPR_NOP_FIN_GCRMSG = 15514; // 4 +const static uint64_t SH_FLD_SLV_SPARE = 15515; // 1 +const static uint64_t SH_FLD_SLV_UNSHDW_DONE_FIN_GCRMSG = 15516; // 4 +const static uint64_t SH_FLD_SLV_UNSHDW_NOP_FIN_GCRMSG = 15517; // 4 +const static uint64_t SH_FLD_SLV_UNSHDW_RPR_DONE_FIN_GCRMSG = 15518; // 4 +const static uint64_t SH_FLD_SLV_UNSHDW_RPR_NOP_FIN_GCRMSG = 15519; // 4 +const static uint64_t SH_FLD_SMALL_STEP = 15520; // 8 +const static uint64_t SH_FLD_SMALL_STEP_LEN = 15521; // 8 +const static uint64_t SH_FLD_SMASK_IN0 = 15522; // 43 +const static uint64_t SH_FLD_SMASK_IN1 = 15523; // 43 +const static uint64_t SH_FLD_SMASK_IN2 = 15524; // 43 +const static uint64_t SH_FLD_SMASK_IN3 = 15525; // 43 +const static uint64_t SH_FLD_SMASK_IN4 = 15526; // 43 +const static uint64_t SH_FLD_SM_1HOT_ERR = 15527; // 16 +const static uint64_t SH_FLD_SM_MMIO0 = 15528; // 3 +const static uint64_t SH_FLD_SM_MMIO1 = 15529; // 3 +const static uint64_t SH_FLD_SM_MMIO2 = 15530; // 3 +const static uint64_t SH_FLD_SM_MMIO3 = 15531; // 3 +const static uint64_t SH_FLD_SM_OR_CASE = 15532; // 2 +const static uint64_t SH_FLD_SM_RESET = 15533; // 1 +const static uint64_t SH_FLD_SN0_CRESP_ATAG_P = 15534; // 12 +const static uint64_t SH_FLD_SN0_CRESP_TTAG_P = 15535; // 12 +const static uint64_t SH_FLD_SN0_RCMD_ADDR_P = 15536; // 12 +const static uint64_t SH_FLD_SN0_RCMD_TTAG_P = 15537; // 12 +const static uint64_t SH_FLD_SN1_CRESP_ATAG_P = 15538; // 12 +const static uint64_t SH_FLD_SN1_CRESP_TTAG_P = 15539; // 12 +const static uint64_t SH_FLD_SN1_RCMD_ADDR_P = 15540; // 12 +const static uint64_t SH_FLD_SN1_RCMD_TTAG_P = 15541; // 12 +const static uint64_t SH_FLD_SN2_CRESP_ATAG_P = 15542; // 12 +const static uint64_t SH_FLD_SN2_CRESP_TTAG_P = 15543; // 12 +const static uint64_t SH_FLD_SN2_RCMD_ADDR_P = 15544; // 12 +const static uint64_t SH_FLD_SN2_RCMD_TTAG_P = 15545; // 12 +const static uint64_t SH_FLD_SN3_CRESP_ATAG_P = 15546; // 12 +const static uint64_t SH_FLD_SN3_CRESP_TTAG_P = 15547; // 12 +const static uint64_t SH_FLD_SN3_RCMD_ADDR_P = 15548; // 12 +const static uint64_t SH_FLD_SN3_RCMD_TTAG_P = 15549; // 12 +const static uint64_t SH_FLD_SND_CHIPID = 15550; // 1 +const static uint64_t SH_FLD_SND_CHIPID_LEN = 15551; // 1 +const static uint64_t SH_FLD_SND_CNT = 15552; // 1 +const static uint64_t SH_FLD_SND_CNT_LEN = 15553; // 1 +const static uint64_t SH_FLD_SND_CNT_STATUS = 15554; // 1 +const static uint64_t SH_FLD_SND_CNT_STATUS_LEN = 15555; // 1 +const static uint64_t SH_FLD_SND_ERROR = 15556; // 1 +const static uint64_t SH_FLD_SND_GROUPID = 15557; // 1 +const static uint64_t SH_FLD_SND_GROUPID_LEN = 15558; // 1 +const static uint64_t SH_FLD_SND_IN_PROGRESS = 15559; // 1 +const static uint64_t SH_FLD_SND_PHASE_STATUS = 15560; // 1 +const static uint64_t SH_FLD_SND_PHASE_STATUS_LEN = 15561; // 1 +const static uint64_t SH_FLD_SND_QID = 15562; // 1 +const static uint64_t SH_FLD_SND_RESERVATION = 15563; // 1 +const static uint64_t SH_FLD_SND_RESET = 15564; // 1 +const static uint64_t SH_FLD_SND_RETRY_COUNT = 15565; // 1 +const static uint64_t SH_FLD_SND_RETRY_COUNT_LEN = 15566; // 1 +const static uint64_t SH_FLD_SND_RETRY_COUNT_OVERCOM = 15567; // 1 +const static uint64_t SH_FLD_SND_RETRY_THRESH = 15568; // 1 +const static uint64_t SH_FLD_SND_RETRY_THRESH_LEN = 15569; // 1 +const static uint64_t SH_FLD_SND_RSVTO_DIV = 15570; // 1 +const static uint64_t SH_FLD_SND_RSVTO_DIV_LEN = 15571; // 1 +const static uint64_t SH_FLD_SND_SCOPE = 15572; // 1 +const static uint64_t SH_FLD_SND_SCOPE_LEN = 15573; // 1 +const static uint64_t SH_FLD_SND_SLS_CMD_GCRMSG = 15574; // 4 +const static uint64_t SH_FLD_SND_SLS_CMD_PREV_GCRMSG = 15575; // 4 +const static uint64_t SH_FLD_SND_SLS_USING_REG_SCRAMBLE = 15576; // 4 +const static uint64_t SH_FLD_SND_STOP = 15577; // 1 +const static uint64_t SH_FLD_SND_TYPE = 15578; // 1 +const static uint64_t SH_FLD_SNFSM_ADDR = 15579; // 12 +const static uint64_t SH_FLD_SNGL_THD_EN = 15580; // 2 +const static uint64_t SH_FLD_SNOOPER_RECOVERABLE_ERROR = 15581; // 4 +const static uint64_t SH_FLD_SNOOPER_SYS_XSTOP_ERROR = 15582; // 4 +const static uint64_t SH_FLD_SNOOP_ARRAY_CE = 15583; // 4 +const static uint64_t SH_FLD_SNOOP_ARRAY_UE = 15584; // 4 +const static uint64_t SH_FLD_SNOOP_DIS = 15585; // 8 +const static uint64_t SH_FLD_SNOP = 15586; // 43 +const static uint64_t SH_FLD_SNOP_FORCE_SG = 15587; // 43 +const static uint64_t SH_FLD_SNOP_LEN = 15588; // 43 +const static uint64_t SH_FLD_SNOP_WAIT = 15589; // 43 +const static uint64_t SH_FLD_SNOP_WAIT_LEN = 15590; // 43 +const static uint64_t SH_FLD_SNP_REG_ERR0 = 15591; // 1 +const static uint64_t SH_FLD_SNP_REG_ERR1 = 15592; // 1 +const static uint64_t SH_FLD_SNP_REG_ERR2 = 15593; // 1 +const static uint64_t SH_FLD_SNP_REG_ERR3 = 15594; // 1 +const static uint64_t SH_FLD_SNP_REG_ERR4 = 15595; // 1 +const static uint64_t SH_FLD_SNP_REG_ERR5 = 15596; // 1 +const static uint64_t SH_FLD_SNP_REG_ERR6 = 15597; // 1 +const static uint64_t SH_FLD_SNS1_UNUSED_0_31 = 15598; // 1 +const static uint64_t SH_FLD_SNS1_UNUSED_0_31_LEN = 15599; // 1 +const static uint64_t SH_FLD_SNS2_UNUSED_0_31 = 15600; // 1 +const static uint64_t SH_FLD_SNS2_UNUSED_0_31_LEN = 15601; // 1 +const static uint64_t SH_FLD_SN_CRESP_ACK_DEAD = 15602; // 12 +const static uint64_t SH_FLD_SN_MACHINE_HANG = 15603; // 12 +const static uint64_t SH_FLD_SN_MSG_MAX_CREDIT = 15604; // 2 +const static uint64_t SH_FLD_SN_MSG_MAX_CREDIT_LEN = 15605; // 2 +const static uint64_t SH_FLD_SN_UNSOLICITED_CRESP = 15606; // 12 +const static uint64_t SH_FLD_SN_WRT_DBUF_MAX_CREDIT = 15607; // 2 +const static uint64_t SH_FLD_SN_WRT_DBUF_MAX_CREDIT_LEN = 15608; // 2 +const static uint64_t SH_FLD_SOCKET = 15609; // 1 +const static uint64_t SH_FLD_SOCKET_LEN = 15610; // 1 +const static uint64_t SH_FLD_SOFT_CE_COUNT = 15611; // 2 +const static uint64_t SH_FLD_SOFT_CE_COUNT_LEN = 15612; // 2 +const static uint64_t SH_FLD_SOFT_MCE_COUNT = 15613; // 2 +const static uint64_t SH_FLD_SOFT_MCE_COUNT_LEN = 15614; // 2 +const static uint64_t SH_FLD_SOFT_NCE_ETE_ATTN = 15615; // 2 +const static uint64_t SH_FLD_SOURCE_SELECT = 15616; // 43 +const static uint64_t SH_FLD_SOURCE_SELECT_LEN = 15617; // 43 +const static uint64_t SH_FLD_SOURCE_SUBUNIT_0_1 = 15618; // 1 +const static uint64_t SH_FLD_SOURCE_SUBUNIT_0_1_LEN = 15619; // 1 +const static uint64_t SH_FLD_SOUTH_CTL_CQ_IDLE_BIT = 15620; // 1 +const static uint64_t SH_FLD_SOUTH_CTL_DISABLE_WC_ECC = 15621; // 1 +const static uint64_t SH_FLD_SOUTH_CTL_DISABLE_WC_SCRUB = 15622; // 1 +const static uint64_t SH_FLD_SOUTH_CTL_DIS_SIMULT_RD_WR = 15623; // 1 +const static uint64_t SH_FLD_SOUTH_CTL_EG_IDLE_BIT = 15624; // 1 +const static uint64_t SH_FLD_SOUTH_CTL_EG_SINGLE_THREAD = 15625; // 1 +const static uint64_t SH_FLD_SOUTH_CTL_EG_STAMP_DEBUG = 15626; // 1 +const static uint64_t SH_FLD_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE = 15627; // 1 +const static uint64_t SH_FLD_SOUTH_CTL_ENA_NOTIFY_ORDER = 15628; // 1 +const static uint64_t SH_FLD_SOUTH_CTL_EN_FAST_SCRUB = 15629; // 1 +const static uint64_t SH_FLD_SOUTH_CTL_UNUSED = 15630; // 1 +const static uint64_t SH_FLD_SOUTH_CTL_UNUSED_LEN = 15631; // 1 +const static uint64_t SH_FLD_SOUTH_CTL_WC_IDLE_BIT = 15632; // 1 +const static uint64_t SH_FLD_SPAM_EN = 15633; // 8 +const static uint64_t SH_FLD_SPARE = 15634; // 74 +const static uint64_t SH_FLD_SPARE0 = 15635; // 105 +const static uint64_t SH_FLD_SPARE0_LEN = 15636; // 8 +const static uint64_t SH_FLD_SPARE1 = 15637; // 5 +const static uint64_t SH_FLD_SPARE10 = 15638; // 1 +const static uint64_t SH_FLD_SPARE11 = 15639; // 13 +const static uint64_t SH_FLD_SPARE13 = 15640; // 1 +const static uint64_t SH_FLD_SPARE14 = 15641; // 1 +const static uint64_t SH_FLD_SPARE15 = 15642; // 1 +const static uint64_t SH_FLD_SPARE2 = 15643; // 4 +const static uint64_t SH_FLD_SPARE3 = 15644; // 1 +const static uint64_t SH_FLD_SPARE4_TIMEOUT = 15645; // 6 +const static uint64_t SH_FLD_SPARE4_TIMEOUT_LEN = 15646; // 6 +const static uint64_t SH_FLD_SPARE7 = 15647; // 1 +const static uint64_t SH_FLD_SPARE8 = 15648; // 1 +const static uint64_t SH_FLD_SPARE9 = 15649; // 1 +const static uint64_t SH_FLD_SPARES = 15650; // 7 +const static uint64_t SH_FLD_SPARES_LEN = 15651; // 7 +const static uint64_t SH_FLD_SPARE_0 = 15652; // 4 +const static uint64_t SH_FLD_SPARE_0_LEN = 15653; // 4 +const static uint64_t SH_FLD_SPARE_10 = 15654; // 2 +const static uint64_t SH_FLD_SPARE_11 = 15655; // 4 +const static uint64_t SH_FLD_SPARE_12 = 15656; // 4 +const static uint64_t SH_FLD_SPARE_13 = 15657; // 4 +const static uint64_t SH_FLD_SPARE_14 = 15658; // 4 +const static uint64_t SH_FLD_SPARE_15 = 15659; // 16 +const static uint64_t SH_FLD_SPARE_16 = 15660; // 14 +const static uint64_t SH_FLD_SPARE_17 = 15661; // 14 +const static uint64_t SH_FLD_SPARE_18 = 15662; // 2 +const static uint64_t SH_FLD_SPARE_18_19 = 15663; // 6 +const static uint64_t SH_FLD_SPARE_18_19_LEN = 15664; // 6 +const static uint64_t SH_FLD_SPARE_19 = 15665; // 4 +const static uint64_t SH_FLD_SPARE_1_3 = 15666; // 1 +const static uint64_t SH_FLD_SPARE_1_3_LEN = 15667; // 1 +const static uint64_t SH_FLD_SPARE_2 = 15668; // 4 +const static uint64_t SH_FLD_SPARE_20 = 15669; // 4 +const static uint64_t SH_FLD_SPARE_21 = 15670; // 4 +const static uint64_t SH_FLD_SPARE_22 = 15671; // 4 +const static uint64_t SH_FLD_SPARE_22_23 = 15672; // 12 +const static uint64_t SH_FLD_SPARE_22_23_LEN = 15673; // 12 +const static uint64_t SH_FLD_SPARE_23 = 15674; // 4 +const static uint64_t SH_FLD_SPARE_24 = 15675; // 4 +const static uint64_t SH_FLD_SPARE_24_31 = 15676; // 1 +const static uint64_t SH_FLD_SPARE_24_31_LEN = 15677; // 1 +const static uint64_t SH_FLD_SPARE_25 = 15678; // 4 +const static uint64_t SH_FLD_SPARE_26 = 15679; // 4 +const static uint64_t SH_FLD_SPARE_27 = 15680; // 4 +const static uint64_t SH_FLD_SPARE_28 = 15681; // 4 +const static uint64_t SH_FLD_SPARE_29 = 15682; // 4 +const static uint64_t SH_FLD_SPARE_2_MASK = 15683; // 1 +const static uint64_t SH_FLD_SPARE_3 = 15684; // 6 +const static uint64_t SH_FLD_SPARE_30 = 15685; // 4 +const static uint64_t SH_FLD_SPARE_31 = 15686; // 5 +const static uint64_t SH_FLD_SPARE_32_33 = 15687; // 12 +const static uint64_t SH_FLD_SPARE_32_33_LEN = 15688; // 12 +const static uint64_t SH_FLD_SPARE_38_39 = 15689; // 12 +const static uint64_t SH_FLD_SPARE_38_39_LEN = 15690; // 12 +const static uint64_t SH_FLD_SPARE_3_MASK = 15691; // 1 +const static uint64_t SH_FLD_SPARE_58 = 15692; // 4 +const static uint64_t SH_FLD_SPARE_58_61 = 15693; // 2 +const static uint64_t SH_FLD_SPARE_58_61_LEN = 15694; // 1 +const static uint64_t SH_FLD_SPARE_58_61_MASK = 15695; // 1 +const static uint64_t SH_FLD_SPARE_58_61_MASK_LEN = 15696; // 1 +const static uint64_t SH_FLD_SPARE_59 = 15697; // 4 +const static uint64_t SH_FLD_SPARE_60 = 15698; // 4 +const static uint64_t SH_FLD_SPARE_61 = 15699; // 4 +const static uint64_t SH_FLD_SPARE_63 = 15700; // 3 +const static uint64_t SH_FLD_SPARE_6_7 = 15701; // 16 +const static uint64_t SH_FLD_SPARE_6_7_LEN = 15702; // 16 +const static uint64_t SH_FLD_SPARE_7 = 15703; // 12 +const static uint64_t SH_FLD_SPARE_8 = 15704; // 2 +const static uint64_t SH_FLD_SPARE_9 = 15705; // 2 +const static uint64_t SH_FLD_SPARE_DI_CONTROL = 15706; // 3 +const static uint64_t SH_FLD_SPARE_ERR_38 = 15707; // 1 +const static uint64_t SH_FLD_SPARE_ERR_38_MASK = 15708; // 1 +const static uint64_t SH_FLD_SPARE_FENCE_CONTROL = 15709; // 3 +const static uint64_t SH_FLD_SPARE_FILT0_PLL = 15710; // 3 +const static uint64_t SH_FLD_SPARE_FILT1_PLL = 15711; // 3 +const static uint64_t SH_FLD_SPARE_LEN = 15712; // 57 +const static uint64_t SH_FLD_SPARE_MODE_0 = 15713; // 116 +const static uint64_t SH_FLD_SPARE_MODE_1 = 15714; // 116 +const static uint64_t SH_FLD_SPARE_MODE_2 = 15715; // 116 +const static uint64_t SH_FLD_SPARE_MODE_3 = 15716; // 116 +const static uint64_t SH_FLD_SPARE_N = 15717; // 2 +const static uint64_t SH_FLD_SPARE_N_LEN = 15718; // 2 +const static uint64_t SH_FLD_SPARE_PIB_CONTROL = 15719; // 3 +const static uint64_t SH_FLD_SPARE_RI_CONTROL = 15720; // 3 +const static uint64_t SH_FLD_SPECIAL_ATTENTION = 15721; // 1 +const static uint64_t SH_FLD_SPECIAL_WAKEUP_C0 = 15722; // 24 +const static uint64_t SH_FLD_SPECIAL_WAKEUP_C1 = 15723; // 24 +const static uint64_t SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL = 15724; // 12 +const static uint64_t SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL = 15725; // 12 +const static uint64_t SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE = 15726; // 12 +const static uint64_t SH_FLD_SPECIAL_WKUP_DONE_C0 = 15727; // 12 +const static uint64_t SH_FLD_SPECIAL_WKUP_DONE_C1 = 15728; // 12 +const static uint64_t SH_FLD_SPECIAL_WKUP_PROTOCOL = 15729; // 30 +const static uint64_t SH_FLD_SPECULATIVE_CHECKIN_COUNT = 15730; // 1 +const static uint64_t SH_FLD_SPECULATIVE_CHECKIN_COUNT_LEN = 15731; // 1 +const static uint64_t SH_FLD_SPEC_CILD_G = 15732; // 1 +const static uint64_t SH_FLD_SPEC_HPC_DIR_STATE = 15733; // 2 +const static uint64_t SH_FLD_SPEC_HPC_DIR_STATE_LEN = 15734; // 2 +const static uint64_t SH_FLD_SPEC_READ_FILTER_NO_HASH_MODE = 15735; // 4 +const static uint64_t SH_FLD_SPEDIV = 15736; // 20 +const static uint64_t SH_FLD_SPEDIV_LEN = 15737; // 20 +const static uint64_t SH_FLD_SPIPSS_ERROR = 15738; // 1 +const static uint64_t SH_FLD_SPLURGE = 15739; // 1 +const static uint64_t SH_FLD_SPRG0 = 15740; // 21 +const static uint64_t SH_FLD_SPRG0_LEN = 15741; // 21 +const static uint64_t SH_FLD_SPR_LNS_PDWN_LITE_GCRMSG = 15742; // 4 +const static uint64_t SH_FLD_SP_COUNT_LT = 15743; // 86 +const static uint64_t SH_FLD_SP_COUNT_LT_LEN = 15744; // 86 +const static uint64_t SH_FLD_SQ_LFSR_CNTL = 15745; // 8 +const static uint64_t SH_FLD_SQ_LFSR_CNTL_LEN = 15746; // 8 +const static uint64_t SH_FLD_SR = 15747; // 8 +const static uint64_t SH_FLD_SRAM_ABIST_DONE_DC = 15748; // 43 +const static uint64_t SH_FLD_SRAM_ACCESS_MODE = 15749; // 16 +const static uint64_t SH_FLD_SRAM_ADDRESS = 15750; // 16 +const static uint64_t SH_FLD_SRAM_ADDRESS_LEN = 15751; // 16 +const static uint64_t SH_FLD_SRAM_CE = 15752; // 12 +const static uint64_t SH_FLD_SRAM_CERRRPT = 15753; // 1 +const static uint64_t SH_FLD_SRAM_CERRRPT_LEN = 15754; // 1 +const static uint64_t SH_FLD_SRAM_DATA = 15755; // 16 +const static uint64_t SH_FLD_SRAM_DATA_LEN = 15756; // 16 +const static uint64_t SH_FLD_SRAM_HIGH_PRIORITY = 15757; // 4 +const static uint64_t SH_FLD_SRAM_HIGH_PRIORITY_LEN = 15758; // 4 +const static uint64_t SH_FLD_SRAM_LOW_PRIORITY = 15759; // 4 +const static uint64_t SH_FLD_SRAM_LOW_PRIORITY_LEN = 15760; // 4 +const static uint64_t SH_FLD_SRAM_SCRUB_ENABLE = 15761; // 16 +const static uint64_t SH_FLD_SRAM_SCRUB_ERR = 15762; // 12 +const static uint64_t SH_FLD_SRAM_SCRUB_INDEX = 15763; // 16 +const static uint64_t SH_FLD_SRAM_SCRUB_INDEX_LEN = 15764; // 16 +const static uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR0 = 15765; // 1 +const static uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR0_MASK = 15766; // 1 +const static uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR1 = 15767; // 1 +const static uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR1_MASK = 15768; // 1 +const static uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR2 = 15769; // 1 +const static uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR2_MASK = 15770; // 1 +const static uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR3 = 15771; // 1 +const static uint64_t SH_FLD_SRAM_SPARE_DIRECT_ERROR3_MASK = 15772; // 1 +const static uint64_t SH_FLD_SRAM_UE = 15773; // 12 +const static uint64_t SH_FLD_SRC_BUS = 15774; // 24 +const static uint64_t SH_FLD_SRC_BUS_LEN = 15775; // 24 +const static uint64_t SH_FLD_SRC_DDE = 15776; // 3 +const static uint64_t SH_FLD_SRC_DDE_LEN = 15777; // 3 +const static uint64_t SH_FLD_SRC_SEL_EQ1_ERR = 15778; // 1 +const static uint64_t SH_FLD_SRQ_CCS_UNEXPECTED_PORT_ACTIVE_HOLD_OUT = 15779; // 2 +const static uint64_t SH_FLD_SRQ_MCBIST_OUT_OF_SYNC_HOLD_OUT = 15780; // 2 +const static uint64_t SH_FLD_SRT_CE = 15781; // 1 +const static uint64_t SH_FLD_SRT_CE_MASK = 15782; // 1 +const static uint64_t SH_FLD_SRT_DATAOUT_PERR = 15783; // 1 +const static uint64_t SH_FLD_SRT_DATAOUT_PERR_MASK = 15784; // 1 +const static uint64_t SH_FLD_SRT_ERROR = 15785; // 1 +const static uint64_t SH_FLD_SRT_FSM_ERR = 15786; // 1 +const static uint64_t SH_FLD_SRT_FSM_ERR_MASK = 15787; // 1 +const static uint64_t SH_FLD_SRT_OCI_ADDR_PARITY_ERR = 15788; // 1 +const static uint64_t SH_FLD_SRT_OCI_ADDR_PARITY_ERR_MASK = 15789; // 1 +const static uint64_t SH_FLD_SRT_OCI_BE_PARITY_ERR = 15790; // 1 +const static uint64_t SH_FLD_SRT_OCI_BE_PARITY_ERR_MASK = 15791; // 1 +const static uint64_t SH_FLD_SRT_OCI_WRITE_DATA_PARITY = 15792; // 1 +const static uint64_t SH_FLD_SRT_OCI_WRITE_DATA_PARITY_MASK = 15793; // 1 +const static uint64_t SH_FLD_SRT_READ_ERROR = 15794; // 1 +const static uint64_t SH_FLD_SRT_READ_ERROR_MASK = 15795; // 1 +const static uint64_t SH_FLD_SRT_UE = 15796; // 1 +const static uint64_t SH_FLD_SRT_UE_MASK = 15797; // 1 +const static uint64_t SH_FLD_SRT_WRITE_ERROR = 15798; // 1 +const static uint64_t SH_FLD_SRT_WRITE_ERROR_MASK = 15799; // 1 +const static uint64_t SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL = 15800; // 4 +const static uint64_t SH_FLD_SR_FINAL_NOP_TIMEOUT_SEL_LEN = 15801; // 4 +const static uint64_t SH_FLD_SR_LEN = 15802; // 8 +const static uint64_t SH_FLD_SSCGEN = 15803; // 3 +const static uint64_t SH_FLD_SS_ENABLE = 15804; // 6 +const static uint64_t SH_FLD_ST2_RESET_PERIOD = 15805; // 1 +const static uint64_t SH_FLD_ST2_RESET_PERIOD_LEN = 15806; // 1 +const static uint64_t SH_FLD_STACK = 15807; // 16 +const static uint64_t SH_FLD_STACK_LEN = 15808; // 16 +const static uint64_t SH_FLD_STACK_SCOM_ERR0 = 15809; // 9 +const static uint64_t SH_FLD_STACK_SCOM_ERR0_MASK = 15810; // 9 +const static uint64_t SH_FLD_STACK_SCOM_ERR1 = 15811; // 9 +const static uint64_t SH_FLD_STACK_SCOM_ERR1_MASK = 15812; // 9 +const static uint64_t SH_FLD_STAGGERED_PATTERN = 15813; // 8 +const static uint64_t SH_FLD_START = 15814; // 23 +const static uint64_t SH_FLD_START0 = 15815; // 5 +const static uint64_t SH_FLD_START1 = 15816; // 5 +const static uint64_t SH_FLD_STARTING_ADDRESS = 15817; // 4 +const static uint64_t SH_FLD_STARTING_ADDRESS_LEN = 15818; // 4 +const static uint64_t SH_FLD_STARTS_BIST = 15819; // 43 +const static uint64_t SH_FLD_START_BOOT_SEQUENCER = 15820; // 1 +const static uint64_t SH_FLD_START_DC_CALIBRATE = 15821; // 4 +const static uint64_t SH_FLD_START_DESKEW = 15822; // 4 +const static uint64_t SH_FLD_START_EYE_OPT = 15823; // 4 +const static uint64_t SH_FLD_START_FUNC_MODE = 15824; // 4 +const static uint64_t SH_FLD_START_INIT = 15825; // 8 +const static uint64_t SH_FLD_START_JTAG_CMD = 15826; // 1 +const static uint64_t SH_FLD_START_LANE_ID = 15827; // 8 +const static uint64_t SH_FLD_START_LANE_ID_LEN = 15828; // 8 +const static uint64_t SH_FLD_START_PPE_ADDR = 15829; // 4 +const static uint64_t SH_FLD_START_PPE_ADDR_LEN = 15830; // 4 +const static uint64_t SH_FLD_START_READ = 15831; // 1 +const static uint64_t SH_FLD_START_REPAIR = 15832; // 4 +const static uint64_t SH_FLD_START_RESTART_VECTOR0 = 15833; // 1 +const static uint64_t SH_FLD_START_RESTART_VECTOR1 = 15834; // 1 +const static uint64_t SH_FLD_START_SEEPROM_ADDRESS = 15835; // 4 +const static uint64_t SH_FLD_START_SEEPROM_ADDRESS_LEN = 15836; // 4 +const static uint64_t SH_FLD_START_WIRETEST = 15837; // 4 +const static uint64_t SH_FLD_START_WRITE = 15838; // 1 +const static uint64_t SH_FLD_START_WR_ADDR = 15839; // 2 +const static uint64_t SH_FLD_START_WR_ADDR_LEN = 15840; // 2 +const static uint64_t SH_FLD_STAT = 15841; // 2 +const static uint64_t SH_FLD_STATE = 15842; // 44 +const static uint64_t SH_FLD_STATE_LEN = 15843; // 43 +const static uint64_t SH_FLD_STATE_LOSS_ENABLE_A_N = 15844; // 96 +const static uint64_t SH_FLD_STATE_MACHINE_TRANSITION_DELAY = 15845; // 1 +const static uint64_t SH_FLD_STATE_MACHINE_TRANSITION_DELAY_LEN = 15846; // 1 +const static uint64_t SH_FLD_STATIC_MAX_SPARES_EXCEEDED = 15847; // 8 +const static uint64_t SH_FLD_STATIC_SPARE_DEPLOYED = 15848; // 8 +const static uint64_t SH_FLD_STATUS = 15849; // 3 +const static uint64_t SH_FLD_STATUS_INVALID_CRESP = 15850; // 2 +const static uint64_t SH_FLD_STATUS_PARITY_ERROR = 15851; // 2 +const static uint64_t SH_FLD_STATUS_PERV = 15852; // 129 +const static uint64_t SH_FLD_STATUS_REC_DROPPED_Q = 15853; // 26 +const static uint64_t SH_FLD_STATUS_REG = 15854; // 1 +const static uint64_t SH_FLD_STATUS_REG_LEN = 15855; // 1 +const static uint64_t SH_FLD_STATUS_SCOM_ERROR = 15856; // 26 +const static uint64_t SH_FLD_STATUS_TRIG_DROPPED_Q = 15857; // 26 +const static uint64_t SH_FLD_STATUS_UNIT1 = 15858; // 129 +const static uint64_t SH_FLD_STATUS_UNIT10 = 15859; // 129 +const static uint64_t SH_FLD_STATUS_UNIT2 = 15860; // 129 +const static uint64_t SH_FLD_STATUS_UNIT3 = 15861; // 129 +const static uint64_t SH_FLD_STATUS_UNIT4 = 15862; // 129 +const static uint64_t SH_FLD_STATUS_UNIT5 = 15863; // 129 +const static uint64_t SH_FLD_STATUS_UNIT6 = 15864; // 129 +const static uint64_t SH_FLD_STATUS_UNIT7 = 15865; // 129 +const static uint64_t SH_FLD_STATUS_UNIT8 = 15866; // 129 +const static uint64_t SH_FLD_STATUS_UNIT9 = 15867; // 129 +const static uint64_t SH_FLD_STATUS_UNUSED = 15868; // 24 +const static uint64_t SH_FLD_STATUS_UNUSED_LEN = 15869; // 24 +const static uint64_t SH_FLD_STAT_LEN = 15870; // 2 +const static uint64_t SH_FLD_STEP_CHECK_CONSTANT_CPS_ENABLE = 15871; // 1 +const static uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION = 15872; // 1 +const static uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR = 15873; // 3 +const static uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN = 15874; // 3 +const static uint64_t SH_FLD_STEP_CHECK_CPS_DEVIATION_LEN = 15875; // 1 +const static uint64_t SH_FLD_STEP_CHECK_ENABLE_CHICKEN_SWITCH = 15876; // 1 +const static uint64_t SH_FLD_STEP_CHECK_STEP_SELECT = 15877; // 1 +const static uint64_t SH_FLD_STEP_CHECK_VALIDITY_COUNT = 15878; // 1 +const static uint64_t SH_FLD_STEP_CHECK_VALIDITY_COUNT_LEN = 15879; // 1 +const static uint64_t SH_FLD_STEP_CREATE_DUAL_EDGE_DISABLE = 15880; // 1 +const static uint64_t SH_FLD_STICKY_CACHE_VDM_DATA = 15881; // 12 +const static uint64_t SH_FLD_STICKY_CACHE_VDM_DATA_LEN = 15882; // 12 +const static uint64_t SH_FLD_STICKY_CORE0_VDM_DATA = 15883; // 12 +const static uint64_t SH_FLD_STICKY_CORE0_VDM_DATA_LEN = 15884; // 12 +const static uint64_t SH_FLD_STICKY_CORE1_VDM_DATA = 15885; // 12 +const static uint64_t SH_FLD_STICKY_CORE1_VDM_DATA_LEN = 15886; // 12 +const static uint64_t SH_FLD_STICKY_CORE2_VDM_DATA = 15887; // 12 +const static uint64_t SH_FLD_STICKY_CORE2_VDM_DATA_LEN = 15888; // 12 +const static uint64_t SH_FLD_STICKY_CORE3_VDM_DATA = 15889; // 12 +const static uint64_t SH_FLD_STICKY_CORE3_VDM_DATA_LEN = 15890; // 12 +const static uint64_t SH_FLD_STICKY_ERROR_INJECT_ENABLE = 15891; // 1 +const static uint64_t SH_FLD_STICKY_VDM_CONTROL_SUMMARY = 15892; // 12 +const static uint64_t SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN = 15893; // 12 +const static uint64_t SH_FLD_STOP = 15894; // 6 +const static uint64_t SH_FLD_STOP1_ACTIVE_ENABLE = 15895; // 12 +const static uint64_t SH_FLD_STOPPED = 15896; // 2 +const static uint64_t SH_FLD_STOP_ACTIVE_MASK = 15897; // 12 +const static uint64_t SH_FLD_STOP_ERROR_0 = 15898; // 4 +const static uint64_t SH_FLD_STOP_ERROR_1 = 15899; // 2 +const static uint64_t SH_FLD_STOP_ERROR_2 = 15900; // 2 +const static uint64_t SH_FLD_STOP_ERROR_3 = 15901; // 2 +const static uint64_t SH_FLD_STOP_EXIT_TYPE_SEL = 15902; // 24 +const static uint64_t SH_FLD_STOP_ON_ERR = 15903; // 45 +const static uint64_t SH_FLD_STOP_ON_RECOV_ERR_SELECTION = 15904; // 43 +const static uint64_t SH_FLD_STOP_ON_SPATTN_SELECTION = 15905; // 43 +const static uint64_t SH_FLD_STOP_ON_XSTOP_SELECTION = 15906; // 43 +const static uint64_t SH_FLD_STOP_OVERRIDE_MODE = 15907; // 12 +const static uint64_t SH_FLD_STOP_RECOVERY_NOTIFY_PRD = 15908; // 1 +const static uint64_t SH_FLD_STOP_REQUEST_LEVEL_A_N = 15909; // 96 +const static uint64_t SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN = 15910; // 96 +const static uint64_t SH_FLD_STOP_RUNN_ON_XSTOP = 15911; // 43 +const static uint64_t SH_FLD_STORE_ADDRESS = 15912; // 21 +const static uint64_t SH_FLD_STORE_ADDRESS_LEN = 15913; // 21 +const static uint64_t SH_FLD_STORE_ON_TRIG_MODE = 15914; // 90 +const static uint64_t SH_FLD_STORE_ON_TRIG_MODE_LEN = 15915; // 90 +const static uint64_t SH_FLD_STORE_TIMEOUT = 15916; // 12 +const static uint64_t SH_FLD_STQ_DATA_HANG = 15917; // 1 +const static uint64_t SH_FLD_STQ_DATA_PARITY_ERR = 15918; // 12 +const static uint64_t SH_FLD_STQ_ERR = 15919; // 12 +const static uint64_t SH_FLD_STQ_ERR_LEN = 15920; // 12 +const static uint64_t SH_FLD_STQ_FSM_PERR = 15921; // 1 +const static uint64_t SH_FLD_STQ_HW_MAX_0_4 = 15922; // 1 +const static uint64_t SH_FLD_STQ_HW_MAX_0_4_LEN = 15923; // 1 +const static uint64_t SH_FLD_STQ_HW_MIN_0_4 = 15924; // 1 +const static uint64_t SH_FLD_STQ_HW_MIN_0_4_LEN = 15925; // 1 +const static uint64_t SH_FLD_STQ_HYP_MAX_0_4 = 15926; // 1 +const static uint64_t SH_FLD_STQ_HYP_MAX_0_4_LEN = 15927; // 1 +const static uint64_t SH_FLD_STQ_HYP_MIN_0_4 = 15928; // 1 +const static uint64_t SH_FLD_STQ_HYP_MIN_0_4_LEN = 15929; // 1 +const static uint64_t SH_FLD_STQ_IPI_MAX_0_4 = 15930; // 1 +const static uint64_t SH_FLD_STQ_IPI_MAX_0_4_LEN = 15931; // 1 +const static uint64_t SH_FLD_STQ_IPI_MIN_0_4 = 15932; // 1 +const static uint64_t SH_FLD_STQ_IPI_MIN_0_4_LEN = 15933; // 1 +const static uint64_t SH_FLD_STQ_OS_MAX_0_4 = 15934; // 1 +const static uint64_t SH_FLD_STQ_OS_MAX_0_4_LEN = 15935; // 1 +const static uint64_t SH_FLD_STQ_OS_MIN_0_4 = 15936; // 1 +const static uint64_t SH_FLD_STQ_OS_MIN_0_4_LEN = 15937; // 1 +const static uint64_t SH_FLD_STQ_RDI_MAX_0_4 = 15938; // 1 +const static uint64_t SH_FLD_STQ_RDI_MAX_0_4_LEN = 15939; // 1 +const static uint64_t SH_FLD_STQ_RDI_MIN_0_4 = 15940; // 1 +const static uint64_t SH_FLD_STQ_RDI_MIN_0_4_LEN = 15941; // 1 +const static uint64_t SH_FLD_STQ_REG_MAX_0_4 = 15942; // 1 +const static uint64_t SH_FLD_STQ_REG_MAX_0_4_LEN = 15943; // 1 +const static uint64_t SH_FLD_STQ_REG_MIN_0_4 = 15944; // 1 +const static uint64_t SH_FLD_STQ_REG_MIN_0_4_LEN = 15945; // 1 +const static uint64_t SH_FLD_STQ_THR_MAX_0_4 = 15946; // 1 +const static uint64_t SH_FLD_STQ_THR_MAX_0_4_LEN = 15947; // 1 +const static uint64_t SH_FLD_STQ_THR_MIN_0_4 = 15948; // 1 +const static uint64_t SH_FLD_STQ_THR_MIN_0_4_LEN = 15949; // 1 +const static uint64_t SH_FLD_STQ_TYPE = 15950; // 12 +const static uint64_t SH_FLD_STQ_TYPE_LEN = 15951; // 12 +const static uint64_t SH_FLD_STQ_VPC_MAX_0_4 = 15952; // 1 +const static uint64_t SH_FLD_STQ_VPC_MAX_0_4_LEN = 15953; // 1 +const static uint64_t SH_FLD_STQ_VPC_MIN_0_4 = 15954; // 1 +const static uint64_t SH_FLD_STQ_VPC_MIN_0_4_LEN = 15955; // 1 +const static uint64_t SH_FLD_STREAM_MODE = 15956; // 4 +const static uint64_t SH_FLD_STREAM_TYPE = 15957; // 4 +const static uint64_t SH_FLD_STRICT_IPI_RULES = 15958; // 1 +const static uint64_t SH_FLD_STRICT_ORDER = 15959; // 1 +const static uint64_t SH_FLD_ST_ACK_DEAD = 15960; // 12 +const static uint64_t SH_FLD_ST_ADDR_ERR = 15961; // 12 +const static uint64_t SH_FLD_ST_CLASS_CMD_ADDR_ERR = 15962; // 4 +const static uint64_t SH_FLD_ST_CLASS_CMD_FOREIGN_LINK_FAIL = 15963; // 4 +const static uint64_t SH_FLD_ST_ECC_CE = 15964; // 1 +const static uint64_t SH_FLD_ST_ECC_UE = 15965; // 1 +const static uint64_t SH_FLD_SUE_0 = 15966; // 8 +const static uint64_t SH_FLD_SUE_1 = 15967; // 8 +const static uint64_t SH_FLD_SUE_DIS_BR = 15968; // 3 +const static uint64_t SH_FLD_SUE_DIS_BR_PERR = 15969; // 3 +const static uint64_t SH_FLD_SUE_DIS_IR = 15970; // 3 +const static uint64_t SH_FLD_SUE_DIS_IR_PERR = 15971; // 3 +const static uint64_t SH_FLD_SUE_DIS_OR = 15972; // 3 +const static uint64_t SH_FLD_SUE_DIS_OR_PERR = 15973; // 3 +const static uint64_t SH_FLD_SUE_DIS_PR = 15974; // 3 +const static uint64_t SH_FLD_SUE_DIS_PT = 15975; // 3 +const static uint64_t SH_FLD_SUMMARY = 15976; // 1 +const static uint64_t SH_FLD_SUOP_ERROR_1 = 15977; // 4 +const static uint64_t SH_FLD_SUOP_ERROR_2 = 15978; // 4 +const static uint64_t SH_FLD_SUOP_ERROR_3 = 15979; // 4 +const static uint64_t SH_FLD_SUPPRESS = 15980; // 301 +const static uint64_t SH_FLD_SUPPRESS_EVEN_CLK = 15981; // 43 +const static uint64_t SH_FLD_SWC_VALUE = 15982; // 1 +const static uint64_t SH_FLD_SWC_VALUE_LEN = 15983; // 1 +const static uint64_t SH_FLD_SWITCH_SYNC_ERROR_DISABLE = 15984; // 1 +const static uint64_t SH_FLD_SYM_CPB_CHECK_DISABLE = 15985; // 1 +const static uint64_t SH_FLD_SYM_MAX_INRD = 15986; // 1 +const static uint64_t SH_FLD_SYM_MAX_INRD_LEN = 15987; // 1 +const static uint64_t SH_FLD_SYNCEN = 15988; // 7 +const static uint64_t SH_FLD_SYNC_BRK = 15989; // 1 +const static uint64_t SH_FLD_SYNC_BRK_LEN = 15990; // 1 +const static uint64_t SH_FLD_SYNC_CREATE_SPS_SELECT = 15991; // 1 +const static uint64_t SH_FLD_SYNC_CREATE_SPS_SELECT_LEN = 15992; // 1 +const static uint64_t SH_FLD_SYNC_DONE = 15993; // 2 +const static uint64_t SH_FLD_SYNC_DONE_LEN = 15994; // 2 +const static uint64_t SH_FLD_SYNC_FENCE = 15995; // 4 +const static uint64_t SH_FLD_SYNC_GO_CH0 = 15996; // 4 +const static uint64_t SH_FLD_SYNC_GO_CH1 = 15997; // 4 +const static uint64_t SH_FLD_SYNC_MODE = 15998; // 4 +const static uint64_t SH_FLD_SYNC_REPLAY_COUNT = 15999; // 4 +const static uint64_t SH_FLD_SYNC_REPLAY_COUNT_LEN = 16000; // 4 +const static uint64_t SH_FLD_SYNC_RESERVED = 16001; // 4 +const static uint64_t SH_FLD_SYNC_RESERVED_LEN = 16002; // 4 +const static uint64_t SH_FLD_SYNC_RESET = 16003; // 1 +const static uint64_t SH_FLD_SYNC_TIMER_SEL = 16004; // 17 +const static uint64_t SH_FLD_SYNC_TIMER_SEL_LEN = 16005; // 17 +const static uint64_t SH_FLD_SYNC_TYPE = 16006; // 4 +const static uint64_t SH_FLD_SYNC_TYPE_LEN = 16007; // 4 +const static uint64_t SH_FLD_SYNC_WAIT = 16008; // 1 +const static uint64_t SH_FLD_SYNC_WAIT_LEN = 16009; // 1 +const static uint64_t SH_FLD_SYNDROME = 16010; // 8 +const static uint64_t SH_FLD_SYNDROME_LEN = 16011; // 8 +const static uint64_t SH_FLD_SYN_HI_0_7 = 16012; // 1 +const static uint64_t SH_FLD_SYN_HI_0_7_LEN = 16013; // 1 +const static uint64_t SH_FLD_SYN_LO_0_7 = 16014; // 1 +const static uint64_t SH_FLD_SYN_LO_0_7_LEN = 16015; // 1 +const static uint64_t SH_FLD_SYSCLK_2X_MEMINTCLKO = 16016; // 8 +const static uint64_t SH_FLD_SYSCLK_RESET = 16017; // 8 +const static uint64_t SH_FLD_SYSMAP_SM_NOT_LG_SEL = 16018; // 12 +const static uint64_t SH_FLD_SYSTEM = 16019; // 2 +const static uint64_t SH_FLD_SYSTEM_CHECKSTOP = 16020; // 1 +const static uint64_t SH_FLD_SYSTEM_FAST_INIT = 16021; // 43 +const static uint64_t SH_FLD_SYSTEM_LEN = 16022; // 2 +const static uint64_t SH_FLD_SYSTEM_RESET = 16023; // 1 +const static uint64_t SH_FLD_S_PATH_0_PARITY = 16024; // 4 +const static uint64_t SH_FLD_S_PATH_0_STEP_CHECK = 16025; // 4 +const static uint64_t SH_FLD_S_PATH_0_STEP_CHECK_VALID = 16026; // 1 +const static uint64_t SH_FLD_S_PATH_1_PARITY = 16027; // 4 +const static uint64_t SH_FLD_S_PATH_1_STEP_CHECK = 16028; // 4 +const static uint64_t SH_FLD_S_PATH_1_STEP_CHECK_VALID = 16029; // 1 +const static uint64_t SH_FLD_S_PATH_SELECT = 16030; // 1 +const static uint64_t SH_FLD_T0_RUN_Q = 16031; // 24 +const static uint64_t SH_FLD_T1_RUN_Q = 16032; // 24 +const static uint64_t SH_FLD_T2_RUN_Q = 16033; // 24 +const static uint64_t SH_FLD_T3_RUN_Q = 16034; // 24 +const static uint64_t SH_FLD_T4_RUN_Q = 16035; // 24 +const static uint64_t SH_FLD_T5_RUN_Q = 16036; // 24 +const static uint64_t SH_FLD_T6_RUN_Q = 16037; // 24 +const static uint64_t SH_FLD_T7_RUN_Q = 16038; // 24 +const static uint64_t SH_FLD_TABLE_ADDRESS = 16039; // 1 +const static uint64_t SH_FLD_TABLE_ADDRESS_LEN = 16040; // 1 +const static uint64_t SH_FLD_TABLE_DATA = 16041; // 1 +const static uint64_t SH_FLD_TABLE_DATA_LEN = 16042; // 1 +const static uint64_t SH_FLD_TABLE_SELECT = 16043; // 1 +const static uint64_t SH_FLD_TABLE_SELECT_LEN = 16044; // 1 +const static uint64_t SH_FLD_TABLE_SEL_0_3 = 16045; // 1 +const static uint64_t SH_FLD_TABLE_SEL_0_3_LEN = 16046; // 1 +const static uint64_t SH_FLD_TAG_ECC = 16047; // 12 +const static uint64_t SH_FLD_TAG_ECC_LEN = 16048; // 12 +const static uint64_t SH_FLD_TAP_SEL = 16049; // 24 +const static uint64_t SH_FLD_TAP_SEL_LEN = 16050; // 24 +const static uint64_t SH_FLD_TARGET_DDE = 16051; // 3 +const static uint64_t SH_FLD_TARGET_DDE_LEN = 16052; // 3 +const static uint64_t SH_FLD_TARGET_ID0 = 16053; // 2 +const static uint64_t SH_FLD_TARGET_MIN = 16054; // 2 +const static uint64_t SH_FLD_TARGET_MIN_LEN = 16055; // 2 +const static uint64_t SH_FLD_TARGET_VALID = 16056; // 2 +const static uint64_t SH_FLD_TARGET_VALID_LEN = 16057; // 2 +const static uint64_t SH_FLD_TCBR_TP_PSI_GLB_ERR_0 = 16058; // 4 +const static uint64_t SH_FLD_TCBR_TP_PSI_GLB_ERR_1 = 16059; // 4 +const static uint64_t SH_FLD_TCD_PERR_ESR = 16060; // 1 +const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_EQ = 16061; // 6 +const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_EQ_LEN = 16062; // 6 +const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_DN = 16063; // 6 +const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_DN_LEN = 16064; // 6 +const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_UP = 16065; // 6 +const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_L3_UP_LEN = 16066; // 6 +const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_DN = 16067; // 6 +const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_DN_LEN = 16068; // 6 +const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_UP = 16069; // 6 +const static uint64_t SH_FLD_TCEP_AMUX_VSELECT_PWR_UP_LEN = 16070; // 6 +const static uint64_t SH_FLD_TCE_CACHE_1W = 16071; // 1 +const static uint64_t SH_FLD_TCE_CACHE_DISABLE = 16072; // 1 +const static uint64_t SH_FLD_TCE_CACHE_MULT_HIT_ERR_ESR = 16073; // 1 +const static uint64_t SH_FLD_TCE_COMMON_FATAL_ERROR = 16074; // 6 +const static uint64_t SH_FLD_TCE_ECC_CORRECTABLE_ERROR = 16075; // 6 +const static uint64_t SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR = 16076; // 6 +const static uint64_t SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR = 16077; // 6 +const static uint64_t SH_FLD_TCE_PAGE_ACCESS_ERR_ESR = 16078; // 1 +const static uint64_t SH_FLD_TCE_REQUEST_TIMEOUT_ERROR = 16079; // 6 +const static uint64_t SH_FLD_TCE_REQ_TO_ERR_ESR = 16080; // 1 +const static uint64_t SH_FLD_TCE_RESPONSE = 16081; // 1 +const static uint64_t SH_FLD_TCE_TIMEOUT = 16082; // 1 +const static uint64_t SH_FLD_TCE_TIMEOUT_LEN = 16083; // 1 +const static uint64_t SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR = 16084; // 6 +const static uint64_t SH_FLD_TCK_WIDTH = 16085; // 1 +const static uint64_t SH_FLD_TCK_WIDTH_LEN = 16086; // 1 +const static uint64_t SH_FLD_TCPERV_AMUX_VSELECT_CHIP = 16087; // 1 +const static uint64_t SH_FLD_TCPERV_AMUX_VSELECT_CHIP_LEN = 16088; // 1 +const static uint64_t SH_FLD_TCTXT_PRESP_ERROR = 16089; // 1 +const static uint64_t SH_FLD_TC_BSC_EXTMODE_DC = 16090; // 43 +const static uint64_t SH_FLD_TC_BSC_INTMODE_DC = 16091; // 43 +const static uint64_t SH_FLD_TC_BSC_INV_DC = 16092; // 43 +const static uint64_t SH_FLD_TC_BSC_WRAPSEL_DC = 16093; // 43 +const static uint64_t SH_FLD_TC_DIAG_PORT0_OUT = 16094; // 43 +const static uint64_t SH_FLD_TC_DIAG_PORT1_OUT = 16095; // 43 +const static uint64_t SH_FLD_TC_EDRAM_ABIST_MODE_DC = 16096; // 43 +const static uint64_t SH_FLD_TC_IOBIST_MODE_DC = 16097; // 43 +const static uint64_t SH_FLD_TC_IOM_DPHY01_PLL_RESET_N = 16098; // 2 +const static uint64_t SH_FLD_TC_IOM_DPHY23_PLL_RESET_N = 16099; // 2 +const static uint64_t SH_FLD_TC_IOP_HSSPCLKOUTEN = 16100; // 3 +const static uint64_t SH_FLD_TC_IOP_HSSPORWREN = 16101; // 3 +const static uint64_t SH_FLD_TC_IOP_SYS_RESET_PCS = 16102; // 3 +const static uint64_t SH_FLD_TC_IOP_SYS_RESET_PMA = 16103; // 3 +const static uint64_t SH_FLD_TC_LP_RESET = 16104; // 1 +const static uint64_t SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC = 16105; // 43 +const static uint64_t SH_FLD_TC_NBTI_PROBE_GATE_DC = 16106; // 43 +const static uint64_t SH_FLD_TC_OB_RATIO_DC = 16107; // 2 +const static uint64_t SH_FLD_TC_OB_RATIO_DC_LEN = 16108; // 2 +const static uint64_t SH_FLD_TC_OELCC_ALIGN_FLUSH_DC = 16109; // 43 +const static uint64_t SH_FLD_TC_OELCC_EDGE_DELAYED_DC = 16110; // 43 +const static uint64_t SH_FLD_TC_PBE0_IOVALID_DC = 16111; // 1 +const static uint64_t SH_FLD_TC_PBE1_IOVALID_DC = 16112; // 1 +const static uint64_t SH_FLD_TC_PBE2_IOVALID_DC = 16113; // 1 +const static uint64_t SH_FLD_TC_PBE3_IOVALID_DC = 16114; // 1 +const static uint64_t SH_FLD_TC_PBE4_IOVALID_DC = 16115; // 1 +const static uint64_t SH_FLD_TC_PBE5_IOVALID_DC = 16116; // 1 +const static uint64_t SH_FLD_TC_PBIOO0_IOVALID = 16117; // 2 +const static uint64_t SH_FLD_TC_PBIOO1_IOVALID = 16118; // 2 +const static uint64_t SH_FLD_TC_PCI0_IOVALID = 16119; // 1 +const static uint64_t SH_FLD_TC_PCI0_LANE_CFG_DC = 16120; // 1 +const static uint64_t SH_FLD_TC_PCI0_LANE_CFG_DC_LEN = 16121; // 1 +const static uint64_t SH_FLD_TC_PCI0_RATIO_DC = 16122; // 1 +const static uint64_t SH_FLD_TC_PCI0_RATIO_DC_LEN = 16123; // 1 +const static uint64_t SH_FLD_TC_PCI0_RATIO_OVERRIDE = 16124; // 1 +const static uint64_t SH_FLD_TC_PCI0_SWAP_DC = 16125; // 1 +const static uint64_t SH_FLD_TC_PCI1X_IOVALID = 16126; // 1 +const static uint64_t SH_FLD_TC_PCI1X_IOVALID_LEN = 16127; // 1 +const static uint64_t SH_FLD_TC_PCI1_LANE_CFG_DC = 16128; // 1 +const static uint64_t SH_FLD_TC_PCI1_LANE_CFG_DC_LEN = 16129; // 1 +const static uint64_t SH_FLD_TC_PCI1_PIPE1_RATIO_DC = 16130; // 1 +const static uint64_t SH_FLD_TC_PCI1_PIPE1_RATIO_DC_LEN = 16131; // 1 +const static uint64_t SH_FLD_TC_PCI1_PIPE2_RATIO_DC = 16132; // 1 +const static uint64_t SH_FLD_TC_PCI1_PIPE2_RATIO_DC_LEN = 16133; // 1 +const static uint64_t SH_FLD_TC_PCI1_RATIO_OVERRIDE = 16134; // 1 +const static uint64_t SH_FLD_TC_PCI1_RATIO_OVERRIDE_LEN = 16135; // 1 +const static uint64_t SH_FLD_TC_PCI1_SWAP_DC = 16136; // 1 +const static uint64_t SH_FLD_TC_PCI1_SWAP_DC_LEN = 16137; // 1 +const static uint64_t SH_FLD_TC_PCI2_IOVALID = 16138; // 1 +const static uint64_t SH_FLD_TC_PCI2_IOVALID_LEN = 16139; // 1 +const static uint64_t SH_FLD_TC_PCI2_LANE_CFG_DC = 16140; // 1 +const static uint64_t SH_FLD_TC_PCI2_LANE_CFG_DC_LEN = 16141; // 1 +const static uint64_t SH_FLD_TC_PCI2_PIPE1_RATIO_DC = 16142; // 1 +const static uint64_t SH_FLD_TC_PCI2_PIPE1_RATIO_DC_LEN = 16143; // 1 +const static uint64_t SH_FLD_TC_PCI2_PIPE2_RATIO_DC = 16144; // 1 +const static uint64_t SH_FLD_TC_PCI2_PIPE2_RATIO_DC_LEN = 16145; // 1 +const static uint64_t SH_FLD_TC_PCI2_PIPE3_RATIO_DC = 16146; // 1 +const static uint64_t SH_FLD_TC_PCI2_PIPE3_RATIO_DC_LEN = 16147; // 1 +const static uint64_t SH_FLD_TC_PCI2_RATIO_OVERRIDE = 16148; // 1 +const static uint64_t SH_FLD_TC_PCI2_RATIO_OVERRIDE_LEN = 16149; // 1 +const static uint64_t SH_FLD_TC_PCI2_SWAP_DC = 16150; // 1 +const static uint64_t SH_FLD_TC_PCI2_SWAP_DC_LEN = 16151; // 1 +const static uint64_t SH_FLD_TC_PERV_EXPORT_FREEZE = 16152; // 1 +const static uint64_t SH_FLD_TC_PERV_REGION_FENCE = 16153; // 43 +const static uint64_t SH_FLD_TC_PSI_IOVALID_DC = 16154; // 1 +const static uint64_t SH_FLD_TC_PSRO_SEL_DC = 16155; // 43 +const static uint64_t SH_FLD_TC_PSRO_SEL_DC_LEN = 16156; // 43 +const static uint64_t SH_FLD_TC_REFCLK_DRVR_EN_DC = 16157; // 43 +const static uint64_t SH_FLD_TC_REGION1_FENCE = 16158; // 42 +const static uint64_t SH_FLD_TC_REGION2_FENCE = 16159; // 42 +const static uint64_t SH_FLD_TC_REGION3_FENCE = 16160; // 16 +const static uint64_t SH_FLD_TC_REGION4_FENCE = 16161; // 12 +const static uint64_t SH_FLD_TC_REGION5_FENCE = 16162; // 10 +const static uint64_t SH_FLD_TC_REGION6_FENCE = 16163; // 8 +const static uint64_t SH_FLD_TC_REGION7_FENCE = 16164; // 7 +const static uint64_t SH_FLD_TC_REGION8_FENCE = 16165; // 6 +const static uint64_t SH_FLD_TC_REGION9_FENCE = 16166; // 6 +const static uint64_t SH_FLD_TC_SKIT_MODE_BIST_DC = 16167; // 43 +const static uint64_t SH_FLD_TC_SRAM_ABIST_MODE_DC = 16168; // 43 +const static uint64_t SH_FLD_TC_START_TEST_DC = 16169; // 43 +const static uint64_t SH_FLD_TC_UNIT_ARY_WRT_THRU_DC = 16170; // 43 +const static uint64_t SH_FLD_TC_UNIT_AVP_MODE = 16171; // 43 +const static uint64_t SH_FLD_TC_UNIT_CHIP_ID_DC = 16172; // 43 +const static uint64_t SH_FLD_TC_UNIT_CHIP_ID_DC_LEN = 16173; // 43 +const static uint64_t SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC = 16174; // 43 +const static uint64_t SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC = 16175; // 43 +const static uint64_t SH_FLD_TC_UNIT_GROUP_ID_DC = 16176; // 43 +const static uint64_t SH_FLD_TC_UNIT_GROUP_ID_DC_LEN = 16177; // 43 +const static uint64_t SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC = 16178; // 43 +const static uint64_t SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE = 16179; // 43 +const static uint64_t SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC = 16180; // 43 +const static uint64_t SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC = 16181; // 43 +const static uint64_t SH_FLD_TC_UNIT_SYS_ID_DC = 16182; // 43 +const static uint64_t SH_FLD_TC_UNIT_SYS_ID_DC_LEN = 16183; // 43 +const static uint64_t SH_FLD_TC_VITL_REGION_FENCE = 16184; // 43 +const static uint64_t SH_FLD_TDR_DAC_CNTL = 16185; // 6 +const static uint64_t SH_FLD_TDR_DAC_CNTL_LEN = 16186; // 6 +const static uint64_t SH_FLD_TDR_ENABLE = 16187; // 116 +const static uint64_t SH_FLD_TDR_PERR_ESR = 16188; // 1 +const static uint64_t SH_FLD_TDR_PHASE_SEL = 16189; // 6 +const static uint64_t SH_FLD_TDR_PULSE_OFFSET = 16190; // 6 +const static uint64_t SH_FLD_TDR_PULSE_OFFSET_LEN = 16191; // 6 +const static uint64_t SH_FLD_TDR_PULSE_WIDTH = 16192; // 6 +const static uint64_t SH_FLD_TDR_PULSE_WIDTH_LEN = 16193; // 6 +const static uint64_t SH_FLD_TER = 16194; // 8 +const static uint64_t SH_FLD_TERM_ENC = 16195; // 1 +const static uint64_t SH_FLD_TERM_ENC_LEN = 16196; // 1 +const static uint64_t SH_FLD_TERM_TEST = 16197; // 1 +const static uint64_t SH_FLD_TER_LEN = 16198; // 8 +const static uint64_t SH_FLD_TER_V = 16199; // 8 +const static uint64_t SH_FLD_TEST_ENABLE = 16200; // 43 +const static uint64_t SH_FLD_TFAC_ERR = 16201; // 96 +const static uint64_t SH_FLD_TFMR_PARITY_ERR = 16202; // 96 +const static uint64_t SH_FLD_TFREQ0 = 16203; // 9 +const static uint64_t SH_FLD_TFREQ0_LEN = 16204; // 9 +const static uint64_t SH_FLD_TFREQ1 = 16205; // 9 +const static uint64_t SH_FLD_TFREQ1_LEN = 16206; // 9 +const static uint64_t SH_FLD_TGT_NODAL_DINC_ERR = 16207; // 12 +const static uint64_t SH_FLD_TGT_NODAL_REQ_DINC_ERR = 16208; // 12 +const static uint64_t SH_FLD_THERM_MODE = 16209; // 43 +const static uint64_t SH_FLD_THERM_MODEREG_PARITY_MASK = 16210; // 43 +const static uint64_t SH_FLD_THERM_MODE_LEN = 16211; // 43 +const static uint64_t SH_FLD_THERM_TRIP = 16212; // 43 +const static uint64_t SH_FLD_THERM_TRIP_LEN = 16213; // 43 +const static uint64_t SH_FLD_THREEPHAS = 16214; // 3 +const static uint64_t SH_FLD_THRESHOLD = 16215; // 1 +const static uint64_t SH_FLD_THRESH_0 = 16216; // 3 +const static uint64_t SH_FLD_THRESH_0_LEN = 16217; // 3 +const static uint64_t SH_FLD_THRESH_1 = 16218; // 3 +const static uint64_t SH_FLD_THRESH_1_LEN = 16219; // 3 +const static uint64_t SH_FLD_THRESH_2 = 16220; // 3 +const static uint64_t SH_FLD_THRESH_2_LEN = 16221; // 3 +const static uint64_t SH_FLD_THRES_ENA = 16222; // 43 +const static uint64_t SH_FLD_THRES_ENA_LEN = 16223; // 43 +const static uint64_t SH_FLD_THRES_OVERFLOW_MASK = 16224; // 43 +const static uint64_t SH_FLD_THRES_STATE_MASK = 16225; // 43 +const static uint64_t SH_FLD_THRES_TRIP_ENA = 16226; // 43 +const static uint64_t SH_FLD_THRES_TRIP_ENA_LEN = 16227; // 43 +const static uint64_t SH_FLD_THRID = 16228; // 1 +const static uint64_t SH_FLD_THRID_LEN = 16229; // 1 +const static uint64_t SH_FLD_THR_ID = 16230; // 1 +const static uint64_t SH_FLD_THR_ID_LEN = 16231; // 1 +const static uint64_t SH_FLD_TID = 16232; // 8 +const static uint64_t SH_FLD_TID_LEN = 16233; // 8 +const static uint64_t SH_FLD_TIER0_VALUE = 16234; // 12 +const static uint64_t SH_FLD_TIER0_VALUE_LEN = 16235; // 12 +const static uint64_t SH_FLD_TIER1_VALUE = 16236; // 24 +const static uint64_t SH_FLD_TIER1_VALUE_LEN = 16237; // 24 +const static uint64_t SH_FLD_TIER2_VALUE = 16238; // 24 +const static uint64_t SH_FLD_TIER2_VALUE_LEN = 16239; // 24 +const static uint64_t SH_FLD_TIME = 16240; // 43 +const static uint64_t SH_FLD_TIMEBASE = 16241; // 330 +const static uint64_t SH_FLD_TIMEBASE_ENABLE = 16242; // 1 +const static uint64_t SH_FLD_TIMEBASE_LEN = 16243; // 330 +const static uint64_t SH_FLD_TIMEOUT_ACTIVE = 16244; // 2 +const static uint64_t SH_FLD_TIMEOUT_EN = 16245; // 1 +const static uint64_t SH_FLD_TIMEOUT_MASK = 16246; // 43 +const static uint64_t SH_FLD_TIMEOUT_N = 16247; // 2 +const static uint64_t SH_FLD_TIMEOUT_ON_I2C_STATUS_RD = 16248; // 1 +const static uint64_t SH_FLD_TIMEOUT_PARITY = 16249; // 43 +const static uint64_t SH_FLD_TIMEOUT_SEL = 16250; // 3 +const static uint64_t SH_FLD_TIMEOUT_SEL_LEN = 16251; // 3 +const static uint64_t SH_FLD_TIMEOUT_VALUE = 16252; // 5 +const static uint64_t SH_FLD_TIMEOUT_VALUE_LEN = 16253; // 5 +const static uint64_t SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 16254; // 43 +const static uint64_t SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 16255; // 43 +const static uint64_t SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 16256; // 43 +const static uint64_t SH_FLD_TIMER = 16257; // 3 +const static uint64_t SH_FLD_TIMER_ENABLE = 16258; // 4 +const static uint64_t SH_FLD_TIMER_EXPIRED_RECOV_ERROR = 16259; // 4 +const static uint64_t SH_FLD_TIMER_EXPIRED_XSTOP_ERROR = 16260; // 4 +const static uint64_t SH_FLD_TIMER_LEN = 16261; // 3 +const static uint64_t SH_FLD_TIMER_N = 16262; // 2 +const static uint64_t SH_FLD_TIMER_N_LEN = 16263; // 2 +const static uint64_t SH_FLD_TIMER_PERIOD_MASK = 16264; // 4 +const static uint64_t SH_FLD_TIMER_PERIOD_MASK_LEN = 16265; // 4 +const static uint64_t SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR = 16266; // 43 +const static uint64_t SH_FLD_TIMESTAMP_COUNTER_VALUE = 16267; // 43 +const static uint64_t SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN = 16268; // 43 +const static uint64_t SH_FLD_TIME_BASE_ERR = 16269; // 4 +const static uint64_t SH_FLD_TLBIE_CNT_THRESH = 16270; // 13 +const static uint64_t SH_FLD_TLBIE_CNT_THRESH_LEN = 16271; // 13 +const static uint64_t SH_FLD_TLBIE_CNT_WT4TX_CORE_EN = 16272; // 12 +const static uint64_t SH_FLD_TLBIE_CONTROL_ERR = 16273; // 12 +const static uint64_t SH_FLD_TLBIE_DEC_RATE = 16274; // 13 +const static uint64_t SH_FLD_TLBIE_DEC_RATE_LEN = 16275; // 13 +const static uint64_t SH_FLD_TLBIE_INC_RATE = 16276; // 13 +const static uint64_t SH_FLD_TLBIE_INC_RATE_LEN = 16277; // 13 +const static uint64_t SH_FLD_TLBIE_MASTER_TIMEOUT = 16278; // 12 +const static uint64_t SH_FLD_TLBIE_PACING_CNT_EN = 16279; // 12 +const static uint64_t SH_FLD_TLBIE_SLBIEG_SW_ERR = 16280; // 12 +const static uint64_t SH_FLD_TLBIE_SNOOP_TIMEOUT = 16281; // 12 +const static uint64_t SH_FLD_TLBIE_STALL_CMPLT_CNT = 16282; // 14 +const static uint64_t SH_FLD_TLBIE_STALL_CMPLT_CNT_LEN = 16283; // 14 +const static uint64_t SH_FLD_TLBIE_STALL_DELAY_CNT = 16284; // 14 +const static uint64_t SH_FLD_TLBIE_STALL_DELAY_CNT_LEN = 16285; // 14 +const static uint64_t SH_FLD_TLBIE_STALL_EN = 16286; // 14 +const static uint64_t SH_FLD_TLBIE_STALL_THRESHOLD = 16287; // 14 +const static uint64_t SH_FLD_TLBIE_STALL_THRESHOLD_LEN = 16288; // 14 +const static uint64_t SH_FLD_TLBI_BAD_OP_ERR = 16289; // 4 +const static uint64_t SH_FLD_TLBI_DATA_POLL_PULSE_DIV = 16290; // 2 +const static uint64_t SH_FLD_TLBI_DATA_POLL_PULSE_DIV_LEN = 16291; // 2 +const static uint64_t SH_FLD_TLBI_FENCE = 16292; // 2 +const static uint64_t SH_FLD_TLBI_GROUP_PUMP_EN = 16293; // 12 +const static uint64_t SH_FLD_TLBI_PSL_DEAD = 16294; // 2 +const static uint64_t SH_FLD_TLBI_SEQ_ERR = 16295; // 4 +const static uint64_t SH_FLD_TLBI_SEQ_NUM_PARITY_ERR = 16296; // 4 +const static uint64_t SH_FLD_TLBI_TIMEOUT = 16297; // 4 +const static uint64_t SH_FLD_TLB_BUS0_STG1_SEL = 16298; // 1 +const static uint64_t SH_FLD_TLB_BUS0_STG2_SEL = 16299; // 1 +const static uint64_t SH_FLD_TLB_BUS1_STG1_SEL = 16300; // 1 +const static uint64_t SH_FLD_TLB_BUS1_STG2_SEL = 16301; // 1 +const static uint64_t SH_FLD_TLB_CHK_WAIT_DEC = 16302; // 12 +const static uint64_t SH_FLD_TLB_CHK_WAIT_DEC_LEN = 16303; // 12 +const static uint64_t SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV = 16304; // 12 +const static uint64_t SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN = 16305; // 12 +const static uint64_t SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV = 16306; // 12 +const static uint64_t SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV_LEN = 16307; // 12 +const static uint64_t SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV = 16308; // 12 +const static uint64_t SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV_LEN = 16309; // 12 +const static uint64_t SH_FLD_TMOD_CYCLES = 16310; // 8 +const static uint64_t SH_FLD_TMOD_CYCLES_LEN = 16311; // 8 +const static uint64_t SH_FLD_TMRSC_CYCLES = 16312; // 8 +const static uint64_t SH_FLD_TMRSC_CYCLES_LEN = 16313; // 8 +const static uint64_t SH_FLD_TMR_PE = 16314; // 8 +const static uint64_t SH_FLD_TM_CAM = 16315; // 12 +const static uint64_t SH_FLD_TM_CAM_LEN = 16316; // 12 +const static uint64_t SH_FLD_TODTLON_OFF_CYCLES = 16317; // 8 +const static uint64_t SH_FLD_TODTLON_OFF_CYCLES_LEN = 16318; // 8 +const static uint64_t SH_FLD_TOD_CMD_OVERRUN = 16319; // 1 +const static uint64_t SH_FLD_TOD_CNTR_REF = 16320; // 1 +const static uint64_t SH_FLD_TOD_CNTR_REF_LEN = 16321; // 1 +const static uint64_t SH_FLD_TOD_HANG_ERR = 16322; // 1 +const static uint64_t SH_FLD_TOD_TAP = 16323; // 24 +const static uint64_t SH_FLD_TOO_MANY_BUS_ERRORS = 16324; // 8 +const static uint64_t SH_FLD_TOR_PERR_ESR = 16325; // 1 +const static uint64_t SH_FLD_TOTAL_FREE_BUF_COUNT = 16326; // 1 +const static uint64_t SH_FLD_TOTAL_FREE_BUF_COUNT_LEN = 16327; // 1 +const static uint64_t SH_FLD_TO_CMP_LT_VALUE = 16328; // 86 +const static uint64_t SH_FLD_TO_CMP_LT_VALUE_LEN = 16329; // 86 +const static uint64_t SH_FLD_TO_IFU = 16330; // 24 +const static uint64_t SH_FLD_TO_ISU = 16331; // 24 +const static uint64_t SH_FLD_TO_LSU = 16332; // 24 +const static uint64_t SH_FLD_TO_PC = 16333; // 24 +const static uint64_t SH_FLD_TO_VSU = 16334; // 24 +const static uint64_t SH_FLD_TPCFSI_OPB_SW0_FENCE_DC = 16335; // 3 +const static uint64_t SH_FLD_TPCFSI_OPB_SW0_FENCE_DC_LEN = 16336; // 3 +const static uint64_t SH_FLD_TPCFSI_OPB_SW1_FENCE_DC = 16337; // 3 +const static uint64_t SH_FLD_TPCFSI_OPB_SW1_FENCE_DC_LEN = 16338; // 3 +const static uint64_t SH_FLD_TPCFSI_OPB_SW_RESET_DC = 16339; // 3 +const static uint64_t SH_FLD_TPFSI_ALTREFCLK_SE1 = 16340; // 3 +const static uint64_t SH_FLD_TPFSI_ALTREFCLK_SEL = 16341; // 3 +const static uint64_t SH_FLD_TPFSI_ARRAY_SET_VBL_TO_VDD_DC = 16342; // 2 +const static uint64_t SH_FLD_TPFSI_ARRAY_VBL_TO_VDD_DC = 16343; // 1 +const static uint64_t SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC = 16344; // 3 +const static uint64_t SH_FLD_TPFSI_OFFCHIP_REFCLK_EN_DC_LEN = 16345; // 3 +const static uint64_t SH_FLD_TPFSI_OSCSW0_PGOOD_N = 16346; // 3 +const static uint64_t SH_FLD_TPFSI_OSCSW1_PGOOD = 16347; // 3 +const static uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ0_DC = 16348; // 3 +const static uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ0_DC_LEN = 16349; // 3 +const static uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ1_DC = 16350; // 3 +const static uint64_t SH_FLD_TPFSI_OSCSW_ERRINJ1_DC_LEN = 16351; // 3 +const static uint64_t SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC = 16352; // 3 +const static uint64_t SH_FLD_TPFSI_OSCSW_SKEW_ADJUST_DC_LEN = 16353; // 3 +const static uint64_t SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC = 16354; // 3 +const static uint64_t SH_FLD_TPFSI_OSCSW_SNS_CONTENT_SEL_DC_LEN = 16355; // 3 +const static uint64_t SH_FLD_TPFSI_OSCSW_TWEAK_DC = 16356; // 3 +const static uint64_t SH_FLD_TPFSI_OSCSW_TWEAK_DC_LEN = 16357; // 3 +const static uint64_t SH_FLD_TPFSI_SBE_FENCE_VTLIO_DC_UNUSED = 16358; // 3 +const static uint64_t SH_FLD_TPFSI_TPI2C_BUS_FENCE_DC = 16359; // 3 +const static uint64_t SH_FLD_TPFSI_TP_FENCE_VTLIO_DC = 16360; // 3 +const static uint64_t SH_FLD_TPFSI_TP_LOWFREQTEST_REFCLK_DC_UNUSED = 16361; // 3 +const static uint64_t SH_FLD_TPFSI_TP_PFET_FORCE_OFF_DC = 16362; // 3 +const static uint64_t SH_FLD_TPFSI_TP_PFET_OVERRIDE_ON_DC_N = 16363; // 3 +const static uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_ASYNC_EN_DC = 16364; // 3 +const static uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_DATA_PAR_DIS_DC = 16365; // 3 +const static uint64_t SH_FLD_TPFSI_TP_VSB_DBG_PCB_TYPE_PAR_DIS_DC = 16366; // 3 +const static uint64_t SH_FLD_TPFSI_TP_VSB_PCB_GSD_LATCHED_MODE_DC = 16367; // 3 +const static uint64_t SH_FLD_TPSBE_TPBR_SBE_INTR = 16368; // 1 +const static uint64_t SH_FLD_TPSBE_TPIO_TPM_RESET = 16369; // 1 +const static uint64_t SH_FLD_TPSBE_TPOCC_HALT_COMPLEX = 16370; // 1 +const static uint64_t SH_FLD_TP_ARRAY_WRITE_ASSIST_EN_DC = 16371; // 3 +const static uint64_t SH_FLD_TP_CHIPLET_EN_DC = 16372; // 3 +const static uint64_t SH_FLD_TP_CLK_ASYNC_RESET_DC = 16373; // 3 +const static uint64_t SH_FLD_TP_CLK_DIV_BYPASS_EN_DC = 16374; // 3 +const static uint64_t SH_FLD_TP_CLK_PDLY_BYPASS1_EN_DC = 16375; // 3 +const static uint64_t SH_FLD_TP_CLK_PDLY_BYPASS2_EN_DC = 16376; // 3 +const static uint64_t SH_FLD_TP_CLK_PULSE_ENABLE_DC = 16377; // 3 +const static uint64_t SH_FLD_TP_CLK_PULSE_MODE_DC = 16378; // 3 +const static uint64_t SH_FLD_TP_CLK_PULSE_MODE_DC_LEN = 16379; // 3 +const static uint64_t SH_FLD_TP_CPM_CAL = 16380; // 1 +const static uint64_t SH_FLD_TP_CPM_CAL_SET = 16381; // 2 +const static uint64_t SH_FLD_TP_DI1_DC_B = 16382; // 3 +const static uint64_t SH_FLD_TP_DI1_DC_N = 16383; // 3 +const static uint64_t SH_FLD_TP_DI2_DC_B = 16384; // 3 +const static uint64_t SH_FLD_TP_DI2_DC_N = 16385; // 3 +const static uint64_t SH_FLD_TP_EDRAM_ENABLE_DC = 16386; // 3 +const static uint64_t SH_FLD_TP_EXSD_FULLSPEED_DC = 16387; // 1 +const static uint64_t SH_FLD_TP_EX_FUSE_FP_THROTTLE_EN_DC = 16388; // 1 +const static uint64_t SH_FLD_TP_EX_FUSE_VMX_CRYPTO_DIS_DC = 16389; // 1 +const static uint64_t SH_FLD_TP_FENCE_EN_DC = 16390; // 3 +const static uint64_t SH_FLD_TP_FENCE_PCB = 16391; // 43 +const static uint64_t SH_FLD_TP_FENCE_PCB_DC = 16392; // 3 +const static uint64_t SH_FLD_TP_FILT0_PLL_BYPASS = 16393; // 3 +const static uint64_t SH_FLD_TP_FILT0_PLL_RESET = 16394; // 3 +const static uint64_t SH_FLD_TP_FILT0_PLL_TEST_EN = 16395; // 3 +const static uint64_t SH_FLD_TP_FILT1_PLL_BYPASS = 16396; // 3 +const static uint64_t SH_FLD_TP_FILT1_PLL_RESET = 16397; // 3 +const static uint64_t SH_FLD_TP_FILT1_PLL_TEST_EN = 16398; // 3 +const static uint64_t SH_FLD_TP_FLUSH_ALIGN_OVERWRITE = 16399; // 3 +const static uint64_t SH_FLD_TP_FLUSH_SCAN_DC_N = 16400; // 3 +const static uint64_t SH_FLD_TP_FSI_CLKIN_SEL_DC = 16401; // 3 +const static uint64_t SH_FLD_TP_FSI_PROBE_SEL_DC = 16402; // 3 +const static uint64_t SH_FLD_TP_FSI_PROBE_SEL_DC_LEN = 16403; // 3 +const static uint64_t SH_FLD_TP_GLBCK_MEM_TESTCLK_SEL_DC = 16404; // 3 +const static uint64_t SH_FLD_TP_GLBCK_VSB_NEST_VREGDLY_SHUTOFF_DC = 16405; // 3 +const static uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC = 16406; // 3 +const static uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_TWEAK_DC_LEN = 16407; // 3 +const static uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC = 16408; // 3 +const static uint64_t SH_FLD_TP_GLBCK_VSB_PCIESW_USEOSC_DC_LEN = 16409; // 3 +const static uint64_t SH_FLD_TP_GPIO_PIB_TIMEOUT = 16410; // 3 +const static uint64_t SH_FLD_TP_GPIO_PIB_TIMEOUT_LEN = 16411; // 3 +const static uint64_t SH_FLD_TP_IDDQ_DC = 16412; // 3 +const static uint64_t SH_FLD_TP_IO_GPIO0_MCPRECOMP = 16413; // 3 +const static uint64_t SH_FLD_TP_IO_GPIO0_MCPRECOMP_LEN = 16414; // 3 +const static uint64_t SH_FLD_TP_IO_GPIO1_MCPRECOMP = 16415; // 3 +const static uint64_t SH_FLD_TP_IO_GPIO1_MCPRECOMP_LEN = 16416; // 3 +const static uint64_t SH_FLD_TP_IO_GPIO2_MCPRECOMP = 16417; // 3 +const static uint64_t SH_FLD_TP_IO_GPIO2_MCPRECOMP_LEN = 16418; // 3 +const static uint64_t SH_FLD_TP_LVLTRANS_FENCE_DC = 16419; // 3 +const static uint64_t SH_FLD_TP_NX_ALLOW_CRYPTO_DC = 16420; // 1 +const static uint64_t SH_FLD_TP_OSCSWITCH_VSB = 16421; // 3 +const static uint64_t SH_FLD_TP_OSCSWITCH_VSB_LEN = 16422; // 3 +const static uint64_t SH_FLD_TP_PCB_EP_RESET_DC = 16423; // 3 +const static uint64_t SH_FLD_TP_PCB_PM_MUX_SEL_DC = 16424; // 3 +const static uint64_t SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC = 16425; // 3 +const static uint64_t SH_FLD_TP_PCIREFCLK_RCVR_TERM_DC_LEN = 16426; // 3 +const static uint64_t SH_FLD_TP_PIB_TRACE_MODE_DATA_DC = 16427; // 3 +const static uint64_t SH_FLD_TP_PIB_VSB_DISABLE_PARITY_DC = 16428; // 3 +const static uint64_t SH_FLD_TP_PIB_VSB_SBE_TRACE_MODE = 16429; // 3 +const static uint64_t SH_FLD_TP_PLLBYP_DC = 16430; // 3 +const static uint64_t SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC = 16431; // 3 +const static uint64_t SH_FLD_TP_PLLREFCLK_RCVR_TERM_DC_LEN = 16432; // 3 +const static uint64_t SH_FLD_TP_PLLRST_DC = 16433; // 3 +const static uint64_t SH_FLD_TP_PLL_CLKIN_SEL1_DC = 16434; // 3 +const static uint64_t SH_FLD_TP_PLL_CLKIN_SEL2_DC = 16435; // 3 +const static uint64_t SH_FLD_TP_PLL_CLKIN_SEL3_DC = 16436; // 3 +const static uint64_t SH_FLD_TP_PLL_CLKIN_SEL4_DC = 16437; // 3 +const static uint64_t SH_FLD_TP_PLL_FORCE_OUT_EN_DC = 16438; // 3 +const static uint64_t SH_FLD_TP_PLL_TEST_EN = 16439; // 3 +const static uint64_t SH_FLD_TP_PLL_TEST_EN_DC = 16440; // 3 +const static uint64_t SH_FLD_TP_PROBE0_SEL_DC = 16441; // 3 +const static uint64_t SH_FLD_TP_PROBE0_SEL_DC_LEN = 16442; // 3 +const static uint64_t SH_FLD_TP_PROBE1_SEL_DC = 16443; // 3 +const static uint64_t SH_FLD_TP_PROBE1_SEL_DC_LEN = 16444; // 3 +const static uint64_t SH_FLD_TP_PROBE_DRV_EN_DC = 16445; // 3 +const static uint64_t SH_FLD_TP_PROBE_HIGHDRIVE_DC = 16446; // 3 +const static uint64_t SH_FLD_TP_PROBE_MESH_SEL_DC = 16447; // 3 +const static uint64_t SH_FLD_TP_RESCLK_DIS_DC = 16448; // 3 +const static uint64_t SH_FLD_TP_RI_DC_B = 16449; // 3 +const static uint64_t SH_FLD_TP_RI_DC_N = 16450; // 3 +const static uint64_t SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC = 16451; // 3 +const static uint64_t SH_FLD_TP_SEC_BUF_DRV_STRENGTH_DC_LEN = 16452; // 3 +const static uint64_t SH_FLD_TP_SS0_PLL_BYPASS = 16453; // 3 +const static uint64_t SH_FLD_TP_SS0_PLL_RESET = 16454; // 3 +const static uint64_t SH_FLD_TP_SS0_PLL_TEST_EN = 16455; // 3 +const static uint64_t SH_FLD_TP_TEST_BURNIN_MODE_DC = 16456; // 3 +const static uint64_t SH_FLD_TP_TPCPERV_VSB_TRACE_STOP = 16457; // 3 +const static uint64_t SH_FLD_TP_TPFSI_ACK = 16458; // 43 +const static uint64_t SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL = 16459; // 30 +const static uint64_t SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL_LEN = 16460; // 30 +const static uint64_t SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL = 16461; // 30 +const static uint64_t SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL_LEN = 16462; // 30 +const static uint64_t SH_FLD_TP_VITL_ACT_DIS_DC = 16463; // 3 +const static uint64_t SH_FLD_TP_VITL_CLKOFF_DC = 16464; // 3 +const static uint64_t SH_FLD_TP_VITL_DELAY_LCLKR_DC = 16465; // 3 +const static uint64_t SH_FLD_TP_VITL_MPW1_DC_N = 16466; // 3 +const static uint64_t SH_FLD_TP_VITL_MPW2_DC_N = 16467; // 3 +const static uint64_t SH_FLD_TP_VITL_MPW3_DC_N = 16468; // 3 +const static uint64_t SH_FLD_TP_VITL_SCAN_CLK_DC = 16469; // 3 +const static uint64_t SH_FLD_TP_VITL_SCIN_DC = 16470; // 3 +const static uint64_t SH_FLD_TRACE_BUS_BITS_0_63 = 16471; // 1 +const static uint64_t SH_FLD_TRACE_BUS_BITS_0_63_LEN = 16472; // 1 +const static uint64_t SH_FLD_TRACE_BUS_BITS_64_87 = 16473; // 1 +const static uint64_t SH_FLD_TRACE_BUS_BITS_64_87_LEN = 16474; // 1 +const static uint64_t SH_FLD_TRACE_BUS_EN = 16475; // 1 +const static uint64_t SH_FLD_TRACE_BUS_SEL_0_1 = 16476; // 1 +const static uint64_t SH_FLD_TRACE_BUS_SEL_0_1_LEN = 16477; // 1 +const static uint64_t SH_FLD_TRACE_BUS_TRIGGER_BITS = 16478; // 1 +const static uint64_t SH_FLD_TRACE_BUS_TRIGGER_BITS_LEN = 16479; // 1 +const static uint64_t SH_FLD_TRACE_DATA_SELECT = 16480; // 1 +const static uint64_t SH_FLD_TRACE_DATA_SELECT_LEN = 16481; // 1 +const static uint64_t SH_FLD_TRACE_DISABLE = 16482; // 1 +const static uint64_t SH_FLD_TRACE_ENABLE = 16483; // 7 +const static uint64_t SH_FLD_TRACE_EVENT = 16484; // 1 +const static uint64_t SH_FLD_TRACE_FREEZE = 16485; // 43 +const static uint64_t SH_FLD_TRACE_MUX_SEL = 16486; // 1 +const static uint64_t SH_FLD_TRACE_SEL = 16487; // 44 +const static uint64_t SH_FLD_TRACE_SELECT = 16488; // 2 +const static uint64_t SH_FLD_TRACE_SELECT_LEN = 16489; // 2 +const static uint64_t SH_FLD_TRACE_SEL_0_1 = 16490; // 1 +const static uint64_t SH_FLD_TRACE_SEL_0_1_LEN = 16491; // 1 +const static uint64_t SH_FLD_TRACE_SEL_LEN = 16492; // 44 +const static uint64_t SH_FLD_TRACE_STATE_LAT = 16493; // 43 +const static uint64_t SH_FLD_TRACE_STATE_LAT_LEN = 16494; // 43 +const static uint64_t SH_FLD_TRACE_TRIGGER = 16495; // 1 +const static uint64_t SH_FLD_TRACKING_TIMEOUT_SEL = 16496; // 6 +const static uint64_t SH_FLD_TRACKING_TIMEOUT_SEL_LEN = 16497; // 6 +const static uint64_t SH_FLD_TRANSPORT_INFORMATIONAL_ERR = 16498; // 4 +const static uint64_t SH_FLD_TRANS_DELAY = 16499; // 1 +const static uint64_t SH_FLD_TRANS_DELAY_LEN = 16500; // 1 +const static uint64_t SH_FLD_TRAPPED_DL_RETURN_P0 = 16501; // 43 +const static uint64_t SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY = 16502; // 43 +const static uint64_t SH_FLD_TRAPPED_GENERAL_TIMEOUT = 16503; // 43 +const static uint64_t SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID = 16504; // 43 +const static uint64_t SH_FLD_TRAPPED_PARALLEL_READ_NVLD = 16505; // 43 +const static uint64_t SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD = 16506; // 43 +const static uint64_t SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE = 16507; // 43 +const static uint64_t SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE = 16508; // 43 +const static uint64_t SH_FLD_TRAPPED_PCB_ADDRESS_PARITY = 16509; // 43 +const static uint64_t SH_FLD_TRAPPED_PCB_COMMAND_PARITY = 16510; // 43 +const static uint64_t SH_FLD_TRAPPED_PCB_WDATA_PARITY = 16511; // 43 +const static uint64_t SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16512; // 43 +const static uint64_t SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 16513; // 43 +const static uint64_t SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 16514; // 43 +const static uint64_t SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 16515; // 43 +const static uint64_t SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 16516; // 43 +const static uint64_t SH_FLD_TRAPPED_UL_P0 = 16517; // 43 +const static uint64_t SH_FLD_TRAPPED_UL_RDATA_PARITY = 16518; // 43 +const static uint64_t SH_FLD_TRASH_EN = 16519; // 12 +const static uint64_t SH_FLD_TRCD_CYCLES = 16520; // 8 +const static uint64_t SH_FLD_TRCD_CYCLES_LEN = 16521; // 8 +const static uint64_t SH_FLD_TRC_CMD_OVERRUN = 16522; // 1 +const static uint64_t SH_FLD_TRC_CYCLES = 16523; // 8 +const static uint64_t SH_FLD_TRC_CYCLES_LEN = 16524; // 8 +const static uint64_t SH_FLD_TRC_MODE = 16525; // 6 +const static uint64_t SH_FLD_TRC_MODE_LEN = 16526; // 6 +const static uint64_t SH_FLD_TRFC_CYCLES = 16527; // 8 +const static uint64_t SH_FLD_TRFC_CYCLES_LEN = 16528; // 8 +const static uint64_t SH_FLD_TRIG = 16529; // 17 +const static uint64_t SH_FLD_TRIG0_AND_MASK = 16530; // 90 +const static uint64_t SH_FLD_TRIG0_AND_MASK_LEN = 16531; // 90 +const static uint64_t SH_FLD_TRIG0_LEVEL_SEL = 16532; // 43 +const static uint64_t SH_FLD_TRIG0_LEVEL_SEL_LEN = 16533; // 43 +const static uint64_t SH_FLD_TRIG0_NOT_MODE = 16534; // 90 +const static uint64_t SH_FLD_TRIG0_OR_MASK = 16535; // 90 +const static uint64_t SH_FLD_TRIG0_OR_MASK_LEN = 16536; // 90 +const static uint64_t SH_FLD_TRIG1_AND_MASK = 16537; // 90 +const static uint64_t SH_FLD_TRIG1_AND_MASK_LEN = 16538; // 90 +const static uint64_t SH_FLD_TRIG1_LEVEL_SEL = 16539; // 43 +const static uint64_t SH_FLD_TRIG1_LEVEL_SEL_LEN = 16540; // 43 +const static uint64_t SH_FLD_TRIG1_NOT_MODE = 16541; // 90 +const static uint64_t SH_FLD_TRIG1_OR_MASK = 16542; // 90 +const static uint64_t SH_FLD_TRIG1_OR_MASK_LEN = 16543; // 90 +const static uint64_t SH_FLD_TRIGGER = 16544; // 55 +const static uint64_t SH_FLD_TRIGGER1 = 16545; // 24 +const static uint64_t SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL = 16546; // 43 +const static uint64_t SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL = 16547; // 43 +const static uint64_t SH_FLD_TRIGGER_OPCG_ON = 16548; // 129 +const static uint64_t SH_FLD_TRIG_FIR_HMI = 16549; // 96 +const static uint64_t SH_FLD_TRIG_SEL = 16550; // 43 +const static uint64_t SH_FLD_TRIG_SEL_LEN = 16551; // 43 +const static uint64_t SH_FLD_TRP_CYCLES = 16552; // 8 +const static uint64_t SH_FLD_TRP_CYCLES_LEN = 16553; // 8 +const static uint64_t SH_FLD_TRRD = 16554; // 8 +const static uint64_t SH_FLD_TRRD_LEN = 16555; // 8 +const static uint64_t SH_FLD_TRRD_SBG = 16556; // 8 +const static uint64_t SH_FLD_TRRD_SBG_LEN = 16557; // 8 +const static uint64_t SH_FLD_TRST_B_EQ0_ERR = 16558; // 1 +const static uint64_t SH_FLD_TRY_ATR_RO = 16559; // 1 +const static uint64_t SH_FLD_TSIZE = 16560; // 25 +const static uint64_t SH_FLD_TSIZE_4_6 = 16561; // 1 +const static uint64_t SH_FLD_TSIZE_4_6_LEN = 16562; // 1 +const static uint64_t SH_FLD_TSIZE_LEN = 16563; // 24 +const static uint64_t SH_FLD_TSIZE_MASK = 16564; // 8 +const static uint64_t SH_FLD_TSIZE_MASK_LEN = 16565; // 8 +const static uint64_t SH_FLD_TSIZE_MATCH = 16566; // 8 +const static uint64_t SH_FLD_TSIZE_MATCH_LEN = 16567; // 8 +const static uint64_t SH_FLD_TTAG_PARITY = 16568; // 2 +const static uint64_t SH_FLD_TTAG_PARITY_ERROR = 16569; // 2 +const static uint64_t SH_FLD_TTYPE = 16570; // 24 +const static uint64_t SH_FLD_TTYPE_LEN = 16571; // 24 +const static uint64_t SH_FLD_TTYPE_MATCH = 16572; // 8 +const static uint64_t SH_FLD_TTYPE_MATCH_LEN = 16573; // 8 +const static uint64_t SH_FLD_TTYPE_REPLACE = 16574; // 8 +const static uint64_t SH_FLD_TTYPE_REPLACE_LEN = 16575; // 8 +const static uint64_t SH_FLD_TVT0_PAGE_SIZE = 16576; // 1 +const static uint64_t SH_FLD_TVT0_PAGE_SIZE_LEN = 16577; // 1 +const static uint64_t SH_FLD_TVT0_SPARE = 16578; // 1 +const static uint64_t SH_FLD_TVT0_SPARE_LEN = 16579; // 1 +const static uint64_t SH_FLD_TVT0_TABLE_LEVEL = 16580; // 1 +const static uint64_t SH_FLD_TVT0_TABLE_LEVEL_LEN = 16581; // 1 +const static uint64_t SH_FLD_TVT0_TABLE_SIZE = 16582; // 1 +const static uint64_t SH_FLD_TVT0_TABLE_SIZE_LEN = 16583; // 1 +const static uint64_t SH_FLD_TVT0_XLAT_ADDR = 16584; // 1 +const static uint64_t SH_FLD_TVT0_XLAT_ADDR_LEN = 16585; // 1 +const static uint64_t SH_FLD_TVT_ADDR_RANGE_ERR_ESR = 16586; // 1 +const static uint64_t SH_FLD_TVT_ENTRY_INVALID_ESR = 16587; // 1 +const static uint64_t SH_FLD_TVT_PERR_ESR = 16588; // 1 +const static uint64_t SH_FLD_TWLDQSEN_CYCLES = 16589; // 8 +const static uint64_t SH_FLD_TWLDQSEN_CYCLES_LEN = 16590; // 8 +const static uint64_t SH_FLD_TWLO_TWLOE = 16591; // 8 +const static uint64_t SH_FLD_TWLO_TWLOE_LEN = 16592; // 8 +const static uint64_t SH_FLD_TWO_CYCLE_ADDR_EN = 16593; // 8 +const static uint64_t SH_FLD_TWRMRD_CYCLES = 16594; // 8 +const static uint64_t SH_FLD_TWRMRD_CYCLES_LEN = 16595; // 8 +const static uint64_t SH_FLD_TWSM_DIS = 16596; // 1 +const static uint64_t SH_FLD_TWSM_DIS_LEN = 16597; // 1 +const static uint64_t SH_FLD_TW_ATT_HPT_SAO_FOLD_DIS = 16598; // 1 +const static uint64_t SH_FLD_TW_ATT_RDX_NIO_FOLD_DIS = 16599; // 1 +const static uint64_t SH_FLD_TW_ATT_RDX_SAO_FOLD_DIS = 16600; // 1 +const static uint64_t SH_FLD_TW_ATT_RDX_TIO_FOLD_DIS = 16601; // 1 +const static uint64_t SH_FLD_TW_BUS0_STG0_SEL = 16602; // 1 +const static uint64_t SH_FLD_TW_BUS0_STG0_SEL_LEN = 16603; // 1 +const static uint64_t SH_FLD_TW_BUS0_STG1_SEL = 16604; // 1 +const static uint64_t SH_FLD_TW_BUS0_STG2_SEL = 16605; // 1 +const static uint64_t SH_FLD_TW_BUS1_STG0_SEL = 16606; // 1 +const static uint64_t SH_FLD_TW_BUS1_STG0_SEL_LEN = 16607; // 1 +const static uint64_t SH_FLD_TW_BUS1_STG1_SEL = 16608; // 1 +const static uint64_t SH_FLD_TW_BUS1_STG2_SEL = 16609; // 1 +const static uint64_t SH_FLD_TW_CXT_CAC_DIS = 16610; // 1 +const static uint64_t SH_FLD_TW_LCO_RDX_C_DIS = 16611; // 1 +const static uint64_t SH_FLD_TW_LCO_RDX_EN = 16612; // 1 +const static uint64_t SH_FLD_TW_LCO_RDX_PDE_EN = 16613; // 1 +const static uint64_t SH_FLD_TW_LCO_RDX_PWC_L2_DIS = 16614; // 1 +const static uint64_t SH_FLD_TW_LCO_RDX_PWC_L3_DIS = 16615; // 1 +const static uint64_t SH_FLD_TW_LCO_RDX_PWC_L4_DIS = 16616; // 1 +const static uint64_t SH_FLD_TW_LCO_RDX_P_DIS = 16617; // 1 +const static uint64_t SH_FLD_TW_PROT_ERR_CHK_DIS = 16618; // 1 +const static uint64_t SH_FLD_TW_PTE_UPD_INTR_EN = 16619; // 1 +const static uint64_t SH_FLD_TW_RDX_INT_PWC_DIS = 16620; // 1 +const static uint64_t SH_FLD_TW_RDX_INT_TLB_DIS = 16621; // 1 +const static uint64_t SH_FLD_TW_RDX_PWC_DIS = 16622; // 1 +const static uint64_t SH_FLD_TW_RDX_PWC_SPLIT_EN = 16623; // 1 +const static uint64_t SH_FLD_TW_RDX_PWC_VA_HASH = 16624; // 1 +const static uint64_t SH_FLD_TW_TIMEOUT_CHK_DIS = 16625; // 1 +const static uint64_t SH_FLD_TXAERR = 16626; // 6 +const static uint64_t SH_FLD_TXBERR = 16627; // 6 +const static uint64_t SH_FLD_TXCERR = 16628; // 6 +const static uint64_t SH_FLD_TXDERR = 16629; // 6 +const static uint64_t SH_FLD_TXEERR = 16630; // 6 +const static uint64_t SH_FLD_TXFERR = 16631; // 6 +const static uint64_t SH_FLD_TXGERR = 16632; // 6 +const static uint64_t SH_FLD_TXHERR = 16633; // 6 +const static uint64_t SH_FLD_TXIERR = 16634; // 6 +const static uint64_t SH_FLD_TXJERR = 16635; // 6 +const static uint64_t SH_FLD_TXKERR = 16636; // 6 +const static uint64_t SH_FLD_TXLERR = 16637; // 6 +const static uint64_t SH_FLD_TXMERR = 16638; // 6 +const static uint64_t SH_FLD_TXNERR = 16639; // 6 +const static uint64_t SH_FLD_TXOERR = 16640; // 6 +const static uint64_t SH_FLD_TXPERR = 16641; // 6 +const static uint64_t SH_FLD_TX_BUS_WIDTH = 16642; // 4 +const static uint64_t SH_FLD_TX_BUS_WIDTH_LEN = 16643; // 4 +const static uint64_t SH_FLD_TX_DATA_ECC_CORR_ENA = 16644; // 6 +const static uint64_t SH_FLD_TX_ECC_DATA_POISON_ENA = 16645; // 6 +const static uint64_t SH_FLD_TX_SLS_DISABLE = 16646; // 4 +const static uint64_t SH_FLD_TX_TRISTATE = 16647; // 8 +const static uint64_t SH_FLD_TX_TTYPE_PIB_MST_FSM_STATE_DISABLE = 16648; // 1 +const static uint64_t SH_FLD_TX_TTYPE_PIB_MST_IF_RESET = 16649; // 1 +const static uint64_t SH_FLD_TYPE = 16650; // 108 +const static uint64_t SH_FLD_TYPE_LEN = 16651; // 44 +const static uint64_t SH_FLD_TZQCS_CYCLES = 16652; // 8 +const static uint64_t SH_FLD_TZQCS_CYCLES_LEN = 16653; // 8 +const static uint64_t SH_FLD_TZQINIT_CYCLES = 16654; // 8 +const static uint64_t SH_FLD_TZQINIT_CYCLES_LEN = 16655; // 8 +const static uint64_t SH_FLD_UE1_0_OUT = 16656; // 4 +const static uint64_t SH_FLD_UE1_1_OUT = 16657; // 4 +const static uint64_t SH_FLD_UE1_2_OUT = 16658; // 4 +const static uint64_t SH_FLD_UE1_3_OUT = 16659; // 4 +const static uint64_t SH_FLD_UE1_4_OUT = 16660; // 4 +const static uint64_t SH_FLD_UE1_5_OUT = 16661; // 4 +const static uint64_t SH_FLD_UE1_6_OUT = 16662; // 4 +const static uint64_t SH_FLD_UE1_7_OUT = 16663; // 4 +const static uint64_t SH_FLD_UE2_0_OUT = 16664; // 4 +const static uint64_t SH_FLD_UE2_1_OUT = 16665; // 4 +const static uint64_t SH_FLD_UE2_2_OUT = 16666; // 4 +const static uint64_t SH_FLD_UE2_3_OUT = 16667; // 4 +const static uint64_t SH_FLD_UE2_4_OUT = 16668; // 4 +const static uint64_t SH_FLD_UE2_5_OUT = 16669; // 4 +const static uint64_t SH_FLD_UE2_6_OUT = 16670; // 4 +const static uint64_t SH_FLD_UE2_7_OUT = 16671; // 4 +const static uint64_t SH_FLD_UE_COUNT = 16672; // 2 +const static uint64_t SH_FLD_UE_COUNT_LEN = 16673; // 2 +const static uint64_t SH_FLD_UE_DISABLE = 16674; // 2 +const static uint64_t SH_FLD_UL_P0 = 16675; // 43 +const static uint64_t SH_FLD_UL_RDATA_PARITY = 16676; // 43 +const static uint64_t SH_FLD_UMAC_CRB_SUE = 16677; // 1 +const static uint64_t SH_FLD_UMAC_CRB_UE = 16678; // 1 +const static uint64_t SH_FLD_UMAC_LD_LINK_ERR = 16679; // 1 +const static uint64_t SH_FLD_UMAC_LINK_ABORT = 16680; // 1 +const static uint64_t SH_FLD_UMAC_MUX_SELECT = 16681; // 1 +const static uint64_t SH_FLD_UMAC_MUX_SELECT_LEN = 16682; // 1 +const static uint64_t SH_FLD_UMAC_RD_DISABLE_GROUP = 16683; // 1 +const static uint64_t SH_FLD_UMAC_RD_DISABLE_LN = 16684; // 1 +const static uint64_t SH_FLD_UMAC_RD_DISABLE_NN_RN = 16685; // 1 +const static uint64_t SH_FLD_UMAC_RD_DISABLE_VG_NOT_SYS = 16686; // 1 +const static uint64_t SH_FLD_UMAC_WC_INT_ADDR_UE = 16687; // 1 +const static uint64_t SH_FLD_UMAC_WR_DISABLE_GROUP = 16688; // 1 +const static uint64_t SH_FLD_UMAC_WR_DISABLE_LN = 16689; // 1 +const static uint64_t SH_FLD_UMAC_WR_DISABLE_NN_RN = 16690; // 1 +const static uint64_t SH_FLD_UMAC_WR_DISABLE_VG_NOT_SYS = 16691; // 1 +const static uint64_t SH_FLD_UNCORR_ERROR = 16692; // 1 +const static uint64_t SH_FLD_UNEXPECTEDCRESP = 16693; // 9 +const static uint64_t SH_FLD_UNEXPECTEDCRESP_MASK = 16694; // 9 +const static uint64_t SH_FLD_UNEXPECTED_PB = 16695; // 4 +const static uint64_t SH_FLD_UNEXPECT_DATA = 16696; // 1 +const static uint64_t SH_FLD_UNIT1 = 16697; // 215 +const static uint64_t SH_FLD_UNIT10 = 16698; // 215 +const static uint64_t SH_FLD_UNIT2 = 16699; // 215 +const static uint64_t SH_FLD_UNIT3 = 16700; // 215 +const static uint64_t SH_FLD_UNIT4 = 16701; // 215 +const static uint64_t SH_FLD_UNIT5 = 16702; // 215 +const static uint64_t SH_FLD_UNIT6 = 16703; // 215 +const static uint64_t SH_FLD_UNIT7 = 16704; // 215 +const static uint64_t SH_FLD_UNIT8 = 16705; // 215 +const static uint64_t SH_FLD_UNIT9 = 16706; // 215 +const static uint64_t SH_FLD_UNIT_REGION_CLKCMD_ENABLE = 16707; // 43 +const static uint64_t SH_FLD_UNLOAD_CLK_DISABLE = 16708; // 116 +const static uint64_t SH_FLD_UNLOAD_SEL = 16709; // 116 +const static uint64_t SH_FLD_UNLOAD_SEL_LEN = 16710; // 116 +const static uint64_t SH_FLD_UNSOLICITED_CRESP = 16711; // 3 +const static uint64_t SH_FLD_UNSOLICITED_PBDATA = 16712; // 1 +const static uint64_t SH_FLD_UNSOLICITIEDPBDATA = 16713; // 9 +const static uint64_t SH_FLD_UNSOLICITIEDPBDATA_MASK = 16714; // 9 +const static uint64_t SH_FLD_UNTRUSTED = 16715; // 4 +const static uint64_t SH_FLD_UNTRUSTED_LEN = 16716; // 4 +const static uint64_t SH_FLD_UNUSED = 16717; // 133 +const static uint64_t SH_FLD_UNUSED0 = 16718; // 1 +const static uint64_t SH_FLD_UNUSED1 = 16719; // 48 +const static uint64_t SH_FLD_UNUSED1119 = 16720; // 43 +const static uint64_t SH_FLD_UNUSED1119_LEN = 16721; // 43 +const static uint64_t SH_FLD_UNUSED1520 = 16722; // 43 +const static uint64_t SH_FLD_UNUSED1520_LEN = 16723; // 43 +const static uint64_t SH_FLD_UNUSED1_LEN = 16724; // 45 +const static uint64_t SH_FLD_UNUSED2 = 16725; // 50 +const static uint64_t SH_FLD_UNUSED23_31 = 16726; // 7 +const static uint64_t SH_FLD_UNUSED23_31_LEN = 16727; // 7 +const static uint64_t SH_FLD_UNUSED2_LEN = 16728; // 44 +const static uint64_t SH_FLD_UNUSED3 = 16729; // 6 +const static uint64_t SH_FLD_UNUSED3_LEN = 16730; // 1 +const static uint64_t SH_FLD_UNUSED4 = 16731; // 9 +const static uint64_t SH_FLD_UNUSED41_63 = 16732; // 43 +const static uint64_t SH_FLD_UNUSED41_63_LEN = 16733; // 43 +const static uint64_t SH_FLD_UNUSED46 = 16734; // 43 +const static uint64_t SH_FLD_UNUSED4_LEN = 16735; // 1 +const static uint64_t SH_FLD_UNUSED5 = 16736; // 7 +const static uint64_t SH_FLD_UNUSED50 = 16737; // 2 +const static uint64_t SH_FLD_UNUSED51 = 16738; // 2 +const static uint64_t SH_FLD_UNUSED63 = 16739; // 3 +const static uint64_t SH_FLD_UNUSED88 = 16740; // 3 +const static uint64_t SH_FLD_UNUSED88_LEN = 16741; // 3 +const static uint64_t SH_FLD_UNUSED_0 = 16742; // 44 +const static uint64_t SH_FLD_UNUSED_0B = 16743; // 43 +const static uint64_t SH_FLD_UNUSED_0D = 16744; // 36 +const static uint64_t SH_FLD_UNUSED_1 = 16745; // 44 +const static uint64_t SH_FLD_UNUSED_10B = 16746; // 35 +const static uint64_t SH_FLD_UNUSED_11B = 16747; // 36 +const static uint64_t SH_FLD_UNUSED_12B = 16748; // 37 +const static uint64_t SH_FLD_UNUSED_13B = 16749; // 37 +const static uint64_t SH_FLD_UNUSED_14B = 16750; // 43 +const static uint64_t SH_FLD_UNUSED_16_22 = 16751; // 1 +const static uint64_t SH_FLD_UNUSED_16_22_LEN = 16752; // 1 +const static uint64_t SH_FLD_UNUSED_17B = 16753; // 43 +const static uint64_t SH_FLD_UNUSED_18B = 16754; // 43 +const static uint64_t SH_FLD_UNUSED_19B = 16755; // 43 +const static uint64_t SH_FLD_UNUSED_1B = 16756; // 43 +const static uint64_t SH_FLD_UNUSED_1D = 16757; // 36 +const static uint64_t SH_FLD_UNUSED_2 = 16758; // 1 +const static uint64_t SH_FLD_UNUSED_20B = 16759; // 42 +const static uint64_t SH_FLD_UNUSED_21B = 16760; // 43 +const static uint64_t SH_FLD_UNUSED_22B = 16761; // 43 +const static uint64_t SH_FLD_UNUSED_23B = 16762; // 43 +const static uint64_t SH_FLD_UNUSED_24B = 16763; // 43 +const static uint64_t SH_FLD_UNUSED_25B = 16764; // 43 +const static uint64_t SH_FLD_UNUSED_26B = 16765; // 43 +const static uint64_t SH_FLD_UNUSED_26_31 = 16766; // 1 +const static uint64_t SH_FLD_UNUSED_26_31_LEN = 16767; // 1 +const static uint64_t SH_FLD_UNUSED_27B = 16768; // 43 +const static uint64_t SH_FLD_UNUSED_28B = 16769; // 43 +const static uint64_t SH_FLD_UNUSED_29B = 16770; // 43 +const static uint64_t SH_FLD_UNUSED_2B = 16771; // 43 +const static uint64_t SH_FLD_UNUSED_2D = 16772; // 36 +const static uint64_t SH_FLD_UNUSED_3 = 16773; // 1 +const static uint64_t SH_FLD_UNUSED_30B = 16774; // 43 +const static uint64_t SH_FLD_UNUSED_31B = 16775; // 43 +const static uint64_t SH_FLD_UNUSED_39_43 = 16776; // 1 +const static uint64_t SH_FLD_UNUSED_39_43_LEN = 16777; // 1 +const static uint64_t SH_FLD_UNUSED_3D = 16778; // 36 +const static uint64_t SH_FLD_UNUSED_47_51 = 16779; // 1 +const static uint64_t SH_FLD_UNUSED_47_51_LEN = 16780; // 1 +const static uint64_t SH_FLD_UNUSED_4_15 = 16781; // 1 +const static uint64_t SH_FLD_UNUSED_4_15_LEN = 16782; // 1 +const static uint64_t SH_FLD_UNUSED_53 = 16783; // 1 +const static uint64_t SH_FLD_UNUSED_5B = 16784; // 1 +const static uint64_t SH_FLD_UNUSED_6B = 16785; // 1 +const static uint64_t SH_FLD_UNUSED_7B = 16786; // 27 +const static uint64_t SH_FLD_UNUSED_8B = 16787; // 31 +const static uint64_t SH_FLD_UNUSED_8_14 = 16788; // 1 +const static uint64_t SH_FLD_UNUSED_8_14_LEN = 16789; // 1 +const static uint64_t SH_FLD_UNUSED_9B = 16790; // 33 +const static uint64_t SH_FLD_UNUSED_LEN = 16791; // 90 +const static uint64_t SH_FLD_UPDATE_COMPLETE = 16792; // 6 +const static uint64_t SH_FLD_UPDATE_ERR = 16793; // 2 +const static uint64_t SH_FLD_UPSTREAM = 16794; // 4 +const static uint64_t SH_FLD_USERDEF_CFG = 16795; // 6 +const static uint64_t SH_FLD_USERDEF_CFG_LEN = 16796; // 6 +const static uint64_t SH_FLD_USERDEF_TIMEOUT = 16797; // 6 +const static uint64_t SH_FLD_USERDEF_TIMEOUT_LEN = 16798; // 6 +const static uint64_t SH_FLD_USER_FILTER_MASK = 16799; // 6 +const static uint64_t SH_FLD_USER_FILTER_MASK_LEN = 16800; // 6 +const static uint64_t SH_FLD_USE_ARY_CLK_DURING_FILL = 16801; // 43 +const static uint64_t SH_FLD_USE_FOR_SCAN = 16802; // 43 +const static uint64_t SH_FLD_USE_OSC_OBSERVATION = 16803; // 1 +const static uint64_t SH_FLD_USE_OSC_OBSERVATION_LEN = 16804; // 1 +const static uint64_t SH_FLD_USE_PECE = 16805; // 24 +const static uint64_t SH_FLD_USE_PECE_LEN = 16806; // 24 +const static uint64_t SH_FLD_USE_PREV_COARSE_VAL = 16807; // 4 +const static uint64_t SH_FLD_USE_REC_LIMIT = 16808; // 24 +const static uint64_t SH_FLD_USE_SLS_AS_SPR = 16809; // 4 +const static uint64_t SH_FLD_USE_TB_STEP_SYNC = 16810; // 1 +const static uint64_t SH_FLD_USE_TB_SYNC_MECHANISM = 16811; // 1 +const static uint64_t SH_FLD_USE_WATCH_TO_READ_CTRL_ARY = 16812; // 2 +const static uint64_t SH_FLD_UT = 16813; // 24 +const static uint64_t SH_FLD_VALID = 16814; // 68 +const static uint64_t SH_FLD_VALID_ATRGPA0 = 16815; // 256 +const static uint64_t SH_FLD_VALID_ATRGPA1 = 16816; // 256 +const static uint64_t SH_FLD_VALID_ATSD = 16817; // 256 +const static uint64_t SH_FLD_VALID_ENTRY = 16818; // 1 +const static uint64_t SH_FLD_VALUE = 16819; // 48 +const static uint64_t SH_FLD_VALUES0 = 16820; // 16 +const static uint64_t SH_FLD_VALUES0_LEN = 16821; // 16 +const static uint64_t SH_FLD_VALUES1 = 16822; // 16 +const static uint64_t SH_FLD_VALUES1_LEN = 16823; // 16 +const static uint64_t SH_FLD_VALUES2 = 16824; // 16 +const static uint64_t SH_FLD_VALUES2_LEN = 16825; // 16 +const static uint64_t SH_FLD_VALUES3 = 16826; // 16 +const static uint64_t SH_FLD_VALUES3_LEN = 16827; // 16 +const static uint64_t SH_FLD_VALUES4 = 16828; // 16 +const static uint64_t SH_FLD_VALUES4_LEN = 16829; // 16 +const static uint64_t SH_FLD_VALUES5 = 16830; // 16 +const static uint64_t SH_FLD_VALUES5_LEN = 16831; // 16 +const static uint64_t SH_FLD_VALUES6 = 16832; // 16 +const static uint64_t SH_FLD_VALUES6_LEN = 16833; // 16 +const static uint64_t SH_FLD_VALUES7 = 16834; // 16 +const static uint64_t SH_FLD_VALUES7_LEN = 16835; // 16 +const static uint64_t SH_FLD_VALUE_LEN = 16836; // 48 +const static uint64_t SH_FLD_VAS_LOCAL_XSTOP = 16837; // 1 +const static uint64_t SH_FLD_VBGENDOC = 16838; // 3 +const static uint64_t SH_FLD_VBGENDOC_LEN = 16839; // 3 +const static uint64_t SH_FLD_VCORANGE = 16840; // 10 +const static uint64_t SH_FLD_VCORANGE_LEN = 16841; // 10 +const static uint64_t SH_FLD_VCOSEL = 16842; // 10 +const static uint64_t SH_FLD_VCS_PFETS_DISABLED_SENSE = 16843; // 30 +const static uint64_t SH_FLD_VCS_PFETS_ENABLED_SENSE = 16844; // 30 +const static uint64_t SH_FLD_VCS_PFET_ENABLE_VALUE = 16845; // 30 +const static uint64_t SH_FLD_VCS_PFET_ENABLE_VALUE_LEN = 16846; // 30 +const static uint64_t SH_FLD_VCS_PFET_FORCE_STATE = 16847; // 30 +const static uint64_t SH_FLD_VCS_PFET_FORCE_STATE_LEN = 16848; // 30 +const static uint64_t SH_FLD_VCS_PFET_SEL_OVERRIDE = 16849; // 30 +const static uint64_t SH_FLD_VCS_PFET_SEL_VALUE = 16850; // 30 +const static uint64_t SH_FLD_VCS_PFET_SEL_VALUE_LEN = 16851; // 30 +const static uint64_t SH_FLD_VCS_PFET_VAL_OVERRIDE = 16852; // 30 +const static uint64_t SH_FLD_VCS_PG_SEL = 16853; // 30 +const static uint64_t SH_FLD_VCS_PG_SEL_LEN = 16854; // 30 +const static uint64_t SH_FLD_VCS_PG_STATE = 16855; // 30 +const static uint64_t SH_FLD_VCS_PG_STATE_LEN = 16856; // 30 +const static uint64_t SH_FLD_VCS_VOFF_SEL = 16857; // 30 +const static uint64_t SH_FLD_VCS_VOFF_SEL_LEN = 16858; // 30 +const static uint64_t SH_FLD_VC_CRD_AVAIL_PERR = 16859; // 1 +const static uint64_t SH_FLD_VC_CRD_PERR = 16860; // 1 +const static uint64_t SH_FLD_VC_FATAL_ERROR_0_1 = 16861; // 1 +const static uint64_t SH_FLD_VC_FATAL_ERROR_0_1_LEN = 16862; // 1 +const static uint64_t SH_FLD_VC_INFO_ERROR_0_1 = 16863; // 1 +const static uint64_t SH_FLD_VC_INFO_ERROR_0_1_LEN = 16864; // 1 +const static uint64_t SH_FLD_VC_PRIORITY_LIMIT_0_3 = 16865; // 1 +const static uint64_t SH_FLD_VC_PRIORITY_LIMIT_0_3_LEN = 16866; // 1 +const static uint64_t SH_FLD_VC_RECOV_ERROR_0_1 = 16867; // 1 +const static uint64_t SH_FLD_VC_RECOV_ERROR_0_1_LEN = 16868; // 1 +const static uint64_t SH_FLD_VDD2VIO_LVL_FENCE_DC = 16869; // 3 +const static uint64_t SH_FLD_VDD_NEST_OBSERVE = 16870; // 1 +const static uint64_t SH_FLD_VDD_PFETS_DISABLED_SENSE = 16871; // 30 +const static uint64_t SH_FLD_VDD_PFETS_ENABLED_SENSE = 16872; // 30 +const static uint64_t SH_FLD_VDD_PFET_ENABLE_VALUE = 16873; // 30 +const static uint64_t SH_FLD_VDD_PFET_ENABLE_VALUE_LEN = 16874; // 30 +const static uint64_t SH_FLD_VDD_PFET_FORCE_STATE = 16875; // 30 +const static uint64_t SH_FLD_VDD_PFET_FORCE_STATE_LEN = 16876; // 30 +const static uint64_t SH_FLD_VDD_PFET_REGULATION_FINGER_EN = 16877; // 30 +const static uint64_t SH_FLD_VDD_PFET_REGULATION_FINGER_VALUE = 16878; // 30 +const static uint64_t SH_FLD_VDD_PFET_SEL_OVERRIDE = 16879; // 30 +const static uint64_t SH_FLD_VDD_PFET_SEL_VALUE = 16880; // 30 +const static uint64_t SH_FLD_VDD_PFET_SEL_VALUE_LEN = 16881; // 30 +const static uint64_t SH_FLD_VDD_PFET_VAL_OVERRIDE = 16882; // 30 +const static uint64_t SH_FLD_VDD_PG_SEL = 16883; // 30 +const static uint64_t SH_FLD_VDD_PG_SEL_LEN = 16884; // 30 +const static uint64_t SH_FLD_VDD_PG_STATE = 16885; // 30 +const static uint64_t SH_FLD_VDD_PG_STATE_LEN = 16886; // 30 +const static uint64_t SH_FLD_VDD_VOFF_SEL = 16887; // 30 +const static uint64_t SH_FLD_VDD_VOFF_SEL_LEN = 16888; // 30 +const static uint64_t SH_FLD_VDM_DISABLE = 16889; // 30 +const static uint64_t SH_FLD_VDM_DROOP_LARGE = 16890; // 6 +const static uint64_t SH_FLD_VDM_DROOP_LARGE_LEN = 16891; // 6 +const static uint64_t SH_FLD_VDM_DROOP_SMALL = 16892; // 6 +const static uint64_t SH_FLD_VDM_DROOP_SMALL_LEN = 16893; // 6 +const static uint64_t SH_FLD_VDM_DROOP_XTREME = 16894; // 6 +const static uint64_t SH_FLD_VDM_DROOP_XTREME_LEN = 16895; // 6 +const static uint64_t SH_FLD_VDM_EXTREME_DROOP_CTR = 16896; // 12 +const static uint64_t SH_FLD_VDM_EXTREME_DROOP_CTR_LEN = 16897; // 12 +const static uint64_t SH_FLD_VDM_LARGE_DROOP_CTR = 16898; // 12 +const static uint64_t SH_FLD_VDM_LARGE_DROOP_CTR_LEN = 16899; // 12 +const static uint64_t SH_FLD_VDM_LCL_SAMPLE_EN = 16900; // 12 +const static uint64_t SH_FLD_VDM_NO_DROOP_CTR = 16901; // 12 +const static uint64_t SH_FLD_VDM_NO_DROOP_CTR_LEN = 16902; // 12 +const static uint64_t SH_FLD_VDM_OVERVOLT = 16903; // 6 +const static uint64_t SH_FLD_VDM_OVERVOLT_CTR = 16904; // 12 +const static uint64_t SH_FLD_VDM_OVERVOLT_CTR_LEN = 16905; // 12 +const static uint64_t SH_FLD_VDM_OVERVOLT_LEN = 16906; // 6 +const static uint64_t SH_FLD_VDM_POWERON = 16907; // 30 +const static uint64_t SH_FLD_VDM_SMALL_DROOP_CTR = 16908; // 12 +const static uint64_t SH_FLD_VDM_SMALL_DROOP_CTR_LEN = 16909; // 12 +const static uint64_t SH_FLD_VDM_VID_COMPARE = 16910; // 6 +const static uint64_t SH_FLD_VDM_VID_COMPARE_LEN = 16911; // 6 +const static uint64_t SH_FLD_VECTOR_GROUP_EPSILON = 16912; // 8 +const static uint64_t SH_FLD_VECTOR_GROUP_EPSILON_LEN = 16913; // 8 +const static uint64_t SH_FLD_VG = 16914; // 1 +const static uint64_t SH_FLD_VG_COUNT = 16915; // 2 +const static uint64_t SH_FLD_VG_COUNT_LEN = 16916; // 2 +const static uint64_t SH_FLD_VG_TARGE = 16917; // 1 +const static uint64_t SH_FLD_VG_TARGET_SEL = 16918; // 24 +const static uint64_t SH_FLD_VG_TARGE_LEN = 16919; // 1 +const static uint64_t SH_FLD_VID_COMPARE_MAX = 16920; // 6 +const static uint64_t SH_FLD_VID_COMPARE_MAX_LEN = 16921; // 6 +const static uint64_t SH_FLD_VID_COMPARE_MIN = 16922; // 6 +const static uint64_t SH_FLD_VID_COMPARE_MIN_LEN = 16923; // 6 +const static uint64_t SH_FLD_VITAL_AL = 16924; // 43 +const static uint64_t SH_FLD_VITAL_PHASE = 16925; // 43 +const static uint64_t SH_FLD_VITAL_SCAN = 16926; // 43 +const static uint64_t SH_FLD_VITAL_SCAN_IN = 16927; // 43 +const static uint64_t SH_FLD_VITAL_THOLD = 16928; // 43 +const static uint64_t SH_FLD_VITL = 16929; // 43 +const static uint64_t SH_FLD_VITL_CLKOFF = 16930; // 43 +const static uint64_t SH_FLD_VOFF_CFG = 16931; // 6 +const static uint64_t SH_FLD_VOFF_CFG_LEN = 16932; // 6 +const static uint64_t SH_FLD_VOLT_MODEREG_PARITY_MASK = 16933; // 43 +const static uint64_t SH_FLD_VP = 16934; // 1 +const static uint64_t SH_FLD_VPC_DMA_ORDERING_TAG = 16935; // 1 +const static uint64_t SH_FLD_VPC_DMA_ORDERING_TAG_LEN = 16936; // 1 +const static uint64_t SH_FLD_VPC_LD_RMT_ORDERING_TAG = 16937; // 1 +const static uint64_t SH_FLD_VPC_LD_RMT_ORDERING_TAG_LEN = 16938; // 1 +const static uint64_t SH_FLD_VPC_LD_RSP_ORDERING_TAG = 16939; // 1 +const static uint64_t SH_FLD_VPC_LD_RSP_ORDERING_TAG_LEN = 16940; // 1 +const static uint64_t SH_FLD_VPC_ST_RMT_ORDERING_TAG = 16941; // 1 +const static uint64_t SH_FLD_VPC_ST_RMT_ORDERING_TAG_LEN = 16942; // 1 +const static uint64_t SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG = 16943; // 1 +const static uint64_t SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG_LEN = 16944; // 1 +const static uint64_t SH_FLD_VPD_DMA_READ = 16945; // 1 +const static uint64_t SH_FLD_VPD_DMA_READ_LEN = 16946; // 1 +const static uint64_t SH_FLD_VPD_DMA_WRITE = 16947; // 1 +const static uint64_t SH_FLD_VPD_DMA_WRITE_LEN = 16948; // 1 +const static uint64_t SH_FLD_VPROTH = 16949; // 8 +const static uint64_t SH_FLD_VPROTH_CTL = 16950; // 8 +const static uint64_t SH_FLD_VPROTH_CTL_LEN = 16951; // 8 +const static uint64_t SH_FLD_VREF = 16952; // 1 +const static uint64_t SH_FLD_VREFDQ0D = 16953; // 8 +const static uint64_t SH_FLD_VREFDQ0DSGN = 16954; // 8 +const static uint64_t SH_FLD_VREFDQ0D_LEN = 16955; // 8 +const static uint64_t SH_FLD_VREFDQ1D = 16956; // 8 +const static uint64_t SH_FLD_VREFDQ1DSGN = 16957; // 8 +const static uint64_t SH_FLD_VREFDQ1D_LEN = 16958; // 8 +const static uint64_t SH_FLD_VREFTUNE = 16959; // 3 +const static uint64_t SH_FLD_VREFTUNE_LEN = 16960; // 3 +const static uint64_t SH_FLD_VREF_LEN = 16961; // 1 +const static uint64_t SH_FLD_VREGBYP = 16962; // 6 +const static uint64_t SH_FLD_VREGBYPASS = 16963; // 4 +const static uint64_t SH_FLD_VREGENABLE_N = 16964; // 4 +const static uint64_t SH_FLD_VREG_S = 16965; // 8 +const static uint64_t SH_FLD_VSEL = 16966; // 10 +const static uint64_t SH_FLD_VSEL_LEN = 16967; // 10 +const static uint64_t SH_FLD_VST_TYPE = 16968; // 1 +const static uint64_t SH_FLD_VST_TYPE_LEN = 16969; // 1 +const static uint64_t SH_FLD_VTARGET = 16970; // 4 +const static uint64_t SH_FLD_VTARGET_LEN = 16971; // 4 +const static uint64_t SH_FLD_V_TARG = 16972; // 1 +const static uint64_t SH_FLD_V_TARG_LEN = 16973; // 1 +const static uint64_t SH_FLD_W0_COUNT = 16974; // 12 +const static uint64_t SH_FLD_W0_COUNT_LEN = 16975; // 12 +const static uint64_t SH_FLD_W1_COUNT = 16976; // 12 +const static uint64_t SH_FLD_W1_COUNT_LEN = 16977; // 12 +const static uint64_t SH_FLD_WAITING = 16978; // 2 +const static uint64_t SH_FLD_WAIT_ALLWAYS = 16979; // 129 +const static uint64_t SH_FLD_WAIT_CYCLES = 16980; // 172 +const static uint64_t SH_FLD_WAIT_CYCLES_LEN = 16981; // 172 +const static uint64_t SH_FLD_WANT_CACHE_DISABLE = 16982; // 4 +const static uint64_t SH_FLD_WANT_INVALIDATE = 16983; // 3 +const static uint64_t SH_FLD_WARB_INVALID_CASE_ERROR = 16984; // 2 +const static uint64_t SH_FLD_WARM_START_COMPLETED = 16985; // 2 +const static uint64_t SH_FLD_WAT0_EVENT_SELECT = 16986; // 8 +const static uint64_t SH_FLD_WAT0_EVENT_SELECT_LEN = 16987; // 8 +const static uint64_t SH_FLD_WAT0_EVENT_SELECT_MCA = 16988; // 8 +const static uint64_t SH_FLD_WAT0_EVENT_SELECT_MCA_LEN = 16989; // 8 +const static uint64_t SH_FLD_WAT0_EVENT_SELECT_NEST = 16990; // 8 +const static uint64_t SH_FLD_WAT0_EVENT_SELECT_NEST_LEN = 16991; // 8 +const static uint64_t SH_FLD_WAT1_EVENT_SELECT = 16992; // 8 +const static uint64_t SH_FLD_WAT1_EVENT_SELECT_LEN = 16993; // 8 +const static uint64_t SH_FLD_WAT1_EVENT_SELECT_MCA = 16994; // 8 +const static uint64_t SH_FLD_WAT1_EVENT_SELECT_MCA_LEN = 16995; // 8 +const static uint64_t SH_FLD_WAT1_EVENT_SELECT_NEST = 16996; // 8 +const static uint64_t SH_FLD_WAT1_EVENT_SELECT_NEST_LEN = 16997; // 8 +const static uint64_t SH_FLD_WATCHDOG_ENABLE = 16998; // 43 +const static uint64_t SH_FLD_WATCHDOG_SEL = 16999; // 17 +const static uint64_t SH_FLD_WATCHDOG_SEL_LEN = 17000; // 17 +const static uint64_t SH_FLD_WATERMARK_REG_0 = 17001; // 2 +const static uint64_t SH_FLD_WATERMARK_REG_0_LEN = 17002; // 2 +const static uint64_t SH_FLD_WATERMARK_REG_1 = 17003; // 1 +const static uint64_t SH_FLD_WATERMARK_REG_1_LEN = 17004; // 1 +const static uint64_t SH_FLD_WATERMARK_REG_2 = 17005; // 1 +const static uint64_t SH_FLD_WATERMARK_REG_2_LEN = 17006; // 1 +const static uint64_t SH_FLD_WATERMARK_REG_3 = 17007; // 1 +const static uint64_t SH_FLD_WATERMARK_REG_3_LEN = 17008; // 1 +const static uint64_t SH_FLD_WAT_DEBUG_ATTN = 17009; // 2 +const static uint64_t SH_FLD_WAT_DEBUG_REG_PE = 17010; // 2 +const static uint64_t SH_FLD_WAT_ERROR = 17011; // 16 +const static uint64_t SH_FLD_WAT_EVENT_ENABLE = 17012; // 8 +const static uint64_t SH_FLD_WAT_EVENT_ENABLE_MCA = 17013; // 8 +const static uint64_t SH_FLD_WAT_EVENT_ENABLE_NEST = 17014; // 8 +const static uint64_t SH_FLD_WAT_SPARE1 = 17015; // 8 +const static uint64_t SH_FLD_WAT_SPARE1_LEN = 17016; // 8 +const static uint64_t SH_FLD_WAT_SPARE1_MCA = 17017; // 8 +const static uint64_t SH_FLD_WAT_SPARE1_MCA_LEN = 17018; // 8 +const static uint64_t SH_FLD_WAT_SPARE1_NEST = 17019; // 8 +const static uint64_t SH_FLD_WAT_SPARE1_NEST_LEN = 17020; // 8 +const static uint64_t SH_FLD_WBMGR_DBG_0_SELECT = 17021; // 8 +const static uint64_t SH_FLD_WBMGR_DBG_1_SELECT = 17022; // 8 +const static uint64_t SH_FLD_WBRD_DEBUG_0_SELECT = 17023; // 8 +const static uint64_t SH_FLD_WBRD_DEBUG_1_SELECT = 17024; // 8 +const static uint64_t SH_FLD_WC = 17025; // 8 +const static uint64_t SH_FLD_WC_BS_BAR = 17026; // 1 +const static uint64_t SH_FLD_WC_BS_BAR_LEN = 17027; // 1 +const static uint64_t SH_FLD_WC_CERR_BIT10 = 17028; // 1 +const static uint64_t SH_FLD_WC_CERR_BIT11 = 17029; // 1 +const static uint64_t SH_FLD_WC_CERR_BIT12 = 17030; // 1 +const static uint64_t SH_FLD_WC_CERR_BIT13 = 17031; // 1 +const static uint64_t SH_FLD_WC_CERR_BIT14 = 17032; // 1 +const static uint64_t SH_FLD_WC_CERR_BIT15 = 17033; // 1 +const static uint64_t SH_FLD_WC_CERR_BIT16 = 17034; // 1 +const static uint64_t SH_FLD_WC_CERR_BIT17 = 17035; // 1 +const static uint64_t SH_FLD_WC_CERR_BIT4 = 17036; // 1 +const static uint64_t SH_FLD_WC_CERR_BIT5 = 17037; // 1 +const static uint64_t SH_FLD_WC_CERR_BIT6 = 17038; // 1 +const static uint64_t SH_FLD_WC_CERR_BIT7 = 17039; // 1 +const static uint64_t SH_FLD_WC_CERR_BIT8 = 17040; // 1 +const static uint64_t SH_FLD_WC_CERR_BIT9 = 17041; // 1 +const static uint64_t SH_FLD_WC_CERR_RESET = 17042; // 1 +const static uint64_t SH_FLD_WC_CERR_UNUSEDBITS = 17043; // 1 +const static uint64_t SH_FLD_WC_CERR_UNUSEDBITS_LEN = 17044; // 1 +const static uint64_t SH_FLD_WC_ECC_CE_ERROR = 17045; // 2 +const static uint64_t SH_FLD_WC_ECC_SUE_ERROR = 17046; // 2 +const static uint64_t SH_FLD_WC_ECC_UE_ERROR = 17047; // 2 +const static uint64_t SH_FLD_WC_LOGIC_HW_ERROR = 17048; // 2 +const static uint64_t SH_FLD_WC_MASK = 17049; // 8 +const static uint64_t SH_FLD_WC_TRACE_GROUP_SEL_HI = 17050; // 1 +const static uint64_t SH_FLD_WC_TRACE_GROUP_SEL_HI_LEN = 17051; // 1 +const static uint64_t SH_FLD_WC_TRACE_GROUP_SEL_LO = 17052; // 1 +const static uint64_t SH_FLD_WC_TRACE_GROUP_SEL_LO_LEN = 17053; // 1 +const static uint64_t SH_FLD_WC_TRACE_INT_DATA_HI = 17054; // 1 +const static uint64_t SH_FLD_WC_TRACE_INT_DATA_LO = 17055; // 1 +const static uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_01 = 17056; // 1 +const static uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_01_LEN = 17057; // 1 +const static uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_23 = 17058; // 1 +const static uint64_t SH_FLD_WC_TRACE_TRIGGER_SEL_23_LEN = 17059; // 1 +const static uint64_t SH_FLD_WDATA = 17060; // 1 +const static uint64_t SH_FLD_WDATA_LEN = 17061; // 1 +const static uint64_t SH_FLD_WDFCFG_PE = 17062; // 8 +const static uint64_t SH_FLD_WDF_ASYNC_ERROR = 17063; // 8 +const static uint64_t SH_FLD_WDF_ASYNC_INTERFACE_ERROR = 17064; // 8 +const static uint64_t SH_FLD_WDF_BUFFER_CE = 17065; // 8 +const static uint64_t SH_FLD_WDF_BUFFER_SUE = 17066; // 8 +const static uint64_t SH_FLD_WDF_BUFFER_UE = 17067; // 8 +const static uint64_t SH_FLD_WDF_ERR_INJECT0 = 17068; // 8 +const static uint64_t SH_FLD_WDF_ERR_INJECT0_LEN = 17069; // 8 +const static uint64_t SH_FLD_WDF_MISC_REGISTER_PARITY_ERROR = 17070; // 8 +const static uint64_t SH_FLD_WDF_OVERRUN_ERROR_0 = 17071; // 8 +const static uint64_t SH_FLD_WDF_OVERRUN_ERROR_1 = 17072; // 8 +const static uint64_t SH_FLD_WDF_SCOM_SEQUENCE_ERROR = 17073; // 8 +const static uint64_t SH_FLD_WDF_STATE_MACHINE_ERROR = 17074; // 8 +const static uint64_t SH_FLD_WECR_PE = 17075; // 8 +const static uint64_t SH_FLD_WHICH_8BECK = 17076; // 8 +const static uint64_t SH_FLD_WHICH_8BECK_LEN = 17077; // 8 +const static uint64_t SH_FLD_WILDCARD = 17078; // 6 +const static uint64_t SH_FLD_WINDOW_SELECT = 17079; // 3 +const static uint64_t SH_FLD_WINDOW_SELECT_LEN = 17080; // 3 +const static uint64_t SH_FLD_WIRETEST_DONE = 17081; // 4 +const static uint64_t SH_FLD_WIRETEST_FAILED = 17082; // 4 +const static uint64_t SH_FLD_WITH_ADDRESS_0 = 17083; // 2 +const static uint64_t SH_FLD_WITH_ADDRESS_1 = 17084; // 1 +const static uint64_t SH_FLD_WITH_ADDRESS_2 = 17085; // 1 +const static uint64_t SH_FLD_WITH_ADDRESS_3 = 17086; // 1 +const static uint64_t SH_FLD_WITH_START_0 = 17087; // 2 +const static uint64_t SH_FLD_WITH_START_1 = 17088; // 1 +const static uint64_t SH_FLD_WITH_START_2 = 17089; // 1 +const static uint64_t SH_FLD_WITH_START_3 = 17090; // 1 +const static uint64_t SH_FLD_WITH_STOP_0 = 17091; // 2 +const static uint64_t SH_FLD_WITH_STOP_1 = 17092; // 1 +const static uint64_t SH_FLD_WITH_STOP_2 = 17093; // 1 +const static uint64_t SH_FLD_WITH_STOP_3 = 17094; // 1 +const static uint64_t SH_FLD_WI_MACHINE_HANG = 17095; // 12 +const static uint64_t SH_FLD_WI_MACHINE_W4DT_HANG = 17096; // 12 +const static uint64_t SH_FLD_WI_UNSOLICITED_DATA = 17097; // 12 +const static uint64_t SH_FLD_WKUP_NOTIFY_SELECT = 17098; // 24 +const static uint64_t SH_FLD_WL_ONE_DQS_PULSE = 17099; // 8 +const static uint64_t SH_FLD_WM_MULTIHIT_ERR = 17100; // 2 +const static uint64_t SH_FLD_WM_WIN_NOT_OPEN_ERR = 17101; // 2 +const static uint64_t SH_FLD_WOF = 17102; // 5 +const static uint64_t SH_FLD_WOF_COUNTER = 17103; // 1 +const static uint64_t SH_FLD_WOF_COUNTER_LEN = 17104; // 1 +const static uint64_t SH_FLD_WOF_LEN = 17105; // 5 +const static uint64_t SH_FLD_WOF_LOW_ORDER_STEP_COUNTER_PARITY = 17106; // 4 +const static uint64_t SH_FLD_WORD = 17107; // 8 +const static uint64_t SH_FLD_WORD_LEN = 17108; // 8 +const static uint64_t SH_FLD_WORK1 = 17109; // 3 +const static uint64_t SH_FLD_WORK1_LEN = 17110; // 3 +const static uint64_t SH_FLD_WORK2 = 17111; // 3 +const static uint64_t SH_FLD_WORK2_LEN = 17112; // 3 +const static uint64_t SH_FLD_WRAP_0 = 17113; // 2 +const static uint64_t SH_FLD_WRAP_1 = 17114; // 1 +const static uint64_t SH_FLD_WRAP_2 = 17115; // 1 +const static uint64_t SH_FLD_WRAP_3 = 17116; // 1 +const static uint64_t SH_FLD_WRCMP = 17117; // 2 +const static uint64_t SH_FLD_WRCMP_LEN = 17118; // 2 +const static uint64_t SH_FLD_WRCNTL_DBG_SELECT = 17119; // 8 +const static uint64_t SH_FLD_WRDM_DLY = 17120; // 8 +const static uint64_t SH_FLD_WRDM_DLY_LEN = 17121; // 8 +const static uint64_t SH_FLD_WRD_MCBIST_OUT_OF_SYNC_HOLD_OUT = 17122; // 2 +const static uint64_t SH_FLD_WRITE = 17123; // 9 +const static uint64_t SH_FLD_WRITE_CMD = 17124; // 1 +const static uint64_t SH_FLD_WRITE_COMPLETE = 17125; // 1 +const static uint64_t SH_FLD_WRITE_COUNT = 17126; // 8 +const static uint64_t SH_FLD_WRITE_COUNTER = 17127; // 1 +const static uint64_t SH_FLD_WRITE_COUNTER_LEN = 17128; // 1 +const static uint64_t SH_FLD_WRITE_COUNT_LEN = 17129; // 8 +const static uint64_t SH_FLD_WRITE_CRD_POOL = 17130; // 1 +const static uint64_t SH_FLD_WRITE_CRD_POOL_LEN = 17131; // 1 +const static uint64_t SH_FLD_WRITE_CTR = 17132; // 8 +const static uint64_t SH_FLD_WRITE_ECC_DATAPATH_ERROR = 17133; // 8 +const static uint64_t SH_FLD_WRITE_ENABLE = 17134; // 129 +const static uint64_t SH_FLD_WRITE_ERR_INJECT0 = 17135; // 8 +const static uint64_t SH_FLD_WRITE_ERR_INJECT0_LEN = 17136; // 8 +const static uint64_t SH_FLD_WRITE_INVALID_FACES = 17137; // 1 +const static uint64_t SH_FLD_WRITE_INVALID_PIB = 17138; // 1 +const static uint64_t SH_FLD_WRITE_LATENCY_OFFSET = 17139; // 8 +const static uint64_t SH_FLD_WRITE_LATENCY_OFFSET_LEN = 17140; // 8 +const static uint64_t SH_FLD_WRITE_NOT_READ = 17141; // 3 +const static uint64_t SH_FLD_WRITE_NVLD = 17142; // 1 +const static uint64_t SH_FLD_WRITE_ON_RUN = 17143; // 90 +const static uint64_t SH_FLD_WRITE_POOL = 17144; // 1 +const static uint64_t SH_FLD_WRITE_POOL_LEN = 17145; // 1 +const static uint64_t SH_FLD_WRITE_RMW_CE = 17146; // 8 +const static uint64_t SH_FLD_WRITE_RMW_SUE = 17147; // 8 +const static uint64_t SH_FLD_WRITE_RMW_UE = 17148; // 8 +const static uint64_t SH_FLD_WRITE_RST_INTERRUPT_FACES = 17149; // 1 +const static uint64_t SH_FLD_WRITE_RST_INTERRUPT_PIB = 17150; // 1 +const static uint64_t SH_FLD_WRITE_TSIZE = 17151; // 4 +const static uint64_t SH_FLD_WRITE_TSIZE_LEN = 17152; // 4 +const static uint64_t SH_FLD_WRITE_TTYPE = 17153; // 4 +const static uint64_t SH_FLD_WRITE_TTYPE_LEN = 17154; // 4 +const static uint64_t SH_FLD_WRITE_WHILE_BRIDGE_BUSY_ERR = 17155; // 1 +const static uint64_t SH_FLD_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN = 17156; // 1 +const static uint64_t SH_FLD_WRMON_BAR0_BA = 17157; // 1 +const static uint64_t SH_FLD_WRMON_BAR0_BA_LEN = 17158; // 1 +const static uint64_t SH_FLD_WRMON_BAR0_SIZE = 17159; // 1 +const static uint64_t SH_FLD_WRMON_BAR0_SIZE_LEN = 17160; // 1 +const static uint64_t SH_FLD_WRMON_BAR1_BA = 17161; // 1 +const static uint64_t SH_FLD_WRMON_BAR1_BA_LEN = 17162; // 1 +const static uint64_t SH_FLD_WRMON_BAR1_SIZE = 17163; // 1 +const static uint64_t SH_FLD_WRMON_BAR1_SIZE_LEN = 17164; // 1 +const static uint64_t SH_FLD_WRMON_BAR2_BA = 17165; // 1 +const static uint64_t SH_FLD_WRMON_BAR2_BA_LEN = 17166; // 1 +const static uint64_t SH_FLD_WRMON_BAR2_SIZE = 17167; // 1 +const static uint64_t SH_FLD_WRMON_BAR2_SIZE_LEN = 17168; // 1 +const static uint64_t SH_FLD_WRMON_BAR3_BA = 17169; // 1 +const static uint64_t SH_FLD_WRMON_BAR3_BA_LEN = 17170; // 1 +const static uint64_t SH_FLD_WRMON_BAR3_SIZE = 17171; // 1 +const static uint64_t SH_FLD_WRMON_BAR3_SIZE_LEN = 17172; // 1 +const static uint64_t SH_FLD_WRMON_BAR4_BA = 17173; // 1 +const static uint64_t SH_FLD_WRMON_BAR4_BA_LEN = 17174; // 1 +const static uint64_t SH_FLD_WRMON_BAR4_SIZE = 17175; // 1 +const static uint64_t SH_FLD_WRMON_BAR4_SIZE_LEN = 17176; // 1 +const static uint64_t SH_FLD_WRMON_BAR5_BA = 17177; // 1 +const static uint64_t SH_FLD_WRMON_BAR5_BA_LEN = 17178; // 1 +const static uint64_t SH_FLD_WRMON_BAR5_SIZE = 17179; // 1 +const static uint64_t SH_FLD_WRMON_BAR5_SIZE_LEN = 17180; // 1 +const static uint64_t SH_FLD_WRMON_BAR6_BA = 17181; // 1 +const static uint64_t SH_FLD_WRMON_BAR6_BA_LEN = 17182; // 1 +const static uint64_t SH_FLD_WRMON_BAR6_SIZE = 17183; // 1 +const static uint64_t SH_FLD_WRMON_BAR6_SIZE_LEN = 17184; // 1 +const static uint64_t SH_FLD_WRMON_BAR7_BA = 17185; // 1 +const static uint64_t SH_FLD_WRMON_BAR7_BA_LEN = 17186; // 1 +const static uint64_t SH_FLD_WRMON_BAR7_SIZE = 17187; // 1 +const static uint64_t SH_FLD_WRMON_BAR7_SIZE_LEN = 17188; // 1 +const static uint64_t SH_FLD_WRMON_CMP0_ENADTTYPE = 17189; // 1 +const static uint64_t SH_FLD_WRMON_CMP0_TSIZE = 17190; // 1 +const static uint64_t SH_FLD_WRMON_CMP0_TSIZEMSK = 17191; // 1 +const static uint64_t SH_FLD_WRMON_CMP0_TSIZEMSK_LEN = 17192; // 1 +const static uint64_t SH_FLD_WRMON_CMP0_TSIZE_LEN = 17193; // 1 +const static uint64_t SH_FLD_WRMON_CMP0_TTYPE = 17194; // 1 +const static uint64_t SH_FLD_WRMON_CMP0_TTYPEDIS = 17195; // 1 +const static uint64_t SH_FLD_WRMON_CMP0_TTYPEDIS_LEN = 17196; // 1 +const static uint64_t SH_FLD_WRMON_CMP0_TTYPEMSK = 17197; // 1 +const static uint64_t SH_FLD_WRMON_CMP0_TTYPEMSK_LEN = 17198; // 1 +const static uint64_t SH_FLD_WRMON_CMP0_TTYPE_LEN = 17199; // 1 +const static uint64_t SH_FLD_WRMON_CMP0_UNUSED = 17200; // 1 +const static uint64_t SH_FLD_WRMON_CMP0_VAL = 17201; // 1 +const static uint64_t SH_FLD_WRMON_CMP1_ENADTTYPE = 17202; // 1 +const static uint64_t SH_FLD_WRMON_CMP1_TSIZE = 17203; // 1 +const static uint64_t SH_FLD_WRMON_CMP1_TSIZEMSK = 17204; // 1 +const static uint64_t SH_FLD_WRMON_CMP1_TSIZEMSK_LEN = 17205; // 1 +const static uint64_t SH_FLD_WRMON_CMP1_TSIZE_LEN = 17206; // 1 +const static uint64_t SH_FLD_WRMON_CMP1_TTYPE = 17207; // 1 +const static uint64_t SH_FLD_WRMON_CMP1_TTYPEDIS = 17208; // 1 +const static uint64_t SH_FLD_WRMON_CMP1_TTYPEDIS_LEN = 17209; // 1 +const static uint64_t SH_FLD_WRMON_CMP1_TTYPEMSK = 17210; // 1 +const static uint64_t SH_FLD_WRMON_CMP1_TTYPEMSK_LEN = 17211; // 1 +const static uint64_t SH_FLD_WRMON_CMP1_TTYPE_LEN = 17212; // 1 +const static uint64_t SH_FLD_WRMON_CMP1_UNUSED = 17213; // 1 +const static uint64_t SH_FLD_WRMON_CMP1_VAL = 17214; // 1 +const static uint64_t SH_FLD_WRMON_CMP2_ENADTTYPE = 17215; // 1 +const static uint64_t SH_FLD_WRMON_CMP2_TSIZE = 17216; // 1 +const static uint64_t SH_FLD_WRMON_CMP2_TSIZEMSK = 17217; // 1 +const static uint64_t SH_FLD_WRMON_CMP2_TSIZEMSK_LEN = 17218; // 1 +const static uint64_t SH_FLD_WRMON_CMP2_TSIZE_LEN = 17219; // 1 +const static uint64_t SH_FLD_WRMON_CMP2_TTYPE = 17220; // 1 +const static uint64_t SH_FLD_WRMON_CMP2_TTYPEDIS = 17221; // 1 +const static uint64_t SH_FLD_WRMON_CMP2_TTYPEDIS_LEN = 17222; // 1 +const static uint64_t SH_FLD_WRMON_CMP2_TTYPEMSK = 17223; // 1 +const static uint64_t SH_FLD_WRMON_CMP2_TTYPEMSK_LEN = 17224; // 1 +const static uint64_t SH_FLD_WRMON_CMP2_TTYPE_LEN = 17225; // 1 +const static uint64_t SH_FLD_WRMON_CMP2_UNUSED = 17226; // 1 +const static uint64_t SH_FLD_WRMON_CMP2_VAL = 17227; // 1 +const static uint64_t SH_FLD_WRMON_CMP3_ENADTTYPE = 17228; // 1 +const static uint64_t SH_FLD_WRMON_CMP3_TSIZE = 17229; // 1 +const static uint64_t SH_FLD_WRMON_CMP3_TSIZEMSK = 17230; // 1 +const static uint64_t SH_FLD_WRMON_CMP3_TSIZEMSK_LEN = 17231; // 1 +const static uint64_t SH_FLD_WRMON_CMP3_TSIZE_LEN = 17232; // 1 +const static uint64_t SH_FLD_WRMON_CMP3_TTYPE = 17233; // 1 +const static uint64_t SH_FLD_WRMON_CMP3_TTYPEDIS = 17234; // 1 +const static uint64_t SH_FLD_WRMON_CMP3_TTYPEDIS_LEN = 17235; // 1 +const static uint64_t SH_FLD_WRMON_CMP3_TTYPEMSK = 17236; // 1 +const static uint64_t SH_FLD_WRMON_CMP3_TTYPEMSK_LEN = 17237; // 1 +const static uint64_t SH_FLD_WRMON_CMP3_TTYPE_LEN = 17238; // 1 +const static uint64_t SH_FLD_WRMON_CMP3_UNUSED = 17239; // 1 +const static uint64_t SH_FLD_WRMON_CMP3_VAL = 17240; // 1 +const static uint64_t SH_FLD_WRMON_CMP4_ENADTTYPE = 17241; // 1 +const static uint64_t SH_FLD_WRMON_CMP4_TSIZE = 17242; // 1 +const static uint64_t SH_FLD_WRMON_CMP4_TSIZEMSK = 17243; // 1 +const static uint64_t SH_FLD_WRMON_CMP4_TSIZEMSK_LEN = 17244; // 1 +const static uint64_t SH_FLD_WRMON_CMP4_TSIZE_LEN = 17245; // 1 +const static uint64_t SH_FLD_WRMON_CMP4_TTYPE = 17246; // 1 +const static uint64_t SH_FLD_WRMON_CMP4_TTYPEDIS = 17247; // 1 +const static uint64_t SH_FLD_WRMON_CMP4_TTYPEDIS_LEN = 17248; // 1 +const static uint64_t SH_FLD_WRMON_CMP4_TTYPEMSK = 17249; // 1 +const static uint64_t SH_FLD_WRMON_CMP4_TTYPEMSK_LEN = 17250; // 1 +const static uint64_t SH_FLD_WRMON_CMP4_TTYPE_LEN = 17251; // 1 +const static uint64_t SH_FLD_WRMON_CMP4_UNUSED = 17252; // 1 +const static uint64_t SH_FLD_WRMON_CMP4_VAL = 17253; // 1 +const static uint64_t SH_FLD_WRMON_CMP5_ENADTTYPE = 17254; // 1 +const static uint64_t SH_FLD_WRMON_CMP5_TSIZE = 17255; // 1 +const static uint64_t SH_FLD_WRMON_CMP5_TSIZEMSK = 17256; // 1 +const static uint64_t SH_FLD_WRMON_CMP5_TSIZEMSK_LEN = 17257; // 1 +const static uint64_t SH_FLD_WRMON_CMP5_TSIZE_LEN = 17258; // 1 +const static uint64_t SH_FLD_WRMON_CMP5_TTYPE = 17259; // 1 +const static uint64_t SH_FLD_WRMON_CMP5_TTYPEDIS = 17260; // 1 +const static uint64_t SH_FLD_WRMON_CMP5_TTYPEDIS_LEN = 17261; // 1 +const static uint64_t SH_FLD_WRMON_CMP5_TTYPEMSK = 17262; // 1 +const static uint64_t SH_FLD_WRMON_CMP5_TTYPEMSK_LEN = 17263; // 1 +const static uint64_t SH_FLD_WRMON_CMP5_TTYPE_LEN = 17264; // 1 +const static uint64_t SH_FLD_WRMON_CMP5_UNUSED = 17265; // 1 +const static uint64_t SH_FLD_WRMON_CMP5_VAL = 17266; // 1 +const static uint64_t SH_FLD_WRMON_CMP6_ENADTTYPE = 17267; // 1 +const static uint64_t SH_FLD_WRMON_CMP6_TSIZE = 17268; // 1 +const static uint64_t SH_FLD_WRMON_CMP6_TSIZEMSK = 17269; // 1 +const static uint64_t SH_FLD_WRMON_CMP6_TSIZEMSK_LEN = 17270; // 1 +const static uint64_t SH_FLD_WRMON_CMP6_TSIZE_LEN = 17271; // 1 +const static uint64_t SH_FLD_WRMON_CMP6_TTYPE = 17272; // 1 +const static uint64_t SH_FLD_WRMON_CMP6_TTYPEDIS = 17273; // 1 +const static uint64_t SH_FLD_WRMON_CMP6_TTYPEDIS_LEN = 17274; // 1 +const static uint64_t SH_FLD_WRMON_CMP6_TTYPEMSK = 17275; // 1 +const static uint64_t SH_FLD_WRMON_CMP6_TTYPEMSK_LEN = 17276; // 1 +const static uint64_t SH_FLD_WRMON_CMP6_TTYPE_LEN = 17277; // 1 +const static uint64_t SH_FLD_WRMON_CMP6_UNUSED = 17278; // 1 +const static uint64_t SH_FLD_WRMON_CMP6_VAL = 17279; // 1 +const static uint64_t SH_FLD_WRMON_CMP7_ENADTTYPE = 17280; // 1 +const static uint64_t SH_FLD_WRMON_CMP7_TSIZE = 17281; // 1 +const static uint64_t SH_FLD_WRMON_CMP7_TSIZEMSK = 17282; // 1 +const static uint64_t SH_FLD_WRMON_CMP7_TSIZEMSK_LEN = 17283; // 1 +const static uint64_t SH_FLD_WRMON_CMP7_TSIZE_LEN = 17284; // 1 +const static uint64_t SH_FLD_WRMON_CMP7_TTYPE = 17285; // 1 +const static uint64_t SH_FLD_WRMON_CMP7_TTYPEDIS = 17286; // 1 +const static uint64_t SH_FLD_WRMON_CMP7_TTYPEDIS_LEN = 17287; // 1 +const static uint64_t SH_FLD_WRMON_CMP7_TTYPEMSK = 17288; // 1 +const static uint64_t SH_FLD_WRMON_CMP7_TTYPEMSK_LEN = 17289; // 1 +const static uint64_t SH_FLD_WRMON_CMP7_TTYPE_LEN = 17290; // 1 +const static uint64_t SH_FLD_WRMON_CMP7_UNUSED = 17291; // 1 +const static uint64_t SH_FLD_WRMON_CMP7_VAL = 17292; // 1 +const static uint64_t SH_FLD_WRMON_WID0 = 17293; // 1 +const static uint64_t SH_FLD_WRMON_WID0_LEN = 17294; // 1 +const static uint64_t SH_FLD_WRMON_WID1 = 17295; // 1 +const static uint64_t SH_FLD_WRMON_WID1_LEN = 17296; // 1 +const static uint64_t SH_FLD_WRMON_WID2 = 17297; // 1 +const static uint64_t SH_FLD_WRMON_WID2_LEN = 17298; // 1 +const static uint64_t SH_FLD_WRMON_WID3 = 17299; // 1 +const static uint64_t SH_FLD_WRMON_WID3_LEN = 17300; // 1 +const static uint64_t SH_FLD_WRMON_WID4 = 17301; // 1 +const static uint64_t SH_FLD_WRMON_WID4_LEN = 17302; // 1 +const static uint64_t SH_FLD_WRMON_WID5 = 17303; // 1 +const static uint64_t SH_FLD_WRMON_WID5_LEN = 17304; // 1 +const static uint64_t SH_FLD_WRMON_WID6 = 17305; // 1 +const static uint64_t SH_FLD_WRMON_WID6_LEN = 17306; // 1 +const static uint64_t SH_FLD_WRMON_WID7 = 17307; // 1 +const static uint64_t SH_FLD_WRMON_WID7_LEN = 17308; // 1 +const static uint64_t SH_FLD_WRQ_BAD_CRESP = 17309; // 1 +const static uint64_t SH_FLD_WRQ_CAPACITY_LIMIT = 17310; // 4 +const static uint64_t SH_FLD_WRQ_CAPACITY_LIMIT_LEN = 17311; // 4 +const static uint64_t SH_FLD_WRQ_FSM_PERR = 17312; // 1 +const static uint64_t SH_FLD_WRQ_HANG = 17313; // 8 +const static uint64_t SH_FLD_WRQ_OP_HANG = 17314; // 1 +const static uint64_t SH_FLD_WRQ_OVERFLOW = 17315; // 1 +const static uint64_t SH_FLD_WRQ_PE = 17316; // 8 +const static uint64_t SH_FLD_WRQ_RRQ_HANG_ERR = 17317; // 16 +const static uint64_t SH_FLD_WRSBG_DLY = 17318; // 8 +const static uint64_t SH_FLD_WRSBG_DLY_LEN = 17319; // 8 +const static uint64_t SH_FLD_WRSMDR_DLY = 17320; // 8 +const static uint64_t SH_FLD_WRSMDR_DLY_LEN = 17321; // 8 +const static uint64_t SH_FLD_WRSMSR_DLY = 17322; // 8 +const static uint64_t SH_FLD_WRSMSR_DLY_LEN = 17323; // 8 +const static uint64_t SH_FLD_WRTCFG_PE = 17324; // 8 +const static uint64_t SH_FLD_WRTO_AMO_COLLISION_RULES = 17325; // 8 +const static uint64_t SH_FLD_WRTO_AMO_COLLISION_RULES_LEN = 17326; // 8 +const static uint64_t SH_FLD_WRT_BUFFER_CE = 17327; // 8 +const static uint64_t SH_FLD_WRT_BUFFER_SUE = 17328; // 8 +const static uint64_t SH_FLD_WRT_BUFFER_UE = 17329; // 8 +const static uint64_t SH_FLD_WRT_MISC_REGISTER_PARITY_ERROR = 17330; // 8 +const static uint64_t SH_FLD_WRT_RST_INTRPT_FACES = 17331; // 1 +const static uint64_t SH_FLD_WRT_RST_INTRPT_PIB = 17332; // 1 +const static uint64_t SH_FLD_WRT_SCOM_SEQUENCE_ERROR = 17333; // 8 +const static uint64_t SH_FLD_WR_BUFFER_STATUS = 17334; // 2 +const static uint64_t SH_FLD_WR_BUFFER_STATUS_LEN = 17335; // 2 +const static uint64_t SH_FLD_WR_BYTE_COUNT = 17336; // 2 +const static uint64_t SH_FLD_WR_BYTE_COUNT_LEN = 17337; // 2 +const static uint64_t SH_FLD_WR_CNTL = 17338; // 8 +const static uint64_t SH_FLD_WR_CNTL_MASK = 17339; // 8 +const static uint64_t SH_FLD_WR_DATA_PARITY_ERROR = 17340; // 3 +const static uint64_t SH_FLD_WR_ECC_CE = 17341; // 1 +const static uint64_t SH_FLD_WR_ECC_UE = 17342; // 1 +const static uint64_t SH_FLD_WR_EPSILON_VALUE = 17343; // 2 +const static uint64_t SH_FLD_WR_EPSILON_VALUE_LEN = 17344; // 2 +const static uint64_t SH_FLD_WR_FIFO_STAB = 17345; // 8 +const static uint64_t SH_FLD_WR_GATHER_TIMEOUT = 17346; // 4 +const static uint64_t SH_FLD_WR_GATHER_TIMEOUT_LEN = 17347; // 4 +const static uint64_t SH_FLD_WR_LEVEL = 17348; // 8 +const static uint64_t SH_FLD_WR_MON_NOT_DISABLED_ERR = 17349; // 2 +const static uint64_t SH_FLD_WR_PAR_ERR = 17350; // 8 +const static uint64_t SH_FLD_WR_PAR_ERR_MASK = 17351; // 8 +const static uint64_t SH_FLD_WR_PRE_DLY = 17352; // 8 +const static uint64_t SH_FLD_WR_PRE_DLY_LEN = 17353; // 8 +const static uint64_t SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT = 17354; // 8 +const static uint64_t SH_FLD_WR_RSVD_LOWER_OR_STATIC_LIMIT_LEN = 17355; // 8 +const static uint64_t SH_FLD_WR_RSVD_UPPER_LIMIT = 17356; // 8 +const static uint64_t SH_FLD_WR_RSVD_UPPER_LIMIT_LEN = 17357; // 8 +const static uint64_t SH_FLD_WR_SCOPE = 17358; // 24 +const static uint64_t SH_FLD_WR_SLVNUM = 17359; // 2 +const static uint64_t SH_FLD_WR_SLVNUM_LEN = 17360; // 2 +const static uint64_t SH_FLD_WR_SPLIT_UT0_ENA = 17361; // 6 +const static uint64_t SH_FLD_WR_SPLIT_UT1_ENA = 17362; // 6 +const static uint64_t SH_FLD_WR_TIER_1_CNT_VAL = 17363; // 1 +const static uint64_t SH_FLD_WR_TIER_1_CNT_VAL_LEN = 17364; // 1 +const static uint64_t SH_FLD_WR_TIER_1_DIV_VAL = 17365; // 1 +const static uint64_t SH_FLD_WR_TIER_1_DIV_VAL_LEN = 17366; // 1 +const static uint64_t SH_FLD_WR_TIER_2_CNT_VAL = 17367; // 1 +const static uint64_t SH_FLD_WR_TIER_2_CNT_VAL_LEN = 17368; // 1 +const static uint64_t SH_FLD_WR_TIER_2_DIV_VAL = 17369; // 1 +const static uint64_t SH_FLD_WR_TIER_2_DIV_VAL_LEN = 17370; // 1 +const static uint64_t SH_FLD_WR_VALID = 17371; // 1 +const static uint64_t SH_FLD_WSIZE = 17372; // 1 +const static uint64_t SH_FLD_WSIZE_LEN = 17373; // 1 +const static uint64_t SH_FLD_WT4CR_TIER0_EPS_VAL = 17374; // 12 +const static uint64_t SH_FLD_WT4CR_TIER0_EPS_VAL_LEN = 17375; // 12 +const static uint64_t SH_FLD_WT4CR_TIER1_EPS_VAL = 17376; // 24 +const static uint64_t SH_FLD_WT4CR_TIER1_EPS_VAL_LEN = 17377; // 24 +const static uint64_t SH_FLD_WT4CR_TIER2_EPS_VAL = 17378; // 24 +const static uint64_t SH_FLD_WT4CR_TIER2_EPS_VAL_LEN = 17379; // 24 +const static uint64_t SH_FLD_WTL_SM_STATUS = 17380; // 4 +const static uint64_t SH_FLD_WTL_SM_STATUS_LEN = 17381; // 4 +const static uint64_t SH_FLD_WTL_TEST_CLOCK = 17382; // 4 +const static uint64_t SH_FLD_WTL_TEST_DATA = 17383; // 4 +const static uint64_t SH_FLD_WTR_MAX_BAD_LANES = 17384; // 4 +const static uint64_t SH_FLD_WTR_MAX_BAD_LANES_LEN = 17385; // 4 +const static uint64_t SH_FLD_WT_ALL_DONE_GCRMSG = 17386; // 4 +const static uint64_t SH_FLD_WT_BS_CLOCK_EN_BYP = 17387; // 4 +const static uint64_t SH_FLD_WT_BS_DATA_EN_BYP = 17388; // 4 +const static uint64_t SH_FLD_WT_CHECK_COUNT = 17389; // 4 +const static uint64_t SH_FLD_WT_CHECK_COUNT_LEN = 17390; // 4 +const static uint64_t SH_FLD_WT_CLK_LANE_BAD_CODE = 17391; // 4 +const static uint64_t SH_FLD_WT_CLK_LANE_BAD_CODE_LEN = 17392; // 4 +const static uint64_t SH_FLD_WT_CLK_LANE_INVERTED = 17393; // 4 +const static uint64_t SH_FLD_WT_CU_BYP_PLL_LOCK = 17394; // 4 +const static uint64_t SH_FLD_WT_CU_PLL_PGOOD = 17395; // 4 +const static uint64_t SH_FLD_WT_EN_ALL_CLK_SEGS_GCRMSG = 17396; // 4 +const static uint64_t SH_FLD_WT_EN_ALL_DATA_SEGS_GCRMSG = 17397; // 4 +const static uint64_t SH_FLD_WT_LANE_BAD_CODE = 17398; // 96 +const static uint64_t SH_FLD_WT_LANE_BAD_CODE_LEN = 17399; // 96 +const static uint64_t SH_FLD_WT_LANE_DISABLED = 17400; // 96 +const static uint64_t SH_FLD_WT_PATTERN_LENGTH = 17401; // 8 +const static uint64_t SH_FLD_WT_PATTERN_LENGTH_LEN = 17402; // 8 +const static uint64_t SH_FLD_WT_PLL_REFCLKSEL = 17403; // 4 +const static uint64_t SH_FLD_WT_PREV_DONE_GCRMSG = 17404; // 4 +const static uint64_t SH_FLD_WT_TIMEOUT_SEL = 17405; // 4 +const static uint64_t SH_FLD_WT_TIMEOUT_SEL_LEN = 17406; // 4 +const static uint64_t SH_FLD_WWDM_DLY = 17407; // 8 +const static uint64_t SH_FLD_WWDM_DLY_LEN = 17408; // 8 +const static uint64_t SH_FLD_WWOP_DLY = 17409; // 8 +const static uint64_t SH_FLD_WWOP_DLY_LEN = 17410; // 8 +const static uint64_t SH_FLD_WWSMDR_DLY = 17411; // 8 +const static uint64_t SH_FLD_WWSMDR_DLY_LEN = 17412; // 8 +const static uint64_t SH_FLD_WWSMSR_DLY = 17413; // 8 +const static uint64_t SH_FLD_WWSMSR_DLY_LEN = 17414; // 8 +const static uint64_t SH_FLD_X0_ACT = 17415; // 1 +const static uint64_t SH_FLD_X0_HI = 17416; // 1 +const static uint64_t SH_FLD_X0_HISTORY = 17417; // 1 +const static uint64_t SH_FLD_X0_HISTORY_LEN = 17418; // 1 +const static uint64_t SH_FLD_X0_HI_LEN = 17419; // 1 +const static uint64_t SH_FLD_X0_LO = 17420; // 1 +const static uint64_t SH_FLD_X0_LO_LEN = 17421; // 1 +const static uint64_t SH_FLD_X0_TX_ENABLE = 17422; // 4 +const static uint64_t SH_FLD_X0_TX_SELECT = 17423; // 4 +const static uint64_t SH_FLD_X0_TX_SELECT_LEN = 17424; // 4 +const static uint64_t SH_FLD_X1_ACT = 17425; // 1 +const static uint64_t SH_FLD_X1_HI = 17426; // 1 +const static uint64_t SH_FLD_X1_HISTORY = 17427; // 1 +const static uint64_t SH_FLD_X1_HISTORY_LEN = 17428; // 1 +const static uint64_t SH_FLD_X1_HI_LEN = 17429; // 1 +const static uint64_t SH_FLD_X1_LO = 17430; // 1 +const static uint64_t SH_FLD_X1_LO_LEN = 17431; // 1 +const static uint64_t SH_FLD_X1_TX_ENABLE = 17432; // 4 +const static uint64_t SH_FLD_X1_TX_SELECT = 17433; // 4 +const static uint64_t SH_FLD_X1_TX_SELECT_LEN = 17434; // 4 +const static uint64_t SH_FLD_X2_ACT = 17435; // 1 +const static uint64_t SH_FLD_X2_HI = 17436; // 1 +const static uint64_t SH_FLD_X2_HISTORY = 17437; // 1 +const static uint64_t SH_FLD_X2_HISTORY_LEN = 17438; // 1 +const static uint64_t SH_FLD_X2_HI_LEN = 17439; // 1 +const static uint64_t SH_FLD_X2_LO = 17440; // 1 +const static uint64_t SH_FLD_X2_LO_LEN = 17441; // 1 +const static uint64_t SH_FLD_X2_TX_ENABLE = 17442; // 4 +const static uint64_t SH_FLD_X2_TX_SELECT = 17443; // 4 +const static uint64_t SH_FLD_X2_TX_SELECT_LEN = 17444; // 4 +const static uint64_t SH_FLD_X3_TX_ENABLE = 17445; // 4 +const static uint64_t SH_FLD_X3_TX_SELECT = 17446; // 4 +const static uint64_t SH_FLD_X3_TX_SELECT_LEN = 17447; // 4 +const static uint64_t SH_FLD_X4_TX_ENABLE = 17448; // 4 +const static uint64_t SH_FLD_X4_TX_SELECT = 17449; // 4 +const static uint64_t SH_FLD_X4_TX_SELECT_LEN = 17450; // 4 +const static uint64_t SH_FLD_X5_TX_ENABLE = 17451; // 4 +const static uint64_t SH_FLD_X5_TX_SELECT = 17452; // 4 +const static uint64_t SH_FLD_X5_TX_SELECT_LEN = 17453; // 4 +const static uint64_t SH_FLD_X6_TX_ENABLE = 17454; // 4 +const static uint64_t SH_FLD_X6_TX_SELECT = 17455; // 4 +const static uint64_t SH_FLD_X6_TX_SELECT_LEN = 17456; // 4 +const static uint64_t SH_FLD_X7_TX_ENABLE = 17457; // 4 +const static uint64_t SH_FLD_X7_TX_SELECT = 17458; // 4 +const static uint64_t SH_FLD_X7_TX_SELECT_LEN = 17459; // 4 +const static uint64_t SH_FLD_XARS = 17460; // 3 +const static uint64_t SH_FLD_XARSP = 17461; // 12 +const static uint64_t SH_FLD_XATS = 17462; // 12 +const static uint64_t SH_FLD_XCR = 17463; // 21 +const static uint64_t SH_FLD_XCR_LEN = 17464; // 21 +const static uint64_t SH_FLD_XIMEM_MEM_IFETCH_PENDING = 17465; // 21 +const static uint64_t SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING = 17466; // 21 +const static uint64_t SH_FLD_XIRAMGA_IR = 17467; // 21 +const static uint64_t SH_FLD_XIRAMGA_IR_LEN = 17468; // 21 +const static uint64_t SH_FLD_XIRAMRA_SPRG0 = 17469; // 42 +const static uint64_t SH_FLD_XIRAMRA_SPRG0_LEN = 17470; // 42 +const static uint64_t SH_FLD_XIXCR_XCR = 17471; // 21 +const static uint64_t SH_FLD_XIXCR_XCR_LEN = 17472; // 21 +const static uint64_t SH_FLD_XLAT = 17473; // 16 +const static uint64_t SH_FLD_XLATE_TO_ADDR_ID_ENABLE = 17474; // 2 +const static uint64_t SH_FLD_XLAT_LEN = 17475; // 16 +const static uint64_t SH_FLD_XPT_POWERBUS_CE = 17476; // 4 +const static uint64_t SH_FLD_XPT_POWERBUS_SUE = 17477; // 4 +const static uint64_t SH_FLD_XPT_POWERBUS_UE = 17478; // 4 +const static uint64_t SH_FLD_XPT_RECOVERABLE_ERROR = 17479; // 4 +const static uint64_t SH_FLD_XPT_SYS_XSTOP_ERROR = 17480; // 4 +const static uint64_t SH_FLD_XSCOM_DONE = 17481; // 96 +const static uint64_t SH_FLD_XSCOM_FAIL = 17482; // 96 +const static uint64_t SH_FLD_XSCOM_STATUS = 17483; // 96 +const static uint64_t SH_FLD_XSCOM_STATUS_LEN = 17484; // 96 +const static uint64_t SH_FLD_XSC_CMD_OVERRUN = 17485; // 1 +const static uint64_t SH_FLD_XSTOP = 17486; // 5 +const static uint64_t SH_FLD_XSTOP_GATE = 17487; // 1 +const static uint64_t SH_FLD_XTS_CONFIG_P = 17488; // 1 +const static uint64_t SH_FLD_XTS_INT = 17489; // 1 +const static uint64_t SH_FLD_XTS_PBUS_PROTOCOL = 17490; // 1 +const static uint64_t SH_FLD_XTS_PROTOCOL_CE = 17491; // 1 +const static uint64_t SH_FLD_XTS_PROTOCOL_UE = 17492; // 1 +const static uint64_t SH_FLD_XTS_RSVD_10 = 17493; // 1 +const static uint64_t SH_FLD_XTS_RSVD_11 = 17494; // 1 +const static uint64_t SH_FLD_XTS_RSVD_12 = 17495; // 1 +const static uint64_t SH_FLD_XTS_RSVD_13 = 17496; // 1 +const static uint64_t SH_FLD_XTS_RSVD_14 = 17497; // 1 +const static uint64_t SH_FLD_XTS_RSVD_15 = 17498; // 1 +const static uint64_t SH_FLD_XTS_RSVD_16 = 17499; // 1 +const static uint64_t SH_FLD_XTS_RSVD_17 = 17500; // 1 +const static uint64_t SH_FLD_XTS_RSVD_18 = 17501; // 1 +const static uint64_t SH_FLD_XTS_RSVD_19 = 17502; // 1 +const static uint64_t SH_FLD_XTS_RSVD_6 = 17503; // 1 +const static uint64_t SH_FLD_XTS_RSVD_7 = 17504; // 1 +const static uint64_t SH_FLD_XTS_RSVD_8 = 17505; // 1 +const static uint64_t SH_FLD_XTS_RSVD_9 = 17506; // 1 +const static uint64_t SH_FLD_XTS_SRAM_CE = 17507; // 1 +const static uint64_t SH_FLD_XTS_SRAM_UE = 17508; // 1 +const static uint64_t SH_FLD_X_COUPLE_SELECT1 = 17509; // 86 +const static uint64_t SH_FLD_X_COUPLE_SELECT1_LEN = 17510; // 86 +const static uint64_t SH_FLD_X_COUPLE_SELECT2 = 17511; // 86 +const static uint64_t SH_FLD_X_COUPLE_SELECT2_LEN = 17512; // 86 +const static uint64_t SH_FLD_Z = 17513; // 1 +const static uint64_t SH_FLD_ZCAL = 17514; // 12 +const static uint64_t SH_FLD_ZCAL_CYA_DATA_INV = 17515; // 4 +const static uint64_t SH_FLD_ZCAL_LEN = 17516; // 4 +const static uint64_t SH_FLD_ZCAL_N = 17517; // 4 +const static uint64_t SH_FLD_ZCAL_NOT_CONT = 17518; // 8 +const static uint64_t SH_FLD_ZCAL_N_LEN = 17519; // 4 +const static uint64_t SH_FLD_ZCAL_P = 17520; // 4 +const static uint64_t SH_FLD_ZCAL_P_LEN = 17521; // 4 +const static uint64_t SH_FLD_ZCAL_RANGE_CHECK = 17522; // 4 +const static uint64_t SH_FLD_ZCAL_SM_MAX_VAL = 17523; // 4 +const static uint64_t SH_FLD_ZCAL_SM_MAX_VAL_LEN = 17524; // 4 +const static uint64_t SH_FLD_ZCAL_SM_MIN_VAL = 17525; // 4 +const static uint64_t SH_FLD_ZCAL_SM_MIN_VAL_LEN = 17526; // 4 +const static uint64_t SH_FLD_ZCAL_SWO_CAL_SEGS = 17527; // 4 +const static uint64_t SH_FLD_ZCAL_SWO_CMP_INV = 17528; // 4 +const static uint64_t SH_FLD_ZCAL_SWO_CMP_OFFSET = 17529; // 4 +const static uint64_t SH_FLD_ZCAL_SWO_CMP_RESET = 17530; // 4 +const static uint64_t SH_FLD_ZCAL_SWO_EN = 17531; // 4 +const static uint64_t SH_FLD_ZCAL_SWO_POWERDOWN = 17532; // 4 +const static uint64_t SH_FLD_ZCAL_SWO_TCOIL = 17533; // 4 +const static uint64_t SH_FLD_ZCAL_TEST_CLK_DIV = 17534; // 4 +const static uint64_t SH_FLD_ZCAL_TEST_OVR_1R = 17535; // 4 +const static uint64_t SH_FLD_ZCAL_TEST_OVR_2R = 17536; // 4 +const static uint64_t SH_FLD_ZCAL_TEST_OVR_4X_SEG = 17537; // 4 #endif |
