diff options
-rw-r--r-- | src/test/testcases/testAduMem_ecc.py | 54 | ||||
-rw-r--r-- | src/test/testcases/testAduMem_itag.py | 39 | ||||
-rw-r--r-- | src/test/testcases/testAduMem_noEccNoItag.py | 78 | ||||
-rw-r--r-- | src/test/testcases/testAduMem_withEccItag.py | 51 | ||||
-rw-r--r-- | src/test/testcases/testMemPBA.py | 135 | ||||
-rw-r--r-- | src/test/testcases/testMemUtil.py | 114 | ||||
-rw-r--r-- | src/test/testcases/testPutGetMem.xml | 9 | ||||
-rw-r--r-- | src/test/testcases/testPutMem.py | 122 |
8 files changed, 375 insertions, 227 deletions
diff --git a/src/test/testcases/testAduMem_ecc.py b/src/test/testcases/testAduMem_ecc.py index d7b10dd0..bcd03645 100644 --- a/src/test/testcases/testAduMem_ecc.py +++ b/src/test/testcases/testAduMem_ecc.py @@ -5,7 +5,7 @@ # # OpenPOWER sbe Project # -# Contributors Listed Below - COPYRIGHT 2016 +# Contributors Listed Below - COPYRIGHT 2016,2017 # [+] International Business Machines Corp. # # @@ -25,35 +25,45 @@ import sys sys.path.append("targets/p9_nimbus/sbeTest" ) import testUtil +import testMemUtil as testMemProcUtil err = False -LOOP_COUNT = 1 - -GETMEMADU_TESTDATA_ECC = [0,0,0,0x6, - 0,0,0xA4,0x01, - 0,0,0x0,0xAD, #CoreChipletId/EccByte/Flags - CacheInhibit/FastMode/NoTag/Ecc/AutoIncr/Adu/Proc - 0,0,0,0, # Addr Upper 32 bit - 0x08,0x00,0x00,0x00, # Addr Lower 32 bit - 0x00,0x00,0x00,0x20] # length of data - -GETMEMADU_EXPDATA_ECC = [0x00,0x00,0x00,0x24, # length of data - 0xc0,0xde,0xa4,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - # MAIN Test Run Starts Here... #------------------------------------------------- def main( ): testUtil.runCycles( 10000000 ) - # GetMemAdu with Ecc - testUtil.writeUsFifo( GETMEMADU_TESTDATA_ECC) - testUtil.writeEot( ) + #PutMemAdu with ECC + data = os.urandom(80) + data = [ord(c) for c in data] + testMemProcUtil.putmem(0x08000000, data, 0xAD, 0xEF) + data = testMemProcUtil.addItagEcc(data,False, True, 0xEF) - testUtil.readDsEntry ( 9 ) - testUtil.readDsFifo( GETMEMADU_EXPDATA_ECC) - testUtil.runCycles( 10000000 ) - testUtil.readEot( ) + # GetMemAdu test with ECC + readData = testMemProcUtil.getmem(0x08000000, 80, 0xAD) + if(data == readData): + print ("Success - Write-Read ADU with ECC") + else: + print data + print readData + raise Exception('data mistmach') + + # Partial Write test + readData = testMemProcUtil.getmem(0x08000000, 40, 0xAD) + data = os.urandom(8) + data = [ord(c) for c in data] + testMemProcUtil.putmem(0x08000008, data, 0xAD, 0xEF) + data = testMemProcUtil.addItagEcc(data,False, True, 0xEF) + readBackData = testMemProcUtil.getmem(0x08000000, 40, 0xAD) + sandwichData = readData[:9]+data+readData[len(data)+9:] + if(sandwichData == readBackData): + print ("Success - Write_Part-Read ADU with ECC") + else: + print readData + print data + print readBackData + print sandwichData + raise Exception('data mistmach') #------------------------------------------------- # Calling all test code diff --git a/src/test/testcases/testAduMem_itag.py b/src/test/testcases/testAduMem_itag.py index 713f572d..1b5be988 100644 --- a/src/test/testcases/testAduMem_itag.py +++ b/src/test/testcases/testAduMem_itag.py @@ -5,7 +5,7 @@ # # OpenPOWER sbe Project # -# Contributors Listed Below - COPYRIGHT 2016 +# Contributors Listed Below - COPYRIGHT 2016,2017 # [+] International Business Machines Corp. # # @@ -25,6 +25,7 @@ import sys sys.path.append("targets/p9_nimbus/sbeTest" ) import testUtil +import testMemUtil as testMemProcUtil err = False GETMEMADU_TESTDATA_ITAG = [0,0,0,0x6, @@ -44,15 +45,37 @@ GETMEMADU_EXPDATA_ITAG = [0x00,0x00,0x00,0x48, # length of data def main( ): testUtil.runCycles( 10000000 ) - # GetMemAdu with Itag - testUtil.writeUsFifo( GETMEMADU_TESTDATA_ITAG ) - testUtil.writeEot( ) + #PutMemAdu with Itag + data = os.urandom(80) + data = [ord(c) for c in data] + testMemProcUtil.putmem(0x08000000, data, 0xB5) + data = testMemProcUtil.addItagEcc(data,True, False) - testUtil.readDsEntry ( 18 ) - testUtil.readDsFifo( GETMEMADU_EXPDATA_ITAG ) - testUtil.runCycles( 10000000 ) - testUtil.readEot( ) + # GetMemAdu test with ECC and Itag + readData = testMemProcUtil.getmem(0x08000000, 80, 0xB5) + if(data == readData): + print ("Success - Write-Read ADU with Itag") + else: + print data + print readData + raise Exception('data mistmach') + # Partial Write test + readData = testMemProcUtil.getmem(0x08000000, 40, 0xB5) + data = os.urandom(8) + data = [ord(c) for c in data] + testMemProcUtil.putmem(0x08000008, data, 0xB5, 0xEF) + data = testMemProcUtil.addItagEcc(data,True, False) + readBackData = testMemProcUtil.getmem(0x08000000, 40, 0xB5) + sandwichData = readData[:9]+data+readData[len(data)+9:] + if(sandwichData == readBackData): + print ("Success - Write_Part-Read ADU with Itag") + else: + print readData + print data + print readBackData + print sandwichData + raise Exception('data mistmach') #------------------------------------------------- # Calling all test code #------------------------------------------------- diff --git a/src/test/testcases/testAduMem_noEccNoItag.py b/src/test/testcases/testAduMem_noEccNoItag.py index bd0fc686..f23b4824 100644 --- a/src/test/testcases/testAduMem_noEccNoItag.py +++ b/src/test/testcases/testAduMem_noEccNoItag.py @@ -5,7 +5,7 @@ # # OpenPOWER sbe Project # -# Contributors Listed Below - COPYRIGHT 2016 +# Contributors Listed Below - COPYRIGHT 2016,2017 # [+] International Business Machines Corp. # # @@ -23,46 +23,13 @@ # # IBM_PROLOG_END_TAG import sys +import os +import struct sys.path.append("targets/p9_nimbus/sbeTest" ) import testUtil +import testMemUtil as testMemProcUtil err = False -LOOP_COUNT = 1 - -PUTMEMADU_CNTLDATA = [0,0,0,0, - 0,0,0xA4,0x02, - 0,0,0x0,0xA5, #CoreChipletId/EccByte/Flags -> NoEccOverride/CacheInhibit/FastMode/NoTag/NoEcc/AutoIncr/Adu/Proc - 0,0,0,0, # Addr Upper 32 bit - 0x08,0x00,0x00,0x00, # Addr Lower 32 bit - 0x00,0x00,0x00,0x10] # length of data - -PUTMEMADU_TESTDATA = [0xab,0xcd,0xef,0x12, - 0xba,0xdc,0xfe,0x21, - 0x34,0x56,0x78,0x9a, - 0x43,0x65,0x87,0xa9] - -PUTMEMADU_EXPDATA = [0x00,0x00,0x00,0x10, # length of data - 0xc0,0xde,0xa4,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - - - -GETMEMADU_TESTDATA = [0,0,0,0x6, - 0,0,0xA4,0x01, - 0,0,0x0,0xA5, #CoreChipletId/EccByte/Flags -> CacheInhibit/FastMode/NoTag/NoEcc/AutoIncr/Adu/Proc - 0,0,0,0, # Addr Upper 32 bit - 0x08,0x00,0x00,0x00, # Addr Lower 32 bit - 0x00,0x00,0x00,0x10] # length of data - -GETMEMADU_EXPDATA = [0xab,0xcd,0xef,0x12, #data - 0xba,0xdc,0xfe,0x21, - 0x34,0x56,0x78,0x9a, - 0x43,0x65,0x87,0xa9, - 0x00,0x00,0x00,0x10, # length of data - 0xc0,0xde,0xa4,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; # MAIN Test Run Starts Here... @@ -71,20 +38,35 @@ def main( ): testUtil.runCycles( 10000000 ) #PutMemAdu Test - testUtil.writeUsFifo( PUTMEMADU_CNTLDATA ) - testUtil.writeUsFifo( PUTMEMADU_TESTDATA ) - testUtil.writeEot( ) - - testUtil.readDsFifo( PUTMEMADU_EXPDATA ) - testUtil.readEot( ) + data = os.urandom(80) + data = [ord(c) for c in data] + testMemProcUtil.putmem(0x08000000, data, 0xA5) # GetMemAdu test - testUtil.writeUsFifo( GETMEMADU_TESTDATA ) - testUtil.writeEot( ) + readData = testMemProcUtil.getmem(0x08000000, 80, 0xA5) + if(data == readData): + print ("Success - Write-Read ADU") + else: + print data + print readData + raise Exception('data mistmach') + + # Partial Write test + readData = testMemProcUtil.getmem(0x08000000, 40, 0xA5) + data = os.urandom(8) + data = [ord(c) for c in data] + testMemProcUtil.putmem(0x08000008, data, 0xA5) + readBackData = testMemProcUtil.getmem(0x08000000, 40, 0xA5) + sandwichData = readData[:8]+data+readData[len(data)+8:] + if(sandwichData == readBackData): + print ("Success - Write_Part-Read ADU") + else: + print readData + print data + print readBackData + print sandwichData + raise Exception('data mistmach') - testUtil.readDsFifo( GETMEMADU_EXPDATA ) - testUtil.runCycles( 10000000 ) - testUtil.readEot( ) #------------------------------------------------- # Calling all test code diff --git a/src/test/testcases/testAduMem_withEccItag.py b/src/test/testcases/testAduMem_withEccItag.py index 453a82a4..5a04f484 100644 --- a/src/test/testcases/testAduMem_withEccItag.py +++ b/src/test/testcases/testAduMem_withEccItag.py @@ -5,7 +5,7 @@ # # OpenPOWER sbe Project # -# Contributors Listed Below - COPYRIGHT 2016 +# Contributors Listed Below - COPYRIGHT 2016,2017 # [+] International Business Machines Corp. # # @@ -25,34 +25,45 @@ import sys sys.path.append("targets/p9_nimbus/sbeTest" ) import testUtil +import testMemUtil as testMemProcUtil err = False -GETMEMADU_TESTDATA_ECC_ITAG = [0,0,0,0x6, - 0,0,0xA4,0x01, - 0,0,0x0,0xBD, #CoreChipletId/EccByte/Flags -> CacheInhibit/FastMode/Tag/Ecc/AutoIncr/Adu/Proc - 0,0,0,0, # Addr Upper 32 bit - 0x08,0x00,0x00,0x00, # Addr Lower 32 bit - 0x00,0x00,0x00,0x40] # length of data - -GETMEMADU_EXPDATA_ECC_ITAG = [0x00,0x00,0x00,0x50, # length of data - 0xc0,0xde,0xa4,0x01, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03]; - # MAIN Test Run Starts Here... #------------------------------------------------- def main( ): testUtil.runCycles( 10000000 ) - # GetMemAdu with Ecc with Itag test - testUtil.writeUsFifo( GETMEMADU_TESTDATA_ECC_ITAG ) - testUtil.writeEot( ) + #PutMemAdu with ECC + data = os.urandom(80) + data = [ord(c) for c in data] + testMemProcUtil.putmem(0x08000000, data, 0xBD, 0xEF) + data = testMemProcUtil.addItagEcc(data,True, True, 0xEF) - testUtil.readDsEntry ( 20 ) - testUtil.readDsFifo( GETMEMADU_EXPDATA_ECC_ITAG ) - testUtil.runCycles( 10000000 ) - testUtil.readEot( ) + # GetMemAdu test with ECC and Itag + readData = testMemProcUtil.getmem(0x08000000, 80, 0xBD) + if(data == readData): + print ("Success - Write-Read ADU with ECC,Itag") + else: + print data + print readData + raise Exception('data mistmach') + # Partial Write test + readData = testMemProcUtil.getmem(0x08000000, 40, 0xBD) + data = os.urandom(8) + data = [ord(c) for c in data] + testMemProcUtil.putmem(0x08000008, data, 0xBD, 0xEF) + data = testMemProcUtil.addItagEcc(data,True, True, 0xEF) + readBackData = testMemProcUtil.getmem(0x08000000, 40, 0xBD) + sandwichData = readData[:10]+data+readData[len(data)+10:] + if(sandwichData == readBackData): + print ("Success - Write_Part-Read ADU with ECC,Itag") + else: + print readData + print data + print readBackData + print sandwichData + raise Exception('data mistmach') #------------------------------------------------- # Calling all test code #------------------------------------------------- diff --git a/src/test/testcases/testMemPBA.py b/src/test/testcases/testMemPBA.py new file mode 100644 index 00000000..1ec1c0a4 --- /dev/null +++ b/src/test/testcases/testMemPBA.py @@ -0,0 +1,135 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testMemPBA.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016,2017 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +import testMemUtil +err = False + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): +# First Case without Fast Mode without LCO + testUtil.runCycles( 10000000 ) + # Put mem PBA + data = os.urandom(128*2) + data = [ord(c) for c in data] + testMemUtil.putmem(0x08000000, data, 0x02) + # Get mem PBA - WO FMODE, WO LCO + readData = testMemUtil.getmem(0x08000000, 128*2, 0x02) + if(data == readData): + print ("Success - Write-Read PBA - WO FMODE, WO LCO") + else: + print data + print readData + raise Exception('data mistmach') + # Partial Write test + readData = testMemUtil.getmem(0x08000000, 128*3, 0x02) + data = os.urandom(128) + data = [ord(c) for c in data] + testMemUtil.putmem(0x08000000+128, data, 0xA5) + readBackData = testMemUtil.getmem(0x08000000, 128*3, 0x02) + sandwichData = readData[:128]+data+readData[len(data)+128:] + if(sandwichData == readBackData): + print ("Success - Write_Part-Read PBA - WO FMODE, WO LCO") + else: + print readData + print data + print readBackData + print sandwichData + raise Exception('data mistmach') + +# Second Case with Fast Mode without LCO + testUtil.runCycles( 10000000 ) + # Put mem PBA - W FMODE, WO LCO + data = os.urandom(128*2) + data = [ord(c) for c in data] + testMemUtil.putmem(0x08000000, data, 0x22) + # Get mem PBA + readData = testMemUtil.getmem(0x08000000, 128*2, 0x22) + if(data == readData): + print ("Success - Write-Read PBA - W FMODE, WO LCO") + else: + print data + print readData + raise Exception('data mistmach') + # Partial Write test + readData = testMemUtil.getmem(0x08000000, 128*3, 0x22) + data = os.urandom(128) + data = [ord(c) for c in data] + testMemUtil.putmem(0x08000000+128, data, 0xA5) + readBackData = testMemUtil.getmem(0x08000000, 128*3, 0x22) + sandwichData = readData[:128]+data+readData[len(data)+128:] + if(sandwichData == readBackData): + print ("Success - Write_Part-Read PBA - W FMODE, WO LCO") + else: + print readData + print data + print readBackData + print sandwichData + raise Exception('data mistmach') + +# Third Case with Fast Mode with LCO + testUtil.runCycles( 10000000 ) + # Put mem PBA - W FMODE, W LCO + data = os.urandom(128*2) + data = [ord(c) for c in data] + testMemUtil.putmem(0x08000000, data, 0x22) + # Get mem PBA + readData = testMemUtil.getmem(0x08000000, 128*2, 0x22) + if(data == readData): + print ("Success - Write-Read PBA - W FMODE, W LCO") + else: + print data + print readData + raise Exception('data mistmach') + # Partial Write test + readData = testMemUtil.getmem(0x08000000, 128*3, 0x62) + data = os.urandom(128) + data = [ord(c) for c in data] + testMemUtil.putmem(0x08000000+128, data, 0xA5) + readBackData = testMemUtil.getmem(0x08000000, 128*3, 0x62) + sandwichData = readData[:128]+data+readData[len(data)+128:] + if(sandwichData == readBackData): + print ("Success - Write_Part-Read PBA - W FMODE, W LCO") + else: + print readData + print data + print readBackData + print sandwichData + raise Exception('data mistmach') + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testMemUtil.py b/src/test/testcases/testMemUtil.py new file mode 100644 index 00000000..95ed304b --- /dev/null +++ b/src/test/testcases/testMemUtil.py @@ -0,0 +1,114 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testMemUtil.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2017 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +import os +import struct +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False + +def gethalfword(dataInInt): + hex_string = '0'*(4-len(str(hex(dataInInt))[2:])) + str(hex(dataInInt))[2:] + return list(struct.unpack('<BB',hex_string.decode('hex'))) +def getsingleword(dataInInt): + hex_string = '0'*(8-len(str(hex(dataInInt))[2:])) + str(hex(dataInInt))[2:] + return list(struct.unpack('<BBBB',hex_string.decode('hex'))) +def getdoubleword(dataInInt): + hex_string = '0'*(16-len(str(hex(dataInInt))[:18][2:])) + str(hex(dataInInt))[:18][2:] + return list(struct.unpack('<BBBBBBBB',hex_string.decode('hex'))) + +def addItagEcc(arr, itag, ecc, eccVal=0): + arrs = [] + while len(arr) > 8: + pice = arr[:8] + arrs += pice + if(itag): + arrs += [1] + if(ecc): + arrs += [eccVal] + arr = arr[8:] + arrs += arr + if(itag): + arrs += [1] + if(ecc): + arrs += [eccVal] + return arrs + +def putmem(addr, data, flags, ecc=0): + totalLen = 5 + len(data)/4 + req = (getsingleword(totalLen) + +[ 0,0,0xA4,0x02] + +[0, ecc] + +gethalfword(flags) + #0,0,0x0,0xA5] #CoreChipletId/EccByte/Flags -> NoEccOverride/CacheInhibit/FastMode/NoTag/NoEcc/AutoIncr/Adu/Proc + + getdoubleword(addr) + + getsingleword(len(data)) # length of data + + data) + testUtil.writeUsFifo(req) + testUtil.writeEot( ) + testUtil.runCycles( 10000000 ) + lenWritten = len(data) + if(flags & 0x0008): + lenWritten += int(len(data)/8) + if(flags & 0x0010): + lenWritten += int(len(data)/8) + expData = (getsingleword(lenWritten) + +[0xc0,0xde,0xa4,0x02, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]) + testUtil.readDsFifo(expData) + testUtil.readEot( ) + +def getmem(addr, len, flags): + req = (getsingleword(6) + + [0, 0, 0xA4, 0x01] + + getsingleword(flags) + #[0,0,0x0,0xA5] + + getdoubleword(addr) + + getsingleword(len)) + testUtil.writeUsFifo(req) + testUtil.writeEot( ) + + # read data + data = [] + lenExp = len + if(flags & 0x0008): + lenExp += int(len/8) + if(flags & 0x0010): + lenExp += int(len/8) + for i in range(0, int(-(-float(lenExp)//4))): + data += list(testUtil.readDsEntryReturnVal()) + + readLen = testUtil.readDsEntryReturnVal() + if(getsingleword(lenExp) != list(readLen)): + print getsingleword(lenExp) + print list(readLen) + raise Exception("Invalid Length") + + expResp = [0xc0,0xde,0xa4,0x01, + 0x0,0x0,0x0,0x0, + 0x00,0x0,0x0,0x03]; + testUtil.readDsFifo(expResp) + testUtil.readEot( ) + return data[:lenExp] diff --git a/src/test/testcases/testPutGetMem.xml b/src/test/testcases/testPutGetMem.xml index 93d224a4..8e87e3c5 100644 --- a/src/test/testcases/testPutGetMem.xml +++ b/src/test/testcases/testPutGetMem.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -25,11 +25,6 @@ <?xml version="1.0" encoding="UTF-8"?> <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutMem.py</simcmd> + <simcmd>run-python-file targets/p9_nimbus/sbeTest/testMemPBA.py</simcmd> <exitonerror>yes</exitonerror> </testcase> - <testcase> - <simcmd>run-python-file targets/p9_nimbus/sbeTest/testGetMem_expdata.py</simcmd> - <exitonerror>yes</exitonerror> - </testcase> - diff --git a/src/test/testcases/testPutMem.py b/src/test/testcases/testPutMem.py deleted file mode 100644 index 6fb0c937..00000000 --- a/src/test/testcases/testPutMem.py +++ /dev/null @@ -1,122 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/test/testcases/testPutMem.py $ -# -# OpenPOWER sbe Project -# -# Contributors Listed Below - COPYRIGHT 2016 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -import sys -sys.path.append("targets/p9_nimbus/sbeTest" ) -import testUtil -err = False -#from testWrite import * - -LOOP_COUNT = 4 - -PUTMEM_TEST_HDR_WO_FMODE_WO_LCO = [0,0,0,0x86, - 0,0,0xA4,0x02, - 0,0,0x0,0x02, - 0,0,0,0, - 0x08,0x00,0x00,0x00, - 0x00,0x00,0x00,0x80] - -PUTMEM_TEST_HDR_W_FMODE_WO_LCO = [0,0,0,0x86, - 0,0,0xA4,0x02, - 0,0,0x0,0x22, - 0,0,0,0, - 0x08,0x00,0x00,0x00, - 0x00,0x00,0x00,0x80] - -PUTMEM_TEST_HDR_W_FMODE_W_LCO = [0,0,0,0x86, - 0,0,0xA4,0x02, - 0x20,0,0x0,0x62, - 0,0,0,0, - 0x08,0x00,0x00,0x00, - 0x00,0x00,0x00,0x80] - -PUTMEM_TEST_DATA = [0xAB,0xCD,0xEF,0x01, - 0xAB,0xCD,0xEF,0x02, - 0xAB,0xCD,0xEF,0x03, - 0xAB,0xCD,0xEF,0x04, - 0xAB,0xCD,0xEF,0x05, - 0xAB,0xCD,0xEF,0x06, - 0xAB,0xCD,0xEF,0x07, - 0xAB,0xCD,0xEF,0x08] - -PUTMEM_EXPDATA = [0x00,0x00,0x00,0x80, - 0xc0,0xde,0xa4,0x02, - 0x0,0x0,0x0,0x0, - 0x00,0x0,0x0,0x03] - - -# MAIN Test Run Starts Here... -#------------------------------------------------- -def main( ): -# First Case without Fast Mode without LCO - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( PUTMEM_TEST_HDR_WO_FMODE_WO_LCO ) - - loop = 1 - while (loop <= LOOP_COUNT): - testUtil.writeUsFifo( PUTMEM_TEST_DATA ) - loop += 1 - testUtil.writeEot( ) - - testUtil.readDsFifo( PUTMEM_EXPDATA ) - testUtil.readEot( ) - -# Second Case with Fast Mode without LCO - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( PUTMEM_TEST_HDR_W_FMODE_WO_LCO ) - - loop = 1 - while (loop <= LOOP_COUNT): - testUtil.writeUsFifo( PUTMEM_TEST_DATA ) - loop += 1 - testUtil.writeEot( ) - - testUtil.readDsFifo( PUTMEM_EXPDATA ) - testUtil.readEot( ) - -# Third Case with Fast Mode with LCO - testUtil.runCycles( 10000000 ) - testUtil.writeUsFifo( PUTMEM_TEST_HDR_W_FMODE_W_LCO ) - - loop = 1 - while (loop <= LOOP_COUNT): - testUtil.writeUsFifo( PUTMEM_TEST_DATA ) - loop += 1 - testUtil.writeEot( ) - - testUtil.readDsFifo( PUTMEM_EXPDATA ) - testUtil.readEot( ) - -#------------------------------------------------- -# Calling all test code -#------------------------------------------------- -main() - -if err: - print ("\nTest Suite completed with error(s)") - #sys.exit(1) -else: - print ("\nTest Suite completed with no errors") - #sys.exit(0); - |