diff options
3 files changed, 24 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C index bf7b1299..952076da 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C @@ -54,6 +54,8 @@ enum P9_SETUP_SBE_CONFIG_scratch4 ATTR_I2C_BUS_DIV_REF_LENGTH = 16, ATTR_NDL_MESHCTRL_SETUP_STARTBIT = 16, ATTR_NDL_MESHCTRL_SETUP_LENGTH = 4, + ATTR_MC_PLL_BUCKET_STARTBIT = 21, + ATTR_MC_PLL_BUCKET_LENGTH = 3, ATTR_OB0_PLL_BUCKET_STARTBIT = 24, ATTR_OB0_PLL_BUCKET_LENGTH = 2, ATTR_OB1_PLL_BUCKET_STARTBIT = 26, @@ -232,6 +234,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const l_read_scratch_reg.extractToRight<ATTR_OB1_PLL_BUCKET_STARTBIT, ATTR_OB1_PLL_BUCKET_LENGTH>(l_ob1_pll_bucket); l_read_scratch_reg.extractToRight<ATTR_OB2_PLL_BUCKET_STARTBIT, ATTR_OB2_PLL_BUCKET_LENGTH>(l_ob2_pll_bucket); l_read_scratch_reg.extractToRight<ATTR_OB3_PLL_BUCKET_STARTBIT, ATTR_OB3_PLL_BUCKET_LENGTH>(l_ob3_pll_bucket); + l_read_scratch_reg.extractToRight<ATTR_MC_PLL_BUCKET_STARTBIT, ATTR_MC_PLL_BUCKET_LENGTH>(l_read_1); // Workaround to handle backward compatibilty // Old drivers will keep MBX OBUS PLL bucket value as zero. So @@ -265,6 +268,9 @@ fapi2::ReturnCode p9_sbe_attr_setup(const FAPI_DBG("Setting up ATTR_NDL_MESHCTRL_SETUP"); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NDL_MESHCTRL_SETUP, i_target_chip, l_ndl_meshctrl_setup)); + FAPI_DBG("Setting up ATTR_MC_PLL_BUCKET"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_MC_PLL_BUCKET, FAPI_SYSTEM, l_read_1)); + FAPI_DBG("Setting up ATTR_OBX_PLL_BUCKET"); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB0_PLL_BUCKET, i_target_chip, l_ob0_pll_bucket)); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OB1_PLL_BUCKET, i_target_chip, l_ob1_pll_bucket)); @@ -285,6 +291,10 @@ fapi2::ReturnCode p9_sbe_attr_setup(const l_read_scratch_reg.insertFromRight< ATTR_NDL_MESHCTRL_SETUP_STARTBIT, ATTR_NDL_MESHCTRL_SETUP_LENGTH >(l_read_1); l_read_scratch_reg.flipBit< ATTR_NDL_MESHCTRL_SETUP_STARTBIT, ATTR_NDL_MESHCTRL_SETUP_LENGTH >(); + FAPI_DBG("Reading ATTR_MC_PLL_BUCKET"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_PLL_BUCKET, FAPI_SYSTEM, l_read_1)); + l_read_scratch_reg.insertFromRight< ATTR_MC_PLL_BUCKET_STARTBIT, ATTR_MC_PLL_BUCKET_LENGTH >(l_read_1); + FAPI_DBG("Reading OB PLL buckets"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB0_PLL_BUCKET, i_target_chip, l_ob0_pll_bucket)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB1_PLL_BUCKET, i_target_chip, l_ob1_pll_bucket)); diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index 1f4018f9..00f50388 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -499,5 +499,9 @@ attribute tank <name>ATTR_SYSTEM_CORECACHE_DCADJ_DISABLE</name> <value>0x0</value> </entry> + <entry> + <name>ATTR_MC_PLL_BUCKET</name> + <value>0x05</value> + </entry> </entries> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index 4344b782..64b240d7 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -767,4 +767,14 @@ <writeable/> </attribute> +<attribute> + <id>ATTR_MC_PLL_BUCKET</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>MC pll bucket selection in async mode for Cumulus</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + </attributes> |
