Dummy commit to enable optimized ppe ffdc collection on SBE

Allows new files needed to mirror gerrit review 41375 to hw/ppe
repo.

Change-Id: I3b40c36b7fbe0714732e5868465afd7f1e517c4c
RTC: 174610
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42665
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42671
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

7 files changed, 952 insertions, 0 deletions

diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.C b/src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.C
new file mode 100644
index 00000000..84a508bb
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.C
@@ -0,0 +1,284 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.C $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2017                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_collect_deadman_ffdc.C
+/// @brief Collects PPE State FFDC based on fails in the Deadman Timer
+///
+/// *HWP HW Owner        : Greg Still <stillgs@us.ibm.com>
+/// *HWP HW Backup Owner : Brian Vanderpool <vanderp@us.ibm.com>
+/// *HWP FW Owner        : Amit Tendolkar <amit.tendolkar@in.ibm.com>
+/// *HWP Team            : PM
+/// *HWP Level           : 1
+/// *HWP Consumed by     : SBE
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+#if 0
+
+#include <fapi2.H>
+#include <p9_collect_deadman_ffdc.H>
+#include <p9_sbe_ppe_ffdc.H>
+#include <p9_ppe_defs.H>
+#include <p9_eq_clear_atomic_lock.H>
+#include <p9_quad_scom_addresses.H>
+
+static const uint32_t default_32 = 0xDEADC0DE;
+static const uint64_t default_64 = 0xBADFEED0DEADC0DEULL;
+static const uint32_t DM_FFDC_SCOMS_PU_MAX = 4;
+static const uint32_t DM_FFDC_SCOMS_EX_MAX = 3;
+
+// @note This enum is used to order/index, as well as pack, data added to
+//       the array of 64 bit buffers. To optimize on space, relevant SCOM
+//       data bits are packed into bits 0-31 or 32-63 of each element
+//       in the array. SCOMs where all 64 bits are relevant are not packed.
+//       This order and packing matches that of the error xml for
+//       RC_CHECK_MASTER_STOP15_FAILED and if need be, both should change in
+//       lock-step.
+typedef enum
+{
+    FFDC_IDX_PU_SCOM_FIRST = 0,                   // 0
+    FFDC_____PU_OCB_OCI_OCCFLG32__CCSR32 = FFDC_IDX_PU_SCOM_FIRST,
+    FFDC_____PU_OCB_OCI_QCSR32__QSSR32,           // 1
+    FFDC_IDX_PU_SCOM_MAX,                         // 2
+    FFDC_IDX_EX_SCOM_FIRST = FFDC_IDX_PU_SCOM_MAX,
+    FFDC_____EQ_PPM_SSHSRC32__EX_CME_LFIR32 = FFDC_IDX_EX_SCOM_FIRST,
+    FFDC_____EX_CME_SICR_64,                      // 3
+    FFDC_____EX_CME_SISR_64,                      // 4
+    FFDC_IDX_EX_SCOM_MAX,                         // 5
+    FFDC_____EQ_ATOMIC_LOCK_REG = FFDC_IDX_EX_SCOM_MAX,
+    FFDC_____EC0_PPM_SSHSRC32__EC1_PPM_SSHSRC32,  // 6
+    FFDC_IDX_SCOM_MAX                             // 7
+}   dmanFfdcScomIndex_t;
+
+
+fapi2::ReturnCode
+p9_collect_deadman_ffdc (
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_core,
+    const p9SbeCheckMasterStop15RC_t              i_reason )
+{
+    FAPI_INF (">> p9_collect_deadman_ffdc RC: 0x%.8X", i_reason);
+    fapi2::ReturnCode l_rc;
+
+    auto l_chip = i_core.getParent<fapi2::TARGET_TYPE_PROC_CHIP>();
+    auto l_ex = i_core.getParent<fapi2::TARGET_TYPE_EX>();
+    auto l_eq = i_core.getParent<fapi2::TARGET_TYPE_EQ>();
+
+    fapi2::buffer<uint64_t> l_data64;
+
+    // Address ordering is relative to PU SCOMs in dmanFfdcScomIndex_t
+    const uint64_t l_dmFfdcPUScomAddrs[DM_FFDC_SCOMS_PU_MAX] =
+    {
+        PU_OCB_OCI_OCCFLG_SCOM, // 0x0006C08A
+        PU_OCB_OCI_CCSR_SCOM,   // 0x0006C090
+        PU_OCB_OCI_QCSR_SCOM,   // 0x0006C094
+        PU_OCB_OCI_QSSR_SCOM    // 0x0006C098
+    };
+
+    // Address ordering is relative to EX SCOMs in dmanFfdcScomIndex_t
+    const uint64_t l_dmFfdcEXScomAddrs[DM_FFDC_SCOMS_EX_MAX] =
+    {
+        EX_CME_SCOM_LFIR,       // 0x10012000
+        EX_CME_SCOM_SICR_SCOM,  // 0x1001203D
+        EX_CME_LCL_SISR_SCOM    // 0x1001204C
+    };
+
+    // Buffer to hold the packed SCOM data based on dmanFfdcScomIndex_t
+    fapi2::buffer<uint64_t> l_dmanFfdcScoms[FFDC_IDX_SCOM_MAX] = {default_64};
+
+    // Vectors to hold PPE state for SGPE and CME
+    std::vector<uint32_t> l_v_sgpe_sprs;
+    std::vector<uint64_t> l_v_sgpe_xirs;
+    std::vector<uint32_t> l_v_cme_sprs;
+    std::vector<uint64_t> l_v_cme_xirs;
+    // Init to hold defaults on ffdc access failures
+    l_v_sgpe_sprs.assign (SPR_IDX_MAX, default_32);
+    l_v_cme_sprs.assign (SPR_IDX_MAX, default_32);
+    l_v_sgpe_xirs.assign (XIR_IDX_MAX, default_64);
+    l_v_cme_xirs.assign (XIR_IDX_MAX, default_64);
+
+    // Get SGPE internal state
+    l_rc = p9_sbe_ppe_ffdc ( l_chip,
+                             SGPE_BASE_ADDRESS,
+                             l_v_sgpe_xirs,
+                             l_v_sgpe_sprs );
+
+    // Read and add PU SCOMs to the FFDC buffer
+    // Incr address for every whereas buffer index for every other iteration
+    // to allow packing 32 bit SCOM data per 64 bit buffer
+    for (uint8_t l_addrIdx = 0, l_buffIdx = FFDC_IDX_PU_SCOM_FIRST;
+         ((l_buffIdx < FFDC_IDX_PU_SCOM_MAX) ||
+          (l_addrIdx < DM_FFDC_SCOMS_PU_MAX));
+         l_buffIdx += ++l_addrIdx / 2 )
+    {
+        l_rc = fapi2::getScom ( l_chip,
+                                l_dmFfdcPUScomAddrs[l_addrIdx],
+                                l_data64 );
+
+        if (l_rc == fapi2::FAPI2_RC_SUCCESS)
+        {
+            // Copy bits 0-31 of SCOM data to the FFDC buffer entry at bits:
+            (l_addrIdx % 2) ? // even iteration?
+            (l_data64.extract<0, 32, 0> (l_dmanFfdcScoms[l_buffIdx])) : // 0-31
+            (l_data64.extract<0, 32, 32>(l_dmanFfdcScoms[l_buffIdx])); // 32-63
+        }
+        else // data already defaulted, optimize after debug
+        {
+            FAPI_ERR ( "Fail PU SCOM Addr 0x%16llX",
+                       l_dmFfdcPUScomAddrs[l_addrIdx] );
+        }
+    }
+
+    // Drop the EQ atomic lock to be able to access FFDC regs
+    l_rc = p9_clear_atomic_lock (l_eq);
+
+    if (l_rc == fapi2::FAPI2_RC_SUCCESS)
+    {
+        FAPI_ERR ("Error grabbing eq atomic lock!");
+
+        // Read & add EQ_PPM_SSHSRC bits 0-31 to the FFDC buffer
+        l_rc = fapi2::getScom ( l_eq,
+                                EQ_PPM_SSHSRC,
+                                l_data64 );
+
+        if (l_rc == fapi2::FAPI2_RC_SUCCESS)
+        {
+            // pack bits 0-31 of SCOM data to bits 0-31 of buffer entry
+            l_data64.extract<0, 32, 0> (
+                l_dmanFfdcScoms[FFDC_____EQ_PPM_SSHSRC32__EX_CME_LFIR32] );
+        }
+        else // TODO optimize away
+        {
+            FAPI_ERR ( "Fail EQ SCOM Addr 0x%16llX", EQ_PPM_SSHSRC);
+        }
+
+        // Read & add CME (EX) SCOMs to the FFDC buffer
+        // Note that unlike pu scoms above, address and buffer indices increment
+        // in lock step. The first entry is packed with the prev eq scom data
+        for ( uint8_t l_addrIdx = 0, l_buffIdx = FFDC_IDX_EX_SCOM_FIRST;
+              ((l_buffIdx < FFDC_IDX_EX_SCOM_MAX) ||
+               (l_addrIdx < DM_FFDC_SCOMS_EX_MAX));
+              ++l_buffIdx, ++l_addrIdx )
+        {
+            l_rc = fapi2::getScom ( l_ex,
+                                    l_dmFfdcEXScomAddrs[l_addrIdx],
+                                    l_data64 );
+
+            if (l_rc == fapi2::FAPI2_RC_SUCCESS)
+            {
+                if (l_buffIdx == FFDC_____EQ_PPM_SSHSRC32__EX_CME_LFIR32)
+                {
+                    // pack bits 0-31 of SCOM data to bits 32-63 of buffer entry
+                    l_data64.extract<0, 32, 32> (l_dmanFfdcScoms[l_buffIdx]);
+                }
+                else
+                {
+                    // for other 2 EX SCOMs, copy all 64 bits of data to buffer
+                    l_dmanFfdcScoms[l_buffIdx] = l_data64;
+                }
+            }
+            else // TODO optimize
+            {
+                FAPI_ERR ( "Fail EX SCOM Addr 0x%16llX",
+                           l_dmFfdcEXScomAddrs[l_addrIdx] );
+            }
+        }
+
+        // Read the CME state
+        uint8_t l_exChipUnitPos = 0;
+        FAPI_ATTR_GET ( fapi2::ATTR_CHIP_UNIT_POS, l_ex, l_exChipUnitPos );
+        uint64_t l_cmeBaseAddr = getCmeBaseAddress (l_exChipUnitPos);
+        l_rc = p9_sbe_ppe_ffdc ( l_chip,
+                                 l_cmeBaseAddr,
+                                 l_v_cme_xirs,
+                                 l_v_cme_sprs );
+    }
+    else
+    {
+        FAPI_ERR ("Error grabbing eq atomic lock! eq/ex SCOMs defaulted!");
+    }
+
+    // Add the quad atomic lock reg to FFDC
+    l_rc = fapi2::getScom ( l_eq, EQ_ATOMIC_LOCK_REG,
+                            l_dmanFfdcScoms[FFDC_____EQ_ATOMIC_LOCK_REG] );
+
+    // Read & add Core SCOM to the FFDC buffer
+    l_rc = fapi2::getScom ( i_core,
+                            C_PPM_SSHSRC,
+                            l_data64 );
+
+    if (l_rc == fapi2::FAPI2_RC_SUCCESS)
+    {
+        // C0: pack bits 0-31 of SCOM data to bits 0-31 of buffer entry
+        l_data64.extract<0, 32, 0> (
+            l_dmanFfdcScoms[FFDC_____EC0_PPM_SSHSRC32__EC1_PPM_SSHSRC32]);
+    }
+    else // TODO clean up
+    {
+        FAPI_ERR ("SCOM to C_PPM_SSHSRC failed!");
+    }
+
+    // @TODO via RTC: 173949
+    // Collect the sibling core register C_PPM_SSHSRC once we have the
+    // ATTR_FUSED_CORE_MODE function
+
+    // Add FFDC to a single FAPI RC, to avoid code bloat from multiple
+    // generated ffdc classes & error info classes per FAPI RC.
+    // Note, we are adding 19 FFDC members. Limit is 20.
+    // If needed, consider packing LR+SPRG0, SRR0+SRR1, to get space for 4 more
+    FAPI_ASSERT ( false,
+                  fapi2::CHECK_MASTER_STOP15_FAILED ()
+                  .set_SBE_CHK_MASTER_STOP15_RC (i_reason)
+                  .set_PU_OCB_OCI_OCCFLG__PU_OCB_OCI_CCSR (
+                      l_dmanFfdcScoms[FFDC_____PU_OCB_OCI_OCCFLG32__CCSR32])
+                  .set_PU_OCB_OCI_QCSR__PU_OCB_OCI_QSSR (
+                      l_dmanFfdcScoms[FFDC_____PU_OCB_OCI_QCSR32__QSSR32])
+                  .set_EQ_PPM_SSHSRC__EX_CME_SCOM_LFIR (
+                      l_dmanFfdcScoms[FFDC_____EQ_PPM_SSHSRC32__EX_CME_LFIR32])
+                  .set_EX_CME_SCOM_SICR_SCOM (
+                      l_dmanFfdcScoms[FFDC_____EX_CME_SICR_64])
+                  .set_EX_CME_LCL_SISR_SCOM (
+                      l_dmanFfdcScoms[FFDC_____EX_CME_SISR_64])
+                  .set_C0_PPM_SSHSRC__C1_PPM_SSHSRC (
+                      l_dmanFfdcScoms[FFDC_____EC0_PPM_SSHSRC32__EC1_PPM_SSHSRC32])
+                  .set_SGPE_XIR_IAR__XIR_XSR (l_v_sgpe_xirs[XIR_IDX_IAR_XSR])
+                  .set_SGPE_XIR_EDR__XIR_IR (l_v_sgpe_xirs[XIR_IDX_EDR_IR])
+                  .set_SGPE_XIR_SPRG0 (l_v_sgpe_xirs[XIR_IDX_SPRG0])
+                  .set_SGPE_SPR_LR (l_v_sgpe_sprs[SPR_IDX_LR])
+                  .set_SGPE_SPR_SRR0 (l_v_sgpe_sprs[SPR_IDX_SRR0])
+                  .set_SGPE_SPR_SRR1 (l_v_sgpe_sprs[SPR_IDX_SRR1])
+                  .set_CME_XIR_IAR__XIR_XSR (l_v_cme_xirs[XIR_IDX_IAR_XSR])
+                  .set_CME_XIR_EDR__XIR_IR (l_v_cme_xirs[XIR_IDX_EDR_IR])
+                  .set_CME_XIR_SPRG0 (l_v_cme_xirs[XIR_IDX_SPRG0])
+                  .set_CME_SPR_LR (l_v_cme_sprs[SPR_IDX_LR])
+                  .set_CME_SPR_SRR0 (l_v_cme_sprs[SPR_IDX_SRR0])
+                  .set_CME_SPR_SRR1 (l_v_cme_sprs[SPR_IDX_SRR1]),
+                  "Check Master STOP15 error 0x%.8X", i_reason );
+
+fapi_try_exit:
+    FAPI_INF ("<< p9_collect_deadman_ffdc");
+    return fapi2::current_err;
+}
+#endif
+
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.H b/src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.H
new file mode 100644
index 00000000..a5b3b1ed
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.H
@@ -0,0 +1,78 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.H $ */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2017                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_collect_deadman_ffdc.H
+/// @brief Collects PPE State FFDC based on fails in the Deadman Timer
+///
+/// *HWP HW Owner        : Greg Still <stillgs@us.ibm.com>
+/// *HWP HW Backup Owner : Brian Vanderpool <vanderp@us.ibm.com>
+/// *HWP FW Owner        : Amit Tendolkar <amit.tendolkar@in.ibm.com>
+/// *HWP Team            : PM
+/// *HWP Level           : 1
+/// *HWP Consumed by     : SBE
+
+#if 0
+#ifndef __P9_COLLECT_DEADMAN_FFDC_H__
+#define __P9_COLLECT_DEADMAN_FFDC_H__
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <return_code.H>
+#include <hwp_return_codes.H>
+
+typedef enum
+{
+    CHECK_MASTER_STOP15_INVALID_STATE,
+    CHECK_MASTER_STOP15_TIMEDOUT,
+    CHECK_MASTER_STOP15_UNKNOWN
+}   p9SbeCheckMasterStop15RC_t;
+
+/// @typedef p9_ppe_state_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_collect_deadman_ffdc_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&,
+    const p9SbeCheckMasterStop15RC_t
+);
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+/// @brief Collects FFDC related to the deadman failure
+/// @param [in] i_target Master core target which failed entering STOP15
+/// @param [in] i_reason Reason code to be added to the FFDC data
+/// @return On success, a ReturnCode object with the input HWP return code
+///                     and relevant FFDC added to it
+///         On failure, a ReturnCode object with the input HWP return code
+///                     and partial or default FFDC added to it
+fapi2::ReturnCode
+p9_collect_deadman_ffdc (
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target,
+    const p9SbeCheckMasterStop15RC_t              i_reason );
+
+#endif  // __P9_COLLECT_DEADMAN_FFDC_H__
+#endif
+
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_ffdc.C b/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_ffdc.C
new file mode 100644
index 00000000..e4cb208e
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_ffdc.C
@@ -0,0 +1,201 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_ffdc.C $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2017                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_sbe_ppe_ffdc.C
+/// @brief Get a PPE minimal internal state for debug
+///
+/// *HWP HW Owner        : Greg Still <stillgs@us.ibm.com>
+/// *HWP HW Backup Owner : Brian Vanderpool <vanderp@us.ibm.com>
+/// *HWP FW Owner        : Amit Tendolkar <amit.tendolkar@in.ibm.com>
+/// *HWP Team            : PM
+/// *HWP Level           : 1
+/// *HWP Consumed by     : SBE
+///
+/// @verbatim
+///
+/// Procedure Summary:
+///   - Reads a PPE's minimalistic state in terms of select XIRs and SPRs
+///
+/// @endverbatim
+#if 0
+
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+#include <fapi2.H>
+#include <p9_sbe_ppe_ffdc.H>
+#include <p9_sbe_ppe_utils.H>
+
+//-----------------------------------------------------------------------------
+/**
+ * @brief Collectes PPE XIRs and SPRs
+ * @param[in]    i_target        Chip Target
+ * @param[in]    i_base_address  Base address of the PPE to be used for access
+ * @param[inout] io_v_ppe_xirs   vector of PPE XIRs collected
+ *               On input, initialized with XIR_IDX_MAX elements defaulted
+ *               On ouptut, elements updated with actual XIR values read
+ * @param[inout] io_v_ppe_sprs   vector of PPE SPRs collected
+ *               On input, initialized with SPR_IDX_MAX elements defaulted
+ *               On output, elements updated with actual SPR values read
+ * @return       FAPI2_RC_SUCCESS
+ */
+fapi2::ReturnCode
+p9_sbe_ppe_ffdc (
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const uint64_t i_base_address,
+    std::vector<uint64_t>& io_v_ppe_xirs,
+    std::vector<uint32_t>& io_v_ppe_sprs )
+{
+    fapi2::ReturnCode l_rc;
+    FAPI_INF(">> p9_sbe_ppe_ffdc: Base Addr: 0x%08llX", i_base_address);
+
+    fapi2::buffer<uint64_t> l_raminstr;
+    fapi2::buffer<uint64_t> l_data64;
+    fapi2::buffer<uint32_t> l_data32;
+    bool l_ppe_halt_state = false;
+
+    // Halt the PPE before grabbing the state
+    // Ignore a fail here, the halted state is checked after the XIR loop
+    l_rc = ppe_halt(i_target, i_base_address);
+
+    FAPI_INF ("Collecting XIRs");
+
+    for (uint8_t i = XIR_IDX_IAR_XSR; i < XIR_IDX_MAX; ++i)
+    {
+        uint64_t l_address = 0;
+
+        switch (i)
+        {
+            case XIR_IDX_IAR_XSR:
+                l_address = i_base_address + PPE_XIDBGPRO;
+                break;
+
+            case XIR_IDX_EDR_IR:
+                l_address = i_base_address + PPE_XIRAMEDR;
+                break;
+
+            case XIR_IDX_SPRG0:
+                l_address = i_base_address + PPE_XIRAMDBG;
+                break;
+        }
+
+        l_rc = getScom (i_target, l_address, l_data64);
+
+        if (l_rc == fapi2::FAPI2_RC_SUCCESS)
+        {
+            io_v_ppe_xirs[i] = l_data64;
+        }
+
+        // On error, we already have the default on input, continue to next
+
+        FAPI_INF ( "XIR Idx %d Addr 0x%.8X Val: 0x%16llX",
+                   i, l_address, io_v_ppe_xirs[i]);
+    } // XIRs Loop
+
+    // Optimizing getScom of i_base_address + PPE_XIRAMDBG as we already have
+    // it from the last XIR_ID_SPRG0 iteration in the above XIR loop
+    l_ppe_halt_state = (l_data64.getBit(0, 1)) ? true : false;
+
+    // Get SPRs if PPE halted
+    if (l_ppe_halt_state)
+    {
+        FAPI_INF ("Collecting SPRs");
+
+        for (uint8_t i = 0; i < SPR_IDX_MAX; ++i)
+        {
+            uint16_t l_sprNr = 0;
+
+            switch (i)
+            {
+                case SPR_IDX_LR:
+                    l_sprNr = LR;
+                    break;
+
+                case SPR_IDX_SRR0:
+                    l_sprNr = SRR0;
+                    break;
+
+                case SPR_IDX_SRR1:
+                    l_sprNr = SRR1;
+                    break;
+            }
+
+            // SPR to R0
+            l_raminstr.flush<0>().insertFromRight (
+                ppe_getMfsprInstruction(0, l_sprNr), 0, 32 );
+
+            // TODO Do we need this for every SPR RAM access?
+            l_rc = ppe_pollHaltState(i_target, i_base_address);
+
+            if (l_rc != fapi2::FAPI2_RC_SUCCESS)
+            {
+                FAPI_ERR ("ppe_pollHaltState fail! Idx %d SPR#%d", i, l_sprNr);
+                continue; // try ramming out the next SPR
+            }
+
+            l_rc = fapi2::putScom (
+                       i_target, i_base_address + PPE_XIRAMEDR, l_raminstr );
+
+            if (l_rc != fapi2::FAPI2_RC_SUCCESS)
+            {
+                FAPI_ERR ("putScom XIRAMEDR fail!. Idx %d SPR#%d Inst 0x%16llX",
+                          i, l_sprNr, l_raminstr);
+                continue; // try ramming out the next SPR
+            }
+
+            // R0 to SPRG0
+            l_raminstr.flush<0>().insertFromRight (
+                ppe_getMtsprInstruction(0, SPRG0), 0, 32 );
+
+            l_rc = ppe_RAMRead(i_target, i_base_address, l_raminstr, l_data32);
+
+            if (l_rc == fapi2::FAPI2_RC_SUCCESS)
+            {
+                io_v_ppe_sprs[i] = l_data32;
+            }
+            else
+            {
+                FAPI_ERR ("ppe_RAMRead fail! Idx %d SPR#%d Inst 0x%16llX",
+                          i, l_sprNr, l_raminstr);
+                continue; // try ramming out the next SPR
+            }
+
+            FAPI_INF ( "Idx %d SPR# %d Value= 0x%.8X",
+                       i, l_sprNr, io_v_ppe_sprs[i] );
+        }   // SPR Loop
+    }
+    // else .. exit with defaulted SPR values, as PPE is not halted
+    else // TODO cleanup after test, convert FAPI_INF to FAPI_DBG, etc.
+    {
+        FAPI_INF("PPE is not Halted .. not collecting SPRs");
+    }
+
+    FAPI_INF ("<< p9_sbe_ppe_ffdc");
+    // Always return success
+    return fapi2::FAPI2_RC_SUCCESS;
+}
+
+#endif
+
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_ffdc.H b/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_ffdc.H
new file mode 100644
index 00000000..ab092765
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_ffdc.H
@@ -0,0 +1,85 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_ffdc.H $    */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2017                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// @file  p9_sbe_ppe_ffdc.H
+/// @brief Dumps a minimal and critical state of a PPE from SBE
+///
+/// *HWP HW Owner        : Greg Still <stillgs@us.ibm.com>
+/// *HWP HW Backup Owner : Brian Vanderpool <vanderp@us.ibm.com>
+/// *HWP FW Owner        : Amit Tendolkar <amit.tendolkar@in.ibm.com>
+/// *HWP Team            : PM
+/// *HWP Level           : 1
+/// *HWP Consumed by     : SBE
+#if 0
+
+#ifndef __P9_SBE_PPE_FFDC_H__
+#define __P9_SBE_PPE_FFDC_H__
+
+#include <target.H>
+#include <return_code.H>
+
+// PM Stop Recovery State Collection.xlsx defines what FFDC is to be collected
+// Members of this enum are ordered to optimize PPE State collection
+// and should not change
+typedef enum
+{
+    XIR_IDX_IAR_XSR = 0,
+    XIR_IDX_EDR_IR,
+    XIR_IDX_SPRG0,
+    XIR_IDX_MAX
+} SbePpeFfdcXIRIdx_t;
+
+typedef enum
+{
+    SPR_IDX_LR = 0,
+    SPR_IDX_SRR0,
+    SPR_IDX_SRR1,
+    SPR_IDX_MAX
+}   SbePpeFfdcSPRIdx_t;
+
+/// @typedef p9_sbe_ppe_ffdc_FP_t
+/// function pointer typedef definition for HWP call support
+typedef fapi2::ReturnCode (*p9_sbe_ppe_ffdc_FP_t) (
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
+    const uint64_t,
+    std::vector<uint64_t>&,
+    std::vector<uint32_t>&
+);
+
+/// @brief Collect PPE XIRs and SPRs
+/// @param [in]  i_target Chip Target
+/// @param [in]  i_base_address Base address of the PPE to be used for access
+/// @param [out] o_v_ppe_xirs vector of XIRs collected
+/// @param [out] o_v_ppe_sprs vector of SPRs collected
+/// @return FAPI2_RC_SUCCESS
+fapi2::ReturnCode
+p9_sbe_ppe_ffdc (
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const uint64_t i_base_address,
+    std::vector<uint64_t>& o_v_ppe_xirs,
+    std::vector<uint32_t>& o_v_ppe_sprs
+);
+
+#endif  // __P9_SBE_PPE_FFDC_H__
+#endif
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_utils.C b/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_utils.C
new file mode 100644
index 00000000..e295e5bc
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_utils.C
@@ -0,0 +1,144 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_utils.C $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2017                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_sbe_ppe_utils.C
+/// @brief Commonly used PPE utilities on the SBE
+///
+/// *HWP HW Owner        : Greg Still <stillgs@us.ibm.com>
+/// *HWP HW Backup Owner : Brian Vanderpool <vanderp@us.ibm.com>
+/// *HWP FW Owner        : Amit Tendolkar <amit.tendolkar@in.ibm.com>
+/// *HWP Team            : PM
+/// *HWP Level           : 1
+/// *HWP Consumed by     : SBE
+///
+/// @verbatim
+///
+/// @endverbatim
+
+#if 0
+//-----------------------------------------------------------------------------
+// Includes
+//-----------------------------------------------------------------------------
+#include <fapi2.H>
+#include <p9_sbe_ppe_utils.H>
+#include <p9_hcd_common.H>
+//-----------------------------------------------------------------------------
+
+uint32_t ppe_getMtsprInstruction( const uint16_t i_Rs, const uint16_t i_Spr )
+{
+    uint32_t mtsprInstOpcode = 0;
+    uint32_t temp = (( i_Spr & 0x03FF ) << 11);
+    mtsprInstOpcode = ( temp  & 0x0000F800 ) << 5;
+    mtsprInstOpcode |= ( temp & 0x001F0000 ) >> 5;
+    mtsprInstOpcode |= MTSPR_BASE_OPCODE;
+    mtsprInstOpcode |= ( i_Rs & 0x001F ) << 21;
+
+    return mtsprInstOpcode;
+}
+//-----------------------------------------------------------------------------
+
+uint32_t ppe_getMfsprInstruction( const uint16_t i_Rt, const uint16_t i_Spr )
+{
+    uint32_t mtsprInstOpcode = 0;
+    uint32_t temp = (( i_Spr & 0x03FF ) << 11);
+    mtsprInstOpcode = ( temp  & 0x0000F800 ) << 5;
+    mtsprInstOpcode |= ( temp & 0x001F0000 ) >> 5;
+    mtsprInstOpcode |= MFSPR_BASE_OPCODE;
+    mtsprInstOpcode |= ( i_Rt & 0x001F ) << 21;
+
+    return mtsprInstOpcode;
+}
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode ppe_pollHaltState(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const uint64_t i_base_address)
+{
+    fapi2::buffer<uint64_t> l_data64;
+
+    // Halt state entry should be very fast on PPEs (eg nanoseconds)
+    // Try only using the SCOM access time to delay.
+    uint32_t l_timeout_count = 20;
+
+    do
+    {
+        FAPI_TRY(getScom ( i_target,
+                           i_base_address + PPE_XIRAMDBG,
+                           l_data64 ),
+                 "Failed reading XIRAMDBG register!" );
+    }
+    while ((! l_data64.getBit<0>()) &&
+           (--l_timeout_count != 0));
+
+    FAPI_ASSERT ((l_data64.getBit<0>()),
+                 fapi2::SBE_PPE_UTILS_HALT_TIMEOUT_ERR(),
+                 "PPE Halt Timeout. Base Addr: 0x%16llX", i_base_address);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode ppe_halt(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const uint64_t i_base_address)
+{
+    fapi2::buffer<uint64_t> l_data64;
+
+    FAPI_INF("   Send HALT command via XCR...");
+    l_data64.flush<0>().insertFromRight(p9hcd::HALT, 1, 3);
+
+    FAPI_TRY(putScom(i_target, i_base_address + PPE_XIXCR, l_data64),
+             "Error in PUTSCOM in XCR to generate Halt condition");
+
+    FAPI_TRY(ppe_pollHaltState(i_target, i_base_address));
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+//-----------------------------------------------------------------------------
+
+fapi2::ReturnCode ppe_RAMRead(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const uint64_t i_base_address,
+    const fapi2::buffer<uint64_t> i_instruction,
+    fapi2::buffer<uint32_t>& o_data)
+{
+    fapi2::buffer<uint64_t> l_data64;
+    FAPI_TRY(ppe_pollHaltState(i_target, i_base_address));
+    FAPI_TRY(fapi2::putScom(i_target, i_base_address + PPE_XIRAMEDR, i_instruction));
+    FAPI_DBG("    RAMREAD i_instruction: 0X%16llX", i_instruction);
+    FAPI_TRY(ppe_pollHaltState(i_target, i_base_address));
+    FAPI_TRY(fapi2::getScom(i_target, i_base_address + PPE_XIRAMDBG, l_data64),
+             "Error in GETSCOM");
+    l_data64.extractToRight(o_data, 32, 32);
+    FAPI_DBG("    RAMREAD o_data: 0X%16llX", o_data);
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+//-----------------------------------------------------------------------------
+#endif
+
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_utils.H b/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_utils.H
new file mode 100644
index 00000000..43f8753b
--- /dev/null
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_utils.H
@@ -0,0 +1,125 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_utils.H $   */
+/*                                                                        */
+/* OpenPOWER sbe Project                                                  */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2017                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+///
+/// @file  p9_sbe_ppe_utils.H
+/// @brief PPE RAM utility functions for SBE
+///
+/// *HWP HW Owner        : Greg Still <stillgs@us.ibm.com>
+/// *HWP HW Backup Owner : Brian Vanderpool <vanderp@us.ibm.com>
+/// *HWP FW Owner        : Amit Tendolkar <amit.tendolkar@in.ibm.com>
+/// *HWP Team            : PM
+/// *HWP Level           : 1
+/// *HWP Consumed by     : SBE
+#if 0
+
+#ifndef __P9_SBE_PPE_UTILS_H__
+#define __P9_SBE_PPE_UTILS_H__
+
+#include <return_code.H>
+#include <target.H>
+
+/**
+ * @brief enumerates opcodes for few instructions.
+ */
+enum
+{
+    OPCODE_31         = 31,
+    MTSPR_CONST1      = 467,
+    MFSPR_CONST1      = 339,
+    MTSPR_BASE_OPCODE = (OPCODE_31 << (31 - 5)) | (MTSPR_CONST1 << (31 - 30)),
+    MFSPR_BASE_OPCODE = (OPCODE_31 << (31 - 5)) | (MFSPR_CONST1 << (31 - 30)),
+};
+
+
+/**
+ * @brief Offsets from base address for XIRs.
+ */
+const static uint64_t PPE_XIXCR    = 0x0; //XCR_NONE
+const static uint64_t PPE_XIRAMDBG = 0x3; //XSR_SPRG0
+const static uint64_t PPE_XIRAMEDR = 0x4; //IR_EDR
+const static uint64_t PPE_XIDBGPRO = 0x5; //XSR_IAR
+
+enum PPE_SPRS
+{
+    LR      = 8,
+    SRR0    = 26,
+    SRR1    = 27,
+    SPRG0   = 272,
+};
+
+/**
+ * @brief generates instruction for mtspr
+ * @param[in] i_Rs      source register number
+ * @param[in] i_Spr represents spr where data is to be moved.
+ * @return returns 32 bit instruction representing mtspr instruction.
+ */
+uint32_t ppe_getMtsprInstruction( const uint16_t i_Rs, const uint16_t i_Spr );
+
+/**
+ * @brief generates instruction for mfspr
+ * @param[in] i_Rt      target register number
+ * @param[in] i_Spr represents spr where data is to sourced
+ * @return returns 32 bit instruction representing mfspr instruction.
+ */
+uint32_t ppe_getMfsprInstruction( const uint16_t i_Rt, const uint16_t i_Spr );
+
+/**
+ * @brief poll for Halt state
+ * @param[in]   i_Rt     target register number
+ * @return  fapi2::ReturnCode
+ * @note    moves contents of register MSR to i_Rt register.
+ */
+fapi2::ReturnCode ppe_pollHaltState(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const uint64_t i_base_address);
+
+/**
+ * @brief halt the engine
+ * @param[in]   i_target  target register number
+ * @return  fapi2::ReturnCode
+ * @note    programs XCR with halt bit to halt the engine.
+ */
+fapi2::ReturnCode ppe_halt(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const uint64_t i_base_address);
+
+/**
+ * @brief Perform RAM "read" operation
+ * @param[in]   i_target        Chip Target
+ * @param[in]   i_base_address  Base SCOM address of the PPE
+ * @param[in]   i_instruction   RAM instruction to move a register
+ * @param[out]  o_data          Returned data
+ * @return  fapi2::ReturnCode
+ */
+fapi2::ReturnCode ppe_RAMRead(
+    const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
+    const uint64_t i_base_address,
+    const fapi2::buffer<uint64_t> i_instruction,
+    fapi2::buffer<uint32_t>& o_data);
+
+
+#endif  // __P9_SBE_PPE_UTILS_H__
+#endif
+
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_ppe_utils.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_ppe_utils.xml
new file mode 100755
index 00000000..1c62688c
--- /dev/null
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_ppe_utils.xml
@@ -0,0 +1,35 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/import/chips/p9/procedures/xml/error_info/p9_sbe_ppe_utils.xml $ -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2017                             -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<hwpErrors>
+  <!-- ******************************************************************** -->
+  <hwpError>
+    <sbeError/>
+    <rc>RC_SBE_PPE_UTILS_HALT_TIMEOUT_ERR</rc>
+    <description>
+      PPE Halt timed out  
+    </description>
+  </hwpError>
+  <!-- ******************************************************************** -->
+</hwpErrors>