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| author | Joe Dery <dery@us.ibm.com> | 2016-09-06 13:46:25 -0400 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-09-08 07:05:14 -0400 |
| commit | ea9c3c688646aa22dc955ca24015df499ee321b8 (patch) | |
| tree | bff42fb3d83b46e448cb82cc0d45fb75ce1451a3 /src | |
| parent | 3fe1c55beea6c4b4d2c575194fbaea56d83f1b79 (diff) | |
| download | talos-sbe-ea9c3c688646aa22dc955ca24015df499ee321b8.tar.gz talos-sbe-ea9c3c688646aa22dc955ca24015df499ee321b8.zip | |
core_chiplet_reset: SCAN_RATIO set according to ATTR_DPLL_BYPASS: 0=4:1, 1=1:1
Change-Id: I355964d3b4bc3bef5c42aa6ca13e027d16db0529
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29276
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Markus Dobler <mado@de.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29278
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C index c3bd9567..a72b4516 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C $ */ +/* $Source: src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_reset.C $ */ /* */ /* OpenPOWER sbe Project */ /* */ @@ -88,6 +88,11 @@ p9_hcd_core_chiplet_reset( { FAPI_INF(">>p9_hcd_core_chiplet_reset"); fapi2::buffer<uint64_t> l_data64; + uint8_t l_dpll_bypass; + + auto l_parent_chip = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DPLL_BYPASS, l_parent_chip, l_dpll_bypass), + "Error from FAPI_ATTR_GET (ATTR_DPLL_BYPASS)"); //-------------------------- // Reset core chiplet logic @@ -134,6 +139,21 @@ p9_hcd_core_chiplet_reset( FAPI_DBG("Drop PCB fence via NET_CTRL0[25]"); FAPI_TRY(putScom(i_target, C_NET_CTRL0_WAND, MASK_UNSET(25))); + if (l_dpll_bypass == 0) + { + FAPI_DBG("Set scan ratio to 4:1 in non-bypass mode via OPCG_ALIGN[47-51]"); + FAPI_TRY(getScom(i_target, C_OPCG_ALIGN, l_data64)); + l_data64.insertFromRight<47, 5>(0x3); + FAPI_TRY(putScom(i_target, C_OPCG_ALIGN, l_data64)); + } + else + { + FAPI_DBG("Set scan ratio to 1:1 in bypass mode via OPCG_ALIGN[47-51]"); + FAPI_TRY(getScom(i_target, C_OPCG_ALIGN, l_data64)); + l_data64.insertFromRight<47, 5>(0x0); + FAPI_TRY(putScom(i_target, C_OPCG_ALIGN, l_data64)); + } + #ifndef P9_HCD_STOP_SKIP_FLUSH //-------------------------------------------- // perform scan0 module for pervasive chiplet |
