Add SPD reader and traits DDR4 def

Includes addition of a generic const file to store
constants that are not controller dependent.
In addition to spd::c_str for SPD decoder tracing.

Change-Id: Ifd57785002c259d5c792d46325a588a3aa8851f5
Original-Change-Id: I6dafe1ff3328a1ac287b29f148e63e304f626ea5
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57492
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>

1 files changed, 79 insertions, 0 deletions

diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H
index 81470721..cb791538 100644
--- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H
+++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H
@@ -22,3 +22,82 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
+
+///
+/// @file mss_generic_consts.H
+/// @brief Common constants to be shared
+///
+
+// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com>
+// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com>
+// *HWP Team: Memory
+// *HWP Level: 3
+// *HWP Consumed by: HB:FSP
+
+#ifndef _MSS_GENERIC_CONSTS_H_
+#define _MSS_GENERIC_CONSTS_H_
+
+#include <cstdint>
+
+namespace mss
+{
+
+///
+/// @brief FFDC generic codes
+///
+enum generic_ffdc_codes
+{
+    // Starting at 0x1%%% to avoid
+    // any collisions with values
+    // from controller specific ffdc codes
+    SET_ATTR_DIMM_TYPE = 0x1000,
+    SET_ATTR_DRAM_GEN = 0x1001,
+    SET_ATTR_HYBRID = 0x1002,
+    SET_ATTR_HYBRID_MEDIA = 0x1003,
+    SET_ATTR_MASTER_RANKS = 0x1004,
+    PRE_DATA_ENGINE_CTOR = 0x1005,
+    EXTRACT_SPD_FLD = 0x1006,
+    SPD_READER = 0x1007,
+    BASE_CNFG_MAKE_OBJ = 0x1008,
+    DIMM_MODULE_MAKE_OBJ = 0x1009,
+    CREATE_BASE_CNFG_FACTORY = 0x100A,
+    CREATE_MODULE_FACTORY = 0x100B,
+    GET_TIMEBASES_FTB = 0x100F,
+    GET_TIMEBASES_MTB = 0x1010,
+};
+
+///
+/// @brief DRAM generation selector
+///
+enum device_type
+{
+    DDR4 = 0x0c,
+};
+
+enum rev : uint8_t
+{
+    V1_0 = 0x10, ///< represents Rev 1.0
+    V1_1 = 0x11, ///< represents Rev 1.1
+    V1_2 = 0x12, ///< represents Rev 1.2
+
+    // These module revisions can vary independently
+    // so we track the largest decoded revision here.
+    GEN_SEC_MAX = V1_1,
+    RDIMM_MAX = V1_1,
+    LRDIMM_MAX = V1_2,
+};
+
+///
+/// @brief SPD module parameters
+/// @note helps distinguish SPD decoder sections
+///
+enum parameters
+{
+    BASE_CNFG,
+    RDIMM_MODULE,
+    LRDIMM_MODULE,
+};
+
+}// mss
+
+#endif