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| author | Joe McGill <jmcgill@us.ibm.com> | 2017-02-22 20:52:23 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-02-24 07:30:35 -0500 |
| commit | b20b0bc1eea0552cd684ffc7532d35df8facb502 (patch) | |
| tree | f112a00332c584c4bb03a88887238263bc736ef3 /src | |
| parent | 68ea5bfbb4df69b1db558d1af76ead67ad18e4c1 (diff) | |
| download | talos-sbe-b20b0bc1eea0552cd684ffc7532d35df8facb502.tar.gz talos-sbe-b20b0bc1eea0552cd684ffc7532d35df8facb502.zip | |
adjust SRAM timings
Change-Id: Iae2a281eeebe46f316dc4c7d23e869f103b88abb
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36892
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: ALEXANDER M. TAFT <amtaft@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36893
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 21 |
1 files changed, 2 insertions, 19 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index c9d49a4d..28295d63 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -1184,10 +1184,10 @@ </attribute> <!-- ******************************************************************** --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_L3_SRAM_RELAXED_SETTINGS</id> + <id>ATTR_CHIP_EC_FEATURE_SRAM_RELAXED_SETTINGS</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - Nimbus DD1 only: SRAM relaced settings + Nimbus DD1 only: adjust/relax SRAM timing parameters </description> <chipEcFeature> <chip> @@ -1323,23 +1323,6 @@ </attribute> <!-- ******************************************************************** --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_L2_DUMMY_PULSE_POK_BITS</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - DD1 only: CAY_L2C_A102_MAC dummy pulse pok bits - </description> - <chipEcFeature> - <chip> - <name>ENUM_ATTR_NAME_NIMBUS</name> - <ec> - <value>0x20</value> - <test>LESS_THAN</test> - </ec> - </chip> - </chipEcFeature> - </attribute> - <!-- ******************************************************************** --> - <attribute> <id>ATTR_CHIP_EC_FEATURE_HW374111</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> |
