Synchronous stopclk procedure for Quad

Change-Id: Id31daf8c02b74d979927540346a3cef5f88768be
RTC: 175615
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34935
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Dev-Ready: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34939
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

9 files changed, 147 insertions, 85 deletions

diff --git a/src/import/chips/p9/common/include/p9_const_common.H b/src/import/chips/p9/common/include/p9_const_common.H
index 51e273c1..ed405843 100644
--- a/src/import/chips/p9/common/include/p9_const_common.H
+++ b/src/import/chips/p9/common/include/p9_const_common.H
@@ -78,24 +78,25 @@ struct has_fixfld
     static const uint8_t value = 255;
 };
 
-const uint32_t N0_CHIPLET_ID = 2;
-const uint32_t N1_CHIPLET_ID = 3;
-const uint32_t N2_CHIPLET_ID = 4;
-const uint32_t N3_CHIPLET_ID = 5;
-const uint32_t XB_CHIPLET_ID = 6;
-const uint32_t MC01_CHIPLET_ID = 7;
-const uint32_t MC23_CHIPLET_ID = 8;
-const uint32_t OB0_CHIPLET_ID = 9;
-const uint32_t OB1_CHIPLET_ID = 10;
-const uint32_t OB2_CHIPLET_ID = 11;
-const uint32_t OB3_CHIPLET_ID = 12;
-const uint32_t PCI0_CHIPLET_ID = 13;
-const uint32_t PCI1_CHIPLET_ID = 14;
-const uint32_t PCI2_CHIPLET_ID = 15;
-const uint32_t EC0_CHIPLET_ID = 0x20;
+const uint32_t PERV_CHIPLET_ID = 0x01;
+const uint32_t N0_CHIPLET_ID   = 0x02;
+const uint32_t N1_CHIPLET_ID   = 0x03;
+const uint32_t N2_CHIPLET_ID   = 0x04;
+const uint32_t N3_CHIPLET_ID   = 0x05;
+const uint32_t XB_CHIPLET_ID   = 0x06;
+const uint32_t MC01_CHIPLET_ID = 0x07;
+const uint32_t MC23_CHIPLET_ID = 0x08;
+const uint32_t OB0_CHIPLET_ID  = 0x09;
+const uint32_t OB1_CHIPLET_ID  = 0x0A;
+const uint32_t OB2_CHIPLET_ID  = 0x0B;
+const uint32_t OB3_CHIPLET_ID  = 0x0C;
+const uint32_t PCI0_CHIPLET_ID = 0x0D;
+const uint32_t PCI1_CHIPLET_ID = 0x0E;
+const uint32_t PCI2_CHIPLET_ID = 0x0F;
+const uint32_t EC0_CHIPLET_ID  = 0x20;
 const uint32_t EC23_CHIPLET_ID = 0x37;
-const uint32_t EQ0_CHIPLET_ID = 0x10;
-const uint32_t EQ5_CHIPLET_ID = 0x15;
+const uint32_t EQ0_CHIPLET_ID  = 0x10;
+const uint32_t EQ5_CHIPLET_ID  = 0x15;
 #define FIXREG8(name, expr, unit, meth, newexpr) template<> struct has_fixup<uint8_t,unit,meth,expr> { static const uint8_t value = newexpr; };
 #define FIXREG32(name, expr, unit, meth, newexpr) template<> struct has_fixup<uint32_t,unit,meth,expr> { static const uint32_t value = newexpr; };
 #define FIXREG64(name, expr, unit, meth, newexpr) template<> struct has_fixup<uint64_t,unit,meth,expr> { static const uint64_t value = newexpr; };
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
index e97c9082..aca9aef2 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C
@@ -67,13 +67,15 @@ fapi2::ReturnCode
 p9_hcd_cache_stopclocks(
     const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
     const p9hcd::P9_HCD_CLK_CTRL_CONSTANTS      i_select_regions,
-    const p9hcd::P9_HCD_EX_CTRL_CONSTANTS       i_select_ex)
+    const p9hcd::P9_HCD_EX_CTRL_CONSTANTS       i_select_ex,
+    const bool i_sync_stop_quad_clk)
 {
     FAPI_INF(">>p9_hcd_cache_stopclocks: regions[%016llx] ex[%d]",
              i_select_regions, i_select_ex);
     fapi2::ReturnCode                              l_rc;
     fapi2::buffer<uint64_t>                        l_data64;
     fapi2::buffer<uint64_t>                        l_temp64;
+    uint64_t                                       l_region_clock              = 0;
     uint64_t                                       l_l3mask_pscom              = 0;
     uint32_t                                       l_loops1ms                  = 0;
     uint32_t                                       l_scom_addr                 = 0;
@@ -193,7 +195,7 @@ p9_hcd_cache_stopclocks(
     // Stop L2 clocks
     // -------------------------------
 
-    if (i_select_ex)
+    if (i_select_ex && !i_sync_stop_quad_clk)
         FAPI_EXEC_HWP(fapi2::current_err,
                       p9_hcd_l2_stopclocks,
                       i_target, i_select_ex);
@@ -205,10 +207,33 @@ p9_hcd_cache_stopclocks(
     FAPI_DBG("Clear all SCAN_REGION_TYPE bits");
     FAPI_TRY(putScom(i_target, EQ_SCAN_REGION_TYPE, MASK_ZERO));
 
-    FAPI_DBG("Stop cache clocks via CLK_REGION");
-    l_data64 = (p9hcd::CLK_STOP_CMD  |
-                i_select_regions     |
-                p9hcd::CLK_THOLD_ALL);
+    l_region_clock = i_select_regions;
+
+    if(i_sync_stop_quad_clk)
+    {
+        if (i_select_ex & p9hcd::EVEN_EX)
+        {
+            l_region_clock |= p9hcd::CLK_REGION_EX0_L2;
+        }
+
+        if (i_select_ex & p9hcd::ODD_EX)
+        {
+            l_region_clock |= p9hcd::CLK_REGION_EX1_L2;
+        }
+
+        FAPI_DBG("Stop cache clocks via CLK_REGION in master mode to perform stop quad clocks synchronously");
+        l_data64 = (p9hcd::CLK_STOP_CMD_MASTER  |
+                    l_region_clock  |
+                    p9hcd::CLK_THOLD_ALL);
+    }
+    else
+    {
+        FAPI_DBG("Stop cache clocks via CLK_REGION");
+        l_data64 = (p9hcd::CLK_STOP_CMD  |
+                    l_region_clock       |
+                    p9hcd::CLK_THOLD_ALL);
+    }
+
     FAPI_TRY(putScom(i_target, EQ_CLK_REGION, l_data64));
 
     FAPI_DBG("Poll for cache clocks stopped via CPLT_STAT0[8]");
@@ -230,7 +255,7 @@ p9_hcd_cache_stopclocks(
     FAPI_DBG("Check cache clocks stopped");
     FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64));
 
-    FAPI_ASSERT((((~l_data64) & i_select_regions) == 0),
+    FAPI_ASSERT((((~l_data64) & l_region_clock) == 0),
                 fapi2::PMPROC_CACHECLKSTOP_FAILED().set_EQCLKSTAT(l_data64),
                 "Cache Clock Stop Failed");
     FAPI_DBG("Cache clocks stopped now");
@@ -243,7 +268,7 @@ p9_hcd_cache_stopclocks(
     FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, MASK_SET(3)));
 
     FAPI_DBG("Assert regional fences via CPLT_CTRL1[4-14]");
-    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, i_select_regions));
+    FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, l_region_clock));
 
     // Gate the PCBMux request so scanning doesn't cause random requests
     for(auto& it : l_core_functional_vector)
@@ -281,7 +306,7 @@ p9_hcd_cache_stopclocks(
     // QCCR[2/6] L3_EX0/1_EDRAM_VROW_VBLH_ENABLE_DC
     // QCCR[3/7] EDRAM_VPP_ENABLE_DC
 
-    if (i_select_regions & p9hcd::CLK_REGION_EX0_REFR)
+    if (l_region_clock & p9hcd::CLK_REGION_EX0_REFR)
     {
         FAPI_DBG("Sequence EX0 EDRAM disables via QPPM_QCCR[0-3]");
         FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WCLEAR, MASK_SET(3)));
@@ -290,7 +315,7 @@ p9_hcd_cache_stopclocks(
         FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WCLEAR, MASK_SET(0)));
     }
 
-    if (i_select_regions & p9hcd::CLK_REGION_EX1_REFR)
+    if (l_region_clock & p9hcd::CLK_REGION_EX1_REFR)
     {
         FAPI_DBG("Sequence EX1 EDRAM disables via QPPM_QCCR[4-7]");
         FAPI_TRY(putScom(i_target, EQ_QPPM_QCCR_WCLEAR, MASK_SET(7)));
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.H b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.H
index bafe95f0..3b693563 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.H
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -45,20 +45,24 @@
 typedef fapi2::ReturnCode (*p9_hcd_cache_stopclocks_FP_t) (
     const fapi2::Target<fapi2::TARGET_TYPE_EQ>&,
     const p9hcd::P9_HCD_CLK_CTRL_CONSTANTS,
-    const p9hcd::P9_HCD_EX_CTRL_CONSTANTS);
+    const p9hcd::P9_HCD_EX_CTRL_CONSTANTS,
+    const bool);
 
 extern "C"
 {
 
 /// @brief Quad Clock Stop
 /// @param [in] i_target TARGET_TYPE_EQ target
-/// @param [in] i_skip_regions select clk regions to skip on stopclocks
+/// @param [in] i_select_regions select clk regions on stopclocks
+/// @param [in] i_select_ex select ex's on stopclocks
+/// @param [in] i_sync_stop_quad_clk to stop CACHE & CORE chiplet clocks synchronously
 /// @return FAPI2_RC_SUCCESS if success, else error code
     fapi2::ReturnCode
     p9_hcd_cache_stopclocks(
         const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target,
         const p9hcd::P9_HCD_CLK_CTRL_CONSTANTS      i_select_regions,
-        const p9hcd::P9_HCD_EX_CTRL_CONSTANTS       i_select_ex);
+        const p9hcd::P9_HCD_EX_CTRL_CONSTANTS       i_select_ex,
+        const bool i_sync_stop_quad_clk = false);
 
 }
 
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
index 0b72b51e..f401258a 100644
--- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.C
@@ -32,7 +32,7 @@
 // *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
 // *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
 // *HWP Team               : PM
-// *HWP Consumed by        : HB:PREV
+// *HWP Consumed by        : HB:PERV
 // *HWP Level              : 2
 
 //------------------------------------------------------------------------------
@@ -65,7 +65,8 @@ enum P9_HCD_CORE_STOPCLOCKS_CONSTANTS
 
 fapi2::ReturnCode
 p9_hcd_core_stopclocks(
-    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target,
+    const bool i_sync_stop_quad_clk)
 {
     FAPI_INF(">>p9_hcd_core_stopclocks");
     fapi2::ReturnCode                              l_rc;
@@ -159,35 +160,47 @@ p9_hcd_core_stopclocks(
     FAPI_DBG("Clear all SCAN_REGION_TYPE bits");
     FAPI_TRY(putScom(i_target, C_SCAN_REGION_TYPE, MASK_ZERO));
 
-    FAPI_DBG("Stop core clocks(all but pll) via CLK_REGION");
-    l_data64 = (p9hcd::CLK_STOP_CMD           |
-                p9hcd::CLK_REGION_ALL_BUT_PLL |
-                p9hcd::CLK_THOLD_ALL);
-    FAPI_TRY(putScom(i_target, C_CLK_REGION, l_data64));
-
-    FAPI_DBG("Poll for core clocks stopped via CPLT_STAT0[8]");
-    l_loops1ms = 1E6 / CORE_CLK_STOP_POLLING_HW_NS_DELAY;
-
-    do
+    if(i_sync_stop_quad_clk)
     {
-        fapi2::delay(CORE_CLK_STOP_POLLING_HW_NS_DELAY,
-                     CORE_CLK_STOP_POLLING_SIM_CYCLE_DELAY);
+        FAPI_DBG("Stop core clocks(all but pll) via CLK_REGION in SLAVE mode");
+        l_data64 = (p9hcd::CLK_STOP_CMD_SLAVE     |
+                    p9hcd::CLK_REGION_ALL_BUT_PLL |
+                    p9hcd::CLK_THOLD_ALL);
+        FAPI_TRY(putScom(i_target, C_CLK_REGION, l_data64));
 
-        FAPI_TRY(getScom(i_target, C_CPLT_STAT0, l_data64));
     }
-    while((l_data64.getBit<8>() != 1) && ((--l_loops1ms) != 0));
+    else
+    {
+        FAPI_DBG("Stop core clocks(all but pll) via CLK_REGION");
+        l_data64 = (p9hcd::CLK_STOP_CMD           |
+                    p9hcd::CLK_REGION_ALL_BUT_PLL |
+                    p9hcd::CLK_THOLD_ALL);
+        FAPI_TRY(putScom(i_target, C_CLK_REGION, l_data64));
 
-    FAPI_ASSERT((l_loops1ms != 0),
-                fapi2::PMPROC_CORECLKSTOP_TIMEOUT().set_CORECPLTSTAT(l_data64),
-                "Core Clock Stop Timeout");
+        FAPI_DBG("Poll for core clocks stopped via CPLT_STAT0[8]");
+        l_loops1ms = 1E6 / CORE_CLK_STOP_POLLING_HW_NS_DELAY;
 
-    FAPI_DBG("Check core clocks stopped via CLOCK_STAT_SL[4-13]");
-    FAPI_TRY(getScom(i_target, C_CLOCK_STAT_SL, l_data64));
+        do
+        {
+            fapi2::delay(CORE_CLK_STOP_POLLING_HW_NS_DELAY,
+                         CORE_CLK_STOP_POLLING_SIM_CYCLE_DELAY);
+
+            FAPI_TRY(getScom(i_target, C_CPLT_STAT0, l_data64));
+        }
+        while((l_data64.getBit<8>() != 1) && ((--l_loops1ms) != 0));
 
-    FAPI_ASSERT((((~l_data64) & p9hcd::CLK_REGION_ALL_BUT_PLL) == 0),
-                fapi2::PMPROC_CORECLKSTOP_FAILED().set_CORECLKSTAT(l_data64),
-                "Core Clock Stop Failed");
-    FAPI_DBG("Core clocks stopped now");
+        FAPI_ASSERT((l_loops1ms != 0),
+                    fapi2::PMPROC_CORECLKSTOP_TIMEOUT().set_CORECPLTSTAT(l_data64),
+                    "Core Clock Stop Timeout");
+
+        FAPI_DBG("Check core clocks stopped via CLOCK_STAT_SL[4-13]");
+        FAPI_TRY(getScom(i_target, C_CLOCK_STAT_SL, l_data64));
+
+        FAPI_ASSERT((((~l_data64) & p9hcd::CLK_REGION_ALL_BUT_PLL) == 0),
+                    fapi2::PMPROC_CORECLKSTOP_FAILED().set_CORECLKSTAT(l_data64),
+                    "Core Clock Stop Failed");
+        FAPI_DBG("Core clocks stopped now");
+    }
 
     // -------------------------------
     // Disable core clock sync
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.H b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.H
index 08638b23..5dee2f07 100644
--- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.H
+++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_stopclocks.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* Contributors Listed Below - COPYRIGHT 2016,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -31,7 +31,7 @@
 // *HWP Backup HWP Owner   : Greg Still     <stillgs@us.ibm.com>
 // *HWP FW Owner           : Sangeetha T S  <sangeet2@in.ibm.com>
 // *HWP Team               : PM
-// *HWP Consumed by        : HB:PREV
+// *HWP Consumed by        : HB:PERV
 // *HWP Level              : 2
 
 #ifndef __P9_HCD_CORE_STOPCLOCKS_H__
@@ -42,17 +42,20 @@
 /// @typedef p9_hcd_core_stopclocks_FP_t
 /// function pointer typedef definition for HWP call support
 typedef fapi2::ReturnCode (*p9_hcd_core_stopclocks_FP_t) (
-    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&);
+    const fapi2::Target<fapi2::TARGET_TYPE_CORE>&,
+    const bool);
 
 extern "C"
 {
 
 /// @brief Quad Clock Stop
 /// @param [in] i_target TARGET_TYPE_EX target
+/// @param [in] i_sync_stop_quad_clk to stop CACHE & CORE chiplet clocks synchronously
 /// @return FAPI2_RC_SUCCESS if success, else error code
     fapi2::ReturnCode
     p9_hcd_core_stopclocks(
-        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target);
+        const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target,
+        const bool i_sync_stop_quad_clk = false);
 
 }
 
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H
index b433f1aa..c8443aa8 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_common.H
@@ -170,6 +170,8 @@ enum P9_HCD_MULTICAST_CONSTANTS
 enum P9_HCD_CLK_CTRL_CONSTANTS
 {
     CLK_STOP_CMD                             = BIT64(0),
+    CLK_STOP_CMD_SLAVE                       = BIT64(0) | BIT64(2),
+    CLK_STOP_CMD_MASTER                      = BIT64(0) | BIT64(3),
     CLK_START_CMD                            = BIT64(1),
     CLK_REGION_PERV                          = BIT64(4),
     CLK_REGION_ANEP                          = BIT64(10),
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_stopclocks.C b/src/import/chips/p9/procedures/hwp/perv/p9_stopclocks.C
index a4aff4f9..0aaf38ed 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_stopclocks.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_stopclocks.C
@@ -32,7 +32,7 @@
 // *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
 // *HWP Team            : Perv
 // *HWP Level           : 2
-// *HWP Consumed by     : FSP:HB
+// *HWP Consumed by     : FSP:SBE:HB
 //------------------------------------------------------------------------------
 
 //## auto_generated
@@ -53,8 +53,8 @@
 
 //------------------------------------------------------------------------------
 // Function definition:  p9_stopclocks
-// parameters: i_target                =>   chip target
-//             i_flags                 =>   flags as per the following definition
+// parameters:  i_target                      =>   chip target
+//              i_flags                       =>   flags as per the following definition
 //              i_flags.stop_nest_clks        =>   True to stop NEST chiplet clocks                              (should default TRUE)
 //              i_flags.stop_mc_clks          =>   True to stop MC chiplet clocks                                (should default TRUE)
 //              i_flags.stop_xbus_clks        =>   True to stop XBUS chiplet clocks                              (should default TRUE)
@@ -65,8 +65,9 @@
 //              i_flags.stop_vitl_clks        =>   True to stop PERVASIVE VITL clocks                            (should default FALSE)
 //              i_flags.stop_cache_clks       =>   True to stop CACHE chiplet clocks                             (should default TRUE)
 //              i_flags.stop_core_clks        =>   True to stop CORE chiplet clocks                              (should default TRUE)
-//             i_eq_clk_regions        =>   EQ chiplet clock regions of which clocks should be stopped    (default ALL_BUT_PLL_REFR)
-//             i_ex_select             =>   EX chiplet selected for clocks stop                           (default BOTH_EX)
+//              i_flags.sync_stop_quad_clks   =>   True to stop CACHE & CORE chiplet clocks synchronously        (should default TRUE)
+//              i_eq_clk_regions              =>   EQ chiplet clock regions of which clocks should be stopped    (default ALL_BUT_PLL_REFR)
+//              i_ex_select                   =>   EX chiplet selected for clocks stop                           (default BOTH_EX)
 // returns: FAPI_RC_SUCCESS if operation was successful, else error
 //------------------------------------------------------------------------------
 
@@ -102,6 +103,8 @@ fapi2::ReturnCode p9_stopclocks(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP
     bool tp_ep_rst            = true;
     bool tp_vitl_clk_off      = true;
     bool tp_mesh_clk_en       = false;
+
+    bool sync_quad_stopclocks = i_flags.sync_stop_quad_clks;
 #ifdef __PPE__
     uint8_t l_tp_chiplet_accesible = 0;
 #endif
@@ -118,9 +121,9 @@ fapi2::ReturnCode p9_stopclocks(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP
              i_flags.stop_tp_clks, i_flags.stop_pib_clks,
              i_flags.stop_vitl_clks);
     FAPI_DBG("p9_stopclocks : Input QUAD arguments received are \n\t"
-             "i_stop_cache = %d\n\t i_stop_core = %d\n\t "
+             "i_stop_cache = %d\n\t i_stop_core = %d\n\t i_sync_stop_quad = %d\n\t "
              "i_eq_clk_regions = %#018lx \n\t i_ex_select = %#018lx\n",
-             i_flags.stop_cache_clks, i_flags.stop_core_clks,
+             i_flags.stop_cache_clks, i_flags.stop_core_clks, i_flags.sync_stop_quad_clks,
              (uint64_t)i_eq_clk_regions, (uint64_t)i_ex_select);
 
     FAPI_DBG("p9_stopclocks : Check to see if the Perv Vital clocks are OFF");
@@ -236,7 +239,7 @@ fapi2::ReturnCode p9_stopclocks(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP
                 uint8_t l_attr_unit_pos = 0;
                 FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_target_cplt, l_attr_unit_pos));
 
-                if (l_attr_unit_pos == 0x01)
+                if (l_attr_unit_pos == PERV_CHIPLET_ID)
                 {
 #ifdef __PPE__
 
@@ -273,23 +276,26 @@ fapi2::ReturnCode p9_stopclocks(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP
                     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_TARGET_IS_SCOMMABLE, l_target_cplt, l_cplt_scomable));
 #endif
 
-                    if (l_attr_unit_pos == 0x02 || l_attr_unit_pos == 0x03 || l_attr_unit_pos == 0x04 || l_attr_unit_pos == 0x05)
+                    if (l_attr_unit_pos == N0_CHIPLET_ID || l_attr_unit_pos == N1_CHIPLET_ID || l_attr_unit_pos == N2_CHIPLET_ID
+                        || l_attr_unit_pos == N3_CHIPLET_ID)
                     {
                         nest_cplt_scomable = l_cplt_scomable;
                     }
-                    else if (l_attr_unit_pos == 0x06)
+                    else if (l_attr_unit_pos == XB_CHIPLET_ID)
                     {
                         xbus_cplt_scomable = l_cplt_scomable;
                     }
-                    else if (l_attr_unit_pos == 0x07 || l_attr_unit_pos == 0x08 )
+                    else if (l_attr_unit_pos == MC01_CHIPLET_ID || l_attr_unit_pos == MC23_CHIPLET_ID )
                     {
                         mc_cplt_scomable = l_cplt_scomable;
                     }
-                    else if (l_attr_unit_pos == 0x09 || l_attr_unit_pos == 0x0A || l_attr_unit_pos == 0x0B || l_attr_unit_pos == 0x0C)
+                    else if (l_attr_unit_pos == OB0_CHIPLET_ID || l_attr_unit_pos == OB1_CHIPLET_ID || l_attr_unit_pos == OB2_CHIPLET_ID
+                             || l_attr_unit_pos == OB3_CHIPLET_ID)
                     {
                         obus_cplt_scomable = l_cplt_scomable;
                     }
-                    else if (l_attr_unit_pos == 0x0D || l_attr_unit_pos == 0x0E || l_attr_unit_pos == 0x0F )
+                    else if (l_attr_unit_pos == PCI0_CHIPLET_ID || l_attr_unit_pos == PCI1_CHIPLET_ID
+                             || l_attr_unit_pos == PCI2_CHIPLET_ID )
                     {
                         pcie_cplt_scomable = l_cplt_scomable;
                     }
@@ -301,22 +307,23 @@ fapi2::ReturnCode p9_stopclocks(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP
                      obus_cplt_scomable, pcie_cplt_scomable);
 
             // Core stopclocks
-            if(i_flags.stop_core_clks)
+            if(i_flags.stop_core_clks || sync_quad_stopclocks)
             {
+
                 for (const auto& l_target_core : i_target_chip.getChildren<fapi2::TARGET_TYPE_CORE>(fapi2::TARGET_STATE_FUNCTIONAL))
                 {
                     FAPI_INF("p9_stopclocks : Calling p9_hcd_core_stopclocks");
-                    FAPI_TRY(p9_hcd_core_stopclocks(l_target_core));
+                    FAPI_TRY(p9_hcd_core_stopclocks(l_target_core, sync_quad_stopclocks));
                 }
             }
 
             // L2 & Cache stopclocks
-            if(i_flags.stop_cache_clks)
+            if(i_flags.stop_cache_clks || sync_quad_stopclocks)
             {
                 for (const auto& l_target_eq : i_target_chip.getChildren<fapi2::TARGET_TYPE_EQ>(fapi2::TARGET_STATE_FUNCTIONAL))
                 {
                     FAPI_INF("p9_stopclocks : Calling p9_hcd_cache_stopclocks");
-                    FAPI_TRY(p9_hcd_cache_stopclocks(l_target_eq, i_eq_clk_regions, i_ex_select));
+                    FAPI_TRY(p9_hcd_cache_stopclocks(l_target_eq, i_eq_clk_regions, i_ex_select, sync_quad_stopclocks));
                 }
             }
 
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_stopclocks.H b/src/import/chips/p9/procedures/hwp/perv/p9_stopclocks.H
index a5dacb06..073d7089 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_stopclocks.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_stopclocks.H
@@ -32,7 +32,7 @@
 // *HWP FW Owner        : Sunil Kumar <skumar8j@in.ibm.com>
 // *HWP Team            : Perv
 // *HWP Level           : 2
-// *HWP Consumed by     : FSP:HB
+// *HWP Consumed by     : FSP:SBE:HB
 //------------------------------------------------------------------------------
 
 
@@ -56,6 +56,7 @@ struct p9_stopclocks_flags
     uint32_t stop_vitl_clks       : 1; //True if PERV VITL clocks should be stopped, else false
     uint32_t stop_cache_clks      : 1; //True if CACHE chiplet clocks should be stopped, else false
     uint32_t stop_core_clks       : 1; //True if CORE chiplet clocks should be stopped, else false
+    uint32_t sync_stop_quad_clks  : 1; //True if CACHE & CORE chiplet clocks should be stopped synchronously, else false
     // Default constructor - fill default values
     p9_stopclocks_flags()
     {
@@ -69,6 +70,7 @@ struct p9_stopclocks_flags
         stop_vitl_clks = false;
         stop_cache_clks = true;
         stop_core_clks = true;
+        sync_stop_quad_clks = true;
     }
     // Set all the flags to false
     void clearAll()
@@ -83,6 +85,7 @@ struct p9_stopclocks_flags
         stop_vitl_clks = false;
         stop_cache_clks = false;
         stop_core_clks = false;
+        sync_stop_quad_clks = true;
     }
 };
 
@@ -96,8 +99,8 @@ extern "C"
     /**
     * @brief p9_stopclocks procedure:  The purpose of this procedure is to stop the clocks of the P9 processor chip
     *
-    * @param[in] i_target                Reference to processor chip target
-    * @param[in] i_flags                 Flags as per the following definition
+    * @param[in] i_target                      Reference to processor chip target
+    * @param[in] i_flags                       Flags as per the following definition
     *            i_flags.stop_nest_clks        True if NEST chiplet clocks should be stopped, else false
     *            i_flags.stop_mc_clks          True if MC   chiplet clocks should be stopped, else false
     *            i_flags.stop_xbus_clks        True if XBUS chiplet clocks should be stopped, else false
@@ -108,8 +111,9 @@ extern "C"
     *            i_flags.stop_vitl_clks        True if PERV VITL clocks should be stopped, else false
     *            i_flags.stop_cache_clks       True if CACHE chiplet clocks should be stopped, else false
     *            i_flags.stop_core_clks        True if CORE chiplet clocks should be stopped, else false
-    * @param[in] i_eq_clk_regions        EQ chiplet clock regions of which clocks should be stopped
-    * @param[in] i_ex_select             EX chiplet selected for clocks stop
+    *            i_flags.sync_stop_quad_clks   True if CACHE & CORE chiplet clocks should be stopped synchronously, else false
+    * @param[in] i_eq_clk_regions              EQ chiplet clock regions of which clocks should be stopped
+    * @param[in] i_ex_select                   EX chiplet selected for clocks stop
     *
     * @return ReturnCode
     */
diff --git a/src/sbefw/sbecmdmpipl.C b/src/sbefw/sbecmdmpipl.C
index 9fed63e8..f28c47e4 100644
--- a/src/sbefw/sbecmdmpipl.C
+++ b/src/sbefw/sbecmdmpipl.C
@@ -329,6 +329,7 @@ uint32_t sbeStopClocks(uint8_t *i_pArg)
                                 (p9hcd::CLK_REGION_EX0_REFR |
                                                     p9hcd::CLK_REGION_EX1_REFR);
             }
+            l_flags.sync_stop_quad_clks = false;
             SBE_EXEC_HWP(l_fapiRc, p9_stopclocks_hwp,
                           plat_getChipTarget(),
                           l_flags,
@@ -350,12 +351,13 @@ uint32_t sbeStopClocks(uint8_t *i_pArg)
                 {
                     SBE_EXEC_HWP(l_fapiRc,
                                  p9_hcd_core_stopclocks_hwp,
-                                 l_childCore);
+                                 l_childCore,
+                                 false);
                 }
             }
             else
             {
-                SBE_EXEC_HWP(l_fapiRc, p9_hcd_core_stopclocks_hwp, l_tgtHndl);
+                SBE_EXEC_HWP(l_fapiRc, p9_hcd_core_stopclocks_hwp, l_tgtHndl, false);
             }
         }
         // Specific EQ/EX
@@ -376,7 +378,8 @@ uint32_t sbeStopClocks(uint8_t *i_pArg)
             SBE_EXEC_HWP(l_fapiRc, p9_hcd_cache_stopclocks_hwp,
                          l_tgtHndl,
                          (p9hcd::P9_HCD_CLK_CTRL_CONSTANTS)l_clk_regions,
-                         (p9hcd::P9_HCD_EX_CTRL_CONSTANTS)l_ex_select);
+                         (p9hcd::P9_HCD_EX_CTRL_CONSTANTS)l_ex_select,
+                         false);
         }
 
         if( l_fapiRc != FAPI2_RC_SUCCESS )