VITAL cleaning for DD2

cq : HW399324

Change-Id: I4236b25b2587cb9705632dd55077c79e3d5cf246
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34827
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34828
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

3 files changed, 29 insertions, 92 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
index 8c9fa7ed..5e42a5dc 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
@@ -126,9 +126,6 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
     // Local variable
     uint8_t l_mc_sync_mode = 0;
     uint8_t l_pll_bypass = 0;
-    fapi2::buffer<uint8_t> l_attr_vitl_setup;
-    fapi2::buffer<uint8_t> l_attr_hang_cnt6_setup;
-    fapi2::TargetState l_target_state = fapi2::TARGET_STATE_FUNCTIONAL;
 #ifndef __PPE__
     fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
     uint8_t l_attr_system_ipl_phase;
@@ -212,9 +209,6 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
     {
 #endif
 
-        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_VITL_CLK_SETUP, i_target_chip,
-                               l_attr_vitl_setup));
-
         // NEST OBUS XBUS PCI MC - Functional
         for (auto& targ : l_perv_func_WO_Core_Cache)
         {
@@ -276,82 +270,47 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
             FAPI_TRY(p9_sbe_chiplet_reset_sectorbuffer_pulsemode_attr_setup(targ));
         }
 
-        if ( l_attr_vitl_setup )
-        {
-            l_target_state = fapi2::TARGET_STATE_PRESENT;
-        }
 
-        if(fapi2::TARGET_STATE_PRESENT == l_target_state)
+        //Perv
+        for (auto& targ : l_perv_pres)
         {
-            //Perv
-            for (auto& targ : l_perv_pres)
-            {
-                uint32_t l_chipletID = targ.getChipletNumber();
-                // Setting up partial good fence drop and resetting chiplet.
-                FAPI_DBG("PLL Setup : Enable pll");
-                FAPI_TRY(p9_sbe_chiplet_reset_pll_setup(targ, true));
-
-                if(l_chipletID == 5)
-                {
-                    FAPI_DBG("Drop clk async reset for N3 chiplet");
-                    FAPI_TRY(p9_sbe_chiplet_reset_nest_ob_async_reset(targ));
-                }
+            uint32_t l_chipletID = targ.getChipletNumber();
+            // Setting up partial good fence drop and resetting chiplet.
+            FAPI_DBG("PLL Setup : Enable pll");
+            FAPI_TRY(p9_sbe_chiplet_reset_pll_setup(targ, true));
 
-                if(l_chipletID >= 7 && l_chipletID <= 8)
-                {
-                    FAPI_DBG("Drop clk async reset for Mc chiplet");
-                    FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(targ, true));
-                }
-            }
-        }
-        else if(fapi2::TARGET_STATE_FUNCTIONAL == l_target_state)
-        {
-            //Perv
-            for (auto& targ : l_perv_func)
+            if(l_chipletID == 5)
             {
-                uint32_t l_chipletID = targ.getChipletNumber();
-                // Setting up partial good fence drop and resetting chiplet.
-                FAPI_DBG("PLL Setup : Enable pll");
-                FAPI_TRY(p9_sbe_chiplet_reset_pll_setup(targ, true));
-
-                if(l_chipletID == 5)
-                {
-                    FAPI_DBG("Drop clk async reset for N3 chiplet");
-                    FAPI_TRY(p9_sbe_chiplet_reset_nest_ob_async_reset(targ));
-                }
+                FAPI_DBG("Drop clk async reset for N3 chiplet");
+                FAPI_TRY(p9_sbe_chiplet_reset_nest_ob_async_reset(targ));
+            }
 
-                if(l_chipletID >= 7 && l_chipletID <= 8)
-                {
-                    FAPI_DBG("Drop clk async reset for Mc chiplet");
-                    FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(targ, true));
-                }
+            if(l_chipletID >= 7 && l_chipletID <= 8)
+            {
+                FAPI_DBG("Drop clk async reset for Mc chiplet");
+                FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(targ, true));
             }
         }
 
         fapi2::delay(10000, (40 * 400));
 
-        if ( l_attr_vitl_setup )
+        // Perv
+        for (auto& targ : l_perv_pres)
         {
-            l_target_state = fapi2::TARGET_STATE_PRESENT;
+            // Setting up partial good fence drop and resetting chiplet.
+            FAPI_DBG("PLL setup : Disable pll");
+            FAPI_TRY(p9_sbe_chiplet_reset_pll_setup(targ, false));
+        }
 
-            // Perv
-            for (auto& targ : l_perv_pres)
-            {
-                // Setting up partial good fence drop and resetting chiplet.
-                FAPI_DBG("PLL setup : Disable pll");
-                FAPI_TRY(p9_sbe_chiplet_reset_pll_setup(targ, false));
-            }
+        for (auto& targ : l_perv_pres)
+        {
+            // MC
+            uint32_t l_chipletID = targ.getChipletNumber();
 
-            for (auto& targ : l_perv_pres)
+            if(l_chipletID >= 7 && l_chipletID <= 8)
             {
-                // MC
-                uint32_t l_chipletID = targ.getChipletNumber();
-
-                if(l_chipletID >= 7 && l_chipletID <= 8)
-                {
-                    FAPI_DBG("Raise clk async reset for Mc chiplet");
-                    FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(targ, false));
-                }
+                FAPI_DBG("Raise clk async reset for Mc chiplet");
+                FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(targ, false));
             }
         }
 
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index b484c15b..8a2dc3b1 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -126,25 +126,7 @@
       </chip>
     </chipEcFeature>
   </attribute>
-  <!-- ********************************************************************* -->
-  <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_VITL_CLK_SETUP</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>
-      Nimbus DD1 for differentiating present/functional targets. True if:
-      Nimbus EC less than 20
-    </description>
-    <chipEcFeature>
-      <chip>
-        <name>ENUM_ATTR_NAME_NIMBUS</name>
-        <ec>
-          <value>0x20</value>
-          <test>LESS_THAN</test>
-        </ec>
-      </chip>
-    </chipEcFeature>
-  </attribute>
-  <!-- ******************************************************************** -->
+  <!-- ********************************************************************* --> 
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index daf348d1..f2c305b6 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -391,11 +391,7 @@ attribute tank
   <entry>
            <name>ATTR_CHIP_EC_FEATURE_N3_FLUSH_MODE</name>
            <virtual/>
-  </entry>
-  <entry>
-           <name>ATTR_CHIP_EC_FEATURE_VITL_CLK_SETUP</name>
-            <virtual/>
-  </entry>
+  </entry> 
   <entry>
            <name>ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING</name>
            <virtual/>