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| author | Alex Taft <amtaft@us.ibm.com> | 2017-04-23 13:55:51 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-04-28 12:18:53 -0400 |
| commit | 80d80f9215ba298a4db7c08895c6c58a60307e95 (patch) | |
| tree | 2133cd6b476c78ab83121787b32c1684fcc8e9cf /src | |
| parent | aef0490300c7ccc1166a0a1073e252c2d5913c73 (diff) | |
| download | talos-sbe-80d80f9215ba298a4db7c08895c6c58a60307e95.tar.gz talos-sbe-80d80f9215ba298a4db7c08895c6c58a60307e95.zip | |
L3 initfile updates
1) L3_CERRS_LRU_DECR_PROB_SEL_CFG should be left at default value
and not altered
3) HW375255 should be applied to all systems since rejected by ccb
4) rddsp_demotion_init_lru_cnt_cfg performance chages
Change-Id: Ic36f360da342c8f98e940642b15111d0540ddfc6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39577
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39606
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C | 6 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 35 |
2 files changed, 18 insertions, 23 deletions
diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C index e6fb5281..be84a853 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_l3_scom.C @@ -33,7 +33,6 @@ constexpr uint64_t literal_1 = 1; constexpr uint64_t literal_8 = 8; constexpr uint64_t literal_0b0 = 0b0; constexpr uint64_t literal_0b0000 = 0b0000; -constexpr uint64_t literal_0b01 = 0b01; constexpr uint64_t literal_0b0001 = 0b0001; constexpr uint64_t literal_0b0100 = 0b0100; @@ -128,11 +127,6 @@ fapi2::ReturnCode p9_l3_scom(const fapi2::Target<fapi2::TARGET_TYPE_EX>& TGT0, l_scom_buffer.insert<30, 1, 63, uint64_t>(l_EXP_L3_L3_MISC_L3CERRS_L3_CERRS_LRU_DECR_EN_CFG_ON ); } - if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) ) - { - l_scom_buffer.insert<31, 2, 62, uint64_t>(literal_0b01 ); - } - l_scom_buffer.insert<14, 4, 60, uint64_t>(literal_0b0001 ); l_scom_buffer.insert<18, 4, 60, uint64_t>(literal_0b0100 ); FAPI_TRY(fapi2::putScom(TGT0, 0x1001182bull, l_scom_buffer)); diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 34ff71fa..9a43337b 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -1256,23 +1256,6 @@ </attribute> <!-- ******************************************************************** --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_HW375255</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - Nimbus DD1 only: HW375255; Defer to DD2: Rd mach goes inactive without sending PF data bypass to L2 - </description> - <chipEcFeature> - <chip> - <name>ENUM_ATTR_NAME_NIMBUS</name> - <ec> - <value>0x20</value> - <test>LESS_THAN</test> - </ec> - </chip> - </chipEcFeature> - </attribute> - <!-- ******************************************************************** --> - <attribute> <id>ATTR_CHIP_EC_FEATURE_SRAM_RELAXED_SETTINGS</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -1958,6 +1941,24 @@ </attribute> <!-- ******************************************************************** --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW405880_LCO_IN_RETENTION</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD1; set to 0b000 + Numbus DD2+; set to 0b110 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_OPTIMAL_LCO_SCAN_ONLY</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> |
