L2 fast array procedure

Change-Id: Ibce0d60d85f8d26a42fef85c8f3b71b42f252363
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33589
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com>
Reviewed-by: Johannes Koesters <koesters@de.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35793
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

2 files changed, 65 insertions, 4 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_fastarray_abist_catchup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_fastarray_abist_catchup.C
index af0e267b..097f4d7e 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_fastarray_abist_catchup.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_fastarray_abist_catchup.C
@@ -6,6 +6,7 @@
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
 /* Contributors Listed Below - COPYRIGHT 2016,2017                        */
+/* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
@@ -39,14 +40,34 @@
 // Includes
 //-----------------------------------------------------------------------------------
 #include <p9_sbe_fastarray_abist_catchup.H>
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
 
 
 fapi2::ReturnCode p9_sbe_fastarray_abist_catchup(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
     const uint32_t i_clockCycles)
 {
-    FAPI_INF("Start");
-    FAPI_INF("End");
+    fapi2::buffer<uint64_t> l_cc_buf = i_clockCycles;
+
+    l_cc_buf.setBit<PERV_1_OPCG_REG0_GO>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_REG0, l_cc_buf), "Failed to clock %d array cycle(s)",
+             i_clockCycles + 1);
+
+    /* If we clocked more than a single cycle, do due diligence and wait for OPCG_DONE */
+    if( i_clockCycles )
+    {
+        do
+        {
+            FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_CPLT_STAT0, l_cc_buf), "Failed to read Chiplet Status 0 Register");
+        }
+        while (!l_cc_buf.getBit<PERV_1_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC>());
+    }
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
     return fapi2::current_err;
+
 }
 
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_fastarray_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_fastarray_setup.C
index 2754f0e0..56f07948 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_fastarray_setup.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_fastarray_setup.C
@@ -6,6 +6,7 @@
 /* OpenPOWER sbe Project                                                  */
 /*                                                                        */
 /* Contributors Listed Below - COPYRIGHT 2016,2017                        */
+/* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
 /* Licensed under the Apache License, Version 2.0 (the "License");        */
@@ -39,13 +40,52 @@
 // Includes
 //-----------------------------------------------------------------------------------
 #include <p9_sbe_fastarray_setup.H>
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
 
 fapi2::ReturnCode p9_sbe_fastarray_setup(
     const fapi2::Target<fapi2::TARGET_TYPE_PERV>& i_target_chiplet,
     const uint64_t i_clock_regions)
 {
-    FAPI_INF("Start");
-    FAPI_INF("End");
+    fapi2::buffer<uint64_t> buf;
+
+    /* Set up ABIST engine */
+    /* TODO: currently set up from the outside */
+
+    /* Set up clock controller to do single BIST pulses */
+    FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_OPCG_ALIGN, buf), "Failed to read OPCG_ALIGN register");
+    buf.insertFromRight<PERV_1_OPCG_ALIGN_SNOP, PERV_1_OPCG_ALIGN_SNOP_LEN>(5)
+    .insertFromRight<PERV_1_OPCG_ALIGN_SNOP_WAIT, PERV_1_OPCG_ALIGN_SNOP_WAIT_LEN>(7);
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_ALIGN, buf), "Failed to update OPCG_ALIGN register");
+
+    buf = i_clock_regions;
+    buf.setBit<PERV_1_CLK_REGION_SEL_THOLD_SL>()
+    .setBit<PERV_1_CLK_REGION_SEL_THOLD_NSL>()
+    .setBit<PERV_1_CLK_REGION_SEL_THOLD_ARY>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_CLK_REGION, buf), "Failed to set up clock regions");
+
+    buf = i_clock_regions;
+    buf.setBit<PERV_1_BIST_TC_SRAM_ABIST_MODE_DC>()
+    .setBit<PERV_1_BIST_TC_START_TEST_DC>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_BIST, buf), "Failed to set up BIST register");
+
+    buf.flush<0>();
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_REG1, buf), "Failed to clear OPCG_REG1");
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_REG2, buf), "Failed to clear OPCG_REG2");
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_CAPT3, buf), "Failed to clear OPCG_CAPT3");
+
+    buf.flush<0>()
+    .insertFromRight<PERV_1_OPCG_CAPT1_COUNT, PERV_1_OPCG_CAPT1_COUNT_LEN>(1)
+    .insertFromRight<PERV_1_OPCG_CAPT1_SEQ_01, PERV_1_OPCG_CAPT1_SEQ_01_LEN>(0x1C);
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_CAPT1, buf), "Failed to set up OPCG_CAPT1");
+
+    buf.flush<0>()
+    .insertFromRight<PERV_1_OPCG_CAPT2_SEQ_13_01EVEN, PERV_1_OPCG_CAPT2_SEQ_13_01EVEN_LEN>(0x1C);
+    FAPI_TRY(fapi2::putScom(i_target_chiplet, PERV_OPCG_CAPT2, buf), "Failed to set up OPCG_CAPT2");
+
+    return fapi2::FAPI2_RC_SUCCESS;
+
+fapi_try_exit:
     return fapi2::current_err;
 }