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authorJoe McGill <jmcgill@us.ibm.com>2017-09-06 15:48:09 -0500
committerSachin Gupta <sgupta2m@in.ibm.com>2017-09-08 21:05:22 -0400
commit76200ad4243b2b04192a95d64d6b75cc6fd30e97 (patch)
treed08d1bcd22287236da46e5af7fed99dbbcdd5f85 /src
parent94e6d03e5479c416bc92899c7e0d41e752a5469b (diff)
downloadtalos-sbe-76200ad4243b2b04192a95d64d6b75cc6fd30e97.tar.gz
talos-sbe-76200ad4243b2b04192a95d64d6b75cc6fd30e97.zip
p9_pba_coherent_utils -- remove unsafe buffer checks
Change-Id: I66696a70446bb5e7af80e46b637f445def2ac03a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45746 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45754 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_pba_access.C2
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C74
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H6
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C3
-rw-r--r--src/import/chips/p9/procedures/xml/error_info/p9_pba_errors.xml58
5 files changed, 7 insertions, 136 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.C b/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.C
index 30324bcb..5c5baa10 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_access.C
@@ -84,7 +84,7 @@ extern "C" {
//If we are not in fastmode or this is the last granule, we want to check the status
if ( i_lastGranule || (l_myPbaFlag.getFastMode() == false) )
{
- l_statusRc = p9_pba_coherent_status_check(i_target);
+ l_statusRc = p9_pba_coherent_check_status(i_target);
// Clean up PBA regardless of status check returned value.
if (i_lastGranule)
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C
index d0d0811a..6e322113 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C
@@ -399,65 +399,6 @@ extern "C"
return fapi2::current_err;
}
- fapi2::ReturnCode p9_pba_coherent_status_check(
- const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
- {
- FAPI_DBG("Start");
-
- fapi2::buffer<uint64_t> rd_buf2_valid;
- fapi2::buffer<uint64_t> rd_buf3_valid;
- fapi2::buffer<uint64_t> wr_buf0_valid;
- fapi2::buffer<uint64_t> wr_buf1_valid;
- fapi2::buffer<uint64_t> reset_buf;
-
- //Check the 2 PBA Read Buffer Valid Status (2 and 3 since we set Buffer pair "B")by reading the read buffer status (bits 33:39) and making sure it's 1
- FAPI_TRY(fapi2::getScom(i_target, PU_PBARBUFVAL2, rd_buf2_valid),
- "Error reading from the PBA Read Buffer Valid 2 Status Register");
- FAPI_TRY(fapi2::getScom(i_target, PU_PBARBUFVAL3, rd_buf3_valid),
- "Error reading from the PBA Read Buffer Valid 3 Status Register");
-
- //Check the 2 PBA Write Buffer Valid Status by reading the write buffer status (bits 35:39) and making sure it's 1
- FAPI_TRY(fapi2::getScom(i_target, PU_PBAWBUFVAL0, wr_buf0_valid),
- "Error reading from the PBA Write Buffer Valid 0 Status Register");
- FAPI_TRY(fapi2::getScom(i_target, PU_PBAWBUFVAL1, wr_buf1_valid),
- "Error reading from the PBA Write Buffer Valid 1 Status Register");
-
- //Check the PBA Slave Reset Register for if things are still in progress
- FAPI_TRY(fapi2::getScom(i_target, PU_PBASLVRST_SCOM, reset_buf),
- "Error reading from the PBA Slave Reset Register");
-
- //If there are any errors in the Status registers that we got above, collect all of the data and send an error
- //Make sure that the read buffers are empty, valid, or validwfp
- //Make sure the write buffers are empty
- //check if there is a PBA slave rest in progress and if the PBA Slave Control is busy for PBASLVCTL3
- FAPI_ASSERT(((rd_buf2_valid & PBA_RD_BUF_CRESPERR) != PBA_RD_BUF_CRESPERR) &&
- ((rd_buf3_valid & PBA_RD_BUF_CRESPERR) != PBA_RD_BUF_CRESPERR) &&
- ((wr_buf0_valid & PBA_WR_BUF_CRESPERR) != PBA_RD_BUF_CRESPERR) &&
- ((wr_buf1_valid & PBA_WR_BUF_CRESPERR) != PBA_RD_BUF_CRESPERR),
- fapi2::P9_PBA_STATUS_ERR_ADDR_ERR().set_TARGET(i_target).set_RDBUF2(
- rd_buf2_valid).set_RDBUF3(rd_buf3_valid).set_WRBUF0(
- wr_buf0_valid).set_WRBUF1(wr_buf1_valid).set_SLVRSTDATA(reset_buf),
- "Combined response address error in PBA Read Buffer, or PBA Write Buffer Registers");
-
- FAPI_ASSERT((((((rd_buf2_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_EMPTY)
- || ((rd_buf2_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_VALID)
- || ((rd_buf2_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_VALIDWFP)) )
- && (((rd_buf3_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_EMPTY)
- || ((rd_buf3_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_VALID)
- || ((rd_buf3_valid & PBA_RD_BUF_VALID_MASK) == PBA_RD_BUF_VALIDWFP) )
- && ((wr_buf0_valid & PBA_WR_BUF_VALID_MASK) == PBA_WR_BUF_EMPTY)
- && ((wr_buf1_valid & PBA_WR_BUF_VALID_MASK) == PBA_WR_BUF_EMPTY)
- && ((reset_buf & PBA_SLVRST_BUSY_IN_PROG_MASK) == 0)),
- fapi2::P9_PBA_STATUS_ERR_NO_ADDR_ERR().set_TARGET(i_target).set_RDBUF2(
- rd_buf2_valid).set_RDBUF3(rd_buf3_valid).set_WRBUF0(
- wr_buf0_valid).set_WRBUF1(wr_buf1_valid).set_SLVRSTDATA(reset_buf),
- "Unexpected state in PBA Reset, PBA Read Buffer, or PBA Write Buffer Registers");
-
- fapi_try_exit:
- FAPI_DBG("End");
- return fapi2::current_err;
- }
-
fapi2::ReturnCode p9_pba_coherent_check_ocb_status(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
{
fapi2::ReturnCode rc;
@@ -541,10 +482,9 @@ extern "C"
}
- fapi2::ReturnCode p9_pba_coherent_check_status_for_err_handling(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
+ fapi2::ReturnCode p9_pba_coherent_check_status(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
i_target)
{
- FAPI_TRY(p9_pba_coherent_status_check(i_target), "Error from p9_pba_coherent_status_check");
FAPI_TRY(p9_pba_coherent_check_pba_fir(i_target), "Error from p9_pba_coherent_check_pba_fir");
FAPI_TRY(p9_pba_coherent_check_ocb_status(i_target), "Error from p9_pba_coherent_check_ocb_status");
@@ -572,8 +512,6 @@ extern "C"
if ((o_rc == (fapi2::ReturnCode) fapi2::RC_P9_PBA_COHERENT_UTILS_INVALID_ARGS)
|| (o_rc == (fapi2::ReturnCode) fapi2::RC_P9_PBA_COHERENT_UTILS_RESET_ERR)
- || (o_rc == (fapi2::ReturnCode) fapi2::RC_P9_PBA_STATUS_ERR_ADDR_ERR)
- || (o_rc == (fapi2::ReturnCode) fapi2::RC_P9_PBA_STATUS_ERR_NO_ADDR_ERR)
|| (o_rc == (fapi2::ReturnCode) fapi2::RC_P9_PBA_FBC_NOT_INITIALIZED_ERR)
|| (o_rc == (fapi2::ReturnCode) fapi2::RC_P9_PBA_COHERENT_UTILS_OCB_STATUS_MISMATCH)
|| (o_rc == (fapi2::ReturnCode) fapi2::RC_P9_PBA_COHERENT_UTILS_PBA_FIR_ERR_ADDR_ERR)
@@ -684,7 +622,7 @@ extern "C"
// PIB is unlocked, analyze state of FIRs/state machines to see if the SCOM
// failure was a result of a read failure on the fabric launched by PBA
- l_return_rc = p9_pba_coherent_check_status_for_err_handling(i_target);
+ l_return_rc = p9_pba_coherent_check_status(i_target);
if (l_return_rc != fapi2::FAPI2_RC_SUCCESS)
{
@@ -692,16 +630,14 @@ extern "C"
// a functional failure in PBA that could result in the SCOM failure as a side-effect
if ((l_return_rc == (fapi2::ReturnCode) fapi2::RC_P9_PBA_COHERENT_UTILS_PBA_FIR_ERR_ADDR_ERR) ||
(l_return_rc == (fapi2::ReturnCode) fapi2::RC_P9_PBA_COHERENT_UTILS_PBA_FIR_ERR_NO_ADDR_ERR) ||
- (l_return_rc == (fapi2::ReturnCode) fapi2::RC_P9_PBA_COHERENT_UTILS_OCB_STATUS_MISMATCH) ||
- (l_return_rc == (fapi2::ReturnCode) fapi2::RC_P9_PBA_STATUS_ERR_ADDR_ERR) ||
- (l_return_rc == (fapi2::ReturnCode) fapi2::RC_P9_PBA_STATUS_ERR_NO_ADDR_ERR))
+ (l_return_rc == (fapi2::ReturnCode) fapi2::RC_P9_PBA_COHERENT_UTILS_OCB_STATUS_MISMATCH))
{
- FAPI_ERR("Error from p9_pba_coherent_check_status_for_err_handling, returning PBA rc");
+ FAPI_ERR("Error from p9_pba_coherent_check_status, returning PBA rc");
}
// none of these match, return the original return code as it was the first error
else
{
- FAPI_ERR("Error from p9_pba_coherent_check_status_for_err_handling, returning original SCOM fail rc");
+ FAPI_ERR("Error from p9_pba_coherent_check_status, returning original SCOM fail rc");
l_return_rc = i_rc;
}
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H
index 804d1cb4..a2b0becd 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.H
@@ -261,10 +261,6 @@ extern "C"
fapi2::ReturnCode p9_pba_coherent_utils_check_args(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target,
const uint64_t i_address);
-/// @brief this checks the PBA/OCB status registers - this is for use at the end of each write/read or at the end of each stream
-/// @return FAPI_RC_SUCCESS if the status check is a success
- fapi2::ReturnCode p9_pba_coherent_status_check(
- const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target);
/// @brief this does any cleanup for the PBA after all reads/writes have been done
/// @param[in] i_target => P9 chip target
@@ -300,7 +296,7 @@ extern "C"
///@brief calls all of the error checking procedures (ocb_status, check_pba_fir, and status_check)
///@param[in] i_target => P9 chip target
///@return FAPI_RC_SUCCESS if no errors are detected on the PBA
- fapi2::ReturnCode p9_pba_coherent_check_status_for_err_handling(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
+ fapi2::ReturnCode p9_pba_coherent_check_status(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&
i_target);
///@brief appends input data to the fapi2 return code if we got an error back
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C
index 687c77ec..36172229 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_setup.C
@@ -71,9 +71,6 @@ extern "C"
//reset the PBA - cleanup just calls reset
FAPI_TRY(p9_pba_coherent_cleanup_pba(i_target), "Error from p9_pba_cleanup_pba");
- //Check to make sure that it's ready for another write
- FAPI_TRY(p9_pba_coherent_status_check(i_target), "Error from p9_pba_coherent_status_check");
-
//The PBA Bar and PBA Bar Mask need to be setup before getting the number of granules because how they get setup affects the number of granules that can be read/written
//setup the PBA Bar
FAPI_TRY(p9_pba_coherent_setup_pba_bar(i_target, i_address),
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pba_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pba_errors.xml
index 397852c4..115ddf04 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_pba_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_pba_errors.xml
@@ -90,64 +90,6 @@
<!-- ******************************************************************** -->
<hwpError>
<sbeError/>
- <rc>RC_P9_PBA_STATUS_ERR_ADDR_ERR</rc>
- <description>
- Procedure: p9_pba_coherent_utils
- PBA Read Status, Write Status, or Reset Register indicated an error,
- with an indication of a combined response address error.
- </description>
- <ffdc>TARGET</ffdc>
- <ffdc>RDBUF2</ffdc>
- <ffdc>RDBUF3</ffdc>
- <ffdc>WRBUF0</ffdc>
- <ffdc>WRBUF1</ffdc>
- <ffdc>SLVRSTDATA</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PBA_REGISTERS</id>
- <targetType>TARGET_TYPE_PROC_CHIP</targetType>
- <target>TARGET</target>
- </collectRegisterFfdc>
- <callout>
- <procedure>CODE</procedure>
- <priority>HIGH</priority>
- </callout>
- <callout>
- <target>TARGET</target>
- <priority>MEDIUM</priority>
- </callout>
- </hwpError>
- <!-- ******************************************************************** -->
- <hwpError>
- <sbeError/>
- <rc>RC_P9_PBA_STATUS_ERR_NO_ADDR_ERR</rc>
- <description>
- Procedure: p9_pba_coherent_utils
- PBA Read Status, Write Status, or Reset Register indicated an error,
- with no indication of a combined response address error.
- </description>
- <ffdc>TARGET</ffdc>
- <ffdc>RDBUF2</ffdc>
- <ffdc>RDBUF3</ffdc>
- <ffdc>WRBUF0</ffdc>
- <ffdc>WRBUF1</ffdc>
- <ffdc>SLVRSTDATA</ffdc>
- <collectRegisterFfdc>
- <id>REG_FFDC_PBA_REGISTERS</id>
- <targetType>TARGET_TYPE_PROC_CHIP</targetType>
- <target>TARGET</target>
- </collectRegisterFfdc>
- <callout>
- <target>TARGET</target>
- <priority>HIGH</priority>
- </callout>
- <callout>
- <procedure>CODE</procedure>
- <priority>MEDIUM</priority>
- </callout>
- </hwpError>
- <!-- ******************************************************************** -->
- <hwpError>
- <sbeError/>
<rc>RC_P9_PBA_FBC_NOT_INITIALIZED_ERR</rc>
<description>
Procedure: p9_pba_coherent_utils
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