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| author | Dan Crowell <dcrowell@us.ibm.com> | 2017-06-08 21:44:44 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-06-13 00:12:33 -0400 |
| commit | 69184204d4d86b53f795acc25867c03f4885bf3b (patch) | |
| tree | 71f3d3699a8fd237ea79bab4f62dd39dd85dabcc /src | |
| parent | de7270c25782072676995c26a262cf5ef0b8762a (diff) | |
| download | talos-sbe-69184204d4d86b53f795acc25867c03f4885bf3b.tar.gz talos-sbe-69184204d4d86b53f795acc25867c03f4885bf3b.zip | |
Fix alignment issues in SBE-HB structure
Add padding to keep all fields aligned to 8-bytes
Add explicit attribute to ensure structure is packed
Change-Id: I55ca10034d7adf3e766edb4d0071f649c7c90446
CQ: SW391259
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41584
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41613
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H | 10 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C | 17 |
2 files changed, 18 insertions, 9 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H index 38ce24c1..d82448e9 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H @@ -74,6 +74,8 @@ union BootloaderSecureSettings }; // Structure starts at the bootloader zero address +// Note - this structure must remain 64-bit aligned to +// maintain compatibility with Hostboot struct BootloaderConfigData_t { uint32_t version; // bytes 4:7 Version field so we know if there is new data being added @@ -82,8 +84,10 @@ struct BootloaderConfigData_t uint16_t pnorSizeMB; // bytes 10:11 Size of PNOR in MB [ATTR_PNOR_SIZE] uint64_t blLoadSize; // bytes 12:19 Size of Load (Exception vectors and Bootloader) BootloaderSecureSettings secureSettings ; // byte 20 - uint64_t xscomBAR; // bytes 21:28 XSCOM MMIO BAR - uint64_t lpcBAR; // bytes 29:36 LPC MMIO BAR -}; + uint8_t reserved[7]; // bytes 21:27 Reserved space to maintain 64-bit alignment + uint64_t xscomBAR; // bytes 28:35 XSCOM MMIO BAR + uint64_t lpcBAR; // bytes 36:43 LPC MMIO BAR +}; // Note: Want to use '__attribute__((packed))' but compiler won't let us + #endif diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C index b4138e1e..3ad213b5 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C @@ -296,15 +296,20 @@ fapi2::ReturnCode p9_sbe_load_bootloader( { l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.secureSettings.data8; } - //At address X + 0x1B (21-28) put the XSCOM BAR - else if (i < 29) + //At address X + 0x15 (21-27) put a zero + else if (i < 28) { - l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.xscomBAR >> (56 - 8 * ((i - 21) % 8))) & 0xFF; + l_data_to_pass_to_pba_array[i] = 0; } - //At address X + 0x1B (29-36) put the LPC BAR - else if (i < 37) + //At address X + 0x1B (28-35) put the XSCOM BAR + else if (i < 36) { - l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.lpcBAR >> (56 - 8 * ((i - 29) % 8))) & 0xFF; + l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.xscomBAR >> (56 - 8 * ((i - 28) % 8))) & 0xFF; + } + //At address X + 0x1B (36-43) put the LPC BAR + else if (i < 44) + { + l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.lpcBAR >> (56 - 8 * ((i - 36) % 8))) & 0xFF; } //Fill the rest with the exception vector instruction else |
