diff options
| author | Srinivas Naga <srinivan@in.ibm.com> | 2016-10-07 10:10:24 +0200 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-10-10 13:23:02 -0400 |
| commit | 505c26b059c1ee892abe6ecc75e5c965f7dd8185 (patch) | |
| tree | 02babe137e3c52b6242d6f66c477e9f64a28755b /src | |
| parent | 0b281e456009d372469eb3e0a7937d71330d3f3e (diff) | |
| download | talos-sbe-505c26b059c1ee892abe6ecc75e5c965f7dd8185.tar.gz talos-sbe-505c26b059c1ee892abe6ecc75e5c965f7dd8185.zip | |
Slowdown after L2cache CE inject
Change-Id: Id4865ca8957a8bb82edb524d5aaf009efd646c85
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30861
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30865
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C index 69b617f2..3e966aef 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init3.C @@ -26,6 +26,11 @@ /// @file p9_sbe_tp_chiplet_init3.C /// /// @brief TP Chiplet Start Clocks +/// Starting clocks for all regions in perv chiplet other than pib and net +/// Clock test to check osc runnong +/// Configures pfet controls, tod errr regs , perv hang counters +/// pervasive LFIRS and set mask in IPOLL mask reg +/// Starts VREF calibration and checks for Calib Done //------------------------------------------------------------------------------ // *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> // *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> @@ -59,7 +64,8 @@ enum P9_SBE_TP_CHIPLET_INIT3_Private_Constants OSC_ERROR_MASK = 0xF700000000000000, // Mask OSC errors LFIR_ACTION0_VALUE = 0x0000000000000000, LFIR_ACTION1_VALUE = 0x8000000000000000, - FIR_MASK_VALUE = 0xFFFFFFFFFFC00000 + FIR_MASK_VALUE = 0xFFFFFFFFFFC00000, + IPOLL_MASK_VALUE = 0xFC00000000000000 }; static fapi2::ReturnCode p9_sbe_tp_chiplet_init3_clock_test2( @@ -190,6 +196,11 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init3(const l_data64.clearBit<6>(); //PERV.HANG_PULSE_5_REG.SUPPRESS_HANG_5 = 0b0 FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_HANG_PULSE_5_REG, l_data64)); + + // Mask IPOLL to hostbridge + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_HOST_MASK_REG, IPOLL_MASK_VALUE)); + + FAPI_DBG("Start calibration"); //Setting KVREF_AND_VMEAS_MODE_STATUS_REG register value FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_KVREF_AND_VMEAS_MODE_STATUS_REG, l_data64)); |
