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| author | Yue Du <daviddu@us.ibm.com> | 2016-11-15 20:47:54 -0600 |
|---|---|---|
| committer | spashabk-in <shakeebbk@in.ibm.com> | 2016-12-20 05:18:26 -0600 |
| commit | 361016907f34a41073e6834b9d40bf7f101157d1 (patch) | |
| tree | 137aab38c451e6b7f494a2981885a738d9aafd62 /src | |
| parent | 1d836bf7b2677c217f708189d2686e66c2089dd5 (diff) | |
| download | talos-sbe-361016907f34a41073e6834b9d40bf7f101157d1.tar.gz talos-sbe-361016907f34a41073e6834b9d40bf7f101157d1.zip | |
Istep4: Shouldn't set group_id in cache-contained mode
Change-Id: I44066d66d85e351e5a9f19571caff35d0fad7d52
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32693
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com>
Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32718
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C | 18 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C | 18 |
2 files changed, 22 insertions, 14 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C index 81cf5ebe..28d836a5 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C @@ -219,13 +219,17 @@ p9_hcd_cache_startclocks( FAPI_DBG("Reset abstclk & syncclk muxsel(io_clk_sel) via CPLT_CTRL0[0:1]"); FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_CLR(0, 2, 3))); - FAPI_DBG("Set fabric group ID[%x] chip ID[%x] system ID[%x]", - l_attr_group_id, l_attr_chip_id, l_attr_system_id); - FAPI_TRY(getScom(i_target, EQ_CPLT_CONF0, l_data64)); - l_data64.insertFromRight<48, 4>(l_attr_group_id). - insertFromRight<52, 3>(l_attr_chip_id). - insertFromRight<56, 5>(l_attr_system_id); - FAPI_TRY(putScom(i_target, EQ_CPLT_CONF0, l_data64)); + if (l_attr_system_ipl_phase != + fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED) + { + FAPI_DBG("Set fabric group ID[%x] chip ID[%x] system ID[%x]", + l_attr_group_id, l_attr_chip_id, l_attr_system_id); + FAPI_TRY(getScom(i_target, EQ_CPLT_CONF0, l_data64)); + l_data64.insertFromRight<48, 4>(l_attr_group_id). + insertFromRight<52, 3>(l_attr_chip_id). + insertFromRight<56, 5>(l_attr_system_id); + FAPI_TRY(putScom(i_target, EQ_CPLT_CONF0, l_data64)); + } // ------------------------------- // Align chiplets diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C index 604692fc..399ccaf6 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C @@ -177,13 +177,17 @@ p9_hcd_core_startclocks( FAPI_DBG("Reset abstclk & syncclk muxsel(io_clk_sel) via CPLT_CTRL0[0:1]"); FAPI_TRY(putScom(i_target, C_CPLT_CTRL0_CLEAR, MASK_CLR(0, 2, 3))); - FAPI_DBG("Set fabric group ID[%x] chip ID[%x] system ID[%x]", - l_attr_group_id, l_attr_chip_id, l_attr_system_id); - FAPI_TRY(getScom(i_target, C_CPLT_CONF0, l_data64)); - l_data64.insertFromRight<48, 4>(l_attr_group_id). - insertFromRight<52, 3>(l_attr_chip_id). - insertFromRight<56, 5>(l_attr_system_id); - FAPI_TRY(putScom(i_target, C_CPLT_CONF0, l_data64)); + if (l_attr_system_ipl_phase != + fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED) + { + FAPI_DBG("Set fabric group ID[%x] chip ID[%x] system ID[%x]", + l_attr_group_id, l_attr_chip_id, l_attr_system_id); + FAPI_TRY(getScom(i_target, C_CPLT_CONF0, l_data64)); + l_data64.insertFromRight<48, 4>(l_attr_group_id). + insertFromRight<52, 3>(l_attr_chip_id). + insertFromRight<56, 5>(l_attr_system_id); + FAPI_TRY(putScom(i_target, C_CPLT_CONF0, l_data64)); + } // ------------------------------- // Align chiplets |
