Enablement of additional eq_ana_bndy rings for Nimbus DD2

- ex_l2_fure_1 and ex_l3_fure_1 rings have been removed

Change-Id: Ia9fd9bce71b24a8512338c26020d60ef38bbf96c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37720
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Martin Peschke <mpeschke@de.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38092
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

5 files changed, 104 insertions, 27 deletions

diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C
index 78fe0f36..f75bbb27 100644
--- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C
+++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_l3_dcc_setup.C
@@ -52,9 +52,9 @@ fapi2::ReturnCode p9_hcd_cache_chiplet_l3_dcc_setup(const
     uint8_t l_read_attr = 0;
     FAPI_DBG("Entering ...");
 
-    FAPI_DBG("Scan eq_ana_bndy_l3dcc_bucket_26 ring");
-    FAPI_TRY(fapi2::putRing(i_target_chiplet, eq_ana_bndy_l3dcc_bucket_26, fapi2::RING_MODE_SET_PULSE_NSL),
-             "Error from putRing (eq_ana_bndy_l3dcc_bucket_26)");
+    FAPI_DBG("Scan eq_ana_bndy_bucket_l3dcc ring");
+    FAPI_TRY(fapi2::putRing(i_target_chiplet, eq_ana_bndy_bucket_l3dcc, fapi2::RING_MODE_SET_PULSE_NSL),
+             "Error from putRing (eq_ana_bndy_bucket_l3dcc)");
 
     FAPI_DBG("Drop L3 DCC bypass");
     //Setting NET_CTRL1 register value
diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.C b/src/import/chips/p9/utils/imageProcs/p9_ringId.C
index 983653d0..307fe450 100644
--- a/src/import/chips/p9/utils/imageProcs/p9_ringId.C
+++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.C
@@ -395,18 +395,32 @@ const GenRingIdList RING_ID_LIST_COMMON[] =
     {"eq_ana_bndy_bucket_23"      , 0x29, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
     {"eq_ana_bndy_bucket_24"      , 0x2a, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
     {"eq_ana_bndy_bucket_25"      , 0x2b, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
-    {"eq_ana_bndy_l3dcc_bucket_26", 0x2c, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_l3dcc"   , 0x2c, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
     {"eq_ana_mode"                , 0x2d, 0x10, 0x10, EKB_RING    , 0x10030101},
-    {"ex_l2_fure_1"               , 0x2e, 0x10, 0x10, EKB_RING    , 0x1003040F},
-    {"ex_l3_fure_1"               , 0x2f, 0x10, 0x10, EKB_RING    , 0x1003100F},
+    {"eq_ana_bndy_bucket_26"      , 0x2e, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_27"      , 0x2f, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_28"      , 0x30, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_29"      , 0x31, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_30"      , 0x32, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_31"      , 0x33, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_32"      , 0x34, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_33"      , 0x35, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_34"      , 0x36, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_35"      , 0x37, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_36"      , 0x38, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_37"      , 0x39, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_38"      , 0x3a, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_39"      , 0x3b, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_40"      , 0x3c, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
+    {"eq_ana_bndy_bucket_41"      , 0x3d, 0x10, 0x10, EKB_FSM_RING, 0x10030108},
 };
 const GenRingIdList RING_ID_LIST_INSTANCE[] =
 {
-    {"eq_repr"                    , 0x30, 0x10, 0x1b, VPD_RING    , 0x10036086},
-    {"ex_l3_repr"                 , 0x31, 0x10, 0x1b, VPD_RING    , 0x10031006},
-    {"ex_l2_repr"                 , 0x32, 0x10, 0x1b, VPD_RING    , 0x10030406},
-    {"ex_l3_refr_repr"            , 0x33, 0x10, 0x1b, VPD_RING    , 0x10030046},
-    {"ex_l3_refr_time"            , 0x34, 0x10, 0x1b, VPD_RING    , 0x10030047},
+    {"eq_repr"                    , 0x3e, 0x10, 0x1b, VPD_RING    , 0x10036086},
+    {"ex_l3_repr"                 , 0x3f, 0x10, 0x1b, VPD_RING    , 0x10031006},
+    {"ex_l2_repr"                 , 0x40, 0x10, 0x1b, VPD_RING    , 0x10030406},
+    {"ex_l3_refr_repr"            , 0x41, 0x10, 0x1b, VPD_RING    , 0x10030046},
+    {"ex_l3_refr_time"            , 0x42, 0x10, 0x1b, VPD_RING    , 0x10030047},
 };
 const RingVariantOrder RING_VARIANT_ORDER[] = { BASE, CC, RL };
 };
diff --git a/src/import/chips/p9/utils/imageProcs/p9_ringId.H b/src/import/chips/p9/utils/imageProcs/p9_ringId.H
index 0a1ead3e..bf886cb8 100644
--- a/src/import/chips/p9/utils/imageProcs/p9_ringId.H
+++ b/src/import/chips/p9/utils/imageProcs/p9_ringId.H
@@ -778,10 +778,24 @@ enum RingOffset
     eq_ana_bndy_bucket_23  = 41,
     eq_ana_bndy_bucket_24  = 42,
     eq_ana_bndy_bucket_25  = 43,
-    eq_ana_bndy_l3dcc_bucket_26  = 44,
+    eq_ana_bndy_bucket_l3dcc  = 44,
     eq_ana_mode     = 45,
-    ex_l2_fure_1    = 46,
-    ex_l3_fure_1    = 47,
+    eq_ana_bndy_bucket_26 = 46,
+    eq_ana_bndy_bucket_27 = 47,
+    eq_ana_bndy_bucket_28 = 48,
+    eq_ana_bndy_bucket_29 = 49,
+    eq_ana_bndy_bucket_30 = 50,
+    eq_ana_bndy_bucket_31 = 51,
+    eq_ana_bndy_bucket_32 = 52,
+    eq_ana_bndy_bucket_33 = 53,
+    eq_ana_bndy_bucket_34 = 54,
+    eq_ana_bndy_bucket_35 = 55,
+    eq_ana_bndy_bucket_36 = 56,
+    eq_ana_bndy_bucket_37 = 57,
+    eq_ana_bndy_bucket_38 = 58,
+    eq_ana_bndy_bucket_39 = 59,
+    eq_ana_bndy_bucket_40 = 60,
+    eq_ana_bndy_bucket_41 = 61,
 
     // Instance Rings
     eq_repr         = (0 | INSTANCE_RING_MARK),
@@ -794,7 +808,7 @@ enum RingOffset
 static const CHIPLET_DATA g_eqData =
 {
     16, // Quad Chiplet ID range is 16 - 21. The base ID is 16.
-    48, // 48 common rings for Quad chiplet.
+    62, // 62 common rings for Quad chiplet.
     5,  // 5 instance specific rings for each EQ chiplet
     9   // 9 different rings since 2 per EX ring and 1 per EQ
 };
@@ -1071,7 +1085,7 @@ static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] =
     { EQ::eq_ana_bndy_bucket_23          , "eq_ana_bndy_bucket_23"       , EQ_TYPE    }, // 215
     { EQ::eq_ana_bndy_bucket_24          , "eq_ana_bndy_bucket_24"       , EQ_TYPE    }, // 216
     { EQ::eq_ana_bndy_bucket_25          , "eq_ana_bndy_bucket_25"       , EQ_TYPE    }, // 217
-    { EQ::eq_ana_bndy_l3dcc_bucket_26    , "eq_ana_bndy_l3dcc_bucket_26" , EQ_TYPE    }, // 218
+    { EQ::eq_ana_bndy_bucket_l3dcc       , "eq_ana_bndy_bucket_l3dcc"    , EQ_TYPE    }, // 218
     { EQ::eq_ana_mode                    , "eq_ana_mode"                 , EQ_TYPE    }, // 219
     { EQ::eq_repr                        , "eq_repr"                     , EQ_TYPE    }, // 220
     { EQ::ex_l3_repr                     , "ex_l3_repr"                  , EQ_TYPE    }, // 221
@@ -1082,10 +1096,25 @@ static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] =
     { EC::ec_time                        , "ec_time"                     , EC_TYPE    }, // 226
     { EC::ec_mode                        , "ec_mode"                     , EC_TYPE    }, // 227
     { EC::ec_repr                        , "ec_repr"                     , EC_TYPE    }, // 228
-    { EQ::ex_l2_fure_1                   , "ex_l2_fure_1"                , EQ_TYPE    }, // 229
-    { EQ::ex_l3_fure_1                   , "ex_l3_fure_1"                , EQ_TYPE    }, // 230
+    { INVALID_RING                       , "invalid"                     , EQ_TYPE    }, // 229
+    { INVALID_RING                       , "invalid"                     , EQ_TYPE    }, // 230
     { EC::ec_abst                        , "ec_abst"                     , EC_TYPE    }, // 231
-
+    { EQ::eq_ana_bndy_bucket_26          , "eq_ana_bndy_bucket_26"       , EQ_TYPE    }, // 232
+    { EQ::eq_ana_bndy_bucket_27          , "eq_ana_bndy_bucket_27"       , EQ_TYPE    }, // 233
+    { EQ::eq_ana_bndy_bucket_28          , "eq_ana_bndy_bucket_28"       , EQ_TYPE    }, // 234
+    { EQ::eq_ana_bndy_bucket_29          , "eq_ana_bndy_bucket_29"       , EQ_TYPE    }, // 235
+    { EQ::eq_ana_bndy_bucket_30          , "eq_ana_bndy_bucket_30"       , EQ_TYPE    }, // 236
+    { EQ::eq_ana_bndy_bucket_31          , "eq_ana_bndy_bucket_31"       , EQ_TYPE    }, // 237
+    { EQ::eq_ana_bndy_bucket_32          , "eq_ana_bndy_bucket_32"       , EQ_TYPE    }, // 238
+    { EQ::eq_ana_bndy_bucket_33          , "eq_ana_bndy_bucket_33"       , EQ_TYPE    }, // 239
+    { EQ::eq_ana_bndy_bucket_34          , "eq_ana_bndy_bucket_34"       , EQ_TYPE    }, // 240
+    { EQ::eq_ana_bndy_bucket_35          , "eq_ana_bndy_bucket_35"       , EQ_TYPE    }, // 241
+    { EQ::eq_ana_bndy_bucket_36          , "eq_ana_bndy_bucket_36"       , EQ_TYPE    }, // 242
+    { EQ::eq_ana_bndy_bucket_37          , "eq_ana_bndy_bucket_37"       , EQ_TYPE    }, // 243
+    { EQ::eq_ana_bndy_bucket_38          , "eq_ana_bndy_bucket_38"       , EQ_TYPE    }, // 244
+    { EQ::eq_ana_bndy_bucket_39          , "eq_ana_bndy_bucket_39"       , EQ_TYPE    }, // 245
+    { EQ::eq_ana_bndy_bucket_40          , "eq_ana_bndy_bucket_40"       , EQ_TYPE    }, // 246
+    { EQ::eq_ana_bndy_bucket_41          , "eq_ana_bndy_bucket_41"       , EQ_TYPE    }, // 247
 };
 #endif
 #ifdef __PPE__
@@ -1309,7 +1338,7 @@ static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] =
     { EQ::eq_ana_bndy_bucket_23          , EQ_TYPE    }, // 215
     { EQ::eq_ana_bndy_bucket_24          , EQ_TYPE    }, // 216
     { EQ::eq_ana_bndy_bucket_25          , EQ_TYPE    }, // 217
-    { EQ::eq_ana_bndy_l3dcc_bucket_26    , EQ_TYPE    }, // 218
+    { EQ::eq_ana_bndy_bucket_l3dcc       , EQ_TYPE    }, // 218
     { EQ::eq_ana_mode                    , EQ_TYPE    }, // 219
     { EQ::eq_repr                        , EQ_TYPE    }, // 220
     { EQ::ex_l3_repr                     , EQ_TYPE    }, // 221
@@ -1320,9 +1349,25 @@ static const ringProperties_t RING_PROPERTIES[NUM_RING_IDS] =
     { EC::ec_time                        , EC_TYPE    }, // 226
     { EC::ec_mode                        , EC_TYPE    }, // 227
     { EC::ec_repr                        , EC_TYPE    }, // 228
-    { EQ::ex_l2_fure_1                   , EQ_TYPE    }, // 229
-    { EQ::ex_l3_fure_1                   , EQ_TYPE    }, // 230
+    { INVALID_RING                       , EQ_TYPE    }, // 229
+    { INVALID_RING                       , EQ_TYPE    }, // 230
     { EC::ec_abst                        , EC_TYPE    }, // 231
+    { EQ::eq_ana_bndy_bucket_26          , EQ_TYPE    }, // 232
+    { EQ::eq_ana_bndy_bucket_27          , EQ_TYPE    }, // 233
+    { EQ::eq_ana_bndy_bucket_28          , EQ_TYPE    }, // 234
+    { EQ::eq_ana_bndy_bucket_29          , EQ_TYPE    }, // 235
+    { EQ::eq_ana_bndy_bucket_30          , EQ_TYPE    }, // 236
+    { EQ::eq_ana_bndy_bucket_31          , EQ_TYPE    }, // 237
+    { EQ::eq_ana_bndy_bucket_32          , EQ_TYPE    }, // 238
+    { EQ::eq_ana_bndy_bucket_33          , EQ_TYPE    }, // 239
+    { EQ::eq_ana_bndy_bucket_34          , EQ_TYPE    }, // 240
+    { EQ::eq_ana_bndy_bucket_35          , EQ_TYPE    }, // 241
+    { EQ::eq_ana_bndy_bucket_36          , EQ_TYPE    }, // 242
+    { EQ::eq_ana_bndy_bucket_37          , EQ_TYPE    }, // 243
+    { EQ::eq_ana_bndy_bucket_38          , EQ_TYPE    }, // 244
+    { EQ::eq_ana_bndy_bucket_39          , EQ_TYPE    }, // 245
+    { EQ::eq_ana_bndy_bucket_40          , EQ_TYPE    }, // 246
+    { EQ::eq_ana_bndy_bucket_41          , EQ_TYPE    }, // 247
 };
 #endif
 
diff --git a/src/import/chips/p9/utils/imageProcs/p9_ring_id.h b/src/import/chips/p9/utils/imageProcs/p9_ring_id.h
index 1eea5f05..116f1cae 100644
--- a/src/import/chips/p9/utils/imageProcs/p9_ring_id.h
+++ b/src/import/chips/p9/utils/imageProcs/p9_ring_id.h
@@ -299,7 +299,7 @@ enum RingID
     eq_ana_bndy_bucket_23 = 215,
     eq_ana_bndy_bucket_24 = 216,
     eq_ana_bndy_bucket_25 = 217,
-    eq_ana_bndy_l3dcc_bucket_26 = 218,
+    eq_ana_bndy_bucket_l3dcc = 218,
     eq_ana_mode = 219,
 
     // Quad Chiplet Rings
@@ -320,14 +320,30 @@ enum RingID
     // EC0 - EC23 instance specific Ring
     ec_repr = 228,
 
-    // Additional rings
-    ex_l2_fure_1 = 229,
-    ex_l3_fure_1 = 230,
+    // Values 229-230 unused
 
     // Core Chiplet Rings
     // ABIST engine mode
     ec_abst = 231,
 
+    // Additional rings for Nimbus DD2
+    eq_ana_bndy_bucket_26 = 232,
+    eq_ana_bndy_bucket_27 = 233,
+    eq_ana_bndy_bucket_28 = 234,
+    eq_ana_bndy_bucket_29 = 235,
+    eq_ana_bndy_bucket_30 = 236,
+    eq_ana_bndy_bucket_31 = 237,
+    eq_ana_bndy_bucket_32 = 238,
+    eq_ana_bndy_bucket_33 = 239,
+    eq_ana_bndy_bucket_34 = 240,
+    eq_ana_bndy_bucket_35 = 241,
+    eq_ana_bndy_bucket_36 = 242,
+    eq_ana_bndy_bucket_37 = 243,
+    eq_ana_bndy_bucket_38 = 244,
+    eq_ana_bndy_bucket_39 = 245,
+    eq_ana_bndy_bucket_40 = 246,
+    eq_ana_bndy_bucket_41 = 247,
+
     //***************************
     // Rings needed for SBE - End
     //***************************
diff --git a/src/import/chips/p9/utils/p9_putRingUtils.C b/src/import/chips/p9/utils/p9_putRingUtils.C
index e4795f86..e27b5c1f 100644
--- a/src/import/chips/p9/utils/p9_putRingUtils.C
+++ b/src/import/chips/p9/utils/p9_putRingUtils.C
@@ -1123,7 +1123,9 @@ fapi2::ReturnCode rs4DecompressionSvc(
     do
     {
         //This is a special case for eq_ana_bndy bucket rings
-        if ((l_ringId >= eq_ana_bndy_bucket_0) && (l_ringId <= eq_ana_bndy_l3dcc_bucket_26))
+        if ( ( (l_ringId >= eq_ana_bndy_bucket_0) && (l_ringId <= eq_ana_bndy_bucket_25) ) ||
+             ( l_ringId == eq_ana_bndy_bucket_l3dcc ) ||
+             ( (l_ringId >= eq_ana_bndy_bucket_26) && (l_ringId <= eq_ana_bndy_bucket_41) ) )
         {
             i_applyOverride = true;
         }