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| author | spashabk-in <shakeebbk@in.ibm.com> | 2017-02-03 05:28:37 -0600 |
|---|---|---|
| committer | AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> | 2017-02-07 09:26:33 -0500 |
| commit | f949711fcc631425fe565096210c9a07ff34c3e5 (patch) | |
| tree | 8c84b7e1258d591587925a3e07030271804627ec /src/test/testcases | |
| parent | 8ba9b982a8f4357dcc4c6ff2204dee00a344c013 (diff) | |
| download | talos-sbe-f949711fcc631425fe565096210c9a07ff34c3e5.tar.gz talos-sbe-f949711fcc631425fe565096210c9a07ff34c3e5.zip | |
TraceArray HWP integration
Change-Id: I33e976bc61213994c6dbe5d2708f4ff20c6dd976
RTC:165714
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33874
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Diffstat (limited to 'src/test/testcases')
| -rw-r--r-- | src/test/testcases/testTraceArray.py | 57 |
1 files changed, 48 insertions, 9 deletions
diff --git a/src/test/testcases/testTraceArray.py b/src/test/testcases/testTraceArray.py index 02c8a9ce..84acdcf6 100644 --- a/src/test/testcases/testTraceArray.py +++ b/src/test/testcases/testTraceArray.py @@ -5,7 +5,7 @@ # # OpenPOWER sbe Project # -# Contributors Listed Below - COPYRIGHT 2016 +# Contributors Listed Below - COPYRIGHT 2016,2017 # [+] International Business Machines Corp. # # @@ -27,10 +27,14 @@ sys.path.append("targets/p9_nimbus/sbeTest" ) import testUtil err = False -CONTROL_TRACE_ARRAY_TESTDATA = [0, 0, 0, 0x04, - 0, 0, 0xA6, 0x02, - 0, 0, 0x04, 0x20, #Core chiplet - 0, 0x01, 0, 0x1D] #reset|collect|stop|ingore mux + #(Target Type, Chiplet Id, Trace bus) +TRACE_IDS = ( + (0x00, 0x00, 0x01), #Proc, xx, PROC_TB_PIB + (0x00, 0x00, 0x3C), #Proc, xx, PROC_TB_IOO + (0x00, 0x00, 0x3E), #Proc, xx, PROC_TB_MCA1 +# (0x01, 0x20, 0x4B), #EX, 0x20, PROC_TB_L20 +# (0x02, 0x20, 0x50) #PERV, 0x20(Core), PROC_TB_CORE1 + ) CONTROL_TRACE_ARRAY_VALID = [0, 0, 0, 0, #Number of Words 0xC0, 0xDE, 0xA6, 0x02, @@ -42,10 +46,45 @@ CONTROL_TRACE_ARRAY_VALID = [0, 0, 0, 0, #Number of Words def main( ): testUtil.runCycles( 10000000 ) print ("\nStarting control tracearray test") - testUtil.writeUsFifo( CONTROL_TRACE_ARRAY_TESTDATA) - testUtil.writeEot( ) - testUtil.readDsFifo( CONTROL_TRACE_ARRAY_VALID) - testUtil.readEot( ) + # Stop all the trace bus + for traceId in TRACE_IDS: + print ("Stop : "+str(traceId[2])) + CONTROL_TRACE_ARRAY_STOP_TESTDATA = [0, 0, 0, 0x04, + 0, 0, 0xA6, 0x02, + 0, traceId[0], 0, traceId[1], #TARGET_PROC_CHIP, chiplet xx + 0, traceId[2], 0, 0x14] #stop & ignore mux + testUtil.writeUsFifo( CONTROL_TRACE_ARRAY_STOP_TESTDATA) + testUtil.writeEot( ) + testUtil.readDsFifo( CONTROL_TRACE_ARRAY_VALID) + testUtil.readEot( ) + # dump traces from all the trace bus + for traceId in TRACE_IDS: + print ("Collect dump : "+str(traceId[2])) + CONTROL_TRACE_ARRAY_COLLECT_DUMP_TESTDATA = [0, 0, 0, 0x04, + 0, 0, 0xA6, 0x02, + 0, traceId[0], 0, traceId[1], #TARGET_PROC_CHIP, chiplet xx + 0, traceId[2], 0, 0x18] #PROC_TB_PIB , stop & ignore mux + testUtil.writeUsFifo(CONTROL_TRACE_ARRAY_COLLECT_DUMP_TESTDATA) + testUtil.writeEot( ) + testUtil.readDsEntry(128 * 4) # Flush tracearray buffer - 128 rows of 4words + CONTROL_TRACE_ARRAY_VALID_DUMP = [0, 0, 0x02, 0x00,#Number of Words - 0x200 - 128*4 + 0xC0, 0xDE, 0xA6, 0x2, + 0, 0, 0, 0, #Primary and secondary status + 0, 0, 0, 0x03] + testUtil.readDsFifo(CONTROL_TRACE_ARRAY_VALID_DUMP) + testUtil.readEot( ) + # Reset and restart all the trace bus + for traceId in TRACE_IDS: + print ("Reset and restart : "+str(traceId[2])) + CONTROL_TRACE_ARRAY_RESET_RESTART_TESTDATA = [0, 0, 0, 0x04, + 0, 0, 0xA6, 0x02, + 0, traceId[0], 0, traceId[1], #TARGET_PROC_CHIP, chiplet xx + 0, traceId[2], 0, 0x13] #reset, restart & ignore mux + testUtil.writeUsFifo(CONTROL_TRACE_ARRAY_RESET_RESTART_TESTDATA) + testUtil.writeEot( ) + testUtil.readDsFifo( CONTROL_TRACE_ARRAY_VALID) + testUtil.readEot( ) + #------------------------------------------------- # Calling all test code |
