ADU 1/2/4B read/write

Change-Id: I7deff3bc60639d5ed9d276d0ff962846a4da8f7b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37582
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

3 files changed, 108 insertions, 6 deletions

diff --git a/src/test/testcases/testAduMem.xml b/src/test/testcases/testAduMem.xml
index 51d2c2b2..2e38530c 100644
--- a/src/test/testcases/testAduMem.xml
+++ b/src/test/testcases/testAduMem.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER sbe Project                                                  -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2016                             -->
+<!-- Contributors Listed Below - COPYRIGHT 2016,2017                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -40,4 +40,8 @@
           <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_noEccNoItag.py</simcmd>
           <exitonerror>yes</exitonerror>
       </testcase>
+      <testcase>
+          <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_124B.py</simcmd>
+          <exitonerror>yes</exitonerror>
+      </testcase>
 
diff --git a/src/test/testcases/testAduMem_124B.py b/src/test/testcases/testAduMem_124B.py
new file mode 100644
index 00000000..100f7bb4
--- /dev/null
+++ b/src/test/testcases/testAduMem_124B.py
@@ -0,0 +1,95 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/test/testcases/testAduMem_124B.py $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2017
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+import sys
+import os
+import struct
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+import testMemUtil as testMemProcUtil
+err = False
+
+
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+    testUtil.runCycles( 10000000 )
+
+# Test case 1: 1byte access
+    #PutMemAdu Test
+    data = os.urandom(1)
+    data = [ord(c) for c in data]
+    testMemProcUtil.putmem(0x08000000, data, 0xA5)
+
+    # GetMemAdu test
+    readData = testMemProcUtil.getmem(0x08000000, 1, 0xA5)
+    if(data == readData):
+        print ("Success - Write-Read ADU")
+    else:
+        print data
+        print readData
+        raise Exception('data mistmach')
+
+# Test case 2: 2byte access
+    #PutMemAdu Test
+    data = os.urandom(2)
+    data = [ord(c) for c in data]
+    testMemProcUtil.putmem(0x08000000, data, 0xA5)
+
+    # GetMemAdu test
+    readData = testMemProcUtil.getmem(0x08000000, 2, 0xA5)
+    if(data == readData):
+        print ("Success - Write-Read ADU")
+    else:
+        print data
+        print readData
+        raise Exception('data mistmach')
+
+# Test case 3: 4byte access
+    #PutMemAdu Test
+    data = os.urandom(4)
+    data = [ord(c) for c in data]
+    testMemProcUtil.putmem(0x08000000, data, 0xA5)
+
+    # GetMemAdu test
+    readData = testMemProcUtil.getmem(0x08000000, 4, 0xA5)
+    if(data == readData):
+        print ("Success - Write-Read ADU")
+    else:
+        print data
+        print readData
+        raise Exception('data mistmach')
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+    print ("\nTest Suite completed with error(s)")
+    #sys.exit(1)
+else:
+    print ("\nTest Suite completed with no errors")
+    #sys.exit(0);
+
diff --git a/src/test/testcases/testMemUtil.py b/src/test/testcases/testMemUtil.py
index 95ed304b..30bb94bd 100644
--- a/src/test/testcases/testMemUtil.py
+++ b/src/test/testcases/testMemUtil.py
@@ -6,6 +6,7 @@
 # OpenPOWER sbe Project
 #
 # Contributors Listed Below - COPYRIGHT 2017
+# [+] International Business Machines Corp.
 #
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -56,6 +57,9 @@ def addItagEcc(arr, itag, ecc, eccVal=0):
     return arrs
 
 def putmem(addr, data, flags, ecc=0):
+    lenInBytes = len(data)
+    if(len(data) < 8):
+        data = data+[0]*(4-len(data))
     totalLen = 5 + len(data)/4
     req = (getsingleword(totalLen)
           +[ 0,0,0xA4,0x02]
@@ -63,17 +67,16 @@ def putmem(addr, data, flags, ecc=0):
           +gethalfword(flags)
           #0,0,0x0,0xA5] #CoreChipletId/EccByte/Flags -> NoEccOverride/CacheInhibit/FastMode/NoTag/NoEcc/AutoIncr/Adu/Proc
           + getdoubleword(addr)
-          + getsingleword(len(data))  # length of data
+          + getsingleword(lenInBytes)  # length of data
           + data)
     testUtil.writeUsFifo(req)
     testUtil.writeEot( )
     testUtil.runCycles( 10000000 )
-    lenWritten = len(data)
     if(flags & 0x0008):
-        lenWritten += int(len(data)/8)
+        lenInBytes += int(len(data)/8)
     if(flags & 0x0010):
-        lenWritten += int(len(data)/8)
-    expData = (getsingleword(lenWritten)
+        lenInBytes += int(len(data)/8)
+    expData = (getsingleword(lenInBytes)
                +[0xc0,0xde,0xa4,0x02,
                  0x0,0x0,0x0,0x0,
                  0x00,0x0,0x0,0x03])