Secure memory window chip-op implementation

Change-Id: I42ff79a15cba235bfd9eb761194c0699c0943332
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43415
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>

7 files changed, 240 insertions, 2 deletions

diff --git a/src/test/testcases/test.xml b/src/test/testcases/test.xml
index ccd03050..aa4ac22f 100755
--- a/src/test/testcases/test.xml
+++ b/src/test/testcases/test.xml
@@ -33,13 +33,16 @@
           <include>../simics/targets/p9_nimbus/sbeTest/testIstep.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testScom.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testGeneric.xml</include>
+          <!-- Memory access testcases -->
+          <include>../simics/targets/p9_nimbus/sbeTest/testUnsecureMemRegionsOpen.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testPutGetMem.xml</include>
+          <include>../simics/targets/p9_nimbus/sbeTest/testAduMem.xml</include>
+          <include>../simics/targets/p9_nimbus/sbeTest/testPSUSetFFDCAddr.xml</include>
+          <include>../simics/targets/p9_nimbus/sbeTest/testUnsecureMemRegionsClose.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testSram.xml</include>
           <!-- TODO add testCntlInstruction.xml -->
           <include>../simics/targets/p9_nimbus/sbeTest/testRegAccess.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testFifoReset.xml</include>
-          <include>../simics/targets/p9_nimbus/sbeTest/testAduMem.xml</include>
-          <include>../simics/targets/p9_nimbus/sbeTest/testPSUSetFFDCAddr.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testSystemFabricMap.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testExecutorCntrlTimer.xml</include>
           <include>../simics/targets/p9_nimbus/sbeTest/testArrayAccess.xml</include>
diff --git a/src/test/testcases/testMemUtil.py b/src/test/testcases/testMemUtil.py
index c6b5ab96..1014f46c 100644
--- a/src/test/testcases/testMemUtil.py
+++ b/src/test/testcases/testMemUtil.py
@@ -26,6 +26,8 @@ import sys
 import os
 import struct
 sys.path.append("targets/p9_nimbus/sbeTest" )
+import testPSUUtil
+import testRegistry as reg
 import testUtil
 err = False
 
@@ -133,3 +135,26 @@ def getmem_failure(addr, len, flags, responseWord):
     + [0x0,0x0,0x0,0x03])
     testUtil.readDsFifo(expResp)
     testUtil.readEot( )
+
+def setUnsecureMemRegion(addr, size, controlFlag, responseWord):
+    req = (["write", reg.REG_MBOX0,"0"*(8-len(hex(controlFlag).split('0x')[-1]))+hex(controlFlag).split('0x')[-1] +"00F0D601", 8, "None", "Writing to MBOX0 address"],
+           ["write", reg.REG_MBOX1, "0"*(16-len(hex(size).split('0x')[-1]))+hex(size).split('0x')[-1], 8, "None", "Writing to MBOX1 address"],
+           ["write", reg.REG_MBOX2, "0"*(16-len(hex(addr).split('0x')[-1]))+hex(addr).split('0x')[-1], 8, "None", "Writing to MBOX1 address"],
+           ["write", reg.PSU_SBE_DOORBELL_REG_WO_OR, "8000000000000000", 8, "None", "Update SBE Doorbell register to interrupt SBE"])
+
+    host_polling_data = (
+                            ["read", reg.PSU_HOST_DOORBELL_REG_WO_OR, "0", 8, "8000000000000000", "Reading Host Doorbell for Interrupt"],
+                        )
+
+    # Host to SBE req
+    regObj = testPSUUtil.registry()
+    regObj.ExecuteTestOp(testPSUUtil.simSbeObj, req)
+    print "\n  Poll on Host side for INTR  ...\n"
+    #Poll on HOST DoorBell Register for interrupt
+    regObj.pollingOn( testPSUUtil.simSbeObj, host_polling_data, 5)
+
+    response = (
+                    ["read", reg.REG_MBOX4, "0", 8, "0"*(8-len(hex(responseWord).split('0x')[-1]))+hex(responseWord).split('0x')[-1]+"00F0D601", "Reading Host MBOX4 data to Validate"],
+                )
+    #SBE->HOST data set execution
+    regObj.ExecuteTestOp( testPSUUtil.simSbeObj, response)
diff --git a/src/test/testcases/testUnsecureMemRegions.py b/src/test/testcases/testUnsecureMemRegions.py
new file mode 100644
index 00000000..129b80c4
--- /dev/null
+++ b/src/test/testcases/testUnsecureMemRegions.py
@@ -0,0 +1,38 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/test/testcases/testUnsecureMemRegions.py $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2017
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+import sys
+import os
+import struct
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+import testMemUtil as testMemProcUtil
+err = False
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main():
+    testUtil.runCycles( 10000000 )
+
+    # Test case 1: open RO mem region - success
+    testMemProcUtil.setUnsecureMemRegion(0x08000000, 1024, 0x0000)
diff --git a/src/test/testcases/testUnsecureMemRegionsClose.py b/src/test/testcases/testUnsecureMemRegionsClose.py
new file mode 100644
index 00000000..3d7b04b4
--- /dev/null
+++ b/src/test/testcases/testUnsecureMemRegionsClose.py
@@ -0,0 +1,53 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/test/testcases/testUnsecureMemRegionsClose.py $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2017
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+import sys
+import os
+import struct
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+import testMemUtil as testMemProcUtil
+err = False
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main():
+    testUtil.runCycles( 10000000 )
+
+    # Test case 1: close RW mem region - success
+    # This region is kept closed after mem testcases - it is opened by
+    # testUnsecureMemRegionsOpen.py
+    testMemProcUtil.setUnsecureMemRegion(0x08000000, 1024, 0x0120, 0)
+    print ("Success - setUnsecureMemRegion - close RW")
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+    print ("\nTest Suite completed with error(s)")
+    #sys.exit(1)
+else:
+    print ("\nTest Suite completed with no errors")
+    #sys.exit(0);
diff --git a/src/test/testcases/testUnsecureMemRegionsClose.xml b/src/test/testcases/testUnsecureMemRegionsClose.xml
new file mode 100644
index 00000000..925b108e
--- /dev/null
+++ b/src/test/testcases/testUnsecureMemRegionsClose.xml
@@ -0,0 +1,30 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/test/testcases/testUnsecureMemRegionsClose.xml $          -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2016,2017                        -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<?xml version="1.0" encoding="UTF-8"?>
+
+      <testcase>
+          <simcmd>run-python-file targets/p9_nimbus/sbeTest/testUnsecureMemRegionsClose.py</simcmd>
+          <exitonerror>yes</exitonerror>
+      </testcase>
+
diff --git a/src/test/testcases/testUnsecureMemRegionsOpen.py b/src/test/testcases/testUnsecureMemRegionsOpen.py
new file mode 100644
index 00000000..2f5dddde
--- /dev/null
+++ b/src/test/testcases/testUnsecureMemRegionsOpen.py
@@ -0,0 +1,59 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/test/testcases/testUnsecureMemRegionsOpen.py $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2017
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+import sys
+import os
+import struct
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+import testMemUtil as testMemProcUtil
+err = False
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main():
+    testUtil.runCycles( 10000000 )
+
+    # Test case 1: open RO mem region - success
+    testMemProcUtil.setUnsecureMemRegion(0x07000000, 1024, 0x0111, 0)
+    print ("Success - setUnsecureMemRegion - open RO")
+    # Test case 2: close RW mem region - success
+    # This region is kept open for mem testcases - will be closed by
+    # testUnsecureMemRegionsClose.py
+    testMemProcUtil.setUnsecureMemRegion(0x08000000, 1024, 0x0112, 0)
+    print ("Success - setUnsecureMemRegion - open RW")
+    # Test case 3: close RO mem region - success
+    testMemProcUtil.setUnsecureMemRegion(0x07000000, 1024, 0x0120, 0)
+    print ("Success - setUnsecureMemRegion - close RO")
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+    print ("\nTest Suite completed with error(s)")
+    #sys.exit(1)
+else:
+    print ("\nTest Suite completed with no errors")
+    #sys.exit(0);
diff --git a/src/test/testcases/testUnsecureMemRegionsOpen.xml b/src/test/testcases/testUnsecureMemRegionsOpen.xml
new file mode 100644
index 00000000..010f4779
--- /dev/null
+++ b/src/test/testcases/testUnsecureMemRegionsOpen.xml
@@ -0,0 +1,30 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/test/testcases/testUnsecureMemRegionsOpen.xml $           -->
+<!--                                                                        -->
+<!-- OpenPOWER sbe Project                                                  -->
+<!--                                                                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2016,2017                        -->
+<!--                                                                        -->
+<!--                                                                        -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
+<!-- you may not use this file except in compliance with the License.       -->
+<!-- You may obtain a copy of the License at                                -->
+<!--                                                                        -->
+<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
+<!--                                                                        -->
+<!-- Unless required by applicable law or agreed to in writing, software    -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
+<!-- implied. See the License for the specific language governing           -->
+<!-- permissions and limitations under the License.                         -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<?xml version="1.0" encoding="UTF-8"?>
+
+      <testcase>
+          <simcmd>run-python-file targets/p9_nimbus/sbeTest/testUnsecureMemRegionsOpen.py</simcmd>
+          <exitonerror>yes</exitonerror>
+      </testcase>
+