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| author | Raja Das <rajadas2@in.ibm.com> | 2017-11-15 01:21:16 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-11-17 06:59:44 -0500 |
| commit | 7f96036fea81c49aacab46d577ccf585bbf8daf8 (patch) | |
| tree | 5ce97bee69ffaf0e14a583b767ac69f05b06a036 /src/test/testcases/testQuiesce.xml | |
| parent | 3d41a2c1dc5009a8f7ad96c4b45b7e4f0b3d008d (diff) | |
| download | talos-sbe-7f96036fea81c49aacab46d577ccf585bbf8daf8.tar.gz talos-sbe-7f96036fea81c49aacab46d577ccf585bbf8daf8.zip | |
Updated Backing build in customrc to move to latest Simics DD2
- Updated Backing build
- Updated Capabilities
- updated EC_20 mode in test case
- test cases updated
Change-Id: I1a8311952c54e9ca8062ab227930571fb0f11a4d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49702
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/test/testcases/testQuiesce.xml')
| -rw-r--r-- | src/test/testcases/testQuiesce.xml | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/src/test/testcases/testQuiesce.xml b/src/test/testcases/testQuiesce.xml index 8b502949..9619b7ae 100644 --- a/src/test/testcases/testQuiesce.xml +++ b/src/test/testcases/testQuiesce.xml @@ -5,7 +5,8 @@ <!-- --> <!-- OpenPOWER sbe Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> +<!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> <!-- Licensed under the Apache License, Version 2.0 (the "License"); --> @@ -38,8 +39,14 @@ <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutGetScom.py</simcmd> <exitonerror>yes</exitonerror> </testcase> + <!-- Taking out this test-case since this requires clock now, and we have + already done stop clock before quiesce. Somehow there is dependency + of clock with ADU, this used to work in DD1. + We can't move stopclock testcase below this since stop clock is from + seeprom region and quiesce prohibits seeprom access. + Disabling ADU access after quiesce operation. --> <!-- An Adu put chip-op should succeed post the Quiesce --> - <testcase> + <!--<testcase> <simcmd>run-python-file targets/p9_nimbus/sbeTest/testAduMem_noEccNoItag.py</simcmd> <exitonerror>yes</exitonerror> - </testcase> + </testcase> --> |
