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authorRaja Das <rajadas2@in.ibm.com>2019-02-05 21:21:33 -0600
committerRAJA DAS <rajadas2@in.ibm.com>2019-04-10 03:27:45 -0500
commit4bd48045fe9aa99f55d328a860dbc39ca8fa2815 (patch)
tree91d92b74d741168457ed22ebfcb7ed7edeaaad2a /src/test/framework
parent249671d79a098be1068df41754a258483aa17614 (diff)
downloadtalos-sbe-4bd48045fe9aa99f55d328a860dbc39ca8fa2815.tar.gz
talos-sbe-4bd48045fe9aa99f55d328a860dbc39ca8fa2815.zip
Update Backing build to customrc and update standalone simics patch
Change-Id: I8ca9aef300a3ef5808db84e28ea80d1dd524e794 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71415 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: MURULIDHAR NATARAJU <murulidhar@in.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Diffstat (limited to 'src/test/framework')
-rw-r--r--src/test/framework/etc/patches/standalone.simics.patch32
1 files changed, 19 insertions, 13 deletions
diff --git a/src/test/framework/etc/patches/standalone.simics.patch b/src/test/framework/etc/patches/standalone.simics.patch
index ccd5be17..da9c0e51 100644
--- a/src/test/framework/etc/patches/standalone.simics.patch
+++ b/src/test/framework/etc/patches/standalone.simics.patch
@@ -1,13 +1,19 @@
-70c70,77
-< ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "00000000_00000000" 64
----
-> # Set the Fsp bit in MBOX3 reg (bit 3), This is to make SBE pick default HRMOR
-> # i.e. 128MB instead of FspLess HRMOR address. Action files in simics are
-> # hardcoded to support 128MB presently. we need to update Simic Action file to
-> # be flexible and pick HRMOR basis this Fsp bit.
-> # TODO - RTC 196986
-> ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "90000000_00000000" 64
-> # Set security enabled bit
-> ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x00050001 "0C000002_00000000" 64
-74a82
-> ($hb_masterproc).proc_chip.invoke parallel_store FSIMBOX 0x08 "00080000" 32
+--- standalone.simics 2019-02-05 02:31:38.785109846 -0600
++++ standalone_930.simics 2019-02-05 02:30:55.445109859 -0600
+@@ -108,7 +108,15 @@
+ # Set mailbox scratch registers so that the SBE starts in plck mode
+ # Set Boot Freq valid bit (bit 3) and valid data bit (bit 7)
+ ($hb_masterproc_cecchip).invoke parallel_store SCOM 0x5003F "31000000_00000000" 64
+- ($hb_masterproc_cecchip).invoke parallel_store SCOM 0x5003A "00000000_00000000" 64
++
++ # Set the Fsp bit in MBOX3 reg (bit 3), This is to make SBE pick default HRMOR
++ # i.e. 128MB instead of FspLess HRMOR address. Action files in simics are
++ # hardcoded to support 128MB presently. we need to update Simic Action file to
++ # be flexible and pick HRMOR basis this Fsp bit.
++ # TODO - RTC 196986
++ ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "90000000_00000000" 64
++ # Set security enabled bit
++ ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x00050001 "0C000002_00000000" 64
+
+ # Set the Nest PLL Bucket ID to 5 in the 4th byte of Mbox Scratch Reg 4
+ ($hb_masterproc_cecchip).invoke parallel_store SCOM 0x5003B "00000005_00000000" 64
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