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authorShakeeb <shakeebbk@in.ibm.com>2016-08-31 15:15:19 -0500
committerAMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>2016-09-01 07:07:29 -0400
commit1008ef70a71fcfdec398ff30923d5025991c85f4 (patch)
treeb22fc2a7cf2c8414ca20dfc7489a7f6d1a145878 /src/test/framework/etc
parent28cb5c42ddba0cb9d2a86f43785c60499170ef2f (diff)
downloadtalos-sbe-1008ef70a71fcfdec398ff30923d5025991c85f4.tar.gz
talos-sbe-1008ef70a71fcfdec398ff30923d5025991c85f4.zip
SBE code restructure: cleanup
Change-Id: I354cc79ba25b843fdb1a7524a19b8d0c41bd9051 RTC:159709 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29060 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Diffstat (limited to 'src/test/framework/etc')
-rw-r--r--src/test/framework/etc/patches/chip.act.patch146
-rw-r--r--src/test/framework/etc/patches/patchlist.txt14
-rw-r--r--src/test/framework/etc/patches/pervasive.act.patch28
-rw-r--r--src/test/framework/etc/patches/powermgmt.act.patch1057
-rw-r--r--src/test/framework/etc/patches/standalone.simics.patch4
-rwxr-xr-xsrc/test/framework/etc/workarounds.postsimsetup44
-rwxr-xr-xsrc/test/framework/etc/workarounds.presimsetup31
7 files changed, 1324 insertions, 0 deletions
diff --git a/src/test/framework/etc/patches/chip.act.patch b/src/test/framework/etc/patches/chip.act.patch
new file mode 100644
index 00000000..0b9cf0f0
--- /dev/null
+++ b/src/test/framework/etc/patches/chip.act.patch
@@ -0,0 +1,146 @@
+184,240c184
+< # ==========================================================================
+< # Actions for p9_adu_access and p9_adu_setup procedures
+< # ==========================================================================
+< #If a read/write is done to the ALTD_DATA Register set the ALTD_STATUS Register so things are as expected
+< CAUSE_EFFECT{
+< LABEL=[ADU Read or write to set ALTD_STATUS Register]
+< #If the data register is read
+< WATCH_READ=[REG(0x00090004)]
+< #If the data register is written
+< WATCH=[REG(0x00090004)]
+<
+< #Set the ALTD_STATUS Register so these bits are set:
+< #FBC_ALTD_BUSY = WAIT_CMD_ARBIT = WAIT_RESP = OVERRUN_ERR = AUTOINC_ERR = COMMAND_ERR = ADDRESS_ERR = COMMAND_HANG_ERR = DATA_HANG_ERR = PBINIT_MISSING = ECC_CE = ECC_UE = ECC_SUE = 0
+< EFFECT: TARGET=[REG(0x00090003)] OP=[BUF,AND] DATA=[LITERAL(64,001FDFFF FFFF1FFF)]
+< EFFECT: TARGET=[REG(0x00090003)] OP=[BUF,OR] DATA=[LITERAL(64,30000000 00000000)]
+< }
+<
+< #If a read/write is done to the ALTD_DATA Register and the Address only bit is not set then set the DATA_DONE bit to 1
+< CAUSE_EFFECT{
+< LABEL=[ADU Read or write to set ALTD_STATUS[DATA_DONE] bit]
+< #If the data register is read
+< WATCH_READ=[REG(0x00090004)]
+< #If the data register is written
+< WATCH=[REG(0x00090004)]
+< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6]
+<
+< #Set the DATA_DONE bit
+< EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3]
+< }
+<
+< #If a read/write is done to the ALTD_DATA Register and the Data only bit is not set then set the ADDR_DONE bit to 1
+< CAUSE_EFFECT{
+< LABEL=[ADU Read or write to set ALTD_STATUS[ADDR_DONE] bit]
+< #If the data register is read
+< WATCH_READ=[REG(0x00090004)]
+< #If the data register is written
+< WATCH=[REG(0x00090004)]
+< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7]
+<
+< #Set the ADDR_DONE bit
+< EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2]
+< }
+<
+< #If a read is done to the ALTD_CMD Register and it sets the lock set the ALTD_STATUS Register so the ALTD_STATUS_BUSY bit is set
+< CAUSE_EFFECT{
+< LABEL=[ADU Write to set ALTD_STATUS_BUSY]
+< WATCH=[REG(0x00090001)]
+< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[11]
+<
+< #Set the ALTD_STATUS Register so the ALTD_STATUS_BUSY bit is set
+< EFFECT: TARGET=[REG(0x090003)] OP=[BIT,ON] BIT=[0]
+< }
+< #If a write is done to the ALD_CMD_REG to set the FBC_ALTD_START_OP bit it should turn FBC_ALTD_BUSY off
+< CAUSE_EFFECT{
+< LABEL=[ADU Write to ALTD_CMD_REG to unset set ALTD_STATUS FBC_ALTD_BUSY bit]
+< WATCH=[REG(0x00090001)]
+< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2]
+---
+> ### ADU ACTIONS - READ WRITE RESET ###
+242,243c186,265
+< #Unset the ALTD_STATUS Register so the ALTD_STATUS_BUSY is unset
+< EFFECT: TARGET=[REG(0x090003)] OP=[BIT,OFF] BIT=[0]
+---
+> # Reset ALTD Status Reg
+> CAUSE_EFFECT {
+> LABEL=[RESET FSM ALTD Status Register]
+> WATCH=[REG(0x00090001)] # ALTD_Cmd_Reg
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[4] #Reset FSM bit
+> EFFECT: TARGET=[REG(0x00090003)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)]
+> }
+>
+> # ADU Transaction Complete Status - Busy Bit Low
+> CAUSE_EFFECT {
+> LABEL=[ALTD_BUSY Status Register Clear]
+> WATCH=[REG(0x00090003)] # ALTD_Status_Reg
+> CAUSE: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE
+> CAUSE: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[19] #AUTO INCR Mode OFF
+>
+> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,OFF] BIT=[0] #BUSY Bit low
+> }
+>
+> # Read without AutoIncr
+> CAUSE_EFFECT{
+> LABEL=[READ Mainstore without AutoIncr]
+> WATCH=[REG(0x00090001)] # ALTD_Cmd_Reg
+>
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[5] #READ ADU Operation
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data
+>
+> EFFECT: TARGET=[MODULE(readMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # read the memory
+> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE
+> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE
+> }
+>
+> # Read with AutoIncr
+> CAUSE_EFFECT{
+> LABEL=[READ Mainstore with AutoIncr]
+> WATCH_READ=[REG(0x00090004)] # ALTD_Data_reg
+>
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[5] #READ ADU Operation
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[19] #AutoInc bit on
+>
+> EFFECT: TARGET=[MODULE(readMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # read the memory
+> EFFECT: TARGET=[REG(0x00090000)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64,00000000 0000FFFF)] # incr addr reg by 8
+> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE
+> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE
+> }
+>
+> # Write without AutoIncr
+> CAUSE_EFFECT{
+> LABEL=[WRITE Mainstore without AutoIncr]
+> WATCH=[REG(0x00090001)] # ALTD_Cmd_Reg
+> WATCH=[REG(0x00090004)] # ALTD_Data_reg
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[5] #WRITE ADU Operation
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[19] #AutoInc bit off
+> EFFECT: TARGET=[MODULE(writeMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # write the memory
+> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE
+> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE
+> }
+>
+> # Write with AutoIncr
+> CAUSE_EFFECT{
+> LABEL=[WRITE Mainstore with AutoIncr]
+> WATCH=[REG(0x00090001)] # ALTD_Cmd_reg
+> WATCH=[REG(0x00090004)] # ALTD_Data_reg
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[5] #WRITE ADU Operation
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data
+> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[19] #AutoInc bit on
+> EFFECT: TARGET=[MODULE(writeMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # write the memory
+> EFFECT: TARGET=[REG(0x00090000)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64, 00000000 0000FFFF)] # incr addr reg by 8
+> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE
+> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE
+265a288
+> EFFECT: TARGET=[MODULE(executeInstruction, MYCORE)] OP=[MODULECALL] DATA=[REG(MYCHIPLET, 0x00010A4F)]
diff --git a/src/test/framework/etc/patches/patchlist.txt b/src/test/framework/etc/patches/patchlist.txt
new file mode 100644
index 00000000..4fd0444a
--- /dev/null
+++ b/src/test/framework/etc/patches/patchlist.txt
@@ -0,0 +1,14 @@
+# Example Format
+#Brief description of the problem or reason for patch
+#-RTC: Task/Story used to remove this patch
+#-CQ: Defect/Req for checking the changes into fips910
+#-Files: list of files
+#-Coreq: list of associated changes, e.g. workarounds.presimsetup
+
+RTC: 144728
+Files : pervasive.act.patch. Currently SUET does not support FSIMBOX KW. Once
+ support is in, remove this patch.
+
+RTC: 128984
+Files: chip.act.patch. Added call for executeInstruction module call.
+ p9.inst.patch. Added P9 specific commands for ramming.
diff --git a/src/test/framework/etc/patches/pervasive.act.patch b/src/test/framework/etc/patches/pervasive.act.patch
new file mode 100644
index 00000000..5531bef6
--- /dev/null
+++ b/src/test/framework/etc/patches/pervasive.act.patch
@@ -0,0 +1,28 @@
+55c55
+< WATCH=[REG(0x00050018)]
+---
+> WATCH=[FSIMBOX(0x18)]
+57c57
+< CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[12]
+---
+> CAUSE: TARGET=[FSIMBOX(0x18)] OP=[BIT,OFF] BIT=[12]
+59c59
+< CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[0]
+---
+> CAUSE: TARGET=[FSIMBOX(0x18)] OP=[BIT,OFF] BIT=[0]
+67c67
+< WATCH=[REG(0x00050018)]
+---
+> WATCH=[FSIMBOX(0x18)]
+69c69
+< CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[4]
+---
+> CAUSE: TARGET=[FSIMBOX(0x18)] OP=[BIT,OFF] BIT=[4]
+78c78
+< WATCH=[REG(0x00050018)]
+---
+> WATCH=[FSIMBOX(0x18)]
+80c80
+< CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[4]
+---
+> CAUSE: TARGET=[FSIMBOX(0x18)] OP=[BIT,OFF] BIT=[4]
diff --git a/src/test/framework/etc/patches/powermgmt.act.patch b/src/test/framework/etc/patches/powermgmt.act.patch
new file mode 100644
index 00000000..efb03845
--- /dev/null
+++ b/src/test/framework/etc/patches/powermgmt.act.patch
@@ -0,0 +1,1057 @@
+43,112d42
+< ## Actions for Procedure - p9_pm_occ_control
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[PPC405 HALT]
+< WATCH=[REG(0x0006D006)]
+< CAUSE: TARGET=[REG(0x0006D006)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 02000000 00000000)]
+< #suet PPC405_UNHALT:tc1- EFFECT: TARGET=[REG(0x01010800)] OP=[BIT,OFF] BIT=[31]
+< EFFECT: TARGET=[REG(0x01010800)] OP=[BIT,ON] BIT=[31]
+< }
+<
+< ##
+< ## Actions for Procedure - p9_pm_occ_gpe_init
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[OCC GPE0 HALT]
+< WATCH=[REG(0x00060010)]
+< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[1]
+< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[2]
+< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,ON] BIT=[3]
+< #suet OCCGPE0_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,OFF] BIT=[0]
+< EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[OCC GPE1 HALT]
+< WATCH=[REG(0x00062010)]
+< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[1]
+< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[2]
+< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,ON] BIT=[3]
+< #suet OCCGPE1_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,OFF] BIT=[0]
+< EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Upon writing the PU_OCB_PIB_OCR[DBG_HALT} bit, set the OCCLFIR_PPC405_DBGSTOPACK_BIT.
+< CAUSE_EFFECT {
+< LABEL=[PPC405 SAFE_HALT]
+< WATCH=[REG(00x0006D002)]
+< CAUSE: TARGET=[REG(0x0006D002)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00200000 00000000)]
+< EFFECT: TARGET=[REG(0x01010800)] OP=[BIT,ON] BIT=[31]
+< }
+<
+<
+< ##
+< ## Actions for Procedure - p9_pm_occ_gpe_init
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[OCC GPE0 HALT]
+< WATCH=[REG(0x00060010)]
+< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[1]
+< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[2]
+< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,ON] BIT=[3]
+< #suet OCCGPE0_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,OFF] BIT=[0]
+< EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[OCC GPE1 HALT]
+< WATCH=[REG(0x00062010)]
+< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[1]
+< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[2]
+< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,ON] BIT=[3]
+< #suet OCCGPE1_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,OFF] BIT=[0]
+< EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,ON] BIT=[0]
+< }
+<
+<
+< ##
+134,409c64
+<
+< ## Core0 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x200F0110)]
+< CAUSE: TARGET=[REG(0x200F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)]
+< EFFECT: TARGET=[REG(0x200F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x200F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x200F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x200F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core0 End
+<
+< ## Core1 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x210F0110)]
+< CAUSE: TARGET=[REG(0x210F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x210F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x210F0110)]
+< EFFECT: TARGET=[REG(0x210F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x210F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x210F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x210F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core1 End
+<
+< ## Core2 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x220F0110)]
+< CAUSE: TARGET=[REG(0x220F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x220F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)]
+< EFFECT: TARGET=[REG(0x220F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x220F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x220F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x220F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core2 End
+<
+< ## Core3 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x230F0110)]
+< CAUSE: TARGET=[REG(0x230F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x230F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x230F0110)]
+< EFFECT: TARGET=[REG(0x230F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x230F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x230F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x230F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core3 End
+<
+< ## Core4 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x240F0110)]
+< CAUSE: TARGET=[REG(0x240F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x240F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x240F0110)]
+< EFFECT: TARGET=[REG(0x240F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x240F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x240F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x240F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core4 End
+<
+< ## Core5 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x250F0110)]
+< CAUSE: TARGET=[REG(0x250F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x250F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x250F0110)]
+< EFFECT: TARGET=[REG(0x250F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x250F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x250F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x250F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core5 End
+<
+< ## Core6 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x260F0110)]
+< CAUSE: TARGET=[REG(0x260F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x260F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)]
+< EFFECT: TARGET=[REG(0x260F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x260F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x260F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x260F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core6 End
+<
+< ## Core7 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x270F0110)]
+< CAUSE: TARGET=[REG(0x270F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x270F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x270F0110)]
+< EFFECT: TARGET=[REG(0x270F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x270F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x270F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x270F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core7 End
+<
+< ## Core8 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x280F0110)]
+< CAUSE: TARGET=[REG(0x280F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x280F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x280F0110)]
+< EFFECT: TARGET=[REG(0x280F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x280F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x280F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x200F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core8 End
+<
+< ## Core9 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x290F0110)]
+< CAUSE: TARGET=[REG(0x290F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x290F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x290F0110)]
+< EFFECT: TARGET=[REG(0x290F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x290F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x290F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x290F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core9 End
+<
+< ## Core10 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x2A0F0110)]
+< CAUSE: TARGET=[REG(0x2A0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2A0F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2A0F0110)]
+< EFFECT: TARGET=[REG(0x2A0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2A0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2A0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2A0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core10 End
+<
+< ## Core11 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x2B0F0110)]
+< CAUSE: TARGET=[REG(0x2B0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2B0F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2B0F0110)]
+< EFFECT: TARGET=[REG(0x2B0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2B0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2B0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2B0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core11 End
+<
+< ## Core12 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x2C0F0110)]
+< CAUSE: TARGET=[REG(0x2C0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2C0F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2C0F0110)]
+< EFFECT: TARGET=[REG(0x2C0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2C0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2C0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2C0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core12 End
+<
+< ## Core13 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x2D0F0110)]
+< CAUSE: TARGET=[REG(0x2D0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2D0F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2D0F0110)]
+< EFFECT: TARGET=[REG(0x2D0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2D0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2D0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2D0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core13 End
+<
+< ## Core14 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x2E0F0110)]
+< CAUSE: TARGET=[REG(0x2E0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2E0F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2E0F0110)]
+< EFFECT: TARGET=[REG(0x2E0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2E0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2E0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2E0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core14 End
+<
+< ## Core15 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x2F0F0110)]
+< CAUSE: TARGET=[REG(0x2F0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2F0F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2F0F0110)]
+< EFFECT: TARGET=[REG(0x2F0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2F0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2F0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x2F0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core15 End
+<
+< ## Core16 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x300F0110)]
+< CAUSE: TARGET=[REG(0x300F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x300F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x300F0110)]
+< EFFECT: TARGET=[REG(0x300F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x300F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x300F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x300F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core16 End
+<
+< ## Core17 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x310F0110)]
+< CAUSE: TARGET=[REG(0x310F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x310F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x310F0110)]
+< EFFECT: TARGET=[REG(0x310F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x310F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x310F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x310F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core17 End
+<
+< ## Core18 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x320F0110)]
+< CAUSE: TARGET=[REG(0x320F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x320F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x320F0110)]
+< EFFECT: TARGET=[REG(0x320F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x320F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x320F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x320F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core18 End
+<
+< ## Core19 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x330F0110)]
+< CAUSE: TARGET=[REG(0x330F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x330F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x330F0110)]
+< EFFECT: TARGET=[REG(0x330F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x330F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x330F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x330F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core19 End
+<
+< ## Core20 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x340F0110)]
+< CAUSE: TARGET=[REG(0x340F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x340F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x340F0110)]
+< EFFECT: TARGET=[REG(0x340F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x340F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x340F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x340F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core20 End
+<
+< ## Core21 Start
+< CAUSE_EFFECT {
+---
+> CAUSE_EFFECT CHIPLETS ec {
+411,478c66,89
+< WATCH=[REG(0x350F0110)]
+< CAUSE: TARGET=[REG(0x350F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x350F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x350F0110)]
+< EFFECT: TARGET=[REG(0x350F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x350F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x350F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x350F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core21 End
+<
+< ## Core22 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x360F0110)]
+< CAUSE: TARGET=[REG(0x360F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x360F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x360F0110)]
+< EFFECT: TARGET=[REG(0x360F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x360F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x360F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x360F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core22 End
+<
+< ## Core23 Start
+< CAUSE_EFFECT {
+< LABEL=[SSH_SRC_WRITE]
+< WATCH=[REG(0x370F0110)]
+< CAUSE: TARGET=[REG(0x370F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x370F0110)]
+< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x370F0110)]
+< EFFECT: TARGET=[REG(0x370F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x370F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x370F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< EFFECT: TARGET=[REG(0x370F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+< }
+< ## Core23 End
+<
+< ##
+< # Actions for Procedure - p9_block_wakeup_intr
+< ##
+<
+< # Core Power Management Mode Register
+< CAUSE_EFFECT {
+< LABEL=[CPMMR Write OR of PPM Write Override]
+< WATCH=[REG(0x290F0108)]
+< CAUSE: TARGET=[REG(0x290F0108)] OP=[BIT,ON] BIT=[1]
+< EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,ON] BIT=[1]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[CPMMR Write CLEAR of PPM Write Override]
+< WATCH=[REG(0x290F0107)]
+< CAUSE: TARGET=[REG(0x290F0107)] OP=[BIT,ON] BIT=[1]
+< EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,OFF] BIT=[1]
+< }
+<
+< # General Power Management Mode Register
+< CAUSE_EFFECT {
+< LABEL=[GPMMR Write OR of Block Wakeup Events]
+< WATCH=[REG(0x290F0102)]
+< CAUSE: TARGET=[REG(0x290F0102)] OP=[BIT,ON] BIT=[6]
+< EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[6]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[GPMMR Write CLEAR of PPM Write Override]
+< WATCH=[REG(0x290F0101)]
+< CAUSE: TARGET=[REG(0x290F0101)] OP=[BIT,ON] BIT=[6]
+< EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[6]
+---
+> WATCH=[REG(MYCHIPLET, 0x0F0110)]
+> CAUSE: TARGET=[REG(MYCHIPLET, 0x0F0110)] OP=[EQUALTO,BUF] DATA=[REG(MYCHIPLET, 0x0F0110)]
+> EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(MYCHIPLET, 0x0F0110)]
+> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)]
+> }
+>
+> ## Action triggered when all threads are idle
+> # Used for istep 16 to have hostboot properly wake up on SBE-set PSU
+> # interrupt as well as to have p9_sbe_check_master_stop15.C properly
+> # execute in firmware simics.
+> # TODO: RTC 147787
+> CAUSE_EFFECT CHIPLETS ec {
+> LABEL=[Master Winkle LPCR]
+> WATCH=[IDLESTATE(MYCHIPLET,0x0)]
+> # look for stop15
+> CAUSE: TARGET=[IDLESTATE(MYCHIPLET,0x0)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,0F000000)] MASK=[LITERAL(32,FF000000)]
+> # Restore LPCR for wake-up options.
+> EFFECT: TARGET=[PROCREG(lpcr, MYCORE, 0)] OP=[BIT,ON] BIT=[17]
+> EFFECT: TARGET=[PROCREG(lpcr, MYCORE, 0)] OP=[BIT,ON] BIT=[49]
+> # Set required C_PPM_SSHOTR register required by procedure
+> EFFECT: TARGET=[REG(0x200F0113)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,8BB00000 FFFFFFFF)]
+514c125
+< ## Actions for p9_pm_ocb_init
+---
+> # Actions for Procedure - p9_hcd_core_poweron / p9_hcd_cache_poweron
+517,524c128,133
+< CAUSE_EFFECT {
+< LABEL=[Channel 0 linear stream]
+< WATCH=[REG(0x0006D013)]
+< WATCH=[REG(0x0006D012)]
+< CAUSE: TARGET=[REG(0x0006D013)] OP=[BIT,ON] BIT=[4]
+< CAUSE: TARGET=[REG(0x0006D012)] OP=[BIT,ON] BIT=[5]
+< EFFECT: TARGET=[REG(0x0006D011)] OP=[BIT,ON] BIT=[4]
+< EFFECT: TARGET=[REG(0x0006D011)] OP=[BIT,OFF] BIT=[5]
+---
+> CAUSE_EFFECT CHIPLETS ec cache {
+> LABEL=[Power on core/cache vdd pfet then fsm is idle and sense is enabled]
+> WATCH=[REG(MYCHIPLET, 0x0F011A)]
+> CAUSE: TARGET=[REG(MYCHIPLET, 0x0F011A)] OP=[BIT,ON] BIT=[0]
+> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0118)] OP=[BIT,ON] BIT=[42]
+> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F011C)] OP=[BIT,ON] BIT=[0]
+527,1071c136
+< CAUSE_EFFECT {
+< LABEL=[Channel 1 linear stream]
+< WATCH=[REG(0x0006D033)]
+< WATCH=[REG(0x0006D032)]
+< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4]
+< CAUSE: TARGET=[REG(0x0006D032)] OP=[BIT,ON] BIT=[5]
+< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4]
+< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,OFF] BIT=[5]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[Channel 1 circular push interupt enable]
+< WATCH=[REG(0x0006D033)]
+< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[3]
+< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4]
+< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[5]
+< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[3]
+< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4]
+< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[5]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[Channel 1 circular push interrupt disable]
+< WATCH=[REG(0x0006D033)]
+< WATCH=[REG(0x0006D032)]
+< CAUSE: TARGET=[REG(0x0006D032)] OP=[BIT,ON] BIT=[3]
+< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4]
+< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[5]
+< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,OFF] BIT=[3]
+< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4]
+< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[5]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[Channel 2 linear stream]
+< WATCH=[REG(0x0006D053)]
+< WATCH=[REG(0x0006D052)]
+< CAUSE: TARGET=[REG(0x0006D053)] OP=[BIT,ON] BIT=[4]
+< CAUSE: TARGET=[REG(0x0006D052)] OP=[BIT,ON] BIT=[5]
+< EFFECT: TARGET=[REG(0x0006D051)] OP=[BIT,ON] BIT=[4]
+< EFFECT: TARGET=[REG(0x0006D051)] OP=[BIT,OFF] BIT=[5]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[Channel 3 linear stream]
+< WATCH=[REG(0x0006D073)]
+< WATCH=[REG(0x0006D072)]
+< CAUSE: TARGET=[REG(0x0006D073)] OP=[BIT,ON] BIT=[4]
+< CAUSE: TARGET=[REG(0x0006D072)] OP=[BIT,ON] BIT=[5]
+< EFFECT: TARGET=[REG(0x0006D071)] OP=[BIT,ON] BIT=[4]
+< EFFECT: TARGET=[REG(0x0006D071)] OP=[BIT,OFF] BIT=[5]
+< ## Actions for Procedure - p9_setup_evid
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[AVSBus Write data register 0B]
+< WATCH=[REG(0x0006C718)]
+< CAUSE: TARGET=[REG(0x0006C718)] OP=[BIT,ON] BIT=[1]
+< EFFECT: TARGET=[REG(0x0006C716)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[AVSBus Status register 0B]
+< WATCH_READ=[REG(0x0006C716)]
+< CAUSE: TARGET=[REG(0x0006C716)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x0006C716)] OP=[BIT,OFF] BIT=[0]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[AVSBus Write data register 1B]
+< WATCH=[REG(0x0006C738)]
+< CAUSE: TARGET=[REG(0x0006C738)] OP=[BIT,ON] BIT=[1]
+< EFFECT: TARGET=[REG(0x0006C736)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[AVSBus Status register 1B]
+< WATCH_READ=[REG(0x0006C736)]
+< CAUSE: TARGET=[REG(0x0006C736)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x0006C736)] OP=[BIT,OFF] BIT=[0]
+< }
+<
+< ## Core 0 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x200F011A)]
+< CAUSE: TARGET=[REG(0x200F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x200F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x200F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 0 End
+< ## Core 1 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x210F011A)]
+< CAUSE: TARGET=[REG(0x210F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x210F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x210F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 1 End
+< ## Core 2 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x220F011A)]
+< CAUSE: TARGET=[REG(0x220F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x220F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x220F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 2 End
+< ## Core 3 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x230F011A)]
+< CAUSE: TARGET=[REG(0x230F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x230F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x230F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 3 End
+< ## Core 4 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x240F011A)]
+< CAUSE: TARGET=[REG(0x240F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x240F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x240F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 4 End
+< ## Core 5 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x250F011A)]
+< CAUSE: TARGET=[REG(0x250F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x250F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x250F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 5 End
+< ## Core 6 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x260F011A)]
+< CAUSE: TARGET=[REG(0x260F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x260F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x260F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 6 End
+< ## Core 7 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x270F011A)]
+< CAUSE: TARGET=[REG(0x270F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x270F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x270F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 7 End
+< ## Core 8 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x280F011A)]
+< CAUSE: TARGET=[REG(0x280F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x280F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x280F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 8 End
+< ## Core 9 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x290F011A)]
+< CAUSE: TARGET=[REG(0x290F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x290F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x290F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 9 End
+< ## Core 10 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x2a0F011A)]
+< CAUSE: TARGET=[REG(0x2a0F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x2a0F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x2a0F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 10 End
+< ## Core 11 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x2b0F011A)]
+< CAUSE: TARGET=[REG(0x2b0F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x2b0F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x2b0F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 11 End
+< ## Core 12 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x2c0F011A)]
+< CAUSE: TARGET=[REG(0x2c0F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x2c0F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x2c0F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 12 End
+< ## Core 13 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x2d0F011A)]
+< CAUSE: TARGET=[REG(0x2d0F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x2d0F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x2d0F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 13 End
+< ## Core 14 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x2e0F011A)]
+< CAUSE: TARGET=[REG(0x2e0F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x2e0F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x2e0F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 14 End
+< ## Core 15 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x2f0F011A)]
+< CAUSE: TARGET=[REG(0x2f0F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x2f0F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x2f0F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 15 End
+< ## Core 16 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x300F011A)]
+< CAUSE: TARGET=[REG(0x300F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x300F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x300F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 16 End
+< ## Core 17 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x310F011A)]
+< CAUSE: TARGET=[REG(0x310F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x310F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x310F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 17 End
+< ## Core 18 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x320F011A)]
+< CAUSE: TARGET=[REG(0x320F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x320F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x320F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 18 End
+< ## Core 19 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x330F011A)]
+< CAUSE: TARGET=[REG(0x330F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x330F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x330F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 19 End
+< ## Core 20 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x340F011A)]
+< CAUSE: TARGET=[REG(0x340F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x340F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x340F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 20 End
+< ## Core 21 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x350F011A)]
+< CAUSE: TARGET=[REG(0x350F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x350F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x350F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 21 End
+< ## Core 22 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x360F011A)]
+< CAUSE: TARGET=[REG(0x360F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x360F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x360F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 22 End
+< ## Core 23 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_core_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x370F011A)]
+< CAUSE: TARGET=[REG(0x370F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x370F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x370F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< # Core 23 End
+< ## EQ 0 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_cache_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x100F011A)]
+< CAUSE: TARGET=[REG(0x100F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x100F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x100F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x100F011A)]
+< CAUSE: TARGET=[REG(0x100F011A)] OP=[BIT,ON] BIT=[2]
+< EFFECT: TARGET=[REG(0x100F0118)] OP=[BIT,ON] BIT=[50]
+< EFFECT: TARGET=[REG(0x100F011C)] OP=[BIT,ON] BIT=[2]
+< }
+<
+< ## EQ 0 End
+<
+< ## EQ 1 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_cache_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x110F011A)]
+< CAUSE: TARGET=[REG(0x110F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x110F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x110F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x110F011A)]
+< CAUSE: TARGET=[REG(0x110F011A)] OP=[BIT,ON] BIT=[2]
+< EFFECT: TARGET=[REG(0x110F0118)] OP=[BIT,ON] BIT=[50]
+< EFFECT: TARGET=[REG(0x110F011C)] OP=[BIT,ON] BIT=[2]
+< }
+<
+< ## EQ 1 End
+<
+< ## EQ 2 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_cache_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x120F011A)]
+< CAUSE: TARGET=[REG(0x120F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x120F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x120F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x120F011A)]
+< CAUSE: TARGET=[REG(0x120F011A)] OP=[BIT,ON] BIT=[2]
+< EFFECT: TARGET=[REG(0x120F0118)] OP=[BIT,ON] BIT=[50]
+< EFFECT: TARGET=[REG(0x120F011C)] OP=[BIT,ON] BIT=[2]
+< }
+<
+< ## EQ 2 End
+<
+< ## EQ 3 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_cache_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x130F011A)]
+< CAUSE: TARGET=[REG(0x130F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x130F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x130F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x130F011A)]
+< CAUSE: TARGET=[REG(0x130F011A)] OP=[BIT,ON] BIT=[2]
+< EFFECT: TARGET=[REG(0x130F0118)] OP=[BIT,ON] BIT=[50]
+< EFFECT: TARGET=[REG(0x130F011C)] OP=[BIT,ON] BIT=[2]
+< }
+<
+< ## EQ 3 End
+<
+< ## EQ 4 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_cache_poweron
+< ##
+<
+< CAUSE_EFFECT {
+---
+> CAUSE_EFFECT CHIPLETS cache {
+1073,1084c138,141
+< WATCH=[REG(0x140F011A)]
+< CAUSE: TARGET=[REG(0x140F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x140F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x140F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x140F011A)]
+< CAUSE: TARGET=[REG(0x140F011A)] OP=[BIT,ON] BIT=[2]
+< EFFECT: TARGET=[REG(0x140F0118)] OP=[BIT,ON] BIT=[50]
+< EFFECT: TARGET=[REG(0x140F011C)] OP=[BIT,ON] BIT=[2]
+---
+> WATCH=[REG(MYCHIPLET, 0x0F011A)]
+> CAUSE: TARGET=[REG(MYCHIPLET, 0x0F011A)] OP=[BIT,ON] BIT=[2]
+> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0118)] OP=[BIT,ON] BIT=[50]
+> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F011C)] OP=[BIT,ON] BIT=[2]
+1087,1112d143
+< ## EQ 4 End
+<
+< ## EQ 5 Start
+<
+< ##
+< # Actions for Procedure - p9_hcd_cache_poweron
+< ##
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x150F011A)]
+< CAUSE: TARGET=[REG(0x150F011A)] OP=[BIT,ON] BIT=[0]
+< EFFECT: TARGET=[REG(0x150F0118)] OP=[BIT,ON] BIT=[42]
+< EFFECT: TARGET=[REG(0x150F011C)] OP=[BIT,ON] BIT=[0]
+< }
+<
+< CAUSE_EFFECT {
+< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled]
+< WATCH=[REG(0x150F011A)]
+< CAUSE: TARGET=[REG(0x150F011A)] OP=[BIT,ON] BIT=[2]
+< EFFECT: TARGET=[REG(0x150F0118)] OP=[BIT,ON] BIT=[50]
+< EFFECT: TARGET=[REG(0x150F011C)] OP=[BIT,ON] BIT=[2]
+< }
+<
+< ## EQ 5 End
+<
diff --git a/src/test/framework/etc/patches/standalone.simics.patch b/src/test/framework/etc/patches/standalone.simics.patch
new file mode 100644
index 00000000..bdc40fd8
--- /dev/null
+++ b/src/test/framework/etc/patches/standalone.simics.patch
@@ -0,0 +1,4 @@
+52c52
+< ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "00000000_00000000" 64
+---
+> ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "80000000_00000000" 64
diff --git a/src/test/framework/etc/workarounds.postsimsetup b/src/test/framework/etc/workarounds.postsimsetup
new file mode 100755
index 00000000..ac7f3a29
--- /dev/null
+++ b/src/test/framework/etc/workarounds.postsimsetup
@@ -0,0 +1,44 @@
+#!/bin/sh
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/test/framework/etc/workarounds.postsimsetup $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+## Workarounds that are run after start_simics is executed for the first time
+## to setup the sandbox
+##
+
+### Example applying a patch to cec-chip files
+#echo "+++ Updating something wonderful in a simics file"
+#mkdir -p $sb/simu/data/cec-chip/
+#cp $BACKING_BUILD/src/simu/data/cec-chip/base_cec_chip_file $sb/simu/data/cec-chip
+#patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $SBEROOT/src/build/citest/etc/patches/my_patch_File
+
+# NOTE: The below patch removes mailbox settings in standalone.simics (comes
+# from HB) that cause the SBE to run in plck mode. For our CI, we need the SBE
+# to be in istep mode. This patch is likely never going to be removed as long as
+# we need our CI to run in istep mode.
+echo "+++ Patching standalone.simics"
+mkdir -p $SANDBOXBASE/obj/ppc/simu/scripts/hbfw
+cp $BACKING_BUILD/obj/ppc/simu/scripts/hbfw/standalone.simics $SANDBOXBASE/obj/ppc/simu/scripts/hbfw
+patch -p0 $SANDBOXBASE/obj/ppc/simu/scripts/hbfw/standalone.simics $SBEROOT/src/test/framework/etc/patches/standalone.simics.patch
+
diff --git a/src/test/framework/etc/workarounds.presimsetup b/src/test/framework/etc/workarounds.presimsetup
new file mode 100755
index 00000000..e863b07d
--- /dev/null
+++ b/src/test/framework/etc/workarounds.presimsetup
@@ -0,0 +1,31 @@
+#!/bin/sh
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/test/framework/etc/workarounds.presimsetup $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+#### Examples ####
+#echo "+++ Some message about why you need to do this."
+#mkdir -p $sb/simu/data
+#egrep -v "WSALIAS DEFAULT FIPSLEVEL|WSALIAS DEFAULT SIMICSLEVEL" $BACKING_BUILD/src/simu/data/simicsInfo > $sb/simu/data/simicsInfo
+#echo "WSALIAS DEFAULT FIPSLEVEL env/gfwb/simics-4.2.0/simics-4.2.83/fips/fld36/fi120201a700.42" >> $sb/simu/data/simicsInfo
+#echo "WSALIAS DEFAULT SIMICSLEVEL env/vtechb/simics-4.2.0/simics-4.2.83/bin" >> $sb/simu/data/simicsInfo
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