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| author | Dean Sanner <dsanner@us.ibm.com> | 2017-09-15 15:01:13 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-09-19 12:58:08 -0400 |
| commit | ff713dfd14ecf97b050a737cc5da2d6f01db493f (patch) | |
| tree | 3c15e0f074faf2191ea84aac1ac37cd044bfa175 /src/sbefw | |
| parent | 4466b70680ac82799375b58739a10881d4394fc3 (diff) | |
| download | talos-sbe-ff713dfd14ecf97b050a737cc5da2d6f01db493f.tar.gz talos-sbe-ff713dfd14ecf97b050a737cc5da2d6f01db493f.zip | |
Prime PSSCR reg on thread 1 so istep 16 works in SMT1
- PSSCR reg comes up to invalid default. Normally STOP
cycle sets to valid value, but for the master core
(prior to istep 16) it is done via SBE. Thread 2/3
already had this set, but missed thread 1 for SMT1
mode
Change-Id: I8358dfa3db863291d72e860c0c0475541af93bf4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46293
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46300
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Diffstat (limited to 'src/sbefw')
0 files changed, 0 insertions, 0 deletions
