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| author | Joe McGill <jmcgill@us.ibm.com> | 2017-01-23 09:52:15 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-02-08 23:15:37 -0500 |
| commit | bf9b6cd49dd4a9d84f41ad37000eb66070f21458 (patch) | |
| tree | 93d47d9daf795922624bafa6edbcfb641c15a044 /src/import | |
| parent | 2018552133496efcd81422082a410258da2c5c6d (diff) | |
| download | talos-sbe-bf9b6cd49dd4a9d84f41ad37000eb66070f21458.tar.gz talos-sbe-bf9b6cd49dd4a9d84f41ad37000eb66070f21458.zip | |
p9_sbe_startclock_chiplets -- leave flushmode_inhibit asserted for PCIE
workaround HW400154 for IOP plat staging bug
will not be fixed in P9
Change-Id: I891581d37b418eff616ceb0c6ff6b90618d6a6d6
CQ: HW400154
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35234
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35370
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C index 05ebb7c5..934dc234 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C @@ -81,7 +81,6 @@ fapi2::ReturnCode p9_sbe_startclock_chiplets(const fapi2::TARGET_FILTER_XBUS | fapi2::TARGET_FILTER_ALL_PCI), fapi2::TARGET_STATE_FUNCTIONAL); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OBUS_RATIO_VALUE, i_target_chip, l_attr_obus_ratio)); @@ -137,8 +136,12 @@ fapi2::ReturnCode p9_sbe_startclock_chiplets(const FAPI_TRY(p9_sbe_startclock_chiplets_fence_drop(targ)); } - FAPI_DBG("call sbe_common_flushmode for xbus, obus, pcie chiplets"); - FAPI_TRY(p9_sbe_common_flushmode(targ)); + // skip dropping flushmode inhbit if PCIE chiplet + if (!(l_chipletID >= 13) && (l_chipletID <= 15)) + { + FAPI_DBG("call sbe_common_flushmode for xbus, obus chiplets"); + FAPI_TRY(p9_sbe_common_flushmode(targ)); + } } FAPI_INF("p9_sbe_startclock_chiplets: Exiting ..."); |
