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| author | Thi Tran <thi@us.ibm.com> | 2016-09-13 10:20:24 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-09-19 23:54:38 -0400 |
| commit | ac9fc4c453f9c76bd878ccbb6430bbef76a4d140 (patch) | |
| tree | 424f9e1ce16e257bc04a6a2e10f55694e68074ea /src/import | |
| parent | 733bed36b738677619e8586f9c3fe4f9212ea063 (diff) | |
| download | talos-sbe-ac9fc4c453f9c76bd878ccbb6430bbef76a4d140.tar.gz talos-sbe-ac9fc4c453f9c76bd878ccbb6430bbef76a4d140.zip | |
Setup ATTR_OBUS_RATIO_VALUE for SBE platform
Change-Id: Ib9db247cf20b084a0106dd7b65819060ea1fc2ca
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29568
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29578
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C | 12 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml | 10 |
2 files changed, 20 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C index b6c8217d..8fc95de1 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C @@ -41,6 +41,12 @@ #include <p9_perv_scom_addresses.H> +enum P9_SETUP_SBE_CONFIG_scratch4 +{ + // Scratch4 reg bit definitions + ATTR_OBUS_RATIO_VALUE_BIT = 21, +}; + fapi2::ReturnCode p9_sbe_attr_setup(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) { @@ -152,6 +158,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const uint8_t l_io_filter_bypass = 0; uint8_t l_dpll_bypass = 0; uint8_t l_nest_mem_x_o_pci_bypass = 0; + uint8_t l_attr_obus_ratio = 0; FAPI_DBG("Reading Scratch_Reg4"); //Getting SCRATCH_REGISTER_4 register value @@ -164,6 +171,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const l_read_scratch_reg.extractToRight<18, 1>(l_io_filter_bypass); l_read_scratch_reg.extractToRight<19, 1>(l_dpll_bypass); l_read_scratch_reg.extractToRight<20, 1>(l_nest_mem_x_o_pci_bypass); + l_read_scratch_reg.extractToRight<ATTR_OBUS_RATIO_VALUE_BIT, 1>(l_attr_obus_ratio); l_read_scratch_reg.extractToRight<24, 8>(l_read_1); FAPI_DBG("Setting up PLL bypass attributes"); @@ -172,11 +180,13 @@ fapi2::ReturnCode p9_sbe_attr_setup(const FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_IO_FILTER_BYPASS, i_target_chip, l_io_filter_bypass)); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DPLL_BYPASS, i_target_chip, l_dpll_bypass)); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_nest_mem_x_o_pci_bypass)); - FAPI_DBG("Setting up ATTR_BOOT_FREQ_MULT, ATTR_NEST_PLL_BUCKET"); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_BOOT_FREQ_MULT, i_target_chip, l_read_4)); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1)); + FAPI_DBG("Setting up ATTR_OBUS_RATIO_VALUE"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_OBUS_RATIO_VALUE, i_target_chip, l_attr_obus_ratio)); + l_read_1 = 0; l_read_4 = 0; } diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index 9c12e076..d632baa3 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -595,11 +595,19 @@ <initToZero/> </attribute> +<!-- TODO: Story 155081 + Not supposed to be writeable, PPE needs to resolve this issue in + p9_sbe_attr_setup.C --> <attribute> <id>ATTR_OBUS_RATIO_VALUE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>Holds Obus ratio value</description> + <description>Holds Obus ratio value + 0b00 Normal speed. + 0b01 Half speed. + </description> <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> <writeable/> </attribute> |
