diff options
| author | Joe McGill <jmcgill@us.ibm.com> | 2016-09-20 17:56:28 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-09-22 10:21:15 -0400 |
| commit | a62943076325f9d966b62518f363d178257577cb (patch) | |
| tree | b37861abf9c66c0aacfb7d281e87b757f008dff7 /src/import | |
| parent | 7bc92647d1c160eab3987c387d7fff53047ffab9 (diff) | |
| download | talos-sbe-a62943076325f9d966b62518f363d178257577cb.tar.gz talos-sbe-a62943076325f9d966b62518f363d178257577cb.zip | |
move C_PPM_SSHSRC setup from p9_hcd_core_scominit to p9_hcd_core_startclocks
Change-Id: Ibfc344ce1b12f1c12a62bd23269f52dbec8d4380
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29999
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Peng Fei Gou <shgoupf@cn.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30000
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C | 3 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C | 6 |
2 files changed, 6 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C index bcd99682..29f4a2ab 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_scominit.C @@ -75,9 +75,6 @@ p9_hcd_core_scominit( FAPI_TRY(getScom(i_target, C_THERM_MODE_REG, l_data64)); FAPI_TRY(putScom(i_target, C_THERM_MODE_REG, DATA_SET(5))); - FAPI_DBG("Set core as ready to run in STOP history register"); - FAPI_TRY(putScom(i_target, C_PPM_SSHSRC, 0)); - // invoke core SCOM initfile FAPI_EXEC_HWP(l_rc, p9_core_scom, i_target); diff --git a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C index 1ae58a8a..d24c0837 100644 --- a/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C @@ -268,6 +268,12 @@ p9_hcd_core_startclocks( BIT64(8 + (l_attr_chip_unit_pos % 2))))); } + if (!l_attr_runn_mode) + { + FAPI_DBG("Set core as ready to run in STOP history register"); + FAPI_TRY(putScom(i_target, C_PPM_SSHSRC, 0)); + } + fapi_try_exit: FAPI_INF("<<p9_hcd_core_startclocks"); |
