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| author | Yue Du <daviddu@us.ibm.com> | 2017-09-25 12:36:13 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-09-27 22:37:31 -0400 |
| commit | 9a3a1f18a6deaa9c24092f4e44e133221ed3af2f (patch) | |
| tree | 0f6c6d8f50c0613c82566d2ad55f4660c6392a79 /src/import | |
| parent | 48231314b8273ecc2d0f5bb336ebee2299a5efe6 (diff) | |
| download | talos-sbe-9a3a1f18a6deaa9c24092f4e44e133221ed3af2f.tar.gz talos-sbe-9a3a1f18a6deaa9c24092f4e44e133221ed3af2f.zip | |
STOP: Fix MPIPL Dpll Lock via ensuring mode 1
Change-Id: Ie1ee6c9fc46575006b163846a8e4c1d1086b99c6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46686
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46688
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C index 0a23dbdb..4b24e3d9 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C @@ -113,10 +113,18 @@ p9_hcd_cache_dpll_setup( FAPI_DBG("Drop analog logic fence via QPPM_PFCS[11]"); FAPI_TRY(putScom(i_target, EQ_PPM_PFCS_WCLEAR, MASK_SET(11))); - FAPI_DBG("Assert DPLL in mode 1,set slew rate via QPPM_DPLL_CTRL[2,6-15]"); + FAPI_DBG("Assert DPLL in mode 1,set slew rate via QPPM_DPLL_CTRL[1,2,16,6-15,22-23]"); l_data64.flush<0>().setBit<2>().insertFromRight<6, 10>(0x01); FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_OR, l_data64)); + // make sure mode1 by clearing + // 1) enable_jump_protect + // 16)ss_enable + // 22)enable_fmin_target + // 23)enable_fmax_target + l_data64.flush<0>().setBit<1>().setBit<16>().setBit<22>().setBit<23>(); + FAPI_TRY(putScom(i_target, EQ_QPPM_DPLL_CTRL_CLEAR, l_data64)); + FAPI_DBG("Drop flushmode_inhibit via CPLT_CTRL0[2]"); FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL0_CLEAR, MASK_SET(2))); |
