support customization of Nimbus DD1 PCI reference clock speed

  rename existing EC feature attribute, now serves as DD1N enable qualifying
  application of MRW-sourced ATTR_DD1_SLOW_PCI_REF_CLOCK:
    0 = NORMAL = 100 MHz
    1 = SLOW = 94 MHz

  MRW attribute is plumbed through SBE mailbox (scratch 5 bit 5, value
  inverted) and added to XIP customize

CMVC-Prereq:1020384
Change-Id: I376f06d0d49ab3d39c965e3131d484cbe9535566
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38129
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38134
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

2 files changed, 38 insertions, 0 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
index 41941df0..8ea0bb77 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C
@@ -79,6 +79,7 @@ enum P9_SETUP_SBE_CONFIG_scratch4
     ATTR_RISK_LEVEL_BIT                = 2,
     ATTR_DISABLE_HBBL_VECTORS_BIT      = 3,
     ATTR_MC_SYNC_MODE_BIT              = 4,
+    ATTR_SLOW_PCI_REF_CLOCK_BIT        = 5,
 
     // Scratch_reg_6
     ATTR_PUMP_CHIP_IS_GROUP            = 23,
@@ -352,6 +353,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
         uint8_t l_disable_hbbl_vectors = 0;
         uint32_t l_pll_mux = 0;
         uint8_t l_mc_sync_mode = 0;
+        uint8_t l_slow_pci_ref_clock = 0;
 
         if ( l_read_scratch8.getBit<4>() )
         {
@@ -390,6 +392,16 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             }
 
             l_read_scratch_reg.extract<4, 1, 7>(l_mc_sync_mode);
+
+            if (l_read_scratch_reg.getBit<ATTR_SLOW_PCI_REF_CLOCK_BIT>())
+            {
+                l_slow_pci_ref_clock = fapi2::ENUM_ATTR_DD1_SLOW_PCI_REF_CLOCK_NORMAL;
+            }
+            else
+            {
+                l_slow_pci_ref_clock = fapi2::ENUM_ATTR_DD1_SLOW_PCI_REF_CLOCK_SLOW;
+            }
+
             l_read_scratch_reg.extract<12, 20, 0>(l_pll_mux);
 
             FAPI_DBG("Setting up SYSTEM_IPL_PHASE, RISK_LEVEL, SYS_FORCE_ALL_CORES");
@@ -398,6 +410,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_risk_level));
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, l_disable_hbbl_vectors));
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_mc_sync_mode));
+            FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DD1_SLOW_PCI_REF_CLOCK, FAPI_SYSTEM, l_slow_pci_ref_clock));
             FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CLOCK_PLL_MUX, i_target_chip, l_pll_mux));
         }
         else
@@ -410,6 +423,7 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
             FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_risk_level));
             FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, l_disable_hbbl_vectors));
             FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_mc_sync_mode));
+            FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DD1_SLOW_PCI_REF_CLOCK, FAPI_SYSTEM, l_slow_pci_ref_clock));
 
             // set cache contained flag
             if (l_system_ipl_phase == fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED)
@@ -461,6 +475,16 @@ fapi2::ReturnCode p9_sbe_attr_setup(const
                 l_read_scratch_reg.clearBit<ATTR_MC_SYNC_MODE_BIT>();
             }
 
+            // set slow PCI ref clock bit
+            if (l_slow_pci_ref_clock == fapi2::ENUM_ATTR_DD1_SLOW_PCI_REF_CLOCK_SLOW)
+            {
+                l_read_scratch_reg.clearBit<ATTR_SLOW_PCI_REF_CLOCK_BIT>();
+            }
+            else
+            {
+                l_read_scratch_reg.setBit<ATTR_SLOW_PCI_REF_CLOCK_BIT>();
+            }
+
             FAPI_DBG("Reading PLL mux attributes");
             FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CLOCK_PLL_MUX, i_target_chip, l_pll_mux));
             // set PLL MUX bits
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
index 39286a8d..02850609 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
@@ -891,6 +891,20 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_pcie(
                            l_use_ss_pll),
              "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK_ENABLE)");
 
+    if (l_use_ss_pll)
+    {
+        fapi2::ATTR_DD1_SLOW_PCI_REF_CLOCK_Type l_slow_ref_clock;
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_DD1_SLOW_PCI_REF_CLOCK,
+                               fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+                               l_slow_ref_clock),
+                 "Error from FAPI_ATTR_GET (ATTR_DD1_SLOW_PCI_REF_CLOCK)");
+
+        if (l_slow_ref_clock != fapi2::ENUM_ATTR_DD1_SLOW_PCI_REF_CLOCK_SLOW)
+        {
+            l_use_ss_pll = 0;
+        }
+    }
+
     if ( l_attr_unit_pos != 0x0E )
     {
         //Setting NET_CTRL1 register value