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| author | Anusha Reddy Rangareddygari <anusrang@in.ibm.com> | 2017-02-14 12:19:37 +0100 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-02-24 07:30:09 -0500 |
| commit | 68ea5bfbb4df69b1db558d1af76ead67ad18e4c1 (patch) | |
| tree | f25349af3e24ee78384ce91bedce98e4ea2c7b3e /src/import | |
| parent | 1444b4766dc16f863a87e83190a3e057c2cb532e (diff) | |
| download | talos-sbe-68ea5bfbb4df69b1db558d1af76ead67ad18e4c1.tar.gz talos-sbe-68ea5bfbb4df69b1db558d1af76ead67ad18e4c1.zip | |
SBE hreset update
Change-Id: Ifb4f009b441718ee70e348cb89a4bb4be5846bc3
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36418
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36419
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C | 10 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C | 11 |
2 files changed, 11 insertions, 10 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C index 47f2c2e5..709719ca 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -76,6 +76,11 @@ fapi2::ReturnCode p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting( l_data64.insertFromRight< 0, 16 >(l_mb_bit_rate_divisor); FAPI_TRY(fapi2::putScom(i_target_chip, PU_MODE_REGISTER_B, l_data64)); + FAPI_DBG("Writing I2C bit rate divisor into mailbox_reg_2"); + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM, l_data64)); + l_data64.insertFromRight< 0, 16 >(l_mb_bit_rate_divisor); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM, l_data64)); + FAPI_DBG("Exiting ..."); fapi_try_exit: @@ -104,8 +109,7 @@ fapi2::ReturnCode p9_sbe_gear_switcher_i2c_stop_sequence( // enable enhance mode // Point to port_0 where the Primary SEEPROM Sits FAPI_INF("Send a STOP sequence on I2C"); - //Setting CONTROL_REGISTER_B register value - FAPI_TRY(fapi2::getScom(i_target_chip, PU_CONTROL_REGISTER_B, l_data64)); + l_data64.flush<0>(); l_data64.setBit<3>(); //PIB.CONTROL_REGISTER_B.PIB_CNTR_REG_BIT_WITHSTOP_0 = 1 //PIB.CONTROL_REGISTER_B.PIB_CNTR_REG_PORT_NUMBER_0 = l_read_attr l_data64.insertFromRight<18, 5>(l_read_attr); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C index 646695fb..357b612c 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_switch_gears.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -64,22 +64,19 @@ fapi2::ReturnCode p9_sbe_tp_switch_gears(const uint8_t l_nest_bypass = 0; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_nest_bypass)); -#ifdef __PPE__ - // - if we've just switched from refclock->PLL, we need to adjust the // i2c bit rate divisor to account for the new frequency (plus // check our ability to access the seeprom with this setting) - // - if no frequency change has occurred (nest PLL in bypass), - // skip all of these steps as the current divisor in place is appropriate + // - if no frequency change has occurred (nest PLL in bypass) if (l_nest_bypass == 0) { FAPI_TRY(p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting(i_target_chip)); FAPI_TRY(p9_sbe_gear_switcher_i2c_stop_sequence(i_target_chip)); +#ifdef __PPE__ FAPI_DBG("Checking Magic number"); FAPI_TRY(p9_sbe_tp_switch_gears_check_magicnumber(i_target_chip)); - } - #endif + } if (l_nest_bypass == 0) { |
