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| author | Raja Das <rajadas2@in.ibm.com> | 2019-08-28 11:01:16 -0500 |
|---|---|---|
| committer | RAJA DAS <rajadas2@in.ibm.com> | 2019-09-30 06:36:03 -0500 |
| commit | 1d411055fab2b31195b43ee56122afd15445380e (patch) | |
| tree | bc2db98c51ba634498bb59f01fb78f5347c4b583 /src/import | |
| parent | b05b7eb24e29eff4a767a7e0d4883a16a989a55b (diff) | |
| download | talos-sbe-1d411055fab2b31195b43ee56122afd15445380e.tar.gz talos-sbe-1d411055fab2b31195b43ee56122afd15445380e.zip | |
Optimized the Control Instruction Chip-op
- Simics doesn't handle core2 onwards properly for control
Instruction. It fails with invalid clock state for core2 onwards.
CecChip::isValidClocksState Invalid clocks state
[0x00000000 0x00000001] to SCOM 0x22010a9c
(clockBits [0xe0000000 0x00000001])
- Need to comeback on this to see why simics doesn't complain about
core0/1.
Change-Id: Id6480b041e4e1ddb29e448ce1653e0995887db2e
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82990
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Diffstat (limited to 'src/import')
0 files changed, 0 insertions, 0 deletions
