SGPE and CME scanning integration

- Enable FAPI2 targets (move to .C)
- Add/enhance hcode_image_build and wrapper tracing for debug
- Fix CME boot to match the layout of CPMR with common scanning
- Add internal target creation to initf for testing
- Update p9_hcode_image_defines with realistic sizes.
- Cleaned up some wrappers for better debug and tracing
- Cleaned up some extraneous defines
- Fixed vector constructor functionality.
    - Removed -gc-sections from stop_gpe.mk so that constructor code remained
    - Fixed hcode_image_build in its adding of scan rings to not overlay the
      Hcode data region.
- Fix quad based creation of local target
- Redid boot_loader to properly deal with scan ring sections
- Fix boot copier header dependency
- Moved SGPE Hcode space to 38KB to deal with present size;  Made SGPE total
  OCC SRAM allocation 80KB for now.  This growth is due to fapi2 required
  vector support (4 x 128KB) plus target init (1KB) plus scan ring allocation
  per latest assumptions. The FAPI2 elements will be readdressed later.
- Remove skip arrayinit/scan0 from istep15_hack and into EPM_TUNING
- Some bug fixes in hcode_image_defines to get proper common ring offsets
  in SGPE header as well as proper placement of common rings in image
- Changes from Prasad with putrings updates
- Removed break points to call broadside scans in CME and SGPE codes.
- Added Prasad's changes for putring for CME and SGPE.
- Increased thread stack size
- Rebased and commented out memory faulting code for now
- Removed call in p9_pm_stop_gpe_init to ppe_state due to HB strings (for now)
- Fix SGPE_ALLOCATED_SIZE
- Boot loader fix
- Pulled in PK PBA context bug fix as this corrupts the PBASLVCTL0 and thus
  memory accesses
- Make CPMR and CME Header values have maximums. Add check to not allow overrun
- Hcode Image Wrapper update
- CME header debug output

Change-Id: I71718485ff3192f3723fdfa03b8bc6f558ef120e
RTC: 136960
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27421
Reviewed-by: AMIT KUMAR <akumar3@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Dev-Ready: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30724
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S
index 9b776d3e..6f3e2358 100644
--- a/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S
+++ b/src/import/chips/p9/procedures/ppe/pk/ppe42/ppe42_exceptions.S
@@ -385,7 +385,7 @@ ctx_continue_push:
         ## Save the context of the PBASLVCTL reg
         _liw    %r7,  PBA_SLVCTLN(PBASLVCTLN)
         lvd     %d7, 0(%r7)
-        stvd    %d7, PK_CTX_PBASLVCTLV(%r4)
+        stvd    %d7, PK_CTX_PBASLVCTLV(%r1)
 #endif