Create dmi.pll.scan.initfile

Support sync and async mode for Cumulus MC

Default buckets are 1.

Change-Id: I62d0221abf7f93030cb8c0200a456609ab4dfe04
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40326
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Benjamin Gass <bgass@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41056
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

7 files changed, 126 insertions, 8 deletions

diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
index 3c981a3f..38c69756 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
@@ -329,6 +329,7 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
     // configure chiplet pervasive FIRs / XFIRs
     {
         uint8_t l_mc_sync_mode = 0;
+        uint8_t l_use_dmi_buckets = 0;
         fapi2::TargetFilter l_target_filter = static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_TP |
                                               fapi2::TARGET_FILTER_ALL_NEST |
                                               fapi2::TARGET_FILTER_XBUS |
@@ -338,7 +339,10 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target, l_mc_sync_mode),
                  "Error from FAPI_ATTR_GET (ATTR_MC_SYNC_MODE)");
 
-        if (l_mc_sync_mode)
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_DMI_MC_PLL_SCAN_BUCKETS, i_target, l_use_dmi_buckets),
+                 "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_DMI_MC_PLL_SCAN_BUCKETS)");
+
+        if (l_mc_sync_mode || l_use_dmi_buckets)
         {
             l_target_filter = static_cast<fapi2::TargetFilter>(l_target_filter | fapi2::TARGET_FILTER_ALL_MC);
         }
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C
index c1eb02ac..a9a04587 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_initf.C
@@ -42,14 +42,23 @@
 #include <p9_ring_id.h>
 #include "p9_frequency_buckets.H"
 
+static const uint8_t P9_DEFAULT_NEST_PLL_BUCKET = 1;
+static const uint8_t P9_DEFAULT_MC_PLL_BUCKET = 1;
+
+
 fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const
         fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
     FAPI_INF("p9_sbe_chiplet_pll_initf: Entering ...");
+    const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
     uint8_t l_ob0_pll_bucket = 0;
     uint8_t l_ob1_pll_bucket = 0;
     uint8_t l_ob2_pll_bucket = 0;
     uint8_t l_ob3_pll_bucket = 0;
+    uint8_t l_nest_pll_bucket = 0;
+    uint8_t l_mc_pll_bucket = 0;
+    uint8_t l_sync_mode = 0;
+    uint8_t l_set_mc_bucket = 0;
 
     // determine obus pll buckets
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB0_PLL_BUCKET, i_target_chip, l_ob0_pll_bucket),
@@ -61,6 +70,33 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OB3_PLL_BUCKET, i_target_chip, l_ob3_pll_bucket),
              "Error from FAPI_ATTR_GET (ATTR_OB3_PLL_BUCKET)");
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM , l_nest_pll_bucket ),
+             "Error from FAPI_ATTR_GET (ATTR_NEST_PLL_BUCKET)");
+
+    if (l_nest_pll_bucket == 0)
+    {
+        l_nest_pll_bucket = P9_DEFAULT_NEST_PLL_BUCKET;
+    }
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_PLL_BUCKET, FAPI_SYSTEM , l_mc_pll_bucket ),
+             "Error from FAPI_ATTR_GET (ATTR_MC_PLL_BUCKET)");
+
+    if (l_mc_pll_bucket == 0)
+    {
+        l_mc_pll_bucket = P9_DEFAULT_MC_PLL_BUCKET;
+    }
+
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_sync_mode));
+
+    if (l_sync_mode)
+    {
+        l_set_mc_bucket = l_nest_pll_bucket;
+    }
+    else
+    {
+        l_set_mc_bucket = l_mc_pll_bucket;
+    }
+
     FAPI_ASSERT((l_ob0_pll_bucket && (l_ob0_pll_bucket <= OBUS_PLL_FREQ_BUCKETS)) &&
                 (l_ob1_pll_bucket && (l_ob1_pll_bucket <= OBUS_PLL_FREQ_BUCKETS)) &&
                 (l_ob2_pll_bucket && (l_ob2_pll_bucket <= OBUS_PLL_FREQ_BUCKETS)) &&
@@ -196,11 +232,53 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const
 
     for (auto& l_chplt_trgt :  i_target_chip.getChildren<fapi2::TARGET_TYPE_MCBIST>(fapi2::TARGET_STATE_FUNCTIONAL))
     {
+
         FAPI_DBG("Scan mc_pll_bndy_bucket_1 ring");
         FAPI_TRY(fapi2::putRing(l_chplt_trgt, mc_pll_bndy_bucket_1, fapi2::RING_MODE_SET_PULSE_NSL),
                  "Error from putRing (mc_pll_bndy)");
     }
 
+    for (auto& l_chplt_trgt :  i_target_chip.getChildren<fapi2::TARGET_TYPE_MC>(fapi2::TARGET_STATE_FUNCTIONAL))
+    {
+
+        RingID ringID = mc_pll_bndy_bucket_1;
+
+        switch(l_set_mc_bucket)
+        {
+            case 1:
+                ringID = mc_pll_bndy_bucket_1;
+                break;
+
+            case 2:
+                ringID = mc_pll_bndy_bucket_2;
+                break;
+
+            case 3:
+                ringID = mc_pll_bndy_bucket_3;
+                break;
+
+            case 4:
+                ringID = mc_pll_bndy_bucket_4;
+                break;
+
+            case 5:
+                ringID = mc_pll_bndy_bucket_5;
+                break;
+
+            default:
+                FAPI_ASSERT(false,
+                            fapi2::P9_SBE_NPLL_INITF_UNSUPPORTED_BUCKET().
+                            set_TARGET(i_target_chip).
+                            set_BUCKET_INDEX(l_nest_pll_bucket),
+                            "Unsupported Nest PLL bucket value!");
+        }
+
+        FAPI_DBG("Scan mc_pll_bndy_bucket_%d ring", l_nest_pll_bucket);
+        FAPI_TRY(fapi2::putRing(l_chplt_trgt, ringID, fapi2::RING_MODE_SET_PULSE_NSL),
+                 "Error from putRing (mc_pll_bndy, ringID: %d)", ringID);
+
+    }
+
 fapi_try_exit:
     FAPI_INF("p9_sbe_chiplet_pll_initf: Exiting ...");
     return fapi2::current_err;
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C
index 9c255adb..71b672aa 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C
@@ -84,6 +84,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
 {
     uint8_t l_read_attr = 0;
     uint8_t l_bypass = 0;
+    uint8_t l_use_dmi_buckets = 0;
     FAPI_INF("p9_sbe_chiplet_pll_setup: Entering ...");
 
     auto l_mc_io_func = i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(
@@ -92,6 +93,9 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
                                     fapi2::TARGET_FILTER_ALL_PCI),
                             fapi2::TARGET_STATE_FUNCTIONAL);
 
+    FAPI_DBG("Read ATTR_CHIP_EC_FEATURE_DMI_MC_PLL_SCAN_BUCKETS ");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_DMI_MC_PLL_SCAN_BUCKETS, i_target_chip, l_use_dmi_buckets));
+
     FAPI_DBG("Reading bypass attribute");
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_bypass));
 
@@ -107,7 +111,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
             FAPI_DBG("Drop PDLY bypass");
             FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_pdly_dcc_bypass(mc, true, false));
 
-            if ( !(l_read_attr) )
+            if ( !(l_read_attr) || l_use_dmi_buckets )
             {
                 FAPI_DBG("Drop DCC  bypass");
                 FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_pdly_dcc_bypass(mc, false, true));
@@ -135,7 +139,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
             uint32_t l_chipletID = targ.getChipletNumber();
 
             if(l_chipletID == XB_CHIPLET_ID || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) ||
-               ((!l_read_attr) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID))  )
+               ((!l_read_attr || l_use_dmi_buckets) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID))  )
             {
                 FAPI_DBG("release pll test enable for except pcie");
                 FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(targ));
@@ -149,7 +153,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
 
             if(l_chipletID == XB_CHIPLET_ID || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) ||
                (l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID) ||
-               ((!l_read_attr) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID))  )
+               ((!l_read_attr || l_use_dmi_buckets) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID))  )
             {
                 FAPI_DBG("Release PLL reset");
                 FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(targ));
@@ -174,7 +178,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
             uint32_t l_chipletID = targ.getChipletNumber();
 
             if(l_chipletID == XB_CHIPLET_ID || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) ||
-               ((!l_read_attr) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID))  )
+               ((!l_read_attr || l_use_dmi_buckets) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID))  )
             {
                 FAPI_DBG("check pll lock for Mc,Xb,Ob");
                 FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(targ, false));
@@ -189,7 +193,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const
 
         if(l_chipletID == XB_CHIPLET_ID || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) ||
            (l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID) ||
-           ((!l_read_attr) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID))  )
+           ((!l_read_attr || l_use_dmi_buckets) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID))  )
         {
             FAPI_TRY(p9_sbe_chiplet_pll_setup_function(targ, l_bypass));
         }
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
index d995106f..c7533c6a 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
@@ -136,6 +136,7 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
 #endif
     const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
     uint8_t attr_force_all = 0;
+    uint8_t l_use_dmi_buckets = 0;
 
     // Created Vectors before hand instead of calling getChildren for each usage
     auto l_perv_func_WO_Core_Cache = i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(
@@ -164,6 +165,9 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_pll_bypass),
              "Error from FAPI_ATTR_GET (ATTR_NEST_MEM_X_O_PCI_BYPASS)");
 
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_DMI_MC_PLL_SCAN_BUCKETS, i_target_chip, l_use_dmi_buckets),
+             "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_DMI_MC_PLL_SCAN_BUCKETS)");
+
     FAPI_INF("p9_sbe_chiplet_reset: Entering ...");
 
     FAPI_DBG("Do a scan0 to all obus chiplets independent of PG information");
@@ -227,7 +231,8 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
             // responsive.  Wait until clocks are started up in hostboot
             uint32_t l_chipletID = targ.getChipletNumber();
 
-            if((l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) && (!l_mc_sync_mode))
+            if((l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) &&
+               (!l_mc_sync_mode && !l_use_dmi_buckets))
             {
                 continue;
             }
@@ -428,7 +433,7 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
         // MC:   on pll, if not in bypsas, and if in sync mode
         if (!l_pll_bypass)
         {
-            if (l_mc_sync_mode)
+            if (l_mc_sync_mode || l_use_dmi_buckets)
             {
                 for (auto& targ : l_perv_func)
                 {
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C
index d37166de..363781de 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C
@@ -65,6 +65,7 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const
         fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
 {
     uint8_t l_read_attr = 0;
+    uint8_t l_use_dmi_buckets = 0;
     fapi2::buffer<uint8_t> l_read_flush_attr;
     fapi2::buffer<uint16_t> l_attr_pg;
     fapi2::buffer<uint64_t> l_pg_vector;
@@ -88,6 +89,11 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const
     FAPI_INF("Reading ATTR_MC_SYNC_MODE");
     FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr));
 
+    FAPI_INF("Read ATTR_CHIP_EC_FEATURE_DMI_MC_PLL_SCAN_BUCKETS ");
+    FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_DMI_MC_PLL_SCAN_BUCKETS, i_target_chip, l_use_dmi_buckets));
+
+    l_read_attr |= l_use_dmi_buckets;
+
     // NEST WEST
     for (auto& nest : l_perv_nest_mc_func)
     {
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index 2dace308..f500bdd2 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -48,6 +48,23 @@
   </attribute>
   <!-- ********************************************************************* -->
   <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_DMI_MC_PLL_SCAN_BUCKETS</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Use nest buckets for mc_pll_bndy for cumulus
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CUMULUS</name>
+        <ec>
+          <value>0x10</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+  <!-- ********************************************************************* -->
+  <attribute>
     <id>ATTR_CHIP_EC_FEATURE_EARLYMODE_FIX</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
index 4599bfd5..e6d68e9f 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml
@@ -351,6 +351,10 @@ attribute tank
 
 <!-- Pervasive EC attributes -->
   <entry>
+           <name>ATTR_CHIP_EC_FEATURE_DMI_MC_PLL_SCAN_BUCKETS</name>
+           <virtual/>
+  </entry>
+  <entry>
            <name>ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE</name>
            <virtual/>
   </entry>