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authorJacob Harvey <jlharvey@us.ibm.com>2017-04-25 09:47:34 -0500
committerSachin Gupta <sgupta2m@in.ibm.com>2017-04-28 12:19:07 -0400
commit6dc41eab547867b09434c468f70526004123589b (patch)
treeeb9fe92c5afb289c2b8ce4e203fb78c2185d56bb /src/import/chips
parent80d80f9215ba298a4db7c08895c6c58a60307e95 (diff)
downloadtalos-sbe-6dc41eab547867b09434c468f70526004123589b.tar.gz
talos-sbe-6dc41eab547867b09434c468f70526004123589b.zip
Change RD_CTR workaround val and update attr name
Change-Id: I00b2cf9cb54fdc4ec54b8f75ae1b9e687d2d4549 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39649 Reviewed-by: ANUWAT SAETOW <asaetow@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Dev-Ready: JACOB L. HARVEY <jlharvey@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39656 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips')
-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index 9a43337b..ddb7009f 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -71,7 +71,7 @@
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
Returns true if the chip has NDL IOValid bits
- P9N dd2
+ P9N dd2
</description>
<chipEcFeature>
<chip>
@@ -162,7 +162,7 @@
</chip>
</chipEcFeature>
</attribute>
- <!-- ********************************************************************* -->
+ <!-- ********************************************************************* -->
<attribute>
<id>ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
@@ -257,7 +257,7 @@
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
Filter pll setting differences.
- Cumulus matches nimbus dd2.
+ Cumulus matches nimbus dd2.
</description>
<chipEcFeature>
<chip>
@@ -345,7 +345,7 @@
<id>ATTR_CHIP_EC_FEATURE_HW405413</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
- HW405413 : NCU sends data out of order
+ HW405413 : NCU sends data out of order
</description>
<chipEcFeature>
<chip>
@@ -1363,7 +1363,7 @@
<id>ATTR_CHIP_EC_FEATURE_HW377094</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
- DD1 only: HW377094 L2 stq and ncu stq deadlock. g/ord_g causes artificial dependency between barrier and snptlbcmp in NCU
+ DD1 only: HW377094 L2 stq and ncu stq deadlock. g/ord_g causes artificial dependency between barrier and snptlbcmp in NCU
while lfsr bits being reused in L2 stq causes entry to never be selected due to high priority ld-hit-st override.
</description>
<chipEcFeature>
@@ -2459,7 +2459,7 @@
<id>ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
- DD1 only: Use the DD1 register addresses for the PHY0 BAR registers, PHY1 BAR registers, and MMIO BAR registers
+ DD1 only: Use the DD1 register addresses for the PHY0 BAR registers, PHY1 BAR registers, and MMIO BAR registers
</description>
<chipEcFeature>
<chip>
@@ -2737,7 +2737,7 @@
</attribute>
<attribute>
- <id>ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WOKRAROUND</id>
+ <id>ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WORKAROUND</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
In below DD2 Nimbus, a workaround after read centering might need to be run.
@@ -2897,7 +2897,7 @@
<id>ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
- For Nimbus DD2 we no longer need a workaround for Ring Save in MPIPL
+ For Nimbus DD2 we no longer need a workaround for Ring Save in MPIPL
</description>
<chipEcFeature>
<chip>
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