Add DLL workaround and unit tests

Change-Id: I142ecd417abb92f4f8ec7d3748563b30359c486d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39673
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Dev-Ready: ANDRE A. MARIN <aamarin@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39726
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>

1 files changed, 73 insertions, 54 deletions

diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index 7d4c58e6..3830464d 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -2702,15 +2702,11 @@
     </chipEcFeature>
   </attribute>
 
-  <!-- ******************************************************************** -->
-  <!-- Memory Section                                                       -->
-  <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_MSS_UT_EC_NIMBUS_LESS_THAN_TWO_OH</id>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Attribute used only for memory subsystem unit tests. Tells us whether
-      the chip EC we're running on is less than 2.0 and we're on a Nimbus
+      Data integrity issue requires us to disable clockgate in read array for Nimbus DD1.0
     </description>
     <chipEcFeature>
       <chip>
@@ -2724,11 +2720,10 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_MCBIST_END_OF_RANK</id>
+    <id>ATTR_CHIP_EC_FEATURE_HW400075</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      MCBIST has a bug where it won't detect the end of a rank properly for
-      a 1R DIMM during super-fast read.
+      Addresses issue where MDI bit was getting wrong values with threadmill and transactional data resulting in coherency issues.
     </description>
     <chipEcFeature>
       <chip>
@@ -2742,10 +2737,10 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_MSS_WR_VREF</id>
+    <id>ATTR_CHIP_EC_FEATURE_HW398139</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      In DD1 Nimbus in the WR VREF algorithm, certain work-arounds are needed
+      Avoid powerbus early hangs by enabling prefetch drops to break out of fairness issue with prefetch ops
     </description>
     <chipEcFeature>
       <chip>
@@ -2759,10 +2754,10 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_MSS_DQS_POLARITY</id>
+    <id>ATTR_CHIP_EC_FEATURE_HW400932</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      For Monza DDR port 2, one pair of DQS P/N is swapped polarity.
+      ATAG info corruption on presp issue requires us to disable clockgate for Nimbus DD1.0
     </description>
     <chipEcFeature>
       <chip>
@@ -2776,10 +2771,10 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_MSS_VREF_DAC</id>
+    <id>ATTR_CHIP_EC_FEATURE_HW401780</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      VREF DAC work-around for Nimbus DD1.0
+      Need AMO caching disabled for multiple defects until Nimbus DD2.0
     </description>
     <chipEcFeature>
       <chip>
@@ -2793,10 +2788,10 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_MSS_WAT_DEBUG_ATTN</id>
+    <id>ATTR_CHIP_EC_FEATURE_HW406577</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      WAT Debug Attention work-around for Nimbus DD1.0
+      Noise window disabled in DD1 because continually reocurring intermittent UE's can cause us to hang on refreshes.
     </description>
     <chipEcFeature>
       <chip>
@@ -2809,11 +2804,15 @@
     </chipEcFeature>
   </attribute>
 
+  <!-- ******************************************************************** -->
+  <!-- Memory Section                                                       -->
+  <!-- ******************************************************************** -->
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE</id>
+    <id>ATTR_CHIP_EC_FEATURE_MCBIST_END_OF_RANK</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Data integrity issue requires us to disable clockgate in read array for Nimbus DD1.0
+      MCBIST has a bug where it won't detect the end of a rank properly for
+      a 1R DIMM during super-fast read.
     </description>
     <chipEcFeature>
       <chip>
@@ -2827,10 +2826,10 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW400075</id>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_WAT_DEBUG_ATTN</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Addresses issue where MDI bit was getting wrong values with threadmill and transactional data resulting in coherency issues.
+      WAT Debug Attention work-around for Nimbus DD1.0
     </description>
     <chipEcFeature>
       <chip>
@@ -2844,10 +2843,11 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW398139</id>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_UT_EC_NIMBUS_LESS_THAN_TWO_OH</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Avoid powerbus early hangs by enabling prefetch drops to break out of fairness issue with prefetch ops
+      Attribute used only for memory subsystem unit tests. Tells us whether
+      the chip EC we're running on is less than 2.0 and we're on a Nimbus
     </description>
     <chipEcFeature>
       <chip>
@@ -2861,10 +2861,10 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW384794</id>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_WR_VREF</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Workaround for defect where clock enables to PHY were incorrectly driven
+      In DD1 Nimbus in the WR VREF algorithm, certain work-arounds are needed
     </description>
     <chipEcFeature>
       <chip>
@@ -2878,10 +2878,10 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW375732</id>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_DQS_POLARITY</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Workaround for Data mismatch discovered by Geyzer at certain async frequency ratios
+      For Monza DDR port 2, one pair of DQS P/N is swapped polarity.
     </description>
     <chipEcFeature>
       <chip>
@@ -2895,12 +2895,10 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_MSS_TRAINING_BAD_BITS</id>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_VREF_DAC</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      For Nimbus pre DD1.02 we want to pass DDR training if we see 'correctable'
-      errors. This isn't the case for post-DD1.02 where we want to pass/fail
-      training based on the results from the PHY itself
+      VREF DAC work-around for Nimbus DD1.0
     </description>
     <chipEcFeature>
       <chip>
@@ -2914,10 +2912,12 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW400932</id>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_TRAINING_BAD_BITS</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      ATAG info corruption on presp issue requires us to disable clockgate for Nimbus DD1.0
+      For Nimbus pre DD1.02 we want to pass DDR training if we see 'correctable'
+      errors. This isn't the case for post-DD1.02 where we want to pass/fail
+      training based on the results from the PHY itself
     </description>
     <chipEcFeature>
       <chip>
@@ -2931,10 +2931,10 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW401780</id>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_CHECK_DISABLE_HW_VREF_CAL</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Need AMO caching disabled for multiple defects until Nimbus DD2.0
+      In below DD2 Nimbus, the HW VREF calibration needs to be checked against the chip subversion to see if it can be run.
     </description>
     <chipEcFeature>
       <chip>
@@ -2948,10 +2948,10 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_HW406577</id>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WORKAROUND</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      Noise window disabled in DD1 because continually reocurring intermittent UE's can cause us to hang on refreshes.
+      In below DD2 Nimbus, a workaround after read centering might need to be run.
     </description>
     <chipEcFeature>
       <chip>
@@ -2965,10 +2965,12 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_MSS_CHECK_DISABLE_HW_VREF_CAL</id>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_ODT_CONFIG</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      In below DD2 Nimbus, the HW VREF calibration needs to be checked against the chip subversion to see if it can be run.
+      For Nimbus pre DD2.** we need to swap ODT2 and ODT3 values in the
+      DDRPHY_SEQ_ODT_RD/WR_CONFIG registers due to a PHY erratum.
+      Post DD2.** will have a hardware enabled fix for this (HW389360).
     </description>
     <chipEcFeature>
       <chip>
@@ -2982,10 +2984,11 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WORKAROUND</id>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_BLUE_WATERFALL_ADJUST</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      In below DD2 Nimbus, a workaround after read centering might need to be run.
+      In DD1.** Nimbus, the blue waterfall can calibrate to an incorrect value. In DD2 Nimbus,
+      This isn't the case as the HW will not allow this calibration value
     </description>
     <chipEcFeature>
       <chip>
@@ -2999,12 +3002,10 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_MSS_ODT_CONFIG</id>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_CHECK_DIABLE_RD_VREF_CAL_VREFSENSE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      For Nimbus pre DD2.** we need to swap ODT2 and ODT3 values in the
-      DDRPHY_SEQ_ODT_RD/WR_CONFIG registers due to a PHY erratum.
-      Post DD2.** will have a hardware enabled fix for this (HW389360).
+      In below DD2 Nimbus, the RD VREF cal VREF sense needs to be checked against the chip subversion to see if it should be run.
     </description>
     <chipEcFeature>
       <chip>
@@ -3018,11 +3019,10 @@
   </attribute>
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_MSS_BLUE_WATERFALL_ADJUST</id>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_DLL_WORKAROUND</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      In DD1.** Nimbus, the blue waterfall can calibrate to an incorrect value. In DD2 Nimbus,
-      This isn't the case as the HW will not allow this calibration value
+      Run DLL workaround algorithm to fix bad voltage settings pre DD2.0
     </description>
     <chipEcFeature>
       <chip>
@@ -3053,12 +3053,32 @@
     </chipEcFeature>
   </attribute>
 
+  <!-- ******************************************************************** -->
+  <!-- End Memory Section                                                   -->
+  <!-- ******************************************************************** -->
 
   <attribute>
-    <id>ATTR_CHIP_EC_FEATURE_MSS_CHECK_DIABLE_RD_VREF_CAL_VREFSENSE</id>
+    <id>ATTR_CHIP_EC_FEATURE_HW384794</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
     <description>
-      In below DD2 Nimbus, the RD VREF cal VREF sense needs to be checked against the chip subversion to see if it should be run.
+      Workaround for defect where clock enables to PHY were incorrectly driven
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW375732</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Workaround for Data mismatch discovered by Geyzer at certain async frequency ratios
     </description>
     <chipEcFeature>
       <chip>
@@ -3173,6 +3193,7 @@
     </chipEcFeature>
   </attribute>
 
+  <!-- ******************************************************************** -->
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW399466</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
@@ -3190,6 +3211,7 @@
     </chipEcFeature>
   </attribute>
 
+  <!-- ******************************************************************** -->
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_HW355538</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
@@ -3207,6 +3229,7 @@
     </chipEcFeature>
   </attribute>
 
+  <!-- ******************************************************************** -->
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>
@@ -3224,10 +3247,6 @@
     </chipEcFeature>
   </attribute>
 
-  <!-- ******************************************************************** -->
-  <!-- End Memory Section                                                   -->
-  <!-- ******************************************************************** -->
-
     <!-- ******************************************************************** -->
     <attribute>
     <id>ATTR_CHIP_EC_FEATURE_DD1_ANALOG</id>