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| author | Jacob Harvey <jlharvey@us.ibm.com> | 2017-08-14 10:22:14 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-12-17 21:12:43 -0600 |
| commit | 3b8fd10f3017c27fb6d10188857a42c76ff35f69 (patch) | |
| tree | edb1064e509e7446304b2eace2a03848777ef497 /src/import/chips | |
| parent | 65add1de701a6e24d9478fefbfdd99458246d0fd (diff) | |
| download | talos-sbe-3b8fd10f3017c27fb6d10188857a42c76ff35f69.tar.gz talos-sbe-3b8fd10f3017c27fb6d10188857a42c76ff35f69.zip | |
Add in L1 draminit_training_adv files
Change-Id: I1a79898572e675242f0c572bd708bbc05b63039d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44604
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69805
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index 90390210..f6d3915b 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -1968,6 +1968,25 @@ </attribute> <attribute> + <id>ATTR_MSS_CUSTOM_TRAINING_ADV_PATTERNS</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + Special training pattern used for draminit_training_advance. Used for read centering + There can be two patterns used here. + The first 0-15 bits are for PATTERN1, + bits 16-32 are for PATTERN2. + If this attribute is set to 0, using the default values of: + 0x952D for PATTERN1 + 0x594A for PATTERN2 + </description> + <initToZero></initToZero> + <valueType>uint32</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>custom_training_adv_pattern</mssAccessorName> + </attribute> + + <attribute> <id>ATTR_MSS_VREF_CAL_ENABLE</id> <targetType>TARGET_TYPE_MCS</targetType> <description> |
