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| author | Brian Silver <bsilver@us.ibm.com> | 2016-09-12 07:06:43 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-12-17 21:05:23 -0600 |
| commit | 1a9deb52ca5ec62e7325de21ce48bea3fd6d4906 (patch) | |
| tree | a86d53cbfd902c4e7f27a5709cf60573ba48014a /src/import/chips | |
| parent | 281819c9a3f66e31ce9e5117050c088f1743cc77 (diff) | |
| download | talos-sbe-1a9deb52ca5ec62e7325de21ce48bea3fd6d4906.tar.gz talos-sbe-1a9deb52ca5ec62e7325de21ce48bea3fd6d4906.zip | |
Add bit field of master ranks attribute for PRD
Change-Id: I2af0639ccc25952d6175c1c940a1d4a60af9843d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29480
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69781
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index 8c8f0e51..ff0003d1 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -1162,6 +1162,20 @@ </attribute> <attribute> + <id>ATTR_EFF_DIMM_RANKS_CONFIGED</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + Bit wise representation of master ranks in each DIMM that are used for reads and writes. + Used by PRD. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array> 2 2</array> + <mssAccessorName>eff_dimm_ranks_configed</mssAccessorName> + </attribute> + + <attribute> <id>ATTR_EFF_NUM_PACKAGES_PER_RANK</id> <targetType>TARGET_TYPE_MCS</targetType> <description>Specifies the number of DRAM packages per rank.</description> |
