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| author | CHRISTINA L. GRAVES <clgraves@us.ibm.com> | 2017-03-03 10:01:06 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-03-16 11:22:58 -0400 |
| commit | 1875d5ca55dc648ea95c5673752f548caf6fcd9c (patch) | |
| tree | 27469f57ecbdf98f83adce1a5323f04ea9b535b1 /src/import/chips | |
| parent | 5701b4f930d3081c69003b57b2982ff2ae2885b5 (diff) | |
| download | talos-sbe-1875d5ca55dc648ea95c5673752f548caf6fcd9c.tar.gz talos-sbe-1875d5ca55dc648ea95c5673752f548caf6fcd9c.zip | |
Change for INT unit because I had reset being set that should only be for DD2
Change-Id: I47b9d1b710ad57f769999700cb876c9b4304aae4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37466
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37468
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C index 52c26cfe..a5812c93 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C @@ -730,6 +730,8 @@ extern "C" { uint64_t l_int_vc_eqc_config_mask_verify_vc_syncs_complete = 0x00000000F8000000; const uint64_t l_intp_scrub_masks[4] = {PU_INT_VC_IVC_SCRUB_MASK, PU_INT_VC_SBC_SCRUB_MASK, PU_INT_VC_EQC_SCRUB_MASK, PU_INT_PC_VPC_SCRUB_MASK}; + //TODO For DD1 this is broken - readd when fixed in DD2 +#ifdef INT_DD2 // Read INT_CQ_RST_CTL so that we don't override anything fapi2::getScom(i_target, PU_INT_CQ_RST_CTL, l_data); @@ -755,12 +757,16 @@ extern "C" { l_data), "INTP master or slave is not IDLE"); //Set sync_reset in RST_CTL - //TODO For DD1 this is broken - readd when fixed in DD2 -#ifdef INT_DD2 l_data.setBit<PU_INT_CQ_RST_CTL_SYNC_RESET>(); fapi2::putScom(i_target, PU_INT_CQ_RST_CTL, l_data); #else //Workaround for the sync reset + //------------------------------------------------------------------ + //Use syncs to make sure no more requests are pending on the queue + //------------------------------------------------------------------ + //Trigger VC Syncs + //This is done up in the CAPP unit because we need the fabric + //Verify VC syncs complete and then reset sync done bits fapi2::getScom(i_target, PU_INT_VC_EQC_CONFIG, l_data); FAPI_ASSERT((l_data & l_int_vc_eqc_config_mask_verify_vc_syncs_complete) == |
