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author | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-01-24 03:02:32 -0600 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-01-26 22:34:42 -0500 |
commit | 15f82bd95cd74099115fec42d81b1a4aa38ba662 (patch) | |
tree | e2d64758b4c0c952992fbb8745c162b84e20c510 /src/import/chips | |
parent | 699a2315f4ac2fde790be769797c57f09207125b (diff) | |
download | talos-sbe-15f82bd95cd74099115fec42d81b1a4aa38ba662.tar.gz talos-sbe-15f82bd95cd74099115fec42d81b1a4aa38ba662.zip |
Remove workaround for DD1 SW reset for XIVE
Change-Id: Ic2cf3510350aa00c0641cc910824000bf58d8276
RTC: 177741
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52512
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: RAJA DAS <rajadas2@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52515
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips')
4 files changed, 22 insertions, 292 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C index 8b4e5725..09305f92 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -133,64 +133,6 @@ extern "C" { fapi2::buffer<uint64_t> l_data(0); - uint8_t l_useXiveHwReset; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_USE_XIVE_HW_RESET, - i_target, - l_useXiveHwReset)); - - //TODO RTC:177741 HW Reset for XIVE isn't working, use this workaround until it does - if(!l_useXiveHwReset) - { - //This part is actually used for the intp quiesce DD1 workaround but - //needs to be here because after this, the fabric is finished - uint64_t l_notify_page_addr = 0x0ull; - uint32_t l_numGranules; - p9_ADU_oper_flag l_adu_flag; - uint8_t l_write_data[8] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; - - //Read the Interrupt Controller BAR to figure out the Notify Port page address - //Notify Port Page is the second page off the IC BAR - //bit 1 will tell whether we need to add a 4K offset (if bit 1 = '0') or - //64K offset (if bit 1 = '1') - //Add this to the address (bits 8:48 of the IC BAR) - FAPI_TRY(fapi2::getScom(i_target, PU_INT_CQ_IC_BAR, l_data)); - l_notify_page_addr = (l_data & 0x00FFFFFFFFFF8000ull) + 0x1000; - - if (l_data.getBit<1>() != 0) - { - l_notify_page_addr = l_notify_page_addr + 0xF000; - } - - //-------------------------------------------------------------------- - // Use syncs to make sure no more requests are pending on the queues - //-------------------------------------------------------------------- - //Trigger VC syncs - //write IPI trigger sync - l_adu_flag.setAutoIncrement(false); - l_adu_flag.setOperationType(p9_ADU_oper_flag::CACHE_INHIBIT); - l_adu_flag.setLockControl(true); - l_adu_flag.setOperFailCleanup(true); - l_adu_flag.setFastMode(false); - l_adu_flag.setItagMode(false); - l_adu_flag.setEccMode(false); - l_adu_flag.setEccItagOverrideMode(false); - l_adu_flag.setTransactionSize(static_cast<p9_ADU_oper_flag::Transaction_size_t>(0x8)); - FAPI_TRY(p9_adu_setup(i_target, (l_notify_page_addr + 0xC00), false, l_adu_flag.setFlag(), l_numGranules)); - FAPI_TRY(p9_adu_access(i_target, (l_notify_page_addr + 0xC00), false, l_adu_flag.setFlag(), true, true, l_write_data)); - //write HW trigger sync - FAPI_TRY(p9_adu_setup(i_target, (l_notify_page_addr + 0xC80), false, l_adu_flag.setFlag(), l_numGranules)); - FAPI_TRY(p9_adu_access(i_target, (l_notify_page_addr + 0xC80), false, l_adu_flag.setFlag(), true, true, l_write_data)); - //write OS trigger sync - FAPI_TRY(p9_adu_setup(i_target, (l_notify_page_addr + 0xD00), false, l_adu_flag.setFlag(), l_numGranules)); - FAPI_TRY(p9_adu_access(i_target, (l_notify_page_addr + 0xD00), false, l_adu_flag.setFlag(), true, true, l_write_data)); - //write Hyp trigger sync - FAPI_TRY(p9_adu_setup(i_target, (l_notify_page_addr + 0xD80), false, l_adu_flag.setFlag(), l_numGranules)); - FAPI_TRY(p9_adu_access(i_target, (l_notify_page_addr + 0xD80), false, l_adu_flag.setFlag(), true, true, l_write_data)); - //Write Redist trigger sync - FAPI_TRY(p9_adu_setup(i_target, (l_notify_page_addr + 0xE00), false, l_adu_flag.setFlag(), l_numGranules)); - FAPI_TRY(p9_adu_access(i_target, (l_notify_page_addr + 0xE00), false, l_adu_flag.setFlag(), true, true, l_write_data)); - } - FAPI_TRY(fapi2::getScom(i_target, CAPP_FLUSHSHUE, l_data)); if (l_data != 0x0ull) @@ -833,227 +775,43 @@ extern "C" { { FAPI_DBG("p9_intp_check_quiesce: Entering..."); fapi2::buffer<uint64_t> l_data(0); - uint8_t l_useXiveHwReset; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_USE_XIVE_HW_RESET, - i_target, - l_useXiveHwReset)); + // Read INT_CQ_RST_CTL so that we don't override anything + FAPI_TRY(fapi2::getScom(i_target, PU_INT_CQ_RST_CTL, l_data)); + + // Set bit in INT_CQ_RST_CTL to request quiesce + l_data.setBit<PU_INT_CQ_RST_CTL_QUIESCE_PB>(); + FAPI_TRY(fapi2::putScom(i_target, PU_INT_CQ_RST_CTL, l_data)); - //TODO RTC:177741 HW reset for INT is not working, need to retest this - //if we ever think the hw is fixed - if(l_useXiveHwReset) + // Poll master and slave quiesced via bits in RST_CTL + for (uint32_t i = 0; i < C_NUM_TRIES_QUIESCE_STATE; i++) { - // Read INT_CQ_RST_CTL so that we don't override anything FAPI_TRY(fapi2::getScom(i_target, PU_INT_CQ_RST_CTL, l_data)); - // Set bit in INT_CQ_RST_CTL to request quiesce - l_data.setBit<PU_INT_CQ_RST_CTL_QUIESCE_PB>(); - FAPI_TRY(fapi2::putScom(i_target, PU_INT_CQ_RST_CTL, l_data)); - - // Poll master and slave quiesced via bits in RST_CTL - for (uint32_t i = 0; i < C_NUM_TRIES_QUIESCE_STATE; i++) + if (l_data.getBit<PU_INT_CQ_RST_CTL_MASTER_IDLE>() && + l_data.getBit<PU_INT_CQ_RST_CTL_SLAVE_IDLE>()) { - FAPI_TRY(fapi2::getScom(i_target, PU_INT_CQ_RST_CTL, l_data)); - - if (l_data.getBit<PU_INT_CQ_RST_CTL_MASTER_IDLE>() && - l_data.getBit<PU_INT_CQ_RST_CTL_SLAVE_IDLE>()) - { - break; - } - - FAPI_TRY(fapi2::delay(C_INTP_DELAY_NS, C_INTP_DELAY_CYCLES)); + break; } - FAPI_ASSERT((l_data.getBit<PU_INT_CQ_RST_CTL_MASTER_IDLE>() - && l_data.getBit<PU_INT_CQ_RST_CTL_SLAVE_IDLE>()), - fapi2::P9_INTP_QUIESCE_TIMEOUT() - .set_TARGET(i_target) - .set_DATA(l_data), "INTP master or slave is not IDLE"); - - //Set sync_reset in RST_CTL - l_data.setBit<PU_INT_CQ_RST_CTL_SYNC_RESET>(); - FAPI_TRY(fapi2::putScom(i_target, PU_INT_CQ_RST_CTL, l_data)); + FAPI_TRY(fapi2::delay(C_INTP_DELAY_NS, C_INTP_DELAY_CYCLES)); } - else - { - uint64_t l_int_vc_eqc_config_mask_verify_vc_syncs_complete = 0x00000000F8000000; - const uint64_t l_intp_scrub_masks[4] = - { - PU_INT_VC_IVC_SCRUB_MASK, PU_INT_VC_SBC_SCRUB_MASK, - PU_INT_VC_EQC_SCRUB_MASK, PU_INT_PC_VPC_SCRUB_MASK - }; - //Workaround for the sync reset - //------------------------------------------------------------------ - //Use syncs to make sure no more requests are pending on the queue - //------------------------------------------------------------------ - //Trigger VC Syncs - //This is done up in the CAPP unit because we need the fabric - - //Verify VC syncs complete and then reset sync done bits - FAPI_TRY(fapi2::getScom(i_target, PU_INT_VC_EQC_CONFIG, l_data)); - FAPI_ASSERT((l_data & l_int_vc_eqc_config_mask_verify_vc_syncs_complete) == - l_int_vc_eqc_config_mask_verify_vc_syncs_complete, - fapi2::P9_INT_WORKAROUND_ERR().set_TARGET(i_target) - .set_ADDRESS(PU_INT_VC_EQC_CONFIG) - .set_DATA(l_data), - "Error with VC syncs not being set as expected"); - l_data.clearBit<32>() - .clearBit<33>() - .clearBit<34>() - .clearBit<35>() - .clearBit<36>(); - FAPI_TRY(fapi2::putScom(i_target, PU_INT_VC_EQC_CONFIG, l_data)); - - //--------------------------- - //Scrub all Int caches - //--------------------------- - //Fill the scrub mask regs to 0 - for (uint32_t i = 0; i < 4; i++) - { - FAPI_TRY(fapi2::putScom(i_target, l_intp_scrub_masks[i], 0x0000000000000000)); - } - - //Start the scrub operation in all caches andPoll for completion - FAPI_TRY(p9_int_scrub_caches(i_target), "Error scrubbing the caches"); - - //---------------------------- - //Change all VSDs to invalid - //---------------------------- - //Change all VC VSDs - //Do the IVE VC VSD - FAPI_TRY(fapi2::putScom(i_target, PU_INT_VC_VSD_TABLE_ADDR, 0x8000000000000000)); - - for (uint32_t i = 0; i < 16; i++) - { - FAPI_TRY(fapi2::putScom(i_target, PU_INT_VC_VSD_TABLE_DATA, 0x0000000000000000)); - } - - //Do the ESB VC VSD - FAPI_TRY(fapi2::putScom(i_target, PU_INT_VC_VSD_TABLE_ADDR, 0x8001000000000000)); - - for (uint32_t i = 0; i < 16; i++) - { - FAPI_TRY(fapi2::putScom(i_target, PU_INT_VC_VSD_TABLE_DATA, 0x0000000000000000)); - } - - //Do the EQD VC VSD - FAPI_TRY(fapi2::putScom(i_target, PU_INT_VC_VSD_TABLE_ADDR, 0x8002000000000000)); - - for (uint32_t i = 0; i < 16; i++) - { - FAPI_TRY(fapi2::putScom(i_target, PU_INT_VC_VSD_TABLE_DATA, 0x0000000000000000)); - } - - //Do the VPD VC VSD - FAPI_TRY(fapi2::putScom(i_target, PU_INT_VC_VSD_TABLE_ADDR, 0x8003000000000000)); - - for (uint32_t i = 0; i < 32; i++) - { - FAPI_TRY(fapi2::putScom(i_target, PU_INT_VC_VSD_TABLE_DATA, 0x0000000000000000)); - } - - //Do the IRQ VC VSD - FAPI_TRY(fapi2::putScom(i_target, PU_INT_VC_VSD_TABLE_ADDR, 0x8004000000000000)); - for (uint32_t i = 0; i < 6; i++) - { - FAPI_TRY(fapi2::putScom(i_target, PU_INT_VC_VSD_TABLE_DATA, 0x0000000000000000)); - } - - //Change all PC VSDs - //Do the IVE PC VSD - FAPI_TRY(fapi2::putScom(i_target, PU_INT_PC_VSD_TABLE_ADDR, 0x8000000000000000)); - - for (uint32_t i = 0; i < 16; i++) - { - FAPI_TRY(fapi2::putScom(i_target, PU_INT_PC_VSD_TABLE_DATA, 0x0000000000000000)); - } - - //Do the ESB PC VSD - FAPI_TRY(fapi2::putScom(i_target, PU_INT_PC_VSD_TABLE_ADDR, 0x8001000000000000)); - - for (uint32_t i = 0; i < 16; i++) - { - FAPI_TRY(fapi2::putScom(i_target, PU_INT_PC_VSD_TABLE_DATA, 0x0000000000000000)); - } - - //Do the EQD PC VSD - FAPI_TRY(fapi2::putScom(i_target, PU_INT_PC_VSD_TABLE_ADDR, 0x8002000000000000)); - - for (uint32_t i = 0; i < 16; i++) - { - FAPI_TRY(fapi2::putScom(i_target, PU_INT_PC_VSD_TABLE_DATA, 0x0000000000000000)); - } - - //Do the VPD PC VSD - FAPI_TRY(fapi2::putScom(i_target, PU_INT_PC_VSD_TABLE_ADDR, 0x8002000000000000)); - - for (uint32_t i = 0; i < 32; i++) - { - FAPI_TRY(fapi2::putScom(i_target, PU_INT_PC_VSD_TABLE_DATA, 0x0000000000000000)); - } + FAPI_ASSERT((l_data.getBit<PU_INT_CQ_RST_CTL_MASTER_IDLE>() + && l_data.getBit<PU_INT_CQ_RST_CTL_SLAVE_IDLE>()), + fapi2::P9_INTP_QUIESCE_TIMEOUT() + .set_TARGET(i_target) + .set_DATA(l_data), "INTP master or slave is not IDLE"); - //---------------------------- - //Re-scrub all Int caches - //---------------------------- - //Start the scrub operation in all caches and Poll for completion - FAPI_TRY(p9_int_scrub_caches(i_target), "Error re-scrubbing the caches"); - //---------------------------- - //Disable all thread contexts (this will also trigger an internal reset) - //---------------------------- - FAPI_TRY(fapi2::putScom(i_target, PU_INT_TCTXT_EN0, 0x0000000000000000)); - FAPI_TRY(fapi2::putScom(i_target, PU_INT_TCTXT_EN1, 0x0000000000000000)); - - //---------------------------- - //Reset Quiesce - //---------------------------- - FAPI_TRY(fapi2::putScom(i_target, PU_INT_CQ_RST_CTL, 0x0000000000000000)); - } + //Set sync_reset in RST_CTL + l_data.setBit<PU_INT_CQ_RST_CTL_SYNC_RESET>(); + FAPI_TRY(fapi2::putScom(i_target, PU_INT_CQ_RST_CTL, l_data)); fapi_try_exit: FAPI_DBG("p9_intp_check_quiesce: Exiting..."); return fapi2::current_err; } - //This is a helper function to scrub all the caches for Int - fapi2::ReturnCode p9_int_scrub_caches( - const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) - { - fapi2::buffer<uint64_t> l_scrub_trig_data(0); - const uint64_t l_scrub_addrs[4] = - { - PU_INT_VC_IVC_SCRUB_TRIG, PU_INT_VC_SBC_SCRUB_TRIG, - PU_INT_VC_EQC_SCRUB_TRIG, PU_INT_PC_VPC_SCRUB_TRIG - }; - - //Start the scrub operation in all caches - for (uint32_t i = 0; i < 4; i++) - { - fapi2::putScom(i_target, l_scrub_addrs[i], 0xA000000000000000); - - for (uint32_t j = 0; j < C_NUM_TRIES_QUIESCE_STATE; j++) - { - FAPI_TRY(fapi2::delay(C_INTP_DELAY_NS, C_INTP_DELAY_CYCLES)); - FAPI_TRY(fapi2::getScom(i_target, l_scrub_addrs[i], l_scrub_trig_data)); - - if (!l_scrub_trig_data.getBit<0>()) - { - break; - } - } - - FAPI_ASSERT(!l_scrub_trig_data.getBit<0>(), - fapi2::P9_INT_WORKAROUND_ERR() - .set_TARGET(i_target) - .set_ADDRESS(l_scrub_addrs[i]) - .set_DATA(l_scrub_trig_data), - "INT_VC_IVC_SCRUB_TRIG register is not complete"); - } - - fapi_try_exit: - return fapi2::current_err; - } - fapi2::ReturnCode p9_pm_check_quiesce(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { // Bit-13 used to set WAKEUP_NOTIFY_SELECT bit on the Core Power Management Mode Reg diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.H index d60d4ca1..4090d4ed 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_check_quiesce.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -124,12 +124,6 @@ extern "C" { fapi2::ReturnCode p9_pm_check_quiesce( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); - /// @brief Helper function to scrub all the caches for Int - /// @param[in] i_target => P9 chip target - /// @return FAPI_RC_SUCCESS if the scrube completes successfully - fapi2::ReturnCode p9_int_scrub_caches( - const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); - } //extern "C" #endif //_P9_SBE_CHECK_QUIESCE_H_ diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index d08cff6e..c791aedf 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -6125,24 +6125,6 @@ </attribute> <!-- ********************************************************************* --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_USE_XIVE_HW_RESET</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description> - HW reset for XIVE unit is not working in DD1 or DD2. Potentially - could be fixed in the future - </description> - <chipEcFeature> - <chip> - <name>ENUM_ATTR_NAME_NIMBUS</name> - <ec> - <value>0x20</value> - <test>GREATER_THAN</test> - </ec> - </chip> - </chipEcFeature> - </attribute> - <!-- ********************************************************************* --> - <attribute> <id>ATTR_CHIP_EC_FEATURE_POUNDV_VALIDATE_DISABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index 08e555f5..d222b7a1 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -546,10 +546,6 @@ attribute tank <value>0x05</value> </entry> <entry> - <name>ATTR_CHIP_EC_FEATURE_USE_XIVE_HW_RESET</name> - <virtual/> - </entry> - <entry> <name>ATTR_CHIP_EC_FEATURE_HW415945</name> <virtual/> </entry> |