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| author | Andre Marin <aamarin@us.ibm.com> | 2017-04-26 19:31:59 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-12-17 21:11:41 -0600 |
| commit | c296d8d25294e65888054e84494e07e8f53c72b9 (patch) | |
| tree | c8d1fc0a05a3224a160d92a398f2e5a514138d9f /src/import/chips/p9 | |
| parent | 8c2f174a055a24687bfc1e269e06c3b5e3bba11c (diff) | |
| download | talos-sbe-c296d8d25294e65888054e84494e07e8f53c72b9.tar.gz talos-sbe-c296d8d25294e65888054e84494e07e8f53c72b9.zip | |
Add PHY sequencer refresh settings after draminit
Change-Id: I2fd7738f8909c3567c6cda8640bbe9d70b62bda3
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39757
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69802
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index be1a5150..450f286c 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -3175,4 +3175,20 @@ <mssAccessorName>rtt_nom_override_disable</mssAccessorName> </attribute> + <attribute> + <id>ATTR_MSS_PHY_SEQ_REFRESH</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description> + Controls ENABLE/DISABLE of workaround that sets + the PHY sequencer to trigger refresh after draminit. + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <enum>DISABLE = 0, ENABLE = 1</enum> + <mssUnits> bool </mssUnits> + <array> 2 </array> + <mssAccessorName>phy_seq_refresh</mssAccessorName> + </attribute> + </attributes> |
