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| author | Joe McGill <jmcgill@us.ibm.com> | 2018-02-07 16:37:55 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-02-12 15:01:48 -0500 |
| commit | 2661ddab79843ac96a7986c3ee9b1bb7dcc46a89 (patch) | |
| tree | 14ebf040de19c412a3fcb24ffcb8f1475aa1e880 /src/import/chips/p9 | |
| parent | 92d0dc997d185360fed7f8d44ffda88514830cac (diff) | |
| download | talos-sbe-2661ddab79843ac96a7986c3ee9b1bb7dcc46a89.tar.gz talos-sbe-2661ddab79843ac96a7986c3ee9b1bb7dcc46a89.zip | |
enforce strict 512 GB per socket limit on Witherspoon memory map (part2)
first commit merged before HW testing was complete, and caused
issue with skiboot's detection of the MCD workaround mechanism
this update restores the chip address extension HW programming to 0x7,
(to avoid a coreq skiboot change) but should still restrict the allocation
to lie within the first 512 GB of address space on each socket
Change-Id: Ie844a609c16ffa1aa38091bae42145da9c7912a4
CQ: SW415901
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53594
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53642
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C | 5 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H | 4 |
2 files changed, 6 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C index a1fd87bc..feea764d 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -295,6 +295,9 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( l_addr_extension_chip_id), "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID"); + // mask all but LSB, prevent regions above RA bit 21 from being exposed to callers + l_addr_extension_chip_id &= 0x01; + // align to RA l_addr_extension_enable.insertFromRight < FABRIC_ADDR_LS_GROUP_ID_START_BIT, FABRIC_ADDR_LS_GROUP_ID_END_BIT - FABRIC_ADDR_LS_GROUP_ID_START_BIT + 1 > diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H index afdf5b4c..6a0c0a35 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H @@ -70,9 +70,9 @@ const uint64_t P9_FBC_UTILS_LAST_ADDR_IN_CACHELINE = 0x78ULL; const uint64_t FABRIC_CACHELINE_SIZE = 0x80; // chip address extension mask, for HW423589_OPTION2 -// repurposes chip ID(2) as address bits +// repurposes chip ID(0:2) as address bits const uint8_t CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_HW423589_OPTION2 = 0x0; -const uint8_t CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2 = 0x1; +const uint8_t CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2 = 0x7; const uint64_t MAX_INTERLEAVE_GROUP_SIZE = 0x40000000000ULL; // 4_TB const uint64_t MAX_INTERLEAVE_GROUP_SIZE_HW423589_OPTION2 = 0x8000000000ULL; // 512_GB |
