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author | Girisankar Paulraj <gpaulraj@in.ibm.com> | 2016-06-13 04:22:11 -0500 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-09-26 03:09:31 -0400 |
commit | aaf33ec6e020cd863069c1c25771f837929f4e75 (patch) | |
tree | 9a1b5e327dcf0d3b540296d108a7b3098a1fb67b /src/import/chips/p9/utils/imageProcs/p9_tor.H | |
parent | 7721ff79aff1e4774ec0630d98f397dd303933a8 (diff) | |
download | talos-sbe-aaf33ec6e020cd863069c1c25771f837929f4e75.tar.gz talos-sbe-aaf33ec6e020cd863069c1c25771f837929f4e75.zip |
Added 0b0,1,2 and 3 chiplet TOR block copy support.
Based on vpd module ring requirement, ob chiplet is separated based
on each chiplet instance. So, ob becomes as ob0, 0b1, 0b2 and 0b3.
Added more logic to traverse over above defined chiplets.
Change-Id: I85b04c33236a03ac49676522325f5e140067e8f1
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25706
Tested-by: Jenkins Server
Tested-by: Hostboot CI
Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Reviewed-by: Martin Peschke <mpeschke@de.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30246
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/utils/imageProcs/p9_tor.H')
-rw-r--r-- | src/import/chips/p9/utils/imageProcs/p9_tor.H | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/src/import/chips/p9/utils/imageProcs/p9_tor.H b/src/import/chips/p9/utils/imageProcs/p9_tor.H index 13a00e98..26ef5a20 100644 --- a/src/import/chips/p9/utils/imageProcs/p9_tor.H +++ b/src/import/chips/p9/utils/imageProcs/p9_tor.H @@ -67,6 +67,7 @@ typedef struct } TorPpeBlock_t; + #define IMGBUILD_TGR_RING_FOUND 0 #define IMGBUILD_TGR_RING_BLOCKS_FOUND 0 #define IMGBUILD_TGR_RING_NOT_FOUND 1 // Ring is not found in HW image. @@ -146,12 +147,16 @@ typedef enum SbeTorId N3_CPLT = 4, XB_CPLT = 5, MC_CPLT = 6, - PCI0_CPLT = 7, - PCI1_CPLT = 8, - PCI2_CPLT = 9, - EQ_CPLT = 10, - EC_CPLT = 11, - SBE_NOOF_CHIPLETS = 12 + OB0_CPLT = 7, + OB1_CPLT = 8, + OB2_CPLT = 9, + OB3_CPLT = 10, + PCI0_CPLT = 11, + PCI1_CPLT = 12, + PCI2_CPLT = 13, + EQ_CPLT = 14, + EC_CPLT = 15, + SBE_NOOF_CHIPLETS = 16 } SbeTorId_t; typedef enum CmeTorId { @@ -230,8 +235,7 @@ int tor_get_ring( void* RingBlockType_t i_RingBlockType, // 0: single ring, 1: ring block void** io_ringBlockPtr, // Addr of ring buffer uint32_t& io_ringBlockSize, // size of ring data - char* o_ringName // Ring name - ); + char* o_ringName); // Ring name int tor_get_single_ring ( void* i_ringSectionPt, // Ring address Ptr any of .rings, .overrides and .overlays. @@ -253,8 +257,7 @@ int tor_get_block_of_rings ( void* RingVariant_t i_RingVariant, // base,cache,etc uint8_t i_instanceId, // Chiplet Instance ID void** io_ringBlockPtr, // Addr of ring buffer - uint32_t& io_ringBlockSize // size of ring data - ); + uint32_t& io_ringBlockSize); // size of ring data }; #endif //_P9_TOR_H_ |