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| author | Joe McGill <jmcgill@us.ibm.com> | 2016-10-12 15:23:48 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2016-10-12 21:29:44 -0400 |
| commit | e9f941c373abaef7a9a2a99022f3c1750ae3feb7 (patch) | |
| tree | abb4f0006765fafeb95810769f9ddfd14c14842f /src/import/chips/p9/procedures | |
| parent | b713730671a4bc7d43ed4ebfba1ab2295c4b9784 (diff) | |
| download | talos-sbe-e9f941c373abaef7a9a2a99022f3c1750ae3feb7.tar.gz talos-sbe-e9f941c373abaef7a9a2a99022f3c1750ae3feb7.zip | |
HW388878 VCS workaround
In pre-poweron HWP, Reset ROOT CTRL and PERV CTRL regs to cold IPL state
Tested with poweron flow which:
drops all rails (preserving Vstandby)
executes pre-poweron HWP to reset cfam region regs
enables rails (excluding VCS)
executes cfam pop start sequence
enables VCS rail
Add defect number to feature attribute, used in all consumer HWPs
Change-Id: I5bf5d61033bdca97527c8b499995eb6920ac1122
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31101
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31105
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures')
3 files changed, 5 insertions, 5 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C index 46dd119e..57413f0e 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_chiplet_reset.C @@ -232,7 +232,7 @@ p9_hcd_cache_chiplet_reset( #ifdef HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX FAPI_TRY(FAPI_ATTR_GET( - fapi2::ATTR_CHIP_EC_FEATURE_VCS_POWER_ON_IN_CHIPLET_RESET, + fapi2::ATTR_CHIP_EC_FEATURE_HW388878, l_chip, l_attr_dd1_vcs_workaround)); if (l_attr_dd1_vcs_workaround) diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C index 855e66ea..cb1d0f5d 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_poweron.C @@ -90,7 +90,7 @@ p9_hcd_cache_poweron( FAPI_DBG("Power on cache chiplet"); #ifdef HW388878_DD1_VCS_POWER_ON_IN_CHIPLET_RESET_FIX FAPI_TRY(FAPI_ATTR_GET( - fapi2::ATTR_CHIP_EC_FEATURE_VCS_POWER_ON_IN_CHIPLET_RESET, + fapi2::ATTR_CHIP_EC_FEATURE_HW388878, l_chip, l_attr_dd1_vcs_workaround)); if (l_attr_dd1_vcs_workaround) diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 88943072..00c3b239 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -183,11 +183,10 @@ </attribute> <!-- ******************************************************************** --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_VCS_POWER_ON_IN_CHIPLET_RESET</id> + <id>ATTR_CHIP_EC_FEATURE_HW388878</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - DD1 only: enable VCS workaround in istep4 cache hwp. This is used by - the procedure for p9_hcd_cache_poweron and p9_hcd_cache_chiplet_reset. + DD1 only: enable workarounds for HW388878 (VCS) </description> <chipEcFeature> <chip> @@ -199,4 +198,5 @@ </chip> </chipEcFeature> </attribute> + <!-- ******************************************************************** --> </attributes> |
