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| author | Alex Taft <amtaft@us.ibm.com> | 2017-02-21 16:29:48 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-02-24 07:26:17 -0500 |
| commit | d2d93b50b7a917710647585d905d3db00f8d59c0 (patch) | |
| tree | 1b5ed18b406ee23d6efe5516b5f5d68b7ec5b083 /src/import/chips/p9/procedures/xml | |
| parent | 4de52659849d6bdad1eb86bf30d0c7697e41dbbe (diff) | |
| download | talos-sbe-d2d93b50b7a917710647585d905d3db00f8d59c0.tar.gz talos-sbe-d2d93b50b7a917710647585d905d3db00f8d59c0.zip | |
New dummy pulse pok bits (for L2/L3)
CAY_L2C_A102_MAC & CAY_L3DIR_MAC
L2 cache and L3 Dir/Lru arrays.
Change-Id: Ib1912c9382a4cd5ce14488683b9b145a0f472d7b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36819
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36820
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index a1cf884b..c9d49a4d 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -1184,6 +1184,23 @@ </attribute> <!-- ******************************************************************** --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_L3_SRAM_RELAXED_SETTINGS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD1 only: SRAM relaced settings + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_HW369979</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -1306,6 +1323,23 @@ </attribute> <!-- ******************************************************************** --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_L2_DUMMY_PULSE_POK_BITS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + DD1 only: CAY_L2C_A102_MAC dummy pulse pok bits + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_HW374111</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> |
