diff options
| author | Louis Stermole <stermole@us.ibm.com> | 2017-02-08 10:27:10 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-02-21 23:25:37 -0500 |
| commit | 8bf6800166bcf60a86e9304a44cd01ebc53fa0e9 (patch) | |
| tree | 4e8d4069fefda62af9fece07d3db2ff34b00c675 /src/import/chips/p9/procedures/xml | |
| parent | c2d87fc372c41d5eab61006a6e9b97922fe56695 (diff) | |
| download | talos-sbe-8bf6800166bcf60a86e9304a44cd01ebc53fa0e9.tar.gz talos-sbe-8bf6800166bcf60a86e9304a44cd01ebc53fa0e9.zip | |
Add workaround for DDRPHY ODT config register erratum (ODT2, ODT3 bits swapped)
Change-Id: If02e5e31c768c62bbdf37c15b5146bacaaf38d80
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36173
Dev-Ready: Louis Stermole <stermole@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36192
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index c6a67e9a..04c7ce34 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -2304,6 +2304,25 @@ </attribute> <attribute> + <id>ATTR_CHIP_EC_FEATURE_MSS_ODT_CONFIG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + For Nimbus pre DD2.** we need to swap ODT2 and ODT3 values in the + DDRPHY_SEQ_ODT_RD/WR_CONFIG registers due to a PHY erratum. + Post DD2.** will have a hardware enabled fix for this (HW389360). + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + + <attribute> <id>ATTR_CHIP_EC_FEATURE_MSS_BLUE_WATERFALL_ADJUST</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -2354,6 +2373,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ******************************************************************** --> <!-- End Memory Section --> <!-- ******************************************************************** --> |
