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author | Nick Klazynski <jklazyns@us.ibm.com> | 2018-06-19 08:23:37 -0500 |
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committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-06-24 10:25:28 -0400 |
commit | 67f436de322f061a8e4140a736ef59acc256005f (patch) | |
tree | 144d136e29581c8ed7b1e3586200fb52be188776 /src/import/chips/p9/procedures/xml | |
parent | 02925f11e3e84adbace59896843330a72990a285 (diff) | |
download | talos-sbe-67f436de322f061a8e4140a736ef59acc256005f.tar.gz talos-sbe-67f436de322f061a8e4140a736ef59acc256005f.zip |
Add RL0/RL1 support for CDD1.2
Change-Id: I21d861481b9909ea024934e8b5830521d407c9a7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60873
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60884
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml')
-rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 39 |
1 files changed, 31 insertions, 8 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 3f4aa7af..58dfced8 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -240,11 +240,10 @@ </attribute> <!-- ********************************************************************* --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_HW430733</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <id>ATTR_CHIP_EC_FEATURE_FLUSH_L1D_TRIG</id> + <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> <description> - Nimbus DD2.2 - MTTRIG2 setup to flush L1D - - Always obey SW branch hint bits + MTTRIG2 setup to flush L1D </description> <chipEcFeature> <chip> @@ -254,6 +253,13 @@ <test>EQUAL</test> </ec> </chip> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x12</value> + <test>EQUAL</test> + </ec> + </chip> </chipEcFeature> </attribute> <!-- ********************************************************************* --> @@ -4658,10 +4664,10 @@ </attribute> <!-- ******************************************************************** --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_CDD11_SEC_MEM</id> + <id>ATTR_CHIP_EC_FEATURE_CORE_CDD11_SECURITY</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> - Secure memory setting for Cumulus DD1.1 + Security settings for Cumulus DD1.1 </description> <chipEcFeature> <chip> @@ -4675,10 +4681,27 @@ </attribute> <!-- ******************************************************************** --> <attribute> - <id>ATTR_CHIP_EC_FEATURE_CDD11_CDD12_SEC_MEM</id> + <id>ATTR_CHIP_EC_FEATURE_CORE_CDD12_SECURITY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Security settings for Cumulus DD1.2 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x12</value> + <test>EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_CORE_CDD11_CDD12_SECURITY</id> <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> <description> - Secure memory setting for Cumulus DD1.1 and DD1.2 + Security settings for Cumulus DD1.1 and DD1.2 </description> <chipEcFeature> <chip> |