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| author | Amit Tendolkar <amit.tendolkar@in.ibm.com> | 2017-12-07 04:11:46 -0600 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-12-11 03:11:12 -0500 |
| commit | be19efc55754acc7acb3203dd70e55a2cc2a2aee (patch) | |
| tree | ad543038700adf0bf373c9b40bfbabfc55219d01 /src/import/chips/p9/procedures/xml/error_info | |
| parent | c88c2c940231ab927b29eecb57733046d246f5fd (diff) | |
| download | talos-sbe-be19efc55754acc7acb3203dd70e55a2cc2a2aee.tar.gz talos-sbe-be19efc55754acc7acb3203dd70e55a2cc2a2aee.zip | |
Enhance SBE Deadman FFDC Format and sequencing
1. align data per FFDC member names
2. set the atomic lock FFDC so that errl parser works
3. collect sibling core data if in fused mode
4. do not collect ffdc on check_master_stop15 fails,
as SBE will do that upon a chip-op request
See https://ralgit01.raleigh.ibm.com/gerrit1/#/c/49473
for FW changes
Change-Id: I9880cdd3480c84c418b662fb7174291ed7b68cdd
RTC: 179364
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50648
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50653
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/error_info')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml | 24 |
1 files changed, 7 insertions, 17 deletions
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml index bc35618b..54043657 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml @@ -44,29 +44,15 @@ Indicates the targeted core is no longer pending entering a STOP state but the achieved level is not appropriate. </description> - <ffdc>CORE_TARGET</ffdc> - <ffdc>STOP_HISTORY</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>LVL_SUPPORT</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CORE_TARGET</target> - </deconfigure> </hwpError> <!-- ******************************************************************** --> <hwpError> <sbeError/> - <rc>RC_CHECK_MASTER_STOP15_FAILED</rc> + <rc>RC_CHECK_MASTER_STOP15_DEADMAN_TIMEOUT</rc> <description> - Indicates the targeted core(s) are no longer pending entering a STOP state - but the achieved level is not appropriate, or the deadman loop timed out. + SBE deadman timer fired with reason set in DEADMAN_TIMEOUT_REASON </description> - <ffdc>SBE_CHK_MASTER_STOP15_RC</ffdc> + <ffdc>DEADMAN_TIMEOUT_REASON</ffdc> <ffdc>CORE_TARGET</ffdc> <ffdc>PU_OCB_OCI_OCCFLG__PU_OCB_OCI_CCSR</ffdc> <ffdc>PU_OCB_OCI_QCSR__PU_OCB_OCI_QSSR</ffdc> @@ -84,6 +70,10 @@ <ffdc>CME_LR__SPRG0</ffdc> <ffdc>CME_SRR0__SRR1</ffdc> <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> <procedure>LVL_SUPPORT</procedure> <priority>LOW</priority> </callout> |
