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| author | Joe McGill <jmcgill@us.ibm.com> | 2017-07-09 14:00:53 -0500 |
|---|---|---|
| committer | spashabk-in <shakeebbk@in.ibm.com> | 2017-09-12 00:18:18 -0500 |
| commit | db0336533babbab87922eee17fa08366db3a6577 (patch) | |
| tree | 4cfc51227de134eb806e0fa3d351eace2f73458d /src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | |
| parent | cd6f911a776fefed9b065312d7fef0339e404846 (diff) | |
| download | talos-sbe-db0336533babbab87922eee17fa08366db3a6577.tar.gz talos-sbe-db0336533babbab87922eee17fa08366db3a6577.zip | |
p9.npu.scom.initfile -- FIR updates to align with RAS XML documentation
create feature attribute to qualify FIR2 inits
update FIR2 XML,inits based on current review feedback
Change-Id: Ib105de1f106ab5bd14684b688c3d2a1b17121d16
Original-Change-Id: I8a1a8a92e4f4ee24b308f0bb731a953f098edc72
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42910
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml')
| -rw-r--r-- | src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index a38819e3..32925e4c 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -3893,6 +3893,24 @@ <!-- ******************************************************************** --> <!-- End Memory Section --> <!-- ******************************************************************** --> + + <attribute> + <id>ATTR_CHIP_EC_FEATURE_DISABLE_NPU_FREEZE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + True if NPU freeze (unit checkstop) should be disabled + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> <id>ATTR_CHIP_EC_FEATURE_NOT_HW399276</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> @@ -4080,6 +4098,23 @@ </chipEcFeature> </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_NO_NPU2_FIR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD1 only: NPU2 FIR not present + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> <attribute> <id>ATTR_CHIP_EC_FEATURE_HW399466</id> |
