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authorJoe McGill <jmcgill@us.ibm.com>2017-06-08 11:45:40 -0500
committerSachin Gupta <sgupta2m@in.ibm.com>2017-08-07 04:29:06 -0400
commitefe5cb3abc1e91eab68d8c94072a16500a3ce3f5 (patch)
treeb5015efc5f4efa2ebeb81eb616e5b8f9a92f0e53 /src/import/chips/p9/procedures/hwp
parent98da28dcc3babbe2591ba1852b48026b3f419d11 (diff)
downloadtalos-sbe-efe5cb3abc1e91eab68d8c94072a16500a3ce3f5.tar.gz
talos-sbe-efe5cb3abc1e91eab68d8c94072a16500a3ce3f5.zip
L3 update -- p9_sbe_load_bootloader
Change-Id: Ia0cb15dc2f6d8dfcfc8e9696a2878fce6a01ccbb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42673 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Martin Gloff <mgloff@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42677 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H41
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C812
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H64
3 files changed, 558 insertions, 359 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
index d82448e9..3380044a 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_hb_structures.H
@@ -22,32 +22,24 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
-//------------------------------------------------------------------------------------
-//
+
+///
/// @file p9_sbe_hb_structures.H
-/// @brief Structures that the SBE and HB will both use
-//
-// *HWP HWP Owner: Joshua Hannan jlhannan@us.ibm.com
+/// @brief Structures shared between SBE/HB code
+///
+
+// *HWP HWP Owner: Joe McGill jmcgill@us.ibm.com
// *HWP FW Owner: Thi Tran thi@us.ibm.com
// *HWP Team: Nest
// *HWP Level: 3
// *HWP Consumed by: SBE, HB
-//-----------------------------------------------------------------------------------
#ifndef _SBE_HB_STRUCTURES_H_
#define _SBE_HB_STRUCTURES_H_
-//-----------------------------------------------------------------------------------
-// Includes
-//-----------------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
// Structure definitions
-//-----------------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------------
-// Constant definitions
-//-----------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
// Used for version checking as the BootloaderConfigData_t structure changes
enum SbeBootloaderVersion
@@ -78,16 +70,19 @@ union BootloaderSecureSettings
// maintain compatibility with Hostboot
struct BootloaderConfigData_t
{
- uint32_t version; // bytes 4:7 Version field so we know if there is new data being added
- uint8_t sbeBootSide; // byte 8 0=SBE side 0, 1=SBE side 1 [ATTR_SBE_BOOT_SIDE]
- uint8_t pnorBootSide; // byte 9 0=PNOR side A, 1=PNOR side B [ATTR_PNOR_BOOT_SIDE]
- uint16_t pnorSizeMB; // bytes 10:11 Size of PNOR in MB [ATTR_PNOR_SIZE]
- uint64_t blLoadSize; // bytes 12:19 Size of Load (Exception vectors and Bootloader)
+ uint32_t version; // bytes 4:7 Version identifier
+ uint8_t sbeBootSide; // byte 8 0=SBE side 0, 1=SBE side 1
+ // [ATTR_SBE_BOOT_SIDE]
+ uint8_t pnorBootSide; // byte 9 0=PNOR side A, 1=PNOR side B
+ // [ATTR_PNOR_BOOT_SIDE]
+ uint16_t pnorSizeMB; // bytes 10:11 Size of PNOR in MB
+ // [ATTR_PNOR_SIZE]
+ uint64_t blLoadSize; // bytes 12:19 Size of Load
+ // Exception vectors and Bootloader
BootloaderSecureSettings secureSettings ; // byte 20
uint8_t reserved[7]; // bytes 21:27 Reserved space to maintain 64-bit alignment
uint64_t xscomBAR; // bytes 28:35 XSCOM MMIO BAR
uint64_t lpcBAR; // bytes 36:43 LPC MMIO BAR
}; // Note: Want to use '__attribute__((packed))' but compiler won't let us
-
-#endif
+#endif // _SBE_HB_STRUCTURES_H_
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C
index c2dc9e95..4e0afc86 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C
@@ -22,116 +22,286 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
-//--------------------------------------------------------------------------
-//
-// @file p9_sbe_load_bootloader.C
-// @brief Shift HB bootloader payload from SEEPROM to L3 cache of master core via PBA
-//
-// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
-// *HWP HWP Writer: Murey A Luna Torres malunato@us.ibm.com, Joseph McGill jmcgill@us.ibm.com
+
+///
+/// @file p9_sbe_load_bootloader.C
+/// @brief Shift HB bootloader payload from SEEPROM to L3 cache of master core
+/// via PBA
+///
+
+// *HWP HWP Owner: Joe McGill jmcgill@us.ibm.com
// *HWP FW Owner: Thi Tran thi@us.ibm.com
// *HWP Team: Nest
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: SBE
-//
-//--------------------------------------------------------------------------
-//--------------------------------------------------------------------------
+//------------------------------------------------------------------------------
// Includes
-//--------------------------------------------------------------------------
+//------------------------------------------------------------------------------
#include <p9_sbe_load_bootloader.H>
+#include <p9_sbe_hb_structures.H>
+
+#include <p9_quad_scom_addresses.H>
+#include <p9_quad_scom_addresses_fld.H>
+#include <p9_perv_scom_addresses.H>
+#include <p9_perv_scom_addresses_fld.H>
+
#include <p9_pba_setup.H>
#include <p9_pba_access.H>
-#include <p9_fbc_utils.H>
#include <p9_pba_coherent_utils.H>
-#include <p9_quad_scom_addresses.H>
-#include <p9_quad_scom_addresses_fld.H>
+#include <p9_fbc_utils.H>
#include <p9_ram_core.H>
-#include <p9_perv_scom_addresses.H>
-//-----------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+// Macro definitions
+//------------------------------------------------------------------------------
+#define PACK_1B(ARR,INDEX,VAL) \
+ { \
+ ARR[INDEX++] = VAL & 0xFFULL; \
+ }
+#define PACK_2B(ARR,INDEX,VAL) \
+ { \
+ ARR[INDEX++] = (VAL >> 8) & 0xFFULL; \
+ ARR[INDEX++] = VAL & 0xFFULL; \
+ }
+#define PACK_4B(ARR,INDEX,VAL) \
+ { \
+ ARR[INDEX++] = (VAL >> 24) & 0xFFULL; \
+ ARR[INDEX++] = (VAL >> 16) & 0xFFULL; \
+ ARR[INDEX++] = (VAL >> 8) & 0xFFULL; \
+ ARR[INDEX++] = VAL & 0xFFULL; \
+ }
+#define PACK_8B(ARR,INDEX,VAL) \
+ { \
+ ARR[INDEX++] = (VAL >> 56) & 0xFFULL; \
+ ARR[INDEX++] = (VAL >> 48) & 0xFFULL; \
+ ARR[INDEX++] = (VAL >> 40) & 0xFFULL; \
+ ARR[INDEX++] = (VAL >> 32) & 0xFFULL; \
+ ARR[INDEX++] = (VAL >> 24) & 0xFFULL; \
+ ARR[INDEX++] = (VAL >> 16) & 0xFFULL; \
+ ARR[INDEX++] = (VAL >> 8) & 0xFFULL; \
+ ARR[INDEX++] = VAL & 0xFFULL; \
+ }
+
+//------------------------------------------------------------------------------
// Constant definitions
-//-----------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+
+// Execption vector constant definitions
+const uint32_t EXCEPTION_VECTOR_SIZE = 12 * 1024; // 12KB
+const uint32_t EXCEPTION_VECTOR_NUM_CACHELINES = EXCEPTION_VECTOR_SIZE /
+ FABRIC_CACHELINE_SIZE;
+// PPC branch instruction inserted into first address of exception vector,
+// used to jump over entirety of exception vector storage
+const uint32_t EXCEPTION_VECTOR_BRANCH = 0x48000000 |
+ EXCEPTION_VECTOR_SIZE;
// PBA setup/access HWP call constants
const bool PBA_HWP_WRITE_OP = false;
-const int EXCEPTION_VECTOR_NUM_CACHELINES = 96;
+
+// static offset between:
+// Core unit target positions 0..23 and their associated
+// Perv unit target positions 32..55
const uint8_t PERV_TO_CORE_POS_OFFSET = 0x20;
-//-----------------------------------------------------------------------------------
-// Function definitions
-//-----------------------------------------------------------------------------------
+// RAM constants
+const uint8_t THREAD_2 = 2;
+const uint8_t THREAD_3 = 3;
+const uint32_t HRMOR_SPR_NUMBER = 313;
+const uint32_t PSSCR_SPR_NUMBER = 855;
+const uint64_t HOSTBOOT_PSSCR_VALUE = 0x00000000003F00FFULL;
-fapi2::ReturnCode p9_sbe_load_bootloader(
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+///
+/// @brief Program SPRs via RAM prior to instructions tart
+///
+/// @param[in] i_master_chip_target Reference to processor chip target
+/// @param[in] i_master_ex_target Reference to EX unit target which is the
+/// parent of the master core(s)
+/// @param[in] i_master_hrmor HRMOR value for master normal core
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode
+ram_sprs(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_master_chip_target,
const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_master_ex_target,
- const uint64_t i_payload_size,
- uint8_t* i_payload_data)
+ const uint64_t i_master_hrmor)
{
- const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
- //the branching instruction for 12KB past where it currently is (1024 * 12 = 12288 = 0x3000)
- //The branch instruction is 0100 10_address to branch to_ 0 0
- // 0 6 29 30 31
- //bit 30 is for absolute address (since it is not set this is relative)
- const uint32_t l_branch_to_12 = 0x48003000ull;
- const uint32_t C_0_THREAD_INFO_RAM_THREAD_ACTIVE_T2 = 20;
- const uint32_t C_0_THREAD_INFO_RAM_THREAD_ACTIVE_T3 = 21;
- const uint64_t HOSTBOOT_PSSCR_VALUE = 0x00000000003F00FF;
+ fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+ std::vector<fapi2::Target<fapi2::TARGET_TYPE_CORE>> l_master_core_targets;
+ uint8_t l_fused_core_mode;
uint64_t l_bootloader_offset;
- uint64_t l_hostboot_hrmor_offset;
- uint64_t l_drawer_base_address_nm0, l_drawer_base_address_nm1;
- uint64_t l_drawer_base_address_m;
- uint64_t l_drawer_base_address_mmio;
- uint64_t l_chip_base_address_nm0, l_chip_base_address_nm1;
- uint64_t l_chip_base_address_m;
- uint64_t l_chip_base_address_mmio;
- uint64_t l_target_address;
- uint32_t l_exception_instruction;
- bool l_firstAccess = true;
- uint32_t l_num_cachelines_to_roll;
- uint8_t l_data_to_pass_to_pba_array[FABRIC_CACHELINE_SIZE];
- uint32_t l_exception_vector_size = 0;
- uint8_t l_master_core = 0;
- int l_cacheline_num = 0;
- uint8_t l_is_mpipl = 0x0;
- p9_PBA_oper_flag l_myPbaFlag;
- fapi2::buffer<uint64_t> l_dataBuf;
- fapi2::Target<fapi2::TARGET_TYPE_CORE> l_coreTarget;
- bool l_coreFoundMatch = false;
+ bool l_master_core_found = false;
+ uint8_t l_master_core_unit_pos = 0;
FAPI_DBG("Start");
- //Find the master core for writing the HRMOR later
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MASTER_CORE, i_master_chip_target, l_master_core), "Error getting ATTR_MASTER_CORE");
+ // determine fused core status
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FUSED_CORE_MODE,
+ FAPI_SYSTEM,
+ l_fused_core_mode),
+ "Error from FAPI_ATTR_GET (ATTR_FUSED_CORE_MODE)");
+
+ // retrieve master core target position (0..23) index via attribute query
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MASTER_CORE,
+ i_master_chip_target,
+ l_master_core_unit_pos),
+ "Error from FAPI_ATTR_GET (ATTR_MASTER_CORE)!");
+
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_BOOTLOADER_OFFSET,
+ FAPI_SYSTEM,
+ l_bootloader_offset),
+ "Error from FAPI_ATTR_GET (ATTR_SBE_BOOTLOADER_OFFSET)");
+
+ for (auto& l_core : i_master_ex_target.getChildren<fapi2::TARGET_TYPE_CORE>())
+ {
+ if (l_fused_core_mode)
+ {
+ l_master_core_targets.push_back(l_core);
+ l_master_core_found = true;
+ }
+ else
+ {
+ // use this to find the master core target, needed for RAM operation
+ // - traverse the children of the master EX target we are passed, and look
+ // for a matching position (via its PERV target parent)
+ // - without modifications to the HWP prototype this is the most efficient
+ // solution possible given SBE FAPI platform support
+ {
+ auto l_perv = l_core.getParent<fapi2::TARGET_TYPE_PERV>();
+ uint8_t l_perv_unit_pos = 0;
+
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,
+ l_perv,
+ l_perv_unit_pos),
+ "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)!");
+
+ // PERV target positions for cores 0..23 are 32:57, compare using
+ // static offset
+ if (l_master_core_unit_pos ==
+ (l_perv_unit_pos - PERV_TO_CORE_POS_OFFSET))
+ {
+ l_master_core_targets.push_back(l_core);
+ l_master_core_found = true;
+ break;
+ }
+ }
+ }
+ }
- for ( auto& l_current_core : i_master_ex_target.getChildren<fapi2::TARGET_TYPE_CORE>())
+ // if target is not found, raise an error
+ FAPI_ASSERT(l_master_core_found,
+ fapi2::P9_MASTER_CORE_NOT_FOUND()
+ .set_CHIP_TARGET(i_master_chip_target)
+ .set_EX_TARGET(i_master_ex_target)
+ .set_MASTER_CORE_UNIT_POS(l_master_core_unit_pos)
+ .set_FUSED_MODE(l_fused_core_mode),
+ "Error finding the master core target!");
+
+ // set the HRMOR (core) and PSSCR (threads 2/3). The PSSCR must be
+ // set on these threads as in fused mode HB will never execute on them,
+ // but CME checks bits in them to perform STOP11 request in step 16
+ for (auto& l_master_core_target : l_master_core_targets)
{
- uint8_t l_attr_chip_unit_pos = 0;
- fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv = l_current_core.getParent<fapi2::TARGET_TYPE_PERV>();
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, l_attr_chip_unit_pos),
- "Error getting ATTR_CHIP_UNIT_POS");
- l_attr_chip_unit_pos = l_attr_chip_unit_pos - PERV_TO_CORE_POS_OFFSET;
- FAPI_DBG("l_attr_chip_unit_pos = %d, l_attr_chip_unit_pos = %d, l_master_core = %d", l_attr_chip_unit_pos,
- l_attr_chip_unit_pos, l_master_core);
-
- if (l_attr_chip_unit_pos == l_master_core)
+ RamCore l_ram_t2(l_master_core_target, THREAD_2);
+ RamCore l_ram_t3(l_master_core_target, THREAD_3);
+ fapi2::buffer<uint64_t> l_sicr = 0;
+ fapi2::buffer<uint64_t> l_thread_info = 0;
+ fapi2::buffer<uint64_t> l_ram_data = i_master_hrmor;
+ uint8_t l_core_unit_pos = 0;
+
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS,
+ l_master_core_target,
+ l_core_unit_pos),
+ "Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)!");
+
+ // override to PM_EXIT is required to RAM given current core
+ // state -- set appropriate bit in parent EX SICR register
+ if (!(l_core_unit_pos % 2))
{
- l_coreTarget = l_current_core;
- l_coreFoundMatch = true;
- break;
+ l_sicr.setBit<EQ_CME_SCOM_SICR_PM_EXIT_C0>();
}
+ else
+ {
+ l_sicr.setBit<EQ_CME_SCOM_SICR_PM_EXIT_C1>();
+ }
+
+ FAPI_TRY(fapi2::putScom(i_master_ex_target,
+ EX_0_CME_SCOM_SICR_SCOM2,
+ l_sicr),
+ "Error from putScom (EX_0_CME_SCOM_SICR_SCOM2)!");
+
+ // override to PC state is required to RAM given current
+ // core state -- set RAM_THREAD_ACTIVE
+ l_thread_info.setBit < C_THREAD_INFO_RAM_THREAD_ACTIVE + THREAD_2 > ();
+ l_thread_info.setBit < C_THREAD_INFO_RAM_THREAD_ACTIVE + THREAD_3 > ();
+ FAPI_TRY(fapi2::putScom(l_master_core_target,
+ C_0_THREAD_INFO,
+ l_thread_info),
+ "Error from putScom (C_0_THREAD_INFO)!");
+
+ // call put_reg method to perform RAM operation
+ if (l_core_unit_pos != l_master_core_unit_pos)
+ {
+ l_ram_data -= l_bootloader_offset;
+ }
+
+ // set HRMOR via thread 2 instance -- core level SPR
+ FAPI_TRY(l_ram_t2.put_reg(REG_SPR, HRMOR_SPR_NUMBER, &l_ram_data),
+ "Error ramming HRMOR (T2)!");
+ // set PSSCR via thread specific instances
+ l_ram_data = HOSTBOOT_PSSCR_VALUE;
+ FAPI_TRY(l_ram_t2.put_reg(REG_SPR, PSSCR_SPR_NUMBER, &l_ram_data),
+ "Error ramming PSSCR (T2)!");
+ FAPI_TRY(l_ram_t3.put_reg(REG_SPR, PSSCR_SPR_NUMBER, &l_ram_data),
+ "Error ramming PSSCR (T3)!");
}
- FAPI_ASSERT(l_coreFoundMatch, fapi2::P9_MASTER_CORE_NOT_FOUND().set_CHIP_TARGET(i_master_chip_target).set_EX_TARGET(
- i_master_ex_target).set_MASTER_CORE(l_master_core) , "Error in finding the master core");
+fapi_try_exit:
+ FAPI_DBG("End");
+ return fapi2::current_err;
+}
- // read platform initialized attributes needed to determine target base address
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_BOOTLOADER_OFFSET, FAPI_SYSTEM, l_bootloader_offset),
- "Error from FAPI_ATTR_GET (ATTR_SBE_BOOTLOADER_OFFSET)");
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HOSTBOOT_HRMOR_OFFSET, FAPI_SYSTEM, l_hostboot_hrmor_offset),
- "Error from FAPI_ATTR_GET (ATTR_HOSTBOOT_HRMOR_OFFSET)");
+///
+/// @brief Read attributes, determine final image footprint (base address/size)
+///
+/// @param[in] i_master_chip_target Reference to processor chip target
+/// @param[in] i_master_ex_target Reference to EX unit target which is the
+/// parent of the master core
+/// @param[in] i_payload_size Size of image payload, in B
+/// @param[out] o_load_base_address Base real address for bootloader load
+/// @param[out] o_load_size Size of complete bootloader payload
+/// @param[out] o_load_exception_vector Bootloader payload includes
+/// exception vector table?
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode
+calc_image_footprint(
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_master_chip_target,
+ const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_master_ex_target,
+ const uint64_t i_payload_size,
+ uint64_t& o_load_base_address,
+ uint64_t& o_load_size,
+ bool& o_load_exception_vector)
+{
+ const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+ uint64_t l_drawer_base_address_nm0;
+ uint64_t l_drawer_base_address_nm1;
+ uint64_t l_drawer_base_address_m;
+ uint64_t l_drawer_base_address_mmio;
+ uint64_t l_bootloader_offset;
+ uint64_t l_hostboot_hrmor_offset;
+ uint32_t l_exception_instruction;
+
+ FAPI_DBG("Start");
+ // read platform initialized attributes needed to determine target
+ // base address for bootloader image load
+ //
// target base address = (drawer non-mirrored base address) +
// (hostboot HRMOR offset) +
// (bootloader offset)
@@ -143,13 +313,15 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
l_drawer_base_address_mmio),
"Error from p9_fbc_utils_get_chip_base_address (drawer)");
- FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_master_chip_target,
- EFF_FBC_GRP_CHIP_IDS,
- l_chip_base_address_nm0,
- l_chip_base_address_nm1,
- l_chip_base_address_m,
- l_chip_base_address_mmio),
- "Error from p9_fbc_utils_get_chip_base_address (chip)");
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_HOSTBOOT_HRMOR_OFFSET,
+ FAPI_SYSTEM,
+ l_hostboot_hrmor_offset),
+ "Error from FAPI_ATTR_GET (ATTR_HOSTBOOT_HRMOR_OFFSET)");
+
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_BOOTLOADER_OFFSET,
+ FAPI_SYSTEM,
+ l_bootloader_offset),
+ "Error from FAPI_ATTR_GET (ATTR_SBE_BOOTLOADER_OFFSET)");
// add hostboot HRMOR offset and bootloader offset contributions
l_drawer_base_address_nm0 += l_hostboot_hrmor_offset;
@@ -157,276 +329,322 @@ fapi2::ReturnCode p9_sbe_load_bootloader(
// check that base address is cacheline aligned
FAPI_ASSERT(!(l_drawer_base_address_nm0 % FABRIC_CACHELINE_SIZE),
- fapi2::P9_SBE_LOAD_BOOTLOADER_INVALID_TARGET_ADDRESS().
- set_CHIP_TARGET(i_master_chip_target).
- set_EX_TARGET(i_master_ex_target).
- set_TARGET_BASE_ADDRESS(l_drawer_base_address_nm0).
- set_HRMOR_OFFSET(l_hostboot_hrmor_offset).
- set_BOOTLOADER_OFFSET(l_bootloader_offset),
+ fapi2::P9_SBE_LOAD_BOOTLOADER_INVALID_TARGET_ADDRESS()
+ .set_CHIP_TARGET(i_master_chip_target)
+ .set_EX_TARGET(i_master_ex_target)
+ .set_TARGET_BASE_ADDRESS(l_drawer_base_address_nm0)
+ .set_HRMOR_OFFSET(l_hostboot_hrmor_offset)
+ .set_BOOTLOADER_OFFSET(l_bootloader_offset),
"Target base address is not cacheline aligned!");
- //Check to see if we need to populate the exception vectors
- //Check the SBE_HBBL_EXCEPTION_INSTRUCT attribute
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_HBBL_EXCEPTION_INSTRUCT, FAPI_SYSTEM, l_exception_instruction),
- "fapiGetAttribute of ATTR_SBE_HBBL_EXCEPTION_INSTRUCT failed!");
+ // read attribute to determine if we should populate the exception vectors
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_HBBL_EXCEPTION_INSTRUCT,
+ FAPI_SYSTEM,
+ l_exception_instruction),
+ "Error from FAPI_ATTR_GET (ATTR_SBE_HBBL_EXCEPTION_INSTRUCT)");
- l_target_address = l_drawer_base_address_nm0;
+ o_load_base_address = l_drawer_base_address_nm0;
+ o_load_size = i_payload_size;
+ o_load_exception_vector = false;
+ if (l_exception_instruction != 0)
+ {
+ o_load_exception_vector = true;
+ o_load_size += EXCEPTION_VECTOR_SIZE;
+ }
+
+ // check that the final load size is non-zero and evenly divisible
+ // into cachelines
+ FAPI_ASSERT(o_load_size && !(o_load_size % FABRIC_CACHELINE_SIZE),
+ fapi2::P9_SBE_LOAD_BOOTLOADER_INVALID_PAYLOAD_SIZE()
+ .set_CHIP_TARGET(i_master_chip_target)
+ .set_EX_TARGET(i_master_ex_target)
+ .set_PAYLOAD_SIZE(o_load_size),
+ "Payload size is invalid!");
+
+fapi_try_exit:
+ FAPI_DBG("End");
+ return fapi2::current_err;
+}
+
+
+///
+/// @brief Determine data to load for cacheline containing bootloader
+/// configuration structure data
+///
+/// @param[in] i_master_chip_target Reference to processor chip target
+/// @param[in] i_load_size Size of complete bootloader payload
+/// @param[inout] io_data Pointer to cacheline buffer to fill
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode
+get_bootloader_config_data(
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_master_chip_target,
+ const uint64_t i_load_size,
+ uint8_t* io_data)
+{
+ const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+ uint64_t l_chip_base_address_nm0;
+ uint64_t l_chip_base_address_nm1;
+ uint64_t l_chip_base_address_m;
+ uint64_t l_chip_base_address_mmio;
+ uint64_t l_index = 0;
+ fapi2::buffer<uint64_t> l_cbs_cs;
BootloaderConfigData_t l_bootloader_config_data;
+ FAPI_DBG("Start");
+
+ // read platform initialized attributes to determine struct content
+ FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_master_chip_target,
+ EFF_FBC_GRP_CHIP_IDS,
+ l_chip_base_address_nm0,
+ l_chip_base_address_nm1,
+ l_chip_base_address_m,
+ l_chip_base_address_mmio),
+ "Error from p9_fbc_utils_get_chip_base_address (chip)");
+
l_bootloader_config_data.version = MMIO_BARS_ADDED;
- //At address X + 0x8 put whatever is in ATTR_SBE_BOOT_SIDE
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_BOOT_SIDE, FAPI_SYSTEM, l_bootloader_config_data.sbeBootSide),
- "fapiGetAttribute of ATTR_SBE_BOOT_SIDE failed!");
+ // XSCOM BAR offset
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET,
+ FAPI_SYSTEM,
+ l_bootloader_config_data.xscomBAR),
+ "Error from FAPI_ATTR_GET (ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET)");
+ l_bootloader_config_data.xscomBAR += l_chip_base_address_mmio;
- //At address X + 0x9 put whatever is in ATTR_PNOR_BOOT_SIDE
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PNOR_BOOT_SIDE, FAPI_SYSTEM, l_bootloader_config_data.pnorBootSide),
- "fapiGetAttribute of ATTR_PNOR_BOOT_SIDE failed!");
+ // LPC BAR offset
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET,
+ FAPI_SYSTEM,
+ l_bootloader_config_data.lpcBAR),
+ "Error from FAPI_ATTR_GET (ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET)");
+ l_bootloader_config_data.lpcBAR += l_chip_base_address_mmio;
- //At address X + 0xA put whatever is in ATTR_PNOR_SIZE
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PNOR_SIZE, FAPI_SYSTEM, l_bootloader_config_data.pnorSizeMB),
- "fapiGetAttribute of ATTR_PNOR_SIZE failed!");
+ // SBE boot side
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_BOOT_SIDE,
+ FAPI_SYSTEM,
+ l_bootloader_config_data.sbeBootSide),
+ "Error from FAPI_ATTR_GET (ATTR_SBE_BOOT_SIDE)");
- // check that the payload size is non-zero and evenly divisible into cachelines
- FAPI_ASSERT(i_payload_size && !(i_payload_size % FABRIC_CACHELINE_SIZE),
- fapi2::P9_SBE_LOAD_BOOTLOADER_INVALID_PAYLOAD_SIZE().
- set_CHIP_TARGET(i_master_chip_target).
- set_EX_TARGET(i_master_ex_target).
- set_PAYLOAD_SIZE(i_payload_size),
- "Payload size is invalid!");
+ // PNOR boot side
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PNOR_BOOT_SIDE,
+ FAPI_SYSTEM,
+ l_bootloader_config_data.pnorBootSide),
+ "Error from FAPI_ATTR_GET (ATTR_PNOR_BOOT_SIDE)");
- // adjust exception vector size
- if (l_exception_instruction != 0x0)
- {
- l_exception_vector_size = EXCEPTION_VECTOR_NUM_CACHELINES * FABRIC_CACHELINE_SIZE;
- }
+ // PNOR size
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PNOR_SIZE,
+ FAPI_SYSTEM,
+ l_bootloader_config_data.pnorSizeMB),
+ "Error from FAPI_ATTR_GET (ATTR_PNOR_SIZE)");
- // Pass size of load including exception vectors and Bootloader
- l_bootloader_config_data.blLoadSize = l_exception_vector_size + i_payload_size;
+ // pass size of load including exception vectors and bootloader
+ l_bootloader_config_data.blLoadSize = i_load_size;
// Set Secure Settings Byte
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SECURE_SETTINGS, FAPI_SYSTEM, l_bootloader_config_data.secureSettings.data8));
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SECURE_SETTINGS,
+ FAPI_SYSTEM,
+ l_bootloader_config_data.secureSettings.data8),
+ "Error from FAPI_ATTR_GET (ATTR_SECURE_SETTINGS)");
+
+ // re-read Secure Access Bit in case it's changed
+ FAPI_TRY(fapi2::getScom(i_master_chip_target,
+ PERV_CBS_CS_SCOM,
+ l_cbs_cs),
+ "Error from getScom (PERV_CBS_CS_SCOM)");
+ l_bootloader_config_data.secureSettings.secureAccessBit =
+ (l_cbs_cs.getBit<PERV_CBS_CS_SECURE_ACCESS_BIT>()) ? (1) : (0);
+
+ // initialize cacheline storage
+ PACK_4B(io_data, l_index, EXCEPTION_VECTOR_BRANCH);
+ PACK_4B(io_data, l_index, l_bootloader_config_data.version);
+ PACK_1B(io_data, l_index, l_bootloader_config_data.sbeBootSide);
+ PACK_1B(io_data, l_index, l_bootloader_config_data.pnorBootSide);
+ PACK_2B(io_data, l_index, l_bootloader_config_data.pnorSizeMB);
+ PACK_8B(io_data, l_index, l_bootloader_config_data.blLoadSize);
+ PACK_1B(io_data, l_index, l_bootloader_config_data.secureSettings.data8);
+ PACK_1B(io_data, l_index, 0x0);
+ PACK_2B(io_data, l_index, 0x0);
+ PACK_4B(io_data, l_index, 0x0);
+ PACK_8B(io_data, l_index, l_bootloader_config_data.xscomBAR);
+ PACK_8B(io_data, l_index, l_bootloader_config_data.lpcBAR);
+
+fapi_try_exit:
+ FAPI_DBG("End");
+ return fapi2::current_err;
+}
- // -- re-read Secure Access Bit in case it's changed
- FAPI_TRY(fapi2::getScom(i_master_chip_target, PERV_CBS_CS_SCOM, l_dataBuf));
- l_bootloader_config_data.secureSettings.secureAccessBit = l_dataBuf.getBit<4>() ? 1 : 0;
- l_dataBuf.flush<0>();
+///
+/// @brief Determine data to load for cacheline containing exception
+/// vector content
+///
+/// @param[inout] io_data Pointer to cacheline buffer to fill
+/// @return fapi::ReturnCode. FAPI2_RC_SUCCESS if success, else error code.
+///
+fapi2::ReturnCode
+get_exception_vector_data(
+ uint8_t* io_data)
+{
+ uint8_t l_index = 0;
+ uint32_t l_exception_instruction;
- // fill in MMIO BARs
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET, FAPI_SYSTEM, l_bootloader_config_data.xscomBAR),
- "Error from FAPI_ATTR_GET (ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET)");
- l_bootloader_config_data.xscomBAR += l_chip_base_address_mmio;
+ FAPI_DBG("Start");
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET, FAPI_SYSTEM, l_bootloader_config_data.lpcBAR),
- "Error from FAPI_ATTR_GET (ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET)");
- l_bootloader_config_data.lpcBAR += l_chip_base_address_mmio;
+ // read attribute to determine if we should populate the exception vectors
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SBE_HBBL_EXCEPTION_INSTRUCT,
+ fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+ l_exception_instruction),
+ "Error from FAPI_ATTR_GET (ATTR_SBE_HBBL_EXCEPTION_INSTRUCT)");
- // move data using PBA setup/access HWPs
- l_myPbaFlag.setFastMode(true); // FASTMODE
+ while (l_index < FABRIC_CACHELINE_SIZE)
+ {
+ PACK_4B(io_data, l_index, l_exception_instruction);
+ }
+
+fapi_try_exit:
+ FAPI_DBG("End");
+ return fapi2::current_err;
+}
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL, FAPI_SYSTEM, l_is_mpipl), "fapiGetAttribute of ATTR_IS_MPIPL failed!");
- if (!l_is_mpipl)
+// HWP entry point, description in header
+fapi2::ReturnCode p9_sbe_load_bootloader(
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_master_chip_target,
+ const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_master_ex_target,
+ const uint64_t i_payload_size,
+ uint8_t* i_payload_data)
+{
+ bool l_first_access = true;
+ uint32_t l_num_cachelines_to_roll;
+ uint32_t l_cacheline_num = 0;
+ uint8_t l_is_mpipl = 0x0;
+ p9_PBA_oper_flag l_pba_flags;
+ uint8_t l_data[FABRIC_CACHELINE_SIZE];
+ uint64_t l_target_address;
+ uint64_t l_end_address;
+ uint64_t l_load_base_address;
+ uint64_t l_load_size;
+ bool l_load_exception_vector;
+
+ FAPI_DBG("Start");
+
+ // set PBA flags which control load operation
+ FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_MPIPL,
+ fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+ l_is_mpipl),
+ "Error from FAPI_ATTR_GET (ATTR_IS_MPIPL)!");
+
+ // set the PBA operation type (ttype) based on the IPL type:
+ // - MPIPL: install the payload into memory via DMA ttype
+ // - non-MPIPL: install the payload directly into the target L3 cache, via
+ // LCO (lateral castout)
+ if (l_is_mpipl)
{
- l_myPbaFlag.setOperationType(p9_PBA_oper_flag::LCO); // LCO operation
+ l_pba_flags.setOperationType(p9_PBA_oper_flag::DMA);
}
else
{
- l_myPbaFlag.setOperationType(p9_PBA_oper_flag::DMA); // DMA operation
+ l_pba_flags.setOperationType(p9_PBA_oper_flag::LCO);
}
- while (l_target_address < (l_drawer_base_address_nm0 + i_payload_size + l_exception_vector_size))
- {
- // invoke PBA setup HWP to prep stream
- FAPI_TRY(p9_pba_setup( i_master_chip_target,
- i_master_ex_target,
- l_target_address,
- PBA_HWP_WRITE_OP,
- l_myPbaFlag.setFlag(),
- l_num_cachelines_to_roll), "Error from p9_pba_setup");
+ l_pba_flags.setFastMode(true);
+
+ // calculate base address/size for image load
+ // also, determine if FW specific exception vector will be installed
+ FAPI_TRY(calc_image_footprint(i_master_chip_target,
+ i_master_ex_target,
+ i_payload_size,
+ l_load_base_address,
+ l_load_size,
+ l_load_exception_vector),
+ "Error from calc_image_footprint");
+
+ l_target_address = l_load_base_address;
+ l_end_address = l_load_base_address + l_load_size;
- l_firstAccess = true;
+ while (l_target_address < l_end_address)
+ {
+ // invoke PBA setup HWP to prepare current stream of contiguous
+ // cachelines
+ FAPI_TRY(p9_pba_setup(i_master_chip_target,
+ i_master_ex_target,
+ l_target_address,
+ PBA_HWP_WRITE_OP,
+ l_pba_flags.setFlag(),
+ l_num_cachelines_to_roll),
+ "Error from p9_pba_setup");
+
+ l_first_access = true;
// call PBA access HWP per cacheline to move payload data
- while (l_num_cachelines_to_roll &&
- (l_target_address < (l_drawer_base_address_nm0 + i_payload_size + l_exception_vector_size)))
+ while (l_num_cachelines_to_roll && (l_target_address < l_end_address))
{
- if ((l_cacheline_num == 0) && (l_exception_instruction != 0))
+ // set content to move into next cacheline based on current
+ // position in load sequence
+ if (l_load_exception_vector && (l_cacheline_num == 0))
{
- //This is for the first cacheline of data that has the branch, pnor_size, and pnor_boot_side in it
- //The rest of the exception vector is what was in SBE_HBBL_EXCEPTION_INSTRUCT replicated multiple times (until the end of 12KB of exception vector data)
- for (uint32_t i = 0; i < FABRIC_CACHELINE_SIZE; i++)
- {
- //At address X (0-3) put whatever is in l_branch_to_12
- if (i < 4)
- {
- l_data_to_pass_to_pba_array[i] = (l_branch_to_12 >> (24 - 8 * i )) & 0xFF;
- }
- //At address X + 0x4 (4-7) put the HBBL_STRUCT_VERSION
- else if (i < 8)
- {
- l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.version >> (24 - 8 * ((i - 4) % 4))) & 0xFF;
- }
- //At address X + 0x8 (8) put the SBE_BOOT_SIDE
- else if (i == 8)
- {
- l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.sbeBootSide;
- }
- //At address X + 0x9 (9) put the PNOR_BOOT_SIDE
- else if (i == 9)
- {
- l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorBootSide;
- }
- //At address X + 0xA (10-11) pu the PNOR_SIZE
- else if (i == 10)
- {
- l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorSizeMB >> 8 & 0xFF;
- }
- else if (i == 11)
- {
- l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.pnorSizeMB & 0xFF;
- }
- //At address X + 0xC (12-19) put the total load size
- else if (i < 20)
- {
- l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.blLoadSize >> (56 - 8 * ((i - 12) % 8))) & 0xFF;
- }
- //At address X + 0x14 (20) put the secure access byte
- else if (i == 20)
- {
- l_data_to_pass_to_pba_array[i] = l_bootloader_config_data.secureSettings.data8;
- }
- //At address X + 0x15 (21-27) put a zero
- else if (i < 28)
- {
- l_data_to_pass_to_pba_array[i] = 0;
- }
- //At address X + 0x1B (28-35) put the XSCOM BAR
- else if (i < 36)
- {
- l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.xscomBAR >> (56 - 8 * ((i - 28) % 8))) & 0xFF;
- }
- //At address X + 0x1B (36-43) put the LPC BAR
- else if (i < 44)
- {
- l_data_to_pass_to_pba_array[i] = (l_bootloader_config_data.lpcBAR >> (56 - 8 * ((i - 36) % 8))) & 0xFF;
- }
- //Fill the rest with the exception vector instruction
- else
- {
- l_data_to_pass_to_pba_array[i] = (l_exception_instruction >> (24 - 8 * (i % 4))) & 0xFF;
- }
- }
+ // write bootloader configuration data in first cacheline
+ FAPI_TRY(get_exception_vector_data(l_data),
+ "Error from get_exception_vector_data");
+ FAPI_TRY(get_bootloader_config_data(i_master_chip_target,
+ l_load_size,
+ l_data),
+ "Error from get_bootloader_config_data");
}
- else if ((l_cacheline_num == 1) && (l_exception_instruction != 0))
+ // write payload image content past end of optional exception vector
+ else if (!l_load_exception_vector ||
+ (l_cacheline_num >= EXCEPTION_VECTOR_NUM_CACHELINES))
{
- //This is for the other 95 cachelines that we are sending
- for (uint32_t i = 0; i < FABRIC_CACHELINE_SIZE; i++)
+ uint64_t l_payload_cacheline_index = l_cacheline_num;
+
+ if (l_load_exception_vector)
{
- l_data_to_pass_to_pba_array[i] = (l_exception_instruction >> (24 - 8 * (i % 4))) & 0xFF;
+ l_payload_cacheline_index -= EXCEPTION_VECTOR_NUM_CACHELINES;
}
- }
- else if ((l_cacheline_num >= EXCEPTION_VECTOR_NUM_CACHELINES) || (l_exception_instruction == 0))
- {
- //This is for the data after the exception vector
- for (uint32_t i = 0; i < FABRIC_CACHELINE_SIZE; i++)
+
+ l_payload_cacheline_index *= FABRIC_CACHELINE_SIZE;
+
+ for (uint8_t ii = 0; ii < FABRIC_CACHELINE_SIZE; ii++)
{
- l_data_to_pass_to_pba_array[i] = i_payload_data[((l_cacheline_num - (l_exception_vector_size / FABRIC_CACHELINE_SIZE)) *
- FABRIC_CACHELINE_SIZE)
- + i];
+ l_data[ii] = i_payload_data[l_payload_cacheline_index + ii];
}
}
FAPI_TRY(p9_pba_access(i_master_chip_target,
l_target_address,
PBA_HWP_WRITE_OP,
- l_myPbaFlag.setFlag(),
- l_firstAccess,
+ l_pba_flags.setFlag(),
+ l_first_access,
(l_num_cachelines_to_roll == 1) ||
((l_target_address + FABRIC_CACHELINE_SIZE) >=
- (l_drawer_base_address_nm0 + i_payload_size + l_exception_vector_size)),
- l_data_to_pass_to_pba_array), "Error from p9_pba_access");
- l_firstAccess = false;
+ l_end_address),
+ l_data),
+ "Error from p9_pba_access");
+
+ // set data to fill pattern for remainder of exception vector
+ if (l_load_exception_vector && (l_cacheline_num == 0))
+ {
+ FAPI_TRY(get_exception_vector_data(l_data),
+ "Error from get_exception_vector_data");
+ }
+
+ // reset flag
+ l_first_access = false;
// decrement count of cachelines remaining in current stream
l_num_cachelines_to_roll--;
-
// stride address/payload data pointer offset to next cacheline
l_target_address += FABRIC_CACHELINE_SIZE;
l_cacheline_num++;
}
}
- {
-
- fapi2::ATTR_FUSED_CORE_MODE_Type l_attr_fused_mode;
- FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FUSED_CORE_MODE,
- FAPI_SYSTEM,
- l_attr_fused_mode));
- l_dataBuf.flush<0>();
-
- //Override PM_EXIT on master core bit 4 is for core 0 bit 5 is for core 1
- if ( (l_master_core % 2 == 0) ||
- (l_attr_fused_mode == fapi2::ENUM_ATTR_FUSED_CORE_MODE_CORE_FUSED))
- {
- l_dataBuf.setBit<EQ_CME_SCOM_SICR_PM_EXIT_C0>();
- }
-
- if ( (l_master_core % 2 != 0) ||
- (l_attr_fused_mode == fapi2::ENUM_ATTR_FUSED_CORE_MODE_CORE_FUSED))
- {
- l_dataBuf.setBit<EQ_CME_SCOM_SICR_PM_EXIT_C1>();
- }
-
- FAPI_TRY(fapi2::putScom(i_master_ex_target, EX_0_CME_SCOM_SICR_SCOM2,
- l_dataBuf) )
-
- for (auto& coreTgt : i_master_ex_target.getChildren<fapi2::TARGET_TYPE_CORE>())
- {
-
- // In non-fused mode, set HRMOR for master core only
- if ((l_attr_fused_mode != fapi2::ENUM_ATTR_FUSED_CORE_MODE_CORE_FUSED) &&
- (( coreTgt != l_coreTarget)))
- {
- continue;
- }
-
- //instantiate the basic RamCore class
- RamCore ram2(coreTgt, 2);
- RamCore ram3(coreTgt, 3);
- //Set the HRMOR (core) and PSSCR (threads 2,3). The PSSCR must be
- //set on threads 2,3 as in fused mode Hostboot will never execute
- //on them, but CME checks bits in them to perform STOP11 request
- //in istep 16
-
- //Set ram_thread_active for t0
- l_dataBuf.flush<0>().setBit<C_0_THREAD_INFO_RAM_THREAD_ACTIVE_T2>();
- l_dataBuf.setBit<C_0_THREAD_INFO_RAM_THREAD_ACTIVE_T3>();
- FAPI_TRY(fapi2::putScom(coreTgt, C_0_THREAD_INFO, l_dataBuf),
- "Error setting thread active for t2,3");
-
- if( coreTgt == l_coreTarget )
- {
- l_dataBuf.flush<0>().insertFromRight<0, 64>(l_drawer_base_address_nm0);
- }
- else
- {
- l_dataBuf.flush<0>().insertFromRight<0, 64>(
- l_drawer_base_address_nm0 - l_bootloader_offset);
- }
-
- //call RamCore put_reg method -- can use thread 2 for HRMOR as applies to
- //full core
- FAPI_TRY(ram2.put_reg(REG_SPR, 313, &l_dataBuf), "Error ramming HRMOR");
- l_dataBuf.flush<0>().insertFromRight<0, 64>(HOSTBOOT_PSSCR_VALUE);
- FAPI_TRY(ram2.put_reg(REG_SPR, 855, &l_dataBuf), "Error ramming PSSCR thread 2");
- FAPI_TRY(ram3.put_reg(REG_SPR, 855, &l_dataBuf), "Error ramming PSSCR thread 3");
- }
- }
+ // RAM SPRs prior to instruction start
+ FAPI_TRY(ram_sprs(i_master_chip_target,
+ i_master_ex_target,
+ l_load_base_address),
+ "Error from ram_sprs");
fapi_try_exit:
FAPI_DBG("End");
return fapi2::current_err;
}
-
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H
index fced2b1e..ae24f617 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER sbe Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015,2016 */
+/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -22,71 +22,57 @@
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
-//------------------------------------------------------------------------------------
-//
+
+///
/// @file p9_sbe_load_bootloader.H
-/// @brief Shift HB bootloader payload from SEEPROM to L3 cache of master core via PBA
-//
-// *HWP HWP Owner: Christina Graves clgraves@us.ibm.com
-// *HWP HWP Writer: Murey A Luna Torres malunato@us.ibm.com, Joseph McGill jmcgill@us.ibm.com
+/// @brief Shift HB bootloader payload from SEEPROM to L3 cache of master core
+/// via PBA
+///
+
+// *HWP HWP Owner: Joseph McGill jmcgill@us.ibm.com
// *HWP FW Owner: Thi Tran thi@us.ibm.com
// *HWP Team: Nest
-// *HWP Level: 2
+// *HWP Level: 3
// *HWP Consumed by: SBE
-//-----------------------------------------------------------------------------------
-// *! ADDITIONAL COMMENTS:
-// *!
-// *! This hardware procedure is used to load a bootloader image from seeprom into
-// *! L3 of master core via PBA unit.
-// *!
-// *! Successful operation assumes that:
-// *! PBA communication is available
-// *!
-// *! High-level procedure flow:
-// *!
-//------------------------------------------------------------------------------------
#ifndef _SBE_BOOTLOADER_H_
#define _SBE_BOOTLOADER_H_
-//-----------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
// Includes
-//-----------------------------------------------------------------------------------
-
+//------------------------------------------------------------------------------
#include <fapi2.H>
-#include <p9_sbe_hb_structures.H>
-//-----------------------------------------------------------------------------------
-// Structure definitions
-//-----------------------------------------------------------------------------------
-//function pointer typedef definition for HWP call support
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+// function pointer typedef definition for HWP call support
typedef fapi2::ReturnCode(*p9_sbe_load_bootloader_FP_t) (
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&,
const fapi2::Target<fapi2::TARGET_TYPE_EX>&,
const uint64_t,
uint8_t*);
-//-----------------------------------------------------------------------------------
-// Constant definitions
-//-----------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+// Function prototype
+//------------------------------------------------------------------------------
+//
extern "C" {
- //-----------------------------------------------------------------------------------
- // Function prototype
- //-----------------------------------------------------------------------------------
- //
-/// @brief Shift HB bootloader payload from SEEPROM to L3 cache of master core via PBA
+///
+/// @brief Shift HB bootloader payload from SEEPROM to L3 cache of master core
+/// via PBA
/// @param[in] i_master_chip_target Reference to master processor chip target
-/// @param[in] i_master_ex_target Reference to master ex unit target
-/// @param[in] i_payload_size Size of image payload load to load, in B
+/// @param[in] i_master_ex_target Reference to master EX unit target
+/// @param[in] i_payload_size Size of image payload data, in B
/// @param[in] i_payload_data Pointer to image payload data
///
/// @return FAPI_RC_SUCCESS if success, else error code
///
fapi2::ReturnCode p9_sbe_load_bootloader(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_master_chip_target,
- const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_master_eq_target,
+ const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_master_ex_target,
const uint64_t i_payload_size,
uint8_t* i_payload_data);
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