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| author | Prem Shanker Jha <premjha2@in.ibm.com> | 2016-06-08 05:48:31 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2017-07-17 01:40:55 -0400 |
| commit | e4859a588965dd88cb370c84741befc1552fa0a7 (patch) | |
| tree | cd9f379dd22c5aa6a43d1a5950ad6a6475345388 /src/import/chips/p9/procedures/hwp | |
| parent | b0577f88e55da39f4e83757a861aa0bbf70bbe5d (diff) | |
| download | talos-sbe-e4859a588965dd88cb370c84741befc1552fa0a7.tar.gz talos-sbe-e4859a588965dd88cb370c84741befc1552fa0a7.zip | |
PM: Added support for PGPE Boot/PGPE integration
- support for P-State parameter block
- implements a compact image layout of PGPE similar to CME/SGPE.
- adds PGPE boot progress code as a field in PPMR header.
- implements PGPE boot loader and PGPE boot copier.
- incorporates ability to generate PPMR header in the build flow.
- change logic for calculating CME's first block copy length.
- Turned on generated tables in PGPE Hcode
- Fixed up pointers to generated tables
- add ATTR_PGPE_HCODE_FUNCTION_ENABLE attribute to control PGPE ops
- fix p9_pstate_parameter_build bug with AVS timing attributes
- Make OCC Pstate Parameter block a fixed offset (128KB) in PPMR
- Make Pstate Table from PGPE a fixed offset (144KB) in PPMR to ease debug
- Fix Endianes issues in OCC PPB and input slope calcs
- Added PGPE Hcode Length to PGPE header so that GPPB SRAM location is known.
- Build flag for OCc Immediate IPC response
- Build flag to no use temp boot settings
- Expanding tracing for debug
- Added default values for PBAX attributes as placeholders for MRW in firmware
- Added WOF VFRT structure definions to headers; movement into HOMER NOT
yet supported
- Addressed review comments and rebased
- Rebased with ATTR_PGPE_HCODE_FUNCTION_ENABLE in separate commit for Cronus
Change-Id: I4befc542a76acf2572b4a688488b03c57e19e588
Original-Change-Id: I4752debbc7fb3275d4e79804333654511de427ff
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26115
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43183
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h b/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h index a7776e1f..cbf80b19 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h @@ -134,6 +134,37 @@ typedef union occ_scratch2 } fields; } occ_scratch2_t; +typedef union pgpe_flags +{ + uint16_t value; + struct + { +#ifdef _BIG_ENDIAN + uint16_t resclk_enable : 1; + uint16_t ivrm_enable : 1; + uint16_t vdm_enable : 1; + uint16_t wof_enable : 1; + uint16_t dpll_dynamic_fmax_enable : 1; + uint16_t dpll_dynamic_fmin_enable : 1; + uint16_t dpll_droop_protect_enable : 1; + uint16_t reserved7 : 1; + uint16_t occ_ipc_immed_response : 1; + uint16_t reserved_9_15 : 7; +#else + uint16_t reserved_9_15 : 7; + uint16_t occ_ipc_immed_response : 1; + uint16_t reserved7 : 1; + uint16_t dpll_droop_protect_enable : 1; + uint16_t dpll_dynamic_fmin_enable : 1; + uint16_t dpll_dynamic_fmax_enable : 1; + uint16_t wof_enable : 1; + uint16_t vdm_enable : 1; + uint16_t ivrm_enable : 1; + uint16_t resclk_enable : 1; +#endif + } fields; +} pgpe_flags_t; + typedef union cme_flags { uint32_t value; |
